[AArch64][SVE] Remove assertion/range check for i16 values during immediate selection

[mnadeem]

Summary

This assertion fails when an i16 constant is promoted to i32.
Example: https://godbolt.org/z/rxo649jEo

The value i16 -32768 is within the range of i16 but is promoted to
positive i32 32768 by an earlier call to DAG.getConstant().

Another option would be to modify the assert to:

assert((ImmVal >= -32768) && (ImmVal <= 65535));

not sure if this is any better.

[mnadeem]

Adding reviewers from: https://reviews.llvm.org/D101833

[mnadeem]

Added a test.

[efriedma]

LGTM with one minor change.

llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

3154–3155

I think the way lowering currently works, we currently don't have any guarantee at all about what the high bits of ImmVal contain; this follows from the definition of SPLAT_VECTOR. So probably we should be explicitly masking off the high bits. I doubt that has any practical effect here, though; just deleting the assertion is probably good enough.

llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll

806

Please stick this next to the other tests in llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-imm.ll .

[mnadeem]

llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll

806

Looks like tests in that file explicitly call the sve intrinsics while this test does not.
There are similar min/max tests above so I think it will be okay here, or should I move it?

[efriedma]

llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll

806

Oh, hmm....

I guess it's fine here, then.

llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

case MVT::i8:
       Imm = CurDAG->getTargetConstant(ImmVal & 0xFF, DL, MVT::i32);
       return true;
     case MVT::i16:
       // i16 values get sign-extended to 32-bits during lowering.
       if ((ImmVal & 0xFF) == ImmVal) {
         Shift = CurDAG->getTargetConstant(0, DL, MVT::i32);
         Imm = CurDAG->getTargetConstant(ImmVal, DL, MVT::i32);
         return true;
       } else if ((ImmVal & 0xFF) == 0) {
-        assert((ImmVal >= -32768) && (ImmVal <= 32512));
         Shift = CurDAG->getTargetConstant(8, DL, MVT::i32);
         Imm = CurDAG->getTargetConstant((ImmVal >> 8) & 0xFF, DL, MVT::i32);
         return true;
       }
       break;
     case MVT::i32:
     case MVT::i64:
       // Range of immediate won't trigger signedness problems for 32/64b.
       if ((ImmVal & 0xFF) == ImmVal) {

llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll

 ; CHECK-NEXT:    ptrue p0.s
 ; CHECK-NEXT:    udiv z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT:    ret
 entry:
   %div = udiv <vscale x 4 x i32> %a, shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> undef, i32 3, i32 0), <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer)
   ret <vscale x 4 x i32> %div
 }
 
+;
+; UQSUB
+;
+define <vscale x 8 x i16> @uqsub(<vscale x 8 x i16> %a) {
+; CHECK-LABEL: uqsub:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    uqsub z0.h, z0.h, #32768 // =0x8000
+; CHECK-NEXT:    ret
+  %cmp = icmp slt <vscale x 8 x i16> %a, shufflevector (<vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 0, i32 0), <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer)
+  %sub = xor <vscale x 8 x i16> %a, shufflevector (<vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 -32768, i32 0), <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer)
+  %sel = select <vscale x 8 x i1> %cmp, <vscale x 8 x i16> %sub, <vscale x 8 x i16> shufflevector (<vscale x 8 x i16> insertelement (<vscale x 8 x i16> undef, i16 0, i32 0), <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer)
+  ret <vscale x 8 x i16> %sel
+}
+
 attributes #0 = { minsize }