[AArch64] Prefer fmov over orr v.16b when copying f32/f64

[dmgreen]

Summary

This change the lowering of f32 and f64 COPY from a 128bit vector ORR to a fmov of the appropriate type. At least on some CPU's with 64bit NEON data paths this is expected to be faster, and shouldn't be slower on any CPU that treats fmov as a register rename.

[dmgreen]

Rebase and update the formatting.

[SjoerdMeijer]

Looks reasonable to me. Perhaps wait a day if others want to comment.

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

 
 // Return true if this instruction simply renames a general register without
 // modifying bits.
 bool AArch64InstrInfo::isFPRCopy(const MachineInstr &MI) {
   switch (MI.getOpcode()) {
   default:
     break;
   case TargetOpcode::COPY: {
-    // FPR64 copies will by lowered to ORR.16b
     Register DstReg = MI.getOperand(0).getReg();
-    return (AArch64::FPR64RegClass.contains(DstReg) ||
-            AArch64::FPR128RegClass.contains(DstReg));
+    return AArch64::FPR128RegClass.contains(DstReg);
   }
   case AArch64::ORRv16i8:
     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
       assert(MI.getDesc().getNumOperands() == 3 && MI.getOperand(0).isReg() &&
              "invalid ORRv16i8 operands");
       return true;
     }
     break;
if (Subtarget.hasNEON()) {
           .addReg(AArch64::SP)
           .addImm(16);
     }
     return;
   }
 
   if (AArch64::FPR64RegClass.contains(DestReg) &&
       AArch64::FPR64RegClass.contains(SrcReg)) {
-    if (Subtarget.hasNEON()) {
-      DestReg = RI.getMatchingSuperReg(DestReg, AArch64::dsub,
-                                       &AArch64::FPR128RegClass);
-      SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::dsub,
-                                      &AArch64::FPR128RegClass);
-      BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
-          .addReg(SrcReg)
-          .addReg(SrcReg, getKillRegState(KillSrc));
-    } else {
-      BuildMI(MBB, I, DL, get(AArch64::FMOVDr), DestReg)
-          .addReg(SrcReg, getKillRegState(KillSrc));
-    }
     return;
   }
 
   if (AArch64::FPR32RegClass.contains(DestReg) &&
       AArch64::FPR32RegClass.contains(SrcReg)) {
-    if (Subtarget.hasNEON()) {
-      DestReg = RI.getMatchingSuperReg(DestReg, AArch64::ssub,
-                                       &AArch64::FPR128RegClass);
-      SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::ssub,
-                                      &AArch64::FPR128RegClass);
-      BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
-          .addReg(SrcReg)
-          .addReg(SrcReg, getKillRegState(KillSrc));
-    } else {
-      BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
-          .addReg(SrcReg, getKillRegState(KillSrc));
-    }
     return;
   }
 
   if (AArch64::FPR16RegClass.contains(DestReg) &&
       AArch64::FPR16RegClass.contains(SrcReg)) {
-    if (Subtarget.hasNEON()) {
-      DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub,
-                                       &AArch64::FPR128RegClass);
-      SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::hsub,
-                                      &AArch64::FPR128RegClass);
-      BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
-          .addReg(SrcReg)
-          .addReg(SrcReg, getKillRegState(KillSrc));
-    } else {
-      DestReg = RI.getMatchingSuperReg(DestReg, AArch64::hsub,
-                                       &AArch64::FPR32RegClass);
-      SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::hsub,
-                                      &AArch64::FPR32RegClass);
-      BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
-          .addReg(SrcReg, getKillRegState(KillSrc));
-    }
+    DestReg =
+        RI.getMatchingSuperReg(DestReg, AArch64::hsub, &AArch64::FPR32RegClass);
+    SrcReg =
+        RI.getMatchingSuperReg(SrcReg, AArch64::hsub, &AArch64::FPR32RegClass);
     return;
   }
 
   if (AArch64::FPR8RegClass.contains(DestReg) &&
       AArch64::FPR8RegClass.contains(SrcReg)) {
-    if (Subtarget.hasNEON()) {
-      DestReg = RI.getMatchingSuperReg(DestReg, AArch64::bsub,
-                                       &AArch64::FPR128RegClass);
-      SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::bsub,
-                                      &AArch64::FPR128RegClass);
-      BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
-          .addReg(SrcReg)
-          .addReg(SrcReg, getKillRegState(KillSrc));
-    } else {
-      DestReg = RI.getMatchingSuperReg(DestReg, AArch64::bsub,
-                                       &AArch64::FPR32RegClass);
-      SrcReg = RI.getMatchingSuperReg(SrcReg, AArch64::bsub,
-                                      &AArch64::FPR32RegClass);
-      BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
-          .addReg(SrcReg, getKillRegState(KillSrc));
-    }
+    DestReg =
+        RI.getMatchingSuperReg(DestReg, AArch64::bsub, &AArch64::FPR32RegClass);
+    SrcReg =
+        RI.getMatchingSuperReg(SrcReg, AArch64::bsub, &AArch64::FPR32RegClass);
     return;
   }
 
   // Copies between GPR64 and FPR64.
   if (AArch64::FPR64RegClass.contains(DestReg) &&
       AArch64::GPR64RegClass.contains(SrcReg)) {
     BuildMI(MBB, I, DL, get(AArch64::FMOVXDr), DestReg)
         .addReg(SrcReg, getKillRegState(KillSrc));

llvm/test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll

-; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -aarch64-neon-syntax=apple -aarch64-enable-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=true | FileCheck %s -check-prefix=CHECK
 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -aarch64-neon-syntax=apple -aarch64-enable-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=false | FileCheck %s -check-prefix=CHECK
-; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -aarch64-neon-syntax=generic -aarch64-enable-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=true | FileCheck %s -check-prefix=GENERIC
 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-eabi -aarch64-neon-syntax=generic -aarch64-enable-simd-scalar=true -asm-verbose=false -disable-adv-copy-opt=false | FileCheck %s -check-prefix=GENERIC
 
 define <2 x i64> @bar(<2 x i64> %a, <2 x i64> %b) nounwind readnone {
 ; CHECK-LABEL: bar:
 ; CHECK: add.2d v[[REG:[0-9]+]], v0, v1
 ; CHECK: add  d[[REG3:[0-9]+]], d[[REG]], d1
 ; CHECK: sub  d[[REG2:[0-9]+]], d[[REG]], d1
 ; CHECK-NOT: fmov

llvm/test/CodeGen/AArch64/arm64-aapcs.ll

 ; CHECK-LABEL: test_vreg_stack:
 ; CHECK: ldr {{q[0-9]+}}, [sp]
   ret <2 x double> %varg_stack;
 }
 
 ; Check that f16 can be passed and returned (ACLE 2.0 extension)
 define half @test_half(float, half %arg) {
 ; CHECK-LABEL: test_half:
-; CHECK: mov v0.16b, v1.16b
+; CHECK: fmov s0, s1
   ret half %arg;
 }
 
 ; Check that f16 constants are materialized correctly
 define half @test_half_const() {
 ; CHECK-LABEL: test_half_const:
 ; CHECK: ldr h0, [x{{[0-9]+}}, :lo12:{{.*}}]
   ret half 0xH4248
 }
 
 ; Check that v4f16 can be passed and returned in registers
 define dso_local <4 x half> @test_v4_half_register(float, <4 x half> %arg) {
 ; CHECK-LABEL: test_v4_half_register:
-; CHECK: mov v0.16b, v1.16b
+; CHECK: fmov d0, d1
   ret <4 x half> %arg;
 }
 
 ; Check that v8f16 can be passed and returned in registers
 define dso_local <8 x half> @test_v8_half_register(float, <8 x half> %arg) {
 ; CHECK-LABEL: test_v8_half_register:
 ; CHECK: mov v0.16b, v1.16b
   ret <8 x half> %arg;

llvm/test/CodeGen/AArch64/arm64-neon-copy.ll

; CHECK-NEXT:    ret
   ret <2 x double> %tmp4
 }
 
 define <8 x i8> @ins16b8(<16 x i8> %tmp1, <8 x i8> %tmp2) {
 ; CHECK-LABEL: ins16b8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
 ; CHECK-NEXT:    mov v1.b[7], v0.b[2]
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
   %tmp3 = extractelement <16 x i8> %tmp1, i32 2
   %tmp4 = insertelement <8 x i8> %tmp2, i8 %tmp3, i32 7
   ret <8 x i8> %tmp4
 }
 
 define <4 x i16> @ins8h4(<8 x i16> %tmp1, <4 x i16> %tmp2) {
 ; CHECK-LABEL: ins8h4:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
 ; CHECK-NEXT:    mov v1.h[3], v0.h[2]
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
   %tmp3 = extractelement <8 x i16> %tmp1, i32 2
   %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 3
   ret <4 x i16> %tmp4
 }
 
 define <2 x i32> @ins4s2(<4 x i32> %tmp1, <2 x i32> %tmp2) {
 ; CHECK-LABEL: ins4s2:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
 ; CHECK-NEXT:    mov v1.s[1], v0.s[2]
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
   %tmp3 = extractelement <4 x i32> %tmp1, i32 2
   %tmp4 = insertelement <2 x i32> %tmp2, i32 %tmp3, i32 1
   ret <2 x i32> %tmp4
 }
 
 define <1 x i64> @ins2d1(<2 x i64> %tmp1, <1 x i64> %tmp2) {
 ; CHECK-LABEL: ins2d1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
 ; CHECK-NEXT:    mov v1.d[0], v0.d[0]
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
   %tmp3 = extractelement <2 x i64> %tmp1, i32 0
   %tmp4 = insertelement <1 x i64> %tmp2, i64 %tmp3, i32 0
   ret <1 x i64> %tmp4
 }
 
 define <2 x float> @ins4f2(<4 x float> %tmp1, <2 x float> %tmp2) {
 ; CHECK-LABEL: ins4f2:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
 ; CHECK-NEXT:    mov v1.s[1], v0.s[2]
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
   %tmp3 = extractelement <4 x float> %tmp1, i32 2
   %tmp4 = insertelement <2 x float> %tmp2, float %tmp3, i32 1
   ret <2 x float> %tmp4
 }
 
 define <1 x double> @ins2f1(<2 x double> %tmp1, <1 x double> %tmp2) {
 ; CHECK-LABEL: ins2f1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    dup v0.2d, v0.d[1]
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
 ; CHECK-NEXT:    ret
   %tmp3 = extractelement <2 x double> %tmp1, i32 1
   %tmp4 = insertelement <1 x double> %tmp2, double %tmp3, i32 0
   ret <1 x double> %tmp4
 }
 
 define <8 x i8> @ins8b8(<8 x i8> %tmp1, <8 x i8> %tmp2) {
 ; CHECK-LABEL: ins8b8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    mov v1.b[4], v0.b[2]
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
   %tmp3 = extractelement <8 x i8> %tmp1, i32 2
   %tmp4 = insertelement <8 x i8> %tmp2, i8 %tmp3, i32 4
   ret <8 x i8> %tmp4
 }
 
 define <4 x i16> @ins4h4(<4 x i16> %tmp1, <4 x i16> %tmp2) {
 ; CHECK-LABEL: ins4h4:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    mov v1.h[3], v0.h[2]
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
   %tmp3 = extractelement <4 x i16> %tmp1, i32 2
   %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 3
   ret <4 x i16> %tmp4
 }
 
 define <2 x i32> @ins2s2(<2 x i32> %tmp1, <2 x i32> %tmp2) {
 ; CHECK-LABEL: ins2s2:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    mov v1.s[1], v0.s[0]
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
   %tmp3 = extractelement <2 x i32> %tmp1, i32 0
   %tmp4 = insertelement <2 x i32> %tmp2, i32 %tmp3, i32 1
   ret <2 x i32> %tmp4
 }
 
 define <1 x i64> @ins1d1(<1 x i64> %tmp1, <1 x i64> %tmp2) {
 ; CHECK-LABEL: ins1d1:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    mov v1.d[0], v0.d[0]
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
   %tmp3 = extractelement <1 x i64> %tmp1, i32 0
   %tmp4 = insertelement <1 x i64> %tmp2, i64 %tmp3, i32 0
   ret <1 x i64> %tmp4
 }
 
 define <2 x float> @ins2f2(<2 x float> %tmp1, <2 x float> %tmp2) {
 ; CHECK-LABEL: ins2f2:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    mov v1.s[1], v0.s[0]
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
   %tmp3 = extractelement <2 x float> %tmp1, i32 0
   %tmp4 = insertelement <2 x float> %tmp2, float %tmp3, i32 1
   ret <2 x float> %tmp4
 }
 
 define <1 x double> @ins1df1(<1 x double> %tmp1, <1 x double> %tmp2) {
 ; CHECK-LABEL: ins1df1:

 }
 
 define <8 x i8> @test_vcopy_lane_swap_s8(<8 x i8> %v1, <8 x i8> %v2) {
 ; CHECK-LABEL: test_vcopy_lane_swap_s8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    mov v1.b[7], v0.b[0]
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
   %vset_lane = shufflevector <8 x i8> %v1, <8 x i8> %v2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 0>
   ret <8 x i8> %vset_lane
 }
 
 define <16 x i8> @test_vcopyq_laneq_swap_s8(<16 x i8> %v1, <16 x i8> %v2) {
 ; CHECK-LABEL: test_vcopyq_laneq_swap_s8:
 ; CHECK:       // %bb.0:

 ; CHECK-NEXT:    str q0, [sp, #-16]!
 ; CHECK-NEXT:    and x8, x0, #0x7
 ; CHECK-NEXT:    mov x9, sp
 ; CHECK-NEXT:    bfi x9, x8, #1, #3
 ; CHECK-NEXT:    ldr h1, [x9]
 ; CHECK-NEXT:    mov v1.h[1], v0.h[1]
 ; CHECK-NEXT:    mov v1.h[2], v0.h[2]
 ; CHECK-NEXT:    mov v1.h[3], v0.h[3]
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    add sp, sp, #16 // =16
 ; CHECK-NEXT:    ret
   %tmp = extractelement <8 x i16> %x, i32 %idx
   %tmp2 = insertelement <4 x i16> undef, i16 %tmp, i32 0
   %tmp3 = extractelement <8 x i16> %x, i32 1
   %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 1
   %tmp5 = extractelement <8 x i16> %x, i32 2
   %tmp6 = insertelement <4 x i16> %tmp4, i16 %tmp5, i32 2

 ; CHECK-NEXT:    and x8, x0, #0x3
 ; CHECK-NEXT:    add x9, sp, #8 // =8
 ; CHECK-NEXT:    bfi x9, x8, #1, #2
 ; CHECK-NEXT:    str h0, [x9]
 ; CHECK-NEXT:    ldr d1, [sp, #8]
 ; CHECK-NEXT:    mov v1.h[1], v0.h[1]
 ; CHECK-NEXT:    mov v1.h[2], v0.h[2]
 ; CHECK-NEXT:    mov v1.h[3], v0.h[3]
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    add sp, sp, #16 // =16
 ; CHECK-NEXT:    ret
   %tmp = extractelement <8 x i16> %x, i32 0
   %tmp2 = insertelement <4 x i16> undef, i16 %tmp, i32 %idx
   %tmp3 = extractelement <8 x i16> %x, i32 1
   %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 1
   %tmp5 = extractelement <8 x i16> %x, i32 2
   %tmp6 = insertelement <4 x i16> %tmp4, i16 %tmp5, i32 2

llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll

 ; GENERIC-LABEL: test_vcvt_f16_f32:
 ; GENERIC:       // %bb.0:
 ; GENERIC-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; GENERIC-NEXT:    fcvt h0, s0
 ; GENERIC-NEXT:    ret
 ;
 ; FAST-LABEL: test_vcvt_f16_f32:
 ; FAST:       // %bb.0:
-; FAST-NEXT:    mov.16b v1, v0
+; FAST-NEXT:    fmov d1, d0
 ; FAST-NEXT:    // implicit-def: $q0
-; FAST-NEXT:    mov.16b v0, v1
+; FAST-NEXT:    fmov d0, d1
 ; FAST-NEXT:    // kill: def $s0 killed $s0 killed $q0
 ; FAST-NEXT:    fcvt h0, s0
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: test_vcvt_f16_f32:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fmov x8, d0
 ; GISEL-NEXT:    fmov s0, w8

 ; GENERIC-LABEL: test_vcvt_high_f32_f64:
 ; GENERIC:       // %bb.0:
 ; GENERIC-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; GENERIC-NEXT:    fcvtn2 v0.4s, v1.2d
 ; GENERIC-NEXT:    ret
 ;
 ; FAST-LABEL: test_vcvt_high_f32_f64:
 ; FAST:       // %bb.0:
-; FAST-NEXT:    mov.16b v2, v0
+; FAST-NEXT:    fmov d2, d0
 ; FAST-NEXT:    // implicit-def: $q0
-; FAST-NEXT:    mov.16b v0, v2
+; FAST-NEXT:    fmov d0, d2
 ; FAST-NEXT:    fcvtn2 v0.4s, v1.2d
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: test_vcvt_high_f32_f64:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; GISEL-NEXT:    fcvtn2 v0.4s, v1.2d
 ; GISEL-NEXT:    ret

 ; GENERIC-LABEL: test_vcvtx_high_f32_f64:
 ; GENERIC:       // %bb.0:
 ; GENERIC-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; GENERIC-NEXT:    fcvtxn2 v0.4s, v1.2d
 ; GENERIC-NEXT:    ret
 ;
 ; FAST-LABEL: test_vcvtx_high_f32_f64:
 ; FAST:       // %bb.0:
-; FAST-NEXT:    mov.16b v2, v0
+; FAST-NEXT:    fmov d2, d0
 ; FAST-NEXT:    // implicit-def: $q0
-; FAST-NEXT:    mov.16b v0, v2
+; FAST-NEXT:    fmov d0, d2
 ; FAST-NEXT:    fcvtxn2 v0.4s, v1.2d
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: test_vcvtx_high_f32_f64:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; GISEL-NEXT:    fcvtxn2 v0.4s, v1.2d
 ; GISEL-NEXT:    ret

 ; GENERIC-NEXT:    fmov w0, s0
 ; GENERIC-NEXT:    ret
 ;
 ; FAST-LABEL: to_half:
 ; FAST:       // %bb.0:
 ; FAST-NEXT:    fcvt h1, s0
 ; FAST-NEXT:    // implicit-def: $w0
 ; FAST-NEXT:    fmov s0, w0
-; FAST-NEXT:    mov.16b v0, v1
+; FAST-NEXT:    fmov s0, s1
 ; FAST-NEXT:    fmov w0, s0
 ; FAST-NEXT:    // kill: def $w1 killed $w0
 ; FAST-NEXT:    ret
 ;
 ; GISEL-LABEL: to_half:
 ; GISEL:       // %bb.0:
 ; GISEL-NEXT:    fcvt h0, s0
 ; GISEL-NEXT:    fmov w0, s0

llvm/test/CodeGen/AArch64/arm64-vector-insertion.ll

 }
 
 define <2 x float> @test_insert_v2f32_undef_zero_vector(float %a) {
 ; CHECK-LABEL: test_insert_v2f32_undef_zero_vector:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    movi d1, #0000000000000000
 ; CHECK-NEXT:    // kill: def $s0 killed $s0 def $q0
 ; CHECK-NEXT:    mov.s v1[1], v0[0]
-; CHECK-NEXT:    mov.16b v0, v1
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
   %v.0 = insertelement <2 x float> <float 0.000000e+00, float undef>, float %a, i32 1
   ret <2 x float> %v.0
 }
 
 define <4 x float> @test_insert_3_f32_undef_zero_vector(float %a) {
 ; CHECK-LABEL: test_insert_3_f32_undef_zero_vector:
 ; CHECK:       // %bb.0:

llvm/test/CodeGen/AArch64/bf16-vector-bitcast.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+bf16 | FileCheck %s
 
 define <4 x i16> @v4bf16_to_v4i16(float, <4 x bfloat> %a) nounwind {
 ; CHECK-LABEL: v4bf16_to_v4i16:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
 entry:
   %1 = bitcast <4 x bfloat> %a to <4 x i16>
   ret <4 x i16> %1
 }
 
 define <2 x i32> @v4bf16_to_v2i32(float, <4 x bfloat> %a) nounwind {
 ; CHECK-LABEL: v4bf16_to_v2i32:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
 entry:
   %1 = bitcast <4 x bfloat> %a to <2 x i32>
   ret <2 x i32> %1
 }
 
 define <1 x i64> @v4bf16_to_v1i64(float, <4 x bfloat> %a) nounwind {
 ; CHECK-LABEL: v4bf16_to_v1i64:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
 entry:
   %1 = bitcast <4 x bfloat> %a to <1 x i64>
   ret <1 x i64> %1
 }
 
 define i64 @v4bf16_to_i64(float, <4 x bfloat> %a) nounwind {
 ; CHECK-LABEL: v4bf16_to_i64:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    fmov x0, d1
 ; CHECK-NEXT:    ret
 entry:
   %1 = bitcast <4 x bfloat> %a to i64
   ret i64 %1
 }
 
 define <2 x float> @v4bf16_to_v2float(float, <4 x bfloat> %a) nounwind {
 ; CHECK-LABEL: v4bf16_to_v2float:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
 entry:
   %1 = bitcast <4 x bfloat> %a to <2 x float>
   ret <2 x float> %1
 }
 
 define <1 x double> @v4bf16_to_v1double(float, <4 x bfloat> %a) nounwind {
 ; CHECK-LABEL: v4bf16_to_v1double:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
 entry:
   %1 = bitcast <4 x bfloat> %a to <1 x double>
   ret <1 x double> %1
 }
 
 define double @v4bf16_to_double(float, <4 x bfloat> %a) nounwind {
 ; CHECK-LABEL: v4bf16_to_double:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
 entry:
   %1 = bitcast <4 x bfloat> %a to double
   ret double %1
 }
 
 
 define <4 x bfloat> @v4i16_to_v4bf16(float, <4 x i16> %a) nounwind {
 ; CHECK-LABEL: v4i16_to_v4bf16:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
 entry:
   %1 = bitcast <4 x i16> %a to <4 x bfloat>
   ret <4 x bfloat> %1
 }
 
 define <4 x bfloat> @v2i32_to_v4bf16(float, <2 x i32> %a) nounwind {
 ; CHECK-LABEL: v2i32_to_v4bf16:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
 entry:
   %1 = bitcast <2 x i32> %a to <4 x bfloat>
   ret <4 x bfloat> %1
 }
 
 define <4 x bfloat> @v1i64_to_v4bf16(float, <1 x i64> %a) nounwind {
 ; CHECK-LABEL: v1i64_to_v4bf16:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
 entry:
   %1 = bitcast <1 x i64> %a to <4 x bfloat>
   ret <4 x bfloat> %1
 }
 
 define <4 x bfloat> @i64_to_v4bf16(float, i64 %a) nounwind {
 ; CHECK-LABEL: i64_to_v4bf16:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    fmov d0, x0
 ; CHECK-NEXT:    ret
 entry:
   %1 = bitcast i64 %a to <4 x bfloat>
   ret <4 x bfloat> %1
 }
 
 define <4 x bfloat> @v2float_to_v4bf16(float, <2 x float> %a) nounwind {
 ; CHECK-LABEL: v2float_to_v4bf16:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
 entry:
   %1 = bitcast <2 x float> %a to <4 x bfloat>
   ret <4 x bfloat> %1
 }
 
 define <4 x bfloat> @v1double_to_v4bf16(float, <1 x double> %a) nounwind {
 ; CHECK-LABEL: v1double_to_v4bf16:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
 entry:
   %1 = bitcast <1 x double> %a to <4 x bfloat>
   ret <4 x bfloat> %1
 }
 
 define <4 x bfloat> @double_to_v4bf16(float, double %a) nounwind {
 ; CHECK-LABEL: double_to_v4bf16:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
 entry:
   %1 = bitcast double %a to <4 x bfloat>
   ret <4 x bfloat> %1
 }
 
 define <8 x i16> @v8bf16_to_v8i16(float, <8 x bfloat> %a) nounwind {
 ; CHECK-LABEL: v8bf16_to_v8i16:

llvm/test/CodeGen/AArch64/bf16-vector-shuffle.ll

 
 ; bfloat16x4_t test_vset_lane_bf16(bfloat16_t a, bfloat16x4_t v) { return vset_lane_bf16(a, v, 1); }
 define <4 x bfloat> @test_vset_lane_bf16(bfloat %a, <4 x bfloat> %v) nounwind {
 ; CHECK-LABEL: test_vset_lane_bf16:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
 ; CHECK-NEXT:    // kill: def $h0 killed $h0 def $q0
 ; CHECK-NEXT:    mov v1.h[1], v0.h[0]
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
 entry:
   %vset_lane = insertelement <4 x bfloat> %v, bfloat %a, i32 1
   ret <4 x bfloat> %vset_lane
 }
 
 ; bfloat16x8_t test_vsetq_lane_bf16(bfloat16_t a, bfloat16x8_t v) { return vsetq_lane_bf16(a, v, 7); }
 define <8 x bfloat> @test_vsetq_lane_bf16(bfloat %a, <8 x bfloat> %v) nounwind {

llvm/test/CodeGen/AArch64/bitcast-promote-widen.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=aarch64-unknown-linux-gnu | FileCheck %s
 
 ; Test cases of bitcasts where one type needs to be widened and one needs to be promoted.
 
 define <2 x i16> @bitcast_v2i16_v2f16(<2 x half> %x) {
 ; CHECK-LABEL: bitcast_v2i16_v2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    umov w8, v0.h[0]
 ; CHECK-NEXT:    fmov s1, w8
 ; CHECK-NEXT:    umov w8, v0.h[1]
 ; CHECK-NEXT:    mov v1.s[1], w8
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
   %y = bitcast <2 x half> %x to <2 x i16>
   ret <2 x i16> %y
 }
 
 define <2 x half> @bitcast_v2f16_v2i16(<2 x i16> %x) {
 ; CHECK-LABEL: bitcast_v2f16_v2i16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    uzp1 v0.4h, v0.4h, v0.4h
 ; CHECK-NEXT:    ret
   %y = bitcast <2 x i16> %x to <2 x half>
   ret <2 x half> %y
 }

llvm/test/CodeGen/AArch64/combine-comparisons-by-cse.ll

 ; CHECK-NEXT:    mov w0, #1
 ; CHECK-NEXT:    bl zoo
 ; CHECK-NEXT:    mov w19, w0
 ; CHECK-NEXT:    mov w0, #-1
 ; CHECK-NEXT:    bl yoo
 ; CHECK-NEXT:    cmp w19, #0 // =0
 ; CHECK-NEXT:    cinc w0, w19, gt
 ; CHECK-NEXT:    mov w1, #2
-; CHECK-NEXT:    mov v8.16b, v0.16b
+; CHECK-NEXT:    fmov d8, d0
 ; CHECK-NEXT:    bl xoo
 ; CHECK-NEXT:    fmov d0, #-1.00000000
 ; CHECK-NEXT:    fadd d0, d8, d0
 ; CHECK-NEXT:    fcmp d8, #0.0
 ; CHECK-NEXT:    fcsel d0, d8, d0, gt
 ; CHECK-NEXT:    fmov d1, #-2.00000000
 ; CHECK-NEXT:    bl woo
 ; CHECK-NEXT:    mov w0, #4

llvm/test/CodeGen/AArch64/f16-instructions.ll

 define half @test_call(half %a, half %b) #0 {
   %r = call half @test_callee(half %a, half %b)
   ret half %r
 }
 
 ; CHECK-COMMON-LABEL: test_call_flipped:
 ; CHECK-COMMON-NEXT: stp x29, x30, [sp, #-16]!
 ; CHECK-COMMON-NEXT: mov  x29, sp
-; CHECK-COMMON-NEXT: mov.16b  v2, v0
-; CHECK-COMMON-NEXT: mov.16b  v0, v1
-; CHECK-COMMON-NEXT: mov.16b  v1, v2
+; CHECK-COMMON-NEXT: fmov  s2, s0
+; CHECK-COMMON-NEXT: fmov  s0, s1
+; CHECK-COMMON-NEXT: fmov  s1, s2
 ; CHECK-COMMON-NEXT: bl {{_?}}test_callee
 ; CHECK-COMMON-NEXT: ldp x29, x30, [sp], #16
 ; CHECK-COMMON-NEXT: ret
 define half @test_call_flipped(half %a, half %b) #0 {
   %r = call half @test_callee(half %b, half %a)
   ret half %r
 }
 
 ; CHECK-COMMON-LABEL: test_tailcall_flipped:
-; CHECK-COMMON-NEXT: mov.16b  v2, v0
-; CHECK-COMMON-NEXT: mov.16b  v0, v1
-; CHECK-COMMON-NEXT: mov.16b  v1, v2
+; CHECK-COMMON-NEXT: fmov  s2, s0
+; CHECK-COMMON-NEXT: fmov  s0, s1
+; CHECK-COMMON-NEXT: fmov  s1, s2
 ; CHECK-COMMON-NEXT: b {{_?}}test_callee
 define half @test_tailcall_flipped(half %a, half %b) #0 {
   %r = tail call half @test_callee(half %b, half %a)
   ret half %r
 }
 
 ; CHECK-CVT-LABEL: test_select:
 ; CHECK-CVT-NEXT: fcvt s1, h1
else:
   store i32 0, i32* %p2
   ret void
 }
 
 ; CHECK-COMMON-LABEL: test_phi:
 ; CHECK-COMMON: mov  x[[PTR:[0-9]+]], x0
 ; CHECK-COMMON: ldr  h[[AB:[0-9]+]], [x0]
 ; CHECK-COMMON: [[LOOP:LBB[0-9_]+]]:
-; CHECK-COMMON: mov.16b  v[[R:[0-9]+]], v[[AB]]
+; CHECK-COMMON: fmov  s[[R:[0-9]+]], s[[AB]]
 ; CHECK-COMMON: ldr  h[[AB]], [x[[PTR]]]
 ; CHECK-COMMON: mov  x0, x[[PTR]]
 ; CHECK-COMMON: bl {{_?}}test_dummy
-; CHECK-COMMON: mov.16b  v0, v[[R]]
+; CHECK-COMMON: fmov  s0, s[[R]]
 ; CHECK-COMMON: ret
 define half @test_phi(half* %p1) #0 {
 entry:
   %a = load half, half* %p1
   br label %loop
 loop:
   %r = phi half [%a, %entry], [%b, %loop]
   %b = load half, half* %p1

llvm/test/CodeGen/AArch64/fadd-combines.ll

 
 define double @test7(double %a, double %b) nounwind {
 ; CHECK-LABEL: test7:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str d8, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    fmov d2, #-2.00000000
 ; CHECK-NEXT:    fmul d1, d1, d2
 ; CHECK-NEXT:    fadd d8, d0, d1
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    str x30, [sp, #8] // 8-byte Folded Spill
 ; CHECK-NEXT:    bl use
 ; CHECK-NEXT:    ldr x30, [sp, #8] // 8-byte Folded Reload
-; CHECK-NEXT:    mov v0.16b, v8.16b
+; CHECK-NEXT:    fmov d0, d8
 ; CHECK-NEXT:    ldr d8, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %mul = fmul double %b, -2.000000e+00
   %add1 = fadd double %a, %mul
   call void @use(double %mul)
   ret double %add1
 }
 
 define float @fadd_const_multiuse_fmf(float %x) {
 ; CHECK-LABEL: fadd_const_multiuse_fmf:
 ; CHECK:       // %bb.0:
-; CHECK-DAG:     mov  [[W59:w[0-9]+]], #1114374144
-; CHECK-DAG:     mov  [[W42:w[0-9]+]], #1109917696
-; CHECK-DAG:     fmov [[FP59:s[0-9]+]], [[W59]]
-; CHECK-DAG:     fmov [[FP42:s[0-9]+]], [[W42]]
-; CHECK-NEXT:    fadd [[TMP1:s[0-9]+]], s0, [[FP42]]
-; CHECK-NEXT:    fadd [[TMP2:s[0-9]+]], s0, [[FP59]]
-; CHECK-NEXT:    fadd s0, [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    mov w8, #1109917696
+; CHECK-NEXT:    mov w9, #1114374144
+; CHECK-NEXT:    fmov s1, w8
+; CHECK-NEXT:    fmov s2, w9
+; CHECK-NEXT:    fadd s1, s0, s1
+; CHECK-NEXT:    fadd s0, s0, s2
+; CHECK-NEXT:    fadd s0, s1, s0
 ; CHECK-NEXT:    ret
   %a1 = fadd float %x, 42.0
   %a2 = fadd nsz reassoc float %a1, 17.0
   %a3 = fadd float %a1, %a2
   ret float %a3
 }
 
 ; DAGCombiner transforms this into: (x + 17.0) + (x + 59.0).
 define float @fadd_const_multiuse_attr(float %x) {
 ; CHECK-LABEL: fadd_const_multiuse_attr:
 ; CHECK:       // %bb.0:
-; CHECK-DAG:     mov  [[W17:w[0-9]+]], #1109917696
-; CHECK-DAG:     mov  [[W59:w[0-9]+]], #1114374144
-; CHECK-NEXT:    fmov [[FP17:s[0-9]+]], [[W17]]
-; CHECK-NEXT:    fmov [[FP59:s[0-9]+]], [[W59]]
-; CHECK-NEXT:    fadd [[TMP1:s[0-9]+]], s0, [[FP17]]
-; CHECK-NEXT:    fadd [[TMP2:s[0-9]+]], s0, [[FP59]]
-; CHECK-NEXT:    fadd s0, [[TMP1]], [[TMP2]]
+; CHECK-NEXT:    mov w8, #1109917696
+; CHECK-NEXT:    mov w9, #1114374144
+; CHECK-NEXT:    fmov s1, w8
+; CHECK-NEXT:    fmov s2, w9
+; CHECK-NEXT:    fadd s1, s0, s1
+; CHECK-NEXT:    fadd s0, s0, s2
+; CHECK-NEXT:    fadd s0, s1, s0
 ; CHECK-NEXT:    ret
   %a1 = fadd fast float %x, 42.0
   %a2 = fadd fast float %a1, 17.0
   %a3 = fadd fast float %a1, %a2
   ret float %a3
 }
 
 ; PR32939 - https://bugs.llvm.org/show_bug.cgi?id=32939

llvm/test/CodeGen/AArch64/fast-isel-select.ll

 ; GISEL-NEXT:  fcsel {{d[0-9]+}}, d0, d1, ne
   %1 = select i1 %c, double %a, double %b
   ret double %1
 }
 
 ; Now test the folding of all compares.
 define float @select_fcmp_false(float %x, float %a, float %b) {
 ; CHECK-LABEL: select_fcmp_false
-; CHECK:       mov.16b {{v[0-9]+}}, v2
+; CHECK:       fmov {{s[0-9]+}}, s2
   %1 = fcmp ogt float %x, %x
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_ogt(float %x, float %y, float %a, float %b) {
 ; CHECK-LABEL: select_fcmp_ogt
 ; CHECK:       fcmp s0, s1

 ; CHECK-NEXT:  fcsel {{s[0-9]+}}, s2, s3, ne
   %1 = fcmp une float %x, %y
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_fcmp_true(float %x, float %a, float %b) {
 ; CHECK-LABEL: select_fcmp_true
-; CHECK:       mov.16b {{v[0-9]+}}, v1
+; CHECK:       fmov {{s[0-9]+}}, s1
   %1 = fcmp ueq float %x, %x
   %2 = select i1 %1, float %a, float %b
   ret float %2
 }
 
 define float @select_icmp_eq(i32 %x, i32 %y, float %a, float %b) {
 ; CHECK-LABEL: select_icmp_eq
 ; CHECK:       cmp w0, w1

llvm/test/CodeGen/AArch64/fp16-v4-instructions.ll

 ; CHECK-DAG: fcvt
 ; CHECK-DAG: fcvt
   %1 = fpext <4 x half> %a to <4 x double>
   ret <4 x double> %1
 }
 
 define <4 x half> @bitcast_i_to_h(float, <4 x i16> %a) {
 ; CHECK-COMMON-LABEL: bitcast_i_to_h:
-; CHECK-COMMON:       mov v0.16b, v1.16b
+; CHECK-COMMON:       fmov d0, d1
 ; CHECK-COMMON-NEXT:  ret
   %2 = bitcast <4 x i16> %a to <4 x half>
   ret <4 x half> %2
 }
 
 define <4 x i16> @bitcast_h_to_i(float, <4 x half> %a) {
 ; CHECK-COMMON-LABEL: bitcast_h_to_i:
-; CHECK-COMMON:       mov v0.16b, v1.16b
+; CHECK-COMMON:       fmov d0, d1
 ; CHECK-COMMON-NEXT:  ret
   %2 = bitcast <4 x half> %a to <4 x i16>
   ret <4 x i16> %2
 }
 
 define <4 x half> @sitofp_i8(<4 x i8> %a) #0 {
 ; CHECK-COMMON-LABEL: sitofp_i8:
 ; CHECK-COMMON-NEXT:  shl [[OP1:v[0-9]+\.4h]], v0.4h, #8

llvm/test/CodeGen/AArch64/fp16-vector-bitcast.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
 
 define <4 x i16> @v4f16_to_v4i16(float, <4 x half> %a) #0 {
 ; CHECK-LABEL: v4f16_to_v4i16:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
 entry:
   %1 = bitcast <4 x half> %a to <4 x i16>
   ret <4 x i16> %1
 }
 
 define <2 x i32> @v4f16_to_v2i32(float, <4 x half> %a) #0 {
 ; CHECK-LABEL: v4f16_to_v2i32:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
 entry:
   %1 = bitcast <4 x half> %a to <2 x i32>
   ret <2 x i32> %1
 }
 
 define <1 x i64> @v4f16_to_v1i64(float, <4 x half> %a) #0 {
 ; CHECK-LABEL: v4f16_to_v1i64:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
 entry:
   %1 = bitcast <4 x half> %a to <1 x i64>
   ret <1 x i64> %1
 }
 
 define i64 @v4f16_to_i64(float, <4 x half> %a) #0 {
 ; CHECK-LABEL: v4f16_to_i64:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    fmov x0, d1
 ; CHECK-NEXT:    ret
 entry:
   %1 = bitcast <4 x half> %a to i64
   ret i64 %1
 }
 
 define <2 x float> @v4f16_to_v2float(float, <4 x half> %a) #0 {
 ; CHECK-LABEL: v4f16_to_v2float:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
 entry:
   %1 = bitcast <4 x half> %a to <2 x float>
   ret <2 x float> %1
 }
 
 define <1 x double> @v4f16_to_v1double(float, <4 x half> %a) #0 {
 ; CHECK-LABEL: v4f16_to_v1double:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
 entry:
   %1 = bitcast <4 x half> %a to <1 x double>
   ret <1 x double> %1
 }
 
 define double @v4f16_to_double(float, <4 x half> %a) #0 {
 ; CHECK-LABEL: v4f16_to_double:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
 entry:
   %1 = bitcast <4 x half> %a to double
   ret double %1
 }
 
 
 define <4 x half> @v4i16_to_v4f16(float, <4 x i16> %a) #0 {
 ; CHECK-LABEL: v4i16_to_v4f16:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
 entry:
   %1 = bitcast <4 x i16> %a to <4 x half>
   ret <4 x half> %1
 }
 
 define <4 x half> @v2i32_to_v4f16(float, <2 x i32> %a) #0 {
 ; CHECK-LABEL: v2i32_to_v4f16:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
 entry:
   %1 = bitcast <2 x i32> %a to <4 x half>
   ret <4 x half> %1
 }
 
 define <4 x half> @v1i64_to_v4f16(float, <1 x i64> %a) #0 {
 ; CHECK-LABEL: v1i64_to_v4f16:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
 entry:
   %1 = bitcast <1 x i64> %a to <4 x half>
   ret <4 x half> %1
 }
 
 define <4 x half> @i64_to_v4f16(float, i64 %a) #0 {
 ; CHECK-LABEL: i64_to_v4f16:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    fmov d0, x0
 ; CHECK-NEXT:    ret
 entry:
   %1 = bitcast i64 %a to <4 x half>
   ret <4 x half> %1
 }
 
 define <4 x half> @v2float_to_v4f16(float, <2 x float> %a) #0 {
 ; CHECK-LABEL: v2float_to_v4f16:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
 entry:
   %1 = bitcast <2 x float> %a to <4 x half>
   ret <4 x half> %1
 }
 
 define <4 x half> @v1double_to_v4f16(float, <1 x double> %a) #0 {
 ; CHECK-LABEL: v1double_to_v4f16:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
 entry:
   %1 = bitcast <1 x double> %a to <4 x half>
   ret <4 x half> %1
 }
 
 define <4 x half> @double_to_v4f16(float, double %a) #0 {
 ; CHECK-LABEL: double_to_v4f16:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
 entry:
   %1 = bitcast double %a to <4 x half>
   ret <4 x half> %1
 }
 
 
 

llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll

; CHECK-NEXT:    ret
     ret i64 %x
 }
 
 define i100 @test_signed_i100_f32(float %f) nounwind {
 ; CHECK-LABEL: test_signed_i100_f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str d8, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    str x30, [sp, #8] // 8-byte Folded Spill
-; CHECK-NEXT:    mov v8.16b, v0.16b
+; CHECK-NEXT:    fmov s8, s0
 ; CHECK-NEXT:    bl __fixsfti
 ; CHECK-NEXT:    mov w8, #-251658240
 ; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    mov w8, #1895825407
 ; CHECK-NEXT:    fcmp s8, s0
 ; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    mov x8, #-34359738368
 ; CHECK-NEXT:    ldr x30, [sp, #8] // 8-byte Folded Reload
; CHECK-NEXT:    ret
     ret i100 %x
 }
 
 define i128 @test_signed_i128_f32(float %f) nounwind {
 ; CHECK-LABEL: test_signed_i128_f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str d8, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    str x30, [sp, #8] // 8-byte Folded Spill
-; CHECK-NEXT:    mov v8.16b, v0.16b
+; CHECK-NEXT:    fmov s8, s0
 ; CHECK-NEXT:    bl __fixsfti
 ; CHECK-NEXT:    mov w8, #-16777216
 ; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    mov w8, #2130706431
 ; CHECK-NEXT:    fcmp s8, s0
 ; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    mov x8, #-9223372036854775808
 ; CHECK-NEXT:    ldr x30, [sp, #8] // 8-byte Folded Reload
; CHECK-NEXT:    ret
     ret i64 %x
 }
 
 define i100 @test_signed_i100_f64(double %f) nounwind {
 ; CHECK-LABEL: test_signed_i100_f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str d8, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    str x30, [sp, #8] // 8-byte Folded Spill
-; CHECK-NEXT:    mov v8.16b, v0.16b
+; CHECK-NEXT:    fmov d8, d0
 ; CHECK-NEXT:    bl __fixdfti
 ; CHECK-NEXT:    mov x8, #-4170333254945079296
 ; CHECK-NEXT:    fmov d0, x8
 ; CHECK-NEXT:    mov x8, #5053038781909696511
 ; CHECK-NEXT:    fcmp d8, d0
 ; CHECK-NEXT:    fmov d0, x8
 ; CHECK-NEXT:    mov x8, #-34359738368
 ; CHECK-NEXT:    ldr x30, [sp, #8] // 8-byte Folded Reload
; CHECK-NEXT:    ret
     ret i100 %x
 }
 
 define i128 @test_signed_i128_f64(double %f) nounwind {
 ; CHECK-LABEL: test_signed_i128_f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str d8, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    str x30, [sp, #8] // 8-byte Folded Spill
-; CHECK-NEXT:    mov v8.16b, v0.16b
+; CHECK-NEXT:    fmov d8, d0
 ; CHECK-NEXT:    bl __fixdfti
 ; CHECK-NEXT:    mov x8, #-4044232465378705408
 ; CHECK-NEXT:    fmov d0, x8
 ; CHECK-NEXT:    mov x8, #5179139571476070399
 ; CHECK-NEXT:    fcmp d8, d0
 ; CHECK-NEXT:    fmov d0, x8
 ; CHECK-NEXT:    mov x8, #-9223372036854775808
 ; CHECK-NEXT:    ldr x30, [sp, #8] // 8-byte Folded Reload
; CHECK-FP16-NEXT:    ret
     ret i64 %x
 }
 
 define i100 @test_signed_i100_f16(half %f) nounwind {
 ; CHECK-LABEL: test_signed_i100_f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str d8, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    fcvt s8, h0
-; CHECK-NEXT:    mov v0.16b, v8.16b
+; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    str x30, [sp, #8] // 8-byte Folded Spill
 ; CHECK-NEXT:    bl __fixsfti
 ; CHECK-NEXT:    mov w8, #-251658240
 ; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    mov w8, #1895825407
 ; CHECK-NEXT:    fcmp s8, s0
 ; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    mov x8, #-34359738368
; CHECK-NEXT:    ret
     ret i100 %x
 }
 
 define i128 @test_signed_i128_f16(half %f) nounwind {
 ; CHECK-LABEL: test_signed_i128_f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str d8, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    fcvt s8, h0
-; CHECK-NEXT:    mov v0.16b, v8.16b
+; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    str x30, [sp, #8] // 8-byte Folded Spill
 ; CHECK-NEXT:    bl __fixsfti
 ; CHECK-NEXT:    mov w8, #-16777216
 ; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    mov w8, #2130706431
 ; CHECK-NEXT:    fcmp s8, s0
 ; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    mov x8, #-9223372036854775808

llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll

 ; CHECK-NEXT:    .cfi_offset w22, -32
 ; CHECK-NEXT:    .cfi_offset w30, -40
 ; CHECK-NEXT:    .cfi_offset b8, -48
 ; CHECK-NEXT:    .cfi_offset b9, -56
 ; CHECK-NEXT:    .cfi_offset b10, -64
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    mov s8, v0.s[1]
 ; CHECK-NEXT:    str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT:    mov v0.16b, v8.16b
+; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    bl __fixsfti
 ; CHECK-NEXT:    mov w8, #-251658240
 ; CHECK-NEXT:    mov w9, #1895825407
 ; CHECK-NEXT:    fmov s9, w8
 ; CHECK-NEXT:    mov x21, #-34359738368
 ; CHECK-NEXT:    fmov s10, w9
 ; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    mov x22, #34359738367

 ; CHECK-NEXT:    .cfi_offset w22, -32
 ; CHECK-NEXT:    .cfi_offset w30, -40
 ; CHECK-NEXT:    .cfi_offset b8, -48
 ; CHECK-NEXT:    .cfi_offset b9, -56
 ; CHECK-NEXT:    .cfi_offset b10, -64
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    mov s8, v0.s[1]
 ; CHECK-NEXT:    str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT:    mov v0.16b, v8.16b
+; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    bl __fixsfti
 ; CHECK-NEXT:    mov w8, #-16777216
 ; CHECK-NEXT:    mov w9, #2130706431
 ; CHECK-NEXT:    fmov s9, w8
 ; CHECK-NEXT:    mov x21, #-9223372036854775808
 ; CHECK-NEXT:    fmov s10, w9
 ; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    mov x22, #9223372036854775807

 ; CHECK-NEXT:    .cfi_offset w21, -24
 ; CHECK-NEXT:    .cfi_offset w22, -32
 ; CHECK-NEXT:    .cfi_offset w30, -40
 ; CHECK-NEXT:    .cfi_offset b8, -48
 ; CHECK-NEXT:    .cfi_offset b9, -56
 ; CHECK-NEXT:    .cfi_offset b10, -64
 ; CHECK-NEXT:    mov d8, v0.d[1]
 ; CHECK-NEXT:    str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT:    mov v0.16b, v8.16b
+; CHECK-NEXT:    fmov d0, d8
 ; CHECK-NEXT:    bl __fixdfti
 ; CHECK-NEXT:    mov x8, #-4170333254945079296
 ; CHECK-NEXT:    mov x9, #5053038781909696511
 ; CHECK-NEXT:    fmov d9, x8
 ; CHECK-NEXT:    mov x21, #-34359738368
 ; CHECK-NEXT:    fmov d10, x9
 ; CHECK-NEXT:    fcmp d8, d9
 ; CHECK-NEXT:    mov x22, #34359738367

 ; CHECK-NEXT:    .cfi_offset w21, -24
 ; CHECK-NEXT:    .cfi_offset w22, -32
 ; CHECK-NEXT:    .cfi_offset w30, -40
 ; CHECK-NEXT:    .cfi_offset b8, -48
 ; CHECK-NEXT:    .cfi_offset b9, -56
 ; CHECK-NEXT:    .cfi_offset b10, -64
 ; CHECK-NEXT:    mov d8, v0.d[1]
 ; CHECK-NEXT:    str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT:    mov v0.16b, v8.16b
+; CHECK-NEXT:    fmov d0, d8
 ; CHECK-NEXT:    bl __fixdfti
 ; CHECK-NEXT:    mov x8, #-4044232465378705408
 ; CHECK-NEXT:    mov x9, #5179139571476070399
 ; CHECK-NEXT:    fmov d9, x8
 ; CHECK-NEXT:    mov x21, #-9223372036854775808
 ; CHECK-NEXT:    fmov d10, x9
 ; CHECK-NEXT:    fcmp d8, d9
 ; CHECK-NEXT:    mov x22, #9223372036854775807

 ; CHECK-NEXT:    .cfi_offset w30, -72
 ; CHECK-NEXT:    .cfi_offset b8, -80
 ; CHECK-NEXT:    .cfi_offset b9, -88
 ; CHECK-NEXT:    .cfi_offset b10, -96
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    mov h1, v0.h[1]
 ; CHECK-NEXT:    fcvt s8, h1
 ; CHECK-NEXT:    str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT:    mov v0.16b, v8.16b
+; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    bl __fixsfti
 ; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
 ; CHECK-NEXT:    mov w8, #-251658240
 ; CHECK-NEXT:    mov w9, #1895825407
 ; CHECK-NEXT:    fmov s9, w8
 ; CHECK-NEXT:    mov x25, #-34359738368
 ; CHECK-NEXT:    fmov s10, w9
 ; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    mov x26, #34359738367
 ; CHECK-NEXT:    csel x8, xzr, x0, lt
 ; CHECK-NEXT:    csel x9, x25, x1, lt
 ; CHECK-NEXT:    fcmp s8, s10
 ; CHECK-NEXT:    mov h0, v0.h[2]
 ; CHECK-NEXT:    csel x9, x26, x9, gt
 ; CHECK-NEXT:    csinv x8, x8, xzr, le
 ; CHECK-NEXT:    fcmp s8, s8
 ; CHECK-NEXT:    fcvt s8, h0
-; CHECK-NEXT:    mov v0.16b, v8.16b
+; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    csel x19, xzr, x8, vs
 ; CHECK-NEXT:    csel x20, xzr, x9, vs
 ; CHECK-NEXT:    bl __fixsfti
 ; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
 ; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    csel x8, xzr, x0, lt
 ; CHECK-NEXT:    csel x9, x25, x1, lt
 ; CHECK-NEXT:    mov h0, v0.h[3]
 ; CHECK-NEXT:    fcmp s8, s10
 ; CHECK-NEXT:    csel x9, x26, x9, gt
 ; CHECK-NEXT:    csinv x8, x8, xzr, le
 ; CHECK-NEXT:    fcmp s8, s8
 ; CHECK-NEXT:    fcvt s8, h0
-; CHECK-NEXT:    mov v0.16b, v8.16b
+; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    csel x21, xzr, x8, vs
 ; CHECK-NEXT:    csel x22, xzr, x9, vs
 ; CHECK-NEXT:    bl __fixsfti
 ; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
 ; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    csel x8, xzr, x0, lt
 ; CHECK-NEXT:    csel x9, x25, x1, lt
 ; CHECK-NEXT:    fcmp s8, s10
 ; CHECK-NEXT:    csel x9, x26, x9, gt
 ; CHECK-NEXT:    csinv x8, x8, xzr, le
 ; CHECK-NEXT:    fcmp s8, s8
 ; CHECK-NEXT:    fcvt s8, h0
-; CHECK-NEXT:    mov v0.16b, v8.16b
+; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    csel x23, xzr, x8, vs
 ; CHECK-NEXT:    csel x24, xzr, x9, vs
 ; CHECK-NEXT:    bl __fixsfti
 ; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    csel x8, x25, x1, lt
 ; CHECK-NEXT:    csel x9, xzr, x0, lt
 ; CHECK-NEXT:    fcmp s8, s10
 ; CHECK-NEXT:    csinv x9, x9, xzr, le

 ; CHECK-NEXT:    .cfi_offset w30, -72
 ; CHECK-NEXT:    .cfi_offset b8, -80
 ; CHECK-NEXT:    .cfi_offset b9, -88
 ; CHECK-NEXT:    .cfi_offset b10, -96
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    mov h1, v0.h[1]
 ; CHECK-NEXT:    fcvt s8, h1
 ; CHECK-NEXT:    str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT:    mov v0.16b, v8.16b
+; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    bl __fixsfti
 ; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
 ; CHECK-NEXT:    mov w8, #-16777216
 ; CHECK-NEXT:    mov w9, #2130706431
 ; CHECK-NEXT:    fmov s9, w8
 ; CHECK-NEXT:    mov x25, #-9223372036854775808
 ; CHECK-NEXT:    fmov s10, w9
 ; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    mov x26, #9223372036854775807
 ; CHECK-NEXT:    csel x8, xzr, x0, lt
 ; CHECK-NEXT:    csel x9, x25, x1, lt
 ; CHECK-NEXT:    fcmp s8, s10
 ; CHECK-NEXT:    mov h0, v0.h[2]
 ; CHECK-NEXT:    csel x9, x26, x9, gt
 ; CHECK-NEXT:    csinv x8, x8, xzr, le
 ; CHECK-NEXT:    fcmp s8, s8
 ; CHECK-NEXT:    fcvt s8, h0
-; CHECK-NEXT:    mov v0.16b, v8.16b
+; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    csel x19, xzr, x8, vs
 ; CHECK-NEXT:    csel x20, xzr, x9, vs
 ; CHECK-NEXT:    bl __fixsfti
 ; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
 ; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    csel x8, xzr, x0, lt
 ; CHECK-NEXT:    csel x9, x25, x1, lt
 ; CHECK-NEXT:    mov h0, v0.h[3]
 ; CHECK-NEXT:    fcmp s8, s10
 ; CHECK-NEXT:    csel x9, x26, x9, gt
 ; CHECK-NEXT:    csinv x8, x8, xzr, le
 ; CHECK-NEXT:    fcmp s8, s8
 ; CHECK-NEXT:    fcvt s8, h0
-; CHECK-NEXT:    mov v0.16b, v8.16b
+; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    csel x21, xzr, x8, vs
 ; CHECK-NEXT:    csel x22, xzr, x9, vs
 ; CHECK-NEXT:    bl __fixsfti
 ; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
 ; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    csel x8, xzr, x0, lt
 ; CHECK-NEXT:    csel x9, x25, x1, lt
 ; CHECK-NEXT:    fcmp s8, s10
 ; CHECK-NEXT:    csel x9, x26, x9, gt
 ; CHECK-NEXT:    csinv x8, x8, xzr, le
 ; CHECK-NEXT:    fcmp s8, s8
 ; CHECK-NEXT:    fcvt s8, h0
-; CHECK-NEXT:    mov v0.16b, v8.16b
+; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    csel x23, xzr, x8, vs
 ; CHECK-NEXT:    csel x24, xzr, x9, vs
 ; CHECK-NEXT:    bl __fixsfti
 ; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    csel x8, x25, x1, lt
 ; CHECK-NEXT:    csel x9, xzr, x0, lt
 ; CHECK-NEXT:    fcmp s8, s10
 ; CHECK-NEXT:    csinv x9, x9, xzr, le

llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll

; CHECK-NEXT:    ret
     ret i64 %x
 }
 
 define i100 @test_unsigned_i100_f32(float %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i100_f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str d8, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    str x30, [sp, #8] // 8-byte Folded Spill
-; CHECK-NEXT:    mov v8.16b, v0.16b
+; CHECK-NEXT:    fmov s8, s0
 ; CHECK-NEXT:    bl __fixunssfti
 ; CHECK-NEXT:    mov w8, #1904214015
 ; CHECK-NEXT:    ldr x30, [sp, #8] // 8-byte Folded Reload
 ; CHECK-NEXT:    fcmp s8, #0.0
 ; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    mov x9, #68719476735
 ; CHECK-NEXT:    csel x10, xzr, x0, lt
 ; CHECK-NEXT:    csel x11, xzr, x1, lt
 ; CHECK-NEXT:    fcmp s8, s0
 ; CHECK-NEXT:    csel x1, x9, x11, gt
 ; CHECK-NEXT:    csinv x0, x10, xzr, le
 ; CHECK-NEXT:    ldr d8, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
     %x = call i100 @llvm.fptoui.sat.i100.f32(float %f)
     ret i100 %x
 }
 
 define i128 @test_unsigned_i128_f32(float %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i128_f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str d8, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    str x30, [sp, #8] // 8-byte Folded Spill
-; CHECK-NEXT:    mov v8.16b, v0.16b
+; CHECK-NEXT:    fmov s8, s0
 ; CHECK-NEXT:    bl __fixunssfti
 ; CHECK-NEXT:    mov w8, #2139095039
 ; CHECK-NEXT:    ldr x30, [sp, #8] // 8-byte Folded Reload
 ; CHECK-NEXT:    fcmp s8, #0.0
 ; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    csel x9, xzr, x1, lt
 ; CHECK-NEXT:    csel x10, xzr, x0, lt
 ; CHECK-NEXT:    fcmp s8, s0
; CHECK-NEXT:    ret
     ret i64 %x
 }
 
 define i100 @test_unsigned_i100_f64(double %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i100_f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str d8, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    str x30, [sp, #8] // 8-byte Folded Spill
-; CHECK-NEXT:    mov v8.16b, v0.16b
+; CHECK-NEXT:    fmov d8, d0
 ; CHECK-NEXT:    bl __fixunsdfti
 ; CHECK-NEXT:    mov x8, #5057542381537067007
 ; CHECK-NEXT:    ldr x30, [sp, #8] // 8-byte Folded Reload
 ; CHECK-NEXT:    fcmp d8, #0.0
 ; CHECK-NEXT:    fmov d0, x8
 ; CHECK-NEXT:    mov x9, #68719476735
 ; CHECK-NEXT:    csel x10, xzr, x0, lt
 ; CHECK-NEXT:    csel x11, xzr, x1, lt
 ; CHECK-NEXT:    fcmp d8, d0
 ; CHECK-NEXT:    csel x1, x9, x11, gt
 ; CHECK-NEXT:    csinv x0, x10, xzr, le
 ; CHECK-NEXT:    ldr d8, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
     %x = call i100 @llvm.fptoui.sat.i100.f64(double %f)
     ret i100 %x
 }
 
 define i128 @test_unsigned_i128_f64(double %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i128_f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str d8, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    str x30, [sp, #8] // 8-byte Folded Spill
-; CHECK-NEXT:    mov v8.16b, v0.16b
+; CHECK-NEXT:    fmov d8, d0
 ; CHECK-NEXT:    bl __fixunsdfti
 ; CHECK-NEXT:    mov x8, #5183643171103440895
 ; CHECK-NEXT:    ldr x30, [sp, #8] // 8-byte Folded Reload
 ; CHECK-NEXT:    fcmp d8, #0.0
 ; CHECK-NEXT:    fmov d0, x8
 ; CHECK-NEXT:    csel x9, xzr, x1, lt
 ; CHECK-NEXT:    csel x10, xzr, x0, lt
 ; CHECK-NEXT:    fcmp d8, d0
; CHECK-FP16-NEXT:    ret
     ret i64 %x
 }
 
 define i100 @test_unsigned_i100_f16(half %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i100_f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str d8, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    fcvt s8, h0
-; CHECK-NEXT:    mov v0.16b, v8.16b
+; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    str x30, [sp, #8] // 8-byte Folded Spill
 ; CHECK-NEXT:    bl __fixunssfti
 ; CHECK-NEXT:    mov w8, #1904214015
 ; CHECK-NEXT:    ldr x30, [sp, #8] // 8-byte Folded Reload
 ; CHECK-NEXT:    fcmp s8, #0.0
 ; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    mov x9, #68719476735
 ; CHECK-NEXT:    csel x10, xzr, x0, lt
 ; CHECK-NEXT:    csel x11, xzr, x1, lt
 ; CHECK-NEXT:    fcmp s8, s0
 ; CHECK-NEXT:    csel x1, x9, x11, gt
 ; CHECK-NEXT:    csinv x0, x10, xzr, le
 ; CHECK-NEXT:    ldr d8, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
     %x = call i100 @llvm.fptoui.sat.i100.f16(half %f)
     ret i100 %x
 }
 
 define i128 @test_unsigned_i128_f16(half %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i128_f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str d8, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    fcvt s8, h0
-; CHECK-NEXT:    mov v0.16b, v8.16b
+; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    str x30, [sp, #8] // 8-byte Folded Spill
 ; CHECK-NEXT:    bl __fixunssfti
 ; CHECK-NEXT:    mov w8, #2139095039
 ; CHECK-NEXT:    ldr x30, [sp, #8] // 8-byte Folded Reload
 ; CHECK-NEXT:    fcmp s8, #0.0
 ; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    csel x9, xzr, x1, lt
 ; CHECK-NEXT:    csel x10, xzr, x0, lt
 ; CHECK-NEXT:    fcmp s8, s0
 ; CHECK-NEXT:    csinv x0, x10, xzr, le
 ; CHECK-NEXT:    csinv x1, x9, xzr, le
 ; CHECK-NEXT:    ldr d8, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
     %x = call i128 @llvm.fptoui.sat.i128.f16(half %f)
     ret i128 %x
 }

llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll

 ; CHECK-NEXT:    .cfi_offset w20, -16
 ; CHECK-NEXT:    .cfi_offset w21, -24
 ; CHECK-NEXT:    .cfi_offset w30, -32
 ; CHECK-NEXT:    .cfi_offset b8, -40
 ; CHECK-NEXT:    .cfi_offset b9, -48
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    mov s8, v0.s[1]
 ; CHECK-NEXT:    str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT:    mov v0.16b, v8.16b
+; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    bl __fixunssfti
 ; CHECK-NEXT:    mov w8, #1904214015
 ; CHECK-NEXT:    fcmp s8, #0.0
 ; CHECK-NEXT:    fmov s9, w8
 ; CHECK-NEXT:    mov x21, #68719476735
 ; CHECK-NEXT:    csel x9, xzr, x0, lt
 ; CHECK-NEXT:    csel x10, xzr, x1, lt
 ; CHECK-NEXT:    fcmp s8, s9

 ; CHECK-NEXT:    .cfi_offset w19, -8
 ; CHECK-NEXT:    .cfi_offset w20, -16
 ; CHECK-NEXT:    .cfi_offset w30, -32
 ; CHECK-NEXT:    .cfi_offset b8, -40
 ; CHECK-NEXT:    .cfi_offset b9, -48
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    mov s8, v0.s[1]
 ; CHECK-NEXT:    str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT:    mov v0.16b, v8.16b
+; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    bl __fixunssfti
 ; CHECK-NEXT:    mov w8, #2139095039
 ; CHECK-NEXT:    fcmp s8, #0.0
 ; CHECK-NEXT:    fmov s9, w8
 ; CHECK-NEXT:    csel x9, xzr, x1, lt
 ; CHECK-NEXT:    csel x10, xzr, x0, lt
 ; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload

 ; CHECK-NEXT:    .cfi_offset w19, -8
 ; CHECK-NEXT:    .cfi_offset w20, -16
 ; CHECK-NEXT:    .cfi_offset w21, -24
 ; CHECK-NEXT:    .cfi_offset w30, -32
 ; CHECK-NEXT:    .cfi_offset b8, -40
 ; CHECK-NEXT:    .cfi_offset b9, -48
 ; CHECK-NEXT:    mov d8, v0.d[1]
 ; CHECK-NEXT:    str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT:    mov v0.16b, v8.16b
+; CHECK-NEXT:    fmov d0, d8
 ; CHECK-NEXT:    bl __fixunsdfti
 ; CHECK-NEXT:    mov x8, #5057542381537067007
 ; CHECK-NEXT:    fcmp d8, #0.0
 ; CHECK-NEXT:    fmov d9, x8
 ; CHECK-NEXT:    mov x21, #68719476735
 ; CHECK-NEXT:    csel x9, xzr, x0, lt
 ; CHECK-NEXT:    csel x10, xzr, x1, lt
 ; CHECK-NEXT:    fcmp d8, d9

 ; CHECK-NEXT:    .cfi_def_cfa_offset 64
 ; CHECK-NEXT:    .cfi_offset w19, -8
 ; CHECK-NEXT:    .cfi_offset w20, -16
 ; CHECK-NEXT:    .cfi_offset w30, -32
 ; CHECK-NEXT:    .cfi_offset b8, -40
 ; CHECK-NEXT:    .cfi_offset b9, -48
 ; CHECK-NEXT:    mov d8, v0.d[1]
 ; CHECK-NEXT:    str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT:    mov v0.16b, v8.16b
+; CHECK-NEXT:    fmov d0, d8
 ; CHECK-NEXT:    bl __fixunsdfti
 ; CHECK-NEXT:    mov x8, #5183643171103440895
 ; CHECK-NEXT:    fcmp d8, #0.0
 ; CHECK-NEXT:    fmov d9, x8
 ; CHECK-NEXT:    csel x9, xzr, x1, lt
 ; CHECK-NEXT:    csel x10, xzr, x0, lt
 ; CHECK-NEXT:    fcmp d8, d9
 ; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload

 ; CHECK-NEXT:    .cfi_offset w25, -56
 ; CHECK-NEXT:    .cfi_offset w30, -64
 ; CHECK-NEXT:    .cfi_offset b8, -72
 ; CHECK-NEXT:    .cfi_offset b9, -80
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    mov h1, v0.h[2]
 ; CHECK-NEXT:    fcvt s8, h1
 ; CHECK-NEXT:    str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT:    mov v0.16b, v8.16b
+; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    bl __fixunssfti
 ; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
 ; CHECK-NEXT:    mov w8, #1904214015
 ; CHECK-NEXT:    fcmp s8, #0.0
 ; CHECK-NEXT:    fmov s9, w8
 ; CHECK-NEXT:    mov h0, v0.h[1]
 ; CHECK-NEXT:    csel x9, xzr, x0, lt
 ; CHECK-NEXT:    csel x10, xzr, x1, lt
 ; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    fcvt s8, h0
 ; CHECK-NEXT:    mov x25, #68719476735
-; CHECK-NEXT:    mov v0.16b, v8.16b
+; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    csel x19, x25, x10, gt
 ; CHECK-NEXT:    csinv x20, x9, xzr, le
 ; CHECK-NEXT:    bl __fixunssfti
 ; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
 ; CHECK-NEXT:    fcmp s8, #0.0
 ; CHECK-NEXT:    csel x8, xzr, x0, lt
 ; CHECK-NEXT:    csel x9, xzr, x1, lt
 ; CHECK-NEXT:    mov h0, v0.h[3]
 ; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    fcvt s8, h0
-; CHECK-NEXT:    mov v0.16b, v8.16b
+; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    csel x21, x25, x9, gt
 ; CHECK-NEXT:    csinv x22, x8, xzr, le
 ; CHECK-NEXT:    bl __fixunssfti
 ; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
 ; CHECK-NEXT:    fcmp s8, #0.0
 ; CHECK-NEXT:    csel x8, xzr, x0, lt
 ; CHECK-NEXT:    csel x9, xzr, x1, lt
 ; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    fcvt s8, h0
-; CHECK-NEXT:    mov v0.16b, v8.16b
+; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    csel x23, x25, x9, gt
 ; CHECK-NEXT:    csinv x24, x8, xzr, le
 ; CHECK-NEXT:    bl __fixunssfti
 ; CHECK-NEXT:    fcmp s8, #0.0
 ; CHECK-NEXT:    csel x8, xzr, x0, lt
 ; CHECK-NEXT:    csel x9, xzr, x1, lt
 ; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    csinv x8, x8, xzr, le

 ; CHECK-NEXT:    .cfi_offset w24, -48
 ; CHECK-NEXT:    .cfi_offset w30, -64
 ; CHECK-NEXT:    .cfi_offset b8, -72
 ; CHECK-NEXT:    .cfi_offset b9, -80
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    mov h1, v0.h[1]
 ; CHECK-NEXT:    fcvt s8, h1
 ; CHECK-NEXT:    str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT:    mov v0.16b, v8.16b
+; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    bl __fixunssfti
 ; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
 ; CHECK-NEXT:    mov w8, #2139095039
 ; CHECK-NEXT:    fcmp s8, #0.0
 ; CHECK-NEXT:    fmov s9, w8
 ; CHECK-NEXT:    mov h0, v0.h[2]
 ; CHECK-NEXT:    csel x9, xzr, x1, lt
 ; CHECK-NEXT:    csel x10, xzr, x0, lt
 ; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    fcvt s8, h0
-; CHECK-NEXT:    mov v0.16b, v8.16b
+; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    csinv x19, x10, xzr, le
 ; CHECK-NEXT:    csinv x20, x9, xzr, le
 ; CHECK-NEXT:    bl __fixunssfti
 ; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
 ; CHECK-NEXT:    fcmp s8, #0.0
 ; CHECK-NEXT:    csel x8, xzr, x1, lt
 ; CHECK-NEXT:    csel x9, xzr, x0, lt
 ; CHECK-NEXT:    mov h0, v0.h[3]
 ; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    fcvt s8, h0
-; CHECK-NEXT:    mov v0.16b, v8.16b
+; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    csinv x21, x9, xzr, le
 ; CHECK-NEXT:    csinv x22, x8, xzr, le
 ; CHECK-NEXT:    bl __fixunssfti
 ; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
 ; CHECK-NEXT:    fcmp s8, #0.0
 ; CHECK-NEXT:    csel x8, xzr, x1, lt
 ; CHECK-NEXT:    csel x9, xzr, x0, lt
 ; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    fcvt s8, h0
-; CHECK-NEXT:    mov v0.16b, v8.16b
+; CHECK-NEXT:    fmov s0, s8
 ; CHECK-NEXT:    csinv x23, x9, xzr, le
 ; CHECK-NEXT:    csinv x24, x8, xzr, le
 ; CHECK-NEXT:    bl __fixunssfti
 ; CHECK-NEXT:    fcmp s8, #0.0
 ; CHECK-NEXT:    csel x8, xzr, x0, lt
 ; CHECK-NEXT:    csel x9, xzr, x1, lt
 ; CHECK-NEXT:    fcmp s8, s9
 ; CHECK-NEXT:    csinv x8, x8, xzr, le

llvm/test/CodeGen/AArch64/machine-combiner.ll

 ; PR25016: https://llvm.org/bugs/show_bug.cgi?id=25016
 ; Verify that reassociation is not happening needlessly or wrongly.
 
 declare double @bar()
 
 define double @reassociate_adds_from_calls() {
 ; CHECK-LABEL: reassociate_adds_from_calls:
 ; CHECK:       bl   bar
-; CHECK-NEXT:  mov  v8.16b, v0.16b 
+; CHECK-NEXT:  fmov d8, d0
 ; CHECK-NEXT:  bl   bar
-; CHECK-NEXT:  mov  v9.16b, v0.16b
+; CHECK-NEXT:  fmov d9, d0
 ; CHECK-NEXT:  bl   bar
-; CHECK-NEXT:  mov  v10.16b, v0.16b 
+; CHECK-NEXT:  fmov d10, d0
 ; CHECK-NEXT:  bl   bar
-; CHECK:       fadd d1, d8, d9 
+; CHECK:       fadd d1, d8, d9
 ; CHECK-NEXT:  fadd d0, d10, d0
 ; CHECK-NEXT:  fadd d0, d1, d0
   %x0 = call double @bar()
   %x1 = call double @bar()
   %x2 = call double @bar()
   %x3 = call double @bar()
   %t0 = fadd double %x0, %x1
   %t1 = fadd double %t0, %x2
   %t2 = fadd double %t1, %x3
   ret double %t2
 }
 
 define double @already_reassociated() {
 ; CHECK-LABEL: already_reassociated:
 ; CHECK:       bl   bar
-; CHECK-NEXT:  mov  v8.16b, v0.16b 
+; CHECK-NEXT:  fmov d8, d0
 ; CHECK-NEXT:  bl   bar
-; CHECK-NEXT:  mov  v9.16b, v0.16b
+; CHECK-NEXT:  fmov d9, d0
 ; CHECK-NEXT:  bl   bar
-; CHECK-NEXT:  mov  v10.16b, v0.16b 
+; CHECK-NEXT:  fmov d10, d0
 ; CHECK-NEXT:  bl   bar
 ; CHECK:       fadd d1, d8, d9 
 ; CHECK-NEXT:  fadd d0, d10, d0
 ; CHECK-NEXT:  fadd d0, d1, d0
   %x0 = call double @bar()
   %x1 = call double @bar()
   %x2 = call double @bar()
   %x3 = call double @bar()
   %t0 = fadd double %x0, %x1
   %t1 = fadd double %x2, %x3
   %t2 = fadd double %t0, %t1
   ret double %t2
 }
 

llvm/test/CodeGen/AArch64/mla_mls_merge.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-unknown-linux-gnu | FileCheck %s
 
 define <4 x i16> @test_mla0(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 x i8> %d) {
 ; CHECK-LABEL: test_mla0:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    umull v2.8h, v2.8b, v3.8b
 ; CHECK-NEXT:    umlal v2.8h, v0.8b, v1.8b
-; CHECK-NEXT:    mov v0.16b, v2.16b
+; CHECK-NEXT:    fmov d0, d2
 ; CHECK-NEXT:    ret
 entry:
   %vmull.i = tail call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> %a, <8 x i8> %b)
   %vmull.i.i = tail call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> %c, <8 x i8> %d)
   %add.i = add <8 x i16> %vmull.i.i, %vmull.i
   %shuffle.i = shufflevector <8 x i16> %add.i, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x i16> %shuffle.i
 }
 
 
 define <4 x i16> @test_mla1(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c, <8 x i8> %d) {
 ; CHECK-LABEL: test_mla1:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    smull v2.8h, v2.8b, v3.8b
 ; CHECK-NEXT:    smlal v2.8h, v0.8b, v1.8b
-; CHECK-NEXT:    mov v0.16b, v2.16b
+; CHECK-NEXT:    fmov d0, d2
 ; CHECK-NEXT:    ret
 entry:
   %vmull.i = tail call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> %a, <8 x i8> %b)
   %vmull.i.i = tail call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> %c, <8 x i8> %d)
   %add.i = add <8 x i16> %vmull.i.i, %vmull.i
   %shuffle.i = shufflevector <8 x i16> %add.i, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x i16> %shuffle.i
 }
 
 
 define <2 x i32> @test_mla2(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c, <4 x i16> %d) {
 ; CHECK-LABEL: test_mla2:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    umull v2.4s, v2.4h, v3.4h
 ; CHECK-NEXT:    umlal v2.4s, v0.4h, v1.4h
-; CHECK-NEXT:    mov v0.16b, v2.16b
+; CHECK-NEXT:    fmov d0, d2
 ; CHECK-NEXT:    ret
 entry:
   %vmull2.i = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %a, <4 x i16> %b)
   %vmull2.i.i = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %c, <4 x i16> %d)
   %add.i = add <4 x i32> %vmull2.i.i, %vmull2.i
   %shuffle.i = shufflevector <4 x i32> %add.i, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
   ret <2 x i32> %shuffle.i
 }
 
 
 define <2 x i32> @test_mla3(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c, <4 x i16> %d) {
 ; CHECK-LABEL: test_mla3:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    smull v2.4s, v2.4h, v3.4h
 ; CHECK-NEXT:    smlal v2.4s, v0.4h, v1.4h
-; CHECK-NEXT:    mov v0.16b, v2.16b
+; CHECK-NEXT:    fmov d0, d2
 ; CHECK-NEXT:    ret
 entry:
   %vmull2.i = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %a, <4 x i16> %b)
   %vmull2.i.i = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %c, <4 x i16> %d)
   %add.i = add <4 x i32> %vmull2.i.i, %vmull2.i
   %shuffle.i = shufflevector <4 x i32> %add.i, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
   ret <2 x i32> %shuffle.i
 }
 
 
 define <1 x i64> @test_mla4(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i32> %d) {
 ; CHECK-LABEL: test_mla4:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    umull v2.2d, v2.2s, v3.2s
 ; CHECK-NEXT:    umlal v2.2d, v0.2s, v1.2s
-; CHECK-NEXT:    mov v0.16b, v2.16b
+; CHECK-NEXT:    fmov d0, d2
 ; CHECK-NEXT:    ret
 entry:
   %vmull2.i = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %a, <2 x i32> %b)
   %vmull2.i.i = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %c, <2 x i32> %d)
   %add.i = add <2 x i64> %vmull2.i.i, %vmull2.i
   %shuffle.i = shufflevector <2 x i64> %add.i, <2 x i64> undef, <1 x i32> zeroinitializer
   ret <1 x i64> %shuffle.i
 }
 
 
 define <1 x i64> @test_mla5(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x i32> %d) {
 ; CHECK-LABEL: test_mla5:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    smull v2.2d, v2.2s, v3.2s
 ; CHECK-NEXT:    smlal v2.2d, v0.2s, v1.2s
-; CHECK-NEXT:    mov v0.16b, v2.16b
+; CHECK-NEXT:    fmov d0, d2
 ; CHECK-NEXT:    ret
 entry:
   %vmull2.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %a, <2 x i32> %b)
   %vmull2.i.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %c, <2 x i32> %d)
   %add.i = add <2 x i64> %vmull2.i.i, %vmull2.i
   %shuffle.i = shufflevector <2 x i64> %add.i, <2 x i64> undef, <1 x i32> zeroinitializer
   ret <1 x i64> %shuffle.i
 }

llvm/test/CodeGen/AArch64/neon-mla-mls.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
 
 
 define <8 x i8> @mla8xi8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C) {
 ; CHECK-LABEL: mla8xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mla v2.8b, v0.8b, v1.8b
-; CHECK-NEXT:    mov v0.16b, v2.16b
+; CHECK-NEXT:    fmov d0, d2
 ; CHECK-NEXT:    ret
   %tmp1 = mul <8 x i8> %A, %B;
   %tmp2 = add <8 x i8> %C, %tmp1;
   ret <8 x i8> %tmp2
 }
 
 define <16 x i8> @mla16xi8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C) {
 ; CHECK-LABEL: mla16xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mla v2.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    mov v0.16b, v2.16b
 ; CHECK-NEXT:    ret
   %tmp1 = mul <16 x i8> %A, %B;
   %tmp2 = add <16 x i8> %C, %tmp1;
   ret <16 x i8> %tmp2
 }
 
 define <4 x i16> @mla4xi16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C) {
 ; CHECK-LABEL: mla4xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mla v2.4h, v0.4h, v1.4h
-; CHECK-NEXT:    mov v0.16b, v2.16b
+; CHECK-NEXT:    fmov d0, d2
 ; CHECK-NEXT:    ret
   %tmp1 = mul <4 x i16> %A, %B;
   %tmp2 = add <4 x i16> %C, %tmp1;
   ret <4 x i16> %tmp2
 }
 
 define <8 x i16> @mla8xi16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C) {
 ; CHECK-LABEL: mla8xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mla v2.8h, v0.8h, v1.8h
 ; CHECK-NEXT:    mov v0.16b, v2.16b
 ; CHECK-NEXT:    ret
   %tmp1 = mul <8 x i16> %A, %B;
   %tmp2 = add <8 x i16> %C, %tmp1;
   ret <8 x i16> %tmp2
 }
 
 define <2 x i32> @mla2xi32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C) {
 ; CHECK-LABEL: mla2xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mla v2.2s, v0.2s, v1.2s
-; CHECK-NEXT:    mov v0.16b, v2.16b
+; CHECK-NEXT:    fmov d0, d2
 ; CHECK-NEXT:    ret
   %tmp1 = mul <2 x i32> %A, %B;
   %tmp2 = add <2 x i32> %C, %tmp1;
   ret <2 x i32> %tmp2
 }
 
 define <4 x i32> @mla4xi32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {
 ; CHECK-LABEL: mla4xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mla v2.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    mov v0.16b, v2.16b
 ; CHECK-NEXT:    ret
   %tmp1 = mul <4 x i32> %A, %B;
   %tmp2 = add <4 x i32> %C, %tmp1;
   ret <4 x i32> %tmp2
 }
 
 define <8 x i8> @mls8xi8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C) {
 ; CHECK-LABEL: mls8xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mls v2.8b, v0.8b, v1.8b
-; CHECK-NEXT:    mov v0.16b, v2.16b
+; CHECK-NEXT:    fmov d0, d2
 ; CHECK-NEXT:    ret
   %tmp1 = mul <8 x i8> %A, %B;
   %tmp2 = sub <8 x i8> %C, %tmp1;
   ret <8 x i8> %tmp2
 }
 
 define <16 x i8> @mls16xi8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C) {
 ; CHECK-LABEL: mls16xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mls v2.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    mov v0.16b, v2.16b
 ; CHECK-NEXT:    ret
   %tmp1 = mul <16 x i8> %A, %B;
   %tmp2 = sub <16 x i8> %C, %tmp1;
   ret <16 x i8> %tmp2
 }
 
 define <4 x i16> @mls4xi16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C) {
 ; CHECK-LABEL: mls4xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mls v2.4h, v0.4h, v1.4h
-; CHECK-NEXT:    mov v0.16b, v2.16b
+; CHECK-NEXT:    fmov d0, d2
 ; CHECK-NEXT:    ret
   %tmp1 = mul <4 x i16> %A, %B;
   %tmp2 = sub <4 x i16> %C, %tmp1;
   ret <4 x i16> %tmp2
 }
 
 define <8 x i16> @mls8xi16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C) {
 ; CHECK-LABEL: mls8xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mls v2.8h, v0.8h, v1.8h
 ; CHECK-NEXT:    mov v0.16b, v2.16b
 ; CHECK-NEXT:    ret
   %tmp1 = mul <8 x i16> %A, %B;
   %tmp2 = sub <8 x i16> %C, %tmp1;
   ret <8 x i16> %tmp2
 }
 
 define <2 x i32> @mls2xi32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C) {
 ; CHECK-LABEL: mls2xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mls v2.2s, v0.2s, v1.2s
-; CHECK-NEXT:    mov v0.16b, v2.16b
+; CHECK-NEXT:    fmov d0, d2
 ; CHECK-NEXT:    ret
   %tmp1 = mul <2 x i32> %A, %B;
   %tmp2 = sub <2 x i32> %C, %tmp1;
   ret <2 x i32> %tmp2
 }
 
 define <4 x i32> @mls4xi32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {
 ; CHECK-LABEL: mls4xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mls v2.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    mov v0.16b, v2.16b
 ; CHECK-NEXT:    ret
   %tmp1 = mul <4 x i32> %A, %B;
   %tmp2 = sub <4 x i32> %C, %tmp1;
   ret <4 x i32> %tmp2
 }
 
 
 define <8 x i8> @mls2v8xi8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C) {
 ; CHECK-LABEL: mls2v8xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    neg v2.8b, v2.8b
 ; CHECK-NEXT:    mla v2.8b, v0.8b, v1.8b
-; CHECK-NEXT:    mov v0.16b, v2.16b
+; CHECK-NEXT:    fmov d0, d2
 ; CHECK-NEXT:    ret
   %tmp1 = mul <8 x i8> %A, %B;
   %tmp2 = sub <8 x i8> %tmp1, %C;
   ret <8 x i8> %tmp2
 }
 
 define <16 x i8> @mls2v16xi8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C) {
 ; CHECK-LABEL: mls2v16xi8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    neg v2.16b, v2.16b
 ; CHECK-NEXT:    mla v2.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    mov v0.16b, v2.16b
 ; CHECK-NEXT:    ret
   %tmp1 = mul <16 x i8> %A, %B;
   %tmp2 = sub <16 x i8> %tmp1, %C;
   ret <16 x i8> %tmp2
 }
 
 define <4 x i16> @mls2v4xi16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C) {
 ; CHECK-LABEL: mls2v4xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    neg v2.4h, v2.4h
 ; CHECK-NEXT:    mla v2.4h, v0.4h, v1.4h
-; CHECK-NEXT:    mov v0.16b, v2.16b
+; CHECK-NEXT:    fmov d0, d2
 ; CHECK-NEXT:    ret
   %tmp1 = mul <4 x i16> %A, %B;
   %tmp2 = sub <4 x i16> %tmp1, %C;
   ret <4 x i16> %tmp2
 }
 
 define <8 x i16> @mls2v8xi16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C) {
 ; CHECK-LABEL: mls2v8xi16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    neg v2.8h, v2.8h
 ; CHECK-NEXT:    mla v2.8h, v0.8h, v1.8h
 ; CHECK-NEXT:    mov v0.16b, v2.16b
 ; CHECK-NEXT:    ret
   %tmp1 = mul <8 x i16> %A, %B;
   %tmp2 = sub <8 x i16> %tmp1, %C;
   ret <8 x i16> %tmp2
 }
 
 define <2 x i32> @mls2v2xi32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C) {
 ; CHECK-LABEL: mls2v2xi32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    neg v2.2s, v2.2s
 ; CHECK-NEXT:    mla v2.2s, v0.2s, v1.2s
-; CHECK-NEXT:    mov v0.16b, v2.16b
+; CHECK-NEXT:    fmov d0, d2
 ; CHECK-NEXT:    ret
   %tmp1 = mul <2 x i32> %A, %B;
   %tmp2 = sub <2 x i32> %tmp1, %C;
   ret <2 x i32> %tmp2
 }
 
 define <4 x i32> @mls2v4xi32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {
 ; CHECK-LABEL: mls2v4xi32:

llvm/test/CodeGen/AArch64/popcount.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -O0 -mtriple=aarch64-unknown-unknown | FileCheck %s
 
 ; Function Attrs: nobuiltin nounwind readonly
 define i8 @popcount128(i128* nocapture nonnull readonly %0) {
 ; CHECK-LABEL: popcount128:
 ; CHECK:       // %bb.0: // %Entry
 ; CHECK-NEXT:    ldr x8, [x0, #8]
 ; CHECK-NEXT:    ldr d1, [x0]
 ; CHECK-NEXT:    // implicit-def: $q0
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    mov v0.d[1], x8
 ; CHECK-NEXT:    cnt v0.16b, v0.16b
 ; CHECK-NEXT:    uaddlv h1, v0.16b
 ; CHECK-NEXT:    // implicit-def: $q0
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov s0, s1
 ; CHECK-NEXT:    fmov w0, s0
 ; CHECK-NEXT:    ret
 Entry:
   %1 = load i128, i128* %0, align 16
   %2 = tail call i128 @llvm.ctpop.i128(i128 %1)
   %3 = trunc i128 %2 to i8
   ret i8 %3
 }
 
 ; Function Attrs: nounwind readnone speculatable willreturn
 declare i128 @llvm.ctpop.i128(i128)
 
 ; Function Attrs: nobuiltin nounwind readonly
 define i16 @popcount256(i256* nocapture nonnull readonly %0) {
 ; CHECK-LABEL: popcount256:
 ; CHECK:       // %bb.0: // %Entry
 ; CHECK-NEXT:    ldr x8, [x0, #8]
 ; CHECK-NEXT:    ldr x9, [x0, #24]
 ; CHECK-NEXT:    ldr d1, [x0, #16]
 ; CHECK-NEXT:    // implicit-def: $q0
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    mov v0.d[1], x9
 ; CHECK-NEXT:    cnt v0.16b, v0.16b
 ; CHECK-NEXT:    uaddlv h1, v0.16b
 ; CHECK-NEXT:    // implicit-def: $q0
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov s0, s1
 ; CHECK-NEXT:    fmov w9, s0
 ; CHECK-NEXT:    ldr d1, [x0]
 ; CHECK-NEXT:    // implicit-def: $q0
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    mov v0.d[1], x8
 ; CHECK-NEXT:    cnt v0.16b, v0.16b
 ; CHECK-NEXT:    uaddlv h1, v0.16b
 ; CHECK-NEXT:    // implicit-def: $q0
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov s0, s1
 ; CHECK-NEXT:    fmov w8, s0
 ; CHECK-NEXT:    add w0, w8, w9
 ; CHECK-NEXT:    ret
 Entry:
   %1 = load i256, i256* %0, align 16
   %2 = tail call i256 @llvm.ctpop.i256(i256 %1)
   %3 = trunc i256 %2 to i16
   ret i16 %3
 }
 
 ; Function Attrs: nounwind readnone speculatable willreturn
 declare i256 @llvm.ctpop.i256(i256)
 
 define <1 x i128> @popcount1x128(<1 x i128> %0) {
 ; CHECK-LABEL: popcount1x128:
 ; CHECK:       // %bb.0: // %Entry
 ; CHECK-NEXT:    // implicit-def: $q0
 ; CHECK-NEXT:    fmov d0, x0
 ; CHECK-NEXT:    mov v0.d[1], x1
 ; CHECK-NEXT:    cnt v0.16b, v0.16b
 ; CHECK-NEXT:    uaddlv h1, v0.16b
 ; CHECK-NEXT:    // implicit-def: $q0
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov s0, s1
 ; CHECK-NEXT:    fmov w0, s0
 ; CHECK-NEXT:    // kill: def $x0 killed $w0
 ; CHECK-NEXT:    movi v0.2d, #0000000000000000
 ; CHECK-NEXT:    mov x1, v0.d[1]
 ; CHECK-NEXT:    ret
 Entry:
   %1 = tail call <1 x i128> @llvm.ctpop.v1.i128(<1 x i128> %0)
   ret <1 x i128> %1
 }
 
 declare <1 x i128> @llvm.ctpop.v1.i128(<1 x i128>)

llvm/test/CodeGen/AArch64/sqrt-fastmath.ll

 ; CHECK-NEXT:    fmul d1, d1, d2
 ; CHECK-NEXT:    fmul d2, d1, d1
 ; CHECK-NEXT:    frsqrts d2, d0, d2
 ; CHECK-NEXT:    fmul d1, d1, d2
 ; CHECK-NEXT:    fcmp d0, #0.0
 ; CHECK-NEXT:    fmul d1, d0, d1
 ; CHECK-NEXT:    fcsel d0, d0, d1, eq
 ; CHECK-NEXT:    str d0, [x0]
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
   %sqrt = call fast double @llvm.sqrt.f64(double %x)
   store double %sqrt, double* %p
   %r = fdiv fast double %x, %sqrt
   ret double %r
 }
 
 define double @sqrt_simplify_before_recip_3_uses(double %x, double* %p1, double* %p2) nounwind {

llvm/test/CodeGen/AArch64/swift-return.ll

define swiftcc { i8, i8, i8, i8 } @gen9(i8 %key) {
   %v0 = insertvalue { i8, i8, i8, i8 } undef, i8 %key, 0
   %v1 = insertvalue { i8, i8, i8, i8 } %v0, i8 %key, 1
   %v2 = insertvalue { i8, i8, i8, i8 } %v1, i8 %key, 2
   %v3 = insertvalue { i8, i8, i8, i8 } %v2, i8 %key, 3
   ret { i8, i8, i8, i8 } %v3
 }
 
 ; CHECK-LABEL: _gen10
-; CHECK:  mov.16b         v1, v0
-; CHECK:  mov.16b         v2, v0
-; CHECK:  mov.16b         v3, v0
+; CHECK:  fmov         d1, d0
+; CHECK:  fmov         d2, d0
+; CHECK:  fmov         d3, d0
 ; CHECK:  mov      w1, w0
 ; CHECK:  mov      w2, w0
 ; CHECK:  mov      w3, w0
 ; CHECK:  ret
 define swiftcc { double, double, double, double, i32, i32, i32, i32 } @gen10(double %keyd, i32 %keyi) {
   %v0 = insertvalue { double, double, double, double, i32, i32, i32, i32 } undef, double %keyd, 0
   %v1 = insertvalue { double, double, double, double, i32, i32, i32, i32 } %v0, double %keyd, 1
   %v2 = insertvalue { double, double, double, double, i32, i32, i32, i32 } %v1, double %keyd, 2
entry:
   ret <4 x float> %add2
 }
 
 declare swiftcc { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @gen11()
 
 ; CHECK-LABEL: _test12
 ; CHECK:  fadd.4s v0, v0, v1
 ; CHECK:  fadd.4s v0, v0, v2
-; CHECK:  mov.16b v1, v3
+; CHECK:  fmov s1, s3
 define swiftcc { <4 x float>, float } @test12() #0 {
 entry:
   %call = call swiftcc { <4 x float>, <4 x float>, <4 x float>, float } @gen12()
 
   %v3 = extractvalue { <4 x float>, <4 x float>, <4 x float>, float } %call, 0
   %v5 = extractvalue { <4 x float>, <4 x float>, <4 x float>, float } %call, 1
   %v6 = extractvalue { <4 x float>, <4 x float>, <4 x float>, float } %call, 2
   %v8 = extractvalue { <4 x float>, <4 x float>, <4 x float>, float } %call, 3

llvm/test/CodeGen/AArch64/urem-vector-lkk.ll

 ; CHECK-NEXT:    umov w10, v0.h[1]
 ; CHECK-NEXT:    fmov s1, w9
 ; CHECK-NEXT:    umov w9, v0.h[2]
 ; CHECK-NEXT:    and w10, w10, #0x1f
 ; CHECK-NEXT:    and w9, w9, #0x7
 ; CHECK-NEXT:    mov v1.h[1], w10
 ; CHECK-NEXT:    mov v1.h[2], w9
 ; CHECK-NEXT:    mov v1.h[3], w8
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
   %1 = urem <4 x i16> %x, <i16 64, i16 32, i16 8, i16 95>
   ret <4 x i16> %1
 }
 
 ; Don't fold if the divisor is one.
 define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {
 ; CHECK-LABEL: dont_fold_srem_one:

 ; CHECK-NEXT:    movi d1, #0000000000000000
 ; CHECK-NEXT:    umull x11, w10, w11
 ; CHECK-NEXT:    mov v1.h[1], w9
 ; CHECK-NEXT:    mov w9, #5423
 ; CHECK-NEXT:    lsr x11, x11, #43
 ; CHECK-NEXT:    mov v1.h[2], w8
 ; CHECK-NEXT:    msub w8, w11, w9, w10
 ; CHECK-NEXT:    mov v1.h[3], w8
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov d0, d1
 ; CHECK-NEXT:    ret
   %1 = urem <4 x i16> %x, <i16 1, i16 654, i16 23, i16 5423>
   ret <4 x i16> %1
 }
 
 ; Don't fold if the divisor is 2^16.
 define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
 ; CHECK-LABEL: dont_fold_urem_i16_smax:

llvm/test/CodeGen/AArch64/vec-libcalls.ll

 
 define <5 x float> @sin_v5f32(<5 x float> %x) nounwind {
 ; CHECK-LABEL: sin_v5f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str d12, [sp, #-48]! // 8-byte Folded Spill
 ; CHECK-NEXT:    stp d11, d10, [sp, #8] // 16-byte Folded Spill
 ; CHECK-NEXT:    stp d9, d8, [sp, #24] // 16-byte Folded Spill
 ; CHECK-NEXT:    str x30, [sp, #40] // 8-byte Folded Spill
-; CHECK-NEXT:    mov v8.16b, v4.16b
-; CHECK-NEXT:    mov v9.16b, v3.16b
-; CHECK-NEXT:    mov v10.16b, v2.16b
-; CHECK-NEXT:    mov v11.16b, v1.16b
-; CHECK-NEXT:    bl sinf
-; CHECK-NEXT:    mov v12.16b, v0.16b
-; CHECK-NEXT:    mov v0.16b, v11.16b
-; CHECK-NEXT:    bl sinf
-; CHECK-NEXT:    mov v11.16b, v0.16b
-; CHECK-NEXT:    mov v0.16b, v10.16b
-; CHECK-NEXT:    bl sinf
-; CHECK-NEXT:    mov v10.16b, v0.16b
-; CHECK-NEXT:    mov v0.16b, v9.16b
-; CHECK-NEXT:    bl sinf
-; CHECK-NEXT:    mov v9.16b, v0.16b
-; CHECK-NEXT:    mov v0.16b, v8.16b
-; CHECK-NEXT:    bl sinf
-; CHECK-NEXT:    mov v1.16b, v11.16b
-; CHECK-NEXT:    mov v2.16b, v10.16b
-; CHECK-NEXT:    mov v3.16b, v9.16b
+; CHECK-NEXT:    fmov s8, s4
+; CHECK-NEXT:    fmov s9, s3
+; CHECK-NEXT:    fmov s10, s2
+; CHECK-NEXT:    fmov s11, s1
+; CHECK-NEXT:    bl sinf
+; CHECK-NEXT:    fmov s12, s0
+; CHECK-NEXT:    fmov s0, s11
+; CHECK-NEXT:    bl sinf
+; CHECK-NEXT:    fmov s11, s0
+; CHECK-NEXT:    fmov s0, s10
+; CHECK-NEXT:    bl sinf
+; CHECK-NEXT:    fmov s10, s0
+; CHECK-NEXT:    fmov s0, s9
+; CHECK-NEXT:    bl sinf
+; CHECK-NEXT:    fmov s9, s0
+; CHECK-NEXT:    fmov s0, s8
+; CHECK-NEXT:    bl sinf
+; CHECK-NEXT:    fmov s1, s11
+; CHECK-NEXT:    fmov s2, s10
+; CHECK-NEXT:    fmov s3, s9
 ; CHECK-NEXT:    ldr x30, [sp, #40] // 8-byte Folded Reload
 ; CHECK-NEXT:    ldp d9, d8, [sp, #24] // 16-byte Folded Reload
 ; CHECK-NEXT:    ldp d11, d10, [sp, #8] // 16-byte Folded Reload
-; CHECK-NEXT:    mov v4.16b, v0.16b
-; CHECK-NEXT:    mov v0.16b, v12.16b
+; CHECK-NEXT:    fmov s4, s0
+; CHECK-NEXT:    fmov s0, s12
 ; CHECK-NEXT:    ldr d12, [sp], #48 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %r = call <5 x float> @llvm.sin.v5f32(<5 x float> %x)
   ret <5 x float> %r
 }
 
 define <6 x float> @sin_v6f32(<6 x float> %x) nounwind {
 ; CHECK-LABEL: sin_v6f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    stp d13, d12, [sp, #-64]! // 16-byte Folded Spill
 ; CHECK-NEXT:    stp d11, d10, [sp, #16] // 16-byte Folded Spill
 ; CHECK-NEXT:    stp d9, d8, [sp, #32] // 16-byte Folded Spill
 ; CHECK-NEXT:    str x30, [sp, #48] // 8-byte Folded Spill
-; CHECK-NEXT:    mov v8.16b, v5.16b
-; CHECK-NEXT:    mov v9.16b, v4.16b
-; CHECK-NEXT:    mov v10.16b, v3.16b
-; CHECK-NEXT:    mov v11.16b, v2.16b
-; CHECK-NEXT:    mov v12.16b, v1.16b
-; CHECK-NEXT:    bl sinf
-; CHECK-NEXT:    mov v13.16b, v0.16b
-; CHECK-NEXT:    mov v0.16b, v12.16b
-; CHECK-NEXT:    bl sinf
-; CHECK-NEXT:    mov v12.16b, v0.16b
-; CHECK-NEXT:    mov v0.16b, v11.16b
-; CHECK-NEXT:    bl sinf
-; CHECK-NEXT:    mov v11.16b, v0.16b
-; CHECK-NEXT:    mov v0.16b, v10.16b
-; CHECK-NEXT:    bl sinf
-; CHECK-NEXT:    mov v10.16b, v0.16b
-; CHECK-NEXT:    mov v0.16b, v9.16b
-; CHECK-NEXT:    bl sinf
-; CHECK-NEXT:    mov v9.16b, v0.16b
-; CHECK-NEXT:    mov v0.16b, v8.16b
-; CHECK-NEXT:    bl sinf
-; CHECK-NEXT:    mov v2.16b, v11.16b
-; CHECK-NEXT:    mov v3.16b, v10.16b
-; CHECK-NEXT:    mov v4.16b, v9.16b
+; CHECK-NEXT:    fmov s8, s5
+; CHECK-NEXT:    fmov s9, s4
+; CHECK-NEXT:    fmov s10, s3
+; CHECK-NEXT:    fmov s11, s2
+; CHECK-NEXT:    fmov s12, s1
+; CHECK-NEXT:    bl sinf
+; CHECK-NEXT:    fmov s13, s0
+; CHECK-NEXT:    fmov s0, s12
+; CHECK-NEXT:    bl sinf
+; CHECK-NEXT:    fmov s12, s0
+; CHECK-NEXT:    fmov s0, s11
+; CHECK-NEXT:    bl sinf
+; CHECK-NEXT:    fmov s11, s0
+; CHECK-NEXT:    fmov s0, s10
+; CHECK-NEXT:    bl sinf
+; CHECK-NEXT:    fmov s10, s0
+; CHECK-NEXT:    fmov s0, s9
+; CHECK-NEXT:    bl sinf
+; CHECK-NEXT:    fmov s9, s0
+; CHECK-NEXT:    fmov s0, s8
+; CHECK-NEXT:    bl sinf
+; CHECK-NEXT:    fmov s2, s11
+; CHECK-NEXT:    fmov s3, s10
+; CHECK-NEXT:    fmov s4, s9
 ; CHECK-NEXT:    ldr x30, [sp, #48] // 8-byte Folded Reload
 ; CHECK-NEXT:    ldp d9, d8, [sp, #32] // 16-byte Folded Reload
 ; CHECK-NEXT:    ldp d11, d10, [sp, #16] // 16-byte Folded Reload
-; CHECK-NEXT:    mov v5.16b, v0.16b
-; CHECK-NEXT:    mov v0.16b, v13.16b
-; CHECK-NEXT:    mov v1.16b, v12.16b
+; CHECK-NEXT:    fmov s5, s0
+; CHECK-NEXT:    fmov s0, s13
+; CHECK-NEXT:    fmov s1, s12
 ; CHECK-NEXT:    ldp d13, d12, [sp], #64 // 16-byte Folded Reload
 ; CHECK-NEXT:    ret
   %r = call <6 x float> @llvm.sin.v6f32(<6 x float> %x)
   ret <6 x float> %r
 }
 
 define <3 x double> @sin_v3f64(<3 x double> %x) nounwind {
 ; CHECK-LABEL: sin_v3f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str d10, [sp, #-32]! // 8-byte Folded Spill
 ; CHECK-NEXT:    stp d9, d8, [sp, #8] // 16-byte Folded Spill
 ; CHECK-NEXT:    str x30, [sp, #24] // 8-byte Folded Spill
-; CHECK-NEXT:    mov v8.16b, v2.16b
-; CHECK-NEXT:    mov v9.16b, v1.16b
+; CHECK-NEXT:    fmov d8, d2
+; CHECK-NEXT:    fmov d9, d1
 ; CHECK-NEXT:    bl sin
-; CHECK-NEXT:    mov v10.16b, v0.16b
-; CHECK-NEXT:    mov v0.16b, v9.16b
+; CHECK-NEXT:    fmov d10, d0
+; CHECK-NEXT:    fmov d0, d9
 ; CHECK-NEXT:    bl sin
-; CHECK-NEXT:    mov v9.16b, v0.16b
-; CHECK-NEXT:    mov v0.16b, v8.16b
+; CHECK-NEXT:    fmov d9, d0
+; CHECK-NEXT:    fmov d0, d8
 ; CHECK-NEXT:    bl sin
-; CHECK-NEXT:    mov v1.16b, v9.16b
+; CHECK-NEXT:    fmov d1, d9
 ; CHECK-NEXT:    ldr x30, [sp, #24] // 8-byte Folded Reload
 ; CHECK-NEXT:    ldp d9, d8, [sp, #8] // 16-byte Folded Reload
-; CHECK-NEXT:    mov v2.16b, v0.16b
-; CHECK-NEXT:    mov v0.16b, v10.16b
+; CHECK-NEXT:    fmov d2, d0
+; CHECK-NEXT:    fmov d0, d10
 ; CHECK-NEXT:    ldr d10, [sp], #32 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %r = call <3 x double> @llvm.sin.v3f64(<3 x double> %x)
   ret <3 x double> %r
 }
 
 define <3 x float> @fabs_v3f32(<3 x float> %x) nounwind {
 ; CHECK-LABEL: fabs_v3f32:

llvm/test/Transforms/LoopStrengthReduce/AArch64/small-constant.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-
 ; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
 
 ; Test LSR for giving small constants, which get re-associated as unfolded
 ; offset, a chance to get combined with loop-invariant registers (same as
 ; large constants which do not fit as add immediate operands). LSR
 ; favors here to bump the base pointer outside the loop.
 
 ; float test(float *arr, long long start, float threshold) {

 ; CHECK-NEXT:  // %bb.3: // %for.cond
 ; CHECK-NEXT:    // in Loop: Header=BB0_2 Depth=1
 ; CHECK-NEXT:    add x1, x1, #1 // =1
 ; CHECK-NEXT:    cbnz x1, .LBB0_2
 ; CHECK-NEXT:  .LBB0_4:
 ; CHECK-NEXT:    fmov s0, #-7.00000000
 ; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB0_5: // %cleanup2
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov s0, s1
 ; CHECK-NEXT:    ret
 entry:
   %cmp11 = icmp eq i64 %start, 0
   br i1 %cmp11, label %cleanup2, label %for.body
 
 for.cond:                                         ; preds = %for.body
   %cmp = icmp eq i64 %inc, 0
   br i1 %cmp, label %cleanup2, label %for.body

 ; CHECK-NEXT:  // %bb.3: // %for.cond
 ; CHECK-NEXT:    // in Loop: Header=BB1_2 Depth=1
 ; CHECK-NEXT:    add x1, x1, #1 // =1
 ; CHECK-NEXT:    cbnz x1, .LBB1_2
 ; CHECK-NEXT:  .LBB1_4:
 ; CHECK-NEXT:    fmov s0, #-7.00000000
 ; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB1_5: // %cleanup4
-; CHECK-NEXT:    mov v0.16b, v1.16b
+; CHECK-NEXT:    fmov s0, s1
 ; CHECK-NEXT:    ret
 entry:
   %cmp14 = icmp eq i64 %start, 0
   br i1 %cmp14, label %cleanup4, label %for.body
 
 for.cond:                                         ; preds = %for.body
   %cmp = icmp eq i64 %inc, 0
   br i1 %cmp, label %cleanup4, label %for.body