[TableGen] Allow isAllocatable inheritence from any superclass

[critson]

Summary

When setting Allocatable on a generated register class check all
superclasses and set Allocatable true if any superclass is
allocatable.

Without this change generated register classes based on an
allocatable class may end up unallocatable due to the topological
inheritance order.

This change primarily effects AMDGPU backend; however, there are
a few changes in MIPs GlobalISel register constraints as a result.

[kparzysz]

I think it's ok, but it makes me wonder about the other properties. If this one can vary depending on the topological ordering, can VTs or CopyCost (for example) change too? Logically, VTs should be the intersection of VTs over all super classes, other properties may need different treatment.

llvm/utils/TableGen/CodeGenRegisters.cpp

836–839

You could just use any_of for the set of super classes.

[critson]

• Rework to use any_of

[critson]

In D105967#2877328, @kparzysz wrote:

I think it's ok, but it makes me wonder about the other properties. If this one can vary depending on the topological ordering, can VTs or CopyCost (for example) change too? Logically, VTs should be the intersection of VTs over all super classes, other properties may need different treatment.

I agree there may be other opportunities to improve the multi-inheritance.

For our usage we have an unallocatable superclass with a mix of allocatable and unallocatable subclasses.
All relevant classes have the same VTs, CopyCost, AllocationPriority, etc.
So at present it is the only the Allocatable flag that has been a problem.

VTs does seem to fit as an intersection.
AllocationPriority, CopyCost could be perhaps be maxima, although this could be restrictive.
No idea about AltOrderSelect.
That said, I do not want to increase the scope of this patch beyond Allocatable.

llvm/utils/TableGen/CodeGenRegisters.cpp

void CodeGenRegisterClass::inheritProperties(CodeGenRegBank &RegBank) {
   // The last super-class is the smallest one.
   CodeGenRegisterClass &Super = *SuperClasses.back();
 
   // Most properties are copied directly.
   // Exceptions are members, size, and alignment
   Namespace = Super.Namespace;
   VTs = Super.VTs;
   CopyCost = Super.CopyCost;
-  Allocatable = Super.Allocatable;
+  // Check for allocatable superclasses.
+  Allocatable = any_of(SuperClasses, [&](const CodeGenRegisterClass *S) {
+    return S->Allocatable;
+  });
   AltOrderSelect = Super.AltOrderSelect;
   AllocationPriority = Super.AllocationPriority;
   GeneratePressureSet |= Super.GeneratePressureSet;
 
   // Copy all allocation orders, filter out foreign registers from the larger
   // super-class.
   Orders.resize(Super.Orders.size());
   for (unsigned i = 0, ie = Super.Orders.size(); i != ie; ++i)