[llvm-objdump] Print memory operand addresses as regular comments

[ikudrin]

Summary

The patch reuses the common code to print memory operand addresses as instruction comments. This helps to align the comments and enables using target-specific comment markers when evaluateMemoryOperandAddress() is implemented for them.

[MaskRay]

LGTM.

[ikudrin]

• Fixed test failures in lld/test/MachO

[int3]

lgtm

llvm/test/tools/llvm-objdump/X86/disassemble-align.s

 # RUN: llvm-mc -filetype=obj -triple=x86_64 %s -o %t
 
 # Use '|' to show where the tabs line up.
-# RUN: llvm-objdump -d --print-imm-hex %t | tr '\t' '|' | FileCheck --strict-whitespace %s
+# RUN: llvm-objdump -d --print-imm-hex %t | tr '\t' '|' | \
+# RUN:   FileCheck --match-full-lines --strict-whitespace %s
 
 # RUN: llvm-objdump -d --print-imm-hex --no-show-raw-insn %t | tr '\t' '|' | \
-# RUN:   FileCheck -check-prefix=NORAW -strict-whitespace %s
+# RUN:   FileCheck -check-prefix=NORAW --match-full-lines -strict-whitespace %s
 
 # Instructions are expected to be aligned if the instruction in hex is not too long.
 
-# CHECK:       0: c3                           |retq
-# CHECK-NEXT:  1: 48 8b 05 56 34 12 00         |movq|0x123456(%rip), %rax
-# CHECK-NEXT:  8: 48 b8 54 55 55 55 55 55 55 55|movabsq|$0x5555555555555554, %rax
-# CHECK-NEXT: 12: 8f ea 00 12 4c 02 40 00 00 00 00     |lwpval|$0x0, 0x40(%rdx,%rax), %r15d
-# CHECK-NEXT: 1d: 8f ea 00 12 04 25 f0 1c f0 1c 00 00 00 00    |lwpins|$0x0, 0x1cf01cf0, %r15d
-# CHECK-NEXT: 2b: ff ff                        |<unknown>
+#      CHECK:       0: c3                           |retq
+# CHECK-NEXT:       1: 48 8b 05 56 34 12 00         |movq|0x123456(%rip), %rax    # 12345e <.text+0x12345e>
+# CHECK-NEXT:       8: 48 b8 54 55 55 55 55 55 55 55|movabsq|$0x5555555555555554, %rax # imm = 0x5555555555555554
+# CHECK-NEXT:      12: 8f ea 00 12 4c 02 40 00 00 00 00     |lwpval|$0x0, 0x40(%rdx,%rax), %r15d
+# CHECK-NEXT:      1d: 8f ea 00 12 04 25 f0 1c f0 1c 00 00 00 00    |lwpins|$0x0, 0x1cf01cf0, %r15d
+# CHECK-NEXT:      2b: ff ff                        |<unknown>
 
-# NORAW:       0:      |retq
-# NORAW-NEXT:  1:      |movq|0x123456(%rip), %rax
-# NORAW-NEXT:  8:      |movabsq|$0x5555555555555554, %rax
-# NORAW-NEXT: 12:      |lwpval|$0x0, 0x40(%rdx,%rax), %r15d
-# NORAW-NEXT: 1d:      |lwpins|$0x0, 0x1cf01cf0, %r15d
-# NORAW-NEXT: 2b:      |<unknown>
+#      NORAW:       0:      |retq
+# NORAW-NEXT:       1:      |movq|0x123456(%rip), %rax    # 12345e <.text+0x12345e>
+# NORAW-NEXT:       8:      |movabsq|$0x5555555555555554, %rax # imm = 0x5555555555555554
+# NORAW-NEXT:      12:      |lwpval|$0x0, 0x40(%rdx,%rax), %r15d
+# NORAW-NEXT:      1d:      |lwpins|$0x0, 0x1cf01cf0, %r15d
+# NORAW-NEXT:      2b:      |<unknown>
 
 .text
   retq
   movq 0x123456(%rip),%rax
   movabs $0x5555555555555554,%rax
   lwpval $0x0, 0x40(%rdx,%rax), %r15d
   lwpins $0x0, 0x1cf01cf0, %r15d
   .word 0xffff

llvm/tools/llvm-objdump/llvm-objdump.cpp

for (unsigned SI = 0, SE = Symbols.size(); SI != SE; ++SI) {
 
           IP->setCommentStream(llvm::nulls());
 
           // If disassembly has failed, avoid analysing invalid/incomplete
           // instruction information. Otherwise, try to resolve the target
           // address (jump target or memory operand address) and print it on the
           // right of the instruction.
           if (Disassembled && MIA) {
+            // Branch targets are printed just after the instructions.
+            llvm::raw_ostream *TargetOS = &FOS;
             uint64_t Target;
             bool PrintTarget =
                 MIA->evaluateBranch(Inst, SectionAddr + Index, Size, Target);
             if (!PrintTarget)
               if (Optional<uint64_t> MaybeTarget =
                       MIA->evaluateMemoryOperandAddress(
                           Inst, SectionAddr + Index, Size)) {
                 Target = *MaybeTarget;
                 PrintTarget = true;
                 // Do not print real address when symbolizing.
-                if (!SymbolizeOperands)
-                  FOS << "  # " << Twine::utohexstr(Target);
+                if (!SymbolizeOperands) {
+                  // Memory operand addresses are printed as comments.
+                  TargetOS = &CommentStream;
+                  *TargetOS << Twine::utohexstr(Target);
+                }
               }
             if (PrintTarget) {
               // In a relocatable object, the target's section must reside in
               // the same section as the call instruction or it is accessed
               // through a relocation.
               //
               // In a non-relocatable object, the target may be in any section.
               // In that case, locate the section(s) containing the target
for (unsigned SI = 0, SE = Symbols.size(); SI != SE; ++SI) {
               bool LabelAvailable = AllLabels.count(Target);
               if (TargetSym != nullptr) {
                 uint64_t TargetAddress = TargetSym->Addr;
                 uint64_t Disp = Target - TargetAddress;
                 std::string TargetName = TargetSym->Name.str();
                 if (Demangle)
                   TargetName = demangle(TargetName);
 
-                FOS << " <";
+                *TargetOS << " <";
                 if (!Disp) {
                   // Always Print the binary symbol precisely corresponding to
                   // the target address.
-                  FOS << TargetName;
+                  *TargetOS << TargetName;
                 } else if (!LabelAvailable) {
                   // Always Print the binary symbol plus an offset if there's no
                   // local label corresponding to the target address.
-                  FOS << TargetName << "+0x" << Twine::utohexstr(Disp);
+                  *TargetOS << TargetName << "+0x" << Twine::utohexstr(Disp);
                 } else {
-                  FOS << AllLabels[Target];
+                  *TargetOS << AllLabels[Target];
                 }
-                FOS << ">";
+                *TargetOS << ">";
               } else if (LabelAvailable) {
-                FOS << " <" << AllLabels[Target] << ">";
+                *TargetOS << " <" << AllLabels[Target] << ">";
               }
+              // By convention, each record in the comment stream should be
+              // terminated.
+              if (TargetOS == &CommentStream)
+                *TargetOS << "\n";
             }
           }
         }
 
         assert(Ctx.getAsmInfo());
         emitPostInstructionInfo(FOS, *Ctx.getAsmInfo(), *STI,
                                 CommentStream.str(), LVP);
         Comments.clear();