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Differential D104597

[SimplifyCFG] Tail-merging all blocks with `ret` terminator
ClosedPublic

Authored by lebedev.ri on Jun 19 2021, 11:57 AM.

Details

Reviewers
rnk
hans
fhahn
nikic
spatel
dmgreen
Commits
rG9c4c2f24725e: [SimplifyCFG] Tail-merging all blocks with `ret` terminator
Summary

Based ontop of D104598, which is a NFCI-ish refactoring.
Here, a restriction, that only empty blocks can be merged, is lifted.

Diff Detail

Event Timeline

lebedev.ri created this revision.Jun 19 2021, 11:57 AM
Herald added subscribers: ormris, wenlei, zzheng, hiraditya. · View Herald TranscriptJun 19 2021, 11:57 AM
lebedev.ri requested review of this revision.Jun 19 2021, 11:57 AM
lebedev.ri updated this revision to Diff 353211.Jun 19 2021, 2:26 PM
lebedev.ri edited the summary of this revision. (Show Details)

Split off mostly NFC refactor into a separate change.

lebedev.ri added a parent revision: D104598: [NFCI-ish][SimplifyCFGPass] Rework and generalize `ret` block tail-merging.Jun 19 2021, 2:26 PM
lebedev.ri mentioned this in D104445: [SimplifyCFGPass] Tail-merging function-terminating blocks.
lebedev.ri edited the summary of this revision. (Show Details)
Harbormaster completed remote builds in B110076: Diff 353211.Jun 19 2021, 7:10 PM
lebedev.ri mentioned this in rGe497b12a6960: [NFC][AArch64][ARM][Thumb][Hexagon] Autogenerate some tests.Jun 20 2021, 4:13 AM
lebedev.ri updated this revision to Diff 353229.Jun 20 2021, 4:19 AM

Autogenerate more, but still not all, affected codegen tests.

Harbormaster completed remote builds in B110093: Diff 353229.Jun 20 2021, 4:51 AM
xbolva00 added a reviewer: dmgreen.Jun 20 2021, 5:02 AM
rnk added a comment.Jun 22 2021, 3:28 PM

I think this is reasonable: later cfg simplifications will tail merge the preceding instructions and delete dbg.values appropriately. I didn't hit "accept" since the tests don't all pass yet.

llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-condbr-lower-tree.ll
37

This transform has the potential to make it harder to recognize some tail calls during codegen, but it's clear from this test that codegen is already smart enough to handle this case. I don't think any change is needed.

llvm/test/CodeGen/ARM/smml.ll
168

I can't understand why these checks disappeared. Is this a bug in the check generation script?

llvm/test/Transforms/PruneEH/ipo-nounwind.ll
33

Seems like another update bug.

lebedev.ri updated this revision to Diff 353951.Jun 23 2021, 6:42 AM
In D104597#2834705, @rnk wrote:

I think this is reasonable: later cfg simplifications will tail merge the preceding instructions and delete dbg.values appropriately. I didn't hit "accept" since the tests don't all pass yet.

Thank you for taking a look!
This is a much warmer reaction than i was expecting.

Autogenerated a few more tests. Still a few more to go.

lebedev.ri updated this revision to Diff 353962.Jun 23 2021, 7:22 AM
lebedev.ri edited the summary of this revision. (Show Details)

@rnk done, all tests updated.

Harbormaster completed remote builds in B110621: Diff 353962.Jun 23 2021, 8:05 AM
ormris removed a subscriber: ormris.Jun 23 2021, 9:32 AM
dmgreen added a comment.Jun 23 2021, 1:41 PM

Some of the test changes here look really ropy, but the performance benchmarks I tested was entirely flat, and codesize neither improved nor regressed by any significant amount.

There are some tests in here, notably the ifcvt ones, that no longer seem to be testing what they were originally intending to test.

llvm/test/CodeGen/AArch64/arm64-instruction-mix-remarks.ll
26–27

I don't know this test, but what happened to this store?

llvm/test/CodeGen/ARM/smml.ll
66–67

Is this left over?

67

These look like they can share CHECK-V6V7?

rnk added a comment.Jun 23 2021, 1:49 PM

I'm pretty sure Clang generates a single return block, so this change alone probably won't affect any C/C++ benchmarks. Most of the affected tests are manually written IR, where LLVM developers tend to use multiple ret terminators for simplicity.

I believe Clang also uses a single resume block, but I could be wrong.

lebedev.ri updated this revision to Diff 354075.Jun 23 2021, 2:06 PM
lebedev.ri marked 3 inline comments as done.

@dmgreen thank you for taking a look! Tidyed-up the two tests you pointed out, hopefully it's better now.

@rnk do tell if there was something else i was supposed to do here..

dmgreen added a comment.Jun 23 2021, 2:29 PM
In D104597#2837100, @rnk wrote:

I'm pretty sure Clang generates a single return block, so this change alone probably won't affect any C/C++ benchmarks. Most of the affected tests are manually written IR, where LLVM developers tend to use multiple ret terminators for simplicity.

I believe Clang also uses a single resume block, but I could be wrong.

Ah. That would explain the performance being flat. Codesize is different enough to suggest something is changing, but it's not enough of a difference to worry about.

Harbormaster completed remote builds in B110707: Diff 354075.Jun 23 2021, 2:39 PM
rnk accepted this revision.Jun 23 2021, 8:46 PM

lgtm

This revision is now accepted and ready to land.Jun 23 2021, 8:46 PM
fhahn added inline comments.Jun 24 2021, 1:38 AM
llvm/test/CodeGen/AArch64/swifterror.ll
429

I noticed you auto-generated the tests for this file and the GlobalISel version. It looks like those tests intentionally only checked the relevant parts related to swifterror, but now the checks are much more verbose (and much more prone to needing updating, because they check lots of 'uninteresting things).

Given that only a few lines out of ~2000 needed updating, I am wondering if it would be better to keep the hand-written checks and just update the failing line? Going forward, I think the auto-generated ones will need updating much more frequently now. Granted it is easy to update them, but it still creates noise in diffs and in theory would require careful checking.

fhahn added inline comments.Jun 24 2021, 1:42 AM
llvm/test/CodeGen/AArch64/swifterror.ll
429

(The original checks also had comments interleaved to explain what is being checked. It looks like they are now all before the auto-generated check lines)

lebedev.ri updated this revision to Diff 354187.Jun 24 2021, 3:10 AM
lebedev.ri marked 2 inline comments as done.

@rnk thank you for the review!

Address nit from @fhahn.

Harbormaster completed remote builds in B110784: Diff 354187.Jun 24 2021, 3:10 AM
This revision was landed with ongoing or failed builds.Jun 24 2021, 3:20 AM
Closed by commit rG9c4c2f24725e: [SimplifyCFG] Tail-merging all blocks with `ret` terminator (authored by lebedev.ri). · Explain Why
This revision was automatically updated to reflect the committed changes.
lebedev.ri mentioned this in rGcba4b104a9c1: [NFC][AArch64] Un-autogenerate swifterror.ll tests.
lebedev.ri added a commit: rG9c4c2f24725e: [SimplifyCFG] Tail-merging all blocks with `ret` terminator.
fhahn added a comment.Jun 25 2021, 2:28 AM

Great, thanks!

jgorbe added a subscriber: jgorbe.Jul 20 2021, 5:20 PM

Revision Contents

PathSize
llvm/
lib/
Transforms/
Scalar/
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test/
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AArch64/
GlobalISel/
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ARM/
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Hexagon/
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Transforms/
LoopUnroll/
ARM/
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PGOProfile/
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PhaseOrdering/
X86/
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PruneEH/
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SimplifyCFG/
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Hexagon/
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Diff 354075

llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp

Show First 20 Lines • Show All 114 Lines • ▼ Show 20 Lines for (BasicBlock &BB : F) {
} }
// PHI nodes cannot have token type, so if the terminator has an operand // PHI nodes cannot have token type, so if the terminator has an operand
// with token type, we can not tail-merge this kind of function terminators. // with token type, we can not tail-merge this kind of function terminators.
if (any_of(Term->operands(), if (any_of(Term->operands(),
[](Value *Op) { return Op->getType()->isTokenTy(); })) [](Value *Op) { return Op->getType()->isTokenTy(); }))
continue; continue;
// Only look at the block if it is empty or the only other thing in it is a
// single PHI node that is the operand to the return.
// FIXME: lift this restriction.
if (Term != &BB.front()) {
// Check for something else in the block.
BasicBlock::iterator I(Term);
--I;
// Skip over debug info.
while (isa<DbgInfoIntrinsic>(I) && I != BB.begin())
--I;
if (!isa<DbgInfoIntrinsic>(I) &&
(!isa<PHINode>(I) || I != BB.begin() || Term->getNumOperands() == 0 ||
Term->getOperand(0) != &*I))
continue;
}
// Canonical blocks are uniqued based on the terminator type (opcode). // Canonical blocks are uniqued based on the terminator type (opcode).
Structure[Term->getOpcode()].emplace_back(&BB); Structure[Term->getOpcode()].emplace_back(&BB);
} }
bool Changed = false; bool Changed = false;
std::vector<DominatorTree::UpdateType> Updates; std::vector<DominatorTree::UpdateType> Updates;
▲ Show 20 Lines • Show All 268 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-condbr-lower-tree.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple aarch64 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s ; RUN: llc -mtriple aarch64 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
declare i32 @bar(...) declare i32 @bar(...)
define void @or_cond(i32 %X, i32 %Y, i32 %Z) nounwind { define void @or_cond(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: or_cond ; CHECK-LABEL: name: or_cond
; CHECK: bb.1.entry: ; CHECK: bb.1.entry:
; CHECK: successors: %bb.2(0x20000000), %bb.4(0x60000000) ; CHECK: successors: %bb.3(0x20000000), %bb.4(0x60000000)
; CHECK: liveins: $w0, $w1, $w2 ; CHECK: liveins: $w0, $w1, $w2
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]] ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]]
; CHECK: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP1]], [[ICMP]] ; CHECK: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP1]], [[ICMP]]
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]] ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]]
; CHECK: G_BRCOND [[ICMP2]](s1), %bb.2 ; CHECK: G_BRCOND [[ICMP2]](s1), %bb.3
; CHECK: G_BR %bb.4 ; CHECK: G_BR %bb.4
; CHECK: bb.4.entry: ; CHECK: bb.4.entry:
; CHECK: successors: %bb.2(0x2aaaaaab), %bb.3(0x55555555) ; CHECK: successors: %bb.3(0x2aaaaaab), %bb.2(0x55555555)
; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; CHECK: G_BRCOND [[ICMP3]](s1), %bb.2 ; CHECK: G_BRCOND [[ICMP3]](s1), %bb.3
; CHECK: G_BR %bb.3 ; CHECK: G_BR %bb.2
; CHECK: bb.2.cond_true: ; CHECK: bb.2.common.ret:
; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
; CHECK: bb.3.UnifiedReturnBlock:
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
; CHECK: bb.3.cond_true:
; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
entry: entry:
%tmp1 = icmp eq i32 %X, 0 %tmp1 = icmp eq i32 %X, 0
%tmp3 = icmp slt i32 %Y, 5 %tmp3 = icmp slt i32 %Y, 5
%tmp4 = or i1 %tmp3, %tmp1 %tmp4 = or i1 %tmp3, %tmp1
br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock
cond_true: cond_true:
%tmp5 = tail call i32 (...) @bar( ) %tmp5 = tail call i32 (...) @bar( )
rnkUnsubmitted
Not Done
ReplyInline Actions

This transform has the potential to make it harder to recognize some tail calls during codegen, but it's clear from this test that codegen is already smart enough to handle this case. I don't think any change is needed.

rnk: This transform has the potential to make it harder to recognize some tail calls during codegen…
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
define void @or_cond_select(i32 %X, i32 %Y, i32 %Z) nounwind { define void @or_cond_select(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: or_cond_select ; CHECK-LABEL: name: or_cond_select
; CHECK: bb.1.entry: ; CHECK: bb.1.entry:
; CHECK: successors: %bb.2(0x20000000), %bb.4(0x60000000) ; CHECK: successors: %bb.3(0x20000000), %bb.4(0x60000000)
; CHECK: liveins: $w0, $w1, $w2 ; CHECK: liveins: $w0, $w1, $w2
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true ; CHECK: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]] ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]]
; CHECK: [[SELECT:%[0-9]+]]:_(s1) = G_SELECT [[ICMP1]](s1), [[C2]], [[ICMP]] ; CHECK: [[SELECT:%[0-9]+]]:_(s1) = G_SELECT [[ICMP1]](s1), [[C2]], [[ICMP]]
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]] ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]]
; CHECK: G_BRCOND [[ICMP2]](s1), %bb.2 ; CHECK: G_BRCOND [[ICMP2]](s1), %bb.3
; CHECK: G_BR %bb.4 ; CHECK: G_BR %bb.4
; CHECK: bb.4.entry: ; CHECK: bb.4.entry:
; CHECK: successors: %bb.2(0x2aaaaaab), %bb.3(0x55555555) ; CHECK: successors: %bb.3(0x2aaaaaab), %bb.2(0x55555555)
; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; CHECK: G_BRCOND [[ICMP3]](s1), %bb.2 ; CHECK: G_BRCOND [[ICMP3]](s1), %bb.3
; CHECK: G_BR %bb.3 ; CHECK: G_BR %bb.2
; CHECK: bb.2.cond_true: ; CHECK: bb.2.common.ret:
; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
; CHECK: bb.3.UnifiedReturnBlock:
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
; CHECK: bb.3.cond_true:
; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
entry: entry:
%tmp1 = icmp eq i32 %X, 0 %tmp1 = icmp eq i32 %X, 0
%tmp3 = icmp slt i32 %Y, 5 %tmp3 = icmp slt i32 %Y, 5
%tmp4 = select i1 %tmp3, i1 true, i1 %tmp1 %tmp4 = select i1 %tmp3, i1 true, i1 %tmp1
br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock
cond_true: cond_true:
%tmp5 = tail call i32 (...) @bar( ) %tmp5 = tail call i32 (...) @bar( )
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
define void @and_cond(i32 %X, i32 %Y, i32 %Z) nounwind { define void @and_cond(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: and_cond ; CHECK-LABEL: name: and_cond
; CHECK: bb.1.entry: ; CHECK: bb.1.entry:
; CHECK: successors: %bb.4(0x60000000), %bb.3(0x20000000) ; CHECK: successors: %bb.4(0x60000000), %bb.2(0x20000000)
; CHECK: liveins: $w0, $w1, $w2 ; CHECK: liveins: $w0, $w1, $w2
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]] ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]]
; CHECK: [[AND:%[0-9]+]]:_(s1) = G_AND [[ICMP1]], [[ICMP]] ; CHECK: [[AND:%[0-9]+]]:_(s1) = G_AND [[ICMP1]], [[ICMP]]
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]] ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]]
; CHECK: G_BRCOND [[ICMP2]](s1), %bb.4 ; CHECK: G_BRCOND [[ICMP2]](s1), %bb.4
; CHECK: G_BR %bb.3 ; CHECK: G_BR %bb.2
; CHECK: bb.4.entry: ; CHECK: bb.4.entry:
; CHECK: successors: %bb.2(0x55555555), %bb.3(0x2aaaaaab) ; CHECK: successors: %bb.3(0x55555555), %bb.2(0x2aaaaaab)
; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; CHECK: G_BRCOND [[ICMP3]](s1), %bb.2 ; CHECK: G_BRCOND [[ICMP3]](s1), %bb.3
; CHECK: G_BR %bb.3 ; CHECK: G_BR %bb.2
; CHECK: bb.2.cond_true: ; CHECK: bb.2.common.ret:
; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
; CHECK: bb.3.UnifiedReturnBlock:
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
; CHECK: bb.3.cond_true:
; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
entry: entry:
%tmp1 = icmp eq i32 %X, 0 %tmp1 = icmp eq i32 %X, 0
%tmp3 = icmp slt i32 %Y, 5 %tmp3 = icmp slt i32 %Y, 5
%tmp4 = and i1 %tmp3, %tmp1 %tmp4 = and i1 %tmp3, %tmp1
br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock
cond_true: cond_true:
%tmp5 = tail call i32 (...) @bar( ) %tmp5 = tail call i32 (...) @bar( )
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
define void @and_cond_select(i32 %X, i32 %Y, i32 %Z) nounwind { define void @and_cond_select(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: and_cond_select ; CHECK-LABEL: name: and_cond_select
; CHECK: bb.1.entry: ; CHECK: bb.1.entry:
; CHECK: successors: %bb.4(0x60000000), %bb.3(0x20000000) ; CHECK: successors: %bb.4(0x60000000), %bb.2(0x20000000)
; CHECK: liveins: $w0, $w1, $w2 ; CHECK: liveins: $w0, $w1, $w2
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 false ; CHECK: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]] ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]]
; CHECK: [[SELECT:%[0-9]+]]:_(s1) = G_SELECT [[ICMP1]](s1), [[ICMP]], [[C2]] ; CHECK: [[SELECT:%[0-9]+]]:_(s1) = G_SELECT [[ICMP1]](s1), [[ICMP]], [[C2]]
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]] ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]]
; CHECK: G_BRCOND [[ICMP2]](s1), %bb.4 ; CHECK: G_BRCOND [[ICMP2]](s1), %bb.4
; CHECK: G_BR %bb.3 ; CHECK: G_BR %bb.2
; CHECK: bb.4.entry: ; CHECK: bb.4.entry:
; CHECK: successors: %bb.2(0x55555555), %bb.3(0x2aaaaaab) ; CHECK: successors: %bb.3(0x55555555), %bb.2(0x2aaaaaab)
; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; CHECK: G_BRCOND [[ICMP3]](s1), %bb.2 ; CHECK: G_BRCOND [[ICMP3]](s1), %bb.3
; CHECK: G_BR %bb.3 ; CHECK: G_BR %bb.2
; CHECK: bb.2.cond_true: ; CHECK: bb.2.common.ret:
; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
; CHECK: bb.3.UnifiedReturnBlock:
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
; CHECK: bb.3.cond_true:
; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
entry: entry:
%tmp1 = icmp eq i32 %X, 0 %tmp1 = icmp eq i32 %X, 0
%tmp3 = icmp slt i32 %Y, 5 %tmp3 = icmp slt i32 %Y, 5
%tmp4 = select i1 %tmp3, i1 %tmp1, i1 false %tmp4 = select i1 %tmp3, i1 %tmp1, i1 false
br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock
cond_true: cond_true:
%tmp5 = tail call i32 (...) @bar( ) %tmp5 = tail call i32 (...) @bar( )
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
; Don't emit two branches for same operands. ; Don't emit two branches for same operands.
define void @or_cond_same_values_cmp(i32 %X, i32 %Y, i32 %Z) nounwind { define void @or_cond_same_values_cmp(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: or_cond_same_values_cmp ; CHECK-LABEL: name: or_cond_same_values_cmp
; CHECK: bb.1.entry: ; CHECK: bb.1.entry:
; CHECK: successors: %bb.2(0x40000000), %bb.3(0x40000000) ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK: liveins: $w0, $w1, $w2 ; CHECK: liveins: $w0, $w1, $w2
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY]](s32), [[C]] ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY]](s32), [[C]]
; CHECK: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP1]], [[ICMP]] ; CHECK: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP1]], [[ICMP]]
; CHECK: G_BRCOND [[OR]](s1), %bb.2 ; CHECK: G_BRCOND [[OR]](s1), %bb.3
; CHECK: G_BR %bb.3 ; CHECK: G_BR %bb.2
; CHECK: bb.2.cond_true: ; CHECK: bb.2.common.ret:
; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
; CHECK: bb.3.UnifiedReturnBlock:
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
; CHECK: bb.3.cond_true:
; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
entry: entry:
%tmp1 = icmp eq i32 %X, 5 %tmp1 = icmp eq i32 %X, 5
%tmp3 = icmp slt i32 %X, 5 %tmp3 = icmp slt i32 %X, 5
%tmp4 = or i1 %tmp3, %tmp1 %tmp4 = or i1 %tmp3, %tmp1
br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock
cond_true: cond_true:
%tmp5 = tail call i32 (...) @bar( ) %tmp5 = tail call i32 (...) @bar( )
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
; Emit multiple branches for more than 2 cases. ; Emit multiple branches for more than 2 cases.
define void @or_cond_multiple_cases(i32 %X, i32 %Y, i32 %Z) nounwind { define void @or_cond_multiple_cases(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: or_cond_multiple_cases ; CHECK-LABEL: name: or_cond_multiple_cases
; CHECK: bb.1.entry: ; CHECK: bb.1.entry:
; CHECK: successors: %bb.2(0x10000000), %bb.5(0x70000000) ; CHECK: successors: %bb.3(0x10000000), %bb.5(0x70000000)
; CHECK: liveins: $w0, $w1, $w2 ; CHECK: liveins: $w0, $w1, $w2
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY]](s32), [[C]] ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY]](s32), [[C]]
; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] ; CHECK: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; CHECK: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP1]], [[ICMP]] ; CHECK: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP1]], [[ICMP]]
; CHECK: [[OR1:%[0-9]+]]:_(s1) = G_OR [[OR]], [[ICMP2]] ; CHECK: [[OR1:%[0-9]+]]:_(s1) = G_OR [[OR]], [[ICMP2]]
; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY]](s32), [[C]] ; CHECK: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY]](s32), [[C]]
; CHECK: G_BRCOND [[ICMP3]](s1), %bb.2 ; CHECK: G_BRCOND [[ICMP3]](s1), %bb.3
; CHECK: G_BR %bb.5 ; CHECK: G_BR %bb.5
; CHECK: bb.5.entry: ; CHECK: bb.5.entry:
; CHECK: successors: %bb.2(0x12492492), %bb.4(0x6db6db6e) ; CHECK: successors: %bb.3(0x12492492), %bb.4(0x6db6db6e)
; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] ; CHECK: [[ICMP4:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; CHECK: G_BRCOND [[ICMP4]](s1), %bb.2 ; CHECK: G_BRCOND [[ICMP4]](s1), %bb.3
; CHECK: G_BR %bb.4 ; CHECK: G_BR %bb.4
; CHECK: bb.4.entry: ; CHECK: bb.4.entry:
; CHECK: successors: %bb.2(0x2aaaaaab), %bb.3(0x55555555) ; CHECK: successors: %bb.3(0x2aaaaaab), %bb.2(0x55555555)
; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]] ; CHECK: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
; CHECK: G_BRCOND [[ICMP5]](s1), %bb.2 ; CHECK: G_BRCOND [[ICMP5]](s1), %bb.3
; CHECK: G_BR %bb.3 ; CHECK: G_BR %bb.2
; CHECK: bb.2.cond_true: ; CHECK: bb.2.common.ret:
; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
; CHECK: bb.3.UnifiedReturnBlock:
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
; CHECK: bb.3.cond_true:
; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
entry: entry:
%tmp1 = icmp eq i32 %X, 5 %tmp1 = icmp eq i32 %X, 5
%tmp3 = icmp slt i32 %X, 5 %tmp3 = icmp slt i32 %X, 5
%tmpZ = icmp eq i32 %Z, 5 %tmpZ = icmp eq i32 %Z, 5
%tmp4 = or i1 %tmp3, %tmp1 %tmp4 = or i1 %tmp3, %tmp1
%final = or i1 %tmp4, %tmpZ %final = or i1 %tmp4, %tmpZ
br i1 %final, label %cond_true, label %UnifiedReturnBlock br i1 %final, label %cond_true, label %UnifiedReturnBlock
cond_true: cond_true:
%tmp5 = tail call i32 (...) @bar( ) %tmp5 = tail call i32 (...) @bar( )
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
; (X != null) | (Y != null) --> (X|Y) != 0 ; (X != null) | (Y != null) --> (X|Y) != 0
; Don't emit two branches. ; Don't emit two branches.
define void @or_cond_ne_null(i32 %X, i32 %Y, i32 %Z) nounwind { define void @or_cond_ne_null(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: or_cond_ne_null ; CHECK-LABEL: name: or_cond_ne_null
; CHECK: bb.1.entry: ; CHECK: bb.1.entry:
; CHECK: successors: %bb.2(0x40000000), %bb.3(0x40000000) ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK: liveins: $w0, $w1, $w2 ; CHECK: liveins: $w0, $w1, $w2
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]] ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
; CHECK: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP1]], [[ICMP]] ; CHECK: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP1]], [[ICMP]]
; CHECK: G_BRCOND [[OR]](s1), %bb.2 ; CHECK: G_BRCOND [[OR]](s1), %bb.3
; CHECK: G_BR %bb.3 ; CHECK: G_BR %bb.2
; CHECK: bb.2.cond_true: ; CHECK: bb.2.common.ret:
; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
; CHECK: bb.3.UnifiedReturnBlock:
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
; CHECK: bb.3.cond_true:
; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
entry: entry:
%tmp1 = icmp ne i32 %X, 0 %tmp1 = icmp ne i32 %X, 0
%tmp3 = icmp ne i32 %Y, 0 %tmp3 = icmp ne i32 %Y, 0
%tmp4 = or i1 %tmp3, %tmp1 %tmp4 = or i1 %tmp3, %tmp1
br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock
cond_true: cond_true:
%tmp5 = tail call i32 (...) @bar( ) %tmp5 = tail call i32 (...) @bar( )
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
; If the branch is unpredictable, don't add another branch ; If the branch is unpredictable, don't add another branch
; regardless of whether they are expensive or not. ; regardless of whether they are expensive or not.
define void @unpredictable(i32 %X, i32 %Y, i32 %Z) nounwind { define void @unpredictable(i32 %X, i32 %Y, i32 %Z) nounwind {
; CHECK-LABEL: name: unpredictable ; CHECK-LABEL: name: unpredictable
; CHECK: bb.1.entry: ; CHECK: bb.1.entry:
; CHECK: successors: %bb.2(0x40000000), %bb.3(0x40000000) ; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)
; CHECK: liveins: $w0, $w1, $w2 ; CHECK: liveins: $w0, $w1, $w2
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2 ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]] ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]] ; CHECK: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[COPY1]](s32), [[C1]]
; CHECK: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP1]], [[ICMP]] ; CHECK: [[OR:%[0-9]+]]:_(s1) = G_OR [[ICMP1]], [[ICMP]]
; CHECK: G_BRCOND [[OR]](s1), %bb.2 ; CHECK: G_BRCOND [[OR]](s1), %bb.3
; CHECK: G_BR %bb.3 ; CHECK: G_BR %bb.2
; CHECK: bb.2.cond_true: ; CHECK: bb.2.common.ret:
; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
; CHECK: bb.3.UnifiedReturnBlock:
; CHECK: RET_ReallyLR ; CHECK: RET_ReallyLR
; CHECK: bb.3.cond_true:
; CHECK: TCRETURNdi @bar, 0, csr_aarch64_aapcs, implicit $sp
entry: entry:
%tmp1 = icmp eq i32 %X, 0 %tmp1 = icmp eq i32 %X, 0
%tmp3 = icmp slt i32 %Y, 5 %tmp3 = icmp slt i32 %Y, 5
%tmp4 = or i1 %tmp3, %tmp1 %tmp4 = or i1 %tmp3, %tmp1
br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock, !unpredictable !0 br i1 %tmp4, label %cond_true, label %UnifiedReturnBlock, !unpredictable !0
cond_true: cond_true:
%tmp5 = tail call i32 (...) @bar( ) %tmp5 = tail call i32 (...) @bar( )
ret void ret void
UnifiedReturnBlock: UnifiedReturnBlock:
ret void ret void
} }
!0 = !{} !0 = !{}

llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll

Show First 20 Lines • Show All 145 Lines • ▼ Show 20 Lineshandler:
ret float 1.0 ret float 1.0
} }
; "foo_if" is a function that takes a swifterror parameter, it sets swifterror ; "foo_if" is a function that takes a swifterror parameter, it sets swifterror
; under a certain condition. ; under a certain condition.
define float @foo_if(%swift_error** swifterror %error_ptr_ref, i32 %cc) { define float @foo_if(%swift_error** swifterror %error_ptr_ref, i32 %cc) {
; CHECK-LABEL: foo_if: ; CHECK-LABEL: foo_if:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: cbz w0, LBB3_2 ; CHECK-NEXT: str d8, [sp, #-32]! ; 8-byte Folded Spill
; CHECK-NEXT: ; %bb.1: ; %gen_error ; CHECK-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill ; CHECK-NEXT: add x29, sp, #16 ; =16
; CHECK-NEXT: mov x29, sp
; CHECK-NEXT: .cfi_def_cfa w29, 16 ; CHECK-NEXT: .cfi_def_cfa w29, 16
; CHECK-NEXT: .cfi_offset w30, -8 ; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: .cfi_offset b8, -32
; CHECK-NEXT: cbz w0, LBB3_2
; CHECK-NEXT: ; %bb.1: ; %gen_error
; CHECK-NEXT: fmov s8, #1.00000000
; CHECK-NEXT: mov w0, #16 ; CHECK-NEXT: mov w0, #16
; CHECK-NEXT: bl _malloc ; CHECK-NEXT: bl _malloc
; CHECK-NEXT: mov x21, x0
; CHECK-NEXT: mov w8, #1 ; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: fmov s0, #1.00000000
; CHECK-NEXT: strb w8, [x0, #8] ; CHECK-NEXT: strb w8, [x0, #8]
; CHECK-NEXT: mov x21, x0 ; CHECK-NEXT: b LBB3_3
; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload ; CHECK-NEXT: LBB3_2:
; CHECK-NEXT: ret ; CHECK-NEXT: movi d8, #0000000000000000
; CHECK-NEXT: LBB3_2: ; %normal ; CHECK-NEXT: LBB3_3: ; %common.ret
; CHECK-NEXT: movi d0, #0000000000000000 ; CHECK-NEXT: mov.16b v0, v8
; CHECK-NEXT: ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
; CHECK-NEXT: ldr d8, [sp], #32 ; 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%cond = icmp ne i32 %cc, 0 %cond = icmp ne i32 %cc, 0
br i1 %cond, label %gen_error, label %normal br i1 %cond, label %gen_error, label %normal
gen_error: gen_error:
%call = call i8* @malloc(i64 16) %call = call i8* @malloc(i64 16)
%call.0 = bitcast i8* %call to %swift_error* %call.0 = bitcast i8* %call to %swift_error*
▲ Show 20 Lines • Show All 699 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/addsub.ll

Show First 20 Lines • Show All 171 Lines • ▼ Show 20 Lines
; CHECK-NEXT: b.lt .LBB5_6 ; CHECK-NEXT: b.lt .LBB5_6
; CHECK-NEXT: // %bb.3: // %test4 ; CHECK-NEXT: // %bb.3: // %test4
; CHECK-NEXT: add w11, w9, #3 // =3 ; CHECK-NEXT: add w11, w9, #3 // =3
; CHECK-NEXT: cmp w10, #321 // =321 ; CHECK-NEXT: cmp w10, #321 // =321
; CHECK-NEXT: str w11, [x8] ; CHECK-NEXT: str w11, [x8]
; CHECK-NEXT: b.gt .LBB5_6 ; CHECK-NEXT: b.gt .LBB5_6
; CHECK-NEXT: // %bb.4: // %test5 ; CHECK-NEXT: // %bb.4: // %test5
; CHECK-NEXT: add w11, w9, #4 // =4 ; CHECK-NEXT: add w11, w9, #4 // =4
; CHECK-NEXT: cmn w10, #444 // =444 ; CHECK-NEXT: cmn w10, #443 // =443
; CHECK-NEXT: str w11, [x8] ; CHECK-NEXT: str w11, [x8]
; CHECK-NEXT: b.gt .LBB5_6 ; CHECK-NEXT: b.ge .LBB5_6
; CHECK-NEXT: // %bb.5: // %test6 ; CHECK-NEXT: // %bb.5: // %test6
; CHECK-NEXT: add w9, w9, #5 // =5 ; CHECK-NEXT: add w9, w9, #5 // =5
; CHECK-NEXT: str w9, [x8] ; CHECK-NEXT: str w9, [x8]
; CHECK-NEXT: .LBB5_6: // %ret ; CHECK-NEXT: .LBB5_6: // %common.ret
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%val = load i32, i32* @var_i32 %val = load i32, i32* @var_i32
%val2 = load i32, i32* @var2_i32 %val2 = load i32, i32* @var2_i32
%cmp_pos_small = icmp ne i32 %val, 4095 %cmp_pos_small = icmp ne i32 %val, 4095
br i1 %cmp_pos_small, label %ret, label %test2 br i1 %cmp_pos_small, label %ret, label %test2
test2: test2:
Show All 32 Lines

llvm/test/CodeGen/AArch64/arm64-instruction-mix-remarks.ll

Show All 11 Lines
; YAML: - INST_add: '2' ; YAML: - INST_add: '2'
; YAML: - INST_b.: '1' ; YAML: - INST_b.: '1'
; YAML: - INST_ldr: '1' ; YAML: - INST_ldr: '1'
; YAML: - INST_movk: '1' ; YAML: - INST_movk: '1'
; YAML: - INST_movz: '1' ; YAML: - INST_movz: '1'
; YAML: - INST_subs: '1' ; YAML: - INST_subs: '1'
; YAML: Name: InstructionMix ; YAML: Name: InstructionMix
; YAML-NEXT: DebugLoc: { File: arm64-instruction-mix-remarks.ll, Line: 20, Column: 20 }
; YAML-NEXT: Function: foo
; YAML-NEXT: Args:
; YAML: - BasicBlock: then
; YAML: - INST_orr: '1'
; YAML: - INST_ret: '1'
; YAML: Name: InstructionMix
dmgreenUnsubmitted
Done
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I don't know this test, but what happened to this store?

dmgreen: I don't know this test, but what happened to this store?
; YAML-NEXT: DebugLoc: { File: arm64-instruction-mix-remarks.ll, Line: 30, Column: 30 } ; YAML-NEXT: DebugLoc: { File: arm64-instruction-mix-remarks.ll, Line: 30, Column: 30 }
; YAML-NEXT: Function: foo ; YAML-NEXT: Function: foo
; YAML-NEXT: Args: ; YAML-NEXT: Args:
; YAML: - BasicBlock: else ; YAML: - BasicBlock: else
; YAML: - INST_madd: '2' ; YAML: - INST_madd: '2'
; YAML: - INST_orr: '1' ; YAML: - INST_movz: '1'
; YAML: - INST_ret: '1'
; YAML: - INST_str: '1' ; YAML: - INST_str: '1'
define i32 @foo(i32* %ptr, i32 %x, i64 %y) !dbg !3 { define i32 @foo(i32* %ptr, i32 %x, i64 %y) !dbg !3 {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: ldr w8, [x0] ; CHECK-NEXT: ldr w9, [x0]
; CHECK-NEXT: mov x8, x0
; CHECK-NEXT: mov w10, #16959 ; CHECK-NEXT: mov w10, #16959
; CHECK-NEXT: movk w10, #15, lsl #16 ; CHECK-NEXT: movk w10, #15, lsl #16
; CHECK-NEXT: add w8, w8, w1 ; CHECK-NEXT: add w0, w9, w1
; CHECK-NEXT: add x9, x8, x2 ; CHECK-NEXT: add x9, x0, x2
; CHECK-NEXT: cmp x9, x10 ; CHECK-NEXT: cmp x9, x10
; CHECK-NEXT: b.ne LBB0_2 ; CHECK-NEXT: b.eq LBB0_2
; CHECK-NEXT: ; %bb.1: ; %then ; CHECK-NEXT: ; %bb.1: ; %else
; CHECK-NEXT: mov w0, w8 ; CHECK-NEXT: mul w10, w0, w1
; CHECK-NEXT: ret
; CHECK-NEXT: LBB0_2: ; %else
; CHECK-NEXT: mul w8, w8, w1
; CHECK-NEXT: mov w9, #10 ; CHECK-NEXT: mov w9, #10
; CHECK-NEXT: mul w8, w8, w1 ; CHECK-NEXT: mul w0, w10, w1
; CHECK-NEXT: str w9, [x0] ; CHECK-NEXT: str w9, [x8]
; CHECK-NEXT: mov w0, w8 ; CHECK-NEXT: LBB0_2: ; %common.ret
; CHECK-NEXT: ; kill: def $w0 killed $w0 killed $x0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%l = load i32, i32* %ptr, !dbg !4 %l = load i32, i32* %ptr, !dbg !4
%add = add i32 %l, %x, !dbg !4 %add = add i32 %l, %x, !dbg !4
%add.ext = zext i32 %add to i64, !dbg !4 %add.ext = zext i32 %add to i64, !dbg !4
%add.64 = add i64 %add.ext, %y, !dbg !4 %add.64 = add i64 %add.ext, %y, !dbg !4
%c = icmp eq i64 %add.64, 999999, !dbg !4 %c = icmp eq i64 %add.64, 999999, !dbg !4
br i1 %c, label %then, label %else, !dbg !4 br i1 %c, label %then, label %else, !dbg !4
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llvm/test/CodeGen/AArch64/branch-relax-alignment.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-apple-darwin -aarch64-bcc-offset-bits=4 -align-all-nofallthru-blocks=4 < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-apple-darwin -aarch64-bcc-offset-bits=4 -align-all-nofallthru-blocks=4 < %s | FileCheck %s
; Long branch is assumed because the block has a higher alignment ; Long branch is assumed because the block has a higher alignment
; requirement than the function. ; requirement than the function.
define i32 @invert_bcc_block_align_higher_func(i32 %x, i32 %y) align 4 #0 { define i32 @invert_bcc_block_align_higher_func(i32 %x, i32 %y) align 4 #0 {
; CHECK-LABEL: invert_bcc_block_align_higher_func: ; CHECK-LABEL: invert_bcc_block_align_higher_func:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0: ; %common.ret
; CHECK-NEXT: cmp w0, w1 ; CHECK-NEXT: cmp w0, w1
; CHECK-NEXT: b.eq LBB0_1
; CHECK-NEXT: b LBB0_2
; CHECK-NEXT: LBB0_1: ; %bb1
; CHECK-NEXT: mov w8, #42
; CHECK-NEXT: mov w0, wzr
; CHECK-NEXT: str w8, [x8]
; CHECK-NEXT: ret
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: LBB0_2: ; %bb2
; CHECK-NEXT: mov w8, #9 ; CHECK-NEXT: mov w8, #9
; CHECK-NEXT: mov w0, #1 ; CHECK-NEXT: mov w9, #42
; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: csel w8, w9, w8, eq
; CHECK-NEXT: str w8, [x8] ; CHECK-NEXT: str w8, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = icmp eq i32 %x, %y %1 = icmp eq i32 %x, %y
br i1 %1, label %bb1, label %bb2 br i1 %1, label %bb1, label %bb2
bb2: bb2:
store volatile i32 9, i32* undef store volatile i32 9, i32* undef
ret i32 1 ret i32 1
bb1: bb1:
store volatile i32 42, i32* undef store volatile i32 42, i32* undef
ret i32 0 ret i32 0
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/test/CodeGen/AArch64/branch-relax-asm.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-apple-ios7.0 -disable-block-placement -aarch64-tbz-offset-bits=4 -o - %s | FileCheck %s ; RUN: llc -mtriple=aarch64-apple-ios7.0 -disable-block-placement -aarch64-tbz-offset-bits=4 -o - %s | FileCheck %s
define i32 @test_asm_length(i32 %in) { define i32 @test_asm_length(i32 %in) {
; It would be more natural to use just one "tbnz %false" here, but if the ; It would be more natural to use just one "tbnz %false" here, but if the
; number of instructions in the asm is counted reasonably, that block is out ; number of instructions in the asm is counted reasonably, that block is out
; of the limited range we gave tbz. So branch relaxation has to invert the ; of the limited range we gave tbz. So branch relaxation has to invert the
; condition. ; condition.
; CHECK-LABEL: test_asm_length: ; CHECK-LABEL: test_asm_length:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: tbz w0, #0, LBB0_1 ; CHECK-NEXT: tbz w0, #0, LBB0_2
; CHECK-NEXT: b LBB0_2 ; CHECK-NEXT: ; %bb.1:
; CHECK-NEXT: LBB0_1: ; %true ; CHECK-NEXT: mov w0, wzr
; CHECK-NEXT: ret
; CHECK-NEXT: LBB0_2: ; %true
; CHECK-NEXT: mov w0, #4 ; CHECK-NEXT: mov w0, #4
; CHECK-NEXT: ; InlineAsm Start ; CHECK-NEXT: ; InlineAsm Start
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: ; InlineAsm End ; CHECK-NEXT: ; InlineAsm End
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: LBB0_2: ; %false
; CHECK-NEXT: mov w0, wzr
; CHECK-NEXT: ret
%val = and i32 %in, 1 %val = and i32 %in, 1
%tst = icmp eq i32 %val, 0 %tst = icmp eq i32 %val, 0
br i1 %tst, label %true, label %false br i1 %tst, label %true, label %false
true: true:
call void asm sideeffect "nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop", ""() call void asm sideeffect "nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop\0A\09nop", ""()
ret i32 4 ret i32 4
false: false:
ret i32 0 ret i32 0
} }

llvm/test/CodeGen/AArch64/branch-relax-bcc.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-apple-darwin -aarch64-bcc-offset-bits=3 < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-apple-darwin -aarch64-bcc-offset-bits=3 < %s | FileCheck %s
define i32 @invert_bcc(float %x, float %y) #0 { define i32 @invert_bcc(float %x, float %y) #0 {
; CHECK-LABEL: invert_bcc: ; CHECK-LABEL: invert_bcc:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: mov w0, wzr
; CHECK-NEXT: fcmp s0, s1 ; CHECK-NEXT: fcmp s0, s1
; CHECK-NEXT: b.ne LBB0_3 ; CHECK-NEXT: mov w8, #42
; CHECK-NEXT: b.pl LBB0_3
; CHECK-NEXT: b LBB0_2 ; CHECK-NEXT: b LBB0_2
; CHECK-NEXT: LBB0_3: ; CHECK-NEXT: LBB0_3:
; CHECK-NEXT: b.vc LBB0_1 ; CHECK-NEXT: b.gt LBB0_2
; CHECK-NEXT: b LBB0_2 ; CHECK-NEXT: ; %bb.1: ; %common.ret
; CHECK-NEXT: LBB0_1: ; %bb2 ; CHECK-NEXT: str w8, [x8]
; CHECK-NEXT: mov w8, #9 ; CHECK-NEXT: ret
; CHECK-NEXT: LBB0_2: ; %bb2
; CHECK-NEXT: mov w0, #1 ; CHECK-NEXT: mov w0, #1
; CHECK-NEXT: mov w8, #9
; CHECK-NEXT: ; InlineAsm Start ; CHECK-NEXT: ; InlineAsm Start
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: ; InlineAsm End ; CHECK-NEXT: ; InlineAsm End
; CHECK-NEXT: str w8, [x8] ; CHECK-NEXT: str w8, [x8]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: LBB0_2: ; %bb1
; CHECK-NEXT: mov w8, #42
; CHECK-NEXT: mov w0, wzr
; CHECK-NEXT: str w8, [x8]
; CHECK-NEXT: ret
%1 = fcmp ueq float %x, %y %1 = fcmp ueq float %x, %y
br i1 %1, label %bb1, label %bb2 br i1 %1, label %bb1, label %bb2
bb2: bb2:
call void asm sideeffect call void asm sideeffect
"nop "nop
nop", nop",
""() #0 ""() #0
▲ Show 20 Lines • Show All 51 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/branch-relax-cbz.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-apple-darwin -aarch64-cbz-offset-bits=3 < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-apple-darwin -aarch64-cbz-offset-bits=3 < %s | FileCheck %s
define void @split_block_no_fallthrough(i64 %val) #0 { define void @split_block_no_fallthrough(i64 %val) #0 {
; CHECK-LABEL: split_block_no_fallthrough: ; CHECK-LABEL: split_block_no_fallthrough:
; CHECK: ; %bb.0: ; %bb ; CHECK: ; %bb.0: ; %bb
; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
; CHECK-NEXT: cmn x0, #5 ; =5 ; CHECK-NEXT: cmn x0, #5 ; =5
; CHECK-NEXT: b.le LBB0_3 ; CHECK-NEXT: b.le LBB0_3
; CHECK-NEXT: ; %bb.1: ; %b3 ; CHECK-NEXT: ; %bb.1: ; %b3
; CHECK-NEXT: ldr w8, [x8] ; CHECK-NEXT: ldr w8, [x8]
; CHECK-NEXT: cbnz w8, LBB0_2 ; CHECK-NEXT: cbnz w8, LBB0_2
; CHECK-NEXT: b LBB0_4 ; CHECK-NEXT: b LBB0_4
; CHECK-NEXT: LBB0_2: ; %b8 ; CHECK-NEXT: LBB0_2: ; %common.ret
; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: LBB0_3: ; %b2 ; CHECK-NEXT: LBB0_3: ; %b2
; CHECK-NEXT: mov w0, #93 ; CHECK-NEXT: mov w0, #93
; CHECK-NEXT: bl _extfunc ; CHECK-NEXT: bl _extfunc
; CHECK-NEXT: cbnz w0, LBB0_2 ; CHECK-NEXT: cbnz w0, LBB0_2
; CHECK-NEXT: LBB0_4: ; %b7 ; CHECK-NEXT: LBB0_4: ; %b7
; CHECK-NEXT: mov w0, #13 ; CHECK-NEXT: mov w0, #13
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llvm/test/CodeGen/AArch64/cfguard-checks.ll

Show First 20 Lines • Show All 90 Lines • ▼ Show 20 Lineslpad: ; preds = %entry
; CHECK: adrp x8, __guard_check_icall_fptr ; CHECK: adrp x8, __guard_check_icall_fptr
; CHECK: ldr x9, [x8, :lo12:__guard_check_icall_fptr] ; CHECK: ldr x9, [x8, :lo12:__guard_check_icall_fptr]
; CHECK: adrp x8, target_func ; CHECK: adrp x8, target_func
; CHECK: add x8, x8, :lo12:target_func ; CHECK: add x8, x8, :lo12:target_func
; CHECK: mov x15, x8 ; CHECK: mov x15, x8
; CHECK: blr x9 ; CHECK: blr x9
; CHECK-NEXT: .Ltmp0: ; CHECK-NEXT: .Ltmp0:
; CHECK-NEXT: blr x8 ; CHECK-NEXT: blr x8
; CHECK: // %invoke.cont ; CHECK: // %common.ret
; CHECK: // %lpad ; CHECK: // %lpad
} }
declare void @h() declare void @h()
; Test that longjmp targets have public labels and are included in the .gljmp section. ; Test that longjmp targets have public labels and are included in the .gljmp section.
%struct._SETJMP_FLOAT128 = type { [2 x i64] } %struct._SETJMP_FLOAT128 = type { [2 x i64] }
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llvm/test/CodeGen/AArch64/cgp-usubo.ll

Show First 20 Lines • Show All 120 Lines • ▼ Show 20 Lines
declare void @call(i1) declare void @call(i1)
define i1 @usubo_ult_sub_dominates_i64(i64 %x, i64 %y, i64* %p, i1 %cond) nounwind { define i1 @usubo_ult_sub_dominates_i64(i64 %x, i64 %y, i64* %p, i1 %cond) nounwind {
; CHECK-LABEL: usubo_ult_sub_dominates_i64: ; CHECK-LABEL: usubo_ult_sub_dominates_i64:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: tbz w3, #0, .LBB7_2 ; CHECK-NEXT: tbz w3, #0, .LBB7_2
; CHECK-NEXT: // %bb.1: // %t ; CHECK-NEXT: // %bb.1: // %t
; CHECK-NEXT: subs x8, x0, x1 ; CHECK-NEXT: subs x8, x0, x1
; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: cset w3, lo
; CHECK-NEXT: str x8, [x2] ; CHECK-NEXT: str x8, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: .LBB7_2: // %common.ret
; CHECK-NEXT: .LBB7_2: // %f
; CHECK-NEXT: and w0, w3, #0x1 ; CHECK-NEXT: and w0, w3, #0x1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
br i1 %cond, label %t, label %f br i1 %cond, label %t, label %f
t: t:
%s = sub i64 %x, %y %s = sub i64 %x, %y
store i64 %s, i64* %p store i64 %s, i64* %p
br i1 %cond, label %end, label %f br i1 %cond, label %end, label %f
f: f:
ret i1 %cond ret i1 %cond
end: end:
%ov = icmp ult i64 %x, %y %ov = icmp ult i64 %x, %y
ret i1 %ov ret i1 %ov
} }
define i1 @usubo_ult_cmp_dominates_i64(i64 %x, i64 %y, i64* %p, i1 %cond) nounwind { define i1 @usubo_ult_cmp_dominates_i64(i64 %x, i64 %y, i64* %p, i1 %cond) nounwind {
; CHECK-LABEL: usubo_ult_cmp_dominates_i64: ; CHECK-LABEL: usubo_ult_cmp_dominates_i64:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: str x30, [sp, #-48]! // 8-byte Folded Spill ; CHECK-NEXT: stp x30, x23, [sp, #-48]! // 16-byte Folded Spill
; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill ; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
; CHECK-NEXT: mov w20, w3 ; CHECK-NEXT: mov w19, w3
; CHECK-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill ; CHECK-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: tbz w3, #0, .LBB8_3 ; CHECK-NEXT: tbz w3, #0, .LBB8_3
; CHECK-NEXT: // %bb.1: // %t ; CHECK-NEXT: // %bb.1: // %t
; CHECK-NEXT: cmp x0, x1 ; CHECK-NEXT: cmp x0, x1
; CHECK-NEXT: mov x22, x0 ; CHECK-NEXT: cset w21, lo
; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: mov x23, x0
; CHECK-NEXT: mov x19, x2 ; CHECK-NEXT: mov w0, w21
; CHECK-NEXT: mov x21, x1 ; CHECK-NEXT: mov x20, x2
; CHECK-NEXT: mov x22, x1
; CHECK-NEXT: bl call ; CHECK-NEXT: bl call
; CHECK-NEXT: subs x8, x22, x21 ; CHECK-NEXT: subs x8, x23, x22
; CHECK-NEXT: b.hs .LBB8_3 ; CHECK-NEXT: b.hs .LBB8_3
; CHECK-NEXT: // %bb.2: // %end ; CHECK-NEXT: // %bb.2: // %end
; CHECK-NEXT: cset w0, lo ; CHECK-NEXT: mov w19, w21
; CHECK-NEXT: str x8, [x19] ; CHECK-NEXT: str x8, [x20]
; CHECK-NEXT: b .LBB8_4 ; CHECK-NEXT: .LBB8_3: // %common.ret
; CHECK-NEXT: .LBB8_3: // %f ; CHECK-NEXT: and w0, w19, #0x1
; CHECK-NEXT: and w0, w20, #0x1
; CHECK-NEXT: .LBB8_4: // %f
; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
; CHECK-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp], #48 // 8-byte Folded Reload ; CHECK-NEXT: ldp x30, x23, [sp], #48 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
br i1 %cond, label %t, label %f br i1 %cond, label %t, label %f
t: t:
%ov = icmp ult i64 %x, %y %ov = icmp ult i64 %x, %y
call void @call(i1 %ov) call void @call(i1 %ov)
br i1 %ov, label %end, label %f br i1 %ov, label %end, label %f
Show All 10 Lines

llvm/test/CodeGen/AArch64/check-sign-bit-before-extension.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-gnu-linux -o - | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-gnu-linux -o - | FileCheck %s
; These tests make sure that the `cmp` instruction is rendered with an ; These tests make sure that the `cmp` instruction is rendered with an
; instruction that checks the sign bit of the original unextended data ; instruction that checks the sign bit of the original unextended data
; (%in) instead of the sign bit of the sign extended one that is ; (%in) instead of the sign bit of the sign extended one that is
; created by the type legalization process. ; created by the type legalization process.
; ;
; The tests are subdivided in tests that determine the sign bit ; The tests are subdivided in tests that determine the sign bit
; looking through a `sign_extend_inreg` and tests that determine the ; looking through a `sign_extend_inreg` and tests that determine the
; sign bit looking through a `sign_extend`. ; sign bit looking through a `sign_extend`.
define i32 @f_i8_sign_extend_inreg(i8 %in, i32 %a, i32 %b) nounwind { define i32 @f_i8_sign_extend_inreg(i8 %in, i32 %a, i32 %b) nounwind {
; CHECK-LABEL: f_i8_sign_extend_inreg: ; CHECK-LABEL: f_i8_sign_extend_inreg:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: and w8, w0, #0xff ; CHECK-NEXT: sxtb w8, w0
; CHECK-NEXT: tbnz w0, #7, .LBB0_2 ; CHECK-NEXT: cmp w8, #0 // =0
; CHECK-NEXT: // %bb.1: // %A ; CHECK-NEXT: csel w8, w1, w2, ge
; CHECK-NEXT: add w0, w8, w1 ; CHECK-NEXT: add w0, w8, w0, uxtb
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB0_2: // %B
; CHECK-NEXT: add w0, w8, w2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%cmp = icmp sgt i8 %in, -1 %cmp = icmp sgt i8 %in, -1
%ext = zext i8 %in to i32 %ext = zext i8 %in to i32
br i1 %cmp, label %A, label %B br i1 %cmp, label %A, label %B
A: A:
%retA = add i32 %ext, %a %retA = add i32 %ext, %a
ret i32 %retA ret i32 %retA
B: B:
%retB = add i32 %ext, %b %retB = add i32 %ext, %b
ret i32 %retB ret i32 %retB
} }
define i32 @f_i16_sign_extend_inreg(i16 %in, i32 %a, i32 %b) nounwind { define i32 @f_i16_sign_extend_inreg(i16 %in, i32 %a, i32 %b) nounwind {
; CHECK-LABEL: f_i16_sign_extend_inreg: ; CHECK-LABEL: f_i16_sign_extend_inreg:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: and w8, w0, #0xffff ; CHECK-NEXT: sxth w8, w0
; CHECK-NEXT: tbnz w0, #15, .LBB1_2 ; CHECK-NEXT: cmp w8, #0 // =0
; CHECK-NEXT: // %bb.1: // %A ; CHECK-NEXT: csel w8, w1, w2, ge
; CHECK-NEXT: add w0, w8, w1 ; CHECK-NEXT: add w0, w8, w0, uxth
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB1_2: // %B
; CHECK-NEXT: add w0, w8, w2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%cmp = icmp sgt i16 %in, -1 %cmp = icmp sgt i16 %in, -1
%ext = zext i16 %in to i32 %ext = zext i16 %in to i32
br i1 %cmp, label %A, label %B br i1 %cmp, label %A, label %B
A: A:
%retA = add i32 %ext, %a %retA = add i32 %ext, %a
ret i32 %retA ret i32 %retA
B: B:
%retB = add i32 %ext, %b %retB = add i32 %ext, %b
ret i32 %retB ret i32 %retB
} }
define i64 @f_i32_sign_extend_inreg(i32 %in, i64 %a, i64 %b) nounwind { define i64 @f_i32_sign_extend_inreg(i32 %in, i64 %a, i64 %b) nounwind {
; CHECK-LABEL: f_i32_sign_extend_inreg: ; CHECK-LABEL: f_i32_sign_extend_inreg:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov w8, w0 ; CHECK-NEXT: cmp w0, #0 // =0
; CHECK-NEXT: tbnz w0, #31, .LBB2_2 ; CHECK-NEXT: csel x8, x1, x2, ge
; CHECK-NEXT: // %bb.1: // %A ; CHECK-NEXT: add x0, x8, w0, uxtw
; CHECK-NEXT: add x0, x8, x1
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB2_2: // %B
; CHECK-NEXT: add x0, x8, x2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%cmp = icmp sgt i32 %in, -1 %cmp = icmp sgt i32 %in, -1
%ext = zext i32 %in to i64 %ext = zext i32 %in to i64
br i1 %cmp, label %A, label %B br i1 %cmp, label %A, label %B
A: A:
%retA = add i64 %ext, %a %retA = add i64 %ext, %a
ret i64 %retA ret i64 %retA
B: B:
%retB = add i64 %ext, %b %retB = add i64 %ext, %b
ret i64 %retB ret i64 %retB
} }
define i32 @g_i8_sign_extend_inreg(i8 %in, i32 %a, i32 %b) nounwind { define i32 @g_i8_sign_extend_inreg(i8 %in, i32 %a, i32 %b) nounwind {
; CHECK-LABEL: g_i8_sign_extend_inreg: ; CHECK-LABEL: g_i8_sign_extend_inreg:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: and w8, w0, #0xff ; CHECK-NEXT: sxtb w8, w0
; CHECK-NEXT: tbnz w0, #7, .LBB3_2 ; CHECK-NEXT: cmp w8, #0 // =0
; CHECK-NEXT: // %bb.1: // %B ; CHECK-NEXT: csel w8, w1, w2, lt
; CHECK-NEXT: add w0, w8, w2 ; CHECK-NEXT: add w0, w8, w0, uxtb
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB3_2: // %A
; CHECK-NEXT: add w0, w8, w1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%cmp = icmp slt i8 %in, 0 %cmp = icmp slt i8 %in, 0
%ext = zext i8 %in to i32 %ext = zext i8 %in to i32
br i1 %cmp, label %A, label %B br i1 %cmp, label %A, label %B
A: A:
%retA = add i32 %ext, %a %retA = add i32 %ext, %a
ret i32 %retA ret i32 %retA
B: B:
%retB = add i32 %ext, %b %retB = add i32 %ext, %b
ret i32 %retB ret i32 %retB
} }
define i32 @g_i16_sign_extend_inreg(i16 %in, i32 %a, i32 %b) nounwind { define i32 @g_i16_sign_extend_inreg(i16 %in, i32 %a, i32 %b) nounwind {
; CHECK-LABEL: g_i16_sign_extend_inreg: ; CHECK-LABEL: g_i16_sign_extend_inreg:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: and w8, w0, #0xffff ; CHECK-NEXT: sxth w8, w0
; CHECK-NEXT: tbnz w0, #15, .LBB4_2 ; CHECK-NEXT: cmp w8, #0 // =0
; CHECK-NEXT: // %bb.1: // %B ; CHECK-NEXT: csel w8, w1, w2, lt
; CHECK-NEXT: add w0, w8, w2 ; CHECK-NEXT: add w0, w8, w0, uxth
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB4_2: // %A
; CHECK-NEXT: add w0, w8, w1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%cmp = icmp slt i16 %in, 0 %cmp = icmp slt i16 %in, 0
%ext = zext i16 %in to i32 %ext = zext i16 %in to i32
br i1 %cmp, label %A, label %B br i1 %cmp, label %A, label %B
A: A:
%retA = add i32 %ext, %a %retA = add i32 %ext, %a
ret i32 %retA ret i32 %retA
B: B:
%retB = add i32 %ext, %b %retB = add i32 %ext, %b
ret i32 %retB ret i32 %retB
} }
define i64 @g_i32_sign_extend_inreg(i32 %in, i64 %a, i64 %b) nounwind { define i64 @g_i32_sign_extend_inreg(i32 %in, i64 %a, i64 %b) nounwind {
; CHECK-LABEL: g_i32_sign_extend_inreg: ; CHECK-LABEL: g_i32_sign_extend_inreg:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov w8, w0 ; CHECK-NEXT: cmp w0, #0 // =0
; CHECK-NEXT: tbnz w0, #31, .LBB5_2 ; CHECK-NEXT: csel x8, x1, x2, lt
; CHECK-NEXT: // %bb.1: // %B ; CHECK-NEXT: add x0, x8, w0, uxtw
; CHECK-NEXT: add x0, x8, x2
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB5_2: // %A
; CHECK-NEXT: add x0, x8, x1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%cmp = icmp slt i32 %in, 0 %cmp = icmp slt i32 %in, 0
%ext = zext i32 %in to i64 %ext = zext i32 %in to i64
br i1 %cmp, label %A, label %B br i1 %cmp, label %A, label %B
A: A:
%retA = add i64 %ext, %a %retA = add i64 %ext, %a
ret i64 %retA ret i64 %retA
B: B:
%retB = add i64 %ext, %b %retB = add i64 %ext, %b
ret i64 %retB ret i64 %retB
} }
define i64 @f_i32_sign_extend_i64(i32 %in, i64 %a, i64 %b) nounwind { define i64 @f_i32_sign_extend_i64(i32 %in, i64 %a, i64 %b) nounwind {
; CHECK-LABEL: f_i32_sign_extend_i64: ; CHECK-LABEL: f_i32_sign_extend_i64:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov w8, w0 ; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: tbnz w0, #31, .LBB6_2 ; CHECK-NEXT: sxtw x8, w0
; CHECK-NEXT: // %bb.1: // %A ; CHECK-NEXT: cmp x8, #0 // =0
; CHECK-NEXT: add x0, x8, x1 ; CHECK-NEXT: csel x8, x1, x2, ge
; CHECK-NEXT: ret ; CHECK-NEXT: add x0, x8, w0, uxtw
; CHECK-NEXT: .LBB6_2: // %B
; CHECK-NEXT: add x0, x8, x2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%inext = sext i32 %in to i64 %inext = sext i32 %in to i64
%cmp = icmp sgt i64 %inext, -1 %cmp = icmp sgt i64 %inext, -1
%ext = zext i32 %in to i64 %ext = zext i32 %in to i64
br i1 %cmp, label %A, label %B br i1 %cmp, label %A, label %B
A: A:
%retA = add i64 %ext, %a %retA = add i64 %ext, %a
ret i64 %retA ret i64 %retA
B: B:
%retB = add i64 %ext, %b %retB = add i64 %ext, %b
ret i64 %retB ret i64 %retB
} }
define i64 @g_i32_sign_extend_i64(i32 %in, i64 %a, i64 %b) nounwind { define i64 @g_i32_sign_extend_i64(i32 %in, i64 %a, i64 %b) nounwind {
; CHECK-LABEL: g_i32_sign_extend_i64: ; CHECK-LABEL: g_i32_sign_extend_i64:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov w8, w0 ; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: tbnz w0, #31, .LBB7_2 ; CHECK-NEXT: sxtw x8, w0
; CHECK-NEXT: // %bb.1: // %B ; CHECK-NEXT: cmp x8, #0 // =0
; CHECK-NEXT: add x0, x8, x2 ; CHECK-NEXT: csel x8, x1, x2, lt
; CHECK-NEXT: ret ; CHECK-NEXT: add x0, x8, w0, uxtw
; CHECK-NEXT: .LBB7_2: // %A
; CHECK-NEXT: add x0, x8, x1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%inext = sext i32 %in to i64 %inext = sext i32 %in to i64
%cmp = icmp slt i64 %inext, 0 %cmp = icmp slt i64 %inext, 0
%ext = zext i32 %in to i64 %ext = zext i32 %in to i64
br i1 %cmp, label %A, label %B br i1 %cmp, label %A, label %B
A: A:
%retA = add i64 %ext, %a %retA = add i64 %ext, %a
ret i64 %retA ret i64 %retA
B: B:
%retB = add i64 %ext, %b %retB = add i64 %ext, %b
ret i64 %retB ret i64 %retB
} }

llvm/test/CodeGen/AArch64/combine-comparisons-by-cse.ll

Show First 20 Lines • Show All 710 Lines • ▼ Show 20 Lines
return: ; preds = %land.lhs.true, %cond.end14 return: ; preds = %land.lhs.true, %cond.end14
%retval.0 = phi i32 [ 4, %cond.end14 ], [ 3, %land.lhs.true ] %retval.0 = phi i32 [ 4, %cond.end14 ], [ 3, %land.lhs.true ]
ret i32 %retval.0 ret i32 %retval.0
} }
define void @cmp_shifted(i32 %in, i32 %lhs, i32 %rhs) { define void @cmp_shifted(i32 %in, i32 %lhs, i32 %rhs) {
; CHECK-LABEL: cmp_shifted: ; CHECK-LABEL: cmp_shifted:
; CHECK: // %bb.0: ; CHECK: // %bb.0: // %common.ret
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -16 ; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: cmp w0, #0 // =0
; CHECK-NEXT: mov w8, #42
; CHECK-NEXT: csinc w8, w8, wzr, gt
; CHECK-NEXT: cmp w0, #2, lsl #12 // =8192 ; CHECK-NEXT: cmp w0, #2, lsl #12 // =8192
; CHECK-NEXT: b.lt .LBB10_2 ; CHECK-NEXT: mov w9, #128
; CHECK-NEXT: // %bb.1: // %true ; CHECK-NEXT: csel w0, w9, w8, ge
; CHECK-NEXT: mov w0, #128
; CHECK-NEXT: b .LBB10_5
; CHECK-NEXT: .LBB10_2: // %false
; CHECK-NEXT: cmp w0, #1 // =1
; CHECK-NEXT: b.lt .LBB10_4
; CHECK-NEXT: // %bb.3: // %truer
; CHECK-NEXT: mov w0, #42
; CHECK-NEXT: b .LBB10_5
; CHECK-NEXT: .LBB10_4: // %falser
; CHECK-NEXT: mov w0, #1
; CHECK-NEXT: .LBB10_5: // %true
; CHECK-NEXT: bl zoo ; CHECK-NEXT: bl zoo
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; [...] ; [...]
%tst_low = icmp sgt i32 %in, 8191 %tst_low = icmp sgt i32 %in, 8191
br i1 %tst_low, label %true, label %false br i1 %tst_low, label %true, label %false
▲ Show 20 Lines • Show All 96 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/cond-br-tuning.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -debugify-and-strip-all-safe < %s -O3 -mtriple=aarch64-eabi -verify-machineinstrs | FileCheck %s ; RUN: llc -debugify-and-strip-all-safe < %s -O3 -mtriple=aarch64-eabi -verify-machineinstrs | FileCheck %s
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-linaro-linux-gnueabi" target triple = "aarch64-linaro-linux-gnueabi"
; CMN is an alias of ADDS. ; CMN is an alias of ADDS.
define void @test_add_cbz(i32 %a, i32 %b, i32* %ptr) { define void @test_add_cbz(i32 %a, i32 %b, i32* %ptr) {
; CHECK-LABEL: test_add_cbz: ; CHECK-LABEL: test_add_cbz:
; CHECK: // %bb.0: ; CHECK: // %bb.0: // %common.ret
; CHECK-NEXT: cmn w0, w1 ; CHECK-NEXT: cmn w0, w1
; CHECK-NEXT: b.eq .LBB0_2 ; CHECK-NEXT: cset w8, eq
; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: str wzr, [x2]
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB0_2: // %L2
; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: str w8, [x2] ; CHECK-NEXT: str w8, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = add nsw i32 %a, %b %c = add nsw i32 %a, %b
%d = icmp ne i32 %c, 0 %d = icmp ne i32 %c, 0
br i1 %d, label %L1, label %L2 br i1 %d, label %L1, label %L2
L1: L1:
store i32 0, i32* %ptr, align 4 store i32 0, i32* %ptr, align 4
ret void ret void
L2: L2:
store i32 1, i32* %ptr, align 4 store i32 1, i32* %ptr, align 4
ret void ret void
} }
define void @test_add_cbz_multiple_use(i32 %a, i32 %b, i32* %ptr) { define void @test_add_cbz_multiple_use(i32 %a, i32 %b, i32* %ptr) {
; CHECK-LABEL: test_add_cbz_multiple_use: ; CHECK-LABEL: test_add_cbz_multiple_use:
; CHECK: // %bb.0: ; CHECK: // %bb.0: // %common.ret
; CHECK-NEXT: adds w8, w0, w1 ; CHECK-NEXT: adds w8, w0, w1
; CHECK-NEXT: b.eq .LBB1_2 ; CHECK-NEXT: csel w8, wzr, w8, ne
; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: str wzr, [x2]
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB1_2: // %L2
; CHECK-NEXT: str w8, [x2] ; CHECK-NEXT: str w8, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = add nsw i32 %a, %b %c = add nsw i32 %a, %b
%d = icmp ne i32 %c, 0 %d = icmp ne i32 %c, 0
br i1 %d, label %L1, label %L2 br i1 %d, label %L1, label %L2
L1: L1:
store i32 0, i32* %ptr, align 4 store i32 0, i32* %ptr, align 4
ret void ret void
L2: L2:
store i32 %c, i32* %ptr, align 4 store i32 %c, i32* %ptr, align 4
ret void ret void
} }
define void @test_add_cbz_64(i64 %a, i64 %b, i64* %ptr) { define void @test_add_cbz_64(i64 %a, i64 %b, i64* %ptr) {
; CHECK-LABEL: test_add_cbz_64: ; CHECK-LABEL: test_add_cbz_64:
; CHECK: // %bb.0: ; CHECK: // %bb.0: // %common.ret
; CHECK-NEXT: cmn x0, x1 ; CHECK-NEXT: cmn x0, x1
; CHECK-NEXT: b.eq .LBB2_2 ; CHECK-NEXT: cset w8, eq
; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: str xzr, [x2]
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB2_2: // %L2
; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: str x8, [x2] ; CHECK-NEXT: str x8, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = add nsw i64 %a, %b %c = add nsw i64 %a, %b
%d = icmp ne i64 %c, 0 %d = icmp ne i64 %c, 0
br i1 %d, label %L1, label %L2 br i1 %d, label %L1, label %L2
L1: L1:
store i64 0, i64* %ptr, align 4 store i64 0, i64* %ptr, align 4
ret void ret void
L2: L2:
store i64 1, i64* %ptr, align 4 store i64 1, i64* %ptr, align 4
ret void ret void
} }
define void @test_and_cbz(i32 %a, i32* %ptr) { define void @test_and_cbz(i32 %a, i32* %ptr) {
; CHECK-LABEL: test_and_cbz: ; CHECK-LABEL: test_and_cbz:
; CHECK: // %bb.0: ; CHECK: // %bb.0: // %common.ret
; CHECK-NEXT: tst w0, #0x6 ; CHECK-NEXT: tst w0, #0x6
; CHECK-NEXT: b.eq .LBB3_2 ; CHECK-NEXT: cset w8, eq
; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: str wzr, [x1]
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB3_2: // %L2
; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: str w8, [x1] ; CHECK-NEXT: str w8, [x1]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = and i32 %a, 6 %c = and i32 %a, 6
%d = icmp ne i32 %c, 0 %d = icmp ne i32 %c, 0
br i1 %d, label %L1, label %L2 br i1 %d, label %L1, label %L2
L1: L1:
store i32 0, i32* %ptr, align 4 store i32 0, i32* %ptr, align 4
ret void ret void
L2: L2:
store i32 1, i32* %ptr, align 4 store i32 1, i32* %ptr, align 4
ret void ret void
} }
define void @test_bic_cbnz(i32 %a, i32 %b, i32* %ptr) { define void @test_bic_cbnz(i32 %a, i32 %b, i32* %ptr) {
; CHECK-LABEL: test_bic_cbnz: ; CHECK-LABEL: test_bic_cbnz:
; CHECK: // %bb.0: ; CHECK: // %bb.0: // %common.ret
; CHECK-NEXT: bics wzr, w1, w0 ; CHECK-NEXT: bics wzr, w1, w0
; CHECK-NEXT: b.ne .LBB4_2 ; CHECK-NEXT: cset w8, ne
; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: str wzr, [x2]
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB4_2: // %L2
; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: str w8, [x2] ; CHECK-NEXT: str w8, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = and i32 %a, %b %c = and i32 %a, %b
%d = icmp eq i32 %c, %b %d = icmp eq i32 %c, %b
br i1 %d, label %L1, label %L2 br i1 %d, label %L1, label %L2
L1: L1:
store i32 0, i32* %ptr, align 4 store i32 0, i32* %ptr, align 4
ret void ret void
▲ Show 20 Lines • Show All 118 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/f16-instructions.ll

Show First 20 Lines • Show All 511 Lines • ▼ Show 20 Linesdefine void @test_fccmp(half %in, half* %out) {
store half %result, half* %out store half %result, half* %out
ret void ret void
} }
; CHECK-CVT-LABEL: test_br_cc: ; CHECK-CVT-LABEL: test_br_cc:
; CHECK-CVT-NEXT: fcvt s1, h1 ; CHECK-CVT-NEXT: fcvt s1, h1
; CHECK-CVT-NEXT: fcvt s0, h0 ; CHECK-CVT-NEXT: fcvt s0, h0
; CHECK-CVT-NEXT: fcmp s0, s1 ; CHECK-CVT-NEXT: fcmp s0, s1
; CHECK-CVT-NEXT: b.mi [[BRCC_ELSE:.?LBB[0-9_]+]] ; CHECK-CVT-NEXT: csel x8, x0, x1, pl
; CHECK-CVT-NEXT: str wzr, [x0] ; CHECK-CVT-NEXT: str wzr, [x8]
; CHECK-CVT-NEXT: ret
; CHECK-CVT-NEXT: [[BRCC_ELSE]]:
; CHECK-CVT-NEXT: str wzr, [x1]
; CHECK-CVT-NEXT: ret ; CHECK-CVT-NEXT: ret
; CHECK-FP16-LABEL: test_br_cc: ; CHECK-FP16-LABEL: test_br_cc:
; CHECK-FP16-NEXT: fcmp h0, h1 ; CHECK-FP16-NEXT: fcmp h0, h1
; CHECK-FP16-NEXT: b.mi [[BRCC_ELSE:.?LBB[0-9_]+]] ; CHECK-FP16-NEXT: csel x8, x0, x1, pl
; CHECK-FP16-NEXT: str wzr, [x0] ; CHECK-FP16-NEXT: str wzr, [x8]
; CHECK-FP16-NEXT: ret
; CHECK-FP16-NEXT: [[BRCC_ELSE]]:
; CHECK-FP16-NEXT: str wzr, [x1]
; CHECK-FP16-NEXT: ret ; CHECK-FP16-NEXT: ret
define void @test_br_cc(half %a, half %b, i32* %p1, i32* %p2) #0 { define void @test_br_cc(half %a, half %b, i32* %p1, i32* %p2) #0 {
%c = fcmp uge half %a, %b %c = fcmp uge half %a, %b
br i1 %c, label %then, label %else br i1 %c, label %then, label %else
then: then:
store i32 0, i32* %p1 store i32 0, i32* %p1
ret void ret void
▲ Show 20 Lines • Show All 845 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/fast-isel-branch-cond-split.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
define i64 @test_or(i32 %a, i32 %b) { define i64 @test_or(i32 %a, i32 %b) {
; CHECK-LABEL: test_or: ; CHECK-LABEL: test_or:
; CHECK: ; %bb.0: ; %bb1 ; CHECK: ; %bb.0: ; %bb1
; CHECK-NEXT: cbnz w0, LBB0_2 ; CHECK-NEXT: mov w8, w0
; CHECK-NEXT: LBB0_1: ; %bb3
; CHECK-NEXT: mov x0, xzr ; CHECK-NEXT: mov x0, xzr
; CHECK-NEXT: cbnz w8, LBB0_2
; CHECK-NEXT: LBB0_1: ; %common.ret
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: LBB0_2: ; %bb1.cond.split ; CHECK-NEXT: LBB0_2: ; %bb1.cond.split
; CHECK-NEXT: mov x0, xzr
; CHECK-NEXT: cbz w1, LBB0_1 ; CHECK-NEXT: cbz w1, LBB0_1
; CHECK-NEXT: ; %bb.3: ; %bb4 ; CHECK-NEXT: ; %bb.3: ; %bb4
; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -8 ; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: bl _bar ; CHECK-NEXT: bl _bar
; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
Show All 10 Lines
bb4: bb4:
%2 = call i64 @bar() %2 = call i64 @bar()
ret i64 %2 ret i64 %2
} }
define i64 @test_or_select(i32 %a, i32 %b) { define i64 @test_or_select(i32 %a, i32 %b) {
; CHECK-LABEL: test_or_select: ; CHECK-LABEL: test_or_select:
; CHECK: ; %bb.0: ; %bb1 ; CHECK: ; %bb.0: ; %bb1
; CHECK-NEXT: cbnz w0, LBB1_2 ; CHECK-NEXT: mov w8, w0
; CHECK-NEXT: LBB1_1: ; %bb3
; CHECK-NEXT: mov x0, xzr ; CHECK-NEXT: mov x0, xzr
; CHECK-NEXT: cbnz w8, LBB1_2
; CHECK-NEXT: LBB1_1: ; %common.ret
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: LBB1_2: ; %bb1.cond.split ; CHECK-NEXT: LBB1_2: ; %bb1.cond.split
; CHECK-NEXT: mov x0, xzr
; CHECK-NEXT: cbz w1, LBB1_1 ; CHECK-NEXT: cbz w1, LBB1_1
; CHECK-NEXT: ; %bb.3: ; %bb4 ; CHECK-NEXT: ; %bb.3: ; %bb4
; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -8 ; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: bl _bar ; CHECK-NEXT: bl _bar
; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
Show All 10 Lines
bb4: bb4:
%2 = call i64 @bar() %2 = call i64 @bar()
ret i64 %2 ret i64 %2
} }
define i64 @test_and(i32 %a, i32 %b) { define i64 @test_and(i32 %a, i32 %b) {
; CHECK-LABEL: test_and: ; CHECK-LABEL: test_and:
; CHECK: ; %bb.0: ; %bb1 ; CHECK: ; %bb.0: ; %bb1
; CHECK-NEXT: cbnz w0, LBB2_2 ; CHECK-NEXT: mov w8, w0
; CHECK-NEXT: LBB2_1: ; %bb3
; CHECK-NEXT: mov x0, xzr ; CHECK-NEXT: mov x0, xzr
; CHECK-NEXT: cbnz w8, LBB2_2
; CHECK-NEXT: LBB2_1: ; %common.ret
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: LBB2_2: ; %bb1.cond.split ; CHECK-NEXT: LBB2_2: ; %bb1.cond.split
; CHECK-NEXT: mov x0, xzr
; CHECK-NEXT: cbz w1, LBB2_1 ; CHECK-NEXT: cbz w1, LBB2_1
; CHECK-NEXT: ; %bb.3: ; %bb4 ; CHECK-NEXT: ; %bb.3: ; %bb4
; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -8 ; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: bl _bar ; CHECK-NEXT: bl _bar
; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
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bb4: bb4:
%2 = call i64 @bar() %2 = call i64 @bar()
ret i64 %2 ret i64 %2
} }
define i64 @test_and_select(i32 %a, i32 %b) { define i64 @test_and_select(i32 %a, i32 %b) {
; CHECK-LABEL: test_and_select: ; CHECK-LABEL: test_and_select:
; CHECK: ; %bb.0: ; %bb1 ; CHECK: ; %bb.0: ; %bb1
; CHECK-NEXT: cbnz w0, LBB3_2 ; CHECK-NEXT: mov w8, w0
; CHECK-NEXT: LBB3_1: ; %bb3
; CHECK-NEXT: mov x0, xzr ; CHECK-NEXT: mov x0, xzr
; CHECK-NEXT: cbnz w8, LBB3_2
; CHECK-NEXT: LBB3_1: ; %common.ret
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: LBB3_2: ; %bb1.cond.split ; CHECK-NEXT: LBB3_2: ; %bb1.cond.split
; CHECK-NEXT: mov x0, xzr
; CHECK-NEXT: cbz w1, LBB3_1 ; CHECK-NEXT: cbz w1, LBB3_1
; CHECK-NEXT: ; %bb.3: ; %bb4 ; CHECK-NEXT: ; %bb.3: ; %bb4
; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -8 ; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: bl _bar ; CHECK-NEXT: bl _bar
; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
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define i64 @test_or_unpredictable(i32 %a, i32 %b) { define i64 @test_or_unpredictable(i32 %a, i32 %b) {
; CHECK-LABEL: test_or_unpredictable: ; CHECK-LABEL: test_or_unpredictable:
; CHECK: ; %bb.0: ; %bb1 ; CHECK: ; %bb.0: ; %bb1
; CHECK-NEXT: cmp w0, #0 ; =0 ; CHECK-NEXT: cmp w0, #0 ; =0
; CHECK-NEXT: cset w8, eq ; CHECK-NEXT: cset w8, eq
; CHECK-NEXT: cmp w1, #0 ; =0 ; CHECK-NEXT: cmp w1, #0 ; =0
; CHECK-NEXT: cset w9, eq ; CHECK-NEXT: cset w9, eq
; CHECK-NEXT: orr w8, w8, w9 ; CHECK-NEXT: orr w8, w8, w9
; CHECK-NEXT: mov x0, xzr
; CHECK-NEXT: tbnz w8, #0, LBB4_2 ; CHECK-NEXT: tbnz w8, #0, LBB4_2
; CHECK-NEXT: ; %bb.1: ; %bb4 ; CHECK-NEXT: ; %bb.1: ; %bb4
; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -8 ; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: bl _bar ; CHECK-NEXT: bl _bar
; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: LBB4_2: ; %common.ret
; CHECK-NEXT: LBB4_2: ; %bb3
; CHECK-NEXT: mov x0, xzr
; CHECK-NEXT: ret ; CHECK-NEXT: ret
bb1: bb1:
%0 = icmp eq i32 %a, 0 %0 = icmp eq i32 %a, 0
%1 = icmp eq i32 %b, 0 %1 = icmp eq i32 %b, 0
%or.cond = or i1 %0, %1 %or.cond = or i1 %0, %1
br i1 %or.cond, label %bb3, label %bb4, !unpredictable !2 br i1 %or.cond, label %bb3, label %bb4, !unpredictable !2
bb3: bb3:
ret i64 0 ret i64 0
bb4: bb4:
%2 = call i64 @bar() %2 = call i64 @bar()
ret i64 %2 ret i64 %2
} }
define i64 @test_and_unpredictable(i32 %a, i32 %b) { define i64 @test_and_unpredictable(i32 %a, i32 %b) {
; CHECK-LABEL: test_and_unpredictable: ; CHECK-LABEL: test_and_unpredictable:
; CHECK: ; %bb.0: ; %bb1 ; CHECK: ; %bb.0: ; %bb1
; CHECK-NEXT: cmp w0, #0 ; =0 ; CHECK-NEXT: cmp w0, #0 ; =0
; CHECK-NEXT: cset w8, ne ; CHECK-NEXT: cset w8, ne
; CHECK-NEXT: cmp w1, #0 ; =0 ; CHECK-NEXT: cmp w1, #0 ; =0
; CHECK-NEXT: cset w9, ne ; CHECK-NEXT: cset w9, ne
; CHECK-NEXT: and w8, w8, w9 ; CHECK-NEXT: and w8, w8, w9
; CHECK-NEXT: mov x0, xzr
; CHECK-NEXT: tbz w8, #0, LBB5_2 ; CHECK-NEXT: tbz w8, #0, LBB5_2
; CHECK-NEXT: ; %bb.1: ; %bb4 ; CHECK-NEXT: ; %bb.1: ; %bb4
; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -8 ; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16 ; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: bl _bar ; CHECK-NEXT: bl _bar
; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: LBB5_2: ; %common.ret
; CHECK-NEXT: LBB5_2: ; %bb3
; CHECK-NEXT: mov x0, xzr
; CHECK-NEXT: ret ; CHECK-NEXT: ret
bb1: bb1:
%0 = icmp ne i32 %a, 0 %0 = icmp ne i32 %a, 0
%1 = icmp ne i32 %b, 0 %1 = icmp ne i32 %b, 0
%or.cond = and i1 %0, %1 %or.cond = and i1 %0, %1
br i1 %or.cond, label %bb4, label %bb3, !unpredictable !2 br i1 %or.cond, label %bb4, label %bb3, !unpredictable !2
bb3: bb3:
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llvm/test/CodeGen/AArch64/implicit-null-check.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -verify-machineinstrs -O3 -mtriple=aarch64-unknown-unknown -enable-implicit-null-checks | FileCheck %s ; RUN: llc < %s -verify-machineinstrs -O3 -mtriple=aarch64-unknown-unknown -enable-implicit-null-checks | FileCheck %s
; Basic test for implicit null check conversion - this is analogous to the ; Basic test for implicit null check conversion - this is analogous to the
; file with the same name in the X86 tree, but adjusted to remove patterns ; file with the same name in the X86 tree, but adjusted to remove patterns
; related to memory folding of arithmetic (since aarch64 doesn't), and add ; related to memory folding of arithmetic (since aarch64 doesn't), and add
; a couple of aarch64 specific tests. ; a couple of aarch64 specific tests.
define i32 @imp_null_check_load_fallthrough(i32* %x) { define i32 @imp_null_check_load_fallthrough(i32* %x) {
; CHECK-LABEL: imp_null_check_load_fallthrough: ; CHECK-LABEL: imp_null_check_load_fallthrough:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: .Ltmp0: ; CHECK-NEXT: .Ltmp0:
; CHECK-NEXT: ldr w0, [x0] // on-fault: .LBB0_2 ; CHECK-NEXT: ldr w0, [x0] // on-fault: .LBB0_2
; CHECK-NEXT: // %bb.1: // %not_null ; CHECK-NEXT: // %bb.1: // %not_null
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB0_2: // %is_null ; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: mov w0, #42 ; CHECK-NEXT: mov w0, #42
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%c = icmp eq i32* %x, null %c = icmp eq i32* %x, null
br i1 %c, label %is_null, label %not_null, !make.implicit !0 br i1 %c, label %is_null, label %not_null, !make.implicit !0
not_null: not_null:
%t = load i32, i32* %x %t = load i32, i32* %x
ret i32 %t ret i32 %t
is_null: is_null:
ret i32 42 ret i32 42
} }
define i32 @imp_null_check_load_reorder(i32* %x) { define i32 @imp_null_check_load_reorder(i32* %x) {
; CHECK-LABEL: imp_null_check_load_reorder: ; CHECK-LABEL: imp_null_check_load_reorder:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: .Ltmp1: ; CHECK-NEXT: .Ltmp1:
; CHECK-NEXT: ldr w0, [x0] // on-fault: .LBB1_2 ; CHECK-NEXT: ldr w0, [x0] // on-fault: .LBB1_2
; CHECK-NEXT: // %bb.1: // %not_null ; CHECK-NEXT: // %bb.1: // %not_null
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB1_2: // %is_null ; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: mov w0, #42 ; CHECK-NEXT: mov w0, #42
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%c = icmp eq i32* %x, null %c = icmp eq i32* %x, null
br i1 %c, label %is_null, label %not_null, !make.implicit !0 br i1 %c, label %is_null, label %not_null, !make.implicit !0
is_null: is_null:
ret i32 42 ret i32 42
not_null: not_null:
%t = load i32, i32* %x %t = load i32, i32* %x
ret i32 %t ret i32 %t
} }
define i32 @imp_null_check_unordered_load(i32* %x) { define i32 @imp_null_check_unordered_load(i32* %x) {
; CHECK-LABEL: imp_null_check_unordered_load: ; CHECK-LABEL: imp_null_check_unordered_load:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: .Ltmp2: ; CHECK-NEXT: .Ltmp2:
; CHECK-NEXT: ldr w0, [x0] // on-fault: .LBB2_2 ; CHECK-NEXT: ldr w0, [x0] // on-fault: .LBB2_2
; CHECK-NEXT: // %bb.1: // %not_null ; CHECK-NEXT: // %bb.1: // %not_null
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB2_2: // %is_null ; CHECK-NEXT: .LBB2_2:
; CHECK-NEXT: mov w0, #42 ; CHECK-NEXT: mov w0, #42
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%c = icmp eq i32* %x, null %c = icmp eq i32* %x, null
br i1 %c, label %is_null, label %not_null, !make.implicit !0 br i1 %c, label %is_null, label %not_null, !make.implicit !0
is_null: is_null:
ret i32 42 ret i32 42
not_null: not_null:
%t = load atomic i32, i32* %x unordered, align 4 %t = load atomic i32, i32* %x unordered, align 4
ret i32 %t ret i32 %t
} }
; TODO: Can be converted into implicit check. ; TODO: Can be converted into implicit check.
;; Probably could be implicit, but we're conservative for now ;; Probably could be implicit, but we're conservative for now
define i32 @imp_null_check_seq_cst_load(i32* %x) { define i32 @imp_null_check_seq_cst_load(i32* %x) {
; CHECK-LABEL: imp_null_check_seq_cst_load: ; CHECK-LABEL: imp_null_check_seq_cst_load:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cbz x0, .LBB3_2 ; CHECK-NEXT: cbz x0, .LBB3_2
; CHECK-NEXT: // %bb.1: // %not_null ; CHECK-NEXT: // %bb.1: // %not_null
; CHECK-NEXT: ldar w0, [x0] ; CHECK-NEXT: ldar w0, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB3_2: // %is_null ; CHECK-NEXT: .LBB3_2:
; CHECK-NEXT: mov w0, #42 ; CHECK-NEXT: mov w0, #42
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%c = icmp eq i32* %x, null %c = icmp eq i32* %x, null
br i1 %c, label %is_null, label %not_null, !make.implicit !0 br i1 %c, label %is_null, label %not_null, !make.implicit !0
is_null: is_null:
ret i32 42 ret i32 42
not_null: not_null:
%t = load atomic i32, i32* %x seq_cst, align 4 %t = load atomic i32, i32* %x seq_cst, align 4
ret i32 %t ret i32 %t
} }
;; Might be memory mapped IO, so can't rely on fault behavior ;; Might be memory mapped IO, so can't rely on fault behavior
define i32 @imp_null_check_volatile_load(i32* %x) { define i32 @imp_null_check_volatile_load(i32* %x) {
; CHECK-LABEL: imp_null_check_volatile_load: ; CHECK-LABEL: imp_null_check_volatile_load:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cbz x0, .LBB4_2 ; CHECK-NEXT: cbz x0, .LBB4_2
; CHECK-NEXT: // %bb.1: // %not_null ; CHECK-NEXT: // %bb.1: // %not_null
; CHECK-NEXT: ldr w0, [x0] ; CHECK-NEXT: ldr w0, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB4_2: // %is_null ; CHECK-NEXT: .LBB4_2:
; CHECK-NEXT: mov w0, #42 ; CHECK-NEXT: mov w0, #42
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%c = icmp eq i32* %x, null %c = icmp eq i32* %x, null
br i1 %c, label %is_null, label %not_null, !make.implicit !0 br i1 %c, label %is_null, label %not_null, !make.implicit !0
is_null: is_null:
ret i32 42 ret i32 42
not_null: not_null:
%t = load volatile i32, i32* %x, align 4 %t = load volatile i32, i32* %x, align 4
ret i32 %t ret i32 %t
} }
define i8 @imp_null_check_load_i8(i8* %x) { define i8 @imp_null_check_load_i8(i8* %x) {
; CHECK-LABEL: imp_null_check_load_i8: ; CHECK-LABEL: imp_null_check_load_i8:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: .Ltmp3: ; CHECK-NEXT: .Ltmp3:
; CHECK-NEXT: ldrb w0, [x0] // on-fault: .LBB5_2 ; CHECK-NEXT: ldrb w0, [x0] // on-fault: .LBB5_2
; CHECK-NEXT: // %bb.1: // %not_null ; CHECK-NEXT: // %bb.1: // %not_null
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB5_2: // %is_null ; CHECK-NEXT: .LBB5_2:
; CHECK-NEXT: mov w0, #42 ; CHECK-NEXT: mov w0, #42
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%c = icmp eq i8* %x, null %c = icmp eq i8* %x, null
br i1 %c, label %is_null, label %not_null, !make.implicit !0 br i1 %c, label %is_null, label %not_null, !make.implicit !0
is_null: is_null:
ret i8 42 ret i8 42
not_null: not_null:
%t = load i8, i8* %x %t = load i8, i8* %x
ret i8 %t ret i8 %t
} }
define i256 @imp_null_check_load_i256(i256* %x) { define i256 @imp_null_check_load_i256(i256* %x) {
; CHECK-LABEL: imp_null_check_load_i256: ; CHECK-LABEL: imp_null_check_load_i256:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cbz x0, .LBB6_2 ; CHECK-NEXT: cbz x0, .LBB6_2
; CHECK-NEXT: // %bb.1: // %not_null ; CHECK-NEXT: // %bb.1: // %not_null
; CHECK-NEXT: ldp x8, x1, [x0]
; CHECK-NEXT: ldp x2, x3, [x0, #16] ; CHECK-NEXT: ldp x2, x3, [x0, #16]
; CHECK-NEXT: mov x0, x8 ; CHECK-NEXT: ldp x0, x1, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB6_2: // %is_null ; CHECK-NEXT: .LBB6_2:
; CHECK-NEXT: mov w0, #42
; CHECK-NEXT: mov x1, xzr ; CHECK-NEXT: mov x1, xzr
; CHECK-NEXT: mov x2, xzr ; CHECK-NEXT: mov x2, xzr
; CHECK-NEXT: mov x3, xzr ; CHECK-NEXT: mov x3, xzr
; CHECK-NEXT: mov w0, #42
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%c = icmp eq i256* %x, null %c = icmp eq i256* %x, null
br i1 %c, label %is_null, label %not_null, !make.implicit !0 br i1 %c, label %is_null, label %not_null, !make.implicit !0
is_null: is_null:
ret i256 42 ret i256 42
not_null: not_null:
%t = load i256, i256* %x %t = load i256, i256* %x
ret i256 %t ret i256 %t
} }
define i32 @imp_null_check_gep_load(i32* %x) { define i32 @imp_null_check_gep_load(i32* %x) {
; CHECK-LABEL: imp_null_check_gep_load: ; CHECK-LABEL: imp_null_check_gep_load:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: .Ltmp4: ; CHECK-NEXT: .Ltmp4:
; CHECK-NEXT: ldr w0, [x0, #128] // on-fault: .LBB7_2 ; CHECK-NEXT: ldr w0, [x0, #128] // on-fault: .LBB7_2
; CHECK-NEXT: // %bb.1: // %not_null ; CHECK-NEXT: // %bb.1: // %not_null
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB7_2: // %is_null ; CHECK-NEXT: .LBB7_2:
; CHECK-NEXT: mov w0, #42 ; CHECK-NEXT: mov w0, #42
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%c = icmp eq i32* %x, null %c = icmp eq i32* %x, null
br i1 %c, label %is_null, label %not_null, !make.implicit !0 br i1 %c, label %is_null, label %not_null, !make.implicit !0
is_null: is_null:
ret i32 42 ret i32 42
not_null: not_null:
%x.gep = getelementptr i32, i32* %x, i32 32 %x.gep = getelementptr i32, i32* %x, i32 32
%t = load i32, i32* %x.gep %t = load i32, i32* %x.gep
ret i32 %t ret i32 %t
} }
define i32 @imp_null_check_add_result(i32* %x, i32 %p) { define i32 @imp_null_check_add_result(i32* %x, i32 %p) {
; CHECK-LABEL: imp_null_check_add_result: ; CHECK-LABEL: imp_null_check_add_result:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: .Ltmp5: ; CHECK-NEXT: .Ltmp5:
; CHECK-NEXT: ldr w8, [x0] // on-fault: .LBB8_2 ; CHECK-NEXT: ldr w8, [x0] // on-fault: .LBB8_2
; CHECK-NEXT: // %bb.1: // %not_null ; CHECK-NEXT: // %bb.1: // %not_null
; CHECK-NEXT: add w0, w8, w1 ; CHECK-NEXT: add w0, w8, w1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB8_2: // %is_null ; CHECK-NEXT: .LBB8_2:
; CHECK-NEXT: mov w0, #42 ; CHECK-NEXT: mov w0, #42
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%c = icmp eq i32* %x, null %c = icmp eq i32* %x, null
br i1 %c, label %is_null, label %not_null, !make.implicit !0 br i1 %c, label %is_null, label %not_null, !make.implicit !0
is_null: is_null:
ret i32 42 ret i32 42
Show All 10 Lines
; CHECK-LABEL: imp_null_check_hoist_over_udiv: ; CHECK-LABEL: imp_null_check_hoist_over_udiv:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: .Ltmp6: ; CHECK-NEXT: .Ltmp6:
; CHECK-NEXT: ldr w8, [x0] // on-fault: .LBB9_2 ; CHECK-NEXT: ldr w8, [x0] // on-fault: .LBB9_2
; CHECK-NEXT: // %bb.1: // %not_null ; CHECK-NEXT: // %bb.1: // %not_null
; CHECK-NEXT: udiv w9, w1, w2 ; CHECK-NEXT: udiv w9, w1, w2
; CHECK-NEXT: add w0, w8, w9 ; CHECK-NEXT: add w0, w8, w9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB9_2: // %is_null ; CHECK-NEXT: .LBB9_2:
; CHECK-NEXT: mov w0, #42 ; CHECK-NEXT: mov w0, #42
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%c = icmp eq i32* %x, null %c = icmp eq i32* %x, null
br i1 %c, label %is_null, label %not_null, !make.implicit !0 br i1 %c, label %is_null, label %not_null, !make.implicit !0
is_null: is_null:
ret i32 42 ret i32 42
Show All 12 Lines
; CHECK-LABEL: imp_null_check_hoist_over_unrelated_load: ; CHECK-LABEL: imp_null_check_hoist_over_unrelated_load:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cbz x0, .LBB10_2 ; CHECK-NEXT: cbz x0, .LBB10_2
; CHECK-NEXT: // %bb.1: // %not_null ; CHECK-NEXT: // %bb.1: // %not_null
; CHECK-NEXT: ldr w8, [x1] ; CHECK-NEXT: ldr w8, [x1]
; CHECK-NEXT: ldr w0, [x0] ; CHECK-NEXT: ldr w0, [x0]
; CHECK-NEXT: str w8, [x2] ; CHECK-NEXT: str w8, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB10_2: // %is_null ; CHECK-NEXT: .LBB10_2:
; CHECK-NEXT: mov w0, #42 ; CHECK-NEXT: mov w0, #42
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%c = icmp eq i32* %x, null %c = icmp eq i32* %x, null
br i1 %c, label %is_null, label %not_null, !make.implicit !0 br i1 %c, label %is_null, label %not_null, !make.implicit !0
is_null: is_null:
ret i32 42 ret i32 42
Show All 10 Lines
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: .Ltmp7: ; CHECK-NEXT: .Ltmp7:
; CHECK-NEXT: ldr w8, [x0] // on-fault: .LBB11_2 ; CHECK-NEXT: ldr w8, [x0] // on-fault: .LBB11_2
; CHECK-NEXT: // %bb.1: // %not_null ; CHECK-NEXT: // %bb.1: // %not_null
; CHECK-NEXT: add w9, w0, w1 ; CHECK-NEXT: add w9, w0, w1
; CHECK-NEXT: add w8, w9, w8 ; CHECK-NEXT: add w8, w9, w8
; CHECK-NEXT: add w0, w8, #4 // =4 ; CHECK-NEXT: add w0, w8, #4 // =4
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB11_2: // %is_null ; CHECK-NEXT: .LBB11_2:
; CHECK-NEXT: mov w0, #42 ; CHECK-NEXT: mov w0, #42
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%c = icmp eq i32* %x, null %c = icmp eq i32* %x, null
br i1 %c, label %is_null, label %not_null, !make.implicit !0 br i1 %c, label %is_null, label %not_null, !make.implicit !0
is_null: is_null:
ret i32 42 ret i32 42
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define i32 @imp_null_check_load_fence1(i32* %x) { define i32 @imp_null_check_load_fence1(i32* %x) {
; CHECK-LABEL: imp_null_check_load_fence1: ; CHECK-LABEL: imp_null_check_load_fence1:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cbz x0, .LBB12_2 ; CHECK-NEXT: cbz x0, .LBB12_2
; CHECK-NEXT: // %bb.1: // %not_null ; CHECK-NEXT: // %bb.1: // %not_null
; CHECK-NEXT: dmb ishld ; CHECK-NEXT: dmb ishld
; CHECK-NEXT: ldr w0, [x0] ; CHECK-NEXT: ldr w0, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB12_2: // %is_null ; CHECK-NEXT: .LBB12_2:
; CHECK-NEXT: mov w0, #42 ; CHECK-NEXT: mov w0, #42
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%c = icmp eq i32* %x, null %c = icmp eq i32* %x, null
br i1 %c, label %is_null, label %not_null, !make.implicit !0 br i1 %c, label %is_null, label %not_null, !make.implicit !0
is_null: is_null:
ret i32 42 ret i32 42
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define i32 @imp_null_check_load_fence2(i32* %x) { define i32 @imp_null_check_load_fence2(i32* %x) {
; CHECK-LABEL: imp_null_check_load_fence2: ; CHECK-LABEL: imp_null_check_load_fence2:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cbz x0, .LBB13_2 ; CHECK-NEXT: cbz x0, .LBB13_2
; CHECK-NEXT: // %bb.1: // %not_null ; CHECK-NEXT: // %bb.1: // %not_null
; CHECK-NEXT: dmb ish ; CHECK-NEXT: dmb ish
; CHECK-NEXT: ldr w0, [x0] ; CHECK-NEXT: ldr w0, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB13_2: // %is_null ; CHECK-NEXT: .LBB13_2:
; CHECK-NEXT: mov w0, #42 ; CHECK-NEXT: mov w0, #42
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%c = icmp eq i32* %x, null %c = icmp eq i32* %x, null
br i1 %c, label %is_null, label %not_null, !make.implicit !0 br i1 %c, label %is_null, label %not_null, !make.implicit !0
is_null: is_null:
ret i32 42 ret i32 42
not_null: not_null:
fence seq_cst fence seq_cst
%t = load i32, i32* %x %t = load i32, i32* %x
ret i32 %t ret i32 %t
} }
; TODO: We can fold to implicit null here, not sure why this isn't working ; TODO: We can fold to implicit null here, not sure why this isn't working
define void @imp_null_check_store(i32* %x) { define void @imp_null_check_store(i32* %x) {
; CHECK-LABEL: imp_null_check_store: ; CHECK-LABEL: imp_null_check_store:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cbz x0, .LBB14_2 ; CHECK-NEXT: cbz x0, .LBB14_2
; CHECK-NEXT: // %bb.1: // %not_null ; CHECK-NEXT: // %bb.1: // %not_null
; CHECK-NEXT: mov w8, #1 ; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: str w8, [x0] ; CHECK-NEXT: str w8, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: .LBB14_2: // %common.ret
; CHECK-NEXT: .LBB14_2: // %is_null
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%c = icmp eq i32* %x, null %c = icmp eq i32* %x, null
br i1 %c, label %is_null, label %not_null, !make.implicit !0 br i1 %c, label %is_null, label %not_null, !make.implicit !0
is_null: is_null:
ret void ret void
not_null: not_null:
store i32 1, i32* %x store i32 1, i32* %x
ret void ret void
} }
;; TODO: can be implicit ;; TODO: can be implicit
define void @imp_null_check_unordered_store(i32* %x) { define void @imp_null_check_unordered_store(i32* %x) {
; CHECK-LABEL: imp_null_check_unordered_store: ; CHECK-LABEL: imp_null_check_unordered_store:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cbz x0, .LBB15_2 ; CHECK-NEXT: cbz x0, .LBB15_2
; CHECK-NEXT: // %bb.1: // %not_null ; CHECK-NEXT: // %bb.1: // %not_null
; CHECK-NEXT: mov w8, #1 ; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: str w8, [x0] ; CHECK-NEXT: str w8, [x0]
; CHECK-NEXT: ret ; CHECK-NEXT: .LBB15_2: // %common.ret
; CHECK-NEXT: .LBB15_2: // %is_null
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%c = icmp eq i32* %x, null %c = icmp eq i32* %x, null
br i1 %c, label %is_null, label %not_null, !make.implicit !0 br i1 %c, label %is_null, label %not_null, !make.implicit !0
is_null: is_null:
ret void ret void
not_null: not_null:
store atomic i32 1, i32* %x unordered, align 4 store atomic i32 1, i32* %x unordered, align 4
ret void ret void
} }
define i32 @imp_null_check_neg_gep_load(i32* %x) { define i32 @imp_null_check_neg_gep_load(i32* %x) {
; CHECK-LABEL: imp_null_check_neg_gep_load: ; CHECK-LABEL: imp_null_check_neg_gep_load:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: .Ltmp8: ; CHECK-NEXT: .Ltmp8:
; CHECK-NEXT: ldur w0, [x0, #-128] // on-fault: .LBB16_2 ; CHECK-NEXT: ldur w0, [x0, #-128] // on-fault: .LBB16_2
; CHECK-NEXT: // %bb.1: // %not_null ; CHECK-NEXT: // %bb.1: // %not_null
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB16_2: // %is_null ; CHECK-NEXT: .LBB16_2:
; CHECK-NEXT: mov w0, #42 ; CHECK-NEXT: mov w0, #42
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%c = icmp eq i32* %x, null %c = icmp eq i32* %x, null
br i1 %c, label %is_null, label %not_null, !make.implicit !0 br i1 %c, label %is_null, label %not_null, !make.implicit !0
is_null: is_null:
ret i32 42 ret i32 42
not_null: not_null:
%x.gep = getelementptr i32, i32* %x, i32 -32 %x.gep = getelementptr i32, i32* %x, i32 -32
%t = load i32, i32* %x.gep %t = load i32, i32* %x.gep
ret i32 %t ret i32 %t
} }
!0 = !{} !0 = !{}

llvm/test/CodeGen/AArch64/ldst-opt-after-block-placement.ll

Show All 14 Lines
; CHECK-NEXT: b.lt .LBB0_3 ; CHECK-NEXT: b.lt .LBB0_3
; CHECK-NEXT: b .LBB0_4 ; CHECK-NEXT: b .LBB0_4
; CHECK-NEXT: .LBB0_2: // %if.else ; CHECK-NEXT: .LBB0_2: // %if.else
; CHECK-NEXT: ldp x8, x9, [x1] ; CHECK-NEXT: ldp x8, x9, [x1]
; CHECK-NEXT: cmp x8, x9 ; CHECK-NEXT: cmp x8, x9
; CHECK-NEXT: b.ge .LBB0_4 ; CHECK-NEXT: b.ge .LBB0_4
; CHECK-NEXT: .LBB0_3: // %exit1 ; CHECK-NEXT: .LBB0_3: // %exit1
; CHECK-NEXT: str xzr, [x1, #8] ; CHECK-NEXT: str xzr, [x1, #8]
; CHECK-NEXT: .LBB0_4: // %exit2 ; CHECK-NEXT: .LBB0_4: // %common.ret
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
br i1 %cond, label %if.then, label %if.else br i1 %cond, label %if.then, label %if.else
if.then: if.then:
%0 = getelementptr inbounds i64, i64* %ptr, i64 2 %0 = getelementptr inbounds i64, i64* %ptr, i64 2
%1 = load i64, i64* %0, align 8 %1 = load i64, i64* %0, align 8
store i64 0, i64* %0, align 8 store i64 0, i64* %0, align 8
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llvm/test/CodeGen/AArch64/ldst-paired-aliasing.ll

Show All 26 Lines
; CHECK-NEXT: ldr w8, [sp, #48] ; CHECK-NEXT: ldr w8, [sp, #48]
; CHECK-NEXT: cmp w8, #1 // =1 ; CHECK-NEXT: cmp w8, #1 // =1
; CHECK-NEXT: b.ne .LBB0_2 ; CHECK-NEXT: b.ne .LBB0_2
; CHECK-NEXT: // %bb.1: // %for.inc ; CHECK-NEXT: // %bb.1: // %for.inc
; CHECK-NEXT: bl f ; CHECK-NEXT: bl f
; CHECK-NEXT: b .LBB0_3 ; CHECK-NEXT: b .LBB0_3
; CHECK-NEXT: .LBB0_2: // %if.then ; CHECK-NEXT: .LBB0_2: // %if.then
; CHECK-NEXT: bl f2 ; CHECK-NEXT: bl f2
; CHECK-NEXT: .LBB0_3: // %for.inc ; CHECK-NEXT: .LBB0_3: // %common.ret
; CHECK-NEXT: ldr x30, [sp, #96] // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp, #96] // 8-byte Folded Reload
; CHECK-NEXT: mov w0, wzr ; CHECK-NEXT: mov w0, wzr
; CHECK-NEXT: add sp, sp, #112 // =112 ; CHECK-NEXT: add sp, sp, #112 // =112
; CHECK-NEXT: ret ; CHECK-NEXT: ret
for.body.lr.ph.i.i.i.i.i.i63: for.body.lr.ph.i.i.i.i.i.i63:
%b1 = alloca [10 x i32], align 16 %b1 = alloca [10 x i32], align 16
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llvm/test/CodeGen/AArch64/logical_shifted_reg.ll

Show First 20 Lines • Show All 259 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ldr x9, [x8] ; CHECK-NEXT: ldr x9, [x8]
; CHECK-NEXT: ldr x10, [x10] ; CHECK-NEXT: ldr x10, [x10]
; CHECK-NEXT: tst x9, x10 ; CHECK-NEXT: tst x9, x10
; CHECK-NEXT: b.gt .LBB2_4 ; CHECK-NEXT: b.gt .LBB2_4
; CHECK-NEXT: // %bb.1: // %test2 ; CHECK-NEXT: // %bb.1: // %test2
; CHECK-NEXT: tst x9, x10, lsl #63 ; CHECK-NEXT: tst x9, x10, lsl #63
; CHECK-NEXT: b.lt .LBB2_4 ; CHECK-NEXT: b.lt .LBB2_4
; CHECK-NEXT: // %bb.2: // %test3 ; CHECK-NEXT: // %bb.2: // %test3
; CHECK-NEXT: tst x9, x10, asr #12 ; CHECK-NEXT: and x10, x9, x10, asr #12
; CHECK-NEXT: b.gt .LBB2_4 ; CHECK-NEXT: cmp x10, #1 // =1
; CHECK-NEXT: b.ge .LBB2_4
; CHECK-NEXT: // %bb.3: // %other_exit ; CHECK-NEXT: // %bb.3: // %other_exit
; CHECK-NEXT: str x9, [x8] ; CHECK-NEXT: str x9, [x8]
; CHECK-NEXT: .LBB2_4: // %ret ; CHECK-NEXT: .LBB2_4: // %common.ret
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%val1 = load i64, i64* @var1_64 %val1 = load i64, i64* @var1_64
%val2 = load i64, i64* @var2_64 %val2 = load i64, i64* @var2_64
%simple_and = and i64 %val1, %val2 %simple_and = and i64 %val1, %val2
%tst1 = icmp sgt i64 %simple_and, 0 %tst1 = icmp sgt i64 %simple_and, 0
br i1 %tst1, label %ret, label %test2, !prof !1 br i1 %tst1, label %ret, label %test2, !prof !1
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llvm/test/CodeGen/AArch64/optimize-cond-branch.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -o - %s | FileCheck %s ; RUN: llc -verify-machineinstrs -o - %s | FileCheck %s
target triple = "arm64--" target triple = "arm64--"
; AArch64InstrInfo::optimizeCondBranch() optimizes the ; AArch64InstrInfo::optimizeCondBranch() optimizes the
; "x = and y, 256; cmp x, 0; br" from an "and; cbnz" to a tbnz instruction. ; "x = and y, 256; cmp x, 0; br" from an "and; cbnz" to a tbnz instruction.
; It forgot to clear the a flag resulting in a MachineVerifier complaint. ; It forgot to clear the a flag resulting in a MachineVerifier complaint.
; ;
; Writing a stable/simple test is tricky since most tbz instructions are already ; Writing a stable/simple test is tricky since most tbz instructions are already
; formed in SelectionDAG, optimizeCondBranch() only triggers if the and ; formed in SelectionDAG, optimizeCondBranch() only triggers if the and
; instruction is in a different block than the conditional jump. ; instruction is in a different block than the conditional jump.
define void @func() { define void @func() {
; CHECK-LABEL: func: ; CHECK-LABEL: func:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: mov w8, #1 ; CHECK-NEXT: mov w8, #1
; CHECK-NEXT: cbnz w8, .LBB0_3 ; CHECK-NEXT: cbnz w8, .LBB0_3
; CHECK-NEXT: // %bb.1: // %b1 ; CHECK-NEXT: // %bb.1: // %b1
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: cbz wzr, .LBB0_4 ; CHECK-NEXT: cbz wzr, .LBB0_4
; CHECK-NEXT: // %bb.2: // %b3 ; CHECK-NEXT: // %bb.2: // %b3
; CHECK-NEXT: ldr w8, [x8] ; CHECK-NEXT: ldr w8, [x8]
; CHECK-NEXT: tbz w8, #8, .LBB0_5 ; CHECK-NEXT: and w0, w8, #0x100
; CHECK-NEXT: .LBB0_3: // %b7
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: cbz w0, .LBB0_5
; CHECK-NEXT: .LBB0_3: // %common.ret.sink.split
; CHECK-NEXT: b extfunc ; CHECK-NEXT: b extfunc
; CHECK-NEXT: .LBB0_4: // %b2 ; CHECK-NEXT: .LBB0_4: // %b2
; CHECK-NEXT: bl extfunc ; CHECK-NEXT: bl extfunc
; CHECK-NEXT: cbnz w0, .LBB0_3
; CHECK-NEXT: .LBB0_5: // %b8
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: cbnz w0, .LBB0_3
; CHECK-NEXT: .LBB0_5: // %common.ret
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c0 = icmp sgt i64 0, 0 %c0 = icmp sgt i64 0, 0
br i1 %c0, label %b1, label %b6 br i1 %c0, label %b1, label %b6
b1: b1:
br i1 undef, label %b3, label %b2 br i1 undef, label %b3, label %b2
b2: b2:
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llvm/test/CodeGen/AArch64/statepoint-call-lowering.ll

Show First 20 Lines • Show All 141 Lines • ▼ Show 20 Lines
; CHECK-NEXT: str x0, [sp, #8] ; CHECK-NEXT: str x0, [sp, #8]
; CHECK-NEXT: bl return_i1 ; CHECK-NEXT: bl return_i1
; CHECK-NEXT: .Ltmp10: ; CHECK-NEXT: .Ltmp10:
; CHECK-NEXT: tbz w20, #0, .LBB8_2 ; CHECK-NEXT: tbz w20, #0, .LBB8_2
; CHECK-NEXT: // %bb.1: // %left ; CHECK-NEXT: // %bb.1: // %left
; CHECK-NEXT: mov w19, w0 ; CHECK-NEXT: mov w19, w0
; CHECK-NEXT: ldr x0, [sp, #8] ; CHECK-NEXT: ldr x0, [sp, #8]
; CHECK-NEXT: bl consume ; CHECK-NEXT: bl consume
; CHECK-NEXT: and w0, w19, #0x1
; CHECK-NEXT: b .LBB8_3 ; CHECK-NEXT: b .LBB8_3
; CHECK-NEXT: .LBB8_2: // %right ; CHECK-NEXT: .LBB8_2:
; CHECK-NEXT: mov w0, #1 ; CHECK-NEXT: mov w19, #1
; CHECK-NEXT: .LBB8_3: // %right ; CHECK-NEXT: .LBB8_3: // %common.ret
; CHECK-NEXT: and w0, w19, #0x1
; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload ; CHECK-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: ldr x30, [sp], #32 // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp], #32 // 8-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%safepoint_token = tail call token (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @return_i1, i32 0, i32 0, i32 0, i32 0) ["gc-live" (i32 addrspace(1)* %a)] %safepoint_token = tail call token (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @return_i1, i32 0, i32 0, i32 0, i32 0) ["gc-live" (i32 addrspace(1)* %a)]
br i1 %external_cond, label %left, label %right br i1 %external_cond, label %left, label %right
left: left:
▲ Show 20 Lines • Show All 56 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/sve-breakdown-scalable-vectortype.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve < %s | FileCheck %s ; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve < %s | FileCheck %s
; Test that scalable vectors that are a multiple of the legal vector size ; Test that scalable vectors that are a multiple of the legal vector size
; can be properly broken down into part vectors. ; can be properly broken down into part vectors.
declare void @bar() declare void @bar()
; ;
; Vectors twice the size ; Vectors twice the size
; ;
define <vscale x 32 x i8> @wide_32i8(i1 %b, <vscale x 16 x i8> %legal, <vscale x 32 x i8> %illegal) nounwind { define <vscale x 32 x i8> @wide_32i8(i1 %b, <vscale x 16 x i8> %legal, <vscale x 32 x i8> %illegal) nounwind {
; CHECK-LABEL: wide_32i8: ; CHECK-LABEL: wide_32i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: tbz w0, #0, .LBB0_2 ; CHECK-NEXT: tbz w0, #0, .LBB0_2
; CHECK-NEXT: // %bb.1: // %L1 ; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-18 ; CHECK-NEXT: addvl sp, sp, #-18
; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill
Show All 16 Lines
; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: str z2, [sp, #1, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl bar ; CHECK-NEXT: bl bar
; CHECK-NEXT: ldr z0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr z2, [sp, #1, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload
Show All 14 Lines
; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #18 ; CHECK-NEXT: addvl sp, sp, #18
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: .LBB0_2: // %common.ret
; CHECK-NEXT: .LBB0_2: // %L2
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: mov z1.d, z2.d ; CHECK-NEXT: mov z1.d, z2.d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
br i1 %b, label %L1, label %L2 br i1 %b, label %L1, label %L2
L1: L1:
call void @bar() call void @bar()
ret <vscale x 32 x i8> undef ret <vscale x 32 x i8> undef
L2: L2:
ret <vscale x 32 x i8> %illegal ret <vscale x 32 x i8> %illegal
} }
define <vscale x 16 x i16> @wide_16i16(i1 %b, <vscale x 16 x i8> %legal, <vscale x 16 x i16> %illegal) nounwind { define <vscale x 16 x i16> @wide_16i16(i1 %b, <vscale x 16 x i8> %legal, <vscale x 16 x i16> %illegal) nounwind {
; CHECK-LABEL: wide_16i16: ; CHECK-LABEL: wide_16i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: tbz w0, #0, .LBB1_2 ; CHECK-NEXT: tbz w0, #0, .LBB1_2
; CHECK-NEXT: // %bb.1: // %L1 ; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-18 ; CHECK-NEXT: addvl sp, sp, #-18
; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill
Show All 16 Lines
; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: str z2, [sp, #1, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl bar ; CHECK-NEXT: bl bar
; CHECK-NEXT: ldr z0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr z2, [sp, #1, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload
Show All 14 Lines
; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #18 ; CHECK-NEXT: addvl sp, sp, #18
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: .LBB1_2: // %common.ret
; CHECK-NEXT: .LBB1_2: // %L2
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: mov z1.d, z2.d ; CHECK-NEXT: mov z1.d, z2.d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
br i1 %b, label %L1, label %L2 br i1 %b, label %L1, label %L2
L1: L1:
call void @bar() call void @bar()
ret <vscale x 16 x i16> undef ret <vscale x 16 x i16> undef
L2: L2:
ret <vscale x 16 x i16> %illegal ret <vscale x 16 x i16> %illegal
} }
define <vscale x 8 x i32> @wide_8i32(i1 %b, <vscale x 16 x i8> %legal, <vscale x 8 x i32> %illegal) nounwind { define <vscale x 8 x i32> @wide_8i32(i1 %b, <vscale x 16 x i8> %legal, <vscale x 8 x i32> %illegal) nounwind {
; CHECK-LABEL: wide_8i32: ; CHECK-LABEL: wide_8i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: tbz w0, #0, .LBB2_2 ; CHECK-NEXT: tbz w0, #0, .LBB2_2
; CHECK-NEXT: // %bb.1: // %L1 ; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-18 ; CHECK-NEXT: addvl sp, sp, #-18
; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill
Show All 16 Lines
; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: str z2, [sp, #1, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl bar ; CHECK-NEXT: bl bar
; CHECK-NEXT: ldr z0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr z2, [sp, #1, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload
Show All 14 Lines
; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #18 ; CHECK-NEXT: addvl sp, sp, #18
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: .LBB2_2: // %common.ret
; CHECK-NEXT: .LBB2_2: // %L2
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: mov z1.d, z2.d ; CHECK-NEXT: mov z1.d, z2.d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
br i1 %b, label %L1, label %L2 br i1 %b, label %L1, label %L2
L1: L1:
call void @bar() call void @bar()
ret <vscale x 8 x i32> undef ret <vscale x 8 x i32> undef
L2: L2:
ret <vscale x 8 x i32> %illegal ret <vscale x 8 x i32> %illegal
} }
define <vscale x 4 x i64> @wide_4i64(i1 %b, <vscale x 16 x i8> %legal, <vscale x 4 x i64> %illegal) nounwind { define <vscale x 4 x i64> @wide_4i64(i1 %b, <vscale x 16 x i8> %legal, <vscale x 4 x i64> %illegal) nounwind {
; CHECK-LABEL: wide_4i64: ; CHECK-LABEL: wide_4i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: tbz w0, #0, .LBB3_2 ; CHECK-NEXT: tbz w0, #0, .LBB3_2
; CHECK-NEXT: // %bb.1: // %L1 ; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-18 ; CHECK-NEXT: addvl sp, sp, #-18
; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill
Show All 16 Lines
; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: str z2, [sp, #1, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl bar ; CHECK-NEXT: bl bar
; CHECK-NEXT: ldr z0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr z2, [sp, #1, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload
Show All 14 Lines
; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #18 ; CHECK-NEXT: addvl sp, sp, #18
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: .LBB3_2: // %common.ret
; CHECK-NEXT: .LBB3_2: // %L2
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: mov z1.d, z2.d ; CHECK-NEXT: mov z1.d, z2.d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
br i1 %b, label %L1, label %L2 br i1 %b, label %L1, label %L2
L1: L1:
call void @bar() call void @bar()
ret <vscale x 4 x i64> undef ret <vscale x 4 x i64> undef
L2: L2:
ret <vscale x 4 x i64> %illegal ret <vscale x 4 x i64> %illegal
} }
define <vscale x 16 x half> @wide_16f16(i1 %b, <vscale x 16 x i8> %legal, <vscale x 16 x half> %illegal) nounwind { define <vscale x 16 x half> @wide_16f16(i1 %b, <vscale x 16 x i8> %legal, <vscale x 16 x half> %illegal) nounwind {
; CHECK-LABEL: wide_16f16: ; CHECK-LABEL: wide_16f16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: tbz w0, #0, .LBB4_2 ; CHECK-NEXT: tbz w0, #0, .LBB4_2
; CHECK-NEXT: // %bb.1: // %L1 ; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-18 ; CHECK-NEXT: addvl sp, sp, #-18
; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill
Show All 16 Lines
; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: str z2, [sp, #1, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl bar ; CHECK-NEXT: bl bar
; CHECK-NEXT: ldr z0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr z2, [sp, #1, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload
Show All 14 Lines
; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #18 ; CHECK-NEXT: addvl sp, sp, #18
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: .LBB4_2: // %common.ret
; CHECK-NEXT: .LBB4_2: // %L2
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: mov z1.d, z2.d ; CHECK-NEXT: mov z1.d, z2.d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
br i1 %b, label %L1, label %L2 br i1 %b, label %L1, label %L2
L1: L1:
call void @bar() call void @bar()
ret <vscale x 16 x half> undef ret <vscale x 16 x half> undef
L2: L2:
ret <vscale x 16 x half> %illegal ret <vscale x 16 x half> %illegal
} }
define <vscale x 8 x float> @wide_8f32(i1 %b, <vscale x 16 x i8> %legal, <vscale x 8 x float> %illegal) nounwind { define <vscale x 8 x float> @wide_8f32(i1 %b, <vscale x 16 x i8> %legal, <vscale x 8 x float> %illegal) nounwind {
; CHECK-LABEL: wide_8f32: ; CHECK-LABEL: wide_8f32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: tbz w0, #0, .LBB5_2 ; CHECK-NEXT: tbz w0, #0, .LBB5_2
; CHECK-NEXT: // %bb.1: // %L1 ; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-18 ; CHECK-NEXT: addvl sp, sp, #-18
; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill
Show All 16 Lines
; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: str z2, [sp, #1, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl bar ; CHECK-NEXT: bl bar
; CHECK-NEXT: ldr z0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr z2, [sp, #1, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload
Show All 14 Lines
; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #18 ; CHECK-NEXT: addvl sp, sp, #18
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: .LBB5_2: // %common.ret
; CHECK-NEXT: .LBB5_2: // %L2
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: mov z1.d, z2.d ; CHECK-NEXT: mov z1.d, z2.d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
br i1 %b, label %L1, label %L2 br i1 %b, label %L1, label %L2
L1: L1:
call void @bar() call void @bar()
ret <vscale x 8 x float> undef ret <vscale x 8 x float> undef
L2: L2:
ret <vscale x 8 x float> %illegal ret <vscale x 8 x float> %illegal
} }
define <vscale x 4 x double> @wide_4f64(i1 %b, <vscale x 16 x i8> %legal, <vscale x 4 x double> %illegal) nounwind { define <vscale x 4 x double> @wide_4f64(i1 %b, <vscale x 16 x i8> %legal, <vscale x 4 x double> %illegal) nounwind {
; CHECK-LABEL: wide_4f64: ; CHECK-LABEL: wide_4f64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: tbz w0, #0, .LBB6_2 ; CHECK-NEXT: tbz w0, #0, .LBB6_2
; CHECK-NEXT: // %bb.1: // %L1 ; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-18 ; CHECK-NEXT: addvl sp, sp, #-18
; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill
Show All 16 Lines
; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-2
; CHECK-NEXT: str z2, [sp, #1, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl bar ; CHECK-NEXT: bl bar
; CHECK-NEXT: ldr z0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr z2, [sp, #1, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload
Show All 14 Lines
; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #18 ; CHECK-NEXT: addvl sp, sp, #18
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: .LBB6_2: // %common.ret
; CHECK-NEXT: .LBB6_2: // %L2
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: mov z1.d, z2.d ; CHECK-NEXT: mov z1.d, z2.d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
br i1 %b, label %L1, label %L2 br i1 %b, label %L1, label %L2
L1: L1:
call void @bar() call void @bar()
ret <vscale x 4 x double> undef ret <vscale x 4 x double> undef
L2: L2:
ret <vscale x 4 x double> %illegal ret <vscale x 4 x double> %illegal
} }
; ;
; Vectors three times the size ; Vectors three times the size
; ;
define <vscale x 48 x i8> @wide_48i8(i1 %b, <vscale x 16 x i8> %legal, <vscale x 48 x i8> %illegal) nounwind { define <vscale x 48 x i8> @wide_48i8(i1 %b, <vscale x 16 x i8> %legal, <vscale x 48 x i8> %illegal) nounwind {
; CHECK-LABEL: wide_48i8: ; CHECK-LABEL: wide_48i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: tbz w0, #0, .LBB7_2 ; CHECK-NEXT: tbz w0, #0, .LBB7_2
; CHECK-NEXT: // %bb.1: // %L1 ; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-18 ; CHECK-NEXT: addvl sp, sp, #-18
; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill
Show All 16 Lines
; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-3
; CHECK-NEXT: str z3, [sp, #2, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z2, [sp, #1, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl bar ; CHECK-NEXT: bl bar
; CHECK-NEXT: ldr z0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr z2, [sp, #1, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z3, [sp, #2, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #3
; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload
Show All 14 Lines
; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #18 ; CHECK-NEXT: addvl sp, sp, #18
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: .LBB7_2: // %common.ret
; CHECK-NEXT: .LBB7_2: // %L2
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: mov z1.d, z2.d ; CHECK-NEXT: mov z1.d, z2.d
; CHECK-NEXT: mov z2.d, z3.d ; CHECK-NEXT: mov z2.d, z3.d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
br i1 %b, label %L1, label %L2 br i1 %b, label %L1, label %L2
L1: L1:
call void @bar() call void @bar()
ret <vscale x 48 x i8> undef ret <vscale x 48 x i8> undef
L2: L2:
ret <vscale x 48 x i8> %illegal ret <vscale x 48 x i8> %illegal
} }
define <vscale x 24 x i16> @wide_24i16(i1 %b, <vscale x 16 x i8> %legal, <vscale x 24 x i16> %illegal) nounwind { define <vscale x 24 x i16> @wide_24i16(i1 %b, <vscale x 16 x i8> %legal, <vscale x 24 x i16> %illegal) nounwind {
; CHECK-LABEL: wide_24i16: ; CHECK-LABEL: wide_24i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: tbz w0, #0, .LBB8_2 ; CHECK-NEXT: tbz w0, #0, .LBB8_2
; CHECK-NEXT: // %bb.1: // %L1 ; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-18 ; CHECK-NEXT: addvl sp, sp, #-18
; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill
Show All 16 Lines
; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-3
; CHECK-NEXT: str z3, [sp, #2, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z2, [sp, #1, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl bar ; CHECK-NEXT: bl bar
; CHECK-NEXT: ldr z0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr z2, [sp, #1, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z3, [sp, #2, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #3
; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload
Show All 14 Lines
; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #18 ; CHECK-NEXT: addvl sp, sp, #18
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: .LBB8_2: // %common.ret
; CHECK-NEXT: .LBB8_2: // %L2
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: mov z1.d, z2.d ; CHECK-NEXT: mov z1.d, z2.d
; CHECK-NEXT: mov z2.d, z3.d ; CHECK-NEXT: mov z2.d, z3.d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
br i1 %b, label %L1, label %L2 br i1 %b, label %L1, label %L2
L1: L1:
call void @bar() call void @bar()
ret <vscale x 24 x i16> undef ret <vscale x 24 x i16> undef
L2: L2:
ret <vscale x 24 x i16> %illegal ret <vscale x 24 x i16> %illegal
} }
define <vscale x 12 x i32> @wide_12i32(i1 %b, <vscale x 16 x i8> %legal, <vscale x 12 x i32> %illegal) nounwind { define <vscale x 12 x i32> @wide_12i32(i1 %b, <vscale x 16 x i8> %legal, <vscale x 12 x i32> %illegal) nounwind {
; CHECK-LABEL: wide_12i32: ; CHECK-LABEL: wide_12i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: tbz w0, #0, .LBB9_2 ; CHECK-NEXT: tbz w0, #0, .LBB9_2
; CHECK-NEXT: // %bb.1: // %L1 ; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-18 ; CHECK-NEXT: addvl sp, sp, #-18
; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill
Show All 16 Lines
; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-3
; CHECK-NEXT: str z3, [sp, #2, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z2, [sp, #1, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl bar ; CHECK-NEXT: bl bar
; CHECK-NEXT: ldr z0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr z2, [sp, #1, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z3, [sp, #2, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #3
; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload
Show All 14 Lines
; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #18 ; CHECK-NEXT: addvl sp, sp, #18
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: .LBB9_2: // %common.ret
; CHECK-NEXT: .LBB9_2: // %L2
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: mov z1.d, z2.d ; CHECK-NEXT: mov z1.d, z2.d
; CHECK-NEXT: mov z2.d, z3.d ; CHECK-NEXT: mov z2.d, z3.d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
br i1 %b, label %L1, label %L2 br i1 %b, label %L1, label %L2
L1: L1:
call void @bar() call void @bar()
ret <vscale x 12 x i32> undef ret <vscale x 12 x i32> undef
L2: L2:
ret <vscale x 12 x i32> %illegal ret <vscale x 12 x i32> %illegal
} }
define <vscale x 6 x i64> @wide_6i64(i1 %b, <vscale x 16 x i8> %legal, <vscale x 6 x i64> %illegal) nounwind { define <vscale x 6 x i64> @wide_6i64(i1 %b, <vscale x 16 x i8> %legal, <vscale x 6 x i64> %illegal) nounwind {
; CHECK-LABEL: wide_6i64: ; CHECK-LABEL: wide_6i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: tbz w0, #0, .LBB10_2 ; CHECK-NEXT: tbz w0, #0, .LBB10_2
; CHECK-NEXT: // %bb.1: // %L1 ; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-18 ; CHECK-NEXT: addvl sp, sp, #-18
; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill
Show All 16 Lines
; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-3
; CHECK-NEXT: str z3, [sp, #2, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z2, [sp, #1, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl bar ; CHECK-NEXT: bl bar
; CHECK-NEXT: ldr z0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr z2, [sp, #1, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z3, [sp, #2, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #3
; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload
Show All 14 Lines
; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #18 ; CHECK-NEXT: addvl sp, sp, #18
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: .LBB10_2: // %common.ret
; CHECK-NEXT: .LBB10_2: // %L2
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: mov z1.d, z2.d ; CHECK-NEXT: mov z1.d, z2.d
; CHECK-NEXT: mov z2.d, z3.d ; CHECK-NEXT: mov z2.d, z3.d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
br i1 %b, label %L1, label %L2 br i1 %b, label %L1, label %L2
L1: L1:
call void @bar() call void @bar()
ret <vscale x 6 x i64> undef ret <vscale x 6 x i64> undef
L2: L2:
ret <vscale x 6 x i64> %illegal ret <vscale x 6 x i64> %illegal
} }
define <vscale x 24 x half> @wide_24f16(i1 %b, <vscale x 16 x i8> %legal, <vscale x 24 x half> %illegal) nounwind { define <vscale x 24 x half> @wide_24f16(i1 %b, <vscale x 16 x i8> %legal, <vscale x 24 x half> %illegal) nounwind {
; CHECK-LABEL: wide_24f16: ; CHECK-LABEL: wide_24f16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: tbz w0, #0, .LBB11_2 ; CHECK-NEXT: tbz w0, #0, .LBB11_2
; CHECK-NEXT: // %bb.1: // %L1 ; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-18 ; CHECK-NEXT: addvl sp, sp, #-18
; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill
Show All 16 Lines
; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-3
; CHECK-NEXT: str z3, [sp, #2, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z2, [sp, #1, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl bar ; CHECK-NEXT: bl bar
; CHECK-NEXT: ldr z0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr z2, [sp, #1, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z3, [sp, #2, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #3
; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload
Show All 14 Lines
; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #18 ; CHECK-NEXT: addvl sp, sp, #18
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: .LBB11_2: // %common.ret
; CHECK-NEXT: .LBB11_2: // %L2
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: mov z1.d, z2.d ; CHECK-NEXT: mov z1.d, z2.d
; CHECK-NEXT: mov z2.d, z3.d ; CHECK-NEXT: mov z2.d, z3.d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
br i1 %b, label %L1, label %L2 br i1 %b, label %L1, label %L2
L1: L1:
call void @bar() call void @bar()
ret <vscale x 24 x half> undef ret <vscale x 24 x half> undef
L2: L2:
ret <vscale x 24 x half> %illegal ret <vscale x 24 x half> %illegal
} }
define <vscale x 12 x float> @wide_12f32(i1 %b, <vscale x 16 x i8> %legal, <vscale x 12 x float> %illegal) nounwind { define <vscale x 12 x float> @wide_12f32(i1 %b, <vscale x 16 x i8> %legal, <vscale x 12 x float> %illegal) nounwind {
; CHECK-LABEL: wide_12f32: ; CHECK-LABEL: wide_12f32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: tbz w0, #0, .LBB12_2 ; CHECK-NEXT: tbz w0, #0, .LBB12_2
; CHECK-NEXT: // %bb.1: // %L1 ; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-18 ; CHECK-NEXT: addvl sp, sp, #-18
; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill
Show All 16 Lines
; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-3
; CHECK-NEXT: str z3, [sp, #2, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z2, [sp, #1, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl bar ; CHECK-NEXT: bl bar
; CHECK-NEXT: ldr z0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr z2, [sp, #1, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z3, [sp, #2, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #3
; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload
Show All 14 Lines
; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #18 ; CHECK-NEXT: addvl sp, sp, #18
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: .LBB12_2: // %common.ret
; CHECK-NEXT: .LBB12_2: // %L2
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: mov z1.d, z2.d ; CHECK-NEXT: mov z1.d, z2.d
; CHECK-NEXT: mov z2.d, z3.d ; CHECK-NEXT: mov z2.d, z3.d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
br i1 %b, label %L1, label %L2 br i1 %b, label %L1, label %L2
L1: L1:
call void @bar() call void @bar()
ret <vscale x 12 x float> undef ret <vscale x 12 x float> undef
L2: L2:
ret <vscale x 12 x float> %illegal ret <vscale x 12 x float> %illegal
} }
define <vscale x 6 x double> @wide_6f64(i1 %b, <vscale x 16 x i8> %legal, <vscale x 6 x double> %illegal) nounwind { define <vscale x 6 x double> @wide_6f64(i1 %b, <vscale x 16 x i8> %legal, <vscale x 6 x double> %illegal) nounwind {
; CHECK-LABEL: wide_6f64: ; CHECK-LABEL: wide_6f64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: tbz w0, #0, .LBB13_2 ; CHECK-NEXT: tbz w0, #0, .LBB13_2
; CHECK-NEXT: // %bb.1: // %L1 ; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-18 ; CHECK-NEXT: addvl sp, sp, #-18
; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill
Show All 16 Lines
; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-3
; CHECK-NEXT: str z3, [sp, #2, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z2, [sp, #1, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl bar ; CHECK-NEXT: bl bar
; CHECK-NEXT: ldr z0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr z2, [sp, #1, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z3, [sp, #2, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #3
; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload
Show All 14 Lines
; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #18 ; CHECK-NEXT: addvl sp, sp, #18
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: .LBB13_2: // %common.ret
; CHECK-NEXT: .LBB13_2: // %L2
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: mov z1.d, z2.d ; CHECK-NEXT: mov z1.d, z2.d
; CHECK-NEXT: mov z2.d, z3.d ; CHECK-NEXT: mov z2.d, z3.d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
br i1 %b, label %L1, label %L2 br i1 %b, label %L1, label %L2
L1: L1:
call void @bar() call void @bar()
ret <vscale x 6 x double> undef ret <vscale x 6 x double> undef
L2: L2:
ret <vscale x 6 x double> %illegal ret <vscale x 6 x double> %illegal
} }
; ;
; Vectors four times the size ; Vectors four times the size
; ;
define <vscale x 64 x i8> @wide_64i8(i1 %b, <vscale x 16 x i8> %legal, <vscale x 64 x i8> %illegal) nounwind { define <vscale x 64 x i8> @wide_64i8(i1 %b, <vscale x 16 x i8> %legal, <vscale x 64 x i8> %illegal) nounwind {
; CHECK-LABEL: wide_64i8: ; CHECK-LABEL: wide_64i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: tbz w0, #0, .LBB14_2 ; CHECK-NEXT: tbz w0, #0, .LBB14_2
; CHECK-NEXT: // %bb.1: // %L1 ; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-18 ; CHECK-NEXT: addvl sp, sp, #-18
; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill
Show All 16 Lines
; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-4
; CHECK-NEXT: str z4, [sp, #3, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z3, [sp, #2, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z2, [sp, #1, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl bar ; CHECK-NEXT: bl bar
; CHECK-NEXT: ldr z0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr z2, [sp, #1, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z3, [sp, #2, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z4, [sp, #3, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #4
; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload
Show All 14 Lines
; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #18 ; CHECK-NEXT: addvl sp, sp, #18
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: .LBB14_2: // %common.ret
; CHECK-NEXT: .LBB14_2: // %L2
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: mov z1.d, z2.d ; CHECK-NEXT: mov z1.d, z2.d
; CHECK-NEXT: mov z2.d, z3.d ; CHECK-NEXT: mov z2.d, z3.d
; CHECK-NEXT: mov z3.d, z4.d ; CHECK-NEXT: mov z3.d, z4.d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
br i1 %b, label %L1, label %L2 br i1 %b, label %L1, label %L2
L1: L1:
call void @bar() call void @bar()
ret <vscale x 64 x i8> undef ret <vscale x 64 x i8> undef
L2: L2:
ret <vscale x 64 x i8> %illegal ret <vscale x 64 x i8> %illegal
} }
define <vscale x 32 x i16> @wide_32i16(i1 %b, <vscale x 16 x i8> %legal, <vscale x 32 x i16> %illegal) nounwind { define <vscale x 32 x i16> @wide_32i16(i1 %b, <vscale x 16 x i8> %legal, <vscale x 32 x i16> %illegal) nounwind {
; CHECK-LABEL: wide_32i16: ; CHECK-LABEL: wide_32i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: tbz w0, #0, .LBB15_2 ; CHECK-NEXT: tbz w0, #0, .LBB15_2
; CHECK-NEXT: // %bb.1: // %L1 ; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-18 ; CHECK-NEXT: addvl sp, sp, #-18
; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill
Show All 16 Lines
; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-4
; CHECK-NEXT: str z4, [sp, #3, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z3, [sp, #2, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z2, [sp, #1, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl bar ; CHECK-NEXT: bl bar
; CHECK-NEXT: ldr z0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr z2, [sp, #1, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z3, [sp, #2, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z4, [sp, #3, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #4
; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload
Show All 14 Lines
; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #18 ; CHECK-NEXT: addvl sp, sp, #18
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: .LBB15_2: // %common.ret
; CHECK-NEXT: .LBB15_2: // %L2
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: mov z1.d, z2.d ; CHECK-NEXT: mov z1.d, z2.d
; CHECK-NEXT: mov z2.d, z3.d ; CHECK-NEXT: mov z2.d, z3.d
; CHECK-NEXT: mov z3.d, z4.d ; CHECK-NEXT: mov z3.d, z4.d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
br i1 %b, label %L1, label %L2 br i1 %b, label %L1, label %L2
L1: L1:
call void @bar() call void @bar()
ret <vscale x 32 x i16> undef ret <vscale x 32 x i16> undef
L2: L2:
ret <vscale x 32 x i16> %illegal ret <vscale x 32 x i16> %illegal
} }
define <vscale x 16 x i32> @wide_16i32(i1 %b, <vscale x 16 x i8> %legal, <vscale x 16 x i32> %illegal) nounwind { define <vscale x 16 x i32> @wide_16i32(i1 %b, <vscale x 16 x i8> %legal, <vscale x 16 x i32> %illegal) nounwind {
; CHECK-LABEL: wide_16i32: ; CHECK-LABEL: wide_16i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: tbz w0, #0, .LBB16_2 ; CHECK-NEXT: tbz w0, #0, .LBB16_2
; CHECK-NEXT: // %bb.1: // %L1 ; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-18 ; CHECK-NEXT: addvl sp, sp, #-18
; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill
Show All 16 Lines
; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-4
; CHECK-NEXT: str z4, [sp, #3, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z3, [sp, #2, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z2, [sp, #1, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl bar ; CHECK-NEXT: bl bar
; CHECK-NEXT: ldr z0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr z2, [sp, #1, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z3, [sp, #2, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z4, [sp, #3, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #4
; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload
Show All 14 Lines
; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #18 ; CHECK-NEXT: addvl sp, sp, #18
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: .LBB16_2: // %common.ret
; CHECK-NEXT: .LBB16_2: // %L2
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: mov z1.d, z2.d ; CHECK-NEXT: mov z1.d, z2.d
; CHECK-NEXT: mov z2.d, z3.d ; CHECK-NEXT: mov z2.d, z3.d
; CHECK-NEXT: mov z3.d, z4.d ; CHECK-NEXT: mov z3.d, z4.d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
br i1 %b, label %L1, label %L2 br i1 %b, label %L1, label %L2
L1: L1:
call void @bar() call void @bar()
ret <vscale x 16 x i32> undef ret <vscale x 16 x i32> undef
L2: L2:
ret <vscale x 16 x i32> %illegal ret <vscale x 16 x i32> %illegal
} }
define <vscale x 8 x i64> @wide_8i64(i1 %b, <vscale x 16 x i8> %legal, <vscale x 8 x i64> %illegal) nounwind { define <vscale x 8 x i64> @wide_8i64(i1 %b, <vscale x 16 x i8> %legal, <vscale x 8 x i64> %illegal) nounwind {
; CHECK-LABEL: wide_8i64: ; CHECK-LABEL: wide_8i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: tbz w0, #0, .LBB17_2 ; CHECK-NEXT: tbz w0, #0, .LBB17_2
; CHECK-NEXT: // %bb.1: // %L1 ; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-18 ; CHECK-NEXT: addvl sp, sp, #-18
; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill
Show All 16 Lines
; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-4
; CHECK-NEXT: str z4, [sp, #3, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z3, [sp, #2, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z2, [sp, #1, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl bar ; CHECK-NEXT: bl bar
; CHECK-NEXT: ldr z0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr z2, [sp, #1, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z3, [sp, #2, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z4, [sp, #3, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #4
; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload
Show All 14 Lines
; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #18 ; CHECK-NEXT: addvl sp, sp, #18
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: .LBB17_2: // %common.ret
; CHECK-NEXT: .LBB17_2: // %L2
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: mov z1.d, z2.d ; CHECK-NEXT: mov z1.d, z2.d
; CHECK-NEXT: mov z2.d, z3.d ; CHECK-NEXT: mov z2.d, z3.d
; CHECK-NEXT: mov z3.d, z4.d ; CHECK-NEXT: mov z3.d, z4.d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
br i1 %b, label %L1, label %L2 br i1 %b, label %L1, label %L2
L1: L1:
call void @bar() call void @bar()
ret <vscale x 8 x i64> undef ret <vscale x 8 x i64> undef
L2: L2:
ret <vscale x 8 x i64> %illegal ret <vscale x 8 x i64> %illegal
} }
define <vscale x 32 x half> @wide_32f16(i1 %b, <vscale x 16 x i8> %legal, <vscale x 32 x half> %illegal) nounwind { define <vscale x 32 x half> @wide_32f16(i1 %b, <vscale x 16 x i8> %legal, <vscale x 32 x half> %illegal) nounwind {
; CHECK-LABEL: wide_32f16: ; CHECK-LABEL: wide_32f16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: tbz w0, #0, .LBB18_2 ; CHECK-NEXT: tbz w0, #0, .LBB18_2
; CHECK-NEXT: // %bb.1: // %L1 ; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-18 ; CHECK-NEXT: addvl sp, sp, #-18
; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill
Show All 16 Lines
; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-4
; CHECK-NEXT: str z4, [sp, #3, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z3, [sp, #2, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z2, [sp, #1, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl bar ; CHECK-NEXT: bl bar
; CHECK-NEXT: ldr z0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr z2, [sp, #1, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z3, [sp, #2, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z4, [sp, #3, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #4
; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload
Show All 14 Lines
; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #18 ; CHECK-NEXT: addvl sp, sp, #18
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: .LBB18_2: // %common.ret
; CHECK-NEXT: .LBB18_2: // %L2
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: mov z1.d, z2.d ; CHECK-NEXT: mov z1.d, z2.d
; CHECK-NEXT: mov z2.d, z3.d ; CHECK-NEXT: mov z2.d, z3.d
; CHECK-NEXT: mov z3.d, z4.d ; CHECK-NEXT: mov z3.d, z4.d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
br i1 %b, label %L1, label %L2 br i1 %b, label %L1, label %L2
L1: L1:
call void @bar() call void @bar()
ret <vscale x 32 x half> undef ret <vscale x 32 x half> undef
L2: L2:
ret <vscale x 32 x half> %illegal ret <vscale x 32 x half> %illegal
} }
define <vscale x 16 x float> @wide_16f32(i1 %b, <vscale x 16 x i8> %legal, <vscale x 16 x float> %illegal) nounwind { define <vscale x 16 x float> @wide_16f32(i1 %b, <vscale x 16 x i8> %legal, <vscale x 16 x float> %illegal) nounwind {
; CHECK-LABEL: wide_16f32: ; CHECK-LABEL: wide_16f32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: tbz w0, #0, .LBB19_2 ; CHECK-NEXT: tbz w0, #0, .LBB19_2
; CHECK-NEXT: // %bb.1: // %L1 ; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-18 ; CHECK-NEXT: addvl sp, sp, #-18
; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill
Show All 16 Lines
; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-4
; CHECK-NEXT: str z4, [sp, #3, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z3, [sp, #2, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z2, [sp, #1, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl bar ; CHECK-NEXT: bl bar
; CHECK-NEXT: ldr z0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr z2, [sp, #1, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z3, [sp, #2, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z4, [sp, #3, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #4
; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload
Show All 14 Lines
; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #18 ; CHECK-NEXT: addvl sp, sp, #18
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: .LBB19_2: // %common.ret
; CHECK-NEXT: .LBB19_2: // %L2
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: mov z1.d, z2.d ; CHECK-NEXT: mov z1.d, z2.d
; CHECK-NEXT: mov z2.d, z3.d ; CHECK-NEXT: mov z2.d, z3.d
; CHECK-NEXT: mov z3.d, z4.d ; CHECK-NEXT: mov z3.d, z4.d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
br i1 %b, label %L1, label %L2 br i1 %b, label %L1, label %L2
L1: L1:
call void @bar() call void @bar()
ret <vscale x 16 x float> undef ret <vscale x 16 x float> undef
L2: L2:
ret <vscale x 16 x float> %illegal ret <vscale x 16 x float> %illegal
} }
define <vscale x 8 x double> @wide_8f64(i1 %b, <vscale x 16 x i8> %legal, <vscale x 8 x double> %illegal) nounwind { define <vscale x 8 x double> @wide_8f64(i1 %b, <vscale x 16 x i8> %legal, <vscale x 8 x double> %illegal) nounwind {
; CHECK-LABEL: wide_8f64: ; CHECK-LABEL: wide_8f64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: tbz w0, #0, .LBB20_2 ; CHECK-NEXT: tbz w0, #0, .LBB20_2
; CHECK-NEXT: // %bb.1: // %L1 ; CHECK-NEXT: // %bb.1: // %L1
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill ; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-18 ; CHECK-NEXT: addvl sp, sp, #-18
; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Folded Spill
; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill ; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Folded Spill
Show All 16 Lines
; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z15, [sp, #10, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z14, [sp, #11, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z13, [sp, #12, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z12, [sp, #13, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z11, [sp, #14, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z10, [sp, #15, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z9, [sp, #16, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill ; CHECK-NEXT: str z8, [sp, #17, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: addvl sp, sp, #-4
; CHECK-NEXT: str z4, [sp, #3, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z3, [sp, #2, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z2, [sp, #1, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: bl bar ; CHECK-NEXT: bl bar
; CHECK-NEXT: ldr z0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr z2, [sp, #1, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z3, [sp, #2, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z4, [sp, #3, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #4
; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload ; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Folded Reload
Show All 14 Lines
; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z13, [sp, #12, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z12, [sp, #13, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z11, [sp, #14, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z10, [sp, #15, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z9, [sp, #16, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload ; CHECK-NEXT: ldr z8, [sp, #17, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #18 ; CHECK-NEXT: addvl sp, sp, #18
; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload ; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload
; CHECK-NEXT: ret ; CHECK-NEXT: .LBB20_2: // %common.ret
; CHECK-NEXT: .LBB20_2: // %L2
; CHECK-NEXT: mov z0.d, z1.d
; CHECK-NEXT: mov z1.d, z2.d ; CHECK-NEXT: mov z1.d, z2.d
; CHECK-NEXT: mov z2.d, z3.d ; CHECK-NEXT: mov z2.d, z3.d
; CHECK-NEXT: mov z3.d, z4.d ; CHECK-NEXT: mov z3.d, z4.d
; CHECK-NEXT: ret ; CHECK-NEXT: ret
br i1 %b, label %L1, label %L2 br i1 %b, label %L1, label %L2
L1: L1:
call void @bar() call void @bar()
ret <vscale x 8 x double> undef ret <vscale x 8 x double> undef
L2: L2:
ret <vscale x 8 x double> %illegal ret <vscale x 8 x double> %illegal
} }

llvm/test/CodeGen/AArch64/swifterror.ll

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; CHECK-APPLE-NEXT: mov x29, sp ; CHECK-APPLE-NEXT: mov x29, sp
; CHECK-APPLE-NEXT: .cfi_def_cfa w29, 16 ; CHECK-APPLE-NEXT: .cfi_def_cfa w29, 16
; CHECK-APPLE-NEXT: .cfi_offset w30, -8 ; CHECK-APPLE-NEXT: .cfi_offset w30, -8
; CHECK-APPLE-NEXT: .cfi_offset w29, -16 ; CHECK-APPLE-NEXT: .cfi_offset w29, -16
; CHECK-APPLE-NEXT: cbz w0, LBB3_2 ; CHECK-APPLE-NEXT: cbz w0, LBB3_2
; CHECK-APPLE-NEXT: ; %bb.1: ; %gen_error ; CHECK-APPLE-NEXT: ; %bb.1: ; %gen_error
; CHECK-APPLE-NEXT: mov w0, #16 ; CHECK-APPLE-NEXT: mov w0, #16
; CHECK-APPLE-NEXT: bl _malloc ; CHECK-APPLE-NEXT: bl _malloc
; CHECK-APPLE-NEXT: mov x21, x0
fhahnUnsubmitted
Done
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I noticed you auto-generated the tests for this file and the GlobalISel version. It looks like those tests intentionally only checked the relevant parts related to swifterror, but now the checks are much more verbose (and much more prone to needing updating, because they check lots of 'uninteresting things).

Given that only a few lines out of ~2000 needed updating, I am wondering if it would be better to keep the hand-written checks and just update the failing line? Going forward, I think the auto-generated ones will need updating much more frequently now. Granted it is easy to update them, but it still creates noise in diffs and in theory would require careful checking.

fhahn: I noticed you auto-generated the tests for this file and the GlobalISel version. It looks like…
fhahnUnsubmitted
Done
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(The original checks also had comments interleaved to explain what is being checked. It looks like they are now all before the auto-generated check lines)

fhahn: (The original checks also had comments interleaved to explain what is being checked. It looks…
; CHECK-APPLE-NEXT: mov w8, #1 ; CHECK-APPLE-NEXT: mov w8, #1
; CHECK-APPLE-NEXT: fmov s0, #1.00000000
; CHECK-APPLE-NEXT: strb w8, [x0, #8] ; CHECK-APPLE-NEXT: strb w8, [x0, #8]
; CHECK-APPLE-NEXT: mov x21, x0 ; CHECK-APPLE-NEXT: fmov s0, #1.00000000
; CHECK-APPLE-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload ; CHECK-APPLE-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
; CHECK-APPLE-NEXT: ret ; CHECK-APPLE-NEXT: ret
; CHECK-APPLE-NEXT: LBB3_2: ; %normal ; CHECK-APPLE-NEXT: LBB3_2:
; CHECK-APPLE-NEXT: movi d0, #0000000000000000 ; CHECK-APPLE-NEXT: movi d0, #0000000000000000
; CHECK-APPLE-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload ; CHECK-APPLE-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
; CHECK-APPLE-NEXT: ret ; CHECK-APPLE-NEXT: ret
; ;
; CHECK-O0-AARCH64-LABEL: foo_if: ; CHECK-O0-AARCH64-LABEL: foo_if:
; CHECK-O0-AARCH64: ; %bb.0: ; %entry ; CHECK-O0-AARCH64: ; %bb.0: ; %entry
; CHECK-O0-AARCH64-NEXT: sub sp, sp, #32 ; =32 ; CHECK-O0-AARCH64-NEXT: sub sp, sp, #32 ; =32
; CHECK-O0-AARCH64-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill ; CHECK-O0-AARCH64-NEXT: stp x29, x30, [sp, #16] ; 16-byte Folded Spill
▲ Show 20 Lines • Show All 1,656 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/use-cr-result-of-dom-icmp-st.ll

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target datalayout = "e-m:e-i64:64-n32:64" target datalayout = "e-m:e-i64:64-n32:64"
define i64 @ll_a_op_b__2(i64 %a, i64 %b) { define i64 @ll_a_op_b__2(i64 %a, i64 %b) {
; CHECK-LABEL: ll_a_op_b__2: ; CHECK-LABEL: ll_a_op_b__2:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: lsl x8, x0, x1 ; CHECK-NEXT: lsl x8, x0, x1
; CHECK-NEXT: cmn x8, #2 // =2 ; CHECK-NEXT: cmn x8, #2 // =2
; CHECK-NEXT: b.le .LBB0_2 ; CHECK-NEXT: csinc x8, x1, xzr, eq
; CHECK-NEXT: // %bb.1: // %return ; CHECK-NEXT: mul x8, x8, x0
; CHECK-NEXT: mov x0, x1 ; CHECK-NEXT: csel x0, x1, x8, gt
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB0_2: // %if.end
; CHECK-NEXT: csinc x8, x1, xzr, ge
; CHECK-NEXT: mul x0, x8, x0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%shl = shl i64 %a, %b %shl = shl i64 %a, %b
%cmp = icmp sgt i64 %shl, -2 %cmp = icmp sgt i64 %shl, -2
br i1 %cmp, label %return, label %if.end br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry if.end: ; preds = %entry
%cmp2 = icmp eq i64 %shl, -2 %cmp2 = icmp eq i64 %shl, -2
%mul = select i1 %cmp2, i64 %b, i64 1 %mul = select i1 %cmp2, i64 %b, i64 1
%spec.select = mul nsw i64 %mul, %a %spec.select = mul nsw i64 %mul, %a
ret i64 %spec.select ret i64 %spec.select
return: ; preds = %entry return: ; preds = %entry
ret i64 %b ret i64 %b
} }
define i64 @ll_a_op_b__1(i64 %a, i64 %b) { define i64 @ll_a_op_b__1(i64 %a, i64 %b) {
; CHECK-LABEL: ll_a_op_b__1: ; CHECK-LABEL: ll_a_op_b__1:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: lsl x8, x0, x1 ; CHECK-NEXT: lsl x8, x0, x1
; CHECK-NEXT: tbnz x8, #63, .LBB1_2
; CHECK-NEXT: // %bb.1: // %return
; CHECK-NEXT: mov x0, x1
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB1_2: // %if.end
; CHECK-NEXT: cmn x8, #1 // =1 ; CHECK-NEXT: cmn x8, #1 // =1
; CHECK-NEXT: csinc x8, x1, xzr, ge ; CHECK-NEXT: csinc x9, x1, xzr, eq
; CHECK-NEXT: mul x0, x8, x0 ; CHECK-NEXT: mul x9, x9, x0
; CHECK-NEXT: cmp x8, #0 // =0
; CHECK-NEXT: csel x0, x1, x9, ge
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%shl = shl i64 %a, %b %shl = shl i64 %a, %b
%cmp = icmp sgt i64 %shl, -1 %cmp = icmp sgt i64 %shl, -1
br i1 %cmp, label %return, label %if.end br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry if.end: ; preds = %entry
%cmp2 = icmp eq i64 %shl, -1 %cmp2 = icmp eq i64 %shl, -1
%mul = select i1 %cmp2, i64 %b, i64 1 %mul = select i1 %cmp2, i64 %b, i64 1
%spec.select = mul nsw i64 %mul, %a %spec.select = mul nsw i64 %mul, %a
ret i64 %spec.select ret i64 %spec.select
return: ; preds = %entry return: ; preds = %entry
ret i64 %b ret i64 %b
} }
define i64 @ll_a_op_b_0(i64 %a, i64 %b) { define i64 @ll_a_op_b_0(i64 %a, i64 %b) {
; CHECK-LABEL: ll_a_op_b_0: ; CHECK-LABEL: ll_a_op_b_0:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: lsl x8, x0, x1 ; CHECK-NEXT: lsl x8, x0, x1
; CHECK-NEXT: cmp x8, #0 // =0 ; CHECK-NEXT: cmp x8, #0 // =0
; CHECK-NEXT: b.le .LBB2_2 ; CHECK-NEXT: csinc x8, x1, xzr, eq
; CHECK-NEXT: // %bb.1: // %return ; CHECK-NEXT: mul x8, x8, x0
; CHECK-NEXT: mov x0, x1 ; CHECK-NEXT: csel x0, x1, x8, gt
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB2_2: // %if.end
; CHECK-NEXT: csinc x8, x1, xzr, ge
; CHECK-NEXT: mul x0, x8, x0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%shl = shl i64 %a, %b %shl = shl i64 %a, %b
%cmp = icmp sgt i64 %shl, 0 %cmp = icmp sgt i64 %shl, 0
br i1 %cmp, label %return, label %if.end br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry if.end: ; preds = %entry
%cmp2 = icmp eq i64 %shl, 0 %cmp2 = icmp eq i64 %shl, 0
%mul = select i1 %cmp2, i64 %b, i64 1 %mul = select i1 %cmp2, i64 %b, i64 1
%spec.select = mul nsw i64 %mul, %a %spec.select = mul nsw i64 %mul, %a
ret i64 %spec.select ret i64 %spec.select
return: ; preds = %entry return: ; preds = %entry
ret i64 %b ret i64 %b
} }
define i64 @ll_a_op_b_1(i64 %a, i64 %b) { define i64 @ll_a_op_b_1(i64 %a, i64 %b) {
; CHECK-LABEL: ll_a_op_b_1: ; CHECK-LABEL: ll_a_op_b_1:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: lsl x8, x0, x1 ; CHECK-NEXT: lsl x8, x0, x1
; CHECK-NEXT: cmp x8, #1 // =1 ; CHECK-NEXT: cmp x8, #1 // =1
; CHECK-NEXT: b.le .LBB3_2 ; CHECK-NEXT: csinc x8, x1, xzr, eq
; CHECK-NEXT: // %bb.1: // %return ; CHECK-NEXT: mul x8, x8, x0
; CHECK-NEXT: mov x0, x1 ; CHECK-NEXT: csel x0, x1, x8, gt
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB3_2: // %if.end
; CHECK-NEXT: csinc x8, x1, xzr, ge
; CHECK-NEXT: mul x0, x8, x0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%shl = shl i64 %a, %b %shl = shl i64 %a, %b
%cmp = icmp sgt i64 %shl, 1 %cmp = icmp sgt i64 %shl, 1
br i1 %cmp, label %return, label %if.end br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry if.end: ; preds = %entry
%cmp2 = icmp eq i64 %shl, 1 %cmp2 = icmp eq i64 %shl, 1
%mul = select i1 %cmp2, i64 %b, i64 1 %mul = select i1 %cmp2, i64 %b, i64 1
%spec.select = mul nsw i64 %mul, %a %spec.select = mul nsw i64 %mul, %a
ret i64 %spec.select ret i64 %spec.select
return: ; preds = %entry return: ; preds = %entry
ret i64 %b ret i64 %b
} }
define i64 @ll_a_op_b_2(i64 %a, i64 %b) { define i64 @ll_a_op_b_2(i64 %a, i64 %b) {
; CHECK-LABEL: ll_a_op_b_2: ; CHECK-LABEL: ll_a_op_b_2:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: lsl x8, x0, x1 ; CHECK-NEXT: lsl x8, x0, x1
; CHECK-NEXT: cmp x8, #2 // =2 ; CHECK-NEXT: cmp x8, #2 // =2
; CHECK-NEXT: b.le .LBB4_2 ; CHECK-NEXT: csinc x8, x1, xzr, eq
; CHECK-NEXT: // %bb.1: // %return ; CHECK-NEXT: mul x8, x8, x0
; CHECK-NEXT: mov x0, x1 ; CHECK-NEXT: csel x0, x1, x8, gt
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB4_2: // %if.end
; CHECK-NEXT: csinc x8, x1, xzr, ge
; CHECK-NEXT: mul x0, x8, x0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%shl = shl i64 %a, %b %shl = shl i64 %a, %b
%cmp = icmp sgt i64 %shl, 2 %cmp = icmp sgt i64 %shl, 2
br i1 %cmp, label %return, label %if.end br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry if.end: ; preds = %entry
%cmp2 = icmp eq i64 %shl, 2 %cmp2 = icmp eq i64 %shl, 2
%mul = select i1 %cmp2, i64 %b, i64 1 %mul = select i1 %cmp2, i64 %b, i64 1
%spec.select = mul nsw i64 %mul, %a %spec.select = mul nsw i64 %mul, %a
ret i64 %spec.select ret i64 %spec.select
return: ; preds = %entry return: ; preds = %entry
ret i64 %b ret i64 %b
} }
define i64 @ll_a__2(i64 %a, i64 %b) { define i64 @ll_a__2(i64 %a, i64 %b) {
; CHECK-LABEL: ll_a__2: ; CHECK-LABEL: ll_a__2:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmn x0, #2 // =2 ; CHECK-NEXT: cmn x0, #2 // =2
; CHECK-NEXT: b.le .LBB5_2 ; CHECK-NEXT: csinc x8, x1, xzr, eq
; CHECK-NEXT: // %bb.1: // %return ; CHECK-NEXT: mul x8, x8, x0
; CHECK-NEXT: mov x0, x1 ; CHECK-NEXT: csel x0, x1, x8, gt
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB5_2: // %if.end
; CHECK-NEXT: csinc x8, x1, xzr, ge
; CHECK-NEXT: mul x0, x8, x0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%cmp = icmp sgt i64 %a, -2 %cmp = icmp sgt i64 %a, -2
br i1 %cmp, label %return, label %if.end br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry if.end: ; preds = %entry
%cmp1 = icmp eq i64 %a, -2 %cmp1 = icmp eq i64 %a, -2
%mul = select i1 %cmp1, i64 %b, i64 1 %mul = select i1 %cmp1, i64 %b, i64 1
%spec.select = mul nsw i64 %mul, %a %spec.select = mul nsw i64 %mul, %a
ret i64 %spec.select ret i64 %spec.select
return: ; preds = %entry return: ; preds = %entry
ret i64 %b ret i64 %b
} }
define i64 @ll_a__1(i64 %a, i64 %b) { define i64 @ll_a__1(i64 %a, i64 %b) {
; CHECK-LABEL: ll_a__1: ; CHECK-LABEL: ll_a__1:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: tbnz x0, #63, .LBB6_2
; CHECK-NEXT: // %bb.1: // %return
; CHECK-NEXT: mov x0, x1
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB6_2: // %if.end
; CHECK-NEXT: cmn x0, #1 // =1 ; CHECK-NEXT: cmn x0, #1 // =1
; CHECK-NEXT: csinc x8, x1, xzr, ge ; CHECK-NEXT: csinc x8, x1, xzr, eq
; CHECK-NEXT: mul x0, x8, x0 ; CHECK-NEXT: mul x8, x8, x0
; CHECK-NEXT: cmp x0, #0 // =0
; CHECK-NEXT: csel x0, x1, x8, ge
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%cmp = icmp sgt i64 %a, -1 %cmp = icmp sgt i64 %a, -1
br i1 %cmp, label %return, label %if.end br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry if.end: ; preds = %entry
%cmp1 = icmp eq i64 %a, -1 %cmp1 = icmp eq i64 %a, -1
%mul = select i1 %cmp1, i64 %b, i64 1 %mul = select i1 %cmp1, i64 %b, i64 1
%spec.select = mul nsw i64 %mul, %a %spec.select = mul nsw i64 %mul, %a
ret i64 %spec.select ret i64 %spec.select
return: ; preds = %entry return: ; preds = %entry
ret i64 %b ret i64 %b
} }
define i64 @ll_a_0(i64 %a, i64 %b) { define i64 @ll_a_0(i64 %a, i64 %b) {
; CHECK-LABEL: ll_a_0: ; CHECK-LABEL: ll_a_0:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmp x0, #0 // =0 ; CHECK-NEXT: cmp x0, #0 // =0
; CHECK-NEXT: b.le .LBB7_2 ; CHECK-NEXT: csinc x8, x1, xzr, eq
; CHECK-NEXT: // %bb.1: // %return ; CHECK-NEXT: mul x8, x8, x0
; CHECK-NEXT: mov x0, x1 ; CHECK-NEXT: csel x0, x1, x8, gt
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB7_2: // %if.end
; CHECK-NEXT: csinc x8, x1, xzr, ge
; CHECK-NEXT: mul x0, x8, x0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%cmp = icmp sgt i64 %a, 0 %cmp = icmp sgt i64 %a, 0
br i1 %cmp, label %return, label %if.end br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry if.end: ; preds = %entry
%cmp1 = icmp eq i64 %a, 0 %cmp1 = icmp eq i64 %a, 0
%mul = select i1 %cmp1, i64 %b, i64 1 %mul = select i1 %cmp1, i64 %b, i64 1
%spec.select = mul nsw i64 %mul, %a %spec.select = mul nsw i64 %mul, %a
ret i64 %spec.select ret i64 %spec.select
return: ; preds = %entry return: ; preds = %entry
ret i64 %b ret i64 %b
} }
define i64 @ll_a_1(i64 %a, i64 %b) { define i64 @ll_a_1(i64 %a, i64 %b) {
; CHECK-LABEL: ll_a_1: ; CHECK-LABEL: ll_a_1:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmp x0, #1 // =1 ; CHECK-NEXT: cmp x0, #1 // =1
; CHECK-NEXT: b.le .LBB8_2 ; CHECK-NEXT: csinc x8, x1, xzr, eq
; CHECK-NEXT: // %bb.1: // %return ; CHECK-NEXT: mul x8, x8, x0
; CHECK-NEXT: mov x0, x1 ; CHECK-NEXT: csel x0, x1, x8, gt
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB8_2: // %if.end
; CHECK-NEXT: csinc x8, x1, xzr, ge
; CHECK-NEXT: mul x0, x8, x0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%cmp = icmp sgt i64 %a, 1 %cmp = icmp sgt i64 %a, 1
br i1 %cmp, label %return, label %if.end br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry if.end: ; preds = %entry
%cmp1 = icmp eq i64 %a, 1 %cmp1 = icmp eq i64 %a, 1
%mul = select i1 %cmp1, i64 %b, i64 1 %mul = select i1 %cmp1, i64 %b, i64 1
%spec.select = mul nsw i64 %mul, %a %spec.select = mul nsw i64 %mul, %a
ret i64 %spec.select ret i64 %spec.select
return: ; preds = %entry return: ; preds = %entry
ret i64 %b ret i64 %b
} }
define i64 @ll_a_2(i64 %a, i64 %b) { define i64 @ll_a_2(i64 %a, i64 %b) {
; CHECK-LABEL: ll_a_2: ; CHECK-LABEL: ll_a_2:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmp x0, #2 // =2 ; CHECK-NEXT: cmp x0, #2 // =2
; CHECK-NEXT: b.le .LBB9_2 ; CHECK-NEXT: csinc x8, x1, xzr, eq
; CHECK-NEXT: // %bb.1: // %return ; CHECK-NEXT: mul x8, x8, x0
; CHECK-NEXT: mov x0, x1 ; CHECK-NEXT: csel x0, x1, x8, gt
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB9_2: // %if.end
; CHECK-NEXT: csinc x8, x1, xzr, ge
; CHECK-NEXT: mul x0, x8, x0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%cmp = icmp sgt i64 %a, 2 %cmp = icmp sgt i64 %a, 2
br i1 %cmp, label %return, label %if.end br i1 %cmp, label %return, label %if.end
if.end: ; preds = %entry if.end: ; preds = %entry
%cmp1 = icmp eq i64 %a, 2 %cmp1 = icmp eq i64 %a, 2
%mul = select i1 %cmp1, i64 %b, i64 1 %mul = select i1 %cmp1, i64 %b, i64 1
▲ Show 20 Lines • Show All 268 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/vec-extract-branch.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -verify-machineinstrs | FileCheck %s
define i32 @vec_extract_branch(<2 x double> %x, i32 %y) { define i32 @vec_extract_branch(<2 x double> %x, i32 %y) {
; CHECK-LABEL: vec_extract_branch: ; CHECK-LABEL: vec_extract_branch:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: fcmgt v0.2d, v0.2d, #0.0 ; CHECK-NEXT: fcmgt v0.2d, v0.2d, #0.0
; CHECK-NEXT: xtn v0.2s, v0.2d ; CHECK-NEXT: xtn v0.2s, v0.2d
; CHECK-NEXT: mov w8, v0.s[1] ; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: and w8, w9, w8 ; CHECK-NEXT: and w8, w9, w8
; CHECK-NEXT: tbz w8, #0, .LBB0_2 ; CHECK-NEXT: tbz w8, #0, .LBB0_2
; CHECK-NEXT: // %bb.1: // %true ; CHECK-NEXT: // %bb.1: // %true
; CHECK-NEXT: mov w8, #42 ; CHECK-NEXT: mov w8, #42
; CHECK-NEXT: sdiv w0, w8, w0 ; CHECK-NEXT: sdiv w0, w8, w0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; CHECK-NEXT: .LBB0_2: // %false ; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: mov w0, #88 ; CHECK-NEXT: mov w0, #88
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t1 = fcmp ogt <2 x double> %x, zeroinitializer %t1 = fcmp ogt <2 x double> %x, zeroinitializer
%t2 = extractelement <2 x i1> %t1, i32 0 %t2 = extractelement <2 x i1> %t1, i32 0
%t3 = extractelement <2 x i1> %t1, i32 1 %t3 = extractelement <2 x i1> %t1, i32 1
%t4 = and i1 %t2, %t3 %t4 = and i1 %t2, %t3
br i1 %t4, label %true, label %false br i1 %t4, label %true, label %false
true: true:
%y1 = sdiv i32 42, %y %y1 = sdiv i32 42, %y
ret i32 %y1 ret i32 %y1
false: false:
ret i32 88 ret i32 88
} }

llvm/test/CodeGen/ARM/cfguard-checks.ll

Show First 20 Lines • Show All 95 Lines • ▼ Show 20 Lineslpad: ; preds = %entry
; CHECK: movt r0, :upper16:__guard_check_icall_fptr ; CHECK: movt r0, :upper16:__guard_check_icall_fptr
; CHECK: ldr r1, [r0] ; CHECK: ldr r1, [r0]
; CHECK: movw r4, :lower16:target_func ; CHECK: movw r4, :lower16:target_func
; CHECK: movt r4, :upper16:target_func ; CHECK: movt r4, :upper16:target_func
; CHECK: mov r0, r4 ; CHECK: mov r0, r4
; CHECK: blx r1 ; CHECK: blx r1
; CHECK-NEXT: $Mtmp0: ; CHECK-NEXT: $Mtmp0:
; CHECK-NEXT: blx r4 ; CHECK-NEXT: blx r4
; CHECK: ; %invoke.cont ; CHECK: ; %common.ret
; CHECK: ; %lpad ; CHECK: ; %lpad
} }
declare void @h() declare void @h()
; Test that longjmp targets have public labels and are included in the .gljmp section. ; Test that longjmp targets have public labels and are included in the .gljmp section.
%struct._SETJMP_FLOAT128 = type { [2 x i64] } %struct._SETJMP_FLOAT128 = type { [2 x i64] }
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llvm/test/CodeGen/ARM/fp16-promote.ll

Show First 20 Lines • Show All 199 Lines • ▼ Show 20 Lines
; CHECK-ALL-LABEL: test_br_cc: ; CHECK-ALL-LABEL: test_br_cc:
; CHECK-FP16: vcvtb.f32.f16 ; CHECK-FP16: vcvtb.f32.f16
; CHECK-FP16: vcvtb.f32.f16 ; CHECK-FP16: vcvtb.f32.f16
; CHECK-LIBCALL: bl __aeabi_h2f ; CHECK-LIBCALL: bl __aeabi_h2f
; CHECK-LIBCALL: bl __aeabi_h2f ; CHECK-LIBCALL: bl __aeabi_h2f
; CHECK-VFP: vcmp.f32 ; CHECK-VFP: vcmp.f32
; CHECK-NOVFP: bl __aeabi_fcmplt ; CHECK-NOVFP: bl __aeabi_fcmplt
; CHECK-FP16: vmrs APSR_nzcv, fpscr ; CHECK-FP16: vmrs APSR_nzcv, fpscr
; CHECK-VFP: strmi ; CHECK-VFP: movmi
; CHECK-VFP: strpl ; CHECK-VFP: str
; CHECK-NOVFP: strne ; CHECK-NOVFP: str
; CHECK-NOVFP: streq
define void @test_br_cc(half* %p, half* %q, i32* %p1, i32* %p2) #0 { define void @test_br_cc(half* %p, half* %q, i32* %p1, i32* %p2) #0 {
%a = load half, half* %p, align 2 %a = load half, half* %p, align 2
%b = load half, half* %q, align 2 %b = load half, half* %q, align 2
%c = fcmp uge half %a, %b %c = fcmp uge half %a, %b
br i1 %c, label %then, label %else br i1 %c, label %then, label %else
then: then:
store i32 0, i32* %p1 store i32 0, i32* %p1
ret void ret void
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llvm/test/CodeGen/ARM/ifcvt-callback.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumb-- %s -o - | FileCheck %s ; RUN: llc -mtriple=thumb-- %s -o - | FileCheck %s
; This test checks that if-conversion pass is unconditionally added to the pass ; This test checks that if-conversion pass is unconditionally added to the pass
; pipeline and is conditionally executed based on the per-function targert-cpu ; pipeline and is conditionally executed based on the per-function targert-cpu
; attribute. ; attribute.
define i32 @test_ifcvt(i32 %a, i32 %b) #0 { define i32 @test_ifcvt(i32 %a, i32 %b) #0 {
; CHECK-LABEL: test_ifcvt: ; CHECK-LABEL: test_ifcvt:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0: @ %common.ret
; CHECK-NEXT: movs r2, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: ite eq ; CHECK-NEXT: it eq
; CHECK-NEXT: subeq r0, r1, #1 ; CHECK-NEXT: moveq.w r2, #-1
; CHECK-NEXT: addne r0, r1, #1 ; CHECK-NEXT: adds r0, r1, r2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
%tmp2 = icmp eq i32 %a, 0 %tmp2 = icmp eq i32 %a, 0
br i1 %tmp2, label %cond_false, label %cond_true br i1 %tmp2, label %cond_false, label %cond_true
cond_true: cond_true:
%tmp5 = add i32 %b, 1 %tmp5 = add i32 %b, 1
ret i32 %tmp5 ret i32 %tmp5
cond_false: cond_false:
%tmp7 = add i32 %b, -1 %tmp7 = add i32 %b, -1
ret i32 %tmp7 ret i32 %tmp7
} }
attributes #0 = { "target-cpu"="cortex-a8" } attributes #0 = { "target-cpu"="cortex-a8" }

llvm/test/CodeGen/ARM/ifcvt-iter-indbr.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple thumbv7s-apple-darwin -asm-verbose=false | FileCheck %s ; RUN: llc < %s -mtriple thumbv7s-apple-darwin -asm-verbose=false | FileCheck %s
; RUN: llc < %s -mtriple thumbv7s-apple-darwin -asm-verbose=false -stop-after=if-converter | FileCheck --check-prefix=CHECK-PROB %s ; RUN: llc < %s -mtriple thumbv7s-apple-darwin -asm-verbose=false -stop-after=if-converter | FileCheck --check-prefix=CHECK-PROB %s
declare i32 @foo(i32) declare i32 @foo(i32)
declare i8* @bar(i32, i8*, i8*) declare i8* @bar(i32, i8*, i8*)
; Verify that we don't try to iteratively re-ifconvert a block with a ; Verify that we don't try to iteratively re-ifconvert a block with a
; (predicated) indirectbr terminator. ; (predicated) indirectbr terminator.
; If we do, we would ignore its fallthrough successor. ; If we do, we would ignore its fallthrough successor.
; CHECK-PROB: bb.0{{[0-9a-zA-Z.]*}}: ; CHECK-PROB: bb.0{{[0-9a-zA-Z.]*}}:
; CHECK-PROB: successors: %bb.1(0x40000000), %bb.3(0x20000000), %bb.5(0x20000000) ; CHECK-PROB: successors: %bb.1(0x40000000), %bb.3(0x20000000), %bb.4(0x20000000)
; CHECK-PROB: bb.2{{[0-9a-zA-Z.]*}}: ; CHECK-PROB: bb.2{{[0-9a-zA-Z.]*}}:
; CHECK-PROB: successors: %bb.3(0x40000000), %bb.5(0x40000000) ; CHECK-PROB: successors: %bb.3(0x40000000), %bb.4(0x40000000)
define i32 @test(i32 %a, i32 %a2, i32* %p, i32* %p2) "frame-pointer"="all" { define i32 @test(i32 %a, i32 %a2, i32* %p, i32* %p2) "frame-pointer"="all" {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: push {r4, r5, r6, r7, lr} ; CHECK: push {r4, r5, r6, r7, lr}
; CHECK-NEXT: add r7, sp, #12 ; CHECK-NEXT: add r7, sp, #12
; CHECK-NEXT: push.w {r8, r10, r11} ; CHECK-NEXT: push.w {r8, r10, r11}
; CHECK-NEXT: str r3, [sp, #-4]! ; CHECK-NEXT: str r3, [sp, #-4]!
; CHECK-NEXT: mov r11, r2 ; CHECK-NEXT: mov r11, r2
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; CHECK-NEXT: mov r1, r6 ; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r2, r8 ; CHECK-NEXT: mov r2, r8
; CHECK-NEXT: bl _bar ; CHECK-NEXT: bl _bar
; CHECK-NEXT: movs r0, #3 ; CHECK-NEXT: movs r0, #3
; CHECK-NEXT: mov r1, r6 ; CHECK-NEXT: mov r1, r6
; CHECK-NEXT: mov r2, r8 ; CHECK-NEXT: mov r2, r8
; CHECK-NEXT: bl _bar ; CHECK-NEXT: bl _bar
; CHECK-NEXT: cmp r5, #21 ; CHECK-NEXT: cmp r5, #21
; CHECK-NEXT: itt eq ; CHECK-NEXT: itttt eq
; CHECK-NEXT: moveq r1, r0
; CHECK-NEXT: streq.w r5, [r11] ; CHECK-NEXT: streq.w r5, [r11]
; CHECK-NEXT: moveq pc, r0 ; CHECK-NEXT: movweq r0, #1234
; CHECK-NEXT: moveq pc, r1
; CHECK-NEXT: LBB0_1: ; CHECK-NEXT: LBB0_1:
; CHECK-NEXT: cmp r4, #42 ; CHECK-NEXT: cmp r4, #42
; CHECK-NEXT: beq LBB0_3 ; CHECK-NEXT: beq LBB0_4
; CHECK-NEXT: ldr r0, [sp] ; CHECK-NEXT: ldr r0, [sp]
; CHECK-NEXT: str r5, [r0] ; CHECK-NEXT: str r5, [r0]
; CHECK-NEXT: movw r0, #1234
; CHECK-NEXT: mov pc, r10 ; CHECK-NEXT: mov pc, r10
; CHECK-NEXT: Ltmp0: ; CHECK-NEXT: Ltmp0:
; CHECK-NEXT: LBB0_3: ; CHECK-NEXT: LBB0_3:
; CHECK-NEXT: movw r0, #1234 ; CHECK-NEXT: movw r0, #4567
; CHECK-NEXT: b LBB0_5 ; CHECK-NEXT: b LBB0_5
; CHECK-NEXT: Ltmp1:
; CHECK-NEXT: LBB0_4: ; CHECK-NEXT: LBB0_4:
; CHECK-NEXT: movw r0, #4567 ; CHECK-NEXT: movw r0, #1234
; CHECK-NEXT: Ltmp1:
; CHECK-NEXT: LBB0_5: ; CHECK-NEXT: LBB0_5:
; CHECK-NEXT: bl _foo ; CHECK-NEXT: bl _foo
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r8, r10, r11} ; CHECK-NEXT: pop.w {r8, r10, r11}
; CHECK-NEXT: pop {r4, r5, r6, r7, pc} ; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: .p2align 2
entry: entry:
%dst1 = call i8* @bar(i32 1, i8* blockaddress(@test, %bb1), i8* blockaddress(@test, %bb2)) %dst1 = call i8* @bar(i32 1, i8* blockaddress(@test, %bb1), i8* blockaddress(@test, %bb2))
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llvm/test/CodeGen/ARM/ifcvt1.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=A8 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=A8
; RUN: llc -mtriple=arm-eabi -mcpu=swift %s -o - | FileCheck %s -check-prefix=SWIFT ; RUN: llc -mtriple=arm-eabi -mcpu=swift %s -o - | FileCheck %s -check-prefix=SWIFT
define i32 @t1(i32 %a, i32 %b) { define i32 @t1(i32 %a, i32 %b) {
; A8-LABEL: t1: ; A8-LABEL: t1:
; A8: @ %bb.0: ; A8: @ %bb.0: @ %common.ret
; A8-NEXT: mov r2, #1
; A8-NEXT: cmp r0, #0 ; A8-NEXT: cmp r0, #0
; A8-NEXT: subeq r0, r1, #1 ; A8-NEXT: mvneq r2, #0
; A8-NEXT: addne r0, r1, #1 ; A8-NEXT: add r0, r1, r2
; A8-NEXT: bx lr ; A8-NEXT: bx lr
; ;
; SWIFT-LABEL: t1: ; SWIFT-LABEL: t1:
; SWIFT: @ %bb.0: ; SWIFT: @ %bb.0: @ %common.ret
; SWIFT-NEXT: mov r2, #1
; SWIFT-NEXT: cmp r0, #0 ; SWIFT-NEXT: cmp r0, #0
; SWIFT-NEXT: sub r0, r1, #1 ; SWIFT-NEXT: mvneq r2, #0
; SWIFT-NEXT: addne r0, r1, #1 ; SWIFT-NEXT: add r0, r1, r2
; SWIFT-NEXT: bx lr ; SWIFT-NEXT: bx lr
%tmp2 = icmp eq i32 %a, 0 %tmp2 = icmp eq i32 %a, 0
br i1 %tmp2, label %cond_false, label %cond_true br i1 %tmp2, label %cond_false, label %cond_true
cond_true: cond_true:
%tmp5 = add i32 %b, 1 %tmp5 = add i32 %b, 1
ret i32 %tmp5 ret i32 %tmp5
cond_false: cond_false:
%tmp7 = add i32 %b, -1 %tmp7 = add i32 %b, -1
ret i32 %tmp7 ret i32 %tmp7
} }

llvm/test/CodeGen/ARM/ifcvt3.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - | FileCheck %s -check-prefix CHECK-V4-CMP ; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - | FileCheck %s -check-prefix CHECK-V4-CMP
; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - | FileCheck %s -check-prefix CHECK-V4-BX ; RUN: llc -mtriple=arm-eabi -mattr=+v4t %s -o - | FileCheck %s -check-prefix CHECK-V4-BX
define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) { define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
; CHECK-LABEL: t1: ; CHECK-LABEL: t1:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: cmp r2, #7 ; CHECK-NEXT: cmp r2, #1
; CHECK-NEXT: cmpne r2, #1 ; CHECK-NEXT: cmpne r2, #7
; CHECK-NEXT: addne r0, r1, r0 ; CHECK-NEXT: addne r0, r1, r0
; CHECK-NEXT: addeq r0, r0, r1 ; CHECK-NEXT: addeq r0, r0, r1
; CHECK-NEXT: addeq r0, r0, #1 ; CHECK-NEXT: addeq r0, r0, #1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
; ;
; CHECK-V4-CMP-LABEL: t1: ; CHECK-V4-CMP-LABEL: t1:
; CHECK-V4-CMP: @ %bb.0: ; CHECK-V4-CMP: @ %bb.0:
; CHECK-V4-CMP-NEXT: cmp r2, #7 ; CHECK-V4-CMP-NEXT: cmp r2, #7
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llvm/test/CodeGen/ARM/ifcvt5.ll

Show All 28 Linesentry:
%tmp = load i32*, i32** @x ; <i32*> [#uses=1] %tmp = load i32*, i32** @x ; <i32*> [#uses=1]
store i32 %a, i32* %tmp store i32 %a, i32* %tmp
ret void ret void
} }
define i32 @t1(i32 %a, i32 %b) "frame-pointer"="all" { define i32 @t1(i32 %a, i32 %b) "frame-pointer"="all" {
; A8-LABEL: t1: ; A8-LABEL: t1:
; A8: @ %bb.0: @ %entry ; A8: @ %bb.0: @ %entry
; A8-NEXT: cmp r0, #11 ; A8-NEXT: mov r2, r0
; A8-NEXT: movlt r0, #1 ; A8-NEXT: mov r0, #1
; A8-NEXT: bxlt lr ; A8-NEXT: cmp r2, #10
; A8-NEXT: bxle lr
; A8-NEXT: LBB1_1: @ %cond_true ; A8-NEXT: LBB1_1: @ %cond_true
; A8-NEXT: push {r7, lr} ; A8-NEXT: push {r7, lr}
; A8-NEXT: mov r7, sp ; A8-NEXT: mov r7, sp
; A8-NEXT: mov r0, r1 ; A8-NEXT: mov r0, r1
; A8-NEXT: bl _foo ; A8-NEXT: bl _foo
; A8-NEXT: mov r0, #0 ; A8-NEXT: mov r0, #0
; A8-NEXT: pop {r7, pc} ; A8-NEXT: pop {r7, lr}
; A8-NEXT: bx lr
; ;
; SWIFT-LABEL: t1: ; SWIFT-LABEL: t1:
; SWIFT: @ %bb.0: @ %entry ; SWIFT: @ %bb.0: @ %entry
; SWIFT-NEXT: cmp r0, #11 ; SWIFT-NEXT: mov r2, r0
; SWIFT-NEXT: movlt r0, #1 ; SWIFT-NEXT: mov r0, #1
; SWIFT-NEXT: bxlt lr ; SWIFT-NEXT: cmp r2, #10
; SWIFT-NEXT: bxle lr
; SWIFT-NEXT: LBB1_1: @ %cond_true ; SWIFT-NEXT: LBB1_1: @ %cond_true
; SWIFT-NEXT: push {r7, lr} ; SWIFT-NEXT: push {r7, lr}
; SWIFT-NEXT: mov r7, sp ; SWIFT-NEXT: mov r7, sp
; SWIFT-NEXT: mov r0, r1 ; SWIFT-NEXT: mov r0, r1
; SWIFT-NEXT: bl _foo ; SWIFT-NEXT: bl _foo
; SWIFT-NEXT: mov r0, #0 ; SWIFT-NEXT: mov r0, #0
; SWIFT-NEXT: pop {r7, pc} ; SWIFT-NEXT: pop {r7, lr}
; SWIFT-NEXT: bx lr
entry: entry:
%tmp1 = icmp sgt i32 %a, 10 ; <i1> [#uses=1] %tmp1 = icmp sgt i32 %a, 10 ; <i1> [#uses=1]
br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock
cond_true: ; preds = %entry cond_true: ; preds = %entry
tail call void @foo( i32 %b ) tail call void @foo( i32 %b )
ret i32 0 ret i32 0
UnifiedReturnBlock: ; preds = %entry UnifiedReturnBlock: ; preds = %entry
ret i32 1 ret i32 1
} }

llvm/test/CodeGen/ARM/ifcvt6.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s ; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s
define void @foo(i32 %X, i32 %Y) { define void @foo(i32 %X, i32 %Y) {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: cmpne r0, #3 ; CHECK-NEXT: beq LBB0_2
; CHECK-NEXT: bxhi lr ; CHECK-NEXT: @ %bb.1: @ %entry
; CHECK-NEXT: LBB0_1: @ %cond_true ; CHECK-NEXT: cmp r0, #4
; CHECK-NEXT: bxhs lr
; CHECK-NEXT: LBB0_2: @ %cond_true
; CHECK-NEXT: push {lr} ; CHECK-NEXT: push {lr}
; CHECK-NEXT: bl _bar ; CHECK-NEXT: bl _bar
; CHECK-NEXT: pop {lr} ; CHECK-NEXT: pop {lr}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%tmp1 = icmp ult i32 %X, 4 ; <i1> [#uses=1] %tmp1 = icmp ult i32 %X, 4 ; <i1> [#uses=1]
%tmp4 = icmp eq i32 %Y, 0 ; <i1> [#uses=1] %tmp4 = icmp eq i32 %Y, 0 ; <i1> [#uses=1]
%tmp7 = or i1 %tmp4, %tmp1 ; <i1> [#uses=1] %tmp7 = or i1 %tmp4, %tmp1 ; <i1> [#uses=1]
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llvm/test/CodeGen/ARM/load-global2.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; PR35221. Test that external global address is not reloaded from GOT in each BB. ; PR35221. Test that external global address is not reloaded from GOT in each BB.
; RUN: llc < %s -mtriple=armv7-linux-gnueabi -relocation-model=pic | FileCheck %s -check-prefix=LINUX-PIC ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -relocation-model=pic | FileCheck %s -check-prefix=LINUX-PIC
@x = external global i8, align 1 @x = external global i8, align 1
define signext i8 @foo() { define signext i8 @foo() {
; LINUX-PIC-LABEL: foo: ; LINUX-PIC-LABEL: foo:
; LINUX-PIC: @ %bb.0: @ %entry ; LINUX-PIC: @ %bb.0: @ %entry
; LINUX-PIC-NEXT: .save {r4, lr} ; LINUX-PIC-NEXT: .save {r4, lr}
; LINUX-PIC-NEXT: push {r4, lr} ; LINUX-PIC-NEXT: push {r4, lr}
; LINUX-PIC-NEXT: ldr r4, .LCPI0_0 ; LINUX-PIC-NEXT: ldr r4, .LCPI0_0
; LINUX-PIC-NEXT: mov r0, #0
; LINUX-PIC-NEXT: .LPC0_0: ; LINUX-PIC-NEXT: .LPC0_0:
; LINUX-PIC-NEXT: ldr r4, [pc, r4] ; LINUX-PIC-NEXT: ldr r4, [pc, r4]
; LINUX-PIC-NEXT: ldrb r0, [r4] ; LINUX-PIC-NEXT: ldrb r1, [r4]
; LINUX-PIC-NEXT: cmp r0, #0 ; LINUX-PIC-NEXT: cmp r1, #0
; LINUX-PIC-NEXT: movne r0, #0 ; LINUX-PIC-NEXT: beq .LBB0_2
; LINUX-PIC-NEXT: popne {r4, pc} ; LINUX-PIC-NEXT: @ %bb.1: @ %common.ret
; LINUX-PIC-NEXT: .LBB0_1: @ %bb1 ; LINUX-PIC-NEXT: sxtb r0, r0
; LINUX-PIC-NEXT: pop {r4, pc}
; LINUX-PIC-NEXT: .LBB0_2: @ %bb1
; LINUX-PIC-NEXT: bl bar ; LINUX-PIC-NEXT: bl bar
; LINUX-PIC-NEXT: ldrsb r0, [r4] ; LINUX-PIC-NEXT: ldrb r0, [r4]
; LINUX-PIC-NEXT: sxtb r0, r0
; LINUX-PIC-NEXT: pop {r4, pc} ; LINUX-PIC-NEXT: pop {r4, pc}
; LINUX-PIC-NEXT: .p2align 2 ; LINUX-PIC-NEXT: .p2align 2
; LINUX-PIC-NEXT: @ %bb.2: ; LINUX-PIC-NEXT: @ %bb.3:
; LINUX-PIC-NEXT: .LCPI0_0: ; LINUX-PIC-NEXT: .LCPI0_0:
; LINUX-PIC-NEXT: .Ltmp0: ; LINUX-PIC-NEXT: .Ltmp0:
; LINUX-PIC-NEXT: .long x(GOT_PREL)-((.LPC0_0+8)-.Ltmp0) ; LINUX-PIC-NEXT: .long x(GOT_PREL)-((.LPC0_0+8)-.Ltmp0)
entry: entry:
%0 = load i8, i8* @x %0 = load i8, i8* @x
%tobool = icmp eq i8 %0, 0 %tobool = icmp eq i8 %0, 0
br i1 %tobool, label %bb1, label %bb2 br i1 %tobool, label %bb1, label %bb2
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llvm/test/CodeGen/ARM/smml.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-V4 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-V4
; RUN: llc -mtriple=armv6-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-V6 ; RUN: llc -mtriple=armv6-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-V6V7,CHECK-ARM-V6V7,CHECK-V6
; RUN: llc -mtriple=armv7-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-V6 ; RUN: llc -mtriple=armv7-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-V6V7,CHECK-ARM-V6V7,CHECK-V7
; RUN: llc -mtriple=thumb-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-THUMB ; RUN: llc -mtriple=thumb-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-THUMB
; RUN: llc -mtriple=thumbv6-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-THUMBV6 ; RUN: llc -mtriple=thumbv6-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-THUMBV6
; RUN: llc -mtriple=thumbv6t2-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-THUMBV6T2 ; RUN: llc -mtriple=thumbv6t2-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-V6V7,CHECK-THUMB-V6V7,CHECK-THUMBV6T2
; RUN: llc -mtriple=thumbv7-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-THUMBV6T2 ; RUN: llc -mtriple=thumbv7-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-V6V7,CHECK-THUMB-V6V7,CHECK-THUMBV7
; RUN: llc -mtriple=thumbv7m-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-V4-THUMBV7M ; RUN: llc -mtriple=thumbv7m-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-THUMBV7M
; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-THUMBV6T2 ; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-V6V7,CHECK-THUMB-V6V7,CHECK-THUMBV7EM
; Next test would previously trigger an assertion responsible for verification of ; Next test would previously trigger an assertion responsible for verification of
; call site info state. ; call site info state.
; RUN: llc -stop-after=if-converter -debug-entry-values -mtriple=thumbv6t2-eabi %s -o -| FileCheck %s -check-prefix=CHECK-CALLSITE ; RUN: llc -stop-after=if-converter -debug-entry-values -mtriple=thumbv6t2-eabi %s -o -| FileCheck %s -check-prefix=CHECK-CALLSITE
; CHECK-CALLSITE: name: test_used_flags ; CHECK-CALLSITE: name: test_used_flags
; CHECK-CALLSITE: callSites: ; CHECK-CALLSITE: callSites:
define i32 @Test0(i32 %a, i32 %b, i32 %c) nounwind readnone ssp { define i32 @Test0(i32 %a, i32 %b, i32 %c) nounwind readnone ssp {
; CHECK-V4-LABEL: Test0: ; CHECK-V4-LABEL: Test0:
; CHECK-V4: @ %bb.0: @ %entry ; CHECK-V4: @ %bb.0: @ %entry
; CHECK-V4-NEXT: smull r3, r12, r2, r1 ; CHECK-V4-NEXT: smull r3, r12, r2, r1
; CHECK-V4-NEXT: sub r0, r0, r12 ; CHECK-V4-NEXT: sub r0, r0, r12
; CHECK-V4-NEXT: mov pc, lr ; CHECK-V4-NEXT: mov pc, lr
; ;
; CHECK-V6-LABEL: Test0: ; CHECK-ARM-V6V7-LABEL: Test0:
; CHECK-V6: @ %bb.0: @ %entry ; CHECK-ARM-V6V7: @ %bb.0: @ %entry
; CHECK-V6-NEXT: smmul r1, r2, r1 ; CHECK-ARM-V6V7-NEXT: smmul r1, r2, r1
; CHECK-V6-NEXT: sub r0, r0, r1 ; CHECK-ARM-V6V7-NEXT: sub r0, r0, r1
; CHECK-V6-NEXT: bx lr ; CHECK-ARM-V6V7-NEXT: bx lr
; ;
; CHECK-THUMB-LABEL: Test0: ; CHECK-THUMB-LABEL: Test0:
; CHECK-THUMB: @ %bb.0: @ %entry ; CHECK-THUMB: @ %bb.0: @ %entry
; CHECK-THUMB-NEXT: .save {r4, r5, r7, lr} ; CHECK-THUMB-NEXT: .save {r4, r5, r7, lr}
; CHECK-THUMB-NEXT: push {r4, r5, r7, lr} ; CHECK-THUMB-NEXT: push {r4, r5, r7, lr}
; CHECK-THUMB-NEXT: movs r5, r1 ; CHECK-THUMB-NEXT: movs r5, r1
; CHECK-THUMB-NEXT: movs r4, r0 ; CHECK-THUMB-NEXT: movs r4, r0
; CHECK-THUMB-NEXT: asrs r1, r2, #31 ; CHECK-THUMB-NEXT: asrs r1, r2, #31
Show All 15 Lines
; CHECK-THUMBV6-NEXT: asrs r1, r2, #31 ; CHECK-THUMBV6-NEXT: asrs r1, r2, #31
; CHECK-THUMBV6-NEXT: asrs r3, r5, #31 ; CHECK-THUMBV6-NEXT: asrs r3, r5, #31
; CHECK-THUMBV6-NEXT: mov r0, r2 ; CHECK-THUMBV6-NEXT: mov r0, r2
; CHECK-THUMBV6-NEXT: mov r2, r5 ; CHECK-THUMBV6-NEXT: mov r2, r5
; CHECK-THUMBV6-NEXT: bl __aeabi_lmul ; CHECK-THUMBV6-NEXT: bl __aeabi_lmul
; CHECK-THUMBV6-NEXT: subs r0, r4, r1 ; CHECK-THUMBV6-NEXT: subs r0, r4, r1
; CHECK-THUMBV6-NEXT: pop {r4, r5, r7, pc} ; CHECK-THUMBV6-NEXT: pop {r4, r5, r7, pc}
; ;
; CHECK-THUMBV6T2-LABEL: Test0: ; CHECK-THUMB-V6V7-LABEL: Test0:
; CHECK-THUMBV6T2: @ %bb.0: @ %entry ; CHECK-THUMB-V6V7: @ %bb.0: @ %entry
; CHECK-THUMBV6T2-NEXT: smmul r1, r2, r1 ; CHECK-THUMB-V6V7-NEXT: smmul r1, r2, r1
; CHECK-THUMBV6T2-NEXT: subs r0, r0, r1 ; CHECK-THUMB-V6V7-NEXT: subs r0, r0, r1
; CHECK-THUMBV6T2-NEXT: bx lr ; CHECK-THUMB-V6V7-NEXT: bx lr
; ;
; CHECK-V4-THUMBV7M-LABEL: Test0: ; CHECK-THUMBV7M-LABEL: Test0:
dmgreenUnsubmitted
Done
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Is this left over?

dmgreen: Is this left over?
dmgreenUnsubmitted
Done
ReplyInline Actions

These look like they can share CHECK-V6V7?

dmgreen: These look like they can share CHECK-V6V7?
; CHECK-V4-THUMBV7M: @ %bb.0: @ %entry ; CHECK-THUMBV7M: @ %bb.0: @ %entry
; CHECK-V4-THUMBV7M-NEXT: smull r1, r2, r2, r1 ; CHECK-THUMBV7M-NEXT: smull r1, r2, r2, r1
; CHECK-V4-THUMBV7M-NEXT: subs r0, r0, r2 ; CHECK-THUMBV7M-NEXT: subs r0, r0, r2
; CHECK-V4-THUMBV7M-NEXT: bx lr ; CHECK-THUMBV7M-NEXT: bx lr
entry: entry:
%conv4 = zext i32 %a to i64 %conv4 = zext i32 %a to i64
%conv1 = sext i32 %b to i64 %conv1 = sext i32 %b to i64
%conv2 = sext i32 %c to i64 %conv2 = sext i32 %c to i64
%mul = mul nsw i64 %conv2, %conv1 %mul = mul nsw i64 %conv2, %conv1
%shr5 = lshr i64 %mul, 32 %shr5 = lshr i64 %mul, 32
%sub = sub nsw i64 %conv4, %shr5 %sub = sub nsw i64 %conv4, %shr5
%conv3 = trunc i64 %sub to i32 %conv3 = trunc i64 %sub to i32
ret i32 %conv3 ret i32 %conv3
} }
define i32 @Test1(i32 %a, i32 %b, i32 %c) { define i32 @Test1(i32 %a, i32 %b, i32 %c) {
; CHECK-V4-LABEL: Test1: ; CHECK-V4-LABEL: Test1:
; CHECK-V4: @ %bb.0: @ %entry ; CHECK-V4: @ %bb.0: @ %entry
; CHECK-V4-NEXT: smull r3, r12, r2, r1 ; CHECK-V4-NEXT: smull r3, r12, r2, r1
; CHECK-V4-NEXT: rsbs r1, r3, #0 ; CHECK-V4-NEXT: rsbs r1, r3, #0
; CHECK-V4-NEXT: sbc r0, r0, r12 ; CHECK-V4-NEXT: sbc r0, r0, r12
; CHECK-V4-NEXT: mov pc, lr ; CHECK-V4-NEXT: mov pc, lr
; ;
; CHECK-V6-LABEL: Test1: ; CHECK-V6V7-LABEL: Test1:
; CHECK-V6: @ %bb.0: @ %entry ; CHECK-V6V7: @ %bb.0: @ %entry
; CHECK-V6-NEXT: smmls r0, r2, r1, r0 ; CHECK-V6V7-NEXT: smmls r0, r2, r1, r0
; CHECK-V6-NEXT: bx lr ; CHECK-V6V7-NEXT: bx lr
; ;
; CHECK-THUMB-LABEL: Test1: ; CHECK-THUMB-LABEL: Test1:
; CHECK-THUMB: @ %bb.0: @ %entry ; CHECK-THUMB: @ %bb.0: @ %entry
; CHECK-THUMB-NEXT: .save {r4, r5, r7, lr} ; CHECK-THUMB-NEXT: .save {r4, r5, r7, lr}
; CHECK-THUMB-NEXT: push {r4, r5, r7, lr} ; CHECK-THUMB-NEXT: push {r4, r5, r7, lr}
; CHECK-THUMB-NEXT: movs r5, r1 ; CHECK-THUMB-NEXT: movs r5, r1
; CHECK-THUMB-NEXT: movs r4, r0 ; CHECK-THUMB-NEXT: movs r4, r0
; CHECK-THUMB-NEXT: asrs r1, r2, #31 ; CHECK-THUMB-NEXT: asrs r1, r2, #31
Show All 19 Lines
; CHECK-THUMBV6-NEXT: mov r0, r2 ; CHECK-THUMBV6-NEXT: mov r0, r2
; CHECK-THUMBV6-NEXT: mov r2, r5 ; CHECK-THUMBV6-NEXT: mov r2, r5
; CHECK-THUMBV6-NEXT: bl __aeabi_lmul ; CHECK-THUMBV6-NEXT: bl __aeabi_lmul
; CHECK-THUMBV6-NEXT: rsbs r0, r0, #0 ; CHECK-THUMBV6-NEXT: rsbs r0, r0, #0
; CHECK-THUMBV6-NEXT: sbcs r4, r1 ; CHECK-THUMBV6-NEXT: sbcs r4, r1
; CHECK-THUMBV6-NEXT: mov r0, r4 ; CHECK-THUMBV6-NEXT: mov r0, r4
; CHECK-THUMBV6-NEXT: pop {r4, r5, r7, pc} ; CHECK-THUMBV6-NEXT: pop {r4, r5, r7, pc}
; ;
; CHECK-THUMBV6T2-LABEL: Test1: ; CHECK-THUMBV7M-LABEL: Test1:
; CHECK-THUMBV6T2: @ %bb.0: @ %entry ; CHECK-THUMBV7M: @ %bb.0: @ %entry
; CHECK-THUMBV6T2-NEXT: smmls r0, r2, r1, r0 ; CHECK-THUMBV7M-NEXT: smull r1, r2, r2, r1
; CHECK-THUMBV6T2-NEXT: bx lr ; CHECK-THUMBV7M-NEXT: rsbs r1, r1, #0
; ; CHECK-THUMBV7M-NEXT: sbcs r0, r2
; CHECK-V4-THUMBV7M-LABEL: Test1: ; CHECK-THUMBV7M-NEXT: bx lr
; CHECK-V4-THUMBV7M: @ %bb.0: @ %entry
; CHECK-V4-THUMBV7M-NEXT: smull r1, r2, r2, r1
; CHECK-V4-THUMBV7M-NEXT: rsbs r1, r1, #0
; CHECK-V4-THUMBV7M-NEXT: sbcs r0, r2
; CHECK-V4-THUMBV7M-NEXT: bx lr
entry: entry:
%conv = sext i32 %b to i64 %conv = sext i32 %b to i64
%conv1 = sext i32 %c to i64 %conv1 = sext i32 %c to i64
%mul = mul nsw i64 %conv1, %conv %mul = mul nsw i64 %conv1, %conv
%conv26 = zext i32 %a to i64 %conv26 = zext i32 %a to i64
%shl = shl nuw i64 %conv26, 32 %shl = shl nuw i64 %conv26, 32
%sub = sub nsw i64 %shl, %mul %sub = sub nsw i64 %shl, %mul
%shr7 = lshr i64 %sub, 32 %shr7 = lshr i64 %sub, 32
Show All 11 Lines
; CHECK-V4-NEXT: rsbs r0, r2, #0 ; CHECK-V4-NEXT: rsbs r0, r2, #0
; CHECK-V4-NEXT: rscs r0, r3, #0 ; CHECK-V4-NEXT: rscs r0, r3, #0
; CHECK-V4-NEXT: movge r0, #42 ; CHECK-V4-NEXT: movge r0, #42
; CHECK-V4-NEXT: movlt r0, #56 ; CHECK-V4-NEXT: movlt r0, #56
; CHECK-V4-NEXT: bl opaque ; CHECK-V4-NEXT: bl opaque
; CHECK-V4-NEXT: pop {r11, lr} ; CHECK-V4-NEXT: pop {r11, lr}
; CHECK-V4-NEXT: mov pc, lr ; CHECK-V4-NEXT: mov pc, lr
; ;
; CHECK-V6-LABEL: test_used_flags: ; CHECK-V6-LABEL: test_used_flags:
rnkUnsubmitted
Not Done
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I can't understand why these checks disappeared. Is this a bug in the check generation script?

rnk: I can't understand why these checks disappeared. Is this a bug in the check generation script?
; CHECK-V6: @ %bb.0: ; CHECK-V6: @ %bb.0: @ %common.ret
; CHECK-V6-NEXT: .save {r11, lr} ; CHECK-V6-NEXT: .save {r11, lr}
; CHECK-V6-NEXT: push {r11, lr} ; CHECK-V6-NEXT: push {r11, lr}
; CHECK-V6-NEXT: smull r0, r1, r0, r1 ; CHECK-V6-NEXT: smull r1, r2, r0, r1
; CHECK-V6-NEXT: rsbs r0, r0, #0
; CHECK-V6-NEXT: rscs r0, r1, #0
; CHECK-V6-NEXT: bge .LBB2_2
; CHECK-V6-NEXT: @ %bb.1: @ %false
; CHECK-V6-NEXT: mov r0, #56 ; CHECK-V6-NEXT: mov r0, #56
; CHECK-V6-NEXT: subs r1, r1, #1
; CHECK-V6-NEXT: sbcs r1, r2, #0
; CHECK-V6-NEXT: movlt r0, #42
; CHECK-V6-NEXT: bl opaque ; CHECK-V6-NEXT: bl opaque
; CHECK-V6-NEXT: pop {r11, pc} ; CHECK-V6-NEXT: pop {r11, pc}
; CHECK-V6-NEXT: .LBB2_2: @ %true ;
; CHECK-V6-NEXT: mov r0, #42 ; CHECK-V7-LABEL: test_used_flags:
; CHECK-V6-NEXT: bl opaque ; CHECK-V7: @ %bb.0: @ %common.ret
; CHECK-V6-NEXT: pop {r11, pc} ; CHECK-V7-NEXT: .save {r11, lr}
; CHECK-V7-NEXT: push {r11, lr}
; CHECK-V7-NEXT: smull r1, r2, r0, r1
; CHECK-V7-NEXT: mov r0, #56
; CHECK-V7-NEXT: subs r1, r1, #1
; CHECK-V7-NEXT: sbcs r1, r2, #0
; CHECK-V7-NEXT: movwlt r0, #42
; CHECK-V7-NEXT: bl opaque
; CHECK-V7-NEXT: pop {r11, pc}
; ;
; CHECK-THUMB-LABEL: test_used_flags: ; CHECK-THUMB-LABEL: test_used_flags:
; CHECK-THUMB: @ %bb.0: ; CHECK-THUMB: @ %bb.0:
; CHECK-THUMB-NEXT: .save {r7, lr} ; CHECK-THUMB-NEXT: .save {r7, lr}
; CHECK-THUMB-NEXT: push {r7, lr} ; CHECK-THUMB-NEXT: push {r7, lr}
; CHECK-THUMB-NEXT: movs r2, r1 ; CHECK-THUMB-NEXT: movs r2, r1
; CHECK-THUMB-NEXT: asrs r1, r0, #31 ; CHECK-THUMB-NEXT: asrs r1, r0, #31
; CHECK-THUMB-NEXT: asrs r3, r2, #31 ; CHECK-THUMB-NEXT: asrs r3, r2, #31
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK-THUMBV6T2-NEXT: rsbs r0, r0, #0 ; CHECK-THUMBV6T2-NEXT: rsbs r0, r0, #0
; CHECK-THUMBV6T2-NEXT: sbcs.w r0, r2, r1 ; CHECK-THUMBV6T2-NEXT: sbcs.w r0, r2, r1
; CHECK-THUMBV6T2-NEXT: ite lt ; CHECK-THUMBV6T2-NEXT: ite lt
; CHECK-THUMBV6T2-NEXT: movlt r0, #56 ; CHECK-THUMBV6T2-NEXT: movlt r0, #56
; CHECK-THUMBV6T2-NEXT: movge r0, #42 ; CHECK-THUMBV6T2-NEXT: movge r0, #42
; CHECK-THUMBV6T2-NEXT: bl opaque ; CHECK-THUMBV6T2-NEXT: bl opaque
; CHECK-THUMBV6T2-NEXT: pop {r7, pc} ; CHECK-THUMBV6T2-NEXT: pop {r7, pc}
; ;
; CHECK-V4-THUMBV7M-LABEL: test_used_flags: ; CHECK-THUMBV7-LABEL: test_used_flags:
; CHECK-V4-THUMBV7M: @ %bb.0: ; CHECK-THUMBV7: @ %bb.0: @ %common.ret
; CHECK-V4-THUMBV7M-NEXT: .save {r7, lr} ; CHECK-THUMBV7-NEXT: .save {r7, lr}
; CHECK-V4-THUMBV7M-NEXT: push {r7, lr} ; CHECK-THUMBV7-NEXT: push {r7, lr}
; CHECK-V4-THUMBV7M-NEXT: smull r0, r1, r0, r1 ; CHECK-THUMBV7-NEXT: smull r1, r2, r0, r1
; CHECK-V4-THUMBV7M-NEXT: movs r2, #0 ; CHECK-THUMBV7-NEXT: movs r0, #56
; CHECK-V4-THUMBV7M-NEXT: rsbs r0, r0, #0 ; CHECK-THUMBV7-NEXT: subs r1, #1
; CHECK-V4-THUMBV7M-NEXT: sbcs.w r0, r2, r1 ; CHECK-THUMBV7-NEXT: sbcs r1, r2, #0
; CHECK-V4-THUMBV7M-NEXT: ite lt ; CHECK-THUMBV7-NEXT: it lt
; CHECK-V4-THUMBV7M-NEXT: movlt r0, #56 ; CHECK-THUMBV7-NEXT: movlt r0, #42
; CHECK-V4-THUMBV7M-NEXT: movge r0, #42 ; CHECK-THUMBV7-NEXT: bl opaque
; CHECK-V4-THUMBV7M-NEXT: bl opaque ; CHECK-THUMBV7-NEXT: pop {r7, pc}
; CHECK-V4-THUMBV7M-NEXT: pop {r7, pc} ;
; CHECK-THUMBV7M-LABEL: test_used_flags:
; CHECK-THUMBV7M: @ %bb.0: @ %common.ret
; CHECK-THUMBV7M-NEXT: .save {r7, lr}
; CHECK-THUMBV7M-NEXT: push {r7, lr}
; CHECK-THUMBV7M-NEXT: smull r1, r2, r0, r1
; CHECK-THUMBV7M-NEXT: movs r0, #56
; CHECK-THUMBV7M-NEXT: subs r1, #1
; CHECK-THUMBV7M-NEXT: sbcs r1, r2, #0
; CHECK-THUMBV7M-NEXT: it lt
; CHECK-THUMBV7M-NEXT: movlt r0, #42
; CHECK-THUMBV7M-NEXT: bl opaque
; CHECK-THUMBV7M-NEXT: pop {r7, pc}
;
; CHECK-THUMBV7EM-LABEL: test_used_flags:
; CHECK-THUMBV7EM: @ %bb.0: @ %common.ret
; CHECK-THUMBV7EM-NEXT: .save {r7, lr}
; CHECK-THUMBV7EM-NEXT: push {r7, lr}
; CHECK-THUMBV7EM-NEXT: smull r1, r2, r0, r1
; CHECK-THUMBV7EM-NEXT: movs r0, #56
; CHECK-THUMBV7EM-NEXT: subs r1, #1
; CHECK-THUMBV7EM-NEXT: sbcs r1, r2, #0
; CHECK-THUMBV7EM-NEXT: it lt
; CHECK-THUMBV7EM-NEXT: movlt r0, #42
; CHECK-THUMBV7EM-NEXT: bl opaque
; CHECK-THUMBV7EM-NEXT: pop {r7, pc}
%in1.64 = sext i32 %in1 to i64 %in1.64 = sext i32 %in1 to i64
%in2.64 = sext i32 %in2 to i64 %in2.64 = sext i32 %in2 to i64
%mul = mul nsw i64 %in1.64, %in2.64 %mul = mul nsw i64 %in1.64, %in2.64
%tst = icmp slt i64 %mul, 1 %tst = icmp slt i64 %mul, 1
br i1 %tst, label %true, label %false br i1 %tst, label %true, label %false
true: true:
call void @opaque(i32 42) call void @opaque(i32 42)
ret void ret void
false: false:
call void @opaque(i32 56) call void @opaque(i32 56)
ret void ret void
} }

llvm/test/CodeGen/ARM/speculation-hardening-sls.ll

Show All 20 Lines
; RUN: llc -fast-isel -mattr=harden-sls-retbr -mattr=harden-sls-blr -mattr=harden-sls-nocomdat -verify-machineinstrs -mtriple=thumbv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=HARDEN,HARDEN-COMDAT-OFF,ISBDSB ; RUN: llc -fast-isel -mattr=harden-sls-retbr -mattr=harden-sls-blr -mattr=harden-sls-nocomdat -verify-machineinstrs -mtriple=thumbv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=HARDEN,HARDEN-COMDAT-OFF,ISBDSB
; RUN: llc -fast-isel -mattr=harden-sls-retbr -mattr=harden-sls-blr -mattr=+sb -verify-machineinstrs -mtriple=armv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=HARDEN,SB ; RUN: llc -fast-isel -mattr=harden-sls-retbr -mattr=harden-sls-blr -mattr=+sb -verify-machineinstrs -mtriple=armv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=HARDEN,SB
; RUN: llc -fast-isel -mattr=harden-sls-retbr -mattr=harden-sls-blr -mattr=+sb -verify-machineinstrs -mtriple=thumbv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=HARDEN,SB ; RUN: llc -fast-isel -mattr=harden-sls-retbr -mattr=harden-sls-blr -mattr=+sb -verify-machineinstrs -mtriple=thumbv8-linux-gnueabi < %s | FileCheck %s --check-prefixes=HARDEN,SB
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define dso_local i32 @double_return(i32 %a, i32 %b) local_unnamed_addr { define dso_local i32 @double_return(i32 %a, i32 %b) local_unnamed_addr {
; NOHARDENARM-LABEL: double_return: ; NOHARDENARM-LABEL: double_return:
; NOHARDENARM: @ %bb.0: @ %entry ; NOHARDENARM: @ %bb.0: @ %entry
; NOHARDENARM-NEXT: cmp r0, #1 ; NOHARDENARM-NEXT: cmp r0, #0
; NOHARDENARM-NEXT: mulge r0, r1, r0 ; NOHARDENARM-NEXT: mulgt r0, r1, r0
; NOHARDENARM-NEXT: bxge lr ; NOHARDENARM-NEXT: bxgt lr
; NOHARDENARM-NEXT: .LBB0_1: @ %if.else ; NOHARDENARM-NEXT: .LBB0_1: @ %if.else
; NOHARDENARM-NEXT: sdiv r1, r0, r1 ; NOHARDENARM-NEXT: sdiv r1, r0, r1
; NOHARDENARM-NEXT: sdiv r1, r0, r1 ; NOHARDENARM-NEXT: sdiv r1, r0, r1
; NOHARDENARM-NEXT: sdiv r0, r0, r1 ; NOHARDENARM-NEXT: sdiv r0, r0, r1
; NOHARDENARM-NEXT: bx lr ; NOHARDENARM-NEXT: bx lr
; ;
; NOHARDENTHUMB-LABEL: double_return: ; NOHARDENTHUMB-LABEL: double_return:
; NOHARDENTHUMB: @ %bb.0: @ %entry ; NOHARDENTHUMB: @ %bb.0: @ %entry
; NOHARDENTHUMB-NEXT: cmp r0, #1 ; NOHARDENTHUMB-NEXT: cmp r0, #0
; NOHARDENTHUMB-NEXT: blt .LBB0_2 ; NOHARDENTHUMB-NEXT: ble .LBB0_2
; NOHARDENTHUMB-NEXT: @ %bb.1: @ %if.then ; NOHARDENTHUMB-NEXT: @ %bb.1: @ %if.then
; NOHARDENTHUMB-NEXT: muls r0, r1, r0 ; NOHARDENTHUMB-NEXT: muls r0, r1, r0
; NOHARDENTHUMB-NEXT: bx lr ; NOHARDENTHUMB-NEXT: bx lr
; NOHARDENTHUMB-NEXT: .LBB0_2: @ %if.else ; NOHARDENTHUMB-NEXT: .LBB0_2: @ %if.else
; NOHARDENTHUMB-NEXT: sdiv r1, r0, r1 ; NOHARDENTHUMB-NEXT: sdiv r1, r0, r1
; NOHARDENTHUMB-NEXT: sdiv r1, r0, r1 ; NOHARDENTHUMB-NEXT: sdiv r1, r0, r1
; NOHARDENTHUMB-NEXT: sdiv r0, r0, r1 ; NOHARDENTHUMB-NEXT: sdiv r0, r0, r1
; NOHARDENTHUMB-NEXT: bx lr ; NOHARDENTHUMB-NEXT: bx lr
▲ Show 20 Lines • Show All 388 Lines • Show Last 20 Lines

llvm/test/CodeGen/ARM/switch-minsize.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s ; RUN: llc < %s | FileCheck %s
target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
target triple = "thumbv7-apple-ios8.0.0" target triple = "thumbv7-apple-ios8.0.0"
declare void @g(i32) declare void @g(i32)
define void @f(i32 %val) optsize minsize { define void @f(i32 %val) optsize minsize {
; CHECK-LABEL: f: ; CHECK-LABEL: f:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: str lr, [sp, #-4]! ; CHECK-NEXT: mov r1, r0
; CHECK-NEXT: movw r1, #1154 ; CHECK-NEXT: movs r0, #1
; CHECK-NEXT: cmp r0, r1 ; CHECK-NEXT: cbz r1, LBB0_6
; CHECK-NEXT: beq LBB0_5
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: cmp r0, #9 ; CHECK-NEXT: movw r2, #1154
; CHECK-NEXT: cmp r1, r2
; CHECK-NEXT: beq LBB0_4 ; CHECK-NEXT: beq LBB0_4
; CHECK-NEXT: @ %bb.2: ; CHECK-NEXT: @ %bb.2:
; CHECK-NEXT: movw r1, #994 ; CHECK-NEXT: movw r2, #994
; CHECK-NEXT: cmp r0, r1 ; CHECK-NEXT: cmp r1, r2
; CHECK-NEXT: beq LBB0_6 ; CHECK-NEXT: beq LBB0_5
; CHECK-NEXT: @ %bb.3: ; CHECK-NEXT: @ %bb.3:
; CHECK-NEXT: cbnz r0, LBB0_7 ; CHECK-NEXT: cmp r1, #9
; CHECK-NEXT: LBB0_4: @ %two ; CHECK-NEXT: it ne
; CHECK-NEXT: movs r0, #1 ; CHECK-NEXT: movne r0, #11
; CHECK-NEXT: b LBB0_8 ; CHECK-NEXT: b LBB0_6
; CHECK-NEXT: LBB0_5: @ %four ; CHECK-NEXT: LBB0_4: @ %four
; CHECK-NEXT: movs r0, #87 ; CHECK-NEXT: movs r0, #87
; CHECK-NEXT: b LBB0_8 ; CHECK-NEXT: b LBB0_6
; CHECK-NEXT: LBB0_6: @ %three ; CHECK-NEXT: LBB0_5: @ %three
; CHECK-NEXT: movs r0, #78 ; CHECK-NEXT: movs r0, #78
; CHECK-NEXT: b LBB0_8 ; CHECK-NEXT: LBB0_6: @ %common.ret
; CHECK-NEXT: LBB0_7: @ %def ; CHECK-NEXT: str lr, [sp, #-4]!
; CHECK-NEXT: movs r0, #11
; CHECK-NEXT: LBB0_8: @ %two
; CHECK-NEXT: bl _g ; CHECK-NEXT: bl _g
; CHECK-NEXT: ldr lr, [sp], #4 ; CHECK-NEXT: ldr lr, [sp], #4
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
switch i32 %val, label %def [ switch i32 %val, label %def [
i32 0, label %one i32 0, label %one
i32 9, label %two i32 9, label %two
i32 994, label %three i32 994, label %three
i32 1154, label %four i32 1154, label %four
Show All 18 Lines

llvm/test/CodeGen/ARM/thumb2-size-opt.ll

Show First 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
; CHECK-OPT: lsrs r{{[0-7]}}, r{{[0-7]}} @ encoding: [{{0x..,0x..}}] ; CHECK-OPT: lsrs r{{[0-7]}}, r{{[0-7]}} @ encoding: [{{0x..,0x..}}]
entry: entry:
%shr = lshr i32 %a, %b %shr = lshr i32 %a, %b
ret i32 %shr ret i32 %shr
} }
define i32 @bundled_instruction(i32* %addr, i32** %addr2, i1 %tst) minsize { define i32 @bundled_instruction(i32* %addr, i32** %addr2, i1 %tst) minsize {
; CHECK-LABEL: bundled_instruction: ; CHECK-LABEL: bundled_instruction:
; CHECK: iteee ne ; CHECK: itee ne
; CHECK: ldmeq r0!, {{{r[0-9]+}}} ; CHECK: ldmeq r3!, {{{r[0-9]+}}}
br i1 %tst, label %true, label %false br i1 %tst, label %true, label %false
true: true:
ret i32 0 ret i32 0
false: false:
%res = load i32, i32* %addr, align 4 %res = load i32, i32* %addr, align 4
%next = getelementptr i32, i32* %addr, i32 1 %next = getelementptr i32, i32* %addr, i32 1
Show All 16 Lines

llvm/test/CodeGen/Hexagon/dont_rotate_pregs_at_O2.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=hexagon -O2 < %s | FileCheck %s ; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
define i32 @f0(i32 %a0, i32 %a1) #0 { define i32 @f0(i32 %a0, i32 %a1) #0 {
; CHECK-LABEL: f0: ; CHECK-LABEL: f0:
; CHECK: .cfi_startproc ; CHECK: .cfi_startproc
; CHECK-NEXT: // %bb.0: // %b0 ; CHECK-NEXT: // %bb.0: // %b0
; CHECK-NEXT: { ; CHECK-NEXT: {
; CHECK-NEXT: p0 = cmp.gt(r1,r0)
; CHECK-NEXT: if (p0.new) r0 = #0
; CHECK-NEXT: if (p0.new) jumpr:nt r31
; CHECK-NEXT: }
; CHECK-NEXT: .LBB0_1: // %b2
; CHECK-NEXT: {
; CHECK-NEXT: p0 = cmp.gt(r1,#99) ; CHECK-NEXT: p0 = cmp.gt(r1,#99)
; CHECK-NEXT: p1 = cmp.gt(r1,r0)
; CHECK-NEXT: } ; CHECK-NEXT: }
; CHECK-NEXT: { ; CHECK-NEXT: {
; CHECK-NEXT: r0 = mux(p0,##321,#123) ; CHECK-NEXT: r0 = mux(p0,##321,#123)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: if (p1) r0 = #0
; CHECK-NEXT: jumpr r31 ; CHECK-NEXT: jumpr r31
; CHECK-NEXT: } ; CHECK-NEXT: }
b0: b0:
%v0 = icmp slt i32 %a0, %a1 %v0 = icmp slt i32 %a0, %a1
br i1 %v0, label %b1, label %b2 br i1 %v0, label %b1, label %b2
b1: b1:
ret i32 0 ret i32 0
b2: b2:
%v1 = icmp slt i32 %a1, 100 %v1 = icmp slt i32 %a1, 100
%v2 = select i1 %v1, i32 123, i32 321 %v2 = select i1 %v1, i32 123, i32 321
ret i32 %v2 ret i32 %v2
} }

llvm/test/CodeGen/Hexagon/noFalignAfterCallAtO2.ll

Show All 24 Lines
; CHECK-NEXT: } // 8-byte Folded Spill ; CHECK-NEXT: } // 8-byte Folded Spill
; CHECK-NEXT: { ; CHECK-NEXT: {
; CHECK-NEXT: call f0 ; CHECK-NEXT: call f0
; CHECK-NEXT: r16 = r0 ; CHECK-NEXT: r16 = r0
; CHECK-NEXT: } ; CHECK-NEXT: }
; CHECK-NEXT: { ; CHECK-NEXT: {
; CHECK-NEXT: r0 = add(r16,r0) ; CHECK-NEXT: r0 = add(r16,r0)
; CHECK-NEXT: r17:16 = memd(r29+#0) ; CHECK-NEXT: r17:16 = memd(r29+#0)
; CHECK-NEXT: dealloc_return ; CHECK-NEXT: deallocframe
; CHECK-NEXT: } // 8-byte Folded Reload ; CHECK-NEXT: } // 8-byte Folded Reload
; CHECK-NEXT: {
; CHECK-NEXT: jumpr r31
; CHECK-NEXT: }
b0: b0:
%v0 = icmp eq i32 %a0, 0 %v0 = icmp eq i32 %a0, 0
br i1 %v0, label %b1, label %b2 br i1 %v0, label %b1, label %b2
b1: ; preds = %b0 b1: ; preds = %b0
%v1 = call i32 @f0() %v1 = call i32 @f0()
%v2 = call i32 @f0() %v2 = call i32 @f0()
%v3 = add i32 %v1, %v2 %v3 = add i32 %v1, %v2
ret i32 %v3 ret i32 %v3
b2: ; preds = %b0 b2: ; preds = %b0
%v4 = add i32 %a0, 5 %v4 = add i32 %a0, 5
ret i32 %v4 ret i32 %v4
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/test/CodeGen/Thumb2/thumb2-ifcvt1.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefixes=ALL,V01 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefixes=ALL,V01
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -arm-default-it | FileCheck %s --check-prefixes=ALL,V01 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -arm-default-it | FileCheck %s --check-prefixes=ALL,V01
; RUN: llc < %s -mtriple=thumbv8 -arm-no-restrict-it | FileCheck %s --check-prefixes=ALL,V23,V2 ; RUN: llc < %s -mtriple=thumbv8 -arm-no-restrict-it | FileCheck %s --check-prefixes=ALL,V23,V2
; RUN: llc < %s -mtriple=thumbv8 -arm-no-restrict-it -enable-tail-merge=0 | FileCheck %s --check-prefixes=ALL,V23,V3 ; RUN: llc < %s -mtriple=thumbv8 -arm-no-restrict-it -enable-tail-merge=0 | FileCheck %s --check-prefixes=ALL,V23,V3
define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; ALL-LABEL: t1: ; ALL-LABEL: t1:
; ALL: @ %bb.0: ; ALL: @ %bb.0:
; ALL-NEXT: cmp r2, #7 ; ALL-NEXT: cmp r2, #1
; ALL-NEXT: ittee ne ; ALL-NEXT: ittee ne
; ALL-NEXT: cmpne r2, #1 ; ALL-NEXT: cmpne r2, #7
; ALL-NEXT: addne r0, r1 ; ALL-NEXT: addne r0, r1
; ALL-NEXT: addeq r0, r1 ; ALL-NEXT: addeq r0, r1
; ALL-NEXT: addeq r0, #1 ; ALL-NEXT: addeq r0, #1
; ALL-NEXT: bx lr ; ALL-NEXT: bx lr
switch i32 %c, label %cond_next [ switch i32 %c, label %cond_next [
i32 1, label %cond_true i32 1, label %cond_true
i32 7, label %cond_true i32 7, label %cond_true
] ]
▲ Show 20 Lines • Show All 216 Lines • ▼ Show 20 Linesentry:
%tmp = load i32*, i32** @x ; <i32*> [#uses=1] %tmp = load i32*, i32** @x ; <i32*> [#uses=1]
store i32 %a, i32* %tmp store i32 %a, i32* %tmp
ret void ret void
} }
define void @t3(i32 %a, i32 %b) nounwind { define void @t3(i32 %a, i32 %b) nounwind {
; V01-LABEL: t3: ; V01-LABEL: t3:
; V01: @ %bb.0: @ %entry ; V01: @ %bb.0: @ %entry
; V01-NEXT: cmp r0, #11 ; V01-NEXT: cmp r0, #10
; V01-NEXT: it lt ; V01-NEXT: it le
; V01-NEXT: bxlt lr ; V01-NEXT: bxle lr
; V01-NEXT: LBB4_1: @ %cond_true ; V01-NEXT: LBB4_1: @ %cond_true
; V01-NEXT: str lr, [sp, #-4]! ; V01-NEXT: str lr, [sp, #-4]!
; V01-NEXT: mov r0, r1 ; V01-NEXT: mov r0, r1
; V01-NEXT: bl _foo ; V01-NEXT: bl _foo
; V01-NEXT: ldr lr, [sp], #4 ; V01-NEXT: ldr lr, [sp], #4
; V01-NEXT: bx lr ; V01-NEXT: bx lr
; ;
; V23-LABEL: t3: ; V23-LABEL: t3:
; V23: @ %bb.0: @ %entry ; V23: @ %bb.0: @ %entry
; V23-NEXT: cmp r0, #11 ; V23-NEXT: cmp r0, #10
; V23-NEXT: it lt ; V23-NEXT: it le
; V23-NEXT: bxlt lr ; V23-NEXT: bxle lr
; V23-NEXT: .LBB4_1: @ %cond_true ; V23-NEXT: .LBB4_1: @ %cond_true
; V23-NEXT: push {r7, lr} ; V23-NEXT: push {r7, lr}
; V23-NEXT: mov r0, r1 ; V23-NEXT: mov r0, r1
; V23-NEXT: bl foo ; V23-NEXT: bl foo
; V23-NEXT: pop {r7, pc} ; V23-NEXT: pop.w {r7, lr}
; V23-NEXT: bx lr
entry: entry:
%tmp1 = icmp sgt i32 %a, 10 ; <i1> [#uses=1] %tmp1 = icmp sgt i32 %a, 10 ; <i1> [#uses=1]
br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock
cond_true: ; preds = %entry cond_true: ; preds = %entry
call void @foo( i32 %b ) call void @foo( i32 %b )
ret void ret void
UnifiedReturnBlock: ; preds = %entry UnifiedReturnBlock: ; preds = %entry
ret void ret void
} }

llvm/test/CodeGen/Thumb2/tpsoft.ll

Show All 20 Lines
; ELFASM-NEXT: .save {r7, lr} ; ELFASM-NEXT: .save {r7, lr}
; ELFASM-NEXT: push {r7, lr} ; ELFASM-NEXT: push {r7, lr}
; ELFASM-NEXT: ldr r0, .LCPI0_0 ; ELFASM-NEXT: ldr r0, .LCPI0_0
; ELFASM-NEXT: .LPC0_0: ; ELFASM-NEXT: .LPC0_0:
; ELFASM-NEXT: add r0, pc ; ELFASM-NEXT: add r0, pc
; ELFASM-NEXT: ldr r1, [r0] ; ELFASM-NEXT: ldr r1, [r0]
; ELFASM-NEXT: bl __aeabi_read_tp ; ELFASM-NEXT: bl __aeabi_read_tp
; ELFASM-NEXT: ldr r0, [r0, r1] ; ELFASM-NEXT: ldr r0, [r0, r1]
; ELFASM-NEXT: cmp r0, #13 ; ELFASM-NEXT: cmp r0, #12
; ELFASM-NEXT: beq .LBB0_3 ; ELFASM-NEXT: beq .LBB0_3
; ELFASM-NEXT: @ %bb.1: @ %entry ; ELFASM-NEXT: @ %bb.1: @ %entry
; ELFASM-NEXT: cmp r0, #12 ; ELFASM-NEXT: cmp r0, #13
; ELFASM-NEXT: itt ne ; ELFASM-NEXT: itt ne
; ELFASM-NEXT: movne.w r0, #-1 ; ELFASM-NEXT: movne.w r0, #-1
; ELFASM-NEXT: popne {r7, pc} ; ELFASM-NEXT: popne {r7, pc}
; ELFASM-NEXT: .LBB0_2: @ %bb ; ELFASM-NEXT: .LBB0_2: @ %bb1
; ELFASM-NEXT: movw r0, :lower16:a
; ELFASM-NEXT: movt r0, :upper16:a
; ELFASM-NEXT: pop.w {r7, lr}
; ELFASM-NEXT: b foo
; ELFASM-NEXT: .LBB0_3: @ %bb1
; ELFASM-NEXT: movw r0, :lower16:b ; ELFASM-NEXT: movw r0, :lower16:b
; ELFASM-NEXT: movt r0, :upper16:b ; ELFASM-NEXT: movt r0, :upper16:b
; ELFASM-NEXT: pop.w {r7, lr} ; ELFASM-NEXT: pop.w {r7, lr}
; ELFASM-NEXT: b bar ; ELFASM-NEXT: b bar
; ELFASM-NEXT: .LBB0_3: @ %bb
; ELFASM-NEXT: movw r0, :lower16:a
; ELFASM-NEXT: movt r0, :upper16:a
; ELFASM-NEXT: pop.w {r7, lr}
; ELFASM-NEXT: b foo
; ELFASM-NEXT: .p2align 2 ; ELFASM-NEXT: .p2align 2
; ELFASM-NEXT: @ %bb.4: ; ELFASM-NEXT: @ %bb.4:
; ELFASM-NEXT: .LCPI0_0: ; ELFASM-NEXT: .LCPI0_0:
; ELFASM-NEXT: .Ltmp0: ; ELFASM-NEXT: .Ltmp0:
; ELFASM-NEXT: .long i(GOTTPOFF)-((.LPC0_0+4)-.Ltmp0) ; ELFASM-NEXT: .long i(GOTTPOFF)-((.LPC0_0+4)-.Ltmp0)
entry: entry:
%0 = load i32, i32* @i, align 4 %0 = load i32, i32* @i, align 4
switch i32 %0, label %bb2 [ switch i32 %0, label %bb2 [
i32 12, label %bb i32 12, label %bb
i32 13, label %bb1 i32 13, label %bb1
] ]
bb: ; preds = %entry bb: ; preds = %entry
%1 = tail call arm_aapcs_vfpcc i32 @foo(i8* @a) nounwind %1 = tail call arm_aapcs_vfpcc i32 @foo(i8* @a) nounwind
ret i32 %1 ret i32 %1
; ELFOBJ: Sections [ ; ELFOBJ: Sections [
; ELFOBJ: Section { ; ELFOBJ: Section {
; ELFOBJ: Name: .text ; ELFOBJ: Name: .text
; ELFOBJ-LE: SectionData ( ; ELFOBJ-LE: SectionData (
;;; BL __aeabi_read_tp is ---+ ;;; BL __aeabi_read_tp is ---+
;;; V ;;; V
; ELFOBJ-LE-NEXT: 0000: 80B50E48 78440168 FFF7FEFF 40580D28 ; ELFOBJ-LE-NEXT: 0000: 80B50E48 78440168 FFF7FEFF 40580C28
; ELFOBJ-BE: SectionData ( ; ELFOBJ-BE: SectionData (
;;; BL __aeabi_read_tp is ---+ ;;; BL __aeabi_read_tp is ---+
;;; V ;;; V
; ELFOBJ-BE-NEXT: 0000: B580480E 44786801 F7FFFFFE 5840280D ; ELFOBJ-BE-NEXT: 0000: B580480E 44786801 F7FFFFFE 5840280C
bb1: ; preds = %entry bb1: ; preds = %entry
%2 = tail call arm_aapcs_vfpcc i32 @bar(i32* bitcast ([10 x i8]* @b to i32*)) nounwind %2 = tail call arm_aapcs_vfpcc i32 @bar(i32* bitcast ([10 x i8]* @b to i32*)) nounwind
ret i32 %2 ret i32 %2
bb2: ; preds = %entry bb2: ; preds = %entry
ret i32 -1 ret i32 -1
} }
declare arm_aapcs_vfpcc i32 @foo(i8*) declare arm_aapcs_vfpcc i32 @foo(i8*)
declare arm_aapcs_vfpcc i32 @bar(i32*) declare arm_aapcs_vfpcc i32 @bar(i32*)

llvm/test/CodeGen/Thumb2/v8_IT_4.ll

Show All 10 Lines
%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >::_Rep_base" = type { i32, i32, i32 } %"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >::_Rep_base" = type { i32, i32, i32 }
define weak arm_aapcs_vfpcc i32 @_ZNKSs7compareERKSs(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this, %"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) { define weak arm_aapcs_vfpcc i32 @_ZNKSs7compareERKSs(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this, %"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) {
; P01-LABEL: _ZNKSs7compareERKSs: ; P01-LABEL: _ZNKSs7compareERKSs:
; P01: @ %bb.0: @ %entry ; P01: @ %bb.0: @ %entry
; P01-NEXT: .save {r4, r5, r6, r7, r8, lr} ; P01-NEXT: .save {r4, r5, r6, r7, r8, lr}
; P01-NEXT: push.w {r4, r5, r6, r7, r8, lr} ; P01-NEXT: push.w {r4, r5, r6, r7, r8, lr}
; P01-NEXT: mov r6, r1 ; P01-NEXT: mov r8, r1
; P01-NEXT: mov r7, r0 ; P01-NEXT: mov r5, r0
; P01-NEXT: bl _ZNKSs4sizeEv ; P01-NEXT: bl _ZNKSs4sizeEv
; P01-NEXT: mov r8, r0 ; P01-NEXT: mov r4, r0
; P01-NEXT: mov r0, r6 ; P01-NEXT: mov r0, r8
; P01-NEXT: bl _ZNKSs4sizeEv ; P01-NEXT: bl _ZNKSs4sizeEv
; P01-NEXT: mov r4, r8 ; P01-NEXT: mov r6, r4
; P01-NEXT: cmp r0, r8 ; P01-NEXT: cmp r4, r0
; P01-NEXT: mov r5, r0
; P01-NEXT: it lo
; P01-NEXT: movlo r4, r0
; P01-NEXT: mov r0, r7
; P01-NEXT: bl _ZNKSs7_M_dataEv
; P01-NEXT: mov r7, r0 ; P01-NEXT: mov r7, r0
; P01-NEXT: mov r0, r6 ; P01-NEXT: it hi
; P01-NEXT: movhi r6, r0
; P01-NEXT: mov r0, r5
; P01-NEXT: bl _ZNKSs7_M_dataEv
; P01-NEXT: mov r5, r0
; P01-NEXT: mov r0, r8
; P01-NEXT: bl _ZNKSs4dataEv ; P01-NEXT: bl _ZNKSs4dataEv
; P01-NEXT: mov r1, r0 ; P01-NEXT: mov r1, r0
; P01-NEXT: mov r0, r7 ; P01-NEXT: mov r0, r5
; P01-NEXT: mov r2, r4 ; P01-NEXT: mov r2, r6
; P01-NEXT: bl memcmp ; P01-NEXT: bl memcmp
; P01-NEXT: cbz r0, .LBB0_2 ; P01-NEXT: subs r1, r4, r7
; P01-NEXT: @ %bb.1: @ %bb1 ; P01-NEXT: cmp r0, #0
; P01-NEXT: pop.w {r4, r5, r6, r7, r8, pc} ; P01-NEXT: it eq
; P01-NEXT: .LBB0_2: @ %bb ; P01-NEXT: moveq r0, r1
; P01-NEXT: sub.w r0, r8, r5
; P01-NEXT: pop.w {r4, r5, r6, r7, r8, pc} ; P01-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
; ;
; P23-LABEL: _ZNKSs7compareERKSs: ; P23-LABEL: _ZNKSs7compareERKSs:
; P23: @ %bb.0: @ %entry ; P23: @ %bb.0: @ %entry
; P23-NEXT: .save {r4, r5, r6, r7, r8, lr} ; P23-NEXT: .save {r4, r5, r6, r7, r8, lr}
; P23-NEXT: push.w {r4, r5, r6, r7, r8, lr} ; P23-NEXT: push.w {r4, r5, r6, r7, r8, lr}
; P23-NEXT: mov r7, r1 ; P23-NEXT: mov r8, r1
; P23-NEXT: mov r5, r0 ; P23-NEXT: mov r7, r0
; P23-NEXT: bl _ZNKSs4sizeEv ; P23-NEXT: bl _ZNKSs4sizeEv
; P23-NEXT: mov r8, r0
; P23-NEXT: mov r0, r7
; P23-NEXT: bl _ZNKSs4sizeEv
; P23-NEXT: mov r4, r8
; P23-NEXT: cmp r0, r8
; P23-NEXT: mov r6, r0 ; P23-NEXT: mov r6, r0
; P23-NEXT: it lo ; P23-NEXT: mov r0, r8
; P23-NEXT: movlo r4, r0 ; P23-NEXT: bl _ZNKSs4sizeEv
; P23-NEXT: mov r0, r5 ; P23-NEXT: mov r4, r6
; P23-NEXT: bl _ZNKSs7_M_dataEv ; P23-NEXT: cmp r6, r0
; P23-NEXT: mov r5, r0 ; P23-NEXT: mov r5, r0
; P23-NEXT: it hi
; P23-NEXT: movhi r4, r0
; P23-NEXT: mov r0, r7 ; P23-NEXT: mov r0, r7
; P23-NEXT: bl _ZNKSs7_M_dataEv
; P23-NEXT: mov r7, r0
; P23-NEXT: mov r0, r8
; P23-NEXT: bl _ZNKSs4dataEv ; P23-NEXT: bl _ZNKSs4dataEv
; P23-NEXT: mov r1, r0 ; P23-NEXT: mov r1, r0
; P23-NEXT: mov r0, r5 ; P23-NEXT: mov r0, r7
; P23-NEXT: mov r2, r4 ; P23-NEXT: mov r2, r4
; P23-NEXT: bl memcmp ; P23-NEXT: bl memcmp
; P23-NEXT: cbz r0, .LBB0_2 ; P23-NEXT: subs r1, r6, r5
; P23-NEXT: @ %bb.1: @ %bb1 ; P23-NEXT: cmp r0, #0
; P23-NEXT: pop.w {r4, r5, r6, r7, r8, pc} ; P23-NEXT: it eq
; P23-NEXT: .LBB0_2: @ %bb ; P23-NEXT: moveq r0, r1
; P23-NEXT: sub.w r0, r8, r6
; P23-NEXT: pop.w {r4, r5, r6, r7, r8, pc} ; P23-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
entry: entry:
%0 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this) ; <i32> [#uses=3] %0 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this) ; <i32> [#uses=3]
%1 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) ; <i32> [#uses=3] %1 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) ; <i32> [#uses=3]
%2 = icmp ult i32 %1, %0 ; <i1> [#uses=1] %2 = icmp ult i32 %1, %0 ; <i1> [#uses=1]
%3 = select i1 %2, i32 %1, i32 %0 ; <i32> [#uses=1] %3 = select i1 %2, i32 %1, i32 %0 ; <i32> [#uses=1]
%4 = tail call arm_aapcs_vfpcc i8* @_ZNKSs7_M_dataEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this) ; <i8*> [#uses=1] %4 = tail call arm_aapcs_vfpcc i8* @_ZNKSs7_M_dataEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this) ; <i8*> [#uses=1]
%5 = tail call arm_aapcs_vfpcc i8* @_ZNKSs4dataEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) ; <i8*> [#uses=1] %5 = tail call arm_aapcs_vfpcc i8* @_ZNKSs4dataEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) ; <i8*> [#uses=1]
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llvm/test/Transforms/LoopUnroll/ARM/upperbound.ll

Show First 20 Lines • Show All 69 Lines • ▼ Show 20 Lines
; Larger test that is still fully unrolled, thanks in part to the constant data and the max upper bound. ; Larger test that is still fully unrolled, thanks in part to the constant data and the max upper bound.
@data = internal constant [50 x i32] [i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50], align 4 @data = internal constant [50 x i32] [i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50], align 4
define i32 @test2(i32 %l86) { define i32 @test2(i32 %l86) {
; CHECK-LABEL: @test2( ; CHECK-LABEL: @test2(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[L86_OFF:%.*]] = add i32 [[L86:%.*]], -1 ; CHECK-NEXT: [[L86_OFF:%.*]] = add i32 [[L86:%.*]], -1
; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i32 [[L86_OFF]], 24 ; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i32 [[L86_OFF]], 24
; CHECK-NEXT: br i1 [[SWITCH]], label [[COMMON_RET:%.*]], label [[FOR_INC_I_3_I_5:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: ret i32 0
; CHECK: for.inc.i.3.i.5:
; CHECK-NEXT: [[DOTNOT30:%.*]] = icmp ne i32 [[L86]], 25 ; CHECK-NEXT: [[DOTNOT30:%.*]] = icmp ne i32 [[L86]], 25
; CHECK-NEXT: [[SPEC_SELECT24:%.*]] = zext i1 [[DOTNOT30]] to i32 ; CHECK-NEXT: [[SPEC_SELECT24:%.*]] = zext i1 [[DOTNOT30]] to i32
; CHECK-NEXT: ret i32 [[SPEC_SELECT24]] ; CHECK-NEXT: [[COMMON_RET31_OP:%.*]] = select i1 [[SWITCH]], i32 0, i32 [[SPEC_SELECT24]]
; CHECK-NEXT: ret i32 [[COMMON_RET31_OP]]
; ;
entry: entry:
br label %for.body.i.i br label %for.body.i.i
for.body.i.i: ; preds = %for.body.i.i.preheader, %for.inc.i.3.i for.body.i.i: ; preds = %for.body.i.i.preheader, %for.inc.i.3.i
%i.0137.i.i = phi i32 [ %add.i.3.i, %for.inc.i.3.i ], [ 0, %entry ] %i.0137.i.i = phi i32 [ %add.i.3.i, %for.inc.i.3.i ], [ 0, %entry ]
%add.i.i = or i32 %i.0137.i.i, 1 %add.i.i = or i32 %i.0137.i.i, 1
%arrayidx.i.i = getelementptr inbounds i32, i32* getelementptr inbounds ([50 x i32], [50 x i32]* @data, i32 0, i32 0), i32 %add.i.i %arrayidx.i.i = getelementptr inbounds i32, i32* getelementptr inbounds ([50 x i32], [50 x i32]* @data, i32 0, i32 0), i32 %add.i.i
▲ Show 20 Lines • Show All 71 Lines • Show Last 20 Lines

llvm/test/Transforms/PGOProfile/chr.ll

Show First 20 Lines • Show All 384 Lines • ▼ Show 20 Lines
; } ; }
define i32 @test_chr_4(i32* %i, i32 %sum0) !prof !14 { define i32 @test_chr_4(i32* %i, i32 %sum0) !prof !14 {
; CHECK-LABEL: @test_chr_4( ; CHECK-LABEL: @test_chr_4(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[I:%.*]], align 4 ; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[I:%.*]], align 4
; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[TMP0]], 3 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[TMP0]], 3
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 3 ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 3
; CHECK-NEXT: br i1 [[TMP2]], label [[ENTRY_SPLIT:%.*]], label [[ENTRY_SPLIT_NONCHR:%.*]], !prof [[PROF15]] ; CHECK-NEXT: br i1 [[TMP2]], label [[ENTRY_SPLIT:%.*]], label [[ENTRY_SPLIT_NONCHR:%.*]], !prof [[PROF15]]
; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ [[TMP3:%.*]], [[ENTRY_SPLIT]] ], [ [[SUM2_NONCHR:%.*]], [[ENTRY_SPLIT_NONCHR]] ]
; CHECK-NEXT: ret i32 [[COMMON_RET_OP]]
; CHECK: entry.split: ; CHECK: entry.split:
; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[SUM0:%.*]], 85 ; CHECK-NEXT: [[TMP3]] = add i32 [[SUM0:%.*]], 85
; CHECK-NEXT: ret i32 [[TMP3]] ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: entry.split.nonchr: ; CHECK: entry.split.nonchr:
; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[SUM0]], 42 ; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[SUM0]], 42
; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP0]], 1 ; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP0]], 1
; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP5]], 0 ; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[TMP5]], 0
; CHECK-NEXT: [[SUM1_NONCHR:%.*]] = select i1 [[DOTNOT]], i32 [[SUM0]], i32 [[TMP4]], !prof [[PROF16]] ; CHECK-NEXT: [[SUM1_NONCHR:%.*]] = select i1 [[DOTNOT]], i32 [[SUM0]], i32 [[TMP4]], !prof [[PROF16]]
; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[TMP0]], 2 ; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[TMP0]], 2
; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0 ; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[SUM1_NONCHR]], 43 ; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[SUM1_NONCHR]], 43
; CHECK-NEXT: [[SUM2_NONCHR:%.*]] = select i1 [[TMP7]], i32 [[SUM1_NONCHR]], i32 [[TMP8]], !prof [[PROF16]] ; CHECK-NEXT: [[SUM2_NONCHR]] = select i1 [[TMP7]], i32 [[SUM1_NONCHR]], i32 [[TMP8]], !prof [[PROF16]]
; CHECK-NEXT: ret i32 [[SUM2_NONCHR]] ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
%0 = load i32, i32* %i %0 = load i32, i32* %i
%1 = and i32 %0, 1 %1 = and i32 %0, 1
%2 = icmp eq i32 %1, 0 %2 = icmp eq i32 %1, 0
%3 = add i32 %sum0, 42 %3 = add i32 %sum0, 42
%sum1 = select i1 %2, i32 %sum0, i32 %3, !prof !15 %sum1 = select i1 %2, i32 %sum0, i32 %3, !prof !15
%4 = and i32 %0, 2 %4 = and i32 %0, 2
▲ Show 20 Lines • Show All 1,590 Lines • ▼ Show 20 Lines
; really slow and doesn't appear to be hanging. ; really slow and doesn't appear to be hanging.
define i64 @test_chr_22(i1 %i, i64* %j, i64 %v0) !prof !14 { define i64 @test_chr_22(i1 %i, i64* %j, i64 %v0) !prof !14 {
; CHECK-LABEL: @test_chr_22( ; CHECK-LABEL: @test_chr_22(
; CHECK-NEXT: bb0: ; CHECK-NEXT: bb0:
; CHECK-NEXT: [[REASS_ADD:%.*]] = shl i64 [[V0:%.*]], 1 ; CHECK-NEXT: [[REASS_ADD:%.*]] = shl i64 [[V0:%.*]], 1
; CHECK-NEXT: [[V2:%.*]] = add i64 [[REASS_ADD]], 3 ; CHECK-NEXT: [[V2:%.*]] = add i64 [[REASS_ADD]], 3
; CHECK-NEXT: [[C1:%.*]] = icmp slt i64 [[V2]], 100 ; CHECK-NEXT: [[C1:%.*]] = icmp slt i64 [[V2]], 100
; CHECK-NEXT: br i1 [[C1]], label [[BB0_SPLIT:%.*]], label [[BB0_SPLIT_NONCHR:%.*]], !prof [[PROF15]] ; CHECK-NEXT: br i1 [[C1]], label [[BB0_SPLIT:%.*]], label [[BB0_SPLIT_NONCHR:%.*]], !prof [[PROF15]]
; CHECK: common.ret:
; CHECK-NEXT: ret i64 99
; CHECK: bb0.split: ; CHECK: bb0.split:
; CHECK-NEXT: [[V299:%.*]] = mul i64 [[V2]], 7860086430977039991 ; CHECK-NEXT: [[V299:%.*]] = mul i64 [[V2]], 7860086430977039991
; CHECK-NEXT: store i64 [[V299]], i64* [[J:%.*]], align 4 ; CHECK-NEXT: store i64 [[V299]], i64* [[J:%.*]], align 4
; CHECK-NEXT: ret i64 99 ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: bb0.split.nonchr: ; CHECK: bb0.split.nonchr:
; CHECK-NEXT: [[V299_NONCHR:%.*]] = mul i64 [[V2]], 7860086430977039991 ; CHECK-NEXT: [[V299_NONCHR:%.*]] = mul i64 [[V2]], 7860086430977039991
; CHECK-NEXT: store i64 [[V299_NONCHR]], i64* [[J]], align 4 ; CHECK-NEXT: store i64 [[V299_NONCHR]], i64* [[J]], align 4
; CHECK-NEXT: ret i64 99 ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
bb0: bb0:
%v1 = add i64 %v0, 3 %v1 = add i64 %v0, 3
%v2 = add i64 %v1, %v0 %v2 = add i64 %v1, %v0
%c1 = icmp sgt i64 %v2, 99 %c1 = icmp sgt i64 %v2, 99
%v3 = select i1 %c1, i64 %v1, i64 %v2, !prof !15 %v3 = select i1 %c1, i64 %v1, i64 %v2, !prof !15
%v4 = add i64 %v2, %v2 %v4 = add i64 %v2, %v2
%v5 = add i64 %v4, %v2 %v5 = add i64 %v4, %v2
▲ Show 20 Lines • Show All 642 Lines • Show Last 20 Lines

llvm/test/Transforms/PhaseOrdering/X86/simplifycfg-late.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes='lto<O2>' -S | FileCheck %s ; RUN: opt < %s -passes='lto<O2>' -S | FileCheck %s
target datalayout = "i32:32:32-i64:64:64" target datalayout = "i32:32:32-i64:64:64"
target triple = "x86_64--" target triple = "x86_64--"
; Verify that the "late" simplifycfg options are set. This should get converted into a lookup table. ; Verify that the "late" simplifycfg options are set. This should get converted into a lookup table.
define i32 @f(i32 %c) { define i32 @f(i32 %c) {
; CHECK-LABEL: @f( ; CHECK-LABEL: @f(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = add i32 [[C:%.*]], -42 ; CHECK-NEXT: [[SWITCH_TABLEIDX:%.*]] = add i32 [[C:%.*]], -42
; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 7 ; CHECK-NEXT: [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 7
; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]] ; CHECK-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[COMMON_RET:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ [[SWITCH_LOAD:%.*]], [[SWITCH_LOOKUP]] ], [ 15, [[ENTRY:%.*]] ]
; CHECK-NEXT: ret i32 [[COMMON_RET_OP]]
; CHECK: switch.lookup: ; CHECK: switch.lookup:
; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[SWITCH_TABLEIDX]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[SWITCH_TABLEIDX]] to i64
; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [7 x i32], [7 x i32]* @switch.table.f, i64 0, i64 [[TMP1]] ; CHECK-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [7 x i32], [7 x i32]* @switch.table.f, i64 0, i64 [[TMP1]]
; CHECK-NEXT: [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]], align 4 ; CHECK-NEXT: [[SWITCH_LOAD]] = load i32, i32* [[SWITCH_GEP]], align 4
; CHECK-NEXT: ret i32 [[SWITCH_LOAD]] ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: return:
; CHECK-NEXT: ret i32 15
; ;
entry: entry:
switch i32 %c, label %sw.default [ switch i32 %c, label %sw.default [
i32 42, label %return i32 42, label %return
i32 43, label %sw.bb1 i32 43, label %sw.bb1
i32 44, label %sw.bb2 i32 44, label %sw.bb2
i32 45, label %sw.bb3 i32 45, label %sw.bb3
i32 46, label %sw.bb4 i32 46, label %sw.bb4
Show All 22 Lines

llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll

Show First 20 Lines • Show All 286 Lines • ▼ Show 20 Lines
; CHECK-NEXT: [[ADD:%.*]] = fsub double [[C:%.*]], [[B]] ; CHECK-NEXT: [[ADD:%.*]] = fsub double [[C:%.*]], [[B]]
; CHECK-NEXT: [[MUL:%.*]] = fmul double [[A:%.*]], 2.000000e+00 ; CHECK-NEXT: [[MUL:%.*]] = fmul double [[A:%.*]], 2.000000e+00
; CHECK-NEXT: [[DIV:%.*]] = fdiv double [[ADD]], [[MUL]] ; CHECK-NEXT: [[DIV:%.*]] = fdiv double [[ADD]], [[MUL]]
; CHECK-NEXT: [[SUB:%.*]] = fsub double [[FNEG]], [[C]] ; CHECK-NEXT: [[SUB:%.*]] = fsub double [[FNEG]], [[C]]
; CHECK-NEXT: [[DIV3:%.*]] = fdiv double [[SUB]], [[MUL]] ; CHECK-NEXT: [[DIV3:%.*]] = fdiv double [[SUB]], [[MUL]]
; CHECK-NEXT: [[CMP:%.*]] = fcmp olt double [[DIV]], 0x3EB0C6F7A0B5ED8D ; CHECK-NEXT: [[CMP:%.*]] = fcmp olt double [[DIV]], 0x3EB0C6F7A0B5ED8D
; CHECK-NEXT: [[CMP4:%.*]] = fcmp olt double [[DIV3]], 0x3EB0C6F7A0B5ED8D ; CHECK-NEXT: [[CMP4:%.*]] = fcmp olt double [[DIV3]], 0x3EB0C6F7A0B5ED8D
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[CMP]], i1 [[CMP4]], i1 false ; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[CMP]], i1 [[CMP4]], i1 false
; CHECK-NEXT: br i1 [[OR_COND]], label [[CLEANUP:%.*]], label [[LOR_LHS_FALSE:%.*]] ; CHECK-NEXT: br i1 [[OR_COND]], label [[COMMON_RET:%.*]], label [[LOR_LHS_FALSE:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i1 [ [[OR_COND1:%.*]], [[LOR_LHS_FALSE]] ], [ false, [[ENTRY:%.*]] ]
; CHECK-NEXT: ret i1 [[COMMON_RET_OP]]
; CHECK: lor.lhs.false: ; CHECK: lor.lhs.false:
; CHECK-NEXT: [[CMP5:%.*]] = fcmp ule double [[DIV]], 1.000000e+00 ; CHECK-NEXT: [[CMP5:%.*]] = fcmp ule double [[DIV]], 1.000000e+00
; CHECK-NEXT: [[CMP7:%.*]] = fcmp ule double [[DIV3]], 1.000000e+00 ; CHECK-NEXT: [[CMP7:%.*]] = fcmp ule double [[DIV3]], 1.000000e+00
; CHECK-NEXT: [[OR_COND1:%.*]] = select i1 [[CMP5]], i1 true, i1 [[CMP7]] ; CHECK-NEXT: [[OR_COND1]] = select i1 [[CMP5]], i1 true, i1 [[CMP7]]
; CHECK-NEXT: ret i1 [[OR_COND1]] ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: cleanup:
; CHECK-NEXT: ret i1 false
; ;
entry: entry:
%fneg = fneg double %b %fneg = fneg double %b
%add = fadd double %fneg, %c %add = fadd double %fneg, %c
%mul = fmul double 2.0, %a %mul = fmul double 2.0, %a
%div = fdiv double %add, %mul %div = fdiv double %add, %mul
%fneg1 = fneg double %b %fneg1 = fneg double %b
%sub = fsub double %fneg1, %c %sub = fsub double %fneg1, %c
Show All 27 Lines

llvm/test/Transforms/PhaseOrdering/inlining-alignment-assumptions.ll

Show All 10 Lines
define internal i1 @callee1(i1 %c, i64* align 8 %ptr) { define internal i1 @callee1(i1 %c, i64* align 8 %ptr) {
store volatile i64 0, i64* %ptr store volatile i64 0, i64* %ptr
ret i1 %c ret i1 %c
} }
define void @caller1(i1 %c, i64* align 1 %ptr) { define void @caller1(i1 %c, i64* align 1 %ptr) {
; ASSUMPTIONS-OFF-LABEL: @caller1( ; ASSUMPTIONS-OFF-LABEL: @caller1(
; ASSUMPTIONS-OFF-NEXT: br i1 [[C:%.*]], label [[TRUE2:%.*]], label [[FALSE2:%.*]] ; ASSUMPTIONS-OFF-NEXT: br i1 [[C:%.*]], label [[COMMON_RET:%.*]], label [[FALSE2:%.*]]
; ASSUMPTIONS-OFF: true2: ; ASSUMPTIONS-OFF: common.ret:
; ASSUMPTIONS-OFF-NEXT: [[DOTSINK:%.*]] = phi i64 [ 3, [[FALSE2]] ], [ 2, [[TMP0:%.*]] ]
; ASSUMPTIONS-OFF-NEXT: store volatile i64 0, i64* [[PTR:%.*]], align 8 ; ASSUMPTIONS-OFF-NEXT: store volatile i64 0, i64* [[PTR:%.*]], align 8
; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4 ; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4 ; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4 ; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4 ; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4 ; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
; ASSUMPTIONS-OFF-NEXT: store volatile i64 2, i64* [[PTR]], align 4 ; ASSUMPTIONS-OFF-NEXT: store volatile i64 [[DOTSINK]], i64* [[PTR]], align 4
; ASSUMPTIONS-OFF-NEXT: ret void ; ASSUMPTIONS-OFF-NEXT: ret void
; ASSUMPTIONS-OFF: false2: ; ASSUMPTIONS-OFF: false2:
; ASSUMPTIONS-OFF-NEXT: store volatile i64 1, i64* [[PTR]], align 4 ; ASSUMPTIONS-OFF-NEXT: store volatile i64 1, i64* [[PTR]], align 4
; ASSUMPTIONS-OFF-NEXT: store volatile i64 0, i64* [[PTR]], align 8 ; ASSUMPTIONS-OFF-NEXT: br label [[COMMON_RET]]
; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
; ASSUMPTIONS-OFF-NEXT: store volatile i64 3, i64* [[PTR]], align 4
; ASSUMPTIONS-OFF-NEXT: ret void
; ;
; ASSUMPTIONS-ON-LABEL: @caller1( ; ASSUMPTIONS-ON-LABEL: @caller1(
; ASSUMPTIONS-ON-NEXT: br i1 [[C:%.*]], label [[TRUE2_CRITEDGE:%.*]], label [[FALSE1:%.*]] ; ASSUMPTIONS-ON-NEXT: br i1 [[C:%.*]], label [[COMMON_RET:%.*]], label [[FALSE1:%.*]]
; ASSUMPTIONS-ON: false1: ; ASSUMPTIONS-ON: false1:
; ASSUMPTIONS-ON-NEXT: store volatile i64 1, i64* [[PTR:%.*]], align 8 ; ASSUMPTIONS-ON-NEXT: store volatile i64 1, i64* [[PTR:%.*]], align 8
; ASSUMPTIONS-ON-NEXT: br label [[COMMON_RET]]
; ASSUMPTIONS-ON: common.ret:
; ASSUMPTIONS-ON-NEXT: [[DOTSINK:%.*]] = phi i64 [ 3, [[FALSE1]] ], [ 2, [[TMP0:%.*]] ]
; ASSUMPTIONS-ON-NEXT: call void @llvm.assume(i1 true) [ "align"(i64* [[PTR]], i64 8) ] ; ASSUMPTIONS-ON-NEXT: call void @llvm.assume(i1 true) [ "align"(i64* [[PTR]], i64 8) ]
; ASSUMPTIONS-ON-NEXT: store volatile i64 0, i64* [[PTR]], align 8 ; ASSUMPTIONS-ON-NEXT: store volatile i64 0, i64* [[PTR]], align 8
; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8 ; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8 ; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8 ; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8 ; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8 ; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; ASSUMPTIONS-ON-NEXT: store volatile i64 3, i64* [[PTR]], align 8 ; ASSUMPTIONS-ON-NEXT: store volatile i64 [[DOTSINK]], i64* [[PTR]], align 8
; ASSUMPTIONS-ON-NEXT: ret void
; ASSUMPTIONS-ON: true2.critedge:
; ASSUMPTIONS-ON-NEXT: call void @llvm.assume(i1 true) [ "align"(i64* [[PTR]], i64 8) ]
; ASSUMPTIONS-ON-NEXT: store volatile i64 0, i64* [[PTR]], align 8
; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; ASSUMPTIONS-ON-NEXT: store volatile i64 2, i64* [[PTR]], align 8
; ASSUMPTIONS-ON-NEXT: ret void ; ASSUMPTIONS-ON-NEXT: ret void
; ;
br i1 %c, label %true1, label %false1 br i1 %c, label %true1, label %false1
true1: true1:
%c2 = call i1 @callee1(i1 %c, i64* %ptr) %c2 = call i1 @callee1(i1 %c, i64* %ptr)
store volatile i64 -1, i64* %ptr store volatile i64 -1, i64* %ptr
store volatile i64 -1, i64* %ptr store volatile i64 -1, i64* %ptr
Show All 35 Lines

llvm/test/Transforms/PruneEH/ipo-nounwind.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -prune-eh -enable-new-pm=0 < %s | FileCheck %s ; RUN: opt -S -prune-eh -enable-new-pm=0 < %s | FileCheck --check-prefixes=ALL,OLDPM %s
; RUN: opt -S -passes='function-attrs,function(simplify-cfg)' < %s | FileCheck %s ; RUN: opt -S -passes='function-attrs,function(simplify-cfg)' < %s | FileCheck --check-prefixes=ALL,NEWPM %s
declare void @may_throw() declare void @may_throw()
; @callee below may be an optimized form of this function, which can ; @callee below may be an optimized form of this function, which can
; throw at runtime (see r265762 for more details): ; throw at runtime (see r265762 for more details):
; ;
; define linkonce_odr void @callee(i32* %ptr) noinline { ; define linkonce_odr void @callee(i32* %ptr) noinline {
; entry: ; entry:
; %val0 = load atomic i32, i32* %ptr unordered, align 4 ; %val0 = load atomic i32, i32* %ptr unordered, align 4
; %val1 = load atomic i32, i32* %ptr unordered, align 4 ; %val1 = load atomic i32, i32* %ptr unordered, align 4
; %cmp = icmp eq i32 %val0, %val1 ; %cmp = icmp eq i32 %val0, %val1
; br i1 %cmp, label %left, label %right ; br i1 %cmp, label %left, label %right
; left: ; left:
; ret void ; ret void
; right: ; right:
; call void @may_throw() ; call void @may_throw()
; ret void ; ret void
; } ; }
define linkonce_odr void @callee(i32* %ptr) noinline { define linkonce_odr void @callee(i32* %ptr) noinline {
; CHECK-LABEL: @callee( ; ALL-LABEL: @callee(
; CHECK-NEXT: ret void ; ALL-NEXT: ret void
; ;
ret void ret void
} }
define i32 @caller(i32* %ptr) personality i32 3 { define i32 @caller(i32* %ptr) personality i32 3 {
; CHECK-LABEL: @caller( ; OLDPM-LABEL: @caller(
rnkUnsubmitted
Not Done
ReplyInline Actions

Seems like another update bug.

rnk: Seems like another update bug.
; CHECK-NEXT: entry: ; OLDPM-NEXT: entry:
; CHECK-NEXT: invoke void @callee(i32* [[PTR:%.*]]) ; OLDPM-NEXT: invoke void @callee(i32* [[PTR:%.*]])
; CHECK-NEXT: to label [[NORMAL:%.*]] unwind label [[UNWIND:%.*]] ; OLDPM-NEXT: to label [[NORMAL:%.*]] unwind label [[UNWIND:%.*]]
; CHECK: normal: ; OLDPM: normal:
; CHECK-NEXT: ret i32 1 ; OLDPM-NEXT: ret i32 1
; CHECK: unwind: ; OLDPM: unwind:
; CHECK-NEXT: [[RES:%.*]] = landingpad { i8*, i32 } ; OLDPM-NEXT: [[RES:%.*]] = landingpad { i8*, i32 }
; CHECK-NEXT: cleanup ; OLDPM-NEXT: cleanup
; CHECK-NEXT: ret i32 2 ; OLDPM-NEXT: ret i32 2
;
; NEWPM-LABEL: @caller(
; NEWPM-NEXT: entry:
; NEWPM-NEXT: invoke void @callee(i32* [[PTR:%.*]])
; NEWPM-NEXT: to label [[COMMON_RET:%.*]] unwind label [[UNWIND:%.*]]
; NEWPM: common.ret:
; NEWPM-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ 2, [[UNWIND]] ], [ 1, [[ENTRY:%.*]] ]
; NEWPM-NEXT: ret i32 [[COMMON_RET_OP]]
; NEWPM: unwind:
; NEWPM-NEXT: [[RES:%.*]] = landingpad { i8*, i32 }
; NEWPM-NEXT: cleanup
; NEWPM-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
invoke void @callee(i32* %ptr) invoke void @callee(i32* %ptr)
to label %normal unwind label %unwind to label %normal unwind label %unwind
normal: normal:
ret i32 1 ret i32 1
unwind: unwind:
%res = landingpad { i8*, i32 } %res = landingpad { i8*, i32 }
cleanup cleanup
ret i32 2 ret i32 2
} }

llvm/test/Transforms/SimplifyCFG/DeadSetCC.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s ; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s
; Check that simplifycfg deletes a dead 'seteq' instruction when it ; Check that simplifycfg deletes a dead 'seteq' instruction when it
; folds a conditional branch into a switch instruction. ; folds a conditional branch into a switch instruction.
declare void @foo() declare void @foo()
declare void @bar() declare void @bar()
define void @testcfg(i32 %V) { define void @testcfg(i32 %V) {
; CHECK-LABEL: @testcfg( ; CHECK-LABEL: @testcfg(
; CHECK-NEXT: [[V_OFF:%.*]] = add i32 [[V:%.*]], -15 ; CHECK-NEXT: [[V_OFF:%.*]] = add i32 [[V:%.*]], -15
; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i32 [[V_OFF]], 2 ; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i32 [[V_OFF]], 2
; CHECK-NEXT: br i1 [[SWITCH]], label [[L2:%.*]], label [[L1:%.*]] ; CHECK-NEXT: br i1 [[SWITCH]], label [[L2:%.*]], label [[L1:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: L1: ; CHECK: L1:
; CHECK-NEXT: call void @foo() ; CHECK-NEXT: call void @foo()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: L2: ; CHECK: L2:
; CHECK-NEXT: call void @bar() ; CHECK-NEXT: call void @bar()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
%C = icmp eq i32 %V, 18 %C = icmp eq i32 %V, 18
%D = icmp eq i32 %V, 180 %D = icmp eq i32 %V, 180
%E = or i1 %C, %D %E = or i1 %C, %D
br i1 %E, label %L1, label %Sw br i1 %E, label %L1, label %Sw
Sw: ; preds = %0 Sw: ; preds = %0
switch i32 %V, label %L1 [ switch i32 %V, label %L1 [
i32 15, label %L2 i32 15, label %L2
Show All 10 Lines

llvm/test/Transforms/SimplifyCFG/FoldValueComparisonIntoPredecessors-domtree-preservation-edgecase-2.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s ; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s
declare void @widget() declare void @widget()
declare i16 @baz() declare i16 @baz()
declare void @snork() declare void @snork()
declare void @spam() declare void @spam()
define void @zot() local_unnamed_addr align 2 personality i8* undef { define void @zot() local_unnamed_addr align 2 personality i8* undef {
; CHECK-LABEL: @zot( ; CHECK-LABEL: @zot(
; CHECK-NEXT: bb: ; CHECK-NEXT: bb:
; CHECK-NEXT: invoke void @widget() ; CHECK-NEXT: invoke void @widget()
; CHECK-NEXT: to label [[BB14:%.*]] unwind label [[BB21:%.*]] ; CHECK-NEXT: to label [[BB14:%.*]] unwind label [[BB21:%.*]]
; CHECK: bb14: ; CHECK: bb14:
; CHECK-NEXT: [[I0:%.*]] = invoke i16 @baz() ; CHECK-NEXT: [[I0:%.*]] = invoke i16 @baz()
; CHECK-NEXT: to label [[BB15:%.*]] unwind label [[BB25:%.*]] ; CHECK-NEXT: to label [[BB15:%.*]] unwind label [[BB21]]
; CHECK: bb15: ; CHECK: bb15:
; CHECK-NEXT: switch i16 [[I0]], label [[BB19:%.*]] [ ; CHECK-NEXT: switch i16 [[I0]], label [[BB19:%.*]] [
; CHECK-NEXT: i16 42, label [[BB23:%.*]] ; CHECK-NEXT: i16 42, label [[BB23:%.*]]
; CHECK-NEXT: i16 21330, label [[BB23]] ; CHECK-NEXT: i16 21330, label [[BB23]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: bb19: ; CHECK: bb19:
; CHECK-NEXT: invoke void @snork() ; CHECK-NEXT: invoke void @snork()
; CHECK-NEXT: to label [[BB20:%.*]] unwind label [[BB25]] ; CHECK-NEXT: to label [[BB20:%.*]] unwind label [[BB21]]
; CHECK: bb20: ; CHECK: bb20:
; CHECK-NEXT: unreachable ; CHECK-NEXT: unreachable
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: bb21: ; CHECK: bb21:
; CHECK-NEXT: [[I22:%.*]] = landingpad { i8*, i32 } ; CHECK-NEXT: [[I22:%.*]] = landingpad { i8*, i32 }
; CHECK-NEXT: cleanup ; CHECK-NEXT: cleanup
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: bb23: ; CHECK: bb23:
; CHECK-NEXT: invoke void @spam() ; CHECK-NEXT: invoke void @spam()
; CHECK-NEXT: to label [[BB24:%.*]] unwind label [[BB25]] ; CHECK-NEXT: to label [[COMMON_RET]] unwind label [[BB21]]
; CHECK: bb24:
; CHECK-NEXT: ret void
; CHECK: bb25:
; CHECK-NEXT: [[I26:%.*]] = landingpad { i8*, i32 }
; CHECK-NEXT: cleanup
; CHECK-NEXT: br label [[BB24]]
; ;
bb: bb:
invoke void @widget() invoke void @widget()
to label %bb14 unwind label %bb21 to label %bb14 unwind label %bb21
bb14: ; preds = %bb bb14: ; preds = %bb
%i0 = invoke i16 @baz() %i0 = invoke i16 @baz()
to label %bb15 unwind label %bb25 to label %bb15 unwind label %bb25
Show All 33 Lines

llvm/test/Transforms/SimplifyCFG/Hexagon/switch-to-lookup-table.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -O2 < %s | FileCheck %s -check-prefix=ENABLE ; RUN: opt -S -O2 < %s | FileCheck %s -check-prefix=ENABLE
; RUN: opt -S -hexagon-emit-lookup-tables=true -O2 < %s | FileCheck %s -check-prefix=ENABLE ; RUN: opt -S -hexagon-emit-lookup-tables=true -O2 < %s | FileCheck %s -check-prefix=ENABLE
; RUN: opt -S -hexagon-emit-lookup-tables=false -O2 < %s | FileCheck %s -check-prefix=DISABLE ; RUN: opt -S -hexagon-emit-lookup-tables=false -O2 < %s | FileCheck %s -check-prefix=DISABLE
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon-unknown--elf" target triple = "hexagon-unknown--elf"
; Function Attrs: noinline nounwind ; Function Attrs: noinline nounwind
define i32 @foo(i32 %x) #0 section ".tcm_text" { define i32 @foo(i32 %x) #0 section ".tcm_text" {
; ENABLE-LABEL: @foo( ; ENABLE-LABEL: @foo(
; ENABLE-NEXT: entry: ; ENABLE-NEXT: entry:
; ENABLE-NEXT: [[TMP0:%.*]] = icmp ult i32 [[X:%.*]], 6 ; ENABLE-NEXT: [[TMP0:%.*]] = icmp ult i32 [[X:%.*]], 6
; ENABLE-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]] ; ENABLE-NEXT: br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[COMMON_RET:%.*]]
; ENABLE: common.ret:
; ENABLE-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ [[SWITCH_LOAD:%.*]], [[SWITCH_LOOKUP]] ], [ 19, [[ENTRY:%.*]] ]
; ENABLE-NEXT: ret i32 [[COMMON_RET_OP]]
; ENABLE: switch.lookup: ; ENABLE: switch.lookup:
; ENABLE-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [6 x i32], [6 x i32]* @switch.table.foo, i32 0, i32 [[X]] ; ENABLE-NEXT: [[SWITCH_GEP:%.*]] = getelementptr inbounds [6 x i32], [6 x i32]* @switch.table.foo, i32 0, i32 [[X]]
; ENABLE-NEXT: [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]], align 4 ; ENABLE-NEXT: [[SWITCH_LOAD]] = load i32, i32* [[SWITCH_GEP]], align 4
; ENABLE-NEXT: ret i32 [[SWITCH_LOAD]] ; ENABLE-NEXT: br label [[COMMON_RET]]
; ENABLE: return:
; ENABLE-NEXT: ret i32 19
; ;
; DISABLE-LABEL: @foo( ; DISABLE-LABEL: @foo(
; DISABLE-NEXT: entry: ; DISABLE-NEXT: entry:
; DISABLE-NEXT: switch i32 [[X:%.*]], label [[SW_DEFAULT:%.*]] [ ; DISABLE-NEXT: switch i32 [[X:%.*]], label [[SW_DEFAULT:%.*]] [
; DISABLE-NEXT: i32 0, label [[RETURN:%.*]] ; DISABLE-NEXT: i32 0, label [[RETURN:%.*]]
; DISABLE-NEXT: i32 1, label [[SW_BB1:%.*]] ; DISABLE-NEXT: i32 1, label [[SW_BB1:%.*]]
; DISABLE-NEXT: i32 2, label [[SW_BB2:%.*]] ; DISABLE-NEXT: i32 2, label [[SW_BB2:%.*]]
; DISABLE-NEXT: i32 3, label [[SW_BB3:%.*]] ; DISABLE-NEXT: i32 3, label [[SW_BB3:%.*]]
▲ Show 20 Lines • Show All 67 Lines • Show Last 20 Lines

llvm/test/Transforms/SimplifyCFG/HoistCode.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=simplifycfg -hoist-common-insts=true -S | FileCheck %s ; RUN: opt < %s -passes=simplifycfg -hoist-common-insts=true -S | FileCheck %s
; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -hoist-common-insts=true -S | FileCheck %s ; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -hoist-common-insts=true -S | FileCheck %s
define void @foo(i1 %C, i32* %P) { define void @foo(i1 %C, i32* %P) {
; CHECK-LABEL: @foo( ; CHECK-LABEL: @foo(
; CHECK-NEXT: common.ret:
; CHECK-NEXT: store i32 7, i32* [[P:%.*]], align 4 ; CHECK-NEXT: store i32 7, i32* [[P:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
br i1 %C, label %T, label %F br i1 %C, label %T, label %F
T: ; preds = %0 T: ; preds = %0
store i32 7, i32* %P store i32 7, i32* %P
ret void ret void
F: ; preds = %0 F: ; preds = %0
Show All 25 Lines

llvm/test/Transforms/SimplifyCFG/basictest.ll

Show All 28 Lines
} }
; Folding branch to a common destination. ; Folding branch to a common destination.
define void @test4_fold(i32 %a, i32 %b) { define void @test4_fold(i32 %a, i32 %b) {
; CHECK-LABEL: @test4_fold( ; CHECK-LABEL: @test4_fold(
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]] ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]]
; CHECK-NEXT: [[CMP2:%.*]] = icmp ugt i32 [[A]], 0 ; CHECK-NEXT: [[CMP2:%.*]] = icmp ugt i32 [[A]], 0
; CHECK-NEXT: [[OR_COND:%.*]] = and i1 [[CMP1]], [[CMP2]] ; CHECK-NEXT: [[OR_COND:%.*]] = and i1 [[CMP1]], [[CMP2]]
; CHECK-NEXT: br i1 [[OR_COND]], label [[ELSE:%.*]], label [[UNTAKEN:%.*]] ; CHECK-NEXT: br i1 [[OR_COND]], label [[ELSE:%.*]], label [[COMMON_RET:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: else: ; CHECK: else:
; CHECK-NEXT: call void @foo() ; CHECK-NEXT: call void @foo()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: untaken:
; CHECK-NEXT: ret void
; ;
%cmp1 = icmp eq i32 %a, %b %cmp1 = icmp eq i32 %a, %b
br i1 %cmp1, label %taken, label %untaken br i1 %cmp1, label %taken, label %untaken
taken: taken:
%cmp2 = icmp ugt i32 %a, 0 %cmp2 = icmp ugt i32 %a, 0
br i1 %cmp2, label %else, label %untaken br i1 %cmp2, label %else, label %untaken
▲ Show 20 Lines • Show All 98 Lines • Show Last 20 Lines

llvm/test/Transforms/SimplifyCFG/branch-fold.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s ; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s
define void @test(i32* %P, i32* %Q, i1 %A, i1 %B) { define void @test(i32* %P, i32* %Q, i1 %A, i1 %B) {
; CHECK-LABEL: @test( ; CHECK-LABEL: @test(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_NOT:%.*]] = xor i1 [[A:%.*]], true ; CHECK-NEXT: [[A_NOT:%.*]] = xor i1 [[A:%.*]], true
; CHECK-NEXT: [[BRMERGE:%.*]] = select i1 [[A_NOT]], i1 true, i1 [[B:%.*]] ; CHECK-NEXT: [[BRMERGE:%.*]] = select i1 [[A_NOT]], i1 true, i1 [[B:%.*]]
; CHECK-NEXT: br i1 [[BRMERGE]], label [[B:%.*]], label [[C:%.*]] ; CHECK-NEXT: br i1 [[BRMERGE]], label [[B:%.*]], label [[COMMON_RET:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: b: ; CHECK: b:
; CHECK-NEXT: store i32 123, i32* [[P:%.*]], align 4 ; CHECK-NEXT: store i32 123, i32* [[P:%.*]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: c:
; CHECK-NEXT: ret void
; ;
entry: entry:
br i1 %A, label %a, label %b br i1 %A, label %a, label %b
a: a:
br i1 %B, label %b, label %c br i1 %B, label %b, label %c
b: b:
store i32 123, i32* %P store i32 123, i32* %P
▲ Show 20 Lines • Show All 94 Lines • Show Last 20 Lines

llvm/test/Transforms/SimplifyCFG/branch-phi-thread.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -adce -S | FileCheck %s ; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -adce -S | FileCheck %s
declare void @f1() declare void @f1()
declare void @f2() declare void @f2()
declare void @f3() declare void @f3()
declare void @f4() declare void @f4()
define i32 @test1(i32 %X, i1 %D) { define i32 @test1(i32 %X, i1 %D) {
; CHECK-LABEL: @test1( ; CHECK-LABEL: @test1(
; CHECK-NEXT: E: ; CHECK-NEXT: E:
; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[X:%.*]], 0 ; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[X:%.*]], 0
; CHECK-NEXT: br i1 [[C]], label [[B:%.*]], label [[F:%.*]] ; CHECK-NEXT: br i1 [[C]], label [[B:%.*]], label [[F:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ 345, [[B]] ], [ 123, [[F]] ]
; CHECK-NEXT: ret i32 [[COMMON_RET_OP]]
; CHECK: B: ; CHECK: B:
; CHECK-NEXT: call void @f2() ; CHECK-NEXT: call void @f2()
; CHECK-NEXT: ret i32 345 ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: F: ; CHECK: F:
; CHECK-NEXT: call void @f3() ; CHECK-NEXT: call void @f3()
; CHECK-NEXT: ret i32 123 ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
E: E:
%C = icmp eq i32 %X, 0 ; <i1> [#uses=2] %C = icmp eq i32 %X, 0 ; <i1> [#uses=2]
br i1 %C, label %T, label %F br i1 %C, label %T, label %F
T: ; preds = %A, %E T: ; preds = %A, %E
br i1 %C, label %B, label %A br i1 %C, label %B, label %A
A: ; preds = %T A: ; preds = %T
call void @f1( ) call void @f1( )
br i1 %D, label %T, label %F br i1 %D, label %T, label %F
B: ; preds = %T B: ; preds = %T
call void @f2( ) call void @f2( )
ret i32 345 ret i32 345
F: ; preds = %A, %E F: ; preds = %A, %E
call void @f3( ) call void @f3( )
ret i32 123 ret i32 123
} }
define i32 @test2(i32 %X, i1 %D) { define i32 @test2(i32 %X, i1 %D) {
; CHECK-LABEL: @test2( ; CHECK-LABEL: @test2(
; CHECK-NEXT: E: ; CHECK-NEXT: E:
; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[X:%.*]], 0 ; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[X:%.*]], 0
; CHECK-NEXT: br i1 [[C]], label [[B:%.*]], label [[F:%.*]] ; CHECK-NEXT: br i1 [[C]], label [[B:%.*]], label [[F:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ 345, [[B]] ], [ 123, [[F]] ]
; CHECK-NEXT: ret i32 [[COMMON_RET_OP]]
; CHECK: B: ; CHECK: B:
; CHECK-NEXT: call void @f2() ; CHECK-NEXT: call void @f2()
; CHECK-NEXT: ret i32 345 ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: F: ; CHECK: F:
; CHECK-NEXT: call void @f3() ; CHECK-NEXT: call void @f3()
; CHECK-NEXT: ret i32 123 ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
E: E:
%C = icmp eq i32 %X, 0 ; <i1> [#uses=2] %C = icmp eq i32 %X, 0 ; <i1> [#uses=2]
br i1 %C, label %T, label %F br i1 %C, label %T, label %F
T: ; preds = %A, %E T: ; preds = %A, %E
%P = phi i1 [ true, %E ], [ %C, %A ] ; <i1> [#uses=1] %P = phi i1 [ true, %E ], [ %C, %A ] ; <i1> [#uses=1]
br i1 %P, label %B, label %A br i1 %P, label %B, label %A
A: ; preds = %T A: ; preds = %T
call void @f1( ) call void @f1( )
br i1 %D, label %T, label %F br i1 %D, label %T, label %F
B: ; preds = %T B: ; preds = %T
call void @f2( ) call void @f2( )
ret i32 345 ret i32 345
F: ; preds = %A, %E F: ; preds = %A, %E
call void @f3( ) call void @f3( )
ret i32 123 ret i32 123
} }
define i32 @test3(i32 %X, i1 %D, i32* %AP, i32* %BP) { define i32 @test3(i32 %X, i1 %D, i32* %AP, i32* %BP) {
; CHECK-LABEL: @test3( ; CHECK-LABEL: @test3(
; CHECK-NEXT: E: ; CHECK-NEXT: E:
; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[X:%.*]], 0 ; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[X:%.*]], 0
; CHECK-NEXT: br i1 [[C]], label [[B_CRITEDGE:%.*]], label [[F:%.*]] ; CHECK-NEXT: br i1 [[C]], label [[B_CRITEDGE:%.*]], label [[F:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ 345, [[B_CRITEDGE]] ], [ 123, [[F]] ]
; CHECK-NEXT: ret i32 [[COMMON_RET_OP]]
; CHECK: B.critedge: ; CHECK: B.critedge:
; CHECK-NEXT: call void @f3() ; CHECK-NEXT: call void @f3()
; CHECK-NEXT: [[XX_C:%.*]] = load i32, i32* [[AP:%.*]], align 4 ; CHECK-NEXT: [[XX_C:%.*]] = load i32, i32* [[AP:%.*]], align 4
; CHECK-NEXT: store i32 [[XX_C]], i32* [[BP:%.*]], align 4 ; CHECK-NEXT: store i32 [[XX_C]], i32* [[BP:%.*]], align 4
; CHECK-NEXT: call void @f2() ; CHECK-NEXT: call void @f2()
; CHECK-NEXT: ret i32 345 ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: F: ; CHECK: F:
; CHECK-NEXT: call void @f3() ; CHECK-NEXT: call void @f3()
; CHECK-NEXT: ret i32 123 ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
E: E:
%C = icmp eq i32 %X, 0 ; <i1> [#uses=2] %C = icmp eq i32 %X, 0 ; <i1> [#uses=2]
br i1 %C, label %T, label %F br i1 %C, label %T, label %F
T: ; preds = %A, %E T: ; preds = %A, %E
call void @f3( ) call void @f3( )
%XX = load i32, i32* %AP ; <i32> [#uses=1] %XX = load i32, i32* %AP ; <i32> [#uses=1]
store i32 %XX, i32* %BP store i32 %XX, i32* %BP
Show All 11 Lines

llvm/test/Transforms/SimplifyCFG/duplicate-landingpad.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s ; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
declare i32 @__gxx_personality_v0(...) declare i32 @__gxx_personality_v0(...)
declare void @fn() declare void @fn()
define void @test1() personality i32 (...)* @__gxx_personality_v0 { define void @test1() personality i32 (...)* @__gxx_personality_v0 {
; CHECK-LABEL: @test1( ; CHECK-LABEL: @test1(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: invoke void @fn() ; CHECK-NEXT: invoke void @fn()
; CHECK-NEXT: to label [[INVOKE2:%.*]] unwind label [[LPAD2:%.*]] ; CHECK-NEXT: to label [[INVOKE2:%.*]] unwind label [[LPAD2:%.*]]
; CHECK: invoke2: ; CHECK: invoke2:
; CHECK-NEXT: invoke void @fn() ; CHECK-NEXT: invoke void @fn()
; CHECK-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD2]] ; CHECK-NEXT: to label [[COMMON_RET:%.*]] unwind label [[LPAD2]]
; CHECK: invoke.cont: ; CHECK: common.ret:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; CHECK: lpad2: ; CHECK: lpad2:
; CHECK-NEXT: [[EXN2:%.*]] = landingpad { i8*, i32 } ; CHECK-NEXT: [[EXN2:%.*]] = landingpad { i8*, i32 }
; CHECK-NEXT: cleanup ; CHECK-NEXT: cleanup
; CHECK-NEXT: call void @fn() ; CHECK-NEXT: call void @fn()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
invoke void @fn() invoke void @fn()
to label %invoke2 unwind label %lpad1 to label %invoke2 unwind label %lpad1
invoke2: invoke2:
invoke void @fn() invoke void @fn()
to label %invoke.cont unwind label %lpad2 to label %invoke.cont unwind label %lpad2
Show All 19 Lines
; Don't trigger if blocks aren't the same/empty ; Don't trigger if blocks aren't the same/empty
define void @neg1() personality i32 (...)* @__gxx_personality_v0 { define void @neg1() personality i32 (...)* @__gxx_personality_v0 {
; CHECK-LABEL: @neg1( ; CHECK-LABEL: @neg1(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: invoke void @fn() ; CHECK-NEXT: invoke void @fn()
; CHECK-NEXT: to label [[INVOKE2:%.*]] unwind label [[LPAD1:%.*]] ; CHECK-NEXT: to label [[INVOKE2:%.*]] unwind label [[LPAD1:%.*]]
; CHECK: invoke2: ; CHECK: invoke2:
; CHECK-NEXT: invoke void @fn() ; CHECK-NEXT: invoke void @fn()
; CHECK-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD2:%.*]] ; CHECK-NEXT: to label [[COMMON_RET:%.*]] unwind label [[LPAD2:%.*]]
; CHECK: invoke.cont: ; CHECK: common.ret:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; CHECK: lpad1: ; CHECK: lpad1:
; CHECK-NEXT: [[EXN:%.*]] = landingpad { i8*, i32 } ; CHECK-NEXT: [[EXN:%.*]] = landingpad { i8*, i32 }
; CHECK-NEXT: filter [0 x i8*] zeroinitializer ; CHECK-NEXT: filter [0 x i8*] zeroinitializer
; CHECK-NEXT: call void @fn() ; CHECK-NEXT: call void @fn()
; CHECK-NEXT: br label [[SHARED_RESUME:%.*]] ; CHECK-NEXT: br label [[SHARED_RESUME:%.*]]
; CHECK: lpad2: ; CHECK: lpad2:
; CHECK-NEXT: [[EXN2:%.*]] = landingpad { i8*, i32 } ; CHECK-NEXT: [[EXN2:%.*]] = landingpad { i8*, i32 }
; CHECK-NEXT: cleanup ; CHECK-NEXT: cleanup
; CHECK-NEXT: br label [[SHARED_RESUME]] ; CHECK-NEXT: br label [[SHARED_RESUME]]
; CHECK: shared_resume: ; CHECK: shared_resume:
; CHECK-NEXT: call void @fn() ; CHECK-NEXT: call void @fn()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
invoke void @fn() invoke void @fn()
to label %invoke2 unwind label %lpad1 to label %invoke2 unwind label %lpad1
invoke2: invoke2:
invoke void @fn() invoke void @fn()
to label %invoke.cont unwind label %lpad2 to label %invoke.cont unwind label %lpad2
Show All 20 Lines
; Should not trigger when the landing pads are not the exact same ; Should not trigger when the landing pads are not the exact same
define void @neg2() personality i32 (...)* @__gxx_personality_v0 { define void @neg2() personality i32 (...)* @__gxx_personality_v0 {
; CHECK-LABEL: @neg2( ; CHECK-LABEL: @neg2(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: invoke void @fn() ; CHECK-NEXT: invoke void @fn()
; CHECK-NEXT: to label [[INVOKE2:%.*]] unwind label [[LPAD1:%.*]] ; CHECK-NEXT: to label [[INVOKE2:%.*]] unwind label [[LPAD1:%.*]]
; CHECK: invoke2: ; CHECK: invoke2:
; CHECK-NEXT: invoke void @fn() ; CHECK-NEXT: invoke void @fn()
; CHECK-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD2:%.*]] ; CHECK-NEXT: to label [[COMMON_RET:%.*]] unwind label [[LPAD2:%.*]]
; CHECK: invoke.cont: ; CHECK: common.ret:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; CHECK: lpad1: ; CHECK: lpad1:
; CHECK-NEXT: [[EXN:%.*]] = landingpad { i8*, i32 } ; CHECK-NEXT: [[EXN:%.*]] = landingpad { i8*, i32 }
; CHECK-NEXT: filter [0 x i8*] zeroinitializer ; CHECK-NEXT: filter [0 x i8*] zeroinitializer
; CHECK-NEXT: br label [[SHARED_RESUME:%.*]] ; CHECK-NEXT: br label [[SHARED_RESUME:%.*]]
; CHECK: lpad2: ; CHECK: lpad2:
; CHECK-NEXT: [[EXN2:%.*]] = landingpad { i8*, i32 } ; CHECK-NEXT: [[EXN2:%.*]] = landingpad { i8*, i32 }
; CHECK-NEXT: cleanup ; CHECK-NEXT: cleanup
; CHECK-NEXT: br label [[SHARED_RESUME]] ; CHECK-NEXT: br label [[SHARED_RESUME]]
; CHECK: shared_resume: ; CHECK: shared_resume:
; CHECK-NEXT: call void @fn() ; CHECK-NEXT: call void @fn()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
invoke void @fn() invoke void @fn()
to label %invoke2 unwind label %lpad1 to label %invoke2 unwind label %lpad1
invoke2: invoke2:
invoke void @fn() invoke void @fn()
to label %invoke.cont unwind label %lpad2 to label %invoke.cont unwind label %lpad2
Show All 18 Lines

llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest-two-preds-cost.ll

Show All 20 Lines
; THR1-NEXT: br i1 [[C1]], label [[FINAL_LEFT:%.*]], label [[DISPATCH:%.*]] ; THR1-NEXT: br i1 [[C1]], label [[FINAL_LEFT:%.*]], label [[DISPATCH:%.*]]
; THR1: pred1: ; THR1: pred1:
; THR1-NEXT: [[C2:%.*]] = icmp eq i8 [[V2:%.*]], 0 ; THR1-NEXT: [[C2:%.*]] = icmp eq i8 [[V2:%.*]], 0
; THR1-NEXT: br i1 [[C2]], label [[DISPATCH]], label [[FINAL_RIGHT:%.*]] ; THR1-NEXT: br i1 [[C2]], label [[DISPATCH]], label [[FINAL_RIGHT:%.*]]
; THR1: dispatch: ; THR1: dispatch:
; THR1-NEXT: [[V3_ADJ:%.*]] = add i8 [[V1]], [[V2]] ; THR1-NEXT: [[V3_ADJ:%.*]] = add i8 [[V1]], [[V2]]
; THR1-NEXT: [[C3:%.*]] = icmp eq i8 [[V3_ADJ]], 0 ; THR1-NEXT: [[C3:%.*]] = icmp eq i8 [[V3_ADJ]], 0
; THR1-NEXT: br i1 [[C3]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]] ; THR1-NEXT: br i1 [[C3]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
; THR1: common.ret:
; THR1-NEXT: ret void
; THR1: final_left: ; THR1: final_left:
; THR1-NEXT: call void @sideeffect0() ; THR1-NEXT: call void @sideeffect0()
; THR1-NEXT: ret void ; THR1-NEXT: br label [[COMMON_RET:%.*]]
; THR1: final_right: ; THR1: final_right:
; THR1-NEXT: call void @sideeffect1() ; THR1-NEXT: call void @sideeffect1()
; THR1-NEXT: ret void ; THR1-NEXT: br label [[COMMON_RET]]
; ;
; THR2-LABEL: @two_preds_with_extra_op( ; THR2-LABEL: @two_preds_with_extra_op(
; THR2-NEXT: entry: ; THR2-NEXT: entry:
; THR2-NEXT: [[C0:%.*]] = icmp eq i8 [[V0:%.*]], 0 ; THR2-NEXT: [[C0:%.*]] = icmp eq i8 [[V0:%.*]], 0
; THR2-NEXT: br i1 [[C0]], label [[PRED0:%.*]], label [[PRED1:%.*]] ; THR2-NEXT: br i1 [[C0]], label [[PRED0:%.*]], label [[PRED1:%.*]]
; THR2: pred0: ; THR2: pred0:
; THR2-NEXT: [[C1:%.*]] = icmp eq i8 [[V1:%.*]], 0 ; THR2-NEXT: [[C1:%.*]] = icmp eq i8 [[V1:%.*]], 0
; THR2-NEXT: [[V3_ADJ_OLD:%.*]] = add i8 [[V1]], [[V2:%.*]] ; THR2-NEXT: [[V3_ADJ_OLD:%.*]] = add i8 [[V1]], [[V2:%.*]]
; THR2-NEXT: [[C3_OLD:%.*]] = icmp eq i8 [[V3_ADJ_OLD]], 0 ; THR2-NEXT: [[C3_OLD:%.*]] = icmp eq i8 [[V3_ADJ_OLD]], 0
; THR2-NEXT: [[OR_COND1:%.*]] = select i1 [[C1]], i1 true, i1 [[C3_OLD]] ; THR2-NEXT: [[OR_COND1:%.*]] = select i1 [[C1]], i1 true, i1 [[C3_OLD]]
; THR2-NEXT: br i1 [[OR_COND1]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]] ; THR2-NEXT: br i1 [[OR_COND1]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]]
; THR2: pred1: ; THR2: pred1:
; THR2-NEXT: [[C2:%.*]] = icmp eq i8 [[V2]], 0 ; THR2-NEXT: [[C2:%.*]] = icmp eq i8 [[V2]], 0
; THR2-NEXT: [[V3_ADJ:%.*]] = add i8 [[V1]], [[V2]] ; THR2-NEXT: [[V3_ADJ:%.*]] = add i8 [[V1]], [[V2]]
; THR2-NEXT: [[C3:%.*]] = icmp eq i8 [[V3_ADJ]], 0 ; THR2-NEXT: [[C3:%.*]] = icmp eq i8 [[V3_ADJ]], 0
; THR2-NEXT: [[OR_COND:%.*]] = select i1 [[C2]], i1 [[C3]], i1 false ; THR2-NEXT: [[OR_COND:%.*]] = select i1 [[C2]], i1 [[C3]], i1 false
; THR2-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]] ; THR2-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
; THR2: common.ret:
; THR2-NEXT: ret void
; THR2: final_left: ; THR2: final_left:
; THR2-NEXT: call void @sideeffect0() ; THR2-NEXT: call void @sideeffect0()
; THR2-NEXT: ret void ; THR2-NEXT: br label [[COMMON_RET:%.*]]
; THR2: final_right: ; THR2: final_right:
; THR2-NEXT: call void @sideeffect1() ; THR2-NEXT: call void @sideeffect1()
; THR2-NEXT: ret void ; THR2-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
%c0 = icmp eq i8 %v0, 0 %c0 = icmp eq i8 %v0, 0
br i1 %c0, label %pred0, label %pred1 br i1 %c0, label %pred0, label %pred1
pred0: pred0:
%c1 = icmp eq i8 %v1, 0 %c1 = icmp eq i8 %v1, 0
br i1 %c1, label %final_left, label %dispatch br i1 %c1, label %final_left, label %dispatch
pred1: pred1:
Show All 28 Lines
; ALL-NEXT: [[V3_ADJ:%.*]] = add i8 [[V1]], [[V2]] ; ALL-NEXT: [[V3_ADJ:%.*]] = add i8 [[V1]], [[V2]]
; ALL-NEXT: [[C3:%.*]] = icmp eq i8 [[V3_ADJ]], 0 ; ALL-NEXT: [[C3:%.*]] = icmp eq i8 [[V3_ADJ]], 0
; ALL-NEXT: [[OR_COND:%.*]] = select i1 [[C2]], i1 [[C3]], i1 false ; ALL-NEXT: [[OR_COND:%.*]] = select i1 [[C2]], i1 [[C3]], i1 false
; ALL-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT:%.*]] ; ALL-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT:%.*]]
; ALL: dispatch: ; ALL: dispatch:
; ALL-NEXT: [[V3_ADJ_OLD:%.*]] = add i8 [[V1]], [[V2]] ; ALL-NEXT: [[V3_ADJ_OLD:%.*]] = add i8 [[V1]], [[V2]]
; ALL-NEXT: [[C3_OLD:%.*]] = icmp eq i8 [[V3_ADJ_OLD]], 0 ; ALL-NEXT: [[C3_OLD:%.*]] = icmp eq i8 [[V3_ADJ_OLD]], 0
; ALL-NEXT: br i1 [[C3_OLD]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]] ; ALL-NEXT: br i1 [[C3_OLD]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
; ALL: common.ret:
; ALL-NEXT: ret void
; ALL: final_left: ; ALL: final_left:
; ALL-NEXT: call void @sideeffect0() ; ALL-NEXT: call void @sideeffect0()
; ALL-NEXT: ret void ; ALL-NEXT: br label [[COMMON_RET:%.*]]
; ALL: final_right: ; ALL: final_right:
; ALL-NEXT: call void @sideeffect1() ; ALL-NEXT: call void @sideeffect1()
; ALL-NEXT: ret void ; ALL-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
%c0 = icmp eq i8 %v0, 0 %c0 = icmp eq i8 %v0, 0
br i1 %c0, label %pred0, label %pred1 br i1 %c0, label %pred0, label %pred1
pred0: pred0:
%c1 = icmp eq i8 %v1, 0 %c1 = icmp eq i8 %v1, 0
br i1 %c1, label %final_left, label %dispatch, !prof !0 ; likely branches to %final_left br i1 %c1, label %final_left, label %dispatch, !prof !0 ; likely branches to %final_left
pred1: pred1:
Show All 17 Lines

llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest.ll

Show All 10 Lines
define void @one_pred(i8 %v0, i8 %v1) { define void @one_pred(i8 %v0, i8 %v1) {
; CHECK-LABEL: @one_pred( ; CHECK-LABEL: @one_pred(
; CHECK-NEXT: pred: ; CHECK-NEXT: pred:
; CHECK-NEXT: [[C0:%.*]] = icmp eq i8 [[V0:%.*]], 0 ; CHECK-NEXT: [[C0:%.*]] = icmp eq i8 [[V0:%.*]], 0
; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[V1:%.*]], 0 ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[V1:%.*]], 0
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false ; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false
; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]] ; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: final_left: ; CHECK: final_left:
; CHECK-NEXT: call void @sideeffect0() ; CHECK-NEXT: call void @sideeffect0()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: final_right: ; CHECK: final_right:
; CHECK-NEXT: call void @sideeffect1() ; CHECK-NEXT: call void @sideeffect1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
pred: pred:
%c0 = icmp eq i8 %v0, 0 %c0 = icmp eq i8 %v0, 0
br i1 %c0, label %dispatch, label %final_right br i1 %c0, label %dispatch, label %final_right
dispatch: dispatch:
%c1 = icmp eq i8 %v1, 0 %c1 = icmp eq i8 %v1, 0
br i1 %c1, label %final_left, label %final_right br i1 %c1, label %final_left, label %final_right
final_left: final_left:
Show All 14 Lines
; CHECK-NEXT: [[C3_OLD:%.*]] = icmp eq i8 [[V3:%.*]], 0 ; CHECK-NEXT: [[C3_OLD:%.*]] = icmp eq i8 [[V3:%.*]], 0
; CHECK-NEXT: [[OR_COND1:%.*]] = select i1 [[C1]], i1 true, i1 [[C3_OLD]] ; CHECK-NEXT: [[OR_COND1:%.*]] = select i1 [[C1]], i1 true, i1 [[C3_OLD]]
; CHECK-NEXT: br i1 [[OR_COND1]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]] ; CHECK-NEXT: br i1 [[OR_COND1]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]]
; CHECK: pred1: ; CHECK: pred1:
; CHECK-NEXT: [[C2:%.*]] = icmp eq i8 [[V2:%.*]], 0 ; CHECK-NEXT: [[C2:%.*]] = icmp eq i8 [[V2:%.*]], 0
; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[V3]], 0 ; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[V3]], 0
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C2]], i1 [[C3]], i1 false ; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C2]], i1 [[C3]], i1 false
; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]] ; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: final_left: ; CHECK: final_left:
; CHECK-NEXT: call void @sideeffect0() ; CHECK-NEXT: call void @sideeffect0()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: final_right: ; CHECK: final_right:
; CHECK-NEXT: call void @sideeffect1() ; CHECK-NEXT: call void @sideeffect1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
%c0 = icmp eq i8 %v0, 0 %c0 = icmp eq i8 %v0, 0
br i1 %c0, label %pred0, label %pred1 br i1 %c0, label %pred0, label %pred1
pred0: pred0:
%c1 = icmp eq i8 %v1, 0 %c1 = icmp eq i8 %v1, 0
br i1 %c1, label %final_left, label %dispatch br i1 %c1, label %final_left, label %dispatch
pred1: pred1:
Show All 15 Lines
define void @one_pred_with_extra_op(i8 %v0, i8 %v1) { define void @one_pred_with_extra_op(i8 %v0, i8 %v1) {
; CHECK-LABEL: @one_pred_with_extra_op( ; CHECK-LABEL: @one_pred_with_extra_op(
; CHECK-NEXT: pred: ; CHECK-NEXT: pred:
; CHECK-NEXT: [[C0:%.*]] = icmp eq i8 [[V0:%.*]], 0 ; CHECK-NEXT: [[C0:%.*]] = icmp eq i8 [[V0:%.*]], 0
; CHECK-NEXT: [[V1_ADJ:%.*]] = add i8 [[V0]], [[V1:%.*]] ; CHECK-NEXT: [[V1_ADJ:%.*]] = add i8 [[V0]], [[V1:%.*]]
; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[V1_ADJ]], 0 ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[V1_ADJ]], 0
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false ; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false
; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]] ; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: final_left: ; CHECK: final_left:
; CHECK-NEXT: call void @sideeffect0() ; CHECK-NEXT: call void @sideeffect0()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: final_right: ; CHECK: final_right:
; CHECK-NEXT: call void @sideeffect1() ; CHECK-NEXT: call void @sideeffect1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
pred: pred:
%c0 = icmp eq i8 %v0, 0 %c0 = icmp eq i8 %v0, 0
br i1 %c0, label %dispatch, label %final_right br i1 %c0, label %dispatch, label %final_right
dispatch: dispatch:
%v1_adj = add i8 %v0, %v1 %v1_adj = add i8 %v0, %v1
%c1 = icmp eq i8 %v1_adj, 0 %c1 = icmp eq i8 %v1_adj, 0
br i1 %c1, label %final_left, label %final_right br i1 %c1, label %final_left, label %final_right
Show All 17 Lines
; CHECK-NEXT: [[OR_COND1:%.*]] = select i1 [[C1]], i1 true, i1 [[C3_OLD]] ; CHECK-NEXT: [[OR_COND1:%.*]] = select i1 [[C1]], i1 true, i1 [[C3_OLD]]
; CHECK-NEXT: br i1 [[OR_COND1]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]] ; CHECK-NEXT: br i1 [[OR_COND1]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]]
; CHECK: pred1: ; CHECK: pred1:
; CHECK-NEXT: [[C2:%.*]] = icmp eq i8 [[V2]], 0 ; CHECK-NEXT: [[C2:%.*]] = icmp eq i8 [[V2]], 0
; CHECK-NEXT: [[V3_ADJ:%.*]] = add i8 [[V1]], [[V2]] ; CHECK-NEXT: [[V3_ADJ:%.*]] = add i8 [[V1]], [[V2]]
; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[V3_ADJ]], 0 ; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[V3_ADJ]], 0
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C2]], i1 [[C3]], i1 false ; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C2]], i1 [[C3]], i1 false
; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]] ; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: final_left: ; CHECK: final_left:
; CHECK-NEXT: call void @sideeffect0() ; CHECK-NEXT: call void @sideeffect0()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: final_right: ; CHECK: final_right:
; CHECK-NEXT: call void @sideeffect1() ; CHECK-NEXT: call void @sideeffect1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
%c0 = icmp eq i8 %v0, 0 %c0 = icmp eq i8 %v0, 0
br i1 %c0, label %pred0, label %pred1 br i1 %c0, label %pred0, label %pred1
pred0: pred0:
%c1 = icmp eq i8 %v1, 0 %c1 = icmp eq i8 %v1, 0
br i1 %c1, label %final_left, label %dispatch br i1 %c1, label %final_left, label %dispatch
pred1: pred1:
Show All 17 Lines
; CHECK-LABEL: @one_pred_with_extra_op_multiuse( ; CHECK-LABEL: @one_pred_with_extra_op_multiuse(
; CHECK-NEXT: pred: ; CHECK-NEXT: pred:
; CHECK-NEXT: [[C0:%.*]] = icmp eq i8 [[V0:%.*]], 0 ; CHECK-NEXT: [[C0:%.*]] = icmp eq i8 [[V0:%.*]], 0
; CHECK-NEXT: [[V1_ADJ:%.*]] = add i8 [[V0]], [[V1:%.*]] ; CHECK-NEXT: [[V1_ADJ:%.*]] = add i8 [[V0]], [[V1:%.*]]
; CHECK-NEXT: [[V1_ADJ_ADJ:%.*]] = add i8 [[V1_ADJ]], [[V1_ADJ]] ; CHECK-NEXT: [[V1_ADJ_ADJ:%.*]] = add i8 [[V1_ADJ]], [[V1_ADJ]]
; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[V1_ADJ_ADJ]], 0 ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[V1_ADJ_ADJ]], 0
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false ; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false
; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]] ; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: final_left: ; CHECK: final_left:
; CHECK-NEXT: call void @sideeffect0() ; CHECK-NEXT: call void @sideeffect0()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: final_right: ; CHECK: final_right:
; CHECK-NEXT: call void @sideeffect1() ; CHECK-NEXT: call void @sideeffect1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
pred: pred:
%c0 = icmp eq i8 %v0, 0 %c0 = icmp eq i8 %v0, 0
br i1 %c0, label %dispatch, label %final_right br i1 %c0, label %dispatch, label %final_right
dispatch: dispatch:
%v1_adj = add i8 %v0, %v1 %v1_adj = add i8 %v0, %v1
%v1_adj_adj = add i8 %v1_adj, %v1_adj %v1_adj_adj = add i8 %v1_adj, %v1_adj
%c1 = icmp eq i8 %v1_adj_adj, 0 %c1 = icmp eq i8 %v1_adj_adj, 0
Show All 20 Lines
; CHECK-NEXT: br i1 [[OR_COND1]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]] ; CHECK-NEXT: br i1 [[OR_COND1]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]]
; CHECK: pred1: ; CHECK: pred1:
; CHECK-NEXT: [[C2:%.*]] = icmp eq i8 [[V2]], 0 ; CHECK-NEXT: [[C2:%.*]] = icmp eq i8 [[V2]], 0
; CHECK-NEXT: [[V3_ADJ:%.*]] = add i8 [[V1]], [[V2]] ; CHECK-NEXT: [[V3_ADJ:%.*]] = add i8 [[V1]], [[V2]]
; CHECK-NEXT: [[V3_ADJ_ADJ:%.*]] = add i8 [[V3_ADJ]], [[V3_ADJ]] ; CHECK-NEXT: [[V3_ADJ_ADJ:%.*]] = add i8 [[V3_ADJ]], [[V3_ADJ]]
; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[V3_ADJ_ADJ]], 0 ; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[V3_ADJ_ADJ]], 0
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C2]], i1 [[C3]], i1 false ; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C2]], i1 [[C3]], i1 false
; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]] ; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: final_left: ; CHECK: final_left:
; CHECK-NEXT: call void @sideeffect0() ; CHECK-NEXT: call void @sideeffect0()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: final_right: ; CHECK: final_right:
; CHECK-NEXT: call void @sideeffect1() ; CHECK-NEXT: call void @sideeffect1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
%c0 = icmp eq i8 %v0, 0 %c0 = icmp eq i8 %v0, 0
br i1 %c0, label %pred0, label %pred1 br i1 %c0, label %pred0, label %pred1
pred0: pred0:
%c1 = icmp eq i8 %v1, 0 %c1 = icmp eq i8 %v1, 0
br i1 %c1, label %final_left, label %dispatch br i1 %c1, label %final_left, label %dispatch
pred1: pred1:
Show All 18 Lines
define void @one_pred_with_extra_op_liveout(i8 %v0, i8 %v1) { define void @one_pred_with_extra_op_liveout(i8 %v0, i8 %v1) {
; CHECK-LABEL: @one_pred_with_extra_op_liveout( ; CHECK-LABEL: @one_pred_with_extra_op_liveout(
; CHECK-NEXT: pred: ; CHECK-NEXT: pred:
; CHECK-NEXT: [[C0:%.*]] = icmp eq i8 [[V0:%.*]], 0 ; CHECK-NEXT: [[C0:%.*]] = icmp eq i8 [[V0:%.*]], 0
; CHECK-NEXT: [[V1_ADJ:%.*]] = add i8 [[V0]], [[V1:%.*]] ; CHECK-NEXT: [[V1_ADJ:%.*]] = add i8 [[V0]], [[V1:%.*]]
; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[V1_ADJ]], 0 ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[V1_ADJ]], 0
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false ; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false
; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]] ; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: final_left: ; CHECK: final_left:
; CHECK-NEXT: call void @sideeffect0() ; CHECK-NEXT: call void @sideeffect0()
; CHECK-NEXT: call void @use8(i8 [[V1_ADJ]]) ; CHECK-NEXT: call void @use8(i8 [[V1_ADJ]])
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: final_right: ; CHECK: final_right:
; CHECK-NEXT: call void @sideeffect1() ; CHECK-NEXT: call void @sideeffect1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
pred: pred:
%c0 = icmp eq i8 %v0, 0 %c0 = icmp eq i8 %v0, 0
br i1 %c0, label %dispatch, label %final_right br i1 %c0, label %dispatch, label %final_right
dispatch: dispatch:
%v1_adj = add i8 %v0, %v1 %v1_adj = add i8 %v0, %v1
%c1 = icmp eq i8 %v1_adj, 0 %c1 = icmp eq i8 %v1_adj, 0
br i1 %c1, label %final_left, label %final_right br i1 %c1, label %final_left, label %final_right
final_left: final_left:
call void @sideeffect0() call void @sideeffect0()
call void @use8(i8 %v1_adj) call void @use8(i8 %v1_adj)
ret void ret void
final_right: final_right:
call void @sideeffect1() call void @sideeffect1()
ret void ret void
} }
define void @one_pred_with_extra_op_liveout_multiuse(i8 %v0, i8 %v1) { define void @one_pred_with_extra_op_liveout_multiuse(i8 %v0, i8 %v1) {
; CHECK-LABEL: @one_pred_with_extra_op_liveout_multiuse( ; CHECK-LABEL: @one_pred_with_extra_op_liveout_multiuse(
; CHECK-NEXT: pred: ; CHECK-NEXT: pred:
; CHECK-NEXT: [[C0:%.*]] = icmp eq i8 [[V0:%.*]], 0 ; CHECK-NEXT: [[C0:%.*]] = icmp eq i8 [[V0:%.*]], 0
; CHECK-NEXT: [[V1_ADJ:%.*]] = add i8 [[V0]], [[V1:%.*]] ; CHECK-NEXT: [[V1_ADJ:%.*]] = add i8 [[V0]], [[V1:%.*]]
; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[V1_ADJ]], 0 ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[V1_ADJ]], 0
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false ; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false
; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]] ; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: final_left: ; CHECK: final_left:
; CHECK-NEXT: call void @sideeffect0() ; CHECK-NEXT: call void @sideeffect0()
; CHECK-NEXT: call void @use8(i8 [[V1_ADJ]]) ; CHECK-NEXT: call void @use8(i8 [[V1_ADJ]])
; CHECK-NEXT: call void @use8(i8 [[V1_ADJ]]) ; CHECK-NEXT: call void @use8(i8 [[V1_ADJ]])
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: final_right: ; CHECK: final_right:
; CHECK-NEXT: call void @sideeffect1() ; CHECK-NEXT: call void @sideeffect1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
pred: pred:
%c0 = icmp eq i8 %v0, 0 %c0 = icmp eq i8 %v0, 0
br i1 %c0, label %dispatch, label %final_right br i1 %c0, label %dispatch, label %final_right
dispatch: dispatch:
%v1_adj = add i8 %v0, %v1 %v1_adj = add i8 %v0, %v1
%c1 = icmp eq i8 %v1_adj, 0 %c1 = icmp eq i8 %v1_adj, 0
br i1 %c1, label %final_left, label %final_right br i1 %c1, label %final_left, label %final_right
Show All 17 Lines
; CHECK-NEXT: [[V2_ADJ:%.*]] = add i8 [[V0]], [[V1]] ; CHECK-NEXT: [[V2_ADJ:%.*]] = add i8 [[V0]], [[V1]]
; CHECK-NEXT: [[C2:%.*]] = icmp eq i8 [[V2_ADJ]], 0 ; CHECK-NEXT: [[C2:%.*]] = icmp eq i8 [[V2_ADJ]], 0
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C1]], i1 [[C2]], i1 false ; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C1]], i1 [[C2]], i1 false
; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]] ; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]]
; CHECK: final_left: ; CHECK: final_left:
; CHECK-NEXT: call void @sideeffect0() ; CHECK-NEXT: call void @sideeffect0()
; CHECK-NEXT: call void @use8(i8 [[V2_ADJ]]) ; CHECK-NEXT: call void @use8(i8 [[V2_ADJ]])
; CHECK-NEXT: br label [[LEFT_END]] ; CHECK-NEXT: br label [[LEFT_END]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: left_end: ; CHECK: left_end:
; CHECK-NEXT: [[MERGE_LEFT:%.*]] = phi i8 [ [[V2_ADJ]], [[FINAL_LEFT]] ], [ 0, [[ENTRY:%.*]] ] ; CHECK-NEXT: [[MERGE_LEFT:%.*]] = phi i8 [ [[V2_ADJ]], [[FINAL_LEFT]] ], [ 0, [[ENTRY:%.*]] ]
; CHECK-NEXT: call void @sideeffect1() ; CHECK-NEXT: call void @sideeffect1()
; CHECK-NEXT: call void @use8(i8 [[MERGE_LEFT]]) ; CHECK-NEXT: call void @use8(i8 [[MERGE_LEFT]])
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: final_right: ; CHECK: final_right:
; CHECK-NEXT: call void @sideeffect2() ; CHECK-NEXT: call void @sideeffect2()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
%c0 = icmp eq i8 %v0, 0 %c0 = icmp eq i8 %v0, 0
br i1 %c0, label %pred, label %left_end br i1 %c0, label %pred, label %left_end
pred: pred:
%c1 = icmp eq i8 %v1, 0 %c1 = icmp eq i8 %v1, 0
br i1 %c1, label %dispatch, label %final_right br i1 %c1, label %dispatch, label %final_right
dispatch: dispatch:
Show All 27 Lines
; CHECK-NEXT: [[V3_ADJ:%.*]] = add i8 [[V1]], [[V2]] ; CHECK-NEXT: [[V3_ADJ:%.*]] = add i8 [[V1]], [[V2]]
; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[V3_ADJ]], 0 ; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[V3_ADJ]], 0
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C2]], i1 [[C3]], i1 false ; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C2]], i1 [[C3]], i1 false
; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT:%.*]] ; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT:%.*]]
; CHECK: dispatch: ; CHECK: dispatch:
; CHECK-NEXT: [[V3_ADJ_OLD:%.*]] = add i8 [[V1]], [[V2]] ; CHECK-NEXT: [[V3_ADJ_OLD:%.*]] = add i8 [[V1]], [[V2]]
; CHECK-NEXT: [[C3_OLD:%.*]] = icmp eq i8 [[V3_ADJ_OLD]], 0 ; CHECK-NEXT: [[C3_OLD:%.*]] = icmp eq i8 [[V3_ADJ_OLD]], 0
; CHECK-NEXT: br i1 [[C3_OLD]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]] ; CHECK-NEXT: br i1 [[C3_OLD]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: final_left: ; CHECK: final_left:
; CHECK-NEXT: [[MERGE_LEFT:%.*]] = phi i8 [ [[V3_ADJ_OLD]], [[DISPATCH]] ], [ 0, [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ] ; CHECK-NEXT: [[MERGE_LEFT:%.*]] = phi i8 [ [[V3_ADJ_OLD]], [[DISPATCH]] ], [ 0, [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ]
; CHECK-NEXT: call void @use8(i8 [[MERGE_LEFT]]) ; CHECK-NEXT: call void @use8(i8 [[MERGE_LEFT]])
; CHECK-NEXT: call void @sideeffect0() ; CHECK-NEXT: call void @sideeffect0()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: final_right: ; CHECK: final_right:
; CHECK-NEXT: call void @sideeffect1() ; CHECK-NEXT: call void @sideeffect1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
%c0 = icmp eq i8 %v0, 0 %c0 = icmp eq i8 %v0, 0
br i1 %c0, label %pred0, label %pred1 br i1 %c0, label %pred0, label %pred1
pred0: pred0:
%c1 = icmp eq i8 %v1, 0 %c1 = icmp eq i8 %v1, 0
br i1 %c1, label %final_left, label %dispatch br i1 %c1, label %final_left, label %dispatch
pred1: pred1:
Show All 26 Lines
; CHECK-NEXT: [[V3_ADJ:%.*]] = add i8 [[V1]], [[V2]] ; CHECK-NEXT: [[V3_ADJ:%.*]] = add i8 [[V1]], [[V2]]
; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[V3_ADJ]], 0 ; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[V3_ADJ]], 0
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C2]], i1 [[C3]], i1 false ; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C2]], i1 [[C3]], i1 false
; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT:%.*]] ; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT:%.*]]
; CHECK: dispatch: ; CHECK: dispatch:
; CHECK-NEXT: [[V3_ADJ_OLD:%.*]] = add i8 [[V1]], [[V2]] ; CHECK-NEXT: [[V3_ADJ_OLD:%.*]] = add i8 [[V1]], [[V2]]
; CHECK-NEXT: [[C3_OLD:%.*]] = icmp eq i8 [[V3_ADJ_OLD]], 0 ; CHECK-NEXT: [[C3_OLD:%.*]] = icmp eq i8 [[V3_ADJ_OLD]], 0
; CHECK-NEXT: br i1 [[C3_OLD]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]] ; CHECK-NEXT: br i1 [[C3_OLD]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: final_left: ; CHECK: final_left:
; CHECK-NEXT: [[MERGE_LEFT:%.*]] = phi i8 [ [[V3_ADJ_OLD]], [[DISPATCH]] ], [ 0, [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ] ; CHECK-NEXT: [[MERGE_LEFT:%.*]] = phi i8 [ [[V3_ADJ_OLD]], [[DISPATCH]] ], [ 0, [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ]
; CHECK-NEXT: [[MERGE_LEFT_2:%.*]] = phi i8 [ [[V3_ADJ_OLD]], [[DISPATCH]] ], [ 42, [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ] ; CHECK-NEXT: [[MERGE_LEFT_2:%.*]] = phi i8 [ [[V3_ADJ_OLD]], [[DISPATCH]] ], [ 42, [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ]
; CHECK-NEXT: call void @use8(i8 [[MERGE_LEFT]]) ; CHECK-NEXT: call void @use8(i8 [[MERGE_LEFT]])
; CHECK-NEXT: call void @use8(i8 [[MERGE_LEFT_2]]) ; CHECK-NEXT: call void @use8(i8 [[MERGE_LEFT_2]])
; CHECK-NEXT: call void @sideeffect0() ; CHECK-NEXT: call void @sideeffect0()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: final_right: ; CHECK: final_right:
; CHECK-NEXT: call void @sideeffect1() ; CHECK-NEXT: call void @sideeffect1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
%c0 = icmp eq i8 %v0, 0 %c0 = icmp eq i8 %v0, 0
br i1 %c0, label %pred0, label %pred1 br i1 %c0, label %pred0, label %pred1
pred0: pred0:
%c1 = icmp eq i8 %v1, 0 %c1 = icmp eq i8 %v1, 0
br i1 %c1, label %final_left, label %dispatch br i1 %c1, label %final_left, label %dispatch
pred1: pred1:
Show All 21 Lines
define void @one_pred_with_extra_op_eexternally_used_only(i8 %v0, i8 %v1) { define void @one_pred_with_extra_op_eexternally_used_only(i8 %v0, i8 %v1) {
; CHECK-LABEL: @one_pred_with_extra_op_eexternally_used_only( ; CHECK-LABEL: @one_pred_with_extra_op_eexternally_used_only(
; CHECK-NEXT: pred: ; CHECK-NEXT: pred:
; CHECK-NEXT: [[C0:%.*]] = icmp eq i8 [[V0:%.*]], 0 ; CHECK-NEXT: [[C0:%.*]] = icmp eq i8 [[V0:%.*]], 0
; CHECK-NEXT: [[V1_ADJ:%.*]] = add i8 [[V0]], [[V1:%.*]] ; CHECK-NEXT: [[V1_ADJ:%.*]] = add i8 [[V0]], [[V1:%.*]]
; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[V1]], 0 ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[V1]], 0
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false ; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false
; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]] ; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: final_left: ; CHECK: final_left:
; CHECK-NEXT: call void @sideeffect0() ; CHECK-NEXT: call void @sideeffect0()
; CHECK-NEXT: call void @use8(i8 [[V1_ADJ]]) ; CHECK-NEXT: call void @use8(i8 [[V1_ADJ]])
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: final_right: ; CHECK: final_right:
; CHECK-NEXT: call void @sideeffect1() ; CHECK-NEXT: call void @sideeffect1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
pred: pred:
%c0 = icmp eq i8 %v0, 0 %c0 = icmp eq i8 %v0, 0
br i1 %c0, label %dispatch, label %final_right br i1 %c0, label %dispatch, label %final_right
dispatch: dispatch:
%v1_adj = add i8 %v0, %v1 %v1_adj = add i8 %v0, %v1
%c1 = icmp eq i8 %v1, 0 %c1 = icmp eq i8 %v1, 0
br i1 %c1, label %final_left, label %final_right br i1 %c1, label %final_left, label %final_right
final_left: final_left:
call void @sideeffect0() call void @sideeffect0()
call void @use8(i8 %v1_adj) call void @use8(i8 %v1_adj)
ret void ret void
final_right: final_right:
call void @sideeffect1() call void @sideeffect1()
ret void ret void
} }
define void @one_pred_with_extra_op_externally_used_only_multiuse(i8 %v0, i8 %v1) { define void @one_pred_with_extra_op_externally_used_only_multiuse(i8 %v0, i8 %v1) {
; CHECK-LABEL: @one_pred_with_extra_op_externally_used_only_multiuse( ; CHECK-LABEL: @one_pred_with_extra_op_externally_used_only_multiuse(
; CHECK-NEXT: pred: ; CHECK-NEXT: pred:
; CHECK-NEXT: [[C0:%.*]] = icmp eq i8 [[V0:%.*]], 0 ; CHECK-NEXT: [[C0:%.*]] = icmp eq i8 [[V0:%.*]], 0
; CHECK-NEXT: [[V1_ADJ:%.*]] = add i8 [[V0]], [[V1:%.*]] ; CHECK-NEXT: [[V1_ADJ:%.*]] = add i8 [[V0]], [[V1:%.*]]
; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[V1]], 0 ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[V1]], 0
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false ; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false
; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]] ; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: final_left: ; CHECK: final_left:
; CHECK-NEXT: call void @sideeffect0() ; CHECK-NEXT: call void @sideeffect0()
; CHECK-NEXT: call void @use8(i8 [[V1_ADJ]]) ; CHECK-NEXT: call void @use8(i8 [[V1_ADJ]])
; CHECK-NEXT: call void @use8(i8 [[V1_ADJ]]) ; CHECK-NEXT: call void @use8(i8 [[V1_ADJ]])
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: final_right: ; CHECK: final_right:
; CHECK-NEXT: call void @sideeffect1() ; CHECK-NEXT: call void @sideeffect1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
pred: pred:
%c0 = icmp eq i8 %v0, 0 %c0 = icmp eq i8 %v0, 0
br i1 %c0, label %dispatch, label %final_right br i1 %c0, label %dispatch, label %final_right
dispatch: dispatch:
%v1_adj = add i8 %v0, %v1 %v1_adj = add i8 %v0, %v1
%c1 = icmp eq i8 %v1, 0 %c1 = icmp eq i8 %v1, 0
br i1 %c1, label %final_left, label %final_right br i1 %c1, label %final_left, label %final_right
Show All 20 Lines
; CHECK-NEXT: [[V3_ADJ:%.*]] = add i8 [[V1]], [[V2]] ; CHECK-NEXT: [[V3_ADJ:%.*]] = add i8 [[V1]], [[V2]]
; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[V3:%.*]], 0 ; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[V3:%.*]], 0
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C2]], i1 [[C3]], i1 false ; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C2]], i1 [[C3]], i1 false
; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT:%.*]] ; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT:%.*]]
; CHECK: dispatch: ; CHECK: dispatch:
; CHECK-NEXT: [[V3_ADJ_OLD:%.*]] = add i8 [[V1]], [[V2]] ; CHECK-NEXT: [[V3_ADJ_OLD:%.*]] = add i8 [[V1]], [[V2]]
; CHECK-NEXT: [[C3_OLD:%.*]] = icmp eq i8 [[V3]], 0 ; CHECK-NEXT: [[C3_OLD:%.*]] = icmp eq i8 [[V3]], 0
; CHECK-NEXT: br i1 [[C3_OLD]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]] ; CHECK-NEXT: br i1 [[C3_OLD]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: final_left: ; CHECK: final_left:
; CHECK-NEXT: [[MERGE_LEFT:%.*]] = phi i8 [ [[V3_ADJ_OLD]], [[DISPATCH]] ], [ 0, [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ] ; CHECK-NEXT: [[MERGE_LEFT:%.*]] = phi i8 [ [[V3_ADJ_OLD]], [[DISPATCH]] ], [ 0, [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ]
; CHECK-NEXT: call void @use8(i8 [[MERGE_LEFT]]) ; CHECK-NEXT: call void @use8(i8 [[MERGE_LEFT]])
; CHECK-NEXT: call void @sideeffect0() ; CHECK-NEXT: call void @sideeffect0()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: final_right: ; CHECK: final_right:
; CHECK-NEXT: call void @sideeffect1() ; CHECK-NEXT: call void @sideeffect1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
%c0 = icmp eq i8 %v0, 0 %c0 = icmp eq i8 %v0, 0
br i1 %c0, label %pred0, label %pred1 br i1 %c0, label %pred0, label %pred1
pred0: pred0:
%c1 = icmp eq i8 %v1, 0 %c1 = icmp eq i8 %v1, 0
br i1 %c1, label %final_left, label %dispatch br i1 %c1, label %final_left, label %dispatch
pred1: pred1:
Show All 26 Lines
; CHECK-NEXT: [[V3_ADJ:%.*]] = add i8 [[V1]], [[V2]] ; CHECK-NEXT: [[V3_ADJ:%.*]] = add i8 [[V1]], [[V2]]
; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[V3:%.*]], 0 ; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[V3:%.*]], 0
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C2]], i1 [[C3]], i1 false ; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C2]], i1 [[C3]], i1 false
; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT:%.*]] ; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT:%.*]]
; CHECK: dispatch: ; CHECK: dispatch:
; CHECK-NEXT: [[V3_ADJ_OLD:%.*]] = add i8 [[V1]], [[V2]] ; CHECK-NEXT: [[V3_ADJ_OLD:%.*]] = add i8 [[V1]], [[V2]]
; CHECK-NEXT: [[C3_OLD:%.*]] = icmp eq i8 [[V3]], 0 ; CHECK-NEXT: [[C3_OLD:%.*]] = icmp eq i8 [[V3]], 0
; CHECK-NEXT: br i1 [[C3_OLD]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]] ; CHECK-NEXT: br i1 [[C3_OLD]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: final_left: ; CHECK: final_left:
; CHECK-NEXT: [[MERGE_LEFT:%.*]] = phi i8 [ [[V3_ADJ_OLD]], [[DISPATCH]] ], [ 0, [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ] ; CHECK-NEXT: [[MERGE_LEFT:%.*]] = phi i8 [ [[V3_ADJ_OLD]], [[DISPATCH]] ], [ 0, [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ]
; CHECK-NEXT: [[MERGE_LEFT_2:%.*]] = phi i8 [ [[V3_ADJ_OLD]], [[DISPATCH]] ], [ 42, [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ] ; CHECK-NEXT: [[MERGE_LEFT_2:%.*]] = phi i8 [ [[V3_ADJ_OLD]], [[DISPATCH]] ], [ 42, [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ]
; CHECK-NEXT: call void @use8(i8 [[MERGE_LEFT]]) ; CHECK-NEXT: call void @use8(i8 [[MERGE_LEFT]])
; CHECK-NEXT: call void @use8(i8 [[MERGE_LEFT_2]]) ; CHECK-NEXT: call void @use8(i8 [[MERGE_LEFT_2]])
; CHECK-NEXT: call void @sideeffect0() ; CHECK-NEXT: call void @sideeffect0()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: final_right: ; CHECK: final_right:
; CHECK-NEXT: call void @sideeffect1() ; CHECK-NEXT: call void @sideeffect1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
%c0 = icmp eq i8 %v0, 0 %c0 = icmp eq i8 %v0, 0
br i1 %c0, label %pred0, label %pred1 br i1 %c0, label %pred0, label %pred1
pred0: pred0:
%c1 = icmp eq i8 %v1, 0 %c1 = icmp eq i8 %v1, 0
br i1 %c1, label %final_left, label %dispatch br i1 %c1, label %final_left, label %dispatch
pred1: pred1:
Show All 26 Lines
; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[V3:%.*]], 0 ; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[V3:%.*]], 0
; CHECK-NEXT: [[V2_ADJ:%.*]] = add i8 [[V4:%.*]], [[V5:%.*]] ; CHECK-NEXT: [[V2_ADJ:%.*]] = add i8 [[V4:%.*]], [[V5:%.*]]
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C1]], i1 [[C3]], i1 false ; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C1]], i1 [[C3]], i1 false
; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]] ; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]]
; CHECK: final_left: ; CHECK: final_left:
; CHECK-NEXT: call void @sideeffect0() ; CHECK-NEXT: call void @sideeffect0()
; CHECK-NEXT: call void @use8(i8 [[V2_ADJ]]) ; CHECK-NEXT: call void @use8(i8 [[V2_ADJ]])
; CHECK-NEXT: br label [[LEFT_END]] ; CHECK-NEXT: br label [[LEFT_END]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: left_end: ; CHECK: left_end:
; CHECK-NEXT: [[MERGE_LEFT:%.*]] = phi i8 [ [[V2_ADJ]], [[FINAL_LEFT]] ], [ 0, [[ENTRY:%.*]] ] ; CHECK-NEXT: [[MERGE_LEFT:%.*]] = phi i8 [ [[V2_ADJ]], [[FINAL_LEFT]] ], [ 0, [[ENTRY:%.*]] ]
; CHECK-NEXT: call void @sideeffect1() ; CHECK-NEXT: call void @sideeffect1()
; CHECK-NEXT: call void @use8(i8 [[MERGE_LEFT]]) ; CHECK-NEXT: call void @use8(i8 [[MERGE_LEFT]])
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: final_right: ; CHECK: final_right:
; CHECK-NEXT: call void @sideeffect2() ; CHECK-NEXT: call void @sideeffect2()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
%c0 = icmp eq i8 %v0, 0 %c0 = icmp eq i8 %v0, 0
br i1 %c0, label %pred, label %left_end br i1 %c0, label %pred, label %left_end
pred: pred:
%c1 = icmp eq i8 %v1, 0 %c1 = icmp eq i8 %v1, 0
br i1 %c1, label %dispatch, label %final_right br i1 %c1, label %dispatch, label %final_right
dispatch: dispatch:
Show All 26 Lines
; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[V3:%.*]], 0 ; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[V3:%.*]], 0
; CHECK-NEXT: [[V3_ADJ:%.*]] = add i8 [[V4:%.*]], [[V5:%.*]] ; CHECK-NEXT: [[V3_ADJ:%.*]] = add i8 [[V4:%.*]], [[V5:%.*]]
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C2]], i1 [[C3]], i1 false ; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[C2]], i1 [[C3]], i1 false
; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT:%.*]] ; CHECK-NEXT: br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT:%.*]]
; CHECK: dispatch: ; CHECK: dispatch:
; CHECK-NEXT: [[C3_OLD:%.*]] = icmp eq i8 [[V3]], 0 ; CHECK-NEXT: [[C3_OLD:%.*]] = icmp eq i8 [[V3]], 0
; CHECK-NEXT: [[V3_ADJ_OLD:%.*]] = add i8 [[V4]], [[V5]] ; CHECK-NEXT: [[V3_ADJ_OLD:%.*]] = add i8 [[V4]], [[V5]]
; CHECK-NEXT: br i1 [[C3_OLD]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]] ; CHECK-NEXT: br i1 [[C3_OLD]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: final_left: ; CHECK: final_left:
; CHECK-NEXT: [[MERGE_LEFT:%.*]] = phi i8 [ [[V3_ADJ_OLD]], [[DISPATCH]] ], [ 0, [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ] ; CHECK-NEXT: [[MERGE_LEFT:%.*]] = phi i8 [ [[V3_ADJ_OLD]], [[DISPATCH]] ], [ 0, [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ]
; CHECK-NEXT: call void @use8(i8 [[MERGE_LEFT]]) ; CHECK-NEXT: call void @use8(i8 [[MERGE_LEFT]])
; CHECK-NEXT: call void @sideeffect0() ; CHECK-NEXT: call void @sideeffect0()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: final_right: ; CHECK: final_right:
; CHECK-NEXT: call void @sideeffect1() ; CHECK-NEXT: call void @sideeffect1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
%c0 = icmp eq i8 %v0, 0 %c0 = icmp eq i8 %v0, 0
br i1 %c0, label %pred0, label %pred1 br i1 %c0, label %pred0, label %pred1
pred0: pred0:
%c1 = icmp eq i8 %v1, 0 %c1 = icmp eq i8 %v1, 0
br i1 %c1, label %final_left, label %dispatch br i1 %c1, label %final_left, label %dispatch
pred1: pred1:
▲ Show 20 Lines • Show All 216 Lines • Show Last 20 Lines

llvm/test/Transforms/SimplifyCFG/guards.ll

Show All 12 Linesentry:
call void(i1, ...) @llvm.experimental.guard(i1 false) [ "deopt"() ] call void(i1, ...) @llvm.experimental.guard(i1 false) [ "deopt"() ]
ret i32 10 ret i32 10
} }
define i32 @f_1(i1 %c) { define i32 @f_1(i1 %c) {
; Demonstrate that we (intentionally) do not simplify a guard on undef ; Demonstrate that we (intentionally) do not simplify a guard on undef
; CHECK-LABEL: @f_1( ; CHECK-LABEL: @f_1(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[C:%.*]], label [[TRUE:%.*]], label [[FALSE:%.*]] ; CHECK-NEXT: br i1 [[C:%.*]], label [[TRUE:%.*]], label [[COMMON_RET:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ 10, [[TRUE]] ], [ 20, [[ENTRY:%.*]] ]
; CHECK-NEXT: ret i32 [[COMMON_RET_OP]]
; CHECK: true: ; CHECK: true:
; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 undef) [ "deopt"() ] ; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 undef) [ "deopt"() ]
; CHECK-NEXT: ret i32 10 ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: false:
; CHECK-NEXT: ret i32 20
; ;
entry: entry:
br i1 %c, label %true, label %false br i1 %c, label %true, label %false
true: true:
call void(i1, ...) @llvm.experimental.guard(i1 undef) [ "deopt"() ] call void(i1, ...) @llvm.experimental.guard(i1 undef) [ "deopt"() ]
ret i32 10 ret i32 10
Show All 31 Lines
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[C0:%.*]] = load volatile i1, i1* [[C:%.*]], align 1 ; CHECK-NEXT: [[C0:%.*]] = load volatile i1, i1* [[C:%.*]], align 1
; CHECK-NEXT: br i1 [[C0]], label [[GUARD_BLOCK:%.*]], label [[MERGE_BLOCK:%.*]] ; CHECK-NEXT: br i1 [[C0]], label [[GUARD_BLOCK:%.*]], label [[MERGE_BLOCK:%.*]]
; CHECK: guard_block: ; CHECK: guard_block:
; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 false) [ "deopt"() ] ; CHECK-NEXT: call void (i1, ...) @llvm.experimental.guard(i1 false) [ "deopt"() ]
; CHECK-NEXT: unreachable ; CHECK-NEXT: unreachable
; CHECK: merge_block: ; CHECK: merge_block:
; CHECK-NEXT: [[C1:%.*]] = load volatile i1, i1* [[C]], align 1 ; CHECK-NEXT: [[C1:%.*]] = load volatile i1, i1* [[C]], align 1
; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[C1]], i32 50, i32 100 ; CHECK-NEXT: [[DOT:%.*]] = select i1 [[C1]], i32 50, i32 100
; CHECK-NEXT: ret i32 [[SPEC_SELECT]] ; CHECK-NEXT: ret i32 [[DOT]]
; ;
entry: entry:
%c0 = load volatile i1, i1* %c %c0 = load volatile i1, i1* %c
br i1 %c0, label %guard_block, label %merge_block br i1 %c0, label %guard_block, label %merge_block
guard_block: guard_block:
call void(i1, ...) @llvm.experimental.guard(i1 false) [ "deopt"() ] call void(i1, ...) @llvm.experimental.guard(i1 false) [ "deopt"() ]
%val = load i32, i32* %buf %val = load i32, i32* %buf
Show All 17 Lines

llvm/test/Transforms/SimplifyCFG/hoist-common-code.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S -hoist-common-insts=true | FileCheck %s ; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S -hoist-common-insts=true | FileCheck %s
declare void @bar(i32) declare void @bar(i32)
define void @test(i1 %P, i32* %Q) { define void @test(i1 %P, i32* %Q) {
; CHECK-LABEL: @test( ; CHECK-LABEL: @test(
; CHECK-NEXT: common.ret:
; CHECK-NEXT: store i32 1, i32* [[Q:%.*]], align 4 ; CHECK-NEXT: store i32 1, i32* [[Q:%.*]], align 4
; CHECK-NEXT: [[A:%.*]] = load i32, i32* [[Q]], align 4 ; CHECK-NEXT: [[A:%.*]] = load i32, i32* [[Q]], align 4
; CHECK-NEXT: call void @bar(i32 [[A]]) ; CHECK-NEXT: call void @bar(i32 [[A]])
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
br i1 %P, label %T, label %F br i1 %P, label %T, label %F
T: ; preds = %0 T: ; preds = %0
store i32 1, i32* %Q store i32 1, i32* %Q
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llvm/test/Transforms/SimplifyCFG/indirectbr.ll

Show All 14 Lines
; CHECK-NEXT: store i8* blockaddress(@indbrtest0, [[BB1:%.*]]), i8** [[P]], align 8 ; CHECK-NEXT: store i8* blockaddress(@indbrtest0, [[BB1:%.*]]), i8** [[P]], align 8
; CHECK-NEXT: store i8* blockaddress(@indbrtest0, [[BB2:%.*]]), i8** [[P]], align 8 ; CHECK-NEXT: store i8* blockaddress(@indbrtest0, [[BB2:%.*]]), i8** [[P]], align 8
; CHECK-NEXT: call void @foo() ; CHECK-NEXT: call void @foo()
; CHECK-NEXT: [[T:%.*]] = load i8*, i8** [[Q:%.*]], align 8 ; CHECK-NEXT: [[T:%.*]] = load i8*, i8** [[Q:%.*]], align 8
; CHECK-NEXT: indirectbr i8* [[T]], [label [[BB0]], label [[BB1]], label %BB2] ; CHECK-NEXT: indirectbr i8* [[T]], [label [[BB0]], label [[BB1]], label %BB2]
; CHECK: BB0: ; CHECK: BB0:
; CHECK-NEXT: call void @A() ; CHECK-NEXT: call void @A()
; CHECK-NEXT: br label [[BB1]] ; CHECK-NEXT: br label [[BB1]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: BB1: ; CHECK: BB1:
; CHECK-NEXT: [[X:%.*]] = phi i32 [ 0, [[BB0]] ], [ 1, [[ENTRY:%.*]] ] ; CHECK-NEXT: [[X:%.*]] = phi i32 [ 0, [[BB0]] ], [ 1, [[ENTRY:%.*]] ]
; CHECK-NEXT: call void @B(i32 [[X]]) ; CHECK-NEXT: call void @B(i32 [[X]])
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: BB2: ; CHECK: BB2:
; CHECK-NEXT: call void @C() ; CHECK-NEXT: call void @C()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
store i8* blockaddress(@indbrtest0, %BB0), i8** %P store i8* blockaddress(@indbrtest0, %BB0), i8** %P
store i8* blockaddress(@indbrtest0, %BB1), i8** %P store i8* blockaddress(@indbrtest0, %BB1), i8** %P
store i8* blockaddress(@indbrtest0, %BB2), i8** %P store i8* blockaddress(@indbrtest0, %BB2), i8** %P
call void @foo() call void @foo()
%t = load i8*, i8** %Q %t = load i8*, i8** %Q
indirectbr i8* %t, [label %BB0, label %BB1, label %BB2, label %BB0, label %BB1, label %BB2] indirectbr i8* %t, [label %BB0, label %BB1, label %BB2, label %BB0, label %BB1, label %BB2]
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; SimplifyCFG should turn the indirectbr into a conditional branch on the ; SimplifyCFG should turn the indirectbr into a conditional branch on the
; condition of the select. ; condition of the select.
define void @indbrtest3(i1 %cond, i8* %address) nounwind { define void @indbrtest3(i1 %cond, i8* %address) nounwind {
; CHECK-LABEL: @indbrtest3( ; CHECK-LABEL: @indbrtest3(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[COND:%.*]], label [[L1:%.*]], label [[L2:%.*]] ; CHECK-NEXT: br i1 [[COND:%.*]], label [[L1:%.*]], label [[L2:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: L1: ; CHECK: L1:
; CHECK-NEXT: call void @A() ; CHECK-NEXT: call void @A()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: L2: ; CHECK: L2:
; CHECK-NEXT: call void @C() ; CHECK-NEXT: call void @C()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
%indirect.goto.dest = select i1 %cond, i8* blockaddress(@indbrtest3, %L1), i8* blockaddress(@indbrtest3, %L2) %indirect.goto.dest = select i1 %cond, i8* blockaddress(@indbrtest3, %L1), i8* blockaddress(@indbrtest3, %L2)
indirectbr i8* %indirect.goto.dest, [label %L1, label %L2, label %L3] indirectbr i8* %indirect.goto.dest, [label %L1, label %L2, label %L3]
L1: L1:
call void @A() call void @A()
ret void ret void
▲ Show 20 Lines • Show All 262 Lines • Show Last 20 Lines

llvm/test/Transforms/SimplifyCFG/invoke.ll

Show First 20 Lines • Show All 162 Lines • ▼ Show 20 Lineslpad:
tail call void @__cxa_call_unexpected(i8* %phi2) noreturn nounwind tail call void @__cxa_call_unexpected(i8* %phi2) noreturn nounwind
unreachable unreachable
} }
define void @f6() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { define void @f6() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
; CHECK-LABEL: @f6( ; CHECK-LABEL: @f6(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[FOO:%.*]] = invoke i32 @fn() ; CHECK-NEXT: [[FOO:%.*]] = invoke i32 @fn()
; CHECK-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]] ; CHECK-NEXT: to label [[COMMON_RET:%.*]] unwind label [[LPAD:%.*]]
; CHECK: invoke.cont2: ; CHECK: common.ret:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; CHECK: lpad: ; CHECK: lpad:
; CHECK-NEXT: [[TMP0:%.*]] = landingpad { i8*, i32 } ; CHECK-NEXT: [[TMP0:%.*]] = landingpad { i8*, i32 }
; CHECK-NEXT: cleanup ; CHECK-NEXT: cleanup
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
invoke void @purefn() invoke void @purefn()
to label %invoke.cont1 unwind label %lpad to label %invoke.cont1 unwind label %lpad
invoke.cont1: invoke.cont1:
%foo = invoke i32 @fn() %foo = invoke i32 @fn()
to label %invoke.cont2 unwind label %lpad to label %invoke.cont2 unwind label %lpad
Show All 12 Lines

llvm/test/Transforms/SimplifyCFG/pr39807.ll

; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -hoist-common-insts=true < %s | FileCheck %s ; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -hoist-common-insts=true < %s | FileCheck %s
declare void @personality() declare void @personality()
define void @test(i1 %b) personality void()* @personality !dbg !1 { define void @test(i1 %b) personality void()* @personality !dbg !1 {
; CHECK: invoke void @inlinable() ; CHECK: invoke void @inlinable()
; CHECK-NEXT: to label %success unwind label %failure, !dbg ![[DBGLOC:[0-9]+]] ; CHECK-NEXT: to label %common.ret unwind label %failure, !dbg ![[DBGLOC:[0-9]+]]
br i1 %b, label %if, label %else br i1 %b, label %if, label %else
if: if:
invoke void @inlinable() invoke void @inlinable()
to label %success unwind label %failure, !dbg !2 to label %success unwind label %failure, !dbg !2
else: else:
invoke void @inlinable() invoke void @inlinable()
Show All 28 Lines

llvm/test/Transforms/SimplifyCFG/pr46638.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s ; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s
define void @pr46638(i1 %c, i32 %x) { define void @pr46638(i1 %c, i32 %x) {
; CHECK-LABEL: @pr46638( ; CHECK-LABEL: @pr46638(
; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[X:%.*]], 0 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[X:%.*]], 0
; CHECK-NEXT: call void @llvm.assume(i1 [[CMP1]]) ; CHECK-NEXT: call void @llvm.assume(i1 [[CMP1]])
; CHECK-NEXT: br i1 [[C:%.*]], label [[TRUE2_CRITEDGE:%.*]], label [[FALSE1:%.*]] ; CHECK-NEXT: br i1 [[C:%.*]], label [[TRUE2_CRITEDGE:%.*]], label [[FALSE1:%.*]]
; CHECK: false1: ; CHECK: false1:
; CHECK-NEXT: call void @dummy(i32 1) ; CHECK-NEXT: call void @dummy(i32 1)
; CHECK-NEXT: [[CMP2:%.*]] = icmp sgt i32 [[X]], 0 ; CHECK-NEXT: [[CMP2:%.*]] = icmp sgt i32 [[X]], 0
; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[CMP2]] to i32 ; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[CMP2]] to i32
; CHECK-NEXT: call void @dummy(i32 [[EXT]]) ; CHECK-NEXT: call void @dummy(i32 [[EXT]])
; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; CHECK: true2.critedge: ; CHECK: true2.critedge:
; CHECK-NEXT: [[CMP2_C:%.*]] = icmp sgt i32 [[X]], 0 ; CHECK-NEXT: [[CMP2_C:%.*]] = icmp sgt i32 [[X]], 0
; CHECK-NEXT: [[EXT_C:%.*]] = zext i1 [[CMP2_C]] to i32 ; CHECK-NEXT: [[EXT_C:%.*]] = zext i1 [[CMP2_C]] to i32
; CHECK-NEXT: call void @dummy(i32 [[EXT_C]]) ; CHECK-NEXT: call void @dummy(i32 [[EXT_C]])
; CHECK-NEXT: call void @dummy(i32 2) ; CHECK-NEXT: call void @dummy(i32 2)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
%cmp1 = icmp slt i32 %x, 0 %cmp1 = icmp slt i32 %x, 0
call void @llvm.assume(i1 %cmp1) call void @llvm.assume(i1 %cmp1)
br i1 %c, label %true1, label %false1 br i1 %c, label %true1, label %false1
true1: true1:
%cmp2 = icmp sgt i32 %x, 0 %cmp2 = icmp sgt i32 %x, 0
%ext = zext i1 %cmp2 to i32 %ext = zext i1 %cmp2 to i32
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llvm/test/Transforms/SimplifyCFG/preserve-branchweights.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals
; RUN: opt -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S -o - < %s | FileCheck %s ; RUN: opt -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S -o - < %s | FileCheck %s
declare void @helper(i32) declare void @helper(i32)
;. ;.
; CHECK: @[[MAX_REGNO:[a-zA-Z0-9_$"\\.-]+]] = common global i32 0, align 4 ; CHECK: @[[MAX_REGNO:[a-zA-Z0-9_$"\\.-]+]] = common global i32 0, align 4
;. ;.
define void @test1(i1 %a, i1 %b) { define void @test1(i1 %a, i1 %b) {
; CHECK-LABEL: @test1( ; CHECK-LABEL: @test1(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_NOT:%.*]] = xor i1 [[A:%.*]], true ; CHECK-NEXT: [[A_NOT:%.*]] = xor i1 [[A:%.*]], true
; CHECK-NEXT: [[C:%.*]] = or i1 [[B:%.*]], false ; CHECK-NEXT: [[C:%.*]] = or i1 [[B:%.*]], false
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[A_NOT]], i1 [[C]], i1 false ; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[A_NOT]], i1 [[C]], i1 false
; CHECK-NEXT: br i1 [[OR_COND]], label [[Z:%.*]], label [[Y:%.*]], !prof [[PROF0:![0-9]+]] ; CHECK-NEXT: br i1 [[OR_COND]], label [[Z:%.*]], label [[Y:%.*]], !prof [[PROF0:![0-9]+]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: Y: ; CHECK: Y:
; CHECK-NEXT: call void @helper(i32 0) ; CHECK-NEXT: call void @helper(i32 0)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: Z: ; CHECK: Z:
; CHECK-NEXT: call void @helper(i32 1) ; CHECK-NEXT: call void @helper(i32 1)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
br i1 %a, label %Y, label %X, !prof !0 br i1 %a, label %Y, label %X, !prof !0
X: X:
%c = or i1 %b, false %c = or i1 %b, false
br i1 %c, label %Z, label %Y, !prof !1 br i1 %c, label %Z, label %Y, !prof !1
Show All 10 Lines
define void @fake_weights(i1 %a, i1 %b) { define void @fake_weights(i1 %a, i1 %b) {
; CHECK-LABEL: @fake_weights( ; CHECK-LABEL: @fake_weights(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[A_NOT:%.*]] = xor i1 [[A:%.*]], true ; CHECK-NEXT: [[A_NOT:%.*]] = xor i1 [[A:%.*]], true
; CHECK-NEXT: [[C:%.*]] = or i1 [[B:%.*]], false ; CHECK-NEXT: [[C:%.*]] = or i1 [[B:%.*]], false
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[A_NOT]], i1 [[C]], i1 false ; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[A_NOT]], i1 [[C]], i1 false
; CHECK-NEXT: br i1 [[OR_COND]], label [[Z:%.*]], label [[Y:%.*]], !prof [[PROF1:![0-9]+]] ; CHECK-NEXT: br i1 [[OR_COND]], label [[Z:%.*]], label [[Y:%.*]], !prof [[PROF1:![0-9]+]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: Y: ; CHECK: Y:
; CHECK-NEXT: call void @helper(i32 0) ; CHECK-NEXT: call void @helper(i32 0)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: Z: ; CHECK: Z:
; CHECK-NEXT: call void @helper(i32 1) ; CHECK-NEXT: call void @helper(i32 1)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
br i1 %a, label %Y, label %X, !prof !12 br i1 %a, label %Y, label %X, !prof !12
X: X:
%c = or i1 %b, false %c = or i1 %b, false
br i1 %c, label %Z, label %Y, !prof !1 br i1 %c, label %Z, label %Y, !prof !1
Y: Y:
call void @helper(i32 0) call void @helper(i32 0)
ret void ret void
Z: Z:
call void @helper(i32 1) call void @helper(i32 1)
ret void ret void
} }
define void @test2(i1 %a, i1 %b) { define void @test2(i1 %a, i1 %b) {
; CHECK-LABEL: @test2( ; CHECK-LABEL: @test2(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[C:%.*]] = or i1 [[B:%.*]], false ; CHECK-NEXT: [[C:%.*]] = or i1 [[B:%.*]], false
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[A:%.*]], i1 [[C]], i1 false ; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[A:%.*]], i1 [[C]], i1 false
; CHECK-NEXT: br i1 [[OR_COND]], label [[Z:%.*]], label [[Y:%.*]], !prof [[PROF2:![0-9]+]] ; CHECK-NEXT: br i1 [[OR_COND]], label [[Z:%.*]], label [[Y:%.*]], !prof [[PROF2:![0-9]+]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: Y: ; CHECK: Y:
; CHECK-NEXT: call void @helper(i32 0) ; CHECK-NEXT: call void @helper(i32 0)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: Z: ; CHECK: Z:
; CHECK-NEXT: call void @helper(i32 1) ; CHECK-NEXT: call void @helper(i32 1)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
br i1 %a, label %X, label %Y, !prof !1 br i1 %a, label %X, label %Y, !prof !1
X: X:
%c = or i1 %b, false %c = or i1 %b, false
br i1 %c, label %Z, label %Y, !prof !2 br i1 %c, label %Z, label %Y, !prof !2
Y: Y:
call void @helper(i32 0) call void @helper(i32 0)
ret void ret void
Z: Z:
call void @helper(i32 1) call void @helper(i32 1)
ret void ret void
} }
define void @test3(i1 %a, i1 %b) { define void @test3(i1 %a, i1 %b) {
; CHECK-LABEL: @test3( ; CHECK-LABEL: @test3(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[C:%.*]] = or i1 [[B:%.*]], false ; CHECK-NEXT: [[C:%.*]] = or i1 [[B:%.*]], false
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[A:%.*]], i1 [[C]], i1 false ; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[A:%.*]], i1 [[C]], i1 false
; CHECK-NEXT: br i1 [[OR_COND]], label [[Z:%.*]], label [[Y:%.*]], !prof [[PROF1]] ; CHECK-NEXT: br i1 [[OR_COND]], label [[Z:%.*]], label [[Y:%.*]], !prof [[PROF1]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: Y: ; CHECK: Y:
; CHECK-NEXT: call void @helper(i32 0) ; CHECK-NEXT: call void @helper(i32 0)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: Z: ; CHECK: Z:
; CHECK-NEXT: call void @helper(i32 1) ; CHECK-NEXT: call void @helper(i32 1)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
br i1 %a, label %X, label %Y, !prof !1 br i1 %a, label %X, label %Y, !prof !1
X: X:
%c = or i1 %b, false %c = or i1 %b, false
br i1 %c, label %Z, label %Y br i1 %c, label %Z, label %Y
Y: Y:
call void @helper(i32 0) call void @helper(i32 0)
ret void ret void
Z: Z:
call void @helper(i32 1) call void @helper(i32 1)
ret void ret void
} }
define void @test4(i1 %a, i1 %b) { define void @test4(i1 %a, i1 %b) {
; CHECK-LABEL: @test4( ; CHECK-LABEL: @test4(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[C:%.*]] = or i1 [[B:%.*]], false ; CHECK-NEXT: [[C:%.*]] = or i1 [[B:%.*]], false
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[A:%.*]], i1 [[C]], i1 false ; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[A:%.*]], i1 [[C]], i1 false
; CHECK-NEXT: br i1 [[OR_COND]], label [[Z:%.*]], label [[Y:%.*]], !prof [[PROF1]] ; CHECK-NEXT: br i1 [[OR_COND]], label [[Z:%.*]], label [[Y:%.*]], !prof [[PROF1]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: Y: ; CHECK: Y:
; CHECK-NEXT: call void @helper(i32 0) ; CHECK-NEXT: call void @helper(i32 0)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: Z: ; CHECK: Z:
; CHECK-NEXT: call void @helper(i32 1) ; CHECK-NEXT: call void @helper(i32 1)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
br i1 %a, label %X, label %Y br i1 %a, label %X, label %Y
X: X:
%c = or i1 %b, false %c = or i1 %b, false
br i1 %c, label %Z, label %Y, !prof !1 br i1 %c, label %Z, label %Y, !prof !1
▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines
;; This test is based on test1 but swapped the targets of the second branch. ;; This test is based on test1 but swapped the targets of the second branch.
define void @test1_swap(i1 %a, i1 %b) { define void @test1_swap(i1 %a, i1 %b) {
; CHECK-LABEL: @test1_swap( ; CHECK-LABEL: @test1_swap(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[C:%.*]] = or i1 [[B:%.*]], false ; CHECK-NEXT: [[C:%.*]] = or i1 [[B:%.*]], false
; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[C]] ; CHECK-NEXT: [[OR_COND:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[C]]
; CHECK-NEXT: br i1 [[OR_COND]], label [[Y:%.*]], label [[Z:%.*]], !prof [[PROF5:![0-9]+]] ; CHECK-NEXT: br i1 [[OR_COND]], label [[Y:%.*]], label [[Z:%.*]], !prof [[PROF5:![0-9]+]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: Y: ; CHECK: Y:
; CHECK-NEXT: call void @helper(i32 0) ; CHECK-NEXT: call void @helper(i32 0)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: Z: ; CHECK: Z:
; CHECK-NEXT: call void @helper(i32 1) ; CHECK-NEXT: call void @helper(i32 1)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
br i1 %a, label %Y, label %X, !prof !0 br i1 %a, label %Y, label %X, !prof !0
X: X:
%c = or i1 %b, false %c = or i1 %b, false
br i1 %c, label %Y, label %Z, !prof !1 br i1 %c, label %Y, label %Z, !prof !1
Y: Y:
call void @helper(i32 0) call void @helper(i32 0)
ret void ret void
Z: Z:
call void @helper(i32 1) call void @helper(i32 1)
ret void ret void
} }
define void @test7(i1 %a, i1 %b) { define void @test7(i1 %a, i1 %b) {
; CHECK-LABEL: @test7( ; CHECK-LABEL: @test7(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[C:%.*]] = or i1 [[B:%.*]], false ; CHECK-NEXT: [[C:%.*]] = or i1 [[B:%.*]], false
; CHECK-NEXT: [[BRMERGE:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[C]] ; CHECK-NEXT: [[BRMERGE:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[C]]
; CHECK-NEXT: br i1 [[BRMERGE]], label [[Y:%.*]], label [[Z:%.*]], !prof [[PROF6:![0-9]+]] ; CHECK-NEXT: br i1 [[BRMERGE]], label [[Y:%.*]], label [[Z:%.*]], !prof [[PROF6:![0-9]+]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: Y: ; CHECK: Y:
; CHECK-NEXT: call void @helper(i32 0) ; CHECK-NEXT: call void @helper(i32 0)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: Z: ; CHECK: Z:
; CHECK-NEXT: call void @helper(i32 1) ; CHECK-NEXT: call void @helper(i32 1)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
%c = or i1 %b, false %c = or i1 %b, false
br i1 %a, label %Y, label %X, !prof !0 br i1 %a, label %Y, label %X, !prof !0
X: X:
br i1 %c, label %Y, label %Z, !prof !6 br i1 %c, label %Y, label %Z, !prof !6
Y: Y:
call void @helper(i32 0) call void @helper(i32 0)
ret void ret void
Z: Z:
call void @helper(i32 1) call void @helper(i32 1)
ret void ret void
} }
; Test basic folding to a conditional branch. ; Test basic folding to a conditional branch.
define void @test8(i64 %x, i64 %y) nounwind { define void @test8(i64 %x, i64 %y) nounwind {
; CHECK-LABEL: @test8( ; CHECK-LABEL: @test8(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[LT:%.*]] = icmp slt i64 [[X:%.*]], [[Y:%.*]] ; CHECK-NEXT: [[LT:%.*]] = icmp slt i64 [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT: br i1 [[LT]], label [[A:%.*]], label [[B:%.*]], !prof [[PROF7:![0-9]+]] ; CHECK-NEXT: br i1 [[LT]], label [[A:%.*]], label [[B:%.*]], !prof [[PROF7:![0-9]+]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: a: ; CHECK: a:
; CHECK-NEXT: call void @helper(i32 0) #[[ATTR1:[0-9]+]] ; CHECK-NEXT: call void @helper(i32 0) #[[ATTR1:[0-9]+]]
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: b: ; CHECK: b:
; CHECK-NEXT: call void @helper(i32 1) #[[ATTR1]] ; CHECK-NEXT: call void @helper(i32 1) #[[ATTR1]]
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
%lt = icmp slt i64 %x, %y %lt = icmp slt i64 %x, %y
%qux = select i1 %lt, i32 0, i32 2 %qux = select i1 %lt, i32 0, i32 2
switch i32 %qux, label %bees [ switch i32 %qux, label %bees [
i32 0, label %a i32 0, label %a
i32 1, label %b i32 1, label %b
i32 2, label %b i32 2, label %b
Show All 15 Lines
; CHECK-LABEL: @test9( ; CHECK-LABEL: @test9(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: switch i32 [[X:%.*]], label [[BEES:%.*]] [ ; CHECK-NEXT: switch i32 [[X:%.*]], label [[BEES:%.*]] [
; CHECK-NEXT: i32 0, label [[A:%.*]] ; CHECK-NEXT: i32 0, label [[A:%.*]]
; CHECK-NEXT: i32 1, label [[END:%.*]] ; CHECK-NEXT: i32 1, label [[END:%.*]]
; CHECK-NEXT: i32 2, label [[END]] ; CHECK-NEXT: i32 2, label [[END]]
; CHECK-NEXT: i32 92, label [[END]] ; CHECK-NEXT: i32 92, label [[END]]
; CHECK-NEXT: ], !prof [[PROF8:![0-9]+]] ; CHECK-NEXT: ], !prof [[PROF8:![0-9]+]]
; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i1 [ [[RETA:%.*]], [[A]] ], [ [[RET:%.*]], [[END]] ]
; CHECK-NEXT: ret i1 [[COMMON_RET_OP]]
; CHECK: a: ; CHECK: a:
; CHECK-NEXT: call void @helper(i32 0) #[[ATTR1]] ; CHECK-NEXT: call void @helper(i32 0) #[[ATTR1]]
; CHECK-NEXT: [[RETA:%.*]] = icmp slt i32 [[X]], [[Y:%.*]] ; CHECK-NEXT: [[RETA]] = icmp slt i32 [[X]], [[Y:%.*]]
; CHECK-NEXT: ret i1 [[RETA]] ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: bees: ; CHECK: bees:
; CHECK-NEXT: br label [[END]] ; CHECK-NEXT: br label [[END]]
; CHECK: end: ; CHECK: end:
; CHECK-NEXT: [[RET:%.*]] = phi i1 [ true, [[ENTRY:%.*]] ], [ false, [[BEES]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ] ; CHECK-NEXT: [[RET]] = phi i1 [ true, [[ENTRY:%.*]] ], [ false, [[BEES]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ]
; CHECK-NEXT: call void @helper(i32 2) #[[ATTR1]] ; CHECK-NEXT: call void @helper(i32 2) #[[ATTR1]]
; CHECK-NEXT: ret i1 [[RET]] ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
switch i32 %x, label %bees [ switch i32 %x, label %bees [
i32 0, label %a i32 0, label %a
i32 1, label %end i32 1, label %end
i32 2, label %end i32 2, label %end
], !prof !7 ], !prof !7
Show All 13 Lines
} }
define void @test10(i32 %x) nounwind readnone ssp noredzone { define void @test10(i32 %x) nounwind readnone ssp noredzone {
; CHECK-LABEL: @test10( ; CHECK-LABEL: @test10(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[X_OFF:%.*]] = add i32 [[X:%.*]], -1 ; CHECK-NEXT: [[X_OFF:%.*]] = add i32 [[X:%.*]], -1
; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i32 [[X_OFF]], 3 ; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i32 [[X_OFF]], 3
; CHECK-NEXT: br i1 [[SWITCH]], label [[LOR_END:%.*]], label [[LOR_RHS:%.*]], !prof [[PROF9:![0-9]+]] ; CHECK-NEXT: br i1 [[SWITCH]], label [[LOR_END:%.*]], label [[LOR_RHS:%.*]], !prof [[PROF9:![0-9]+]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: lor.rhs: ; CHECK: lor.rhs:
; CHECK-NEXT: call void @helper(i32 1) #[[ATTR1]] ; CHECK-NEXT: call void @helper(i32 1) #[[ATTR1]]
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: lor.end: ; CHECK: lor.end:
; CHECK-NEXT: call void @helper(i32 0) #[[ATTR1]] ; CHECK-NEXT: call void @helper(i32 0) #[[ATTR1]]
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
switch i32 %x, label %lor.rhs [ switch i32 %x, label %lor.rhs [
i32 2, label %lor.end i32 2, label %lor.end
i32 1, label %lor.end i32 1, label %lor.end
i32 3, label %lor.end i32 3, label %lor.end
], !prof !7 ], !prof !7
lor.rhs: lor.rhs:
call void @helper(i32 1) nounwind call void @helper(i32 1) nounwind
ret void ret void
lor.end: lor.end:
call void @helper(i32 0) nounwind call void @helper(i32 0) nounwind
ret void ret void
} }
; Remove dead cases from the switch. ; Remove dead cases from the switch.
define void @test11(i32 %x) nounwind { define void @test11(i32 %x) nounwind {
; CHECK-LABEL: @test11( ; CHECK-LABEL: @test11(
; CHECK-NEXT: [[I:%.*]] = shl i32 [[X:%.*]], 1 ; CHECK-NEXT: [[I:%.*]] = shl i32 [[X:%.*]], 1
; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[I]], 24 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[I]], 24
; CHECK-NEXT: br i1 [[COND]], label [[C:%.*]], label [[A:%.*]], !prof [[PROF10:![0-9]+]] ; CHECK-NEXT: br i1 [[COND]], label [[C:%.*]], label [[A:%.*]], !prof [[PROF10:![0-9]+]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: a: ; CHECK: a:
; CHECK-NEXT: call void @helper(i32 0) #[[ATTR1]] ; CHECK-NEXT: call void @helper(i32 0) #[[ATTR1]]
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: c: ; CHECK: c:
; CHECK-NEXT: call void @helper(i32 2) #[[ATTR1]] ; CHECK-NEXT: call void @helper(i32 2) #[[ATTR1]]
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
%i = shl i32 %x, 1 %i = shl i32 %x, 1
switch i32 %i, label %a [ switch i32 %i, label %a [
i32 21, label %b i32 21, label %b
i32 24, label %c i32 24, label %c
], !prof !8 ], !prof !8
a: a:
▲ Show 20 Lines • Show All 668 Lines • Show Last 20 Lines

llvm/test/Transforms/SimplifyCFG/switch-dead-default.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt %s -S -passes='simplify-cfg<switch-to-lookup>' -simplifycfg-require-and-preserve-domtree=1 | FileCheck %s ; RUN: opt %s -S -passes='simplify-cfg<switch-to-lookup>' -simplifycfg-require-and-preserve-domtree=1 | FileCheck %s
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
declare void @foo(i32) declare void @foo(i32)
define void @test(i1 %a) { define void @test(i1 %a) {
; CHECK-LABEL: @test( ; CHECK-LABEL: @test(
; CHECK-NEXT: [[A_OFF:%.*]] = add i1 [[A:%.*]], true ; CHECK-NEXT: [[A_OFF:%.*]] = add i1 [[A:%.*]], true
; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i1 [[A_OFF]], true ; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i1 [[A_OFF]], true
; CHECK-NEXT: br i1 [[SWITCH]], label [[TRUE:%.*]], label [[FALSE:%.*]] ; CHECK-NEXT: br i1 [[SWITCH]], label [[TRUE:%.*]], label [[FALSE:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: true: ; CHECK: true:
; CHECK-NEXT: call void @foo(i32 1) ; CHECK-NEXT: call void @foo(i32 1)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: false: ; CHECK: false:
; CHECK-NEXT: call void @foo(i32 3) ; CHECK-NEXT: call void @foo(i32 3)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
switch i1 %a, label %default [i1 1, label %true switch i1 %a, label %default [i1 1, label %true
i1 0, label %false] i1 0, label %false]
true: true:
call void @foo(i32 1) call void @foo(i32 1)
ret void ret void
false: false:
call void @foo(i32 3) call void @foo(i32 3)
ret void ret void
default: default:
call void @foo(i32 2) call void @foo(i32 2)
ret void ret void
} }
define void @test2(i2 %a) { define void @test2(i2 %a) {
; CHECK-LABEL: @test2( ; CHECK-LABEL: @test2(
; CHECK-NEXT: switch i2 [[A:%.*]], label [[DEFAULT1:%.*]] [ ; CHECK-NEXT: switch i2 [[A:%.*]], label [[DEFAULT1:%.*]] [
; CHECK-NEXT: i2 0, label [[CASE0:%.*]] ; CHECK-NEXT: i2 0, label [[CASE0:%.*]]
; CHECK-NEXT: i2 1, label [[CASE1:%.*]] ; CHECK-NEXT: i2 1, label [[CASE1:%.*]]
; CHECK-NEXT: i2 -2, label [[CASE2:%.*]] ; CHECK-NEXT: i2 -2, label [[CASE2:%.*]]
; CHECK-NEXT: i2 -1, label [[CASE3:%.*]] ; CHECK-NEXT: i2 -1, label [[CASE3:%.*]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: case0: ; CHECK: case0:
; CHECK-NEXT: call void @foo(i32 0) ; CHECK-NEXT: call void @foo(i32 0)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: case1: ; CHECK: case1:
; CHECK-NEXT: call void @foo(i32 1) ; CHECK-NEXT: call void @foo(i32 1)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: case2: ; CHECK: case2:
; CHECK-NEXT: call void @foo(i32 2) ; CHECK-NEXT: call void @foo(i32 2)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: case3: ; CHECK: case3:
; CHECK-NEXT: call void @foo(i32 3) ; CHECK-NEXT: call void @foo(i32 3)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: default1: ; CHECK: default1:
; CHECK-NEXT: unreachable ; CHECK-NEXT: unreachable
; ;
switch i2 %a, label %default [i2 0, label %case0 switch i2 %a, label %default [i2 0, label %case0
i2 1, label %case1 i2 1, label %case1
i2 2, label %case2 i2 2, label %case2
i2 3, label %case3] i2 3, label %case3]
case0: case0:
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; but that's about it ; but that's about it
define void @test3(i2 %a) { define void @test3(i2 %a) {
; CHECK-LABEL: @test3( ; CHECK-LABEL: @test3(
; CHECK-NEXT: switch i2 [[A:%.*]], label [[DEFAULT:%.*]] [ ; CHECK-NEXT: switch i2 [[A:%.*]], label [[DEFAULT:%.*]] [
; CHECK-NEXT: i2 0, label [[CASE0:%.*]] ; CHECK-NEXT: i2 0, label [[CASE0:%.*]]
; CHECK-NEXT: i2 1, label [[CASE1:%.*]] ; CHECK-NEXT: i2 1, label [[CASE1:%.*]]
; CHECK-NEXT: i2 -2, label [[CASE2:%.*]] ; CHECK-NEXT: i2 -2, label [[CASE2:%.*]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: case0: ; CHECK: case0:
; CHECK-NEXT: call void @foo(i32 0) ; CHECK-NEXT: call void @foo(i32 0)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: case1: ; CHECK: case1:
; CHECK-NEXT: call void @foo(i32 1) ; CHECK-NEXT: call void @foo(i32 1)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: case2: ; CHECK: case2:
; CHECK-NEXT: call void @foo(i32 2) ; CHECK-NEXT: call void @foo(i32 2)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: default: ; CHECK: default:
; CHECK-NEXT: call void @foo(i32 3) ; CHECK-NEXT: call void @foo(i32 3)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
switch i2 %a, label %default [i2 0, label %case0 switch i2 %a, label %default [i2 0, label %case0
i2 1, label %case1 i2 1, label %case1
i2 2, label %case2] i2 2, label %case2]
case0: case0:
call void @foo(i32 0) call void @foo(i32 0)
ret void ret void
Show All 11 Lines
; Negative test - check for possible overflow when computing ; Negative test - check for possible overflow when computing
; number of possible cases. ; number of possible cases.
define void @test4(i128 %a) { define void @test4(i128 %a) {
; CHECK-LABEL: @test4( ; CHECK-LABEL: @test4(
; CHECK-NEXT: switch i128 [[A:%.*]], label [[DEFAULT:%.*]] [ ; CHECK-NEXT: switch i128 [[A:%.*]], label [[DEFAULT:%.*]] [
; CHECK-NEXT: i128 0, label [[CASE0:%.*]] ; CHECK-NEXT: i128 0, label [[CASE0:%.*]]
; CHECK-NEXT: i128 1, label [[CASE1:%.*]] ; CHECK-NEXT: i128 1, label [[CASE1:%.*]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: case0: ; CHECK: case0:
; CHECK-NEXT: call void @foo(i32 0) ; CHECK-NEXT: call void @foo(i32 0)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: case1: ; CHECK: case1:
; CHECK-NEXT: call void @foo(i32 1) ; CHECK-NEXT: call void @foo(i32 1)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: default: ; CHECK: default:
; CHECK-NEXT: call void @foo(i32 2) ; CHECK-NEXT: call void @foo(i32 2)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
switch i128 %a, label %default [i128 0, label %case0 switch i128 %a, label %default [i128 0, label %case0
i128 1, label %case1] i128 1, label %case1]
case0: case0:
call void @foo(i32 0) call void @foo(i32 0)
ret void ret void
case1: case1:
call void @foo(i32 1) call void @foo(i32 1)
ret void ret void
default: default:
call void @foo(i32 2) call void @foo(i32 2)
ret void ret void
} }
; All but one bit known zero ; All but one bit known zero
define void @test5(i8 %a) { define void @test5(i8 %a) {
; CHECK-LABEL: @test5( ; CHECK-LABEL: @test5(
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 [[A:%.*]], 2 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 [[A:%.*]], 2
; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]]) ; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])
; CHECK-NEXT: [[A_OFF:%.*]] = add i8 [[A]], -1 ; CHECK-NEXT: [[A_OFF:%.*]] = add i8 [[A]], -1
; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i8 [[A_OFF]], 1 ; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i8 [[A_OFF]], 1
; CHECK-NEXT: br i1 [[SWITCH]], label [[TRUE:%.*]], label [[FALSE:%.*]] ; CHECK-NEXT: br i1 [[SWITCH]], label [[TRUE:%.*]], label [[FALSE:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: true: ; CHECK: true:
; CHECK-NEXT: call void @foo(i32 1) ; CHECK-NEXT: call void @foo(i32 1)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: false: ; CHECK: false:
; CHECK-NEXT: call void @foo(i32 3) ; CHECK-NEXT: call void @foo(i32 3)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
%cmp = icmp ult i8 %a, 2 %cmp = icmp ult i8 %a, 2
call void @llvm.assume(i1 %cmp) call void @llvm.assume(i1 %cmp)
switch i8 %a, label %default [i8 1, label %true switch i8 %a, label %default [i8 1, label %true
i8 0, label %false] i8 0, label %false]
true: true:
call void @foo(i32 1) call void @foo(i32 1)
ret void ret void
Show All 9 Lines
define void @test6(i8 %a) { define void @test6(i8 %a) {
; CHECK-LABEL: @test6( ; CHECK-LABEL: @test6(
; CHECK-NEXT: [[AND:%.*]] = and i8 [[A:%.*]], -2 ; CHECK-NEXT: [[AND:%.*]] = and i8 [[A:%.*]], -2
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[AND]], -2 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[AND]], -2
; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]]) ; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])
; CHECK-NEXT: [[A_OFF:%.*]] = add i8 [[A]], 1 ; CHECK-NEXT: [[A_OFF:%.*]] = add i8 [[A]], 1
; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i8 [[A_OFF]], 1 ; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i8 [[A_OFF]], 1
; CHECK-NEXT: br i1 [[SWITCH]], label [[TRUE:%.*]], label [[FALSE:%.*]] ; CHECK-NEXT: br i1 [[SWITCH]], label [[TRUE:%.*]], label [[FALSE:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: true: ; CHECK: true:
; CHECK-NEXT: call void @foo(i32 1) ; CHECK-NEXT: call void @foo(i32 1)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: false: ; CHECK: false:
; CHECK-NEXT: call void @foo(i32 3) ; CHECK-NEXT: call void @foo(i32 3)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
%and = and i8 %a, 254 %and = and i8 %a, 254
%cmp = icmp eq i8 %and, 254 %cmp = icmp eq i8 %and, 254
call void @llvm.assume(i1 %cmp) call void @llvm.assume(i1 %cmp)
switch i8 %a, label %default [i8 255, label %true switch i8 %a, label %default [i8 255, label %true
i8 254, label %false] i8 254, label %false]
true: true:
call void @foo(i32 1) call void @foo(i32 1)
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define void @test7(i8 %a) { define void @test7(i8 %a) {
; CHECK-LABEL: @test7( ; CHECK-LABEL: @test7(
; CHECK-NEXT: [[AND:%.*]] = and i8 [[A:%.*]], -2 ; CHECK-NEXT: [[AND:%.*]] = and i8 [[A:%.*]], -2
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[AND]], -2 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[AND]], -2
; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]]) ; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]])
; CHECK-NEXT: [[A_OFF:%.*]] = add i8 [[A]], 1 ; CHECK-NEXT: [[A_OFF:%.*]] = add i8 [[A]], 1
; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i8 [[A_OFF]], 1 ; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i8 [[A_OFF]], 1
; CHECK-NEXT: br i1 [[SWITCH]], label [[TRUE:%.*]], label [[FALSE:%.*]] ; CHECK-NEXT: br i1 [[SWITCH]], label [[TRUE:%.*]], label [[FALSE:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: true: ; CHECK: true:
; CHECK-NEXT: call void @foo(i32 1) ; CHECK-NEXT: call void @foo(i32 1)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: false: ; CHECK: false:
; CHECK-NEXT: call void @foo(i32 3) ; CHECK-NEXT: call void @foo(i32 3)
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
%and = and i8 %a, 254 %and = and i8 %a, 254
%cmp = icmp eq i8 %and, 254 %cmp = icmp eq i8 %and, 254
call void @llvm.assume(i1 %cmp) call void @llvm.assume(i1 %cmp)
switch i8 %a, label %default [i8 255, label %true switch i8 %a, label %default [i8 255, label %true
i8 254, label %false i8 254, label %false
i8 0, label %also_dead] i8 0, label %also_dead]
true: true:
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llvm/test/Transforms/SimplifyCFG/switch-on-const-select.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s ; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s
; Test basic folding to a conditional branch. ; Test basic folding to a conditional branch.
define i32 @foo(i64 %x, i64 %y) nounwind { define i32 @foo(i64 %x, i64 %y) nounwind {
; CHECK-LABEL: @foo( ; CHECK-LABEL: @foo(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[EQ:%.*]] = icmp eq i64 [[X:%.*]], [[Y:%.*]] ; CHECK-NEXT: [[EQ:%.*]] = icmp eq i64 [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT: br i1 [[EQ]], label [[B:%.*]], label [[SWITCH:%.*]] ; CHECK-NEXT: br i1 [[EQ]], label [[B:%.*]], label [[SWITCH:%.*]]
; CHECK: switch: ; CHECK: switch:
; CHECK-NEXT: [[LT:%.*]] = icmp slt i64 [[X]], [[Y]] ; CHECK-NEXT: [[LT:%.*]] = icmp slt i64 [[X]], [[Y]]
; CHECK-NEXT: br i1 [[LT]], label [[A:%.*]], label [[B]] ; CHECK-NEXT: br i1 [[LT]], label [[A:%.*]], label [[B]]
; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ 1, [[A]] ], [ [[RETVAL:%.*]], [[B]] ]
; CHECK-NEXT: ret i32 [[COMMON_RET_OP]]
; CHECK: a: ; CHECK: a:
; CHECK-NEXT: tail call void @bees.a() #[[ATTR0:[0-9]+]] ; CHECK-NEXT: tail call void @bees.a() #[[ATTR0:[0-9]+]]
; CHECK-NEXT: ret i32 1 ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: b: ; CHECK: b:
; CHECK-NEXT: [[RETVAL:%.*]] = phi i32 [ 0, [[SWITCH]] ], [ 2, [[ENTRY:%.*]] ] ; CHECK-NEXT: [[RETVAL]] = phi i32 [ 0, [[SWITCH]] ], [ 2, [[ENTRY:%.*]] ]
; CHECK-NEXT: tail call void @bees.b() #[[ATTR0]] ; CHECK-NEXT: tail call void @bees.b() #[[ATTR0]]
; CHECK-NEXT: ret i32 [[RETVAL]] ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
%eq = icmp eq i64 %x, %y %eq = icmp eq i64 %x, %y
br i1 %eq, label %b, label %switch br i1 %eq, label %b, label %switch
switch: switch:
%lt = icmp slt i64 %x, %y %lt = icmp slt i64 %x, %y
%qux = select i1 %lt, i32 0, i32 2 %qux = select i1 %lt, i32 0, i32 2
switch i32 %qux, label %bees [ switch i32 %qux, label %bees [
▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
; A final test, for phi node munging. ; A final test, for phi node munging.
define i32 @xyzzy(i64 %x, i64 %y) { define i32 @xyzzy(i64 %x, i64 %y) {
; CHECK-LABEL: @xyzzy( ; CHECK-LABEL: @xyzzy(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[EQ:%.*]] = icmp eq i64 [[X:%.*]], [[Y:%.*]] ; CHECK-NEXT: [[EQ:%.*]] = icmp eq i64 [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT: [[LT:%.*]] = icmp slt i64 [[X]], [[Y]] ; CHECK-NEXT: [[LT:%.*]] = icmp slt i64 [[X]], [[Y]]
; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[LT]], i32 -1, i32 1 ; CHECK-NEXT: [[SPEC_SELECT:%.*]] = select i1 [[LT]], i32 -1, i32 1
; CHECK-NEXT: [[VAL:%.*]] = select i1 [[EQ]], i32 0, i32 [[SPEC_SELECT]] ; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = select i1 [[EQ]], i32 0, i32 [[SPEC_SELECT]]
; CHECK-NEXT: ret i32 [[VAL]] ; CHECK-NEXT: ret i32 [[COMMON_RET_OP]]
; ;
entry: entry:
%eq = icmp eq i64 %x, %y %eq = icmp eq i64 %x, %y
br i1 %eq, label %r, label %cont br i1 %eq, label %r, label %cont
cont: cont:
%lt = icmp slt i64 %x, %y %lt = icmp slt i64 %x, %y
%qux = select i1 %lt, i32 0, i32 2 %qux = select i1 %lt, i32 0, i32 2
switch i32 %qux, label %bees [ switch i32 %qux, label %bees [
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llvm/test/Transforms/SimplifyCFG/switch-range-to-icmp.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s ; RUN: opt %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s
declare i32 @f(i32) declare i32 @f(i32)
define i32 @basic(i32 %x) { define i32 @basic(i32 %x) {
; CHECK-LABEL: @basic( ; CHECK-LABEL: @basic(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[X_OFF:%.*]] = add i32 [[X:%.*]], -5 ; CHECK-NEXT: [[X_OFF:%.*]] = add i32 [[X:%.*]], -5
; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i32 [[X_OFF]], 3 ; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i32 [[X_OFF]], 3
; CHECK-NEXT: br i1 [[SWITCH]], label [[A:%.*]], label [[DEFAULT:%.*]] ; CHECK-NEXT: br i1 [[SWITCH]], label [[A:%.*]], label [[DEFAULT:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ [[TMP0:%.*]], [[DEFAULT]] ], [ [[TMP1:%.*]], [[A]] ]
; CHECK-NEXT: ret i32 [[COMMON_RET_OP]]
; CHECK: default: ; CHECK: default:
; CHECK-NEXT: [[TMP0:%.*]] = call i32 @f(i32 0) ; CHECK-NEXT: [[TMP0]] = call i32 @f(i32 0)
; CHECK-NEXT: ret i32 [[TMP0]] ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: a: ; CHECK: a:
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @f(i32 1) ; CHECK-NEXT: [[TMP1]] = call i32 @f(i32 1)
; CHECK-NEXT: ret i32 [[TMP1]] ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
switch i32 %x, label %default [ switch i32 %x, label %default [
i32 5, label %a i32 5, label %a
i32 6, label %a i32 6, label %a
i32 7, label %a i32 7, label %a
] ]
default: default:
%0 = call i32 @f(i32 0) %0 = call i32 @f(i32 0)
ret i32 %0 ret i32 %0
a: a:
%1 = call i32 @f(i32 1) %1 = call i32 @f(i32 1)
ret i32 %1 ret i32 %1
} }
define i32 @unreachable(i32 %x) { define i32 @unreachable(i32 %x) {
; CHECK-LABEL: @unreachable( ; CHECK-LABEL: @unreachable(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[X_OFF:%.*]] = add i32 [[X:%.*]], -5 ; CHECK-NEXT: [[X_OFF:%.*]] = add i32 [[X:%.*]], -5
; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i32 [[X_OFF]], 3 ; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i32 [[X_OFF]], 3
; CHECK-NEXT: br i1 [[SWITCH]], label [[A:%.*]], label [[B:%.*]] ; CHECK-NEXT: br i1 [[SWITCH]], label [[A:%.*]], label [[B:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ [[TMP0:%.*]], [[A]] ], [ [[TMP1:%.*]], [[B]] ]
; CHECK-NEXT: ret i32 [[COMMON_RET_OP]]
; CHECK: a: ; CHECK: a:
; CHECK-NEXT: [[TMP0:%.*]] = call i32 @f(i32 0) ; CHECK-NEXT: [[TMP0]] = call i32 @f(i32 0)
; CHECK-NEXT: ret i32 [[TMP0]] ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: b: ; CHECK: b:
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @f(i32 1) ; CHECK-NEXT: [[TMP1]] = call i32 @f(i32 1)
; CHECK-NEXT: ret i32 [[TMP1]] ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
switch i32 %x, label %unreachable [ switch i32 %x, label %unreachable [
i32 5, label %a i32 5, label %a
i32 6, label %a i32 6, label %a
i32 7, label %a i32 7, label %a
i32 10, label %b i32 10, label %b
Show All 13 Lines
define i32 @unreachable2(i32 %x) { define i32 @unreachable2(i32 %x) {
; CHECK-LABEL: @unreachable2( ; CHECK-LABEL: @unreachable2(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[X_OFF:%.*]] = add i32 [[X:%.*]], -5 ; CHECK-NEXT: [[X_OFF:%.*]] = add i32 [[X:%.*]], -5
; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i32 [[X_OFF]], 3 ; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i32 [[X_OFF]], 3
; CHECK-NEXT: br i1 [[SWITCH]], label [[A:%.*]], label [[B:%.*]] ; CHECK-NEXT: br i1 [[SWITCH]], label [[A:%.*]], label [[B:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ [[TMP0:%.*]], [[A]] ], [ [[TMP1:%.*]], [[B]] ]
; CHECK-NEXT: ret i32 [[COMMON_RET_OP]]
; CHECK: a: ; CHECK: a:
; CHECK-NEXT: [[TMP0:%.*]] = call i32 @f(i32 0) ; CHECK-NEXT: [[TMP0]] = call i32 @f(i32 0)
; CHECK-NEXT: ret i32 [[TMP0]] ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: b: ; CHECK: b:
; CHECK-NEXT: [[TMP1:%.*]] = call i32 @f(i32 1) ; CHECK-NEXT: [[TMP1]] = call i32 @f(i32 1)
; CHECK-NEXT: ret i32 [[TMP1]] ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
entry: entry:
; Note: folding the most popular case destination into the default ; Note: folding the most popular case destination into the default
; would prevent switch-to-icmp here. ; would prevent switch-to-icmp here.
switch i32 %x, label %unreachable [ switch i32 %x, label %unreachable [
i32 5, label %a i32 5, label %a
i32 6, label %a i32 6, label %a
▲ Show 20 Lines • Show All 51 Lines • Show Last 20 Lines

llvm/test/Transforms/SimplifyCFG/switch_create-custom-dl.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s ; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s
target datalayout="p:40:64:64:32" target datalayout="p:40:64:64:32"
declare void @foo1() declare void @foo1()
declare void @foo2() declare void @foo2()
define void @test1(i32 %V) { define void @test1(i32 %V) {
; CHECK-LABEL: @test1( ; CHECK-LABEL: @test1(
; CHECK-NEXT: switch i32 [[V:%.*]], label [[F:%.*]] [ ; CHECK-NEXT: switch i32 [[V:%.*]], label [[F:%.*]] [
; CHECK-NEXT: i32 17, label [[T:%.*]] ; CHECK-NEXT: i32 17, label [[T:%.*]]
; CHECK-NEXT: i32 4, label [[T]] ; CHECK-NEXT: i32 4, label [[T]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: T: ; CHECK: T:
; CHECK-NEXT: call void @foo1() ; CHECK-NEXT: call void @foo1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: F: ; CHECK: F:
; CHECK-NEXT: call void @foo2() ; CHECK-NEXT: call void @foo2()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
%C1 = icmp eq i32 %V, 4 ; <i1> [#uses=1] %C1 = icmp eq i32 %V, 4 ; <i1> [#uses=1]
%C2 = icmp eq i32 %V, 17 ; <i1> [#uses=1] %C2 = icmp eq i32 %V, 17 ; <i1> [#uses=1]
%CN = or i1 %C1, %C2 ; <i1> [#uses=1] %CN = or i1 %C1, %C2 ; <i1> [#uses=1]
br i1 %CN, label %T, label %F br i1 %CN, label %T, label %F
T: ; preds = %0 T: ; preds = %0
call void @foo1( ) call void @foo1( )
ret void ret void
F: ; preds = %0 F: ; preds = %0
call void @foo2( ) call void @foo2( )
ret void ret void
} }
define void @test1_ptr(i32* %V) { define void @test1_ptr(i32* %V) {
; CHECK-LABEL: @test1_ptr( ; CHECK-LABEL: @test1_ptr(
; CHECK-NEXT: [[MAGICPTR:%.*]] = ptrtoint i32* [[V:%.*]] to i40 ; CHECK-NEXT: [[MAGICPTR:%.*]] = ptrtoint i32* [[V:%.*]] to i40
; CHECK-NEXT: switch i40 [[MAGICPTR]], label [[F:%.*]] [ ; CHECK-NEXT: switch i40 [[MAGICPTR]], label [[F:%.*]] [
; CHECK-NEXT: i40 17, label [[T:%.*]] ; CHECK-NEXT: i40 17, label [[T:%.*]]
; CHECK-NEXT: i40 4, label [[T]] ; CHECK-NEXT: i40 4, label [[T]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: T: ; CHECK: T:
; CHECK-NEXT: call void @foo1() ; CHECK-NEXT: call void @foo1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: F: ; CHECK: F:
; CHECK-NEXT: call void @foo2() ; CHECK-NEXT: call void @foo2()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
%C1 = icmp eq i32* %V, inttoptr (i32 4 to i32*) %C1 = icmp eq i32* %V, inttoptr (i32 4 to i32*)
%C2 = icmp eq i32* %V, inttoptr (i32 17 to i32*) %C2 = icmp eq i32* %V, inttoptr (i32 17 to i32*)
%CN = or i1 %C1, %C2 ; <i1> [#uses=1] %CN = or i1 %C1, %C2 ; <i1> [#uses=1]
br i1 %CN, label %T, label %F br i1 %CN, label %T, label %F
T: ; preds = %0 T: ; preds = %0
call void @foo1( ) call void @foo1( )
ret void ret void
F: ; preds = %0 F: ; preds = %0
call void @foo2( ) call void @foo2( )
ret void ret void
} }
define void @test1_ptr_as1(i32 addrspace(1)* %V) { define void @test1_ptr_as1(i32 addrspace(1)* %V) {
; CHECK-LABEL: @test1_ptr_as1( ; CHECK-LABEL: @test1_ptr_as1(
; CHECK-NEXT: [[MAGICPTR:%.*]] = ptrtoint i32 addrspace(1)* [[V:%.*]] to i40 ; CHECK-NEXT: [[MAGICPTR:%.*]] = ptrtoint i32 addrspace(1)* [[V:%.*]] to i40
; CHECK-NEXT: switch i40 [[MAGICPTR]], label [[F:%.*]] [ ; CHECK-NEXT: switch i40 [[MAGICPTR]], label [[F:%.*]] [
; CHECK-NEXT: i40 17, label [[T:%.*]] ; CHECK-NEXT: i40 17, label [[T:%.*]]
; CHECK-NEXT: i40 4, label [[T]] ; CHECK-NEXT: i40 4, label [[T]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: T: ; CHECK: T:
; CHECK-NEXT: call void @foo1() ; CHECK-NEXT: call void @foo1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: F: ; CHECK: F:
; CHECK-NEXT: call void @foo2() ; CHECK-NEXT: call void @foo2()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
%C1 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 4 to i32 addrspace(1)*) %C1 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 4 to i32 addrspace(1)*)
%C2 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 17 to i32 addrspace(1)*) %C2 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 17 to i32 addrspace(1)*)
%CN = or i1 %C1, %C2 ; <i1> [#uses=1] %CN = or i1 %C1, %C2 ; <i1> [#uses=1]
br i1 %CN, label %T, label %F br i1 %CN, label %T, label %F
T: ; preds = %0 T: ; preds = %0
call void @foo1( ) call void @foo1( )
ret void ret void
F: ; preds = %0 F: ; preds = %0
call void @foo2( ) call void @foo2( )
ret void ret void
} }
define void @test2(i32 %V) { define void @test2(i32 %V) {
; CHECK-LABEL: @test2( ; CHECK-LABEL: @test2(
; CHECK-NEXT: switch i32 [[V:%.*]], label [[T:%.*]] [ ; CHECK-NEXT: switch i32 [[V:%.*]], label [[T:%.*]] [
; CHECK-NEXT: i32 17, label [[F:%.*]] ; CHECK-NEXT: i32 17, label [[F:%.*]]
; CHECK-NEXT: i32 4, label [[F]] ; CHECK-NEXT: i32 4, label [[F]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: T: ; CHECK: T:
; CHECK-NEXT: call void @foo1() ; CHECK-NEXT: call void @foo1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: F: ; CHECK: F:
; CHECK-NEXT: call void @foo2() ; CHECK-NEXT: call void @foo2()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
%C1 = icmp ne i32 %V, 4 ; <i1> [#uses=1] %C1 = icmp ne i32 %V, 4 ; <i1> [#uses=1]
%C2 = icmp ne i32 %V, 17 ; <i1> [#uses=1] %C2 = icmp ne i32 %V, 17 ; <i1> [#uses=1]
%CN = and i1 %C1, %C2 ; <i1> [#uses=1] %CN = and i1 %C1, %C2 ; <i1> [#uses=1]
br i1 %CN, label %T, label %F br i1 %CN, label %T, label %F
T: ; preds = %0 T: ; preds = %0
call void @foo1( ) call void @foo1( )
ret void ret void
F: ; preds = %0 F: ; preds = %0
call void @foo2( ) call void @foo2( )
ret void ret void
} }
define void @test3(i32 %V) { define void @test3(i32 %V) {
; CHECK-LABEL: @test3( ; CHECK-LABEL: @test3(
; CHECK-NEXT: switch i32 [[V:%.*]], label [[F:%.*]] [ ; CHECK-NEXT: switch i32 [[V:%.*]], label [[F:%.*]] [
; CHECK-NEXT: i32 4, label [[T:%.*]] ; CHECK-NEXT: i32 4, label [[T:%.*]]
; CHECK-NEXT: i32 17, label [[T]] ; CHECK-NEXT: i32 17, label [[T]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: T: ; CHECK: T:
; CHECK-NEXT: call void @foo1() ; CHECK-NEXT: call void @foo1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: F: ; CHECK: F:
; CHECK-NEXT: call void @foo2() ; CHECK-NEXT: call void @foo2()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
%C1 = icmp eq i32 %V, 4 ; <i1> [#uses=1] %C1 = icmp eq i32 %V, 4 ; <i1> [#uses=1]
br i1 %C1, label %T, label %N br i1 %C1, label %T, label %N
N: ; preds = %0 N: ; preds = %0
%C2 = icmp eq i32 %V, 17 ; <i1> [#uses=1] %C2 = icmp eq i32 %V, 17 ; <i1> [#uses=1]
br i1 %C2, label %T, label %F br i1 %C2, label %T, label %F
T: ; preds = %N, %0 T: ; preds = %N, %0
call void @foo1( ) call void @foo1( )
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} }
define void @test7(i8 zeroext %c, i32 %x) nounwind ssp noredzone { define void @test7(i8 zeroext %c, i32 %x) nounwind ssp noredzone {
; CHECK-LABEL: @test7( ; CHECK-LABEL: @test7(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 32 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 32
; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[SWITCH_EARLY_TEST:%.*]] ; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[SWITCH_EARLY_TEST:%.*]]
; CHECK: switch.early.test: ; CHECK: switch.early.test:
; CHECK-NEXT: switch i8 [[C:%.*]], label [[IF_END:%.*]] [ ; CHECK-NEXT: switch i8 [[C:%.*]], label [[COMMON_RET:%.*]] [
; CHECK-NEXT: i8 99, label [[IF_THEN]] ; CHECK-NEXT: i8 99, label [[IF_THEN]]
; CHECK-NEXT: i8 97, label [[IF_THEN]] ; CHECK-NEXT: i8 97, label [[IF_THEN]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: if.then: ; CHECK: if.then:
; CHECK-NEXT: tail call void @foo1() #[[ATTR2:[0-9]+]] ; CHECK-NEXT: tail call void @foo1() #[[ATTR2:[0-9]+]]
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: if.end:
; CHECK-NEXT: ret void
; ;
entry: entry:
%cmp = icmp ult i32 %x, 32 %cmp = icmp ult i32 %x, 32
%cmp4 = icmp eq i8 %c, 97 %cmp4 = icmp eq i8 %c, 97
%or.cond = or i1 %cmp, %cmp4 %or.cond = or i1 %cmp, %cmp4
%cmp9 = icmp eq i8 %c, 99 %cmp9 = icmp eq i8 %c, 99
%or.cond11 = or i1 %or.cond, %cmp9 %or.cond11 = or i1 %or.cond, %cmp9
br i1 %or.cond11, label %if.then, label %if.end br i1 %or.cond11, label %if.then, label %if.end
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define i32 @test8(i8 zeroext %c, i32 %x, i1 %C) nounwind ssp noredzone { define i32 @test8(i8 zeroext %c, i32 %x, i1 %C) nounwind ssp noredzone {
; CHECK-LABEL: @test8( ; CHECK-LABEL: @test8(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[C:%.*]], label [[N:%.*]], label [[IF_THEN:%.*]] ; CHECK-NEXT: br i1 [[C:%.*]], label [[N:%.*]], label [[IF_THEN:%.*]]
; CHECK: N: ; CHECK: N:
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 32 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 32
; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN]], label [[SWITCH_EARLY_TEST:%.*]] ; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN]], label [[SWITCH_EARLY_TEST:%.*]]
; CHECK: switch.early.test: ; CHECK: switch.early.test:
; CHECK-NEXT: switch i8 [[C:%.*]], label [[IF_END:%.*]] [ ; CHECK-NEXT: switch i8 [[C:%.*]], label [[COMMON_RET:%.*]] [
; CHECK-NEXT: i8 99, label [[IF_THEN]] ; CHECK-NEXT: i8 99, label [[IF_THEN]]
; CHECK-NEXT: i8 97, label [[IF_THEN]] ; CHECK-NEXT: i8 97, label [[IF_THEN]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ [[A:%.*]], [[IF_THEN]] ], [ 0, [[SWITCH_EARLY_TEST]] ]
; CHECK-NEXT: ret i32 [[COMMON_RET_OP]]
; CHECK: if.then: ; CHECK: if.then:
; CHECK-NEXT: [[A:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ 42, [[SWITCH_EARLY_TEST]] ], [ 42, [[N]] ], [ 42, [[SWITCH_EARLY_TEST]] ] ; CHECK-NEXT: [[A]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ 42, [[SWITCH_EARLY_TEST]] ], [ 42, [[N]] ], [ 42, [[SWITCH_EARLY_TEST]] ]
; CHECK-NEXT: tail call void @foo1() #[[ATTR2]] ; CHECK-NEXT: tail call void @foo1() #[[ATTR2]]
; CHECK-NEXT: ret i32 [[A]] ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: if.end:
; CHECK-NEXT: ret i32 0
; ;
entry: entry:
br i1 %C, label %N, label %if.then br i1 %C, label %N, label %if.then
N: N:
%cmp = icmp ult i32 %x, 32 %cmp = icmp ult i32 %x, 32
%cmp4 = icmp eq i8 %c, 97 %cmp4 = icmp eq i8 %c, 97
%or.cond = or i1 %cmp, %cmp4 %or.cond = or i1 %cmp, %cmp4
%cmp9 = icmp eq i8 %c, 99 %cmp9 = icmp eq i8 %c, 99
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define i32 @test10(i32 %mode, i1 %Cond) { define i32 @test10(i32 %mode, i1 %Cond) {
; CHECK-LABEL: @test10( ; CHECK-LABEL: @test10(
; CHECK-NEXT: br i1 [[COND:%.*]], label [[SWITCH_EARLY_TEST:%.*]], label [[F:%.*]] ; CHECK-NEXT: br i1 [[COND:%.*]], label [[SWITCH_EARLY_TEST:%.*]], label [[F:%.*]]
; CHECK: switch.early.test: ; CHECK: switch.early.test:
; CHECK-NEXT: switch i32 [[MODE:%.*]], label [[T:%.*]] [ ; CHECK-NEXT: switch i32 [[MODE:%.*]], label [[T:%.*]] [
; CHECK-NEXT: i32 51, label [[F]] ; CHECK-NEXT: i32 51, label [[F]]
; CHECK-NEXT: i32 0, label [[F]] ; CHECK-NEXT: i32 0, label [[F]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ 123, [[T]] ], [ 324, [[F]] ]
; CHECK-NEXT: ret i32 [[COMMON_RET_OP]]
; CHECK: T: ; CHECK: T:
; CHECK-NEXT: call void @foo1() ; CHECK-NEXT: call void @foo1()
; CHECK-NEXT: ret i32 123 ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: F: ; CHECK: F:
; CHECK-NEXT: call void @foo2() ; CHECK-NEXT: call void @foo2()
; CHECK-NEXT: ret i32 324 ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
%A = icmp ne i32 %mode, 0 %A = icmp ne i32 %mode, 0
%B = icmp ne i32 %mode, 51 %B = icmp ne i32 %mode, 51
%C = and i1 %A, %B %C = and i1 %A, %B
%D = and i1 %C, %Cond %D = and i1 %C, %Cond
br i1 %D, label %T, label %F br i1 %D, label %T, label %F
T: T:
call void @foo1() call void @foo1()
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} }
; Check that we don't turn an icmp into a switch where it's not useful. ; Check that we don't turn an icmp into a switch where it's not useful.
define void @test17(i32 %x, i32 %y) { define void @test17(i32 %x, i32 %y) {
; CHECK-LABEL: @test17( ; CHECK-LABEL: @test17(
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 3 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 3
; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i32 [[Y:%.*]], 2 ; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i32 [[Y:%.*]], 2
; CHECK-NEXT: [[OR_COND775:%.*]] = or i1 [[CMP]], [[SWITCH]] ; CHECK-NEXT: [[OR_COND775:%.*]] = or i1 [[CMP]], [[SWITCH]]
; CHECK-NEXT: br i1 [[OR_COND775]], label [[LOR_LHS_FALSE8:%.*]], label [[RETURN:%.*]] ; CHECK-NEXT: br i1 [[OR_COND775]], label [[LOR_LHS_FALSE8:%.*]], label [[COMMON_RET:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: lor.lhs.false8: ; CHECK: lor.lhs.false8:
; CHECK-NEXT: tail call void @foo1() ; CHECK-NEXT: tail call void @foo1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: return:
; CHECK-NEXT: ret void
; ;
%cmp = icmp ult i32 %x, 3 %cmp = icmp ult i32 %x, 3
%switch = icmp ult i32 %y, 2 %switch = icmp ult i32 %y, 2
%or.cond775 = or i1 %cmp, %switch %or.cond775 = or i1 %cmp, %switch
br i1 %or.cond775, label %lor.lhs.false8, label %return br i1 %or.cond775, label %lor.lhs.false8, label %return
lor.lhs.false8: lor.lhs.false8:
tail call void @foo1() tail call void @foo1()
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unreachable unreachable
if.end29: ; preds = %entry if.end29: ; preds = %entry
ret void ret void
} }
define void @test19(i32 %arg) { define void @test19(i32 %arg) {
; CHECK-LABEL: @test19( ; CHECK-LABEL: @test19(
; CHECK-NEXT: switch i32 [[ARG:%.*]], label [[ELSE:%.*]] [ ; CHECK-NEXT: switch i32 [[ARG:%.*]], label [[COMMON_RET:%.*]] [
; CHECK-NEXT: i32 32, label [[IF:%.*]] ; CHECK-NEXT: i32 32, label [[IF:%.*]]
; CHECK-NEXT: i32 13, label [[IF]] ; CHECK-NEXT: i32 13, label [[IF]]
; CHECK-NEXT: i32 12, label [[IF]] ; CHECK-NEXT: i32 12, label [[IF]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: if: ; CHECK: if:
; CHECK-NEXT: call void @foo1() ; CHECK-NEXT: call void @foo1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: else:
; CHECK-NEXT: ret void
; ;
%and = and i32 %arg, -2 %and = and i32 %arg, -2
%cmp1 = icmp eq i32 %and, 12 %cmp1 = icmp eq i32 %and, 12
%cmp2 = icmp eq i32 %arg, 32 %cmp2 = icmp eq i32 %arg, 32
%pred = or i1 %cmp1, %cmp2 %pred = or i1 %cmp1, %cmp2
br i1 %pred, label %if, label %else br i1 %pred, label %if, label %else
if: if:
call void @foo1() call void @foo1()
ret void ret void
else: else:
ret void ret void
} }
; Since %cmp1 is always false, a switch is never formed ; Since %cmp1 is always false, a switch is never formed
define void @test20(i32 %arg) { define void @test20(i32 %arg) {
; CHECK-LABEL: @test20( ; CHECK-LABEL: @test20(
; CHECK-NEXT: [[AND:%.*]] = and i32 [[ARG:%.*]], -2 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[ARG:%.*]], -2
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND]], 13 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND]], 13
; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[ARG]], 32 ; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[ARG]], 32
; CHECK-NEXT: [[PRED:%.*]] = or i1 [[CMP1]], [[CMP2]] ; CHECK-NEXT: [[PRED:%.*]] = or i1 [[CMP1]], [[CMP2]]
; CHECK-NEXT: br i1 [[PRED]], label [[IF:%.*]], label [[ELSE:%.*]] ; CHECK-NEXT: br i1 [[PRED]], label [[IF:%.*]], label [[COMMON_RET:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: if: ; CHECK: if:
; CHECK-NEXT: call void @foo1() ; CHECK-NEXT: call void @foo1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: else:
; CHECK-NEXT: ret void
; ;
%and = and i32 %arg, -2 %and = and i32 %arg, -2
%cmp1 = icmp eq i32 %and, 13 %cmp1 = icmp eq i32 %and, 13
%cmp2 = icmp eq i32 %arg, 32 %cmp2 = icmp eq i32 %arg, 32
%pred = or i1 %cmp1, %cmp2 %pred = or i1 %cmp1, %cmp2
br i1 %pred, label %if, label %else br i1 %pred, label %if, label %else
if: if:
call void @foo1() call void @foo1()
ret void ret void
else: else:
ret void ret void
} }
; Form a switch when or'ing a power of two ; Form a switch when or'ing a power of two
define void @test21(i32 %arg) { define void @test21(i32 %arg) {
; CHECK-LABEL: @test21( ; CHECK-LABEL: @test21(
; CHECK-NEXT: switch i32 [[ARG:%.*]], label [[IF:%.*]] [ ; CHECK-NEXT: switch i32 [[ARG:%.*]], label [[IF:%.*]] [
; CHECK-NEXT: i32 32, label [[ELSE:%.*]] ; CHECK-NEXT: i32 32, label [[COMMON_RET:%.*]]
; CHECK-NEXT: i32 13, label [[ELSE]] ; CHECK-NEXT: i32 13, label [[COMMON_RET]]
; CHECK-NEXT: i32 12, label [[ELSE]] ; CHECK-NEXT: i32 12, label [[COMMON_RET]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: if: ; CHECK: if:
; CHECK-NEXT: call void @foo1() ; CHECK-NEXT: call void @foo1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: else:
; CHECK-NEXT: ret void
; ;
%and = or i32 %arg, 1 %and = or i32 %arg, 1
%cmp1 = icmp ne i32 %and, 13 %cmp1 = icmp ne i32 %and, 13
%cmp2 = icmp ne i32 %arg, 32 %cmp2 = icmp ne i32 %arg, 32
%pred = and i1 %cmp1, %cmp2 %pred = and i1 %cmp1, %cmp2
br i1 %pred, label %if, label %else br i1 %pred, label %if, label %else
if: if:
call void @foo1() call void @foo1()
ret void ret void
else: else:
ret void ret void
} }
; Since %cmp1 is always false, a switch is never formed ; Since %cmp1 is always false, a switch is never formed
define void @test22(i32 %arg) { define void @test22(i32 %arg) {
; CHECK-LABEL: @test22( ; CHECK-LABEL: @test22(
; CHECK-NEXT: [[AND:%.*]] = or i32 [[ARG:%.*]], 1 ; CHECK-NEXT: [[AND:%.*]] = or i32 [[ARG:%.*]], 1
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND]], 12 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND]], 12
; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[ARG]], 32 ; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[ARG]], 32
; CHECK-NEXT: [[PRED:%.*]] = and i1 [[CMP1]], [[CMP2]] ; CHECK-NEXT: [[PRED:%.*]] = and i1 [[CMP1]], [[CMP2]]
; CHECK-NEXT: br i1 [[PRED]], label [[IF:%.*]], label [[ELSE:%.*]] ; CHECK-NEXT: br i1 [[PRED]], label [[IF:%.*]], label [[COMMON_RET:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: if: ; CHECK: if:
; CHECK-NEXT: call void @foo1() ; CHECK-NEXT: call void @foo1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: else:
; CHECK-NEXT: ret void
; ;
%and = or i32 %arg, 1 %and = or i32 %arg, 1
%cmp1 = icmp ne i32 %and, 12 %cmp1 = icmp ne i32 %and, 12
%cmp2 = icmp ne i32 %arg, 32 %cmp2 = icmp ne i32 %arg, 32
%pred = and i1 %cmp1, %cmp2 %pred = and i1 %cmp1, %cmp2
br i1 %pred, label %if, label %else br i1 %pred, label %if, label %else
if: if:
call void @foo1() call void @foo1()
ret void ret void
else: else:
ret void ret void
} }

llvm/test/Transforms/SimplifyCFG/switch_create.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s ; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s
; RUN: opt -S -data-layout="p:32:32-p1:16:16" -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=CHECK -check-prefix=DL %s ; RUN: opt -S -data-layout="p:32:32-p1:16:16" -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=CHECK -check-prefix=DL %s
declare void @foo1() declare void @foo1()
declare void @foo2() declare void @foo2()
define void @test1(i32 %V) { define void @test1(i32 %V) {
; CHECK-LABEL: @test1( ; CHECK-LABEL: @test1(
; CHECK-NEXT: switch i32 [[V:%.*]], label [[F:%.*]] [ ; CHECK-NEXT: switch i32 [[V:%.*]], label [[F:%.*]] [
; CHECK-NEXT: i32 17, label [[T:%.*]] ; CHECK-NEXT: i32 17, label [[T:%.*]]
; CHECK-NEXT: i32 4, label [[T]] ; CHECK-NEXT: i32 4, label [[T]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: T: ; CHECK: T:
; CHECK-NEXT: call void @foo1() ; CHECK-NEXT: call void @foo1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: F: ; CHECK: F:
; CHECK-NEXT: call void @foo2() ; CHECK-NEXT: call void @foo2()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
%C1 = icmp eq i32 %V, 4 ; <i1> [#uses=1] %C1 = icmp eq i32 %V, 4 ; <i1> [#uses=1]
%C2 = icmp eq i32 %V, 17 ; <i1> [#uses=1] %C2 = icmp eq i32 %V, 17 ; <i1> [#uses=1]
%CN = or i1 %C1, %C2 ; <i1> [#uses=1] %CN = or i1 %C1, %C2 ; <i1> [#uses=1]
br i1 %CN, label %T, label %F br i1 %CN, label %T, label %F
T: ; preds = %0 T: ; preds = %0
call void @foo1( ) call void @foo1( )
ret void ret void
F: ; preds = %0 F: ; preds = %0
call void @foo2( ) call void @foo2( )
ret void ret void
} }
define void @test1_select(i32 %V) { define void @test1_select(i32 %V) {
; CHECK-LABEL: @test1_select( ; CHECK-LABEL: @test1_select(
; CHECK-NEXT: switch i32 [[V:%.*]], label [[F:%.*]] [ ; CHECK-NEXT: switch i32 [[V:%.*]], label [[F:%.*]] [
; CHECK-NEXT: i32 17, label [[T:%.*]] ; CHECK-NEXT: i32 17, label [[T:%.*]]
; CHECK-NEXT: i32 4, label [[T]] ; CHECK-NEXT: i32 4, label [[T]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: T: ; CHECK: T:
; CHECK-NEXT: call void @foo1() ; CHECK-NEXT: call void @foo1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: F: ; CHECK: F:
; CHECK-NEXT: call void @foo2() ; CHECK-NEXT: call void @foo2()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
%C1 = icmp eq i32 %V, 4 %C1 = icmp eq i32 %V, 4
%C2 = icmp eq i32 %V, 17 %C2 = icmp eq i32 %V, 17
%CN = select i1 %C1, i1 true, i1 %C2 %CN = select i1 %C1, i1 true, i1 %C2
br i1 %CN, label %T, label %F br i1 %CN, label %T, label %F
T: T:
call void @foo1( ) call void @foo1( )
ret void ret void
F: F:
call void @foo2( ) call void @foo2( )
ret void ret void
} }
define void @test1_ptr(i32* %V) { define void @test1_ptr(i32* %V) {
; DL-LABEL: @test1_ptr( ; DL-LABEL: @test1_ptr(
; DL-NEXT: [[MAGICPTR:%.*]] = ptrtoint i32* [[V:%.*]] to i32 ; DL-NEXT: [[MAGICPTR:%.*]] = ptrtoint i32* [[V:%.*]] to i32
; DL-NEXT: switch i32 [[MAGICPTR]], label [[F:%.*]] [ ; DL-NEXT: switch i32 [[MAGICPTR]], label [[F:%.*]] [
; DL-NEXT: i32 17, label [[T:%.*]] ; DL-NEXT: i32 17, label [[T:%.*]]
; DL-NEXT: i32 4, label [[T]] ; DL-NEXT: i32 4, label [[T]]
; DL-NEXT: ] ; DL-NEXT: ]
; DL: common.ret:
; DL-NEXT: ret void
; DL: T: ; DL: T:
; DL-NEXT: call void @foo1() ; DL-NEXT: call void @foo1()
; DL-NEXT: ret void ; DL-NEXT: br label [[COMMON_RET:%.*]]
; DL: F: ; DL: F:
; DL-NEXT: call void @foo2() ; DL-NEXT: call void @foo2()
; DL-NEXT: ret void ; DL-NEXT: br label [[COMMON_RET]]
; ;
%C1 = icmp eq i32* %V, inttoptr (i32 4 to i32*) %C1 = icmp eq i32* %V, inttoptr (i32 4 to i32*)
%C2 = icmp eq i32* %V, inttoptr (i32 17 to i32*) %C2 = icmp eq i32* %V, inttoptr (i32 17 to i32*)
%CN = or i1 %C1, %C2 ; <i1> [#uses=1] %CN = or i1 %C1, %C2 ; <i1> [#uses=1]
br i1 %CN, label %T, label %F br i1 %CN, label %T, label %F
T: ; preds = %0 T: ; preds = %0
call void @foo1( ) call void @foo1( )
ret void ret void
F: ; preds = %0 F: ; preds = %0
call void @foo2( ) call void @foo2( )
ret void ret void
} }
define void @test1_ptr_as1(i32 addrspace(1)* %V) { define void @test1_ptr_as1(i32 addrspace(1)* %V) {
; DL-LABEL: @test1_ptr_as1( ; DL-LABEL: @test1_ptr_as1(
; DL-NEXT: [[MAGICPTR:%.*]] = ptrtoint i32 addrspace(1)* [[V:%.*]] to i16 ; DL-NEXT: [[MAGICPTR:%.*]] = ptrtoint i32 addrspace(1)* [[V:%.*]] to i16
; DL-NEXT: switch i16 [[MAGICPTR]], label [[F:%.*]] [ ; DL-NEXT: switch i16 [[MAGICPTR]], label [[F:%.*]] [
; DL-NEXT: i16 17, label [[T:%.*]] ; DL-NEXT: i16 17, label [[T:%.*]]
; DL-NEXT: i16 4, label [[T]] ; DL-NEXT: i16 4, label [[T]]
; DL-NEXT: ] ; DL-NEXT: ]
; DL: common.ret:
; DL-NEXT: ret void
; DL: T: ; DL: T:
; DL-NEXT: call void @foo1() ; DL-NEXT: call void @foo1()
; DL-NEXT: ret void ; DL-NEXT: br label [[COMMON_RET:%.*]]
; DL: F: ; DL: F:
; DL-NEXT: call void @foo2() ; DL-NEXT: call void @foo2()
; DL-NEXT: ret void ; DL-NEXT: br label [[COMMON_RET]]
; ;
%C1 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 4 to i32 addrspace(1)*) %C1 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 4 to i32 addrspace(1)*)
%C2 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 17 to i32 addrspace(1)*) %C2 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 17 to i32 addrspace(1)*)
%CN = or i1 %C1, %C2 ; <i1> [#uses=1] %CN = or i1 %C1, %C2 ; <i1> [#uses=1]
br i1 %CN, label %T, label %F br i1 %CN, label %T, label %F
T: ; preds = %0 T: ; preds = %0
call void @foo1( ) call void @foo1( )
ret void ret void
F: ; preds = %0 F: ; preds = %0
call void @foo2( ) call void @foo2( )
ret void ret void
} }
define void @test2(i32 %V) { define void @test2(i32 %V) {
; CHECK-LABEL: @test2( ; CHECK-LABEL: @test2(
; CHECK-NEXT: switch i32 [[V:%.*]], label [[T:%.*]] [ ; CHECK-NEXT: switch i32 [[V:%.*]], label [[T:%.*]] [
; CHECK-NEXT: i32 17, label [[F:%.*]] ; CHECK-NEXT: i32 17, label [[F:%.*]]
; CHECK-NEXT: i32 4, label [[F]] ; CHECK-NEXT: i32 4, label [[F]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: T: ; CHECK: T:
; CHECK-NEXT: call void @foo1() ; CHECK-NEXT: call void @foo1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: F: ; CHECK: F:
; CHECK-NEXT: call void @foo2() ; CHECK-NEXT: call void @foo2()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
%C1 = icmp ne i32 %V, 4 ; <i1> [#uses=1] %C1 = icmp ne i32 %V, 4 ; <i1> [#uses=1]
%C2 = icmp ne i32 %V, 17 ; <i1> [#uses=1] %C2 = icmp ne i32 %V, 17 ; <i1> [#uses=1]
%CN = and i1 %C1, %C2 ; <i1> [#uses=1] %CN = and i1 %C1, %C2 ; <i1> [#uses=1]
br i1 %CN, label %T, label %F br i1 %CN, label %T, label %F
T: ; preds = %0 T: ; preds = %0
call void @foo1( ) call void @foo1( )
ret void ret void
F: ; preds = %0 F: ; preds = %0
call void @foo2( ) call void @foo2( )
ret void ret void
} }
define void @test2_select(i32 %V) { define void @test2_select(i32 %V) {
; CHECK-LABEL: @test2_select( ; CHECK-LABEL: @test2_select(
; CHECK-NEXT: switch i32 [[V:%.*]], label [[T:%.*]] [ ; CHECK-NEXT: switch i32 [[V:%.*]], label [[T:%.*]] [
; CHECK-NEXT: i32 17, label [[F:%.*]] ; CHECK-NEXT: i32 17, label [[F:%.*]]
; CHECK-NEXT: i32 4, label [[F]] ; CHECK-NEXT: i32 4, label [[F]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: T: ; CHECK: T:
; CHECK-NEXT: call void @foo1() ; CHECK-NEXT: call void @foo1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: F: ; CHECK: F:
; CHECK-NEXT: call void @foo2() ; CHECK-NEXT: call void @foo2()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
%C1 = icmp ne i32 %V, 4 %C1 = icmp ne i32 %V, 4
%C2 = icmp ne i32 %V, 17 %C2 = icmp ne i32 %V, 17
%CN = select i1 %C1, i1 %C2, i1 false %CN = select i1 %C1, i1 %C2, i1 false
br i1 %CN, label %T, label %F br i1 %CN, label %T, label %F
T: T:
call void @foo1( ) call void @foo1( )
ret void ret void
F: F:
call void @foo2( ) call void @foo2( )
ret void ret void
} }
define void @test3(i32 %V) { define void @test3(i32 %V) {
; CHECK-LABEL: @test3( ; CHECK-LABEL: @test3(
; CHECK-NEXT: switch i32 [[V:%.*]], label [[F:%.*]] [ ; CHECK-NEXT: switch i32 [[V:%.*]], label [[F:%.*]] [
; CHECK-NEXT: i32 4, label [[T:%.*]] ; CHECK-NEXT: i32 4, label [[T:%.*]]
; CHECK-NEXT: i32 17, label [[T]] ; CHECK-NEXT: i32 17, label [[T]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: T: ; CHECK: T:
; CHECK-NEXT: call void @foo1() ; CHECK-NEXT: call void @foo1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: F: ; CHECK: F:
; CHECK-NEXT: call void @foo2() ; CHECK-NEXT: call void @foo2()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
%C1 = icmp eq i32 %V, 4 ; <i1> [#uses=1] %C1 = icmp eq i32 %V, 4 ; <i1> [#uses=1]
br i1 %C1, label %T, label %N br i1 %C1, label %T, label %N
N: ; preds = %0 N: ; preds = %0
%C2 = icmp eq i32 %V, 17 ; <i1> [#uses=1] %C2 = icmp eq i32 %V, 17 ; <i1> [#uses=1]
br i1 %C2, label %T, label %F br i1 %C2, label %T, label %F
T: ; preds = %N, %0 T: ; preds = %N, %0
call void @foo1( ) call void @foo1( )
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} }
define void @test7(i8 zeroext %c, i32 %x) nounwind ssp noredzone { define void @test7(i8 zeroext %c, i32 %x) nounwind ssp noredzone {
; CHECK-LABEL: @test7( ; CHECK-LABEL: @test7(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 32 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 32
; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[SWITCH_EARLY_TEST:%.*]] ; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[SWITCH_EARLY_TEST:%.*]]
; CHECK: switch.early.test: ; CHECK: switch.early.test:
; CHECK-NEXT: switch i8 [[C:%.*]], label [[IF_END:%.*]] [ ; CHECK-NEXT: switch i8 [[C:%.*]], label [[COMMON_RET:%.*]] [
; CHECK-NEXT: i8 99, label [[IF_THEN]] ; CHECK-NEXT: i8 99, label [[IF_THEN]]
; CHECK-NEXT: i8 97, label [[IF_THEN]] ; CHECK-NEXT: i8 97, label [[IF_THEN]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: if.then: ; CHECK: if.then:
; CHECK-NEXT: tail call void @foo1() #[[ATTR2:[0-9]+]] ; CHECK-NEXT: tail call void @foo1() #[[ATTR2:[0-9]+]]
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: if.end:
; CHECK-NEXT: ret void
; ;
entry: entry:
%cmp = icmp ult i32 %x, 32 %cmp = icmp ult i32 %x, 32
%cmp4 = icmp eq i8 %c, 97 %cmp4 = icmp eq i8 %c, 97
%or.cond = or i1 %cmp, %cmp4 %or.cond = or i1 %cmp, %cmp4
%cmp9 = icmp eq i8 %c, 99 %cmp9 = icmp eq i8 %c, 99
%or.cond11 = or i1 %or.cond, %cmp9 %or.cond11 = or i1 %or.cond, %cmp9
br i1 %or.cond11, label %if.then, label %if.end br i1 %or.cond11, label %if.then, label %if.end
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define i32 @test8(i8 zeroext %c, i32 %x, i1 %C) nounwind ssp noredzone { define i32 @test8(i8 zeroext %c, i32 %x, i1 %C) nounwind ssp noredzone {
; CHECK-LABEL: @test8( ; CHECK-LABEL: @test8(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[C:%.*]], label [[N:%.*]], label [[IF_THEN:%.*]] ; CHECK-NEXT: br i1 [[C:%.*]], label [[N:%.*]], label [[IF_THEN:%.*]]
; CHECK: N: ; CHECK: N:
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 32 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 32
; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN]], label [[SWITCH_EARLY_TEST:%.*]] ; CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN]], label [[SWITCH_EARLY_TEST:%.*]]
; CHECK: switch.early.test: ; CHECK: switch.early.test:
; CHECK-NEXT: switch i8 [[C:%.*]], label [[IF_END:%.*]] [ ; CHECK-NEXT: switch i8 [[C:%.*]], label [[COMMON_RET:%.*]] [
; CHECK-NEXT: i8 99, label [[IF_THEN]] ; CHECK-NEXT: i8 99, label [[IF_THEN]]
; CHECK-NEXT: i8 97, label [[IF_THEN]] ; CHECK-NEXT: i8 97, label [[IF_THEN]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ [[A:%.*]], [[IF_THEN]] ], [ 0, [[SWITCH_EARLY_TEST]] ]
; CHECK-NEXT: ret i32 [[COMMON_RET_OP]]
; CHECK: if.then: ; CHECK: if.then:
; CHECK-NEXT: [[A:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ 42, [[SWITCH_EARLY_TEST]] ], [ 42, [[N]] ], [ 42, [[SWITCH_EARLY_TEST]] ] ; CHECK-NEXT: [[A]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ 42, [[SWITCH_EARLY_TEST]] ], [ 42, [[N]] ], [ 42, [[SWITCH_EARLY_TEST]] ]
; CHECK-NEXT: tail call void @foo1() #[[ATTR2]] ; CHECK-NEXT: tail call void @foo1() #[[ATTR2]]
; CHECK-NEXT: ret i32 [[A]] ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: if.end:
; CHECK-NEXT: ret i32 0
; ;
entry: entry:
br i1 %C, label %N, label %if.then br i1 %C, label %N, label %if.then
N: N:
%cmp = icmp ult i32 %x, 32 %cmp = icmp ult i32 %x, 32
%cmp4 = icmp eq i8 %c, 97 %cmp4 = icmp eq i8 %c, 97
%or.cond = or i1 %cmp, %cmp4 %or.cond = or i1 %cmp, %cmp4
%cmp9 = icmp eq i8 %c, 99 %cmp9 = icmp eq i8 %c, 99
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define i32 @test10(i32 %mode, i1 %Cond) { define i32 @test10(i32 %mode, i1 %Cond) {
; CHECK-LABEL: @test10( ; CHECK-LABEL: @test10(
; CHECK-NEXT: br i1 [[COND:%.*]], label [[SWITCH_EARLY_TEST:%.*]], label [[F:%.*]] ; CHECK-NEXT: br i1 [[COND:%.*]], label [[SWITCH_EARLY_TEST:%.*]], label [[F:%.*]]
; CHECK: switch.early.test: ; CHECK: switch.early.test:
; CHECK-NEXT: switch i32 [[MODE:%.*]], label [[T:%.*]] [ ; CHECK-NEXT: switch i32 [[MODE:%.*]], label [[T:%.*]] [
; CHECK-NEXT: i32 51, label [[F]] ; CHECK-NEXT: i32 51, label [[F]]
; CHECK-NEXT: i32 0, label [[F]] ; CHECK-NEXT: i32 0, label [[F]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ 123, [[T]] ], [ 324, [[F]] ]
; CHECK-NEXT: ret i32 [[COMMON_RET_OP]]
; CHECK: T: ; CHECK: T:
; CHECK-NEXT: call void @foo1() ; CHECK-NEXT: call void @foo1()
; CHECK-NEXT: ret i32 123 ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: F: ; CHECK: F:
; CHECK-NEXT: call void @foo2() ; CHECK-NEXT: call void @foo2()
; CHECK-NEXT: ret i32 324 ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
%A = icmp ne i32 %mode, 0 %A = icmp ne i32 %mode, 0
%B = icmp ne i32 %mode, 51 %B = icmp ne i32 %mode, 51
%C = and i1 %A, %B %C = and i1 %A, %B
%D = and i1 %C, %Cond %D = and i1 %C, %Cond
br i1 %D, label %T, label %F br i1 %D, label %T, label %F
T: T:
call void @foo1() call void @foo1()
ret i32 123 ret i32 123
F: F:
call void @foo2() call void @foo2()
ret i32 324 ret i32 324
} }
define i32 @test10_select(i32 %mode, i1 %Cond) { define i32 @test10_select(i32 %mode, i1 %Cond) {
; CHECK-LABEL: @test10_select( ; CHECK-LABEL: @test10_select(
; CHECK-NEXT: br i1 [[COND:%.*]], label [[SWITCH_EARLY_TEST:%.*]], label [[F:%.*]] ; CHECK-NEXT: br i1 [[COND:%.*]], label [[SWITCH_EARLY_TEST:%.*]], label [[F:%.*]]
; CHECK: switch.early.test: ; CHECK: switch.early.test:
; CHECK-NEXT: switch i32 [[MODE:%.*]], label [[T:%.*]] [ ; CHECK-NEXT: switch i32 [[MODE:%.*]], label [[T:%.*]] [
; CHECK-NEXT: i32 51, label [[F]] ; CHECK-NEXT: i32 51, label [[F]]
; CHECK-NEXT: i32 0, label [[F]] ; CHECK-NEXT: i32 0, label [[F]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ 123, [[T]] ], [ 324, [[F]] ]
; CHECK-NEXT: ret i32 [[COMMON_RET_OP]]
; CHECK: T: ; CHECK: T:
; CHECK-NEXT: call void @foo1() ; CHECK-NEXT: call void @foo1()
; CHECK-NEXT: ret i32 123 ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: F: ; CHECK: F:
; CHECK-NEXT: call void @foo2() ; CHECK-NEXT: call void @foo2()
; CHECK-NEXT: ret i32 324 ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
%A = icmp ne i32 %mode, 0 %A = icmp ne i32 %mode, 0
%B = icmp ne i32 %mode, 51 %B = icmp ne i32 %mode, 51
%C = select i1 %A, i1 %B, i1 false %C = select i1 %A, i1 %B, i1 false
%D = select i1 %C, i1 %Cond, i1 false %D = select i1 %C, i1 %Cond, i1 false
br i1 %D, label %T, label %F br i1 %D, label %T, label %F
T: T:
call void @foo1() call void @foo1()
ret i32 123 ret i32 123
F: F:
call void @foo2() call void @foo2()
ret i32 324 ret i32 324
} }
; TODO: %Cond doesn't need freeze ; TODO: %Cond doesn't need freeze
define i32 @test10_select_and(i32 %mode, i1 %Cond) { define i32 @test10_select_and(i32 %mode, i1 %Cond) {
; CHECK-LABEL: @test10_select_and( ; CHECK-LABEL: @test10_select_and(
; CHECK-NEXT: br i1 [[COND:%.*]], label [[SWITCH_EARLY_TEST:%.*]], label [[F:%.*]] ; CHECK-NEXT: br i1 [[COND:%.*]], label [[SWITCH_EARLY_TEST:%.*]], label [[F:%.*]]
; CHECK: switch.early.test: ; CHECK: switch.early.test:
; CHECK-NEXT: switch i32 [[MODE:%.*]], label [[T:%.*]] [ ; CHECK-NEXT: switch i32 [[MODE:%.*]], label [[T:%.*]] [
; CHECK-NEXT: i32 51, label [[F]] ; CHECK-NEXT: i32 51, label [[F]]
; CHECK-NEXT: i32 0, label [[F]] ; CHECK-NEXT: i32 0, label [[F]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ 123, [[T]] ], [ 324, [[F]] ]
; CHECK-NEXT: ret i32 [[COMMON_RET_OP]]
; CHECK: T: ; CHECK: T:
; CHECK-NEXT: call void @foo1() ; CHECK-NEXT: call void @foo1()
; CHECK-NEXT: ret i32 123 ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: F: ; CHECK: F:
; CHECK-NEXT: call void @foo2() ; CHECK-NEXT: call void @foo2()
; CHECK-NEXT: ret i32 324 ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
%A = icmp ne i32 %mode, 0 %A = icmp ne i32 %mode, 0
%B = icmp ne i32 %mode, 51 %B = icmp ne i32 %mode, 51
%C = select i1 %A, i1 %B, i1 false %C = select i1 %A, i1 %B, i1 false
%D = and i1 %C, %Cond %D = and i1 %C, %Cond
br i1 %D, label %T, label %F br i1 %D, label %T, label %F
T: T:
call void @foo1() call void @foo1()
ret i32 123 ret i32 123
F: F:
call void @foo2() call void @foo2()
ret i32 324 ret i32 324
} }
define i32 @test10_select_nofreeze(i32 %mode, i1 noundef %Cond) { define i32 @test10_select_nofreeze(i32 %mode, i1 noundef %Cond) {
; CHECK-LABEL: @test10_select_nofreeze( ; CHECK-LABEL: @test10_select_nofreeze(
; CHECK-NEXT: br i1 [[COND:%.*]], label [[SWITCH_EARLY_TEST:%.*]], label [[F:%.*]] ; CHECK-NEXT: br i1 [[COND:%.*]], label [[SWITCH_EARLY_TEST:%.*]], label [[F:%.*]]
; CHECK: switch.early.test: ; CHECK: switch.early.test:
; CHECK-NEXT: switch i32 [[MODE:%.*]], label [[T:%.*]] [ ; CHECK-NEXT: switch i32 [[MODE:%.*]], label [[T:%.*]] [
; CHECK-NEXT: i32 51, label [[F]] ; CHECK-NEXT: i32 51, label [[F]]
; CHECK-NEXT: i32 0, label [[F]] ; CHECK-NEXT: i32 0, label [[F]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: [[COMMON_RET_OP:%.*]] = phi i32 [ 123, [[T]] ], [ 324, [[F]] ]
; CHECK-NEXT: ret i32 [[COMMON_RET_OP]]
; CHECK: T: ; CHECK: T:
; CHECK-NEXT: call void @foo1() ; CHECK-NEXT: call void @foo1()
; CHECK-NEXT: ret i32 123 ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: F: ; CHECK: F:
; CHECK-NEXT: call void @foo2() ; CHECK-NEXT: call void @foo2()
; CHECK-NEXT: ret i32 324 ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
%A = icmp ne i32 %mode, 0 %A = icmp ne i32 %mode, 0
%B = icmp ne i32 %mode, 51 %B = icmp ne i32 %mode, 51
%C = select i1 %A, i1 %B, i1 false %C = select i1 %A, i1 %B, i1 false
%D = select i1 %C, i1 %Cond, i1 false %D = select i1 %C, i1 %Cond, i1 false
br i1 %D, label %T, label %F br i1 %D, label %T, label %F
T: T:
call void @foo1() call void @foo1()
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} }
; Check that we don't turn an icmp into a switch where it's not useful. ; Check that we don't turn an icmp into a switch where it's not useful.
define void @test17(i32 %x, i32 %y) { define void @test17(i32 %x, i32 %y) {
; CHECK-LABEL: @test17( ; CHECK-LABEL: @test17(
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 3 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 3
; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i32 [[Y:%.*]], 2 ; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i32 [[Y:%.*]], 2
; CHECK-NEXT: [[OR_COND775:%.*]] = or i1 [[CMP]], [[SWITCH]] ; CHECK-NEXT: [[OR_COND775:%.*]] = or i1 [[CMP]], [[SWITCH]]
; CHECK-NEXT: br i1 [[OR_COND775]], label [[LOR_LHS_FALSE8:%.*]], label [[RETURN:%.*]] ; CHECK-NEXT: br i1 [[OR_COND775]], label [[LOR_LHS_FALSE8:%.*]], label [[COMMON_RET:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: lor.lhs.false8: ; CHECK: lor.lhs.false8:
; CHECK-NEXT: tail call void @foo1() ; CHECK-NEXT: tail call void @foo1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: return:
; CHECK-NEXT: ret void
; ;
%cmp = icmp ult i32 %x, 3 %cmp = icmp ult i32 %x, 3
%switch = icmp ult i32 %y, 2 %switch = icmp ult i32 %y, 2
%or.cond775 = or i1 %cmp, %switch %or.cond775 = or i1 %cmp, %switch
br i1 %or.cond775, label %lor.lhs.false8, label %return br i1 %or.cond775, label %lor.lhs.false8, label %return
lor.lhs.false8: lor.lhs.false8:
tail call void @foo1() tail call void @foo1()
ret void ret void
return: return:
ret void ret void
} }
define void @test17_select(i32 %x, i32 %y) { define void @test17_select(i32 %x, i32 %y) {
; CHECK-LABEL: @test17_select( ; CHECK-LABEL: @test17_select(
; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 3 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 3
; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i32 [[Y:%.*]], 2 ; CHECK-NEXT: [[SWITCH:%.*]] = icmp ult i32 [[Y:%.*]], 2
; CHECK-NEXT: [[OR_COND775:%.*]] = select i1 [[CMP]], i1 true, i1 [[SWITCH]] ; CHECK-NEXT: [[OR_COND775:%.*]] = select i1 [[CMP]], i1 true, i1 [[SWITCH]]
; CHECK-NEXT: br i1 [[OR_COND775]], label [[LOR_LHS_FALSE8:%.*]], label [[RETURN:%.*]] ; CHECK-NEXT: br i1 [[OR_COND775]], label [[LOR_LHS_FALSE8:%.*]], label [[COMMON_RET:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: lor.lhs.false8: ; CHECK: lor.lhs.false8:
; CHECK-NEXT: tail call void @foo1() ; CHECK-NEXT: tail call void @foo1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: return:
; CHECK-NEXT: ret void
; ;
%cmp = icmp ult i32 %x, 3 %cmp = icmp ult i32 %x, 3
%switch = icmp ult i32 %y, 2 %switch = icmp ult i32 %y, 2
%or.cond775 = select i1 %cmp, i1 true, i1 %switch %or.cond775 = select i1 %cmp, i1 true, i1 %switch
br i1 %or.cond775, label %lor.lhs.false8, label %return br i1 %or.cond775, label %lor.lhs.false8, label %return
lor.lhs.false8: lor.lhs.false8:
tail call void @foo1() tail call void @foo1()
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Lines
if.end29: ; preds = %entry if.end29: ; preds = %entry
ret void ret void
} }
; Form a switch when and'ing a negated power of two ; Form a switch when and'ing a negated power of two
define void @test19(i32 %arg) { define void @test19(i32 %arg) {
; CHECK-LABEL: @test19( ; CHECK-LABEL: @test19(
; CHECK-NEXT: switch i32 [[ARG:%.*]], label [[ELSE:%.*]] [ ; CHECK-NEXT: switch i32 [[ARG:%.*]], label [[COMMON_RET:%.*]] [
; CHECK-NEXT: i32 32, label [[IF:%.*]] ; CHECK-NEXT: i32 32, label [[IF:%.*]]
; CHECK-NEXT: i32 13, label [[IF]] ; CHECK-NEXT: i32 13, label [[IF]]
; CHECK-NEXT: i32 12, label [[IF]] ; CHECK-NEXT: i32 12, label [[IF]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: if: ; CHECK: if:
; CHECK-NEXT: call void @foo1() ; CHECK-NEXT: call void @foo1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: else:
; CHECK-NEXT: ret void
; ;
%and = and i32 %arg, -2 %and = and i32 %arg, -2
%cmp1 = icmp eq i32 %and, 12 %cmp1 = icmp eq i32 %and, 12
%cmp2 = icmp eq i32 %arg, 32 %cmp2 = icmp eq i32 %arg, 32
%pred = or i1 %cmp1, %cmp2 %pred = or i1 %cmp1, %cmp2
br i1 %pred, label %if, label %else br i1 %pred, label %if, label %else
if: if:
call void @foo1() call void @foo1()
ret void ret void
else: else:
ret void ret void
} }
define void @test19_select(i32 %arg) { define void @test19_select(i32 %arg) {
; CHECK-LABEL: @test19_select( ; CHECK-LABEL: @test19_select(
; CHECK-NEXT: switch i32 [[ARG:%.*]], label [[ELSE:%.*]] [ ; CHECK-NEXT: switch i32 [[ARG:%.*]], label [[COMMON_RET:%.*]] [
; CHECK-NEXT: i32 32, label [[IF:%.*]] ; CHECK-NEXT: i32 32, label [[IF:%.*]]
; CHECK-NEXT: i32 13, label [[IF]] ; CHECK-NEXT: i32 13, label [[IF]]
; CHECK-NEXT: i32 12, label [[IF]] ; CHECK-NEXT: i32 12, label [[IF]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: if: ; CHECK: if:
; CHECK-NEXT: call void @foo1() ; CHECK-NEXT: call void @foo1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: else:
; CHECK-NEXT: ret void
; ;
%and = and i32 %arg, -2 %and = and i32 %arg, -2
%cmp1 = icmp eq i32 %and, 12 %cmp1 = icmp eq i32 %and, 12
%cmp2 = icmp eq i32 %arg, 32 %cmp2 = icmp eq i32 %arg, 32
%pred = select i1 %cmp1, i1 true, i1 %cmp2 %pred = select i1 %cmp1, i1 true, i1 %cmp2
br i1 %pred, label %if, label %else br i1 %pred, label %if, label %else
if: if:
call void @foo1() call void @foo1()
ret void ret void
else: else:
ret void ret void
} }
; Since %cmp1 is always false, a switch is never formed ; Since %cmp1 is always false, a switch is never formed
define void @test20(i32 %arg) { define void @test20(i32 %arg) {
; CHECK-LABEL: @test20( ; CHECK-LABEL: @test20(
; CHECK-NEXT: [[AND:%.*]] = and i32 [[ARG:%.*]], -2 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[ARG:%.*]], -2
; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND]], 13 ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[AND]], 13
; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[ARG]], 32 ; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[ARG]], 32
; CHECK-NEXT: [[PRED:%.*]] = or i1 [[CMP1]], [[CMP2]] ; CHECK-NEXT: [[PRED:%.*]] = or i1 [[CMP1]], [[CMP2]]
; CHECK-NEXT: br i1 [[PRED]], label [[IF:%.*]], label [[ELSE:%.*]] ; CHECK-NEXT: br i1 [[PRED]], label [[IF:%.*]], label [[COMMON_RET:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: if: ; CHECK: if:
; CHECK-NEXT: call void @foo1() ; CHECK-NEXT: call void @foo1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: else:
; CHECK-NEXT: ret void
; ;
%and = and i32 %arg, -2 %and = and i32 %arg, -2
%cmp1 = icmp eq i32 %and, 13 %cmp1 = icmp eq i32 %and, 13
%cmp2 = icmp eq i32 %arg, 32 %cmp2 = icmp eq i32 %arg, 32
%pred = or i1 %cmp1, %cmp2 %pred = or i1 %cmp1, %cmp2
br i1 %pred, label %if, label %else br i1 %pred, label %if, label %else
if: if:
call void @foo1() call void @foo1()
ret void ret void
else: else:
ret void ret void
} }
; Form a switch when or'ing a power of two ; Form a switch when or'ing a power of two
define void @test21(i32 %arg) { define void @test21(i32 %arg) {
; CHECK-LABEL: @test21( ; CHECK-LABEL: @test21(
; CHECK-NEXT: switch i32 [[ARG:%.*]], label [[IF:%.*]] [ ; CHECK-NEXT: switch i32 [[ARG:%.*]], label [[IF:%.*]] [
; CHECK-NEXT: i32 32, label [[ELSE:%.*]] ; CHECK-NEXT: i32 32, label [[COMMON_RET:%.*]]
; CHECK-NEXT: i32 13, label [[ELSE]] ; CHECK-NEXT: i32 13, label [[COMMON_RET]]
; CHECK-NEXT: i32 12, label [[ELSE]] ; CHECK-NEXT: i32 12, label [[COMMON_RET]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: if: ; CHECK: if:
; CHECK-NEXT: call void @foo1() ; CHECK-NEXT: call void @foo1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: else:
; CHECK-NEXT: ret void
; ;
%and = or i32 %arg, 1 %and = or i32 %arg, 1
%cmp1 = icmp ne i32 %and, 13 %cmp1 = icmp ne i32 %and, 13
%cmp2 = icmp ne i32 %arg, 32 %cmp2 = icmp ne i32 %arg, 32
%pred = and i1 %cmp1, %cmp2 %pred = and i1 %cmp1, %cmp2
br i1 %pred, label %if, label %else br i1 %pred, label %if, label %else
if: if:
call void @foo1() call void @foo1()
ret void ret void
else: else:
ret void ret void
} }
; Since %cmp1 is always false, a switch is never formed ; Since %cmp1 is always false, a switch is never formed
define void @test22(i32 %arg) { define void @test22(i32 %arg) {
; CHECK-LABEL: @test22( ; CHECK-LABEL: @test22(
; CHECK-NEXT: [[AND:%.*]] = or i32 [[ARG:%.*]], 1 ; CHECK-NEXT: [[AND:%.*]] = or i32 [[ARG:%.*]], 1
; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND]], 12 ; CHECK-NEXT: [[CMP1:%.*]] = icmp ne i32 [[AND]], 12
; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[ARG]], 32 ; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i32 [[ARG]], 32
; CHECK-NEXT: [[PRED:%.*]] = and i1 [[CMP1]], [[CMP2]] ; CHECK-NEXT: [[PRED:%.*]] = and i1 [[CMP1]], [[CMP2]]
; CHECK-NEXT: br i1 [[PRED]], label [[IF:%.*]], label [[ELSE:%.*]] ; CHECK-NEXT: br i1 [[PRED]], label [[IF:%.*]], label [[COMMON_RET:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: if: ; CHECK: if:
; CHECK-NEXT: call void @foo1() ; CHECK-NEXT: call void @foo1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: else:
; CHECK-NEXT: ret void
; ;
%and = or i32 %arg, 1 %and = or i32 %arg, 1
%cmp1 = icmp ne i32 %and, 12 %cmp1 = icmp ne i32 %and, 12
%cmp2 = icmp ne i32 %arg, 32 %cmp2 = icmp ne i32 %arg, 32
%pred = and i1 %cmp1, %cmp2 %pred = and i1 %cmp1, %cmp2
br i1 %pred, label %if, label %else br i1 %pred, label %if, label %else
if: if:
call void @foo1() call void @foo1()
ret void ret void
else: else:
ret void ret void
} }

llvm/test/Transforms/SimplifyCFG/switch_switch_fold.ll

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define void @test1(i32 %V) { define void @test1(i32 %V) {
; CHECK-LABEL: @test1( ; CHECK-LABEL: @test1(
; CHECK-NEXT: switch i32 [[V:%.*]], label [[INFLOOP:%.*]] [ ; CHECK-NEXT: switch i32 [[V:%.*]], label [[INFLOOP:%.*]] [
; CHECK-NEXT: i32 4, label [[A:%.*]] ; CHECK-NEXT: i32 4, label [[A:%.*]]
; CHECK-NEXT: i32 17, label [[B:%.*]] ; CHECK-NEXT: i32 17, label [[B:%.*]]
; CHECK-NEXT: i32 18, label [[B]] ; CHECK-NEXT: i32 18, label [[B]]
; CHECK-NEXT: i32 42, label [[D:%.*]] ; CHECK-NEXT: i32 42, label [[D:%.*]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: A: ; CHECK: A:
; CHECK-NEXT: call void @foo1() ; CHECK-NEXT: call void @foo1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: B: ; CHECK: B:
; CHECK-NEXT: call void @foo2() ; CHECK-NEXT: call void @foo2()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: D: ; CHECK: D:
; CHECK-NEXT: call void @foo4() ; CHECK-NEXT: call void @foo4()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: infloop: ; CHECK: infloop:
; CHECK-NEXT: br label [[INFLOOP]] ; CHECK-NEXT: br label [[INFLOOP]]
; ;
switch i32 %V, label %F [ switch i32 %V, label %F [
i32 4, label %T i32 4, label %T
i32 17, label %T i32 17, label %T
i32 5, label %T i32 5, label %T
i32 1234, label %F i32 1234, label %F
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llvm/test/Transforms/SimplifyCFG/switch_thread.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s ; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s
; Test that we can thread a simple known condition through switch statements. ; Test that we can thread a simple known condition through switch statements.
declare void @foo1() declare void @foo1()
declare void @foo2() declare void @foo2()
declare void @DEAD() declare void @DEAD()
define void @test1(i32 %V) { define void @test1(i32 %V) {
; CHECK-LABEL: @test1( ; CHECK-LABEL: @test1(
; CHECK-NEXT: switch i32 [[V:%.*]], label [[A:%.*]] [ ; CHECK-NEXT: switch i32 [[V:%.*]], label [[A:%.*]] [
; CHECK-NEXT: i32 4, label [[T:%.*]] ; CHECK-NEXT: i32 4, label [[T:%.*]]
; CHECK-NEXT: i32 17, label [[DONE:%.*]] ; CHECK-NEXT: i32 17, label [[COMMON_RET:%.*]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: T: ; CHECK: T:
; CHECK-NEXT: call void @foo1() ; CHECK-NEXT: call void @foo1()
; CHECK-NEXT: call void @foo2() ; CHECK-NEXT: call void @foo2()
; CHECK-NEXT: br label [[DONE]] ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: A: ; CHECK: A:
; CHECK-NEXT: call void @foo1() ; CHECK-NEXT: call void @foo1()
; CHECK-NEXT: br label [[DONE]] ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: Done: ; CHECK: common.ret:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
switch i32 %V, label %A [ switch i32 %V, label %A [
i32 4, label %T i32 4, label %T
i32 17, label %Done i32 17, label %Done
i32 1234, label %A i32 1234, label %A
] ]
;; V == 4 if we get here. ;; V == 4 if we get here.
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} }
define void @test2(i32 %V) { define void @test2(i32 %V) {
; CHECK-LABEL: @test2( ; CHECK-LABEL: @test2(
; CHECK-NEXT: switch i32 [[V:%.*]], label [[A:%.*]] [ ; CHECK-NEXT: switch i32 [[V:%.*]], label [[A:%.*]] [
; CHECK-NEXT: i32 4, label [[T:%.*]] ; CHECK-NEXT: i32 4, label [[T:%.*]]
; CHECK-NEXT: i32 17, label [[D:%.*]] ; CHECK-NEXT: i32 17, label [[D:%.*]]
; CHECK-NEXT: i32 1234, label [[E:%.*]] ; CHECK-NEXT: i32 1234, label [[COMMON_RET:%.*]]
; CHECK-NEXT: ] ; CHECK-NEXT: ]
; CHECK: A: ; CHECK: A:
; CHECK-NEXT: call void @foo1() ; CHECK-NEXT: call void @foo1()
; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[V]], 42 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[V]], 42
; CHECK-NEXT: br i1 [[COND]], label [[D]], label [[E]] ; CHECK-NEXT: br i1 [[COND]], label [[D]], label [[COMMON_RET]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: T: ; CHECK: T:
; CHECK-NEXT: call void @foo1() ; CHECK-NEXT: call void @foo1()
; CHECK-NEXT: call void @foo1() ; CHECK-NEXT: call void @foo1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: D: ; CHECK: D:
; CHECK-NEXT: call void @foo1() ; CHECK-NEXT: call void @foo1()
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; CHECK: E:
; CHECK-NEXT: ret void
; ;
switch i32 %V, label %A [ switch i32 %V, label %A [
i32 4, label %T i32 4, label %T
i32 17, label %D i32 17, label %D
i32 1234, label %E i32 1234, label %E
] ]
;; V != 4, 17, 1234 here. ;; V != 4, 17, 1234 here.
A: ; preds = %0 A: ; preds = %0
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llvm/test/Transforms/SimplifyCFG/unprofitable-pr.ll

Show All 12 Lines
; CHECK: false1: ; CHECK: false1:
; CHECK-NEXT: store volatile i64 1, i64* [[PTR:%.*]], align 4 ; CHECK-NEXT: store volatile i64 1, i64* [[PTR:%.*]], align 4
; CHECK-NEXT: [[PTRINT:%.*]] = ptrtoint i64* [[PTR]] to i64 ; CHECK-NEXT: [[PTRINT:%.*]] = ptrtoint i64* [[PTR]] to i64
; CHECK-NEXT: [[MASKEDPTR:%.*]] = and i64 [[PTRINT]], 7 ; CHECK-NEXT: [[MASKEDPTR:%.*]] = and i64 [[PTRINT]], 7
; CHECK-NEXT: [[MASKCOND:%.*]] = icmp eq i64 [[MASKEDPTR]], 0 ; CHECK-NEXT: [[MASKCOND:%.*]] = icmp eq i64 [[MASKEDPTR]], 0
; CHECK-NEXT: tail call void @llvm.assume(i1 [[MASKCOND]]) ; CHECK-NEXT: tail call void @llvm.assume(i1 [[MASKCOND]])
; CHECK-NEXT: store volatile i64 0, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 0, i64* [[PTR]], align 8
; CHECK-NEXT: store volatile i64 3, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 3, i64* [[PTR]], align 8
; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; CHECK: true2.critedge: ; CHECK: true2.critedge:
; CHECK-NEXT: [[PTRINT_C:%.*]] = ptrtoint i64* [[PTR]] to i64 ; CHECK-NEXT: [[PTRINT_C:%.*]] = ptrtoint i64* [[PTR]] to i64
; CHECK-NEXT: [[MASKEDPTR_C:%.*]] = and i64 [[PTRINT_C]], 7 ; CHECK-NEXT: [[MASKEDPTR_C:%.*]] = and i64 [[PTRINT_C]], 7
; CHECK-NEXT: [[MASKCOND_C:%.*]] = icmp eq i64 [[MASKEDPTR_C]], 0 ; CHECK-NEXT: [[MASKCOND_C:%.*]] = icmp eq i64 [[MASKEDPTR_C]], 0
; CHECK-NEXT: tail call void @llvm.assume(i1 [[MASKCOND_C]]) ; CHECK-NEXT: tail call void @llvm.assume(i1 [[MASKCOND_C]])
; CHECK-NEXT: store volatile i64 0, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 0, i64* [[PTR]], align 8
; CHECK-NEXT: store volatile i64 2, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 2, i64* [[PTR]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
br i1 %c, label %true1, label %false1 br i1 %c, label %true1, label %false1
true1: ; preds = %false1, %0 true1: ; preds = %false1, %0
%ptrint = ptrtoint i64* %ptr to i64 %ptrint = ptrtoint i64* %ptr to i64
%maskedptr = and i64 %ptrint, 7 %maskedptr = and i64 %ptrint, 7
%maskcond = icmp eq i64 %maskedptr, 0 %maskcond = icmp eq i64 %maskedptr, 0
tail call void @llvm.assume(i1 %maskcond) tail call void @llvm.assume(i1 %maskcond)
Show All 25 Lines
; CHECK-NEXT: tail call void @llvm.assume(i1 [[MASKCOND]]) ; CHECK-NEXT: tail call void @llvm.assume(i1 [[MASKCOND]])
; CHECK-NEXT: store volatile i64 0, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 0, i64* [[PTR]], align 8
; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; CHECK-NEXT: store volatile i64 3, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 3, i64* [[PTR]], align 8
; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; CHECK: true2.critedge: ; CHECK: true2.critedge:
; CHECK-NEXT: [[PTRINT_C:%.*]] = ptrtoint i64* [[PTR]] to i64 ; CHECK-NEXT: [[PTRINT_C:%.*]] = ptrtoint i64* [[PTR]] to i64
; CHECK-NEXT: [[MASKEDPTR_C:%.*]] = and i64 [[PTRINT_C]], 7 ; CHECK-NEXT: [[MASKEDPTR_C:%.*]] = and i64 [[PTRINT_C]], 7
; CHECK-NEXT: [[MASKCOND_C:%.*]] = icmp eq i64 [[MASKEDPTR_C]], 0 ; CHECK-NEXT: [[MASKCOND_C:%.*]] = icmp eq i64 [[MASKEDPTR_C]], 0
; CHECK-NEXT: tail call void @llvm.assume(i1 [[MASKCOND_C]]) ; CHECK-NEXT: tail call void @llvm.assume(i1 [[MASKCOND_C]])
; CHECK-NEXT: store volatile i64 0, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 0, i64* [[PTR]], align 8
; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; CHECK-NEXT: store volatile i64 2, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 2, i64* [[PTR]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
br i1 %c, label %true1, label %false1 br i1 %c, label %true1, label %false1
true1: ; preds = %false1, %0 true1: ; preds = %false1, %0
%ptrint = ptrtoint i64* %ptr to i64 %ptrint = ptrtoint i64* %ptr to i64
%maskedptr = and i64 %ptrint, 7 %maskedptr = and i64 %ptrint, 7
%maskcond = icmp eq i64 %maskedptr, 0 %maskcond = icmp eq i64 %maskedptr, 0
tail call void @llvm.assume(i1 %maskcond) tail call void @llvm.assume(i1 %maskcond)
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; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; CHECK-NEXT: br i1 [[C]], label [[TRUE2:%.*]], label [[FALSE2:%.*]] ; CHECK-NEXT: br i1 [[C]], label [[TRUE2:%.*]], label [[FALSE2:%.*]]
; CHECK: false1: ; CHECK: false1:
; CHECK-NEXT: store volatile i64 1, i64* [[PTR]], align 4 ; CHECK-NEXT: store volatile i64 1, i64* [[PTR]], align 4
; CHECK-NEXT: br label [[TRUE1]] ; CHECK-NEXT: br label [[TRUE1]]
; CHECK: common.ret:
; CHECK-NEXT: ret void
; CHECK: true2: ; CHECK: true2:
; CHECK-NEXT: store volatile i64 2, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 2, i64* [[PTR]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: false2: ; CHECK: false2:
; CHECK-NEXT: store volatile i64 3, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 3, i64* [[PTR]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
br i1 %c, label %true1, label %false1 br i1 %c, label %true1, label %false1
true1: ; preds = %false1, %0 true1: ; preds = %false1, %0
%ptrint = ptrtoint i64* %ptr to i64 %ptrint = ptrtoint i64* %ptr to i64
%maskedptr = and i64 %ptrint, 7 %maskedptr = and i64 %ptrint, 7
%maskcond = icmp eq i64 %maskedptr, 0 %maskcond = icmp eq i64 %maskedptr, 0
tail call void @llvm.assume(i1 %maskcond) tail call void @llvm.assume(i1 %maskcond)
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[P]]) ; CHECK-NEXT: tail call void @llvm.assume(i1 [[P]])
; CHECK-NEXT: store volatile i64 0, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 0, i64* [[PTR]], align 8
; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; CHECK-NEXT: store volatile i64 3, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 3, i64* [[PTR]], align 8
; CHECK-NEXT: br label [[COMMON_RET:%.*]]
; CHECK: common.ret:
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; CHECK: true2.critedge: ; CHECK: true2.critedge:
; CHECK-NEXT: [[VTABLEI8_C:%.*]] = bitcast [3 x i8*]* [[VTABLE]] to i8* ; CHECK-NEXT: [[VTABLEI8_C:%.*]] = bitcast [3 x i8*]* [[VTABLE]] to i8*
; CHECK-NEXT: [[P_C:%.*]] = call i1 @llvm.type.test(i8* [[VTABLEI8_C]], metadata !"foo") ; CHECK-NEXT: [[P_C:%.*]] = call i1 @llvm.type.test(i8* [[VTABLEI8_C]], metadata !"foo")
; CHECK-NEXT: tail call void @llvm.assume(i1 [[P_C]]) ; CHECK-NEXT: tail call void @llvm.assume(i1 [[P_C]])
; CHECK-NEXT: store volatile i64 0, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 0, i64* [[PTR]], align 8
; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
; CHECK-NEXT: store volatile i64 2, i64* [[PTR]], align 8 ; CHECK-NEXT: store volatile i64 2, i64* [[PTR]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: br label [[COMMON_RET]]
; ;
br i1 %c, label %true1, label %false1 br i1 %c, label %true1, label %false1
true1: ; preds = %false1, %0 true1: ; preds = %false1, %0
%vtablei8 = bitcast [3 x i8*]* %vtable to i8* %vtablei8 = bitcast [3 x i8*]* %vtable to i8*
%p = call i1 @llvm.type.test(i8* %vtablei8, metadata !"foo") %p = call i1 @llvm.type.test(i8* %vtablei8, metadata !"foo")
tail call void @llvm.assume(i1 %p) tail call void @llvm.assume(i1 %p)
store volatile i64 0, i64* %ptr, align 8 store volatile i64 0, i64* %ptr, align 8
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