[SimplifyCFG] Tail-merging all blocks with `ret` terminator

[lebedev.ri]

Summary

Based ontop of D104598, which is a NFCI-ish refactoring.
Here, a restriction, that only empty blocks can be merged, is lifted.

[lebedev.ri]

Split off mostly NFC refactor into a separate change.

[lebedev.ri]

Autogenerate more, but still not all, affected codegen tests.

[rnk]

I think this is reasonable: later cfg simplifications will tail merge the preceding instructions and delete dbg.values appropriately. I didn't hit "accept" since the tests don't all pass yet.

llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-condbr-lower-tree.ll

37 ↗

(On Diff #353229)

This transform has the potential to make it harder to recognize some tail calls during codegen, but it's clear from this test that codegen is already smart enough to handle this case. I don't think any change is needed.

llvm/test/CodeGen/ARM/smml.ll

168 ↗

(On Diff #353229)

I can't understand why these checks disappeared. Is this a bug in the check generation script?

llvm/test/Transforms/PruneEH/ipo-nounwind.ll

33

Seems like another update bug.

[lebedev.ri]

In D104597#2834705, @rnk wrote:

I think this is reasonable: later cfg simplifications will tail merge the preceding instructions and delete dbg.values appropriately. I didn't hit "accept" since the tests don't all pass yet.

Thank you for taking a look!
This is a much warmer reaction than i was expecting.

Autogenerated a few more tests. Still a few more to go.

[lebedev.ri]

@rnk done, all tests updated.

[dmgreen]

Some of the test changes here look really ropy, but the performance benchmarks I tested was entirely flat, and codesize neither improved nor regressed by any significant amount.

There are some tests in here, notably the ifcvt ones, that no longer seem to be testing what they were originally intending to test.

llvm/test/CodeGen/AArch64/arm64-instruction-mix-remarks.ll

42 ↗

(On Diff #353962)

I don't know this test, but what happened to this store?

llvm/test/CodeGen/ARM/smml.ll

67 ↗

(On Diff #353962)

These look like they can share CHECK-V6V7?

84 ↗

(On Diff #353962)

Is this left over?

[rnk]

I'm pretty sure Clang generates a single return block, so this change alone probably won't affect any C/C++ benchmarks. Most of the affected tests are manually written IR, where LLVM developers tend to use multiple ret terminators for simplicity.

I believe Clang also uses a single resume block, but I could be wrong.

[lebedev.ri]

@dmgreen thank you for taking a look! Tidyed-up the two tests you pointed out, hopefully it's better now.

@rnk do tell if there was something else i was supposed to do here..

[dmgreen]

In D104597#2837100, @rnk wrote:

I'm pretty sure Clang generates a single return block, so this change alone probably won't affect any C/C++ benchmarks. Most of the affected tests are manually written IR, where LLVM developers tend to use multiple ret terminators for simplicity.

I believe Clang also uses a single resume block, but I could be wrong.

Ah. That would explain the performance being flat. Codesize is different enough to suggest something is changing, but it's not enough of a difference to worry about.

[rnk]

lgtm

[fhahn]

llvm/test/CodeGen/AArch64/swifterror.ll

429 ↗

(On Diff #354075)

I noticed you auto-generated the tests for this file and the GlobalISel version. It looks like those tests intentionally only checked the relevant parts related to swifterror, but now the checks are much more verbose (and much more prone to needing updating, because they check lots of 'uninteresting things).

Given that only a few lines out of ~2000 needed updating, I am wondering if it would be better to keep the hand-written checks and just update the failing line? Going forward, I think the auto-generated ones will need updating much more frequently now. Granted it is easy to update them, but it still creates noise in diffs and in theory would require careful checking.

[fhahn]

llvm/test/CodeGen/AArch64/swifterror.ll

429 ↗

(On Diff #354075)

(The original checks also had comments interleaved to explain what is being checked. It looks like they are now all before the auto-generated check lines)

[lebedev.ri]

@rnk thank you for the review!

Address nit from @fhahn.

[fhahn]

Great, thanks!

llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp

 //   * Eliminates PHI nodes for basic blocks with a single predecessor.
 //   * Eliminates a basic block that only contains an unconditional branch.
 //   * Changes invoke instructions to nounwind functions to be calls.
 //   * Change things like "if (x) if (y)" into "if (x&y)".
 //   * etc..
 //
 //===----------------------------------------------------------------------===//
 
+#include "llvm/ADT/MapVector.h"
 #include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/Analysis/AssumptionCache.h"
 #include "llvm/Analysis/CFG.h"
 #include "llvm/Analysis/DomTreeUpdater.h"
 #include "llvm/Analysis/GlobalsModRef.h"
 #include "llvm/Analysis/TargetTransformInfo.h"

 
 static cl::opt<bool> UserSinkCommonInsts(
     "sink-common-insts", cl::Hidden, cl::init(false),
     cl::desc("Sink common instructions (default = false)"));
 
 
 STATISTIC(NumSimpl, "Number of blocks simplified");
 
-/// If we have more than one empty (other than phi node) return blocks,
-/// merge them together to promote recursive block merging.
-static bool mergeEmptyReturnBlocks(Function &F, DomTreeUpdater *DTU) {
-  bool Changed = false;
+static bool tailMergeBlocksWithSimilarFunctionTerminators(Function &F,
+                                                          DomTreeUpdater *DTU) {
+  SmallMapVector<unsigned /*TerminatorOpcode*/, SmallVector<BasicBlock *, 2>, 4>
+      Structure;
 
-  std::vector<DominatorTree::UpdateType> Updates;
-  SmallVector<BasicBlock *, 8> DeadBlocks;
+  // Scan all the blocks in the function, record the interesting-ones.
+  for (BasicBlock &BB : F) {
+    if (DTU && DTU->isBBPendingDeletion(&BB))
+      continue;
 
-  BasicBlock *RetBlock = nullptr;
+    // We are only interested in function-terminating blocks.
+    if (!succ_empty(&BB))
+      continue;
 
-  // Scan all the blocks in the function, looking for empty return blocks.
-  for (BasicBlock &BB : make_early_inc_range(F)) {
-    if (DTU && DTU->isBBPendingDeletion(&BB))
+    auto *Term = BB.getTerminator();
+
+    // Fow now only support `ret` function terminators.
+    // FIXME: lift this restriction.
+    if (Term->getOpcode() != Instruction::Ret)
       continue;
 
-    // Only look at return blocks.
-    ReturnInst *Ret = dyn_cast<ReturnInst>(BB.getTerminator());
-    if (!Ret) continue;
-
-    // Only look at the block if it is empty or the only other thing in it is a
-    // single PHI node that is the operand to the return.
-    if (Ret != &BB.front()) {
-      // Check for something else in the block.
-      BasicBlock::iterator I(Ret);
-      --I;
-      // Skip over debug info.
-      while (isa<DbgInfoIntrinsic>(I) && I != BB.begin())
-        --I;
-      if (!isa<DbgInfoIntrinsic>(I) &&
-          (!isa<PHINode>(I) || I != BB.begin() || Ret->getNumOperands() == 0 ||
-           Ret->getOperand(0) != &*I))
-        continue;
-    }
+    // We can't tail-merge block that contains a musttail call.
+    if (BB.getTerminatingMustTailCall())
 
-    // If this is the first returning block, remember it and keep going.
-    if (!RetBlock) {
-      RetBlock = &BB;
+    // Calls to experimental_deoptimize must be followed by a return
+    // of the value computed by experimental_deoptimize.
+    // I.e., we can not change `ret` to `br` for this block.
+    if (auto *CI =
+            dyn_cast_or_null<CallInst>(Term->getPrevNonDebugInstruction())) {
+      if (Function *F = CI->getCalledFunction())
+        if (Intrinsic::ID ID = F->getIntrinsicID())
+          if (ID == Intrinsic::experimental_deoptimize)
             continue;
     }
 
-    // Skip merging if this would result in a CallBr instruction with a
-    // duplicate destination. FIXME: See note in CodeGenPrepare.cpp.
-    bool SkipCallBr = false;
-    for (pred_iterator PI = pred_begin(&BB), E = pred_end(&BB);
-         PI != E && !SkipCallBr; ++PI) {
-      if (auto *CBI = dyn_cast<CallBrInst>((*PI)->getTerminator()))
-        for (unsigned i = 0, e = CBI->getNumSuccessors(); i != e; ++i)
-          if (RetBlock == CBI->getSuccessor(i)) {
-            SkipCallBr = true;
-            break;
-          }
-    }
-    if (SkipCallBr)
+    // PHI nodes cannot have token type, so if the terminator has an operand
+    // with token type, we can not tail-merge this kind of function terminators.
+    if (any_of(Term->operands(),
+               [](Value *Op) { return Op->getType()->isTokenTy(); }))
+      continue;
+
+    // Canonical blocks are uniqued based on the terminator type (opcode).
+    Structure[Term->getOpcode()].emplace_back(&BB);
+
+  bool Changed = false;
+
+  std::vector<DominatorTree::UpdateType> Updates;
+
+  for (ArrayRef<BasicBlock *> BBs : make_second_range(Structure)) {
+    BasicBlock *CanonicalBB = nullptr;
+    SmallVector<PHINode *, 1> Ops;
+
+    // We don't want to change IR just because we can.
+    // Only do that if there are at least two blocks we'll tail-merge.
+    if (BBs.size() < 2)
       continue;
 
-    // Otherwise, we found a duplicate return block.  Merge the two.
     Changed = true;
 
-    // Case when there is no input to the return or when the returned values
-    // agree is trivial.  Note that they can't agree if there are phis in the
-    // blocks.
-    if (Ret->getNumOperands() == 0 ||
-        Ret->getOperand(0) ==
-          cast<ReturnInst>(RetBlock->getTerminator())->getOperand(0)) {
-      // All predecessors of BB should now branch to RetBlock instead.
-      if (DTU) {
-        SmallPtrSet<BasicBlock *, 2> PredsOfBB(pred_begin(&BB), pred_end(&BB));
-        SmallPtrSet<BasicBlock *, 2> PredsOfRetBlock(pred_begin(RetBlock),
-                                                     pred_end(RetBlock));
-        Updates.reserve(Updates.size() + 2 * PredsOfBB.size());
-        for (auto *Predecessor : PredsOfBB)
-          // But, iff Predecessor already branches to RetBlock,
-          // don't (re-)add DomTree edge, because it already exists.
-          if (!PredsOfRetBlock.contains(Predecessor))
-            Updates.push_back({DominatorTree::Insert, Predecessor, RetBlock});
-        for (auto *Predecessor : PredsOfBB)
-          Updates.push_back({DominatorTree::Delete, Predecessor, &BB});
-      }
-      BB.replaceAllUsesWith(RetBlock);
-      DeadBlocks.emplace_back(&BB);
-      continue;
-    }
+    if (DTU)
+      Updates.reserve(Updates.size() + BBs.size());
 
-    // If the canonical return block has no PHI node, create one now.
-    PHINode *RetBlockPHI = dyn_cast<PHINode>(RetBlock->begin());
-    if (!RetBlockPHI) {
-      Value *InVal = cast<ReturnInst>(RetBlock->getTerminator())->getOperand(0);
-      pred_iterator PB = pred_begin(RetBlock), PE = pred_end(RetBlock);
-      RetBlockPHI = PHINode::Create(Ret->getOperand(0)->getType(),
-                                    std::distance(PB, PE), "merge",
-                                    &RetBlock->front());
-
-      for (pred_iterator PI = PB; PI != PE; ++PI)
-        RetBlockPHI->addIncoming(InVal, *PI);
-      RetBlock->getTerminator()->setOperand(0, RetBlockPHI);
-    }
-
-    // Turn BB into a block that just unconditionally branches to the return
-    // block.  This handles the case when the two return blocks have a common
-    // predecessor but that return different things.
-    RetBlockPHI->addIncoming(Ret->getOperand(0), &BB);
-    BB.getTerminator()->eraseFromParent();
-    BranchInst::Create(RetBlock, &BB);
+    for (BasicBlock *BB : BBs) {
+      auto *Term = BB->getTerminator();
+
+      // Do we already have a canonical block for this function terminator type?
+      if (CanonicalBB == nullptr) {
+        // We do not. Create one now.
+        CanonicalBB = BasicBlock::Create(
+            F.getContext(), Twine("common.") + Term->getOpcodeName(), &F);
+        // We'll also need a PHI node per each operand of the terminator.
+        Ops.resize(Term->getNumOperands());
+        for (auto I : zip(Term->operands(), Ops)) {
+          std::get<1>(I) = PHINode::Create(std::get<0>(I)->getType(),
+                                           /*NumReservedValues=*/BBs.size(),
+                                           CanonicalBB->getName() + ".op");
+          CanonicalBB->getInstList().push_back(std::get<1>(I));
+        }
+        // Make it so that this canonical block actually has the right
+        // terminator.
+        auto *CanonicalTerm = Term->clone();
+        CanonicalBB->getInstList().push_back(CanonicalTerm);
+        // If the canonical terminator has operands, rewrite it to take PHI's.
+        for (auto I : zip(Ops, CanonicalTerm->operands()))
+          std::get<1>(I) = std::get<0>(I);
+      }
+
+      // Aha, found a new non-canonical function terminator.
+      // If it has operands, forward them to the PHI nodes in the canonical
+      // block.
+      for (auto I : zip(Term->operands(), Ops))
+        std::get<1>(I)->addIncoming(std::get<0>(I), BB);
+
+      // And turn BB into a block that just unconditionally branches
+      // to the canonical block.
+      Term->eraseFromParent();
+      BranchInst::Create(CanonicalBB, BB);
       if (DTU)
-      Updates.push_back({DominatorTree::Insert, &BB, RetBlock});
+        Updates.push_back({DominatorTree::Insert, BB, CanonicalBB});
+    }
   }
 
   if (DTU)
     DTU->applyUpdates(Updates);
 
-  DeleteDeadBlocks(DeadBlocks, DTU);
-
   return Changed;
 }
 
 /// Call SimplifyCFG on all the blocks in the function,
 /// iterating until no more changes are made.
 static bool iterativelySimplifyCFG(Function &F, const TargetTransformInfo &TTI,
                                    DomTreeUpdater *DTU,
                                    const SimplifyCFGOptions &Options) {

 }
 
 static bool simplifyFunctionCFGImpl(Function &F, const TargetTransformInfo &TTI,
                                     DominatorTree *DT,
                                     const SimplifyCFGOptions &Options) {
   DomTreeUpdater DTU(DT, DomTreeUpdater::UpdateStrategy::Eager);
 
   bool EverChanged = removeUnreachableBlocks(F, DT ? &DTU : nullptr);
-  EverChanged |= mergeEmptyReturnBlocks(F, DT ? &DTU : nullptr);
+  EverChanged |=
+      tailMergeBlocksWithSimilarFunctionTerminators(F, DT ? &DTU : nullptr);
   EverChanged |= iterativelySimplifyCFG(F, TTI, DT ? &DTU : nullptr, Options);
 
   // If neither pass changed anything, we're done.
   if (!EverChanged) return false;
 
   // iterativelySimplifyCFG can (rarely) make some loops dead.  If this happens,
   // removeUnreachableBlocks is needed to nuke them, which means we should
   // iterate between the two optimizations.  We structure the code like this to

llvm/test/CodeGen/AArch64/branch-relax-cbz.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=aarch64-apple-darwin -aarch64-cbz-offset-bits=3 < %s | FileCheck %s
 
 
 define void @split_block_no_fallthrough(i64 %val) #0 {
 ; CHECK-LABEL: split_block_no_fallthrough:
 ; CHECK:       ; %bb.0: ; %bb
 ; CHECK-NEXT:    stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
 ; CHECK-NEXT:    cmn x0, #5 ; =5
 ; CHECK-NEXT:    b.le LBB0_3
 ; CHECK-NEXT:  ; %bb.1: ; %b3
 ; CHECK-NEXT:    ldr w8, [x8]
 ; CHECK-NEXT:    cbnz w8, LBB0_2
 ; CHECK-NEXT:    b LBB0_4
-; CHECK-NEXT:  LBB0_2: ; %b8
+; CHECK-NEXT:  LBB0_2: ; %common.ret
 ; CHECK-NEXT:    ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
 ; CHECK-NEXT:    ret
 ; CHECK-NEXT:  LBB0_3: ; %b2
 ; CHECK-NEXT:    mov w0, #93
 ; CHECK-NEXT:    bl _extfunc
 ; CHECK-NEXT:    cbnz w0, LBB0_2
 ; CHECK-NEXT:  LBB0_4: ; %b7
 ; CHECK-NEXT:    mov w0, #13

llvm/test/CodeGen/AArch64/cgp-usubo.ll

 declare void @call(i1)
 
 define i1 @usubo_ult_sub_dominates_i64(i64 %x, i64 %y, i64* %p, i1 %cond) nounwind {
 ; CHECK-LABEL: usubo_ult_sub_dominates_i64:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    tbz w3, #0, .LBB7_2
 ; CHECK-NEXT:  // %bb.1: // %t
 ; CHECK-NEXT:    subs x8, x0, x1
-; CHECK-NEXT:    cset w0, lo
+; CHECK-NEXT:    cset w3, lo
 ; CHECK-NEXT:    str x8, [x2]
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB7_2: // %f
+; CHECK-NEXT:  .LBB7_2: // %common.ret
 ; CHECK-NEXT:    and w0, w3, #0x1
 ; CHECK-NEXT:    ret
 entry:
   br i1 %cond, label %t, label %f
 
 t:
   %s = sub i64 %x, %y
   store i64 %s, i64* %p
   br i1 %cond, label %end, label %f
 
 f:
   ret i1 %cond
 
 end:
   %ov = icmp ult i64 %x, %y
   ret i1 %ov
 }
 
 define i1 @usubo_ult_cmp_dominates_i64(i64 %x, i64 %y, i64* %p, i1 %cond) nounwind {
 ; CHECK-LABEL: usubo_ult_cmp_dominates_i64:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    str x30, [sp, #-48]! // 8-byte Folded Spill
+; CHECK-NEXT:    stp x30, x23, [sp, #-48]! // 16-byte Folded Spill
 ; CHECK-NEXT:    stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-NEXT:    mov w20, w3
+; CHECK-NEXT:    mov w19, w3
 ; CHECK-NEXT:    stp x22, x21, [sp, #16] // 16-byte Folded Spill
 ; CHECK-NEXT:    tbz w3, #0, .LBB8_3
 ; CHECK-NEXT:  // %bb.1: // %t
 ; CHECK-NEXT:    cmp x0, x1
-; CHECK-NEXT:    mov x22, x0
-; CHECK-NEXT:    cset w0, lo
-; CHECK-NEXT:    mov x19, x2
-; CHECK-NEXT:    mov x21, x1
+; CHECK-NEXT:    cset w21, lo
+; CHECK-NEXT:    mov x23, x0
+; CHECK-NEXT:    mov w0, w21
+; CHECK-NEXT:    mov x20, x2
+; CHECK-NEXT:    mov x22, x1
 ; CHECK-NEXT:    bl call
-; CHECK-NEXT:    subs x8, x22, x21
+; CHECK-NEXT:    subs x8, x23, x22
 ; CHECK-NEXT:    b.hs .LBB8_3
 ; CHECK-NEXT:  // %bb.2: // %end
-; CHECK-NEXT:    cset w0, lo
-; CHECK-NEXT:    str x8, [x19]
-; CHECK-NEXT:    b .LBB8_4
-; CHECK-NEXT:  .LBB8_3: // %f
-; CHECK-NEXT:    and w0, w20, #0x1
-; CHECK-NEXT:  .LBB8_4: // %f
+; CHECK-NEXT:    mov w19, w21
+; CHECK-NEXT:    str x8, [x20]
+; CHECK-NEXT:  .LBB8_3: // %common.ret
+; CHECK-NEXT:    and w0, w19, #0x1
 ; CHECK-NEXT:    ldp x20, x19, [sp, #32] // 16-byte Folded Reload
 ; CHECK-NEXT:    ldp x22, x21, [sp, #16] // 16-byte Folded Reload
-; CHECK-NEXT:    ldr x30, [sp], #48 // 8-byte Folded Reload
+; CHECK-NEXT:    ldp x30, x23, [sp], #48 // 16-byte Folded Reload
 ; CHECK-NEXT:    ret
 entry:
   br i1 %cond, label %t, label %f
 
 t:
   %ov = icmp ult i64 %x, %y
   call void @call(i1 %ov)
   br i1 %ov, label %end, label %f

llvm/test/CodeGen/AArch64/implicit-null-check.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -verify-machineinstrs -O3 -mtriple=aarch64-unknown-unknown -enable-implicit-null-checks | FileCheck %s
 
 ; Basic test for implicit null check conversion - this is analogous to the
 ; file with the same name in the X86 tree, but adjusted to remove patterns
 ; related to memory folding of arithmetic (since aarch64 doesn't), and add
 ; a couple of aarch64 specific tests.
 
 define i32 @imp_null_check_load_fallthrough(i32* %x) {
 ; CHECK-LABEL: imp_null_check_load_fallthrough:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:  .Ltmp0:
 ; CHECK-NEXT:    ldr w0, [x0] // on-fault: .LBB0_2
 ; CHECK-NEXT:  // %bb.1: // %not_null
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB0_2: // %is_null
+; CHECK-NEXT:  .LBB0_2:
 ; CHECK-NEXT:    mov w0, #42
 ; CHECK-NEXT:    ret
  entry:
   %c = icmp eq i32* %x, null
   br i1 %c, label %is_null, label %not_null, !make.implicit !0
 
  not_null:
   %t = load i32, i32* %x
   ret i32 %t
 
 is_null:
   ret i32 42
 }
 
 
 define i32 @imp_null_check_load_reorder(i32* %x) {
 ; CHECK-LABEL: imp_null_check_load_reorder:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:  .Ltmp1:
 ; CHECK-NEXT:    ldr w0, [x0] // on-fault: .LBB1_2
 ; CHECK-NEXT:  // %bb.1: // %not_null
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB1_2: // %is_null
+; CHECK-NEXT:  .LBB1_2:
 ; CHECK-NEXT:    mov w0, #42
 ; CHECK-NEXT:    ret
  entry:
   %c = icmp eq i32* %x, null
   br i1 %c, label %is_null, label %not_null, !make.implicit !0
 
  is_null:
   ret i32 42
 
  not_null:
   %t = load i32, i32* %x
   ret i32 %t
 }
 
 define i32 @imp_null_check_unordered_load(i32* %x) {
 ; CHECK-LABEL: imp_null_check_unordered_load:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:  .Ltmp2:
 ; CHECK-NEXT:    ldr w0, [x0] // on-fault: .LBB2_2
 ; CHECK-NEXT:  // %bb.1: // %not_null
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB2_2: // %is_null
+; CHECK-NEXT:  .LBB2_2:
 ; CHECK-NEXT:    mov w0, #42
 ; CHECK-NEXT:    ret
  entry:
   %c = icmp eq i32* %x, null
   br i1 %c, label %is_null, label %not_null, !make.implicit !0
 
  is_null:
   ret i32 42
 
  not_null:
   %t = load atomic i32, i32* %x unordered, align 4
   ret i32 %t
 }
 
 
 ; TODO: Can be converted into implicit check.
 ;; Probably could be implicit, but we're conservative for now
 define i32 @imp_null_check_seq_cst_load(i32* %x) {
 ; CHECK-LABEL: imp_null_check_seq_cst_load:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    cbz x0, .LBB3_2
 ; CHECK-NEXT:  // %bb.1: // %not_null
 ; CHECK-NEXT:    ldar w0, [x0]
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB3_2: // %is_null
+; CHECK-NEXT:  .LBB3_2:
 ; CHECK-NEXT:    mov w0, #42
 ; CHECK-NEXT:    ret
  entry:
   %c = icmp eq i32* %x, null
   br i1 %c, label %is_null, label %not_null, !make.implicit !0
 
  is_null:
   ret i32 42
 
  not_null:
   %t = load atomic i32, i32* %x seq_cst, align 4
   ret i32 %t
 }
 
 ;; Might be memory mapped IO, so can't rely on fault behavior
 define i32 @imp_null_check_volatile_load(i32* %x) {
 ; CHECK-LABEL: imp_null_check_volatile_load:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    cbz x0, .LBB4_2
 ; CHECK-NEXT:  // %bb.1: // %not_null
 ; CHECK-NEXT:    ldr w0, [x0]
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB4_2: // %is_null
+; CHECK-NEXT:  .LBB4_2:
 ; CHECK-NEXT:    mov w0, #42
 ; CHECK-NEXT:    ret
  entry:
   %c = icmp eq i32* %x, null
   br i1 %c, label %is_null, label %not_null, !make.implicit !0
 
  is_null:
   ret i32 42
 
  not_null:
   %t = load volatile i32, i32* %x, align 4
   ret i32 %t
 }
 
 
 define i8 @imp_null_check_load_i8(i8* %x) {
 ; CHECK-LABEL: imp_null_check_load_i8:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:  .Ltmp3:
 ; CHECK-NEXT:    ldrb w0, [x0] // on-fault: .LBB5_2
 ; CHECK-NEXT:  // %bb.1: // %not_null
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB5_2: // %is_null
+; CHECK-NEXT:  .LBB5_2:
 ; CHECK-NEXT:    mov w0, #42
 ; CHECK-NEXT:    ret
  entry:
   %c = icmp eq i8* %x, null
   br i1 %c, label %is_null, label %not_null, !make.implicit !0
 
  is_null:
   ret i8 42
 
  not_null:
   %t = load i8, i8* %x
   ret i8 %t
 }
 
 define i256 @imp_null_check_load_i256(i256* %x) {
 ; CHECK-LABEL: imp_null_check_load_i256:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    cbz x0, .LBB6_2
 ; CHECK-NEXT:  // %bb.1: // %not_null
-; CHECK-NEXT:    ldp x8, x1, [x0]
 ; CHECK-NEXT:    ldp x2, x3, [x0, #16]
-; CHECK-NEXT:    mov x0, x8
+; CHECK-NEXT:    ldp x0, x1, [x0]
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB6_2: // %is_null
-; CHECK-NEXT:    mov w0, #42
+; CHECK-NEXT:  .LBB6_2:
 ; CHECK-NEXT:    mov x1, xzr
 ; CHECK-NEXT:    mov x2, xzr
 ; CHECK-NEXT:    mov x3, xzr
+; CHECK-NEXT:    mov w0, #42
 ; CHECK-NEXT:    ret
  entry:
   %c = icmp eq i256* %x, null
   br i1 %c, label %is_null, label %not_null, !make.implicit !0
 
  is_null:
   ret i256 42
 
  not_null:
   %t = load i256, i256* %x
   ret i256 %t
 }
 
 
 
 define i32 @imp_null_check_gep_load(i32* %x) {
 ; CHECK-LABEL: imp_null_check_gep_load:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:  .Ltmp4:
 ; CHECK-NEXT:    ldr w0, [x0, #128] // on-fault: .LBB7_2
 ; CHECK-NEXT:  // %bb.1: // %not_null
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB7_2: // %is_null
+; CHECK-NEXT:  .LBB7_2:
 ; CHECK-NEXT:    mov w0, #42
 ; CHECK-NEXT:    ret
  entry:
   %c = icmp eq i32* %x, null
   br i1 %c, label %is_null, label %not_null, !make.implicit !0
 
  is_null:
   ret i32 42
 
  not_null:
   %x.gep = getelementptr i32, i32* %x, i32 32
   %t = load i32, i32* %x.gep
   ret i32 %t
 }
 
 define i32 @imp_null_check_add_result(i32* %x, i32 %p) {
 ; CHECK-LABEL: imp_null_check_add_result:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:  .Ltmp5:
 ; CHECK-NEXT:    ldr w8, [x0] // on-fault: .LBB8_2
 ; CHECK-NEXT:  // %bb.1: // %not_null
 ; CHECK-NEXT:    add w0, w8, w1
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB8_2: // %is_null
+; CHECK-NEXT:  .LBB8_2:
 ; CHECK-NEXT:    mov w0, #42
 ; CHECK-NEXT:    ret
  entry:
   %c = icmp eq i32* %x, null
   br i1 %c, label %is_null, label %not_null, !make.implicit !0
 
  is_null:
   ret i32 42

 ; CHECK-LABEL: imp_null_check_hoist_over_udiv:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:  .Ltmp6:
 ; CHECK-NEXT:    ldr w8, [x0] // on-fault: .LBB9_2
 ; CHECK-NEXT:  // %bb.1: // %not_null
 ; CHECK-NEXT:    udiv w9, w1, w2
 ; CHECK-NEXT:    add w0, w8, w9
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB9_2: // %is_null
+; CHECK-NEXT:  .LBB9_2:
 ; CHECK-NEXT:    mov w0, #42
 ; CHECK-NEXT:    ret
  entry:
   %c = icmp eq i32* %x, null
   br i1 %c, label %is_null, label %not_null, !make.implicit !0
 
  is_null:
   ret i32 42

 ; CHECK-LABEL: imp_null_check_hoist_over_unrelated_load:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    cbz x0, .LBB10_2
 ; CHECK-NEXT:  // %bb.1: // %not_null
 ; CHECK-NEXT:    ldr w8, [x1]
 ; CHECK-NEXT:    ldr w0, [x0]
 ; CHECK-NEXT:    str w8, [x2]
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB10_2: // %is_null
+; CHECK-NEXT:  .LBB10_2:
 ; CHECK-NEXT:    mov w0, #42
 ; CHECK-NEXT:    ret
  entry:
   %c = icmp eq i32* %x, null
   br i1 %c, label %is_null, label %not_null, !make.implicit !0
 
  is_null:
   ret i32 42

 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:  .Ltmp7:
 ; CHECK-NEXT:    ldr w8, [x0] // on-fault: .LBB11_2
 ; CHECK-NEXT:  // %bb.1: // %not_null
 ; CHECK-NEXT:    add w9, w0, w1
 ; CHECK-NEXT:    add w8, w9, w8
 ; CHECK-NEXT:    add w0, w8, #4 // =4
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB11_2: // %is_null
+; CHECK-NEXT:  .LBB11_2:
 ; CHECK-NEXT:    mov w0, #42
 ; CHECK-NEXT:    ret
  entry:
   %c = icmp eq i32* %x, null
   br i1 %c, label %is_null, label %not_null, !make.implicit !0
 
  is_null:
   ret i32 42

 define i32 @imp_null_check_load_fence1(i32* %x) {
 ; CHECK-LABEL: imp_null_check_load_fence1:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    cbz x0, .LBB12_2
 ; CHECK-NEXT:  // %bb.1: // %not_null
 ; CHECK-NEXT:    dmb ishld
 ; CHECK-NEXT:    ldr w0, [x0]
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB12_2: // %is_null
+; CHECK-NEXT:  .LBB12_2:
 ; CHECK-NEXT:    mov w0, #42
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp eq i32* %x, null
   br i1 %c, label %is_null, label %not_null, !make.implicit !0
 
 is_null:
   ret i32 42

 define i32 @imp_null_check_load_fence2(i32* %x) {
 ; CHECK-LABEL: imp_null_check_load_fence2:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    cbz x0, .LBB13_2
 ; CHECK-NEXT:  // %bb.1: // %not_null
 ; CHECK-NEXT:    dmb ish
 ; CHECK-NEXT:    ldr w0, [x0]
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB13_2: // %is_null
+; CHECK-NEXT:  .LBB13_2:
 ; CHECK-NEXT:    mov w0, #42
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp eq i32* %x, null
   br i1 %c, label %is_null, label %not_null, !make.implicit !0
 
 is_null:
   ret i32 42
 
 not_null:
   fence seq_cst
   %t = load i32, i32* %x
   ret i32 %t
 }
 
 ; TODO: We can fold to implicit null here, not sure why this isn't working
 define void @imp_null_check_store(i32* %x) {
 ; CHECK-LABEL: imp_null_check_store:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    cbz x0, .LBB14_2
 ; CHECK-NEXT:  // %bb.1: // %not_null
 ; CHECK-NEXT:    mov w8, #1
 ; CHECK-NEXT:    str w8, [x0]
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB14_2: // %is_null
+; CHECK-NEXT:  .LBB14_2: // %common.ret
 ; CHECK-NEXT:    ret
  entry:
   %c = icmp eq i32* %x, null
   br i1 %c, label %is_null, label %not_null, !make.implicit !0
 
  is_null:
   ret void
 
  not_null:
   store i32 1, i32* %x
   ret void
 }
 
 ;; TODO: can be implicit
 define void @imp_null_check_unordered_store(i32* %x) {
 ; CHECK-LABEL: imp_null_check_unordered_store:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    cbz x0, .LBB15_2
 ; CHECK-NEXT:  // %bb.1: // %not_null
 ; CHECK-NEXT:    mov w8, #1
 ; CHECK-NEXT:    str w8, [x0]
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB15_2: // %is_null
+; CHECK-NEXT:  .LBB15_2: // %common.ret
 ; CHECK-NEXT:    ret
  entry:
   %c = icmp eq i32* %x, null
   br i1 %c, label %is_null, label %not_null, !make.implicit !0
 
  is_null:
   ret void
 
  not_null:
   store atomic i32 1, i32* %x unordered, align 4
   ret void
 }
 
 define i32 @imp_null_check_neg_gep_load(i32* %x) {
 ; CHECK-LABEL: imp_null_check_neg_gep_load:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:  .Ltmp8:
 ; CHECK-NEXT:    ldur w0, [x0, #-128] // on-fault: .LBB16_2
 ; CHECK-NEXT:  // %bb.1: // %not_null
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB16_2: // %is_null
+; CHECK-NEXT:  .LBB16_2:
 ; CHECK-NEXT:    mov w0, #42
 ; CHECK-NEXT:    ret
  entry:
   %c = icmp eq i32* %x, null
   br i1 %c, label %is_null, label %not_null, !make.implicit !0
 
  is_null:
   ret i32 42
 
  not_null:
   %x.gep = getelementptr i32, i32* %x, i32 -32
   %t = load i32, i32* %x.gep
   ret i32 %t
 }
 
 !0 = !{}

llvm/test/CodeGen/AArch64/ldst-opt-after-block-placement.ll

 ; CHECK-NEXT:    b.lt .LBB0_3
 ; CHECK-NEXT:    b .LBB0_4
 ; CHECK-NEXT:  .LBB0_2: // %if.else
 ; CHECK-NEXT:    ldp x8, x9, [x1]
 ; CHECK-NEXT:    cmp x8, x9
 ; CHECK-NEXT:    b.ge .LBB0_4
 ; CHECK-NEXT:  .LBB0_3: // %exit1
 ; CHECK-NEXT:    str xzr, [x1, #8]
-; CHECK-NEXT:  .LBB0_4: // %exit2
+; CHECK-NEXT:  .LBB0_4: // %common.ret
 ; CHECK-NEXT:    ret
 entry:
   br i1 %cond, label %if.then, label %if.else
 
 if.then:
   %0 = getelementptr inbounds i64, i64* %ptr, i64 2
   %1 = load i64, i64* %0, align 8
   store i64 0, i64* %0, align 8

llvm/test/CodeGen/AArch64/ldst-paired-aliasing.ll

 ; CHECK-NEXT:    ldr w8, [sp, #48]
 ; CHECK-NEXT:    cmp w8, #1 // =1
 ; CHECK-NEXT:    b.ne .LBB0_2
 ; CHECK-NEXT:  // %bb.1: // %for.inc
 ; CHECK-NEXT:    bl f
 ; CHECK-NEXT:    b .LBB0_3
 ; CHECK-NEXT:  .LBB0_2: // %if.then
 ; CHECK-NEXT:    bl f2
-; CHECK-NEXT:  .LBB0_3: // %for.inc
+; CHECK-NEXT:  .LBB0_3: // %common.ret
 ; CHECK-NEXT:    ldr x30, [sp, #96] // 8-byte Folded Reload
 ; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    add sp, sp, #112 // =112
 ; CHECK-NEXT:    ret
 
 
 for.body.lr.ph.i.i.i.i.i.i63:
   %b1 = alloca [10 x i32], align 16

llvm/test/CodeGen/AArch64/statepoint-call-lowering.ll

 ; CHECK-NEXT:    str x0, [sp, #8]
 ; CHECK-NEXT:    bl return_i1
 ; CHECK-NEXT:  .Ltmp10:
 ; CHECK-NEXT:    tbz w20, #0, .LBB8_2
 ; CHECK-NEXT:  // %bb.1: // %left
 ; CHECK-NEXT:    mov w19, w0
 ; CHECK-NEXT:    ldr x0, [sp, #8]
 ; CHECK-NEXT:    bl consume
-; CHECK-NEXT:    and w0, w19, #0x1
 ; CHECK-NEXT:    b .LBB8_3
-; CHECK-NEXT:  .LBB8_2: // %right
-; CHECK-NEXT:    mov w0, #1
-; CHECK-NEXT:  .LBB8_3: // %right
+; CHECK-NEXT:  .LBB8_2:
+; CHECK-NEXT:    mov w19, #1
+; CHECK-NEXT:  .LBB8_3: // %common.ret
+; CHECK-NEXT:    and w0, w19, #0x1
 ; CHECK-NEXT:    ldp x20, x19, [sp, #16] // 16-byte Folded Reload
 ; CHECK-NEXT:    ldr x30, [sp], #32 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
 entry:
   %safepoint_token = tail call token (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @return_i1, i32 0, i32 0, i32 0, i32 0) ["gc-live" (i32 addrspace(1)* %a)]
   br i1 %external_cond, label %left, label %right
 
 left:

llvm/test/CodeGen/AArch64/use-cr-result-of-dom-icmp-st.ll

 
 target datalayout = "e-m:e-i64:64-n32:64"
 
 define i64 @ll_a_op_b__2(i64 %a, i64 %b) {
 ; CHECK-LABEL: ll_a_op_b__2:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    lsl x8, x0, x1
 ; CHECK-NEXT:    cmn x8, #2 // =2
-; CHECK-NEXT:    b.le .LBB0_2
-; CHECK-NEXT:  // %bb.1: // %return
-; CHECK-NEXT:    mov x0, x1
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB0_2: // %if.end
-; CHECK-NEXT:    csinc x8, x1, xzr, ge
-; CHECK-NEXT:    mul x0, x8, x0
+; CHECK-NEXT:    csinc x8, x1, xzr, eq
+; CHECK-NEXT:    mul x8, x8, x0
+; CHECK-NEXT:    csel x0, x1, x8, gt
 ; CHECK-NEXT:    ret
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, -2
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp2 = icmp eq i64 %shl, -2
   %mul = select i1 %cmp2, i64 %b, i64 1
   %spec.select = mul nsw i64 %mul, %a
   ret i64 %spec.select
 
 return:                                           ; preds = %entry
   ret i64 %b
 }
 
 define i64 @ll_a_op_b__1(i64 %a, i64 %b) {
 ; CHECK-LABEL: ll_a_op_b__1:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    lsl x8, x0, x1
-; CHECK-NEXT:    tbnz x8, #63, .LBB1_2
-; CHECK-NEXT:  // %bb.1: // %return
-; CHECK-NEXT:    mov x0, x1
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB1_2: // %if.end
 ; CHECK-NEXT:    cmn x8, #1 // =1
-; CHECK-NEXT:    csinc x8, x1, xzr, ge
-; CHECK-NEXT:    mul x0, x8, x0
+; CHECK-NEXT:    csinc x9, x1, xzr, eq
+; CHECK-NEXT:    mul x9, x9, x0
+; CHECK-NEXT:    cmp x8, #0 // =0
+; CHECK-NEXT:    csel x0, x1, x9, ge
 ; CHECK-NEXT:    ret
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, -1
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp2 = icmp eq i64 %shl, -1
   %mul = select i1 %cmp2, i64 %b, i64 1
   %spec.select = mul nsw i64 %mul, %a
   ret i64 %spec.select
 
 return:                                           ; preds = %entry
   ret i64 %b
 }
 
 define i64 @ll_a_op_b_0(i64 %a, i64 %b) {
 ; CHECK-LABEL: ll_a_op_b_0:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    lsl x8, x0, x1
 ; CHECK-NEXT:    cmp x8, #0 // =0
-; CHECK-NEXT:    b.le .LBB2_2
-; CHECK-NEXT:  // %bb.1: // %return
-; CHECK-NEXT:    mov x0, x1
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB2_2: // %if.end
-; CHECK-NEXT:    csinc x8, x1, xzr, ge
-; CHECK-NEXT:    mul x0, x8, x0
+; CHECK-NEXT:    csinc x8, x1, xzr, eq
+; CHECK-NEXT:    mul x8, x8, x0
+; CHECK-NEXT:    csel x0, x1, x8, gt
 ; CHECK-NEXT:    ret
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, 0
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp2 = icmp eq i64 %shl, 0
   %mul = select i1 %cmp2, i64 %b, i64 1
   %spec.select = mul nsw i64 %mul, %a
   ret i64 %spec.select
 
 return:                                           ; preds = %entry
   ret i64 %b
 }
 
 define i64 @ll_a_op_b_1(i64 %a, i64 %b) {
 ; CHECK-LABEL: ll_a_op_b_1:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    lsl x8, x0, x1
 ; CHECK-NEXT:    cmp x8, #1 // =1
-; CHECK-NEXT:    b.le .LBB3_2
-; CHECK-NEXT:  // %bb.1: // %return
-; CHECK-NEXT:    mov x0, x1
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB3_2: // %if.end
-; CHECK-NEXT:    csinc x8, x1, xzr, ge
-; CHECK-NEXT:    mul x0, x8, x0
+; CHECK-NEXT:    csinc x8, x1, xzr, eq
+; CHECK-NEXT:    mul x8, x8, x0
+; CHECK-NEXT:    csel x0, x1, x8, gt
 ; CHECK-NEXT:    ret
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, 1
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp2 = icmp eq i64 %shl, 1
   %mul = select i1 %cmp2, i64 %b, i64 1
   %spec.select = mul nsw i64 %mul, %a
   ret i64 %spec.select
 
 return:                                           ; preds = %entry
   ret i64 %b
 }
 
 define i64 @ll_a_op_b_2(i64 %a, i64 %b) {
 ; CHECK-LABEL: ll_a_op_b_2:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    lsl x8, x0, x1
 ; CHECK-NEXT:    cmp x8, #2 // =2
-; CHECK-NEXT:    b.le .LBB4_2
-; CHECK-NEXT:  // %bb.1: // %return
-; CHECK-NEXT:    mov x0, x1
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB4_2: // %if.end
-; CHECK-NEXT:    csinc x8, x1, xzr, ge
-; CHECK-NEXT:    mul x0, x8, x0
+; CHECK-NEXT:    csinc x8, x1, xzr, eq
+; CHECK-NEXT:    mul x8, x8, x0
+; CHECK-NEXT:    csel x0, x1, x8, gt
 ; CHECK-NEXT:    ret
 entry:
   %shl = shl i64 %a, %b
   %cmp = icmp sgt i64 %shl, 2
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp2 = icmp eq i64 %shl, 2
   %mul = select i1 %cmp2, i64 %b, i64 1
   %spec.select = mul nsw i64 %mul, %a
   ret i64 %spec.select
 
 return:                                           ; preds = %entry
   ret i64 %b
 }
 
 define i64 @ll_a__2(i64 %a, i64 %b) {
 ; CHECK-LABEL: ll_a__2:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    cmn x0, #2 // =2
-; CHECK-NEXT:    b.le .LBB5_2
-; CHECK-NEXT:  // %bb.1: // %return
-; CHECK-NEXT:    mov x0, x1
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB5_2: // %if.end
-; CHECK-NEXT:    csinc x8, x1, xzr, ge
-; CHECK-NEXT:    mul x0, x8, x0
+; CHECK-NEXT:    csinc x8, x1, xzr, eq
+; CHECK-NEXT:    mul x8, x8, x0
+; CHECK-NEXT:    csel x0, x1, x8, gt
 ; CHECK-NEXT:    ret
 entry:
   %cmp = icmp sgt i64 %a, -2
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp1 = icmp eq i64 %a, -2
   %mul = select i1 %cmp1, i64 %b, i64 1
   %spec.select = mul nsw i64 %mul, %a
   ret i64 %spec.select
 
 return:                                           ; preds = %entry
   ret i64 %b
 }
 
 define i64 @ll_a__1(i64 %a, i64 %b) {
 ; CHECK-LABEL: ll_a__1:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    tbnz x0, #63, .LBB6_2
-; CHECK-NEXT:  // %bb.1: // %return
-; CHECK-NEXT:    mov x0, x1
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB6_2: // %if.end
 ; CHECK-NEXT:    cmn x0, #1 // =1
-; CHECK-NEXT:    csinc x8, x1, xzr, ge
-; CHECK-NEXT:    mul x0, x8, x0
+; CHECK-NEXT:    csinc x8, x1, xzr, eq
+; CHECK-NEXT:    mul x8, x8, x0
+; CHECK-NEXT:    cmp x0, #0 // =0
+; CHECK-NEXT:    csel x0, x1, x8, ge
 ; CHECK-NEXT:    ret
 entry:
   %cmp = icmp sgt i64 %a, -1
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp1 = icmp eq i64 %a, -1
   %mul = select i1 %cmp1, i64 %b, i64 1
   %spec.select = mul nsw i64 %mul, %a
   ret i64 %spec.select
 
 return:                                           ; preds = %entry
   ret i64 %b
 }
 
 define i64 @ll_a_0(i64 %a, i64 %b) {
 ; CHECK-LABEL: ll_a_0:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    cmp x0, #0 // =0
-; CHECK-NEXT:    b.le .LBB7_2
-; CHECK-NEXT:  // %bb.1: // %return
-; CHECK-NEXT:    mov x0, x1
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB7_2: // %if.end
-; CHECK-NEXT:    csinc x8, x1, xzr, ge
-; CHECK-NEXT:    mul x0, x8, x0
+; CHECK-NEXT:    csinc x8, x1, xzr, eq
+; CHECK-NEXT:    mul x8, x8, x0
+; CHECK-NEXT:    csel x0, x1, x8, gt
 ; CHECK-NEXT:    ret
 entry:
   %cmp = icmp sgt i64 %a, 0
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp1 = icmp eq i64 %a, 0
   %mul = select i1 %cmp1, i64 %b, i64 1
   %spec.select = mul nsw i64 %mul, %a
   ret i64 %spec.select
 
 return:                                           ; preds = %entry
   ret i64 %b
 }
 
 define i64 @ll_a_1(i64 %a, i64 %b) {
 ; CHECK-LABEL: ll_a_1:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    cmp x0, #1 // =1
-; CHECK-NEXT:    b.le .LBB8_2
-; CHECK-NEXT:  // %bb.1: // %return
-; CHECK-NEXT:    mov x0, x1
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB8_2: // %if.end
-; CHECK-NEXT:    csinc x8, x1, xzr, ge
-; CHECK-NEXT:    mul x0, x8, x0
+; CHECK-NEXT:    csinc x8, x1, xzr, eq
+; CHECK-NEXT:    mul x8, x8, x0
+; CHECK-NEXT:    csel x0, x1, x8, gt
 ; CHECK-NEXT:    ret
 entry:
   %cmp = icmp sgt i64 %a, 1
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp1 = icmp eq i64 %a, 1
   %mul = select i1 %cmp1, i64 %b, i64 1
   %spec.select = mul nsw i64 %mul, %a
   ret i64 %spec.select
 
 return:                                           ; preds = %entry
   ret i64 %b
 }
 
 define i64 @ll_a_2(i64 %a, i64 %b) {
 ; CHECK-LABEL: ll_a_2:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    cmp x0, #2 // =2
-; CHECK-NEXT:    b.le .LBB9_2
-; CHECK-NEXT:  // %bb.1: // %return
-; CHECK-NEXT:    mov x0, x1
-; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB9_2: // %if.end
-; CHECK-NEXT:    csinc x8, x1, xzr, ge
-; CHECK-NEXT:    mul x0, x8, x0
+; CHECK-NEXT:    csinc x8, x1, xzr, eq
+; CHECK-NEXT:    mul x8, x8, x0
+; CHECK-NEXT:    csel x0, x1, x8, gt
 ; CHECK-NEXT:    ret
 entry:
   %cmp = icmp sgt i64 %a, 2
   br i1 %cmp, label %return, label %if.end
 
 if.end:                                           ; preds = %entry
   %cmp1 = icmp eq i64 %a, 2
   %mul = select i1 %cmp1, i64 %b, i64 1

llvm/test/CodeGen/AArch64/vec-extract-branch.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -verify-machineinstrs | FileCheck %s
 
 define i32 @vec_extract_branch(<2 x double> %x, i32 %y)  {
 ; CHECK-LABEL: vec_extract_branch:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.2d, v0.2d, #0.0
 ; CHECK-NEXT:    xtn v0.2s, v0.2d
 ; CHECK-NEXT:    mov w8, v0.s[1]
 ; CHECK-NEXT:    fmov w9, s0
 ; CHECK-NEXT:    and w8, w9, w8
 ; CHECK-NEXT:    tbz w8, #0, .LBB0_2
 ; CHECK-NEXT:  // %bb.1: // %true
 ; CHECK-NEXT:    mov w8, #42
 ; CHECK-NEXT:    sdiv w0, w8, w0
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB0_2: // %false
+; CHECK-NEXT:  .LBB0_2:
 ; CHECK-NEXT:    mov w0, #88
 ; CHECK-NEXT:    ret
   %t1 = fcmp ogt <2 x double> %x, zeroinitializer
   %t2 = extractelement <2 x i1> %t1, i32 0
   %t3 = extractelement <2 x i1> %t1, i32 1
   %t4 = and i1 %t2, %t3
   br i1 %t4, label %true, label %false
 true:
   %y1 = sdiv i32 42, %y
   ret i32 %y1
 false:
   ret i32 88
 }

llvm/test/Transforms/LoopUnroll/ARM/upperbound.ll

 
 ; Larger test that is still fully unrolled, thanks in part to the constant data and the max upper bound.
 @data = internal constant [50 x i32] [i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50], align 4
 define i32 @test2(i32 %l86) {
 ; CHECK-LABEL: @test2(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[L86_OFF:%.*]] = add i32 [[L86:%.*]], -1
 ; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[L86_OFF]], 24
-; CHECK-NEXT:    br i1 [[SWITCH]], label [[FOR_END_I_IF_END8_I_CRIT_EDGE_I:%.*]], label [[FOR_INC_I_3_I_5:%.*]]
-; CHECK:       for.end.i.if.end8.i_crit_edge.i:
-; CHECK-NEXT:    ret i32 0
-; CHECK:       for.inc.i.3.i.5:
 ; CHECK-NEXT:    [[DOTNOT30:%.*]] = icmp ne i32 [[L86]], 25
 ; CHECK-NEXT:    [[SPEC_SELECT24:%.*]] = zext i1 [[DOTNOT30]] to i32
-; CHECK-NEXT:    ret i32 [[SPEC_SELECT24]]
+; CHECK-NEXT:    [[COMMON_RET31_OP:%.*]] = select i1 [[SWITCH]], i32 0, i32 [[SPEC_SELECT24]]
+; CHECK-NEXT:    ret i32 [[COMMON_RET31_OP]]
 ;
 entry:
   br label %for.body.i.i
 
 for.body.i.i:                                     ; preds = %for.body.i.i.preheader, %for.inc.i.3.i
   %i.0137.i.i = phi i32 [ %add.i.3.i, %for.inc.i.3.i ], [ 0, %entry ]
   %add.i.i = or i32 %i.0137.i.i, 1
   %arrayidx.i.i = getelementptr inbounds i32, i32* getelementptr inbounds ([50 x i32], [50 x i32]* @data, i32 0, i32 0), i32 %add.i.i

llvm/test/Transforms/PGOProfile/chr.ll

 ; CHECK-LABEL: @test_chr_4(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[TMP0:%.*]] = load i32, i32* [[I:%.*]], align 4
 ; CHECK-NEXT:    [[TMP1:%.*]] = and i32 [[TMP0]], 3
 ; CHECK-NEXT:    [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 3
 ; CHECK-NEXT:    br i1 [[TMP2]], label [[ENTRY_SPLIT:%.*]], label [[ENTRY_SPLIT_NONCHR:%.*]], !prof [[PROF15]]
 ; CHECK:       entry.split:
 ; CHECK-NEXT:    [[TMP3:%.*]] = add i32 [[SUM0:%.*]], 85
-; CHECK-NEXT:    ret i32 [[TMP3]]
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       entry.split.nonchr:
 ; CHECK-NEXT:    [[TMP4:%.*]] = add i32 [[SUM0]], 42
 ; CHECK-NEXT:    [[TMP5:%.*]] = and i32 [[TMP0]], 1
 ; CHECK-NEXT:    [[DOTNOT:%.*]] = icmp eq i32 [[TMP5]], 0
 ; CHECK-NEXT:    [[SUM1_NONCHR:%.*]] = select i1 [[DOTNOT]], i32 [[SUM0]], i32 [[TMP4]], !prof [[PROF16]]
 ; CHECK-NEXT:    [[TMP6:%.*]] = and i32 [[TMP0]], 2
 ; CHECK-NEXT:    [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0
 ; CHECK-NEXT:    [[TMP8:%.*]] = add i32 [[SUM1_NONCHR]], 43
 ; CHECK-NEXT:    [[SUM2_NONCHR:%.*]] = select i1 [[TMP7]], i32 [[SUM1_NONCHR]], i32 [[TMP8]], !prof [[PROF16]]
-; CHECK-NEXT:    ret i32 [[SUM2_NONCHR]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ [[TMP3]], [[ENTRY_SPLIT]] ], [ [[SUM2_NONCHR]], [[ENTRY_SPLIT_NONCHR]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ;
 entry:
   %0 = load i32, i32* %i
   %1 = and i32 %0, 1
   %2 = icmp eq i32 %1, 0
   %3 = add i32 %sum0, 42
   %sum1 = select i1 %2, i32 %sum0, i32 %3, !prof !15
   %4 = and i32 %0, 2

 ; CHECK-NEXT:  bb0:
 ; CHECK-NEXT:    [[REASS_ADD:%.*]] = shl i64 [[V0:%.*]], 1
 ; CHECK-NEXT:    [[V2:%.*]] = add i64 [[REASS_ADD]], 3
 ; CHECK-NEXT:    [[C1:%.*]] = icmp slt i64 [[V2]], 100
 ; CHECK-NEXT:    br i1 [[C1]], label [[BB0_SPLIT:%.*]], label [[BB0_SPLIT_NONCHR:%.*]], !prof [[PROF15]]
 ; CHECK:       bb0.split:
 ; CHECK-NEXT:    [[V299:%.*]] = mul i64 [[V2]], 7860086430977039991
 ; CHECK-NEXT:    store i64 [[V299]], i64* [[J:%.*]], align 4
-; CHECK-NEXT:    ret i64 99
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       bb0.split.nonchr:
 ; CHECK-NEXT:    [[V299_NONCHR:%.*]] = mul i64 [[V2]], 7860086430977039991
 ; CHECK-NEXT:    store i64 [[V299_NONCHR]], i64* [[J]], align 4
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret i64 99
 ;
 bb0:
   %v1 = add i64 %v0, 3
   %v2 = add i64 %v1, %v0
   %c1 = icmp sgt i64 %v2, 99
   %v3 = select i1 %c1, i64 %v1, i64 %v2, !prof !15
   %v4 = add i64 %v2, %v2

llvm/test/Transforms/PhaseOrdering/X86/simplifycfg-late.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -passes='lto<O2>' -S | FileCheck %s
 
 target datalayout = "i32:32:32-i64:64:64"
 target triple = "x86_64--"
 
 ; Verify that the "late" simplifycfg options are set. This should get converted into a lookup table.
 
 define i32 @f(i32 %c) {
 ; CHECK-LABEL: @f(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[SWITCH_TABLEIDX:%.*]] = add i32 [[C:%.*]], -42
 ; CHECK-NEXT:    [[TMP0:%.*]] = icmp ult i32 [[SWITCH_TABLEIDX]], 7
-; CHECK-NEXT:    br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]]
+; CHECK-NEXT:    br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[COMMON_RET:%.*]]
 ; CHECK:       switch.lookup:
 ; CHECK-NEXT:    [[TMP1:%.*]] = sext i32 [[SWITCH_TABLEIDX]] to i64
 ; CHECK-NEXT:    [[SWITCH_GEP:%.*]] = getelementptr inbounds [7 x i32], [7 x i32]* @switch.table.f, i64 0, i64 [[TMP1]]
 ; CHECK-NEXT:    [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]], align 4
-; CHECK-NEXT:    ret i32 [[SWITCH_LOAD]]
-; CHECK:       return:
-; CHECK-NEXT:    ret i32 15
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 15, [[ENTRY:%.*]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ;
 entry:
   switch i32 %c, label %sw.default [
   i32 42, label %return
   i32 43, label %sw.bb1
   i32 44, label %sw.bb2
   i32 45, label %sw.bb3
   i32 46, label %sw.bb4

llvm/test/Transforms/PhaseOrdering/X86/vector-reductions.ll

 ; CHECK-NEXT:    [[ADD:%.*]] = fsub double [[C:%.*]], [[B]]
 ; CHECK-NEXT:    [[MUL:%.*]] = fmul double [[A:%.*]], 2.000000e+00
 ; CHECK-NEXT:    [[DIV:%.*]] = fdiv double [[ADD]], [[MUL]]
 ; CHECK-NEXT:    [[SUB:%.*]] = fsub double [[FNEG]], [[C]]
 ; CHECK-NEXT:    [[DIV3:%.*]] = fdiv double [[SUB]], [[MUL]]
 ; CHECK-NEXT:    [[CMP:%.*]] = fcmp olt double [[DIV]], 0x3EB0C6F7A0B5ED8D
 ; CHECK-NEXT:    [[CMP4:%.*]] = fcmp olt double [[DIV3]], 0x3EB0C6F7A0B5ED8D
 ; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[CMP]], i1 [[CMP4]], i1 false
-; CHECK-NEXT:    br i1 [[OR_COND]], label [[CLEANUP:%.*]], label [[LOR_LHS_FALSE:%.*]]
+; CHECK-NEXT:    br i1 [[OR_COND]], label [[COMMON_RET:%.*]], label [[LOR_LHS_FALSE:%.*]]
 ; CHECK:       lor.lhs.false:
 ; CHECK-NEXT:    [[CMP5:%.*]] = fcmp ule double [[DIV]], 1.000000e+00
 ; CHECK-NEXT:    [[CMP7:%.*]] = fcmp ule double [[DIV3]], 1.000000e+00
 ; CHECK-NEXT:    [[OR_COND1:%.*]] = select i1 [[CMP5]], i1 true, i1 [[CMP7]]
-; CHECK-NEXT:    ret i1 [[OR_COND1]]
-; CHECK:       cleanup:
-; CHECK-NEXT:    ret i1 false
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i1 [ [[OR_COND1]], [[LOR_LHS_FALSE]] ], [ false, [[ENTRY:%.*]] ]
+; CHECK-NEXT:    ret i1 [[COMMON_RET_OP]]
 ;
 entry:
   %fneg = fneg double %b
   %add = fadd double %fneg, %c
   %mul = fmul double 2.0, %a
   %div = fdiv double %add, %mul
   %fneg1 = fneg double %b
   %sub = fsub double %fneg1, %c

llvm/test/Transforms/PhaseOrdering/inlining-alignment-assumptions.ll

 
 define internal i1 @callee1(i1 %c, i64* align 8 %ptr) {
   store volatile i64 0, i64* %ptr
   ret i1 %c
 }
 
 define void @caller1(i1 %c, i64* align 1 %ptr) {
 ; ASSUMPTIONS-OFF-LABEL: @caller1(
-; ASSUMPTIONS-OFF-NEXT:    br i1 [[C:%.*]], label [[TRUE2:%.*]], label [[FALSE2:%.*]]
-; ASSUMPTIONS-OFF:       true2:
-; ASSUMPTIONS-OFF-NEXT:    store volatile i64 0, i64* [[PTR:%.*]], align 8
-; ASSUMPTIONS-OFF-NEXT:    store volatile i64 -1, i64* [[PTR]], align 4
-; ASSUMPTIONS-OFF-NEXT:    store volatile i64 -1, i64* [[PTR]], align 4
-; ASSUMPTIONS-OFF-NEXT:    store volatile i64 -1, i64* [[PTR]], align 4
-; ASSUMPTIONS-OFF-NEXT:    store volatile i64 -1, i64* [[PTR]], align 4
-; ASSUMPTIONS-OFF-NEXT:    store volatile i64 -1, i64* [[PTR]], align 4
-; ASSUMPTIONS-OFF-NEXT:    store volatile i64 2, i64* [[PTR]], align 4
-; ASSUMPTIONS-OFF-NEXT:    ret void
+; ASSUMPTIONS-OFF-NEXT:    br i1 [[C:%.*]], label [[COMMON_RET:%.*]], label [[FALSE2:%.*]]
 ; ASSUMPTIONS-OFF:       false2:
-; ASSUMPTIONS-OFF-NEXT:    store volatile i64 1, i64* [[PTR]], align 4
+; ASSUMPTIONS-OFF-NEXT:    store volatile i64 1, i64* [[PTR:%.*]], align 4
+; ASSUMPTIONS-OFF-NEXT:    br label [[COMMON_RET]]
+; ASSUMPTIONS-OFF:       common.ret:
+; ASSUMPTIONS-OFF-NEXT:    [[DOTSINK:%.*]] = phi i64 [ 3, [[FALSE2]] ], [ 2, [[TMP0:%.*]] ]
 ; ASSUMPTIONS-OFF-NEXT:    store volatile i64 0, i64* [[PTR]], align 8
 ; ASSUMPTIONS-OFF-NEXT:    store volatile i64 -1, i64* [[PTR]], align 4
 ; ASSUMPTIONS-OFF-NEXT:    store volatile i64 -1, i64* [[PTR]], align 4
 ; ASSUMPTIONS-OFF-NEXT:    store volatile i64 -1, i64* [[PTR]], align 4
 ; ASSUMPTIONS-OFF-NEXT:    store volatile i64 -1, i64* [[PTR]], align 4
 ; ASSUMPTIONS-OFF-NEXT:    store volatile i64 -1, i64* [[PTR]], align 4
-; ASSUMPTIONS-OFF-NEXT:    store volatile i64 3, i64* [[PTR]], align 4
+; ASSUMPTIONS-OFF-NEXT:    store volatile i64 [[DOTSINK]], i64* [[PTR]], align 4
 ; ASSUMPTIONS-OFF-NEXT:    ret void
 ;
 ; ASSUMPTIONS-ON-LABEL: @caller1(
-; ASSUMPTIONS-ON-NEXT:    br i1 [[C:%.*]], label [[TRUE2_CRITEDGE:%.*]], label [[FALSE1:%.*]]
+; ASSUMPTIONS-ON-NEXT:    br i1 [[C:%.*]], label [[COMMON_RET:%.*]], label [[FALSE1:%.*]]
 ; ASSUMPTIONS-ON:       false1:
 ; ASSUMPTIONS-ON-NEXT:    store volatile i64 1, i64* [[PTR:%.*]], align 8
+; ASSUMPTIONS-ON-NEXT:    br label [[COMMON_RET]]
+; ASSUMPTIONS-ON:       common.ret:
+; ASSUMPTIONS-ON-NEXT:    [[DOTSINK:%.*]] = phi i64 [ 3, [[FALSE1]] ], [ 2, [[TMP0:%.*]] ]
 ; ASSUMPTIONS-ON-NEXT:    call void @llvm.assume(i1 true) [ "align"(i64* [[PTR]], i64 8) ]
 ; ASSUMPTIONS-ON-NEXT:    store volatile i64 0, i64* [[PTR]], align 8
 ; ASSUMPTIONS-ON-NEXT:    store volatile i64 -1, i64* [[PTR]], align 8
 ; ASSUMPTIONS-ON-NEXT:    store volatile i64 -1, i64* [[PTR]], align 8
 ; ASSUMPTIONS-ON-NEXT:    store volatile i64 -1, i64* [[PTR]], align 8
 ; ASSUMPTIONS-ON-NEXT:    store volatile i64 -1, i64* [[PTR]], align 8
 ; ASSUMPTIONS-ON-NEXT:    store volatile i64 -1, i64* [[PTR]], align 8
-; ASSUMPTIONS-ON-NEXT:    store volatile i64 3, i64* [[PTR]], align 8
-; ASSUMPTIONS-ON-NEXT:    ret void
-; ASSUMPTIONS-ON:       true2.critedge:
-; ASSUMPTIONS-ON-NEXT:    call void @llvm.assume(i1 true) [ "align"(i64* [[PTR]], i64 8) ]
-; ASSUMPTIONS-ON-NEXT:    store volatile i64 0, i64* [[PTR]], align 8
-; ASSUMPTIONS-ON-NEXT:    store volatile i64 -1, i64* [[PTR]], align 8
-; ASSUMPTIONS-ON-NEXT:    store volatile i64 -1, i64* [[PTR]], align 8
-; ASSUMPTIONS-ON-NEXT:    store volatile i64 -1, i64* [[PTR]], align 8
-; ASSUMPTIONS-ON-NEXT:    store volatile i64 -1, i64* [[PTR]], align 8
-; ASSUMPTIONS-ON-NEXT:    store volatile i64 -1, i64* [[PTR]], align 8
-; ASSUMPTIONS-ON-NEXT:    store volatile i64 2, i64* [[PTR]], align 8
+; ASSUMPTIONS-ON-NEXT:    store volatile i64 [[DOTSINK]], i64* [[PTR]], align 8
 ; ASSUMPTIONS-ON-NEXT:    ret void
 ;
   br i1 %c, label %true1, label %false1
 
 true1:
   %c2 = call i1 @callee1(i1 %c, i64* %ptr)
   store volatile i64 -1, i64* %ptr
   store volatile i64 -1, i64* %ptr

llvm/test/Transforms/PruneEH/ipo-nounwind.ll

 define linkonce_odr void @callee(i32* %ptr) noinline {
 ; CHECK-LABEL: @callee(
 ; CHECK-NEXT:    ret void
 ;
   ret void
 }
 
 define i32 @caller(i32* %ptr) personality i32 3 {
-; CHECK-LABEL: @caller(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    invoke void @callee(i32* [[PTR:%.*]])
-; CHECK-NEXT:    to label [[NORMAL:%.*]] unwind label [[UNWIND:%.*]]
-; CHECK:       normal:
-; CHECK-NEXT:    ret i32 1
-; CHECK:       unwind:
-; CHECK-NEXT:    [[RES:%.*]] = landingpad { i8*, i32 }
-; CHECK-NEXT:    cleanup
-; CHECK-NEXT:    ret i32 2
-;
 
 entry:
   invoke void @callee(i32* %ptr)
   to label %normal unwind label %unwind
 
 normal:
   ret i32 1
 
 unwind:
   %res = landingpad { i8*, i32 }
   cleanup
   ret i32 2
 }

llvm/test/Transforms/SimplifyCFG/2003-08-17-FoldSwitch.ll

Start:          ; preds = %0
   ]
 TheDest:
   ret i32 1234
 }
 
 ; Test folding switch -> branch
 define i32 @test4(i32 %C) {
 ; CHECK-LABEL: @test4(
-; CHECK-NEXT:  L1:
+; CHECK-NEXT:  common.ret:
 ; CHECK-NEXT:    [[COND:%.*]] = icmp eq i32 [[C:%.*]], 0
-; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[COND]], i32 1, i32 0
-; CHECK-NEXT:    ret i32 [[SPEC_SELECT]]
+; CHECK-NEXT:    [[DOT:%.*]] = select i1 [[COND]], i32 1, i32 0
+; CHECK-NEXT:    ret i32 [[DOT]]
 ;
   switch i32 %C, label %L1 [
   i32 0, label %L2
   ]
 L1:
   ret i32 0
 L2:
   ret i32 1
 }
 
 ; Can fold into a cond branch!
 define i32 @test5(i32 %C) {
 ; CHECK-LABEL: @test5(
-; CHECK-NEXT:  L1:
+; CHECK-NEXT:  common.ret:
 ; CHECK-NEXT:    [[COND:%.*]] = icmp eq i32 [[C:%.*]], 0
-; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[COND]], i32 1, i32 0
-; CHECK-NEXT:    ret i32 [[SPEC_SELECT]]
+; CHECK-NEXT:    [[DOT:%.*]] = select i1 [[COND]], i32 1, i32 0
+; CHECK-NEXT:    ret i32 [[DOT]]
 ;
   switch i32 %C, label %L1 [
   i32 0, label %L2
   i32 123, label %L1
   ]
 L1:
   ret i32 0
 L2:
   ret i32 1
 }
 

llvm/test/Transforms/SimplifyCFG/ConditionalTrappingConstantExpr.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s
 
 @G = extern_weak global i32
 
 ; PR3354
 ; Do not merge bb1 into the entry block, it might trap.
 
 define i32 @admiral(i32 %a, i32 %b) {
 ; CHECK-LABEL: @admiral(
 ; CHECK-NEXT:    [[C:%.*]] = icmp sle i32 [[A:%.*]], [[B:%.*]]
-; CHECK-NEXT:    br i1 [[C]], label [[BB2:%.*]], label [[BB1:%.*]]
+; CHECK-NEXT:    br i1 [[C]], label [[COMMON_RET:%.*]], label [[BB1:%.*]]
 ; CHECK:       bb1:
 ; CHECK-NEXT:    [[D:%.*]] = icmp sgt i32 sdiv (i32 -32768, i32 ptrtoint (i32* @G to i32)), 0
 ; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[D]], i32 927, i32 42
-; CHECK-NEXT:    br label [[BB2]]
-; CHECK:       bb2:
-; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ 42, [[TMP0:%.*]] ], [ [[SPEC_SELECT]], [[BB1]] ]
-; CHECK-NEXT:    ret i32 [[MERGE]]
+; CHECK-NEXT:    ret i32 [[SPEC_SELECT]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    ret i32 42
 ;
   %c = icmp sle i32 %a, %b
   br i1 %c, label %bb2, label %bb1
 bb1:
   %d = icmp sgt i32 sdiv (i32 -32768, i32 ptrtoint (i32* @G to i32)), 0
   br i1 %d, label %bb6, label %bb2
 bb2:
   ret i32 42
 bb6:
   ret i32 927
 }
 
 define i32 @ackbar(i1 %c) {
 ; CHECK-LABEL: @ackbar(
-; CHECK-NEXT:    br i1 [[C:%.*]], label [[BB5:%.*]], label [[BB6:%.*]]
+; CHECK-NEXT:    br i1 [[C:%.*]], label [[BB5:%.*]], label [[COMMON_RET:%.*]]
 ; CHECK:       bb5:
 ; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 icmp sgt (i32 sdiv (i32 32767, i32 ptrtoint (i32* @G to i32)), i32 0), i32 42, i32 927
-; CHECK-NEXT:    br label [[BB6]]
-; CHECK:       bb6:
-; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ 42, [[TMP0:%.*]] ], [ [[SPEC_SELECT]], [[BB5]] ]
-; CHECK-NEXT:    ret i32 [[MERGE]]
+; CHECK-NEXT:    ret i32 [[SPEC_SELECT]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    ret i32 42
 ;
   br i1 %c, label %bb5, label %bb6
 bb5:
   br i1 icmp sgt (i32 sdiv (i32 32767, i32 ptrtoint (i32* @G to i32)), i32 0), label %bb6, label %bb7
 bb6:
   ret i32 42
 bb7:
   ret i32 927
 }
 
 ; FP ops don't trap by default, so this is safe to hoist.
 
 define i32 @tarp(i1 %c) {
 ; CHECK-LABEL: @tarp(
-; CHECK-NEXT:  bb9:
-; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 fcmp oeq (float fdiv (float 3.000000e+00, float sitofp (i32 ptrtoint (i32* @G to i32) to float)), float 1.000000e+00), i32 42, i32 927
-; CHECK-NEXT:    [[MERGE:%.*]] = select i1 [[C:%.*]], i32 [[SPEC_SELECT]], i32 42
-; CHECK-NEXT:    ret i32 [[MERGE]]
+; CHECK-NEXT:  common.ret:
+; CHECK-NEXT:    [[C_NOT:%.*]] = xor i1 [[C:%.*]], true
+; CHECK-NEXT:    [[BRMERGE:%.*]] = or i1 [[C_NOT]], fcmp oeq (float fdiv (float 3.000000e+00, float sitofp (i32 ptrtoint (i32* @G to i32) to float)), float 1.000000e+00)
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = select i1 [[BRMERGE]], i32 42, i32 927
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ;
   br i1 %c, label %bb8, label %bb9
 bb8:
   br i1 fcmp oeq (float fdiv (float 3.0, float sitofp (i32 ptrtoint (i32* @G to i32) to float)), float 1.0), label %bb9, label %bb10
 bb9:
   ret i32 42
 bb10:
   ret i32 927
 }

llvm/test/Transforms/SimplifyCFG/DeadSetCC.ll

 
 define void @testcfg(i32 %V) {
 ; CHECK-LABEL: @testcfg(
 ; CHECK-NEXT:    [[V_OFF:%.*]] = add i32 [[V:%.*]], -15
 ; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[V_OFF]], 2
 ; CHECK-NEXT:    br i1 [[SWITCH]], label [[L2:%.*]], label [[L1:%.*]]
 ; CHECK:       L1:
 ; CHECK-NEXT:    call void @foo()
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       L2:
 ; CHECK-NEXT:    call void @bar()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   %C = icmp eq i32 %V, 18
   %D = icmp eq i32 %V, 180
   %E = or i1 %C, %D
   br i1 %E, label %L1, label %Sw
 Sw:             ; preds = %0
   switch i32 %V, label %L1 [

llvm/test/Transforms/SimplifyCFG/FoldValueComparisonIntoPredecessors-domtree-preservation-edgecase-2.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s
 
 declare void @widget()
 declare i16 @baz()
 declare void @snork()
 declare void @spam()
 
 define void @zot() local_unnamed_addr align 2 personality i8* undef {
 ; CHECK-LABEL: @zot(
 ; CHECK-NEXT:  bb:
 ; CHECK-NEXT:    invoke void @widget()
 ; CHECK-NEXT:    to label [[BB14:%.*]] unwind label [[BB21:%.*]]
 ; CHECK:       bb14:
 ; CHECK-NEXT:    [[I0:%.*]] = invoke i16 @baz()
-; CHECK-NEXT:    to label [[BB15:%.*]] unwind label [[BB25:%.*]]
+; CHECK-NEXT:    to label [[BB15:%.*]] unwind label [[BB21]]
 ; CHECK:       bb15:
 ; CHECK-NEXT:    switch i16 [[I0]], label [[BB19:%.*]] [
 ; CHECK-NEXT:    i16 42, label [[BB23:%.*]]
 ; CHECK-NEXT:    i16 21330, label [[BB23]]
 ; CHECK-NEXT:    ]
 ; CHECK:       bb19:
 ; CHECK-NEXT:    invoke void @snork()
-; CHECK-NEXT:    to label [[BB20:%.*]] unwind label [[BB25]]
+; CHECK-NEXT:    to label [[BB20:%.*]] unwind label [[BB21]]
 ; CHECK:       bb20:
 ; CHECK-NEXT:    unreachable
 ; CHECK:       bb21:
 ; CHECK-NEXT:    [[I22:%.*]] = landingpad { i8*, i32 }
 ; CHECK-NEXT:    cleanup
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       bb23:
 ; CHECK-NEXT:    invoke void @spam()
-; CHECK-NEXT:    to label [[BB24:%.*]] unwind label [[BB25]]
-; CHECK:       bb24:
+; CHECK-NEXT:    to label [[COMMON_RET]] unwind label [[BB21]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
-; CHECK:       bb25:
-; CHECK-NEXT:    [[I26:%.*]] = landingpad { i8*, i32 }
-; CHECK-NEXT:    cleanup
-; CHECK-NEXT:    br label [[BB24]]
 ;
 bb:
   invoke void @widget()
   to label %bb14 unwind label %bb21
 
 bb14:                                             ; preds = %bb
   %i0 = invoke i16 @baz()
   to label %bb15 unwind label %bb25

llvm/test/Transforms/SimplifyCFG/FoldValueComparisonIntoPredecessors-domtree-preservation-edgecase.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s
 
 define dso_local i32 @readCBPandCoeffsFromNAL(i1 %c, i32 %x, i32 %y) local_unnamed_addr {
 ; CHECK-LABEL: @readCBPandCoeffsFromNAL(
 ; CHECK-NEXT:  if.end:
-; CHECK-NEXT:    br i1 [[C:%.*]], label [[IF_END80:%.*]], label [[IF_THEN64:%.*]]
-; CHECK:       if.then64:
-; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ [[Y:%.*]], [[IF_END:%.*]] ], [ 1, [[IF_END172237:%.*]] ], [ 0, [[IF_END80]] ], [ 0, [[IF_END80]] ]
-; CHECK-NEXT:    ret i32 [[MERGE]]
+; CHECK-NEXT:    br i1 [[C:%.*]], label [[IF_END80:%.*]], label [[COMMON_RET:%.*]]
 ; CHECK:       if.end80:
 ; CHECK-NEXT:    switch i32 [[X:%.*]], label [[INFLOOP:%.*]] [
-; CHECK-NEXT:    i32 10, label [[IF_END172237]]
+; CHECK-NEXT:    i32 10, label [[IF_END172237:%.*]]
 ; CHECK-NEXT:    i32 14, label [[IF_END172237]]
-; CHECK-NEXT:    i32 9, label [[IF_THEN64]]
-; CHECK-NEXT:    i32 12, label [[IF_THEN64]]
+; CHECK-NEXT:    i32 9, label [[COMMON_RET]]
+; CHECK-NEXT:    i32 12, label [[COMMON_RET]]
 ; CHECK-NEXT:    ]
 ; CHECK:       if.end172237:
-; CHECK-NEXT:    br label [[IF_THEN64]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ [[Y:%.*]], [[IF_END:%.*]] ], [ 1, [[IF_END172237]] ], [ 0, [[IF_END80]] ], [ 0, [[IF_END80]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ; CHECK:       infloop:
 ; CHECK-NEXT:    br label [[INFLOOP]]
 ;
 if.end:
   br i1 %c, label %if.end80, label %if.then64
 
 if.then64:                                        ; preds = %if.end
   ret i32 %y

llvm/test/Transforms/SimplifyCFG/FoldValueComparisonIntoPredecessors-no-new-successors.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s
 
 define void @widget(i32 %arg) {
 ; CHECK-LABEL: @widget(
 ; CHECK-NEXT:  bb:
 ; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[ARG:%.*]], 2
-; CHECK-NEXT:    br i1 [[SWITCH]], label [[BB2:%.*]], label [[INFLOOP:%.*]]
-; CHECK:       bb2:
+; CHECK-NEXT:    br i1 [[SWITCH]], label [[COMMON_RET:%.*]], label [[INFLOOP:%.*]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ; CHECK:       infloop:
 ; CHECK-NEXT:    br label [[INFLOOP]]
 ;
 bb:
   %tmp = icmp eq i32 %arg, 0
   br i1 %tmp, label %bb2, label %bb1
 

llvm/test/Transforms/SimplifyCFG/Hexagon/switch-to-lookup-table.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -O2 < %s | FileCheck %s -check-prefix=ENABLE
 ; RUN: opt -S -hexagon-emit-lookup-tables=true -O2 < %s | FileCheck %s -check-prefix=ENABLE
 ; RUN: opt -S -hexagon-emit-lookup-tables=false -O2 < %s | FileCheck %s -check-prefix=DISABLE
 
 target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
 target triple = "hexagon-unknown--elf"
 
 ; Function Attrs: noinline nounwind
 define i32 @foo(i32 %x) #0 section ".tcm_text" {
 ; ENABLE-LABEL: @foo(
 ; ENABLE-NEXT:  entry:
 ; ENABLE-NEXT:    [[TMP0:%.*]] = icmp ult i32 [[X:%.*]], 6
-; ENABLE-NEXT:    br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[RETURN:%.*]]
+; ENABLE-NEXT:    br i1 [[TMP0]], label [[SWITCH_LOOKUP:%.*]], label [[COMMON_RET:%.*]]
 ; ENABLE:       switch.lookup:
 ; ENABLE-NEXT:    [[SWITCH_GEP:%.*]] = getelementptr inbounds [6 x i32], [6 x i32]* @switch.table.foo, i32 0, i32 [[X]]
 ; ENABLE-NEXT:    [[SWITCH_LOAD:%.*]] = load i32, i32* [[SWITCH_GEP]], align 4
-; ENABLE-NEXT:    ret i32 [[SWITCH_LOAD]]
-; ENABLE:       return:
-; ENABLE-NEXT:    ret i32 19
+; ENABLE-NEXT:    br label [[COMMON_RET]]
+; ENABLE:       common.ret:
+; ENABLE-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ [[SWITCH_LOAD]], [[SWITCH_LOOKUP]] ], [ 19, [[ENTRY:%.*]] ]
+; ENABLE-NEXT:    ret i32 [[COMMON_RET_OP]]
 ;
 ; DISABLE-LABEL: @foo(
 ; DISABLE-NEXT:  entry:
 ; DISABLE-NEXT:    switch i32 [[X:%.*]], label [[SW_DEFAULT:%.*]] [
 ; DISABLE-NEXT:    i32 0, label [[RETURN:%.*]]
 ; DISABLE-NEXT:    i32 1, label [[SW_BB1:%.*]]
 ; DISABLE-NEXT:    i32 2, label [[SW_BB2:%.*]]
 ; DISABLE-NEXT:    i32 3, label [[SW_BB3:%.*]]

llvm/test/Transforms/SimplifyCFG/HoistCode.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -passes=simplifycfg -hoist-common-insts=true -S | FileCheck %s
 ; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -hoist-common-insts=true -S | FileCheck %s
 
 define void @foo(i1 %C, i32* %P) {
 ; CHECK-LABEL: @foo(
+; CHECK-NEXT:  common.ret:
 ; CHECK-NEXT:    store i32 7, i32* [[P:%.*]], align 4
 ; CHECK-NEXT:    ret void
 ;
   br i1 %C, label %T, label %F
 T:              ; preds = %0
   store i32 7, i32* %P
   ret void
 F:              ; preds = %0

llvm/test/Transforms/SimplifyCFG/SimplifyEqualityComparisonWithOnlyPredecessor-domtree-preservation-edgecase.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s
 
 declare void @zzz()
 
 define i32 @lex(i1 %c0, i1 %c1, i32 %r0, i32 %r1, i32 %v) {
 ; CHECK-LABEL: @lex(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[C0_NOT:%.*]] = xor i1 [[C0:%.*]], true
 ; CHECK-NEXT:    [[C1_NOT:%.*]] = xor i1 [[C1:%.*]], true
 ; CHECK-NEXT:    [[BRMERGE:%.*]] = select i1 [[C0_NOT]], i1 true, i1 [[C1_NOT]]
 ; CHECK-NEXT:    [[R0_MUX:%.*]] = select i1 [[C0_NOT]], i32 [[R0:%.*]], i32 [[R1:%.*]]
-; CHECK-NEXT:    br i1 [[BRMERGE]], label [[IF_THEN:%.*]], label [[DO_BODY:%.*]]
-; CHECK:       if.then:
-; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ [[R0_MUX]], [[ENTRY:%.*]] ], [ [[R1]], [[DO_BODY]] ]
-; CHECK-NEXT:    ret i32 [[MERGE]]
+; CHECK-NEXT:    br i1 [[BRMERGE]], label [[COMMON_RET:%.*]], label [[DO_BODY:%.*]]
 ; CHECK:       do.body:
 ; CHECK-NEXT:    call void @zzz()
-; CHECK-NEXT:    switch i32 [[V:%.*]], label [[IF_THEN]] [
+; CHECK-NEXT:    switch i32 [[V:%.*]], label [[COMMON_RET]] [
 ; CHECK-NEXT:    i32 10, label [[DO_BODY]]
 ; CHECK-NEXT:    i32 32, label [[DO_BODY]]
 ; CHECK-NEXT:    i32 9, label [[DO_BODY]]
 ; CHECK-NEXT:    ]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ [[R0_MUX]], [[ENTRY:%.*]] ], [ [[R1]], [[DO_BODY]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ;
 entry:
   br i1 %c0, label %if.end, label %if.then
 
 if.then:                                          ; preds = %entry
   ret i32 %r0
 
 if.end:                                           ; preds = %entry

llvm/test/Transforms/SimplifyCFG/basictest.ll

 }
 
 ; Folding branch to a common destination.
 define void @test4_fold(i32 %a, i32 %b) {
 ; CHECK-LABEL: @test4_fold(
 ; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[A:%.*]], [[B:%.*]]
 ; CHECK-NEXT:    [[CMP2:%.*]] = icmp ugt i32 [[A]], 0
 ; CHECK-NEXT:    [[OR_COND:%.*]] = and i1 [[CMP1]], [[CMP2]]
-; CHECK-NEXT:    br i1 [[OR_COND]], label [[ELSE:%.*]], label [[UNTAKEN:%.*]]
+; CHECK-NEXT:    br i1 [[OR_COND]], label [[ELSE:%.*]], label [[COMMON_RET:%.*]]
 ; CHECK:       else:
 ; CHECK-NEXT:    call void @foo()
-; CHECK-NEXT:    ret void
-; CHECK:       untaken:
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   %cmp1 = icmp eq i32 %a, %b
   br i1 %cmp1, label %taken, label %untaken
 
 taken:
   %cmp2 = icmp ugt i32 %a, 0
   br i1 %cmp2, label %else, label %untaken
untaken:
   ret void
 }
 
 declare void @foo()
 
 ; PR5795
 define void @test5(i32 %A) {
 ; CHECK-LABEL: @test5(
+; CHECK-NEXT:  common.ret:
 ; CHECK-NEXT:    ret void
 ;
   switch i32 %A, label %return [
   i32 2, label %1
   i32 10, label %2
   ]
 
   ret void

llvm/test/Transforms/SimplifyCFG/branch-fold.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s
 
 define void @test(i32* %P, i32* %Q, i1 %A, i1 %B) {
 ; CHECK-LABEL: @test(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[A_NOT:%.*]] = xor i1 [[A:%.*]], true
 ; CHECK-NEXT:    [[BRMERGE:%.*]] = select i1 [[A_NOT]], i1 true, i1 [[B:%.*]]
-; CHECK-NEXT:    br i1 [[BRMERGE]], label [[B:%.*]], label [[C:%.*]]
+; CHECK-NEXT:    br i1 [[BRMERGE]], label [[B:%.*]], label [[COMMON_RET:%.*]]
 ; CHECK:       b:
 ; CHECK-NEXT:    store i32 123, i32* [[P:%.*]], align 4
-; CHECK-NEXT:    ret void
-; CHECK:       c:
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 
 entry:
   br i1 %A, label %a, label %b
 a:
   br i1 %B, label %b, label %c
 b:

llvm/test/Transforms/SimplifyCFG/duplicate-landingpad.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 
 declare i32 @__gxx_personality_v0(...)
 declare void @fn()
 
 
 define void @test1() personality i32 (...)* @__gxx_personality_v0 {
 ; CHECK-LABEL: @test1(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    invoke void @fn()
 ; CHECK-NEXT:    to label [[INVOKE2:%.*]] unwind label [[LPAD2:%.*]]
 ; CHECK:       invoke2:
 ; CHECK-NEXT:    invoke void @fn()
-; CHECK-NEXT:    to label [[INVOKE_CONT:%.*]] unwind label [[LPAD2]]
-; CHECK:       invoke.cont:
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    to label [[COMMON_RET:%.*]] unwind label [[LPAD2]]
 ; CHECK:       lpad2:
 ; CHECK-NEXT:    [[EXN2:%.*]] = landingpad { i8*, i32 }
 ; CHECK-NEXT:    cleanup
 ; CHECK-NEXT:    call void @fn()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   invoke void @fn()
   to label %invoke2 unwind label %lpad1
 
 invoke2:
   invoke void @fn()

 ; Don't trigger if blocks aren't the same/empty
 define void @neg1() personality i32 (...)* @__gxx_personality_v0 {
 ; CHECK-LABEL: @neg1(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    invoke void @fn()
 ; CHECK-NEXT:    to label [[INVOKE2:%.*]] unwind label [[LPAD1:%.*]]
 ; CHECK:       invoke2:
 ; CHECK-NEXT:    invoke void @fn()
-; CHECK-NEXT:    to label [[INVOKE_CONT:%.*]] unwind label [[LPAD2:%.*]]
-; CHECK:       invoke.cont:
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    to label [[COMMON_RET:%.*]] unwind label [[LPAD2:%.*]]
 ; CHECK:       lpad1:
 ; CHECK-NEXT:    [[EXN:%.*]] = landingpad { i8*, i32 }
 ; CHECK-NEXT:    filter [0 x i8*] zeroinitializer
 ; CHECK-NEXT:    call void @fn()
 ; CHECK-NEXT:    br label [[SHARED_RESUME:%.*]]
 ; CHECK:       lpad2:
 ; CHECK-NEXT:    [[EXN2:%.*]] = landingpad { i8*, i32 }
 ; CHECK-NEXT:    cleanup
 ; CHECK-NEXT:    br label [[SHARED_RESUME]]
 ; CHECK:       shared_resume:
 ; CHECK-NEXT:    call void @fn()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   invoke void @fn()
   to label %invoke2 unwind label %lpad1
 
 invoke2:
   invoke void @fn()

 ; Should not trigger when the landing pads are not the exact same
 define void @neg2() personality i32 (...)* @__gxx_personality_v0 {
 ; CHECK-LABEL: @neg2(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    invoke void @fn()
 ; CHECK-NEXT:    to label [[INVOKE2:%.*]] unwind label [[LPAD1:%.*]]
 ; CHECK:       invoke2:
 ; CHECK-NEXT:    invoke void @fn()
-; CHECK-NEXT:    to label [[INVOKE_CONT:%.*]] unwind label [[LPAD2:%.*]]
-; CHECK:       invoke.cont:
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    to label [[COMMON_RET:%.*]] unwind label [[LPAD2:%.*]]
 ; CHECK:       lpad1:
 ; CHECK-NEXT:    [[EXN:%.*]] = landingpad { i8*, i32 }
 ; CHECK-NEXT:    filter [0 x i8*] zeroinitializer
 ; CHECK-NEXT:    br label [[SHARED_RESUME:%.*]]
 ; CHECK:       lpad2:
 ; CHECK-NEXT:    [[EXN2:%.*]] = landingpad { i8*, i32 }
 ; CHECK-NEXT:    cleanup
 ; CHECK-NEXT:    br label [[SHARED_RESUME]]
 ; CHECK:       shared_resume:
 ; CHECK-NEXT:    call void @fn()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   invoke void @fn()
   to label %invoke2 unwind label %lpad1
 
 invoke2:
   invoke void @fn()

llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest-two-preds-cost.ll

 ; THR1-NEXT:    [[C2:%.*]] = icmp eq i8 [[V2:%.*]], 0
 ; THR1-NEXT:    br i1 [[C2]], label [[DISPATCH]], label [[FINAL_RIGHT:%.*]]
 ; THR1:       dispatch:
 ; THR1-NEXT:    [[V3_ADJ:%.*]] = add i8 [[V1]], [[V2]]
 ; THR1-NEXT:    [[C3:%.*]] = icmp eq i8 [[V3_ADJ]], 0
 ; THR1-NEXT:    br i1 [[C3]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
 ; THR1:       final_left:
 ; THR1-NEXT:    call void @sideeffect0()
-; THR1-NEXT:    ret void
+; THR1-NEXT:    br label [[COMMON_RET:%.*]]
 ; THR1:       final_right:
 ; THR1-NEXT:    call void @sideeffect1()
+; THR1-NEXT:    br label [[COMMON_RET]]
+; THR1:       common.ret:
 ; THR1-NEXT:    ret void
 ;
 ; THR2-LABEL: @two_preds_with_extra_op(
 ; THR2-NEXT:  entry:
 ; THR2-NEXT:    [[C0:%.*]] = icmp eq i8 [[V0:%.*]], 0
 ; THR2-NEXT:    br i1 [[C0]], label [[PRED0:%.*]], label [[PRED1:%.*]]
 ; THR2:       pred0:
 ; THR2-NEXT:    [[C1:%.*]] = icmp eq i8 [[V1:%.*]], 0
 ; THR2-NEXT:    [[V3_ADJ_OLD:%.*]] = add i8 [[V1]], [[V2:%.*]]
 ; THR2-NEXT:    [[C3_OLD:%.*]] = icmp eq i8 [[V3_ADJ_OLD]], 0
 ; THR2-NEXT:    [[OR_COND1:%.*]] = select i1 [[C1]], i1 true, i1 [[C3_OLD]]
 ; THR2-NEXT:    br i1 [[OR_COND1]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]]
 ; THR2:       pred1:
 ; THR2-NEXT:    [[C2:%.*]] = icmp eq i8 [[V2]], 0
 ; THR2-NEXT:    [[V3_ADJ:%.*]] = add i8 [[V1]], [[V2]]
 ; THR2-NEXT:    [[C3:%.*]] = icmp eq i8 [[V3_ADJ]], 0
 ; THR2-NEXT:    [[OR_COND:%.*]] = select i1 [[C2]], i1 [[C3]], i1 false
 ; THR2-NEXT:    br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
 ; THR2:       final_left:
 ; THR2-NEXT:    call void @sideeffect0()
-; THR2-NEXT:    ret void
+; THR2-NEXT:    br label [[COMMON_RET:%.*]]
 ; THR2:       final_right:
 ; THR2-NEXT:    call void @sideeffect1()
+; THR2-NEXT:    br label [[COMMON_RET]]
+; THR2:       common.ret:
 ; THR2-NEXT:    ret void
 ;
 entry:
   %c0 = icmp eq i8 %v0, 0
   br i1 %c0, label %pred0, label %pred1
 pred0:
   %c1 = icmp eq i8 %v1, 0
   br i1 %c1, label %final_left, label %dispatch

 ; ALL-NEXT:    [[OR_COND:%.*]] = select i1 [[C2]], i1 [[C3]], i1 false
 ; ALL-NEXT:    br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT:%.*]]
 ; ALL:       dispatch:
 ; ALL-NEXT:    [[V3_ADJ_OLD:%.*]] = add i8 [[V1]], [[V2]]
 ; ALL-NEXT:    [[C3_OLD:%.*]] = icmp eq i8 [[V3_ADJ_OLD]], 0
 ; ALL-NEXT:    br i1 [[C3_OLD]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
 ; ALL:       final_left:
 ; ALL-NEXT:    call void @sideeffect0()
-; ALL-NEXT:    ret void
+; ALL-NEXT:    br label [[COMMON_RET:%.*]]
 ; ALL:       final_right:
 ; ALL-NEXT:    call void @sideeffect1()
+; ALL-NEXT:    br label [[COMMON_RET]]
+; ALL:       common.ret:
 ; ALL-NEXT:    ret void
 ;
 entry:
   %c0 = icmp eq i8 %v0, 0
   br i1 %c0, label %pred0, label %pred1
 pred0:
   %c1 = icmp eq i8 %v1, 0
   br i1 %c1, label %final_left, label %dispatch, !prof !0 ; likely branches to %final_left

llvm/test/Transforms/SimplifyCFG/fold-branch-to-common-dest.ll

 ; CHECK-LABEL: @one_pred(
 ; CHECK-NEXT:  pred:
 ; CHECK-NEXT:    [[C0:%.*]] = icmp eq i8 [[V0:%.*]], 0
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[V1:%.*]], 0
 ; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false
 ; CHECK-NEXT:    br i1 [[OR_COND]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]]
 ; CHECK:       final_left:
 ; CHECK-NEXT:    call void @sideeffect0()
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       final_right:
 ; CHECK-NEXT:    call void @sideeffect1()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 pred:
   %c0 = icmp eq i8 %v0, 0
   br i1 %c0, label %dispatch, label %final_right
 dispatch:
   %c1 = icmp eq i8 %v1, 0
   br i1 %c1, label %final_left, label %final_right

 ; CHECK-NEXT:    br i1 [[OR_COND1]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]]
 ; CHECK:       pred1:
 ; CHECK-NEXT:    [[C2:%.*]] = icmp eq i8 [[V2:%.*]], 0
 ; CHECK-NEXT:    [[C3:%.*]] = icmp eq i8 [[V3]], 0
 ; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[C2]], i1 [[C3]], i1 false
 ; CHECK-NEXT:    br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
 ; CHECK:       final_left:
 ; CHECK-NEXT:    call void @sideeffect0()
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       final_right:
 ; CHECK-NEXT:    call void @sideeffect1()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   %c0 = icmp eq i8 %v0, 0
   br i1 %c0, label %pred0, label %pred1
 pred0:
   %c1 = icmp eq i8 %v1, 0
   br i1 %c1, label %final_left, label %dispatch

 ; CHECK-NEXT:  pred:
 ; CHECK-NEXT:    [[C0:%.*]] = icmp eq i8 [[V0:%.*]], 0
 ; CHECK-NEXT:    [[V1_ADJ:%.*]] = add i8 [[V0]], [[V1:%.*]]
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[V1_ADJ]], 0
 ; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false
 ; CHECK-NEXT:    br i1 [[OR_COND]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]]
 ; CHECK:       final_left:
 ; CHECK-NEXT:    call void @sideeffect0()
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       final_right:
 ; CHECK-NEXT:    call void @sideeffect1()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 pred:
   %c0 = icmp eq i8 %v0, 0
   br i1 %c0, label %dispatch, label %final_right
 dispatch:
   %v1_adj = add i8 %v0, %v1
   %c1 = icmp eq i8 %v1_adj, 0

 ; CHECK:       pred1:
 ; CHECK-NEXT:    [[C2:%.*]] = icmp eq i8 [[V2]], 0
 ; CHECK-NEXT:    [[V3_ADJ:%.*]] = add i8 [[V1]], [[V2]]
 ; CHECK-NEXT:    [[C3:%.*]] = icmp eq i8 [[V3_ADJ]], 0
 ; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[C2]], i1 [[C3]], i1 false
 ; CHECK-NEXT:    br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
 ; CHECK:       final_left:
 ; CHECK-NEXT:    call void @sideeffect0()
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       final_right:
 ; CHECK-NEXT:    call void @sideeffect1()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   %c0 = icmp eq i8 %v0, 0
   br i1 %c0, label %pred0, label %pred1
 pred0:
   %c1 = icmp eq i8 %v1, 0
   br i1 %c1, label %final_left, label %dispatch

 ; CHECK-NEXT:    [[C0:%.*]] = icmp eq i8 [[V0:%.*]], 0
 ; CHECK-NEXT:    [[V1_ADJ:%.*]] = add i8 [[V0]], [[V1:%.*]]
 ; CHECK-NEXT:    [[V1_ADJ_ADJ:%.*]] = add i8 [[V1_ADJ]], [[V1_ADJ]]
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[V1_ADJ_ADJ]], 0
 ; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false
 ; CHECK-NEXT:    br i1 [[OR_COND]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]]
 ; CHECK:       final_left:
 ; CHECK-NEXT:    call void @sideeffect0()
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       final_right:
 ; CHECK-NEXT:    call void @sideeffect1()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 pred:
   %c0 = icmp eq i8 %v0, 0
   br i1 %c0, label %dispatch, label %final_right
 dispatch:
   %v1_adj = add i8 %v0, %v1
   %v1_adj_adj = add i8 %v1_adj, %v1_adj

 ; CHECK-NEXT:    [[C2:%.*]] = icmp eq i8 [[V2]], 0
 ; CHECK-NEXT:    [[V3_ADJ:%.*]] = add i8 [[V1]], [[V2]]
 ; CHECK-NEXT:    [[V3_ADJ_ADJ:%.*]] = add i8 [[V3_ADJ]], [[V3_ADJ]]
 ; CHECK-NEXT:    [[C3:%.*]] = icmp eq i8 [[V3_ADJ_ADJ]], 0
 ; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[C2]], i1 [[C3]], i1 false
 ; CHECK-NEXT:    br i1 [[OR_COND]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
 ; CHECK:       final_left:
 ; CHECK-NEXT:    call void @sideeffect0()
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       final_right:
 ; CHECK-NEXT:    call void @sideeffect1()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   %c0 = icmp eq i8 %v0, 0
   br i1 %c0, label %pred0, label %pred1
 pred0:
   %c1 = icmp eq i8 %v1, 0
   br i1 %c1, label %final_left, label %dispatch

 ; CHECK-NEXT:    [[C0:%.*]] = icmp eq i8 [[V0:%.*]], 0
 ; CHECK-NEXT:    [[V1_ADJ:%.*]] = add i8 [[V0]], [[V1:%.*]]
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[V1_ADJ]], 0
 ; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false
 ; CHECK-NEXT:    br i1 [[OR_COND]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]]
 ; CHECK:       final_left:
 ; CHECK-NEXT:    call void @sideeffect0()
 ; CHECK-NEXT:    call void @use8(i8 [[V1_ADJ]])
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       final_right:
 ; CHECK-NEXT:    call void @sideeffect1()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 pred:
   %c0 = icmp eq i8 %v0, 0
   br i1 %c0, label %dispatch, label %final_right
 dispatch:
   %v1_adj = add i8 %v0, %v1
   %c1 = icmp eq i8 %v1_adj, 0

 ; CHECK-NEXT:    [[V1_ADJ:%.*]] = add i8 [[V0]], [[V1:%.*]]
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[V1_ADJ]], 0
 ; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false
 ; CHECK-NEXT:    br i1 [[OR_COND]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]]
 ; CHECK:       final_left:
 ; CHECK-NEXT:    call void @sideeffect0()
 ; CHECK-NEXT:    call void @use8(i8 [[V1_ADJ]])
 ; CHECK-NEXT:    call void @use8(i8 [[V1_ADJ]])
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       final_right:
 ; CHECK-NEXT:    call void @sideeffect1()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 pred:
   %c0 = icmp eq i8 %v0, 0
   br i1 %c0, label %dispatch, label %final_right
 dispatch:
   %v1_adj = add i8 %v0, %v1
   %c1 = icmp eq i8 %v1_adj, 0

 ; CHECK:       final_left:
 ; CHECK-NEXT:    call void @sideeffect0()
 ; CHECK-NEXT:    call void @use8(i8 [[V2_ADJ]])
 ; CHECK-NEXT:    br label [[LEFT_END]]
 ; CHECK:       left_end:
 ; CHECK-NEXT:    [[MERGE_LEFT:%.*]] = phi i8 [ [[V2_ADJ]], [[FINAL_LEFT]] ], [ 0, [[ENTRY:%.*]] ]
 ; CHECK-NEXT:    call void @sideeffect1()
 ; CHECK-NEXT:    call void @use8(i8 [[MERGE_LEFT]])
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       final_right:
 ; CHECK-NEXT:    call void @sideeffect2()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   %c0 = icmp eq i8 %v0, 0
   br i1 %c0, label %pred, label %left_end
 pred:
   %c1 = icmp eq i8 %v1, 0
   br i1 %c1, label %dispatch, label %final_right

 ; CHECK:       dispatch:
 ; CHECK-NEXT:    [[V3_ADJ_OLD:%.*]] = add i8 [[V1]], [[V2]]
 ; CHECK-NEXT:    [[C3_OLD:%.*]] = icmp eq i8 [[V3_ADJ_OLD]], 0
 ; CHECK-NEXT:    br i1 [[C3_OLD]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
 ; CHECK:       final_left:
 ; CHECK-NEXT:    [[MERGE_LEFT:%.*]] = phi i8 [ [[V3_ADJ_OLD]], [[DISPATCH]] ], [ 0, [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ]
 ; CHECK-NEXT:    call void @use8(i8 [[MERGE_LEFT]])
 ; CHECK-NEXT:    call void @sideeffect0()
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       final_right:
 ; CHECK-NEXT:    call void @sideeffect1()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   %c0 = icmp eq i8 %v0, 0
   br i1 %c0, label %pred0, label %pred1
 pred0:
   %c1 = icmp eq i8 %v1, 0
   br i1 %c1, label %final_left, label %dispatch

 ; CHECK-NEXT:    [[C3_OLD:%.*]] = icmp eq i8 [[V3_ADJ_OLD]], 0
 ; CHECK-NEXT:    br i1 [[C3_OLD]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
 ; CHECK:       final_left:
 ; CHECK-NEXT:    [[MERGE_LEFT:%.*]] = phi i8 [ [[V3_ADJ_OLD]], [[DISPATCH]] ], [ 0, [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ]
 ; CHECK-NEXT:    [[MERGE_LEFT_2:%.*]] = phi i8 [ [[V3_ADJ_OLD]], [[DISPATCH]] ], [ 42, [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ]
 ; CHECK-NEXT:    call void @use8(i8 [[MERGE_LEFT]])
 ; CHECK-NEXT:    call void @use8(i8 [[MERGE_LEFT_2]])
 ; CHECK-NEXT:    call void @sideeffect0()
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       final_right:
 ; CHECK-NEXT:    call void @sideeffect1()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   %c0 = icmp eq i8 %v0, 0
   br i1 %c0, label %pred0, label %pred1
 pred0:
   %c1 = icmp eq i8 %v1, 0
   br i1 %c1, label %final_left, label %dispatch

 ; CHECK-NEXT:    [[C0:%.*]] = icmp eq i8 [[V0:%.*]], 0
 ; CHECK-NEXT:    [[V1_ADJ:%.*]] = add i8 [[V0]], [[V1:%.*]]
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[V1]], 0
 ; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false
 ; CHECK-NEXT:    br i1 [[OR_COND]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]]
 ; CHECK:       final_left:
 ; CHECK-NEXT:    call void @sideeffect0()
 ; CHECK-NEXT:    call void @use8(i8 [[V1_ADJ]])
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       final_right:
 ; CHECK-NEXT:    call void @sideeffect1()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 pred:
   %c0 = icmp eq i8 %v0, 0
   br i1 %c0, label %dispatch, label %final_right
 dispatch:
   %v1_adj = add i8 %v0, %v1
   %c1 = icmp eq i8 %v1, 0

 ; CHECK-NEXT:    [[V1_ADJ:%.*]] = add i8 [[V0]], [[V1:%.*]]
 ; CHECK-NEXT:    [[C1:%.*]] = icmp eq i8 [[V1]], 0
 ; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[C0]], i1 [[C1]], i1 false
 ; CHECK-NEXT:    br i1 [[OR_COND]], label [[FINAL_LEFT:%.*]], label [[FINAL_RIGHT:%.*]]
 ; CHECK:       final_left:
 ; CHECK-NEXT:    call void @sideeffect0()
 ; CHECK-NEXT:    call void @use8(i8 [[V1_ADJ]])
 ; CHECK-NEXT:    call void @use8(i8 [[V1_ADJ]])
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       final_right:
 ; CHECK-NEXT:    call void @sideeffect1()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 pred:
   %c0 = icmp eq i8 %v0, 0
   br i1 %c0, label %dispatch, label %final_right
 dispatch:
   %v1_adj = add i8 %v0, %v1
   %c1 = icmp eq i8 %v1, 0

 ; CHECK:       dispatch:
 ; CHECK-NEXT:    [[V3_ADJ_OLD:%.*]] = add i8 [[V1]], [[V2]]
 ; CHECK-NEXT:    [[C3_OLD:%.*]] = icmp eq i8 [[V3]], 0
 ; CHECK-NEXT:    br i1 [[C3_OLD]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
 ; CHECK:       final_left:
 ; CHECK-NEXT:    [[MERGE_LEFT:%.*]] = phi i8 [ [[V3_ADJ_OLD]], [[DISPATCH]] ], [ 0, [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ]
 ; CHECK-NEXT:    call void @use8(i8 [[MERGE_LEFT]])
 ; CHECK-NEXT:    call void @sideeffect0()
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       final_right:
 ; CHECK-NEXT:    call void @sideeffect1()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   %c0 = icmp eq i8 %v0, 0
   br i1 %c0, label %pred0, label %pred1
 pred0:
   %c1 = icmp eq i8 %v1, 0
   br i1 %c1, label %final_left, label %dispatch

 ; CHECK-NEXT:    [[C3_OLD:%.*]] = icmp eq i8 [[V3]], 0
 ; CHECK-NEXT:    br i1 [[C3_OLD]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
 ; CHECK:       final_left:
 ; CHECK-NEXT:    [[MERGE_LEFT:%.*]] = phi i8 [ [[V3_ADJ_OLD]], [[DISPATCH]] ], [ 0, [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ]
 ; CHECK-NEXT:    [[MERGE_LEFT_2:%.*]] = phi i8 [ [[V3_ADJ_OLD]], [[DISPATCH]] ], [ 42, [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ]
 ; CHECK-NEXT:    call void @use8(i8 [[MERGE_LEFT]])
 ; CHECK-NEXT:    call void @use8(i8 [[MERGE_LEFT_2]])
 ; CHECK-NEXT:    call void @sideeffect0()
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       final_right:
 ; CHECK-NEXT:    call void @sideeffect1()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   %c0 = icmp eq i8 %v0, 0
   br i1 %c0, label %pred0, label %pred1
 pred0:
   %c1 = icmp eq i8 %v1, 0
   br i1 %c1, label %final_left, label %dispatch

 ; CHECK:       final_left:
 ; CHECK-NEXT:    call void @sideeffect0()
 ; CHECK-NEXT:    call void @use8(i8 [[V2_ADJ]])
 ; CHECK-NEXT:    br label [[LEFT_END]]
 ; CHECK:       left_end:
 ; CHECK-NEXT:    [[MERGE_LEFT:%.*]] = phi i8 [ [[V2_ADJ]], [[FINAL_LEFT]] ], [ 0, [[ENTRY:%.*]] ]
 ; CHECK-NEXT:    call void @sideeffect1()
 ; CHECK-NEXT:    call void @use8(i8 [[MERGE_LEFT]])
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       final_right:
 ; CHECK-NEXT:    call void @sideeffect2()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   %c0 = icmp eq i8 %v0, 0
   br i1 %c0, label %pred, label %left_end
 pred:
   %c1 = icmp eq i8 %v1, 0
   br i1 %c1, label %dispatch, label %final_right

 ; CHECK:       dispatch:
 ; CHECK-NEXT:    [[C3_OLD:%.*]] = icmp eq i8 [[V3]], 0
 ; CHECK-NEXT:    [[V3_ADJ_OLD:%.*]] = add i8 [[V4]], [[V5]]
 ; CHECK-NEXT:    br i1 [[C3_OLD]], label [[FINAL_LEFT]], label [[FINAL_RIGHT]]
 ; CHECK:       final_left:
 ; CHECK-NEXT:    [[MERGE_LEFT:%.*]] = phi i8 [ [[V3_ADJ_OLD]], [[DISPATCH]] ], [ 0, [[PRED0]] ], [ [[V3_ADJ]], [[PRED1]] ]
 ; CHECK-NEXT:    call void @use8(i8 [[MERGE_LEFT]])
 ; CHECK-NEXT:    call void @sideeffect0()
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       final_right:
 ; CHECK-NEXT:    call void @sideeffect1()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   %c0 = icmp eq i8 %v0, 0
   br i1 %c0, label %pred0, label %pred1
 pred0:
   %c1 = icmp eq i8 %v1, 0
   br i1 %c1, label %final_left, label %dispatch

llvm/test/Transforms/SimplifyCFG/guards.ll

entry:
   call void(i1, ...) @llvm.experimental.guard(i1 false) [ "deopt"() ]
   ret i32 10
 }
 
 define i32 @f_1(i1 %c) {
 ; Demonstrate that we (intentionally) do not simplify a guard on undef
 ; CHECK-LABEL: @f_1(
 ; CHECK-NEXT:  entry:
-; CHECK-NEXT:    br i1 [[C:%.*]], label [[TRUE:%.*]], label [[FALSE:%.*]]
+; CHECK-NEXT:    br i1 [[C:%.*]], label [[TRUE:%.*]], label [[COMMON_RET:%.*]]
 ; CHECK:       true:
 ; CHECK-NEXT:    call void (i1, ...) @llvm.experimental.guard(i1 undef) [ "deopt"() ]
-; CHECK-NEXT:    ret i32 10
-; CHECK:       false:
-; CHECK-NEXT:    ret i32 20
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ 10, [[TRUE]] ], [ 20, [[ENTRY:%.*]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ;
 
 entry:
   br i1 %c, label %true, label %false
 
 true:
   call void(i1, ...) @llvm.experimental.guard(i1 undef) [ "deopt"() ]
   ret i32 10

 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[C0:%.*]] = load volatile i1, i1* [[C:%.*]], align 1
 ; CHECK-NEXT:    br i1 [[C0]], label [[GUARD_BLOCK:%.*]], label [[MERGE_BLOCK:%.*]]
 ; CHECK:       guard_block:
 ; CHECK-NEXT:    call void (i1, ...) @llvm.experimental.guard(i1 false) [ "deopt"() ]
 ; CHECK-NEXT:    unreachable
 ; CHECK:       merge_block:
 ; CHECK-NEXT:    [[C1:%.*]] = load volatile i1, i1* [[C]], align 1
-; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[C1]], i32 50, i32 100
-; CHECK-NEXT:    ret i32 [[SPEC_SELECT]]
+; CHECK-NEXT:    [[DOT:%.*]] = select i1 [[C1]], i32 50, i32 100
+; CHECK-NEXT:    ret i32 [[DOT]]
 ;
 entry:
   %c0 = load volatile i1, i1* %c
   br i1 %c0, label %guard_block, label %merge_block
 
 guard_block:
   call void(i1, ...) @llvm.experimental.guard(i1 false) [ "deopt"() ]
   %val = load i32, i32* %buf

llvm/test/Transforms/SimplifyCFG/hoist-dbgvalue.ll

 define i16 @hoist_with_debug3_pr49982(i32 %x, i1 %c.2) !dbg !26 {
 ; CHECK-LABEL: @hoist_with_debug3_pr49982(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br label [[FOR_COND:%.*]]
 ; CHECK:       for.cond:
 ; CHECK-NEXT:    [[C_0:%.*]] = icmp sgt i32 [[X:%.*]], 0
 ; CHECK-NEXT:    [[BRMERGE:%.*]] = select i1 [[C_0]], i1 true, i1 [[C_2:%.*]]
 ; CHECK-NEXT:    [[DOTMUX:%.*]] = select i1 [[C_0]], i16 0, i16 20
-; CHECK-NEXT:    br i1 [[BRMERGE]], label [[EXIT_1:%.*]], label [[FOR_COND]]
-; CHECK:       exit.1:
+; CHECK-NEXT:    br i1 [[BRMERGE]], label [[COMMON_RET:%.*]], label [[FOR_COND]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret i16 [[DOTMUX]]
 ;
 entry:
   br label %for.cond
 
 for.cond:
   %c.0 = icmp sgt i32 %x, 0
   br i1 %c.0, label %check, label %latch

llvm/test/Transforms/SimplifyCFG/indirectbr.ll

 ; CHECK-NEXT:    [[T:%.*]] = load i8*, i8** [[Q:%.*]], align 8
 ; CHECK-NEXT:    indirectbr i8* [[T]], [label [[BB0]], label [[BB1]], label %BB2]
 ; CHECK:       BB0:
 ; CHECK-NEXT:    call void @A()
 ; CHECK-NEXT:    br label [[BB1]]
 ; CHECK:       BB1:
 ; CHECK-NEXT:    [[X:%.*]] = phi i32 [ 0, [[BB0]] ], [ 1, [[ENTRY:%.*]] ]
 ; CHECK-NEXT:    call void @B(i32 [[X]])
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       BB2:
 ; CHECK-NEXT:    call void @C()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   store i8* blockaddress(@indbrtest0, %BB0), i8** %P
   store i8* blockaddress(@indbrtest0, %BB1), i8** %P
   store i8* blockaddress(@indbrtest0, %BB2), i8** %P
   call void @foo()
   %t = load i8*, i8** %Q

 ; condition of the select.
 
 define void @indbrtest3(i1 %cond, i8* %address) nounwind {
 ; CHECK-LABEL: @indbrtest3(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br i1 [[COND:%.*]], label [[L1:%.*]], label [[L2:%.*]]
 ; CHECK:       L1:
 ; CHECK-NEXT:    call void @A()
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       L2:
 ; CHECK-NEXT:    call void @C()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   %indirect.goto.dest = select i1 %cond, i8* blockaddress(@indbrtest3, %L1), i8* blockaddress(@indbrtest3, %L2)
   indirectbr i8* %indirect.goto.dest, [label %L1, label %L2, label %L3]
 
 L1:
   call void @A()

llvm/test/Transforms/SimplifyCFG/invoke.ll

lpad:
   tail call void @__cxa_call_unexpected(i8* %phi2) noreturn nounwind
   unreachable
 }
 
 define void @f6() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
 ; CHECK-LABEL: @f6(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[FOO:%.*]] = invoke i32 @fn()
-; CHECK-NEXT:    to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD:%.*]]
-; CHECK:       invoke.cont2:
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    to label [[COMMON_RET:%.*]] unwind label [[LPAD:%.*]]
 ; CHECK:       lpad:
 ; CHECK-NEXT:    [[TMP0:%.*]] = landingpad { i8*, i32 }
 ; CHECK-NEXT:    cleanup
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   invoke void @purefn()
   to label %invoke.cont1 unwind label %lpad
 
 invoke.cont1:
   %foo = invoke i32 @fn()

llvm/test/Transforms/SimplifyCFG/pr39807.ll

 ; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -hoist-common-insts=true < %s | FileCheck %s
 
 declare void @personality()
 
 define void @test(i1 %b) personality void()* @personality !dbg !1 {
 ; CHECK:      invoke void @inlinable()
-; CHECK-NEXT:    to label %success unwind label %failure, !dbg ![[DBGLOC:[0-9]+]]
+; CHECK-NEXT:    to label %common.ret unwind label %failure, !dbg ![[DBGLOC:[0-9]+]]
     br i1 %b, label %if, label %else
 
 if:
     invoke void @inlinable()
         to label %success unwind label %failure, !dbg !2
 
 else:
     invoke void @inlinable()

llvm/test/Transforms/SimplifyCFG/pr46638.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s
 
 define void @pr46638(i1 %c, i32 %x) {
 ; CHECK-LABEL: @pr46638(
 ; CHECK-NEXT:    [[CMP1:%.*]] = icmp slt i32 [[X:%.*]], 0
 ; CHECK-NEXT:    call void @llvm.assume(i1 [[CMP1]])
 ; CHECK-NEXT:    br i1 [[C:%.*]], label [[TRUE2_CRITEDGE:%.*]], label [[FALSE1:%.*]]
 ; CHECK:       false1:
 ; CHECK-NEXT:    call void @dummy(i32 1)
 ; CHECK-NEXT:    [[CMP2:%.*]] = icmp sgt i32 [[X]], 0
 ; CHECK-NEXT:    [[EXT:%.*]] = zext i1 [[CMP2]] to i32
 ; CHECK-NEXT:    call void @dummy(i32 [[EXT]])
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       true2.critedge:
 ; CHECK-NEXT:    [[CMP2_C:%.*]] = icmp sgt i32 [[X]], 0
 ; CHECK-NEXT:    [[EXT_C:%.*]] = zext i1 [[CMP2_C]] to i32
 ; CHECK-NEXT:    call void @dummy(i32 [[EXT_C]])
 ; CHECK-NEXT:    call void @dummy(i32 2)
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   %cmp1 = icmp slt i32 %x, 0
   call void @llvm.assume(i1 %cmp1)
   br i1 %c, label %true1, label %false1
 
 true1:
   %cmp2 = icmp sgt i32 %x, 0

llvm/test/Transforms/SimplifyCFG/pr48778-sdiv-speculation.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -simplifycfg -S < %s | FileCheck %s
 
 ; sdiv INT_MIN / -1 should not be speculated.
 define i32 @test(i1 %cmp) {
 ; CHECK-LABEL: @test(
-; CHECK-NEXT:    br i1 [[CMP:%.*]], label [[IF:%.*]], label [[ELSE:%.*]]
+; CHECK-NEXT:    br i1 [[CMP:%.*]], label [[IF:%.*]], label [[COMMON_RET:%.*]]
 ; CHECK:       if:
 ; CHECK-NEXT:    [[DIV:%.*]] = sdiv i32 -2147483648, -1
 ; CHECK-NEXT:    [[CMP2:%.*]] = icmp ne i32 [[DIV]], 0
 ; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[CMP2]], i32 1, i32 0
-; CHECK-NEXT:    br label [[ELSE]]
-; CHECK:       else:
-; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ 0, [[TMP0:%.*]] ], [ [[SPEC_SELECT]], [[IF]] ]
-; CHECK-NEXT:    ret i32 [[MERGE]]
+; CHECK-NEXT:    ret i32 [[SPEC_SELECT]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    ret i32 0
 ;
   br i1 %cmp, label %if, label %else
 
 if:
   %div = sdiv i32 -2147483648, -1
   %cmp2 = icmp ne i32 %div, 0
   br i1 %cmp2, label %end, label %else
 
 else:
   ret i32 0
 
 end:
   ret i32 1
 }

llvm/test/Transforms/SimplifyCFG/preserve-branchweights.ll

 ; CHECK-LABEL: @test1(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[A_NOT:%.*]] = xor i1 [[A:%.*]], true
 ; CHECK-NEXT:    [[C:%.*]] = or i1 [[B:%.*]], false
 ; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[A_NOT]], i1 [[C]], i1 false
 ; CHECK-NEXT:    br i1 [[OR_COND]], label [[Z:%.*]], label [[Y:%.*]], !prof [[PROF0:![0-9]+]]
 ; CHECK:       Y:
 ; CHECK-NEXT:    call void @helper(i32 0)
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       Z:
 ; CHECK-NEXT:    call void @helper(i32 1)
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   br i1 %a, label %Y, label %X, !prof !0
 
 X:
   %c = or i1 %b, false
   br i1 %c, label %Z, label %Y, !prof !1

 ; CHECK-LABEL: @fake_weights(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[A_NOT:%.*]] = xor i1 [[A:%.*]], true
 ; CHECK-NEXT:    [[C:%.*]] = or i1 [[B:%.*]], false
 ; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[A_NOT]], i1 [[C]], i1 false
 ; CHECK-NEXT:    br i1 [[OR_COND]], label [[Z:%.*]], label [[Y:%.*]], !prof [[PROF1:![0-9]+]]
 ; CHECK:       Y:
 ; CHECK-NEXT:    call void @helper(i32 0)
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       Z:
 ; CHECK-NEXT:    call void @helper(i32 1)
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   br i1 %a, label %Y, label %X, !prof !12
 X:
   %c = or i1 %b, false
   br i1 %c, label %Z, label %Y, !prof !1
 

 define void @test2(i1 %a, i1 %b) {
 ; CHECK-LABEL: @test2(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[C:%.*]] = or i1 [[B:%.*]], false
 ; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[A:%.*]], i1 [[C]], i1 false
 ; CHECK-NEXT:    br i1 [[OR_COND]], label [[Z:%.*]], label [[Y:%.*]], !prof [[PROF2:![0-9]+]]
 ; CHECK:       Y:
 ; CHECK-NEXT:    call void @helper(i32 0)
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       Z:
 ; CHECK-NEXT:    call void @helper(i32 1)
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   br i1 %a, label %X, label %Y, !prof !1
 
 X:
   %c = or i1 %b, false
   br i1 %c, label %Z, label %Y, !prof !2

 define void @test3(i1 %a, i1 %b) {
 ; CHECK-LABEL: @test3(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[C:%.*]] = or i1 [[B:%.*]], false
 ; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[A:%.*]], i1 [[C]], i1 false
 ; CHECK-NEXT:    br i1 [[OR_COND]], label [[Z:%.*]], label [[Y:%.*]], !prof [[PROF1]]
 ; CHECK:       Y:
 ; CHECK-NEXT:    call void @helper(i32 0)
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       Z:
 ; CHECK-NEXT:    call void @helper(i32 1)
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   br i1 %a, label %X, label %Y, !prof !1
 
 X:
   %c = or i1 %b, false
   br i1 %c, label %Z, label %Y

 define void @test4(i1 %a, i1 %b) {
 ; CHECK-LABEL: @test4(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[C:%.*]] = or i1 [[B:%.*]], false
 ; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[A:%.*]], i1 [[C]], i1 false
 ; CHECK-NEXT:    br i1 [[OR_COND]], label [[Z:%.*]], label [[Y:%.*]], !prof [[PROF1]]
 ; CHECK:       Y:
 ; CHECK-NEXT:    call void @helper(i32 0)
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       Z:
 ; CHECK-NEXT:    call void @helper(i32 1)
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   br i1 %a, label %X, label %Y
 
 X:
   %c = or i1 %b, false
   br i1 %c, label %Z, label %Y, !prof !1

 define void @test1_swap(i1 %a, i1 %b) {
 ; CHECK-LABEL: @test1_swap(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[C:%.*]] = or i1 [[B:%.*]], false
 ; CHECK-NEXT:    [[OR_COND:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[C]]
 ; CHECK-NEXT:    br i1 [[OR_COND]], label [[Y:%.*]], label [[Z:%.*]], !prof [[PROF5:![0-9]+]]
 ; CHECK:       Y:
 ; CHECK-NEXT:    call void @helper(i32 0)
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       Z:
 ; CHECK-NEXT:    call void @helper(i32 1)
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   br i1 %a, label %Y, label %X, !prof !0
 
 X:
   %c = or i1 %b, false
   br i1 %c, label %Y, label %Z, !prof !1

 define void @test7(i1 %a, i1 %b) {
 ; CHECK-LABEL: @test7(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[C:%.*]] = or i1 [[B:%.*]], false
 ; CHECK-NEXT:    [[BRMERGE:%.*]] = select i1 [[A:%.*]], i1 true, i1 [[C]]
 ; CHECK-NEXT:    br i1 [[BRMERGE]], label [[Y:%.*]], label [[Z:%.*]], !prof [[PROF6:![0-9]+]]
 ; CHECK:       Y:
 ; CHECK-NEXT:    call void @helper(i32 0)
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       Z:
 ; CHECK-NEXT:    call void @helper(i32 1)
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   %c = or i1 %b, false
   br i1 %a, label %Y, label %X, !prof !0
 
 X:
   br i1 %c, label %Y, label %Z, !prof !6

 ; Test basic folding to a conditional branch.
 define void @test8(i64 %x, i64 %y) nounwind {
 ; CHECK-LABEL: @test8(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[LT:%.*]] = icmp slt i64 [[X:%.*]], [[Y:%.*]]
 ; CHECK-NEXT:    br i1 [[LT]], label [[A:%.*]], label [[B:%.*]], !prof [[PROF7:![0-9]+]]
 ; CHECK:       a:
 ; CHECK-NEXT:    call void @helper(i32 0) #[[ATTR1:[0-9]+]]
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       b:
 ; CHECK-NEXT:    call void @helper(i32 1) #[[ATTR1]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   %lt = icmp slt i64 %x, %y
   %qux = select i1 %lt, i32 0, i32 2
   switch i32 %qux, label %bees [
   i32 0, label %a
   i32 1, label %b

 ; CHECK-NEXT:    i32 0, label [[A:%.*]]
 ; CHECK-NEXT:    i32 1, label [[END:%.*]]
 ; CHECK-NEXT:    i32 2, label [[END]]
 ; CHECK-NEXT:    i32 92, label [[END]]
 ; CHECK-NEXT:    ], !prof [[PROF8:![0-9]+]]
 ; CHECK:       a:
 ; CHECK-NEXT:    call void @helper(i32 0) #[[ATTR1]]
 ; CHECK-NEXT:    [[RETA:%.*]] = icmp slt i32 [[X]], [[Y:%.*]]
-; CHECK-NEXT:    ret i1 [[RETA]]
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       bees:
 ; CHECK-NEXT:    br label [[END]]
 ; CHECK:       end:
 ; CHECK-NEXT:    [[RET:%.*]] = phi i1 [ true, [[ENTRY:%.*]] ], [ false, [[BEES]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ]
 ; CHECK-NEXT:    call void @helper(i32 2) #[[ATTR1]]
-; CHECK-NEXT:    ret i1 [[RET]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i1 [ [[RETA]], [[A]] ], [ [[RET]], [[END]] ]
+; CHECK-NEXT:    ret i1 [[COMMON_RET_OP]]
 ;
 entry:
   switch i32 %x, label %bees [
   i32 0, label %a
   i32 1, label %end
   i32 2, label %end
   ], !prof !7
 

 define void @test10(i32 %x) nounwind readnone ssp noredzone {
 ; CHECK-LABEL: @test10(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[X_OFF:%.*]] = add i32 [[X:%.*]], -1
 ; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[X_OFF]], 3
 ; CHECK-NEXT:    br i1 [[SWITCH]], label [[LOR_END:%.*]], label [[LOR_RHS:%.*]], !prof [[PROF9:![0-9]+]]
 ; CHECK:       lor.rhs:
 ; CHECK-NEXT:    call void @helper(i32 1) #[[ATTR1]]
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       lor.end:
 ; CHECK-NEXT:    call void @helper(i32 0) #[[ATTR1]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   switch i32 %x, label %lor.rhs [
   i32 2, label %lor.end
   i32 1, label %lor.end
   i32 3, label %lor.end
   ], !prof !7

 ; Remove dead cases from the switch.
 define void @test11(i32 %x) nounwind {
 ; CHECK-LABEL: @test11(
 ; CHECK-NEXT:    [[I:%.*]] = shl i32 [[X:%.*]], 1
 ; CHECK-NEXT:    [[COND:%.*]] = icmp eq i32 [[I]], 24
 ; CHECK-NEXT:    br i1 [[COND]], label [[C:%.*]], label [[A:%.*]], !prof [[PROF10:![0-9]+]]
 ; CHECK:       a:
 ; CHECK-NEXT:    call void @helper(i32 0) #[[ATTR1]]
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       c:
 ; CHECK-NEXT:    call void @helper(i32 2) #[[ATTR1]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   %i = shl i32 %x, 1
   switch i32 %i, label %a [
   i32 21, label %b
   i32 24, label %c
   ], !prof !8
 

llvm/test/Transforms/SimplifyCFG/rangereduce.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -switch-to-lookup -S | FileCheck %s
 ; RUN: opt < %s -passes='simplify-cfg<switch-to-lookup>' -S | FileCheck %s
 
 target datalayout = "e-n32"
 
 define i32 @test1(i32 %a) {
 ; CHECK-LABEL: @test1(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub i32 [[A:%.*]], 97
 ; CHECK-NEXT:    [[TMP2:%.*]] = lshr i32 [[TMP1]], 2
 ; CHECK-NEXT:    [[TMP3:%.*]] = shl i32 [[TMP1]], 30
 ; CHECK-NEXT:    [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
-; CHECK-NEXT:    switch i32 [[TMP4]], label [[DEF:%.*]] [
+; CHECK-NEXT:    switch i32 [[TMP4]], label [[COMMON_RET:%.*]] [
 ; CHECK-NEXT:    i32 0, label [[ONE:%.*]]
 ; CHECK-NEXT:    i32 1, label [[TWO:%.*]]
 ; CHECK-NEXT:    i32 2, label [[THREE:%.*]]
 ; CHECK-NEXT:    i32 3, label [[THREE]]
 ; CHECK-NEXT:    ]
-; CHECK:       def:
-; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ 8867, [[TMP0:%.*]] ], [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ]
-; CHECK-NEXT:    ret i32 [[MERGE]]
 ; CHECK:       one:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       two:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       three:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ], [ 8867, [[TMP0:%.*]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ;
   switch i32 %a, label %def [
   i32 97, label %one
   i32 101, label %two
   i32 105, label %three
   i32 109, label %three
   ]
 
 def:
   ret i32 8867
 
 one:
   ret i32 11984
 two:
   ret i32 1143
 three:
   ret i32 99783
 }
 
 ; Optimization shouldn't trigger; bitwidth > 64
 define i128 @test2(i128 %a) {
 ; CHECK-LABEL: @test2(
-; CHECK-NEXT:    switch i128 [[A:%.*]], label [[DEF:%.*]] [
+; CHECK-NEXT:    switch i128 [[A:%.*]], label [[COMMON_RET:%.*]] [
 ; CHECK-NEXT:    i128 97, label [[ONE:%.*]]
 ; CHECK-NEXT:    i128 101, label [[TWO:%.*]]
 ; CHECK-NEXT:    i128 105, label [[THREE:%.*]]
 ; CHECK-NEXT:    i128 109, label [[THREE]]
 ; CHECK-NEXT:    ]
-; CHECK:       def:
-; CHECK-NEXT:    [[MERGE:%.*]] = phi i128 [ 8867, [[TMP0:%.*]] ], [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ]
-; CHECK-NEXT:    ret i128 [[MERGE]]
 ; CHECK:       one:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       two:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       three:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i128 [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ], [ 8867, [[TMP0:%.*]] ]
+; CHECK-NEXT:    ret i128 [[COMMON_RET_OP]]
 ;
   switch i128 %a, label %def [
   i128 97, label %one
   i128 101, label %two
   i128 105, label %three
   i128 109, label %three
   ]
 
 def:
   ret i128 8867
 
 one:
   ret i128 11984
 two:
   ret i128 1143
 three:
   ret i128 99783
 }
 
 ; Optimization shouldn't trigger; no holes present
 define i32 @test3(i32 %a) {
 ; CHECK-LABEL: @test3(
-; CHECK-NEXT:    switch i32 [[A:%.*]], label [[DEF:%.*]] [
+; CHECK-NEXT:    switch i32 [[A:%.*]], label [[COMMON_RET:%.*]] [
 ; CHECK-NEXT:    i32 97, label [[ONE:%.*]]
 ; CHECK-NEXT:    i32 98, label [[TWO:%.*]]
 ; CHECK-NEXT:    i32 99, label [[THREE:%.*]]
 ; CHECK-NEXT:    ]
-; CHECK:       def:
-; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ 8867, [[TMP0:%.*]] ], [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ]
-; CHECK-NEXT:    ret i32 [[MERGE]]
 ; CHECK:       one:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       two:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       three:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ], [ 8867, [[TMP0:%.*]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ;
   switch i32 %a, label %def [
   i32 97, label %one
   i32 98, label %two
   i32 99, label %three
   ]
 
 def:
   ret i32 8867
 
 one:
   ret i32 11984
 two:
   ret i32 1143
 three:
   ret i32 99783
 }
 
 ; Optimization shouldn't trigger; not an arithmetic progression
 define i32 @test4(i32 %a) {
 ; CHECK-LABEL: @test4(
-; CHECK-NEXT:    switch i32 [[A:%.*]], label [[DEF:%.*]] [
+; CHECK-NEXT:    switch i32 [[A:%.*]], label [[COMMON_RET:%.*]] [
 ; CHECK-NEXT:    i32 97, label [[ONE:%.*]]
 ; CHECK-NEXT:    i32 102, label [[TWO:%.*]]
 ; CHECK-NEXT:    i32 105, label [[THREE:%.*]]
 ; CHECK-NEXT:    i32 109, label [[THREE]]
 ; CHECK-NEXT:    ]
-; CHECK:       def:
-; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ 8867, [[TMP0:%.*]] ], [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ]
-; CHECK-NEXT:    ret i32 [[MERGE]]
 ; CHECK:       one:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       two:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       three:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ], [ 8867, [[TMP0:%.*]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ;
   switch i32 %a, label %def [
   i32 97, label %one
   i32 102, label %two
   i32 105, label %three
   i32 109, label %three
   ]
 
 def:
   ret i32 8867
 
 one:
   ret i32 11984
 two:
   ret i32 1143
 three:
   ret i32 99783
 }
 
 ; Optimization shouldn't trigger; not a power of two
 define i32 @test5(i32 %a) {
 ; CHECK-LABEL: @test5(
-; CHECK-NEXT:    switch i32 [[A:%.*]], label [[DEF:%.*]] [
+; CHECK-NEXT:    switch i32 [[A:%.*]], label [[COMMON_RET:%.*]] [
 ; CHECK-NEXT:    i32 97, label [[ONE:%.*]]
 ; CHECK-NEXT:    i32 102, label [[TWO:%.*]]
 ; CHECK-NEXT:    i32 107, label [[THREE:%.*]]
 ; CHECK-NEXT:    i32 112, label [[THREE]]
 ; CHECK-NEXT:    ]
-; CHECK:       def:
-; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ 8867, [[TMP0:%.*]] ], [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ]
-; CHECK-NEXT:    ret i32 [[MERGE]]
 ; CHECK:       one:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       two:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       three:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ], [ 8867, [[TMP0:%.*]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ;
   switch i32 %a, label %def [
   i32 97, label %one
   i32 102, label %two
   i32 107, label %three
   i32 112, label %three
   ]
 

 }
 
 define i32 @test6(i32 %a) optsize {
 ; CHECK-LABEL: @test6(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub i32 [[A:%.*]], -109
 ; CHECK-NEXT:    [[TMP2:%.*]] = lshr i32 [[TMP1]], 2
 ; CHECK-NEXT:    [[TMP3:%.*]] = shl i32 [[TMP1]], 30
 ; CHECK-NEXT:    [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
-; CHECK-NEXT:    switch i32 [[TMP4]], label [[DEF:%.*]] [
+; CHECK-NEXT:    switch i32 [[TMP4]], label [[COMMON_RET:%.*]] [
 ; CHECK-NEXT:    i32 3, label [[ONE:%.*]]
 ; CHECK-NEXT:    i32 2, label [[TWO:%.*]]
 ; CHECK-NEXT:    i32 1, label [[THREE:%.*]]
 ; CHECK-NEXT:    i32 0, label [[THREE]]
 ; CHECK-NEXT:    ]
-; CHECK:       def:
-; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ 8867, [[TMP0:%.*]] ], [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ]
-; CHECK-NEXT:    ret i32 [[MERGE]]
 ; CHECK:       one:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       two:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       three:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ], [ 8867, [[TMP0:%.*]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ;
   switch i32 %a, label %def [
   i32 -97, label %one
   i32 -101, label %two
   i32 -105, label %three
   i32 -109, label %three
   ]
 

 
 define i8 @test7(i8 %a) optsize {
 ; CHECK-LABEL: @test7(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub i8 [[A:%.*]], -36
 ; CHECK-NEXT:    [[TMP2:%.*]] = lshr i8 [[TMP1]], 2
 ; CHECK-NEXT:    [[TMP3:%.*]] = shl i8 [[TMP1]], 6
 ; CHECK-NEXT:    [[TMP4:%.*]] = or i8 [[TMP2]], [[TMP3]]
 ; CHECK-NEXT:    [[TMP5:%.*]] = icmp ult i8 [[TMP4]], 4
-; CHECK-NEXT:    br i1 [[TMP5]], label [[SWITCH_LOOKUP:%.*]], label [[DEF:%.*]]
+; CHECK-NEXT:    br i1 [[TMP5]], label [[SWITCH_LOOKUP:%.*]], label [[COMMON_RET:%.*]]
 ; CHECK:       switch.lookup:
 ; CHECK-NEXT:    [[SWITCH_CAST:%.*]] = zext i8 [[TMP4]] to i32
 ; CHECK-NEXT:    [[SWITCH_SHIFTAMT:%.*]] = mul i32 [[SWITCH_CAST]], 8
 ; CHECK-NEXT:    [[SWITCH_DOWNSHIFT:%.*]] = lshr i32 -943228976, [[SWITCH_SHIFTAMT]]
 ; CHECK-NEXT:    [[SWITCH_MASKED:%.*]] = trunc i32 [[SWITCH_DOWNSHIFT]] to i8
 ; CHECK-NEXT:    ret i8 [[SWITCH_MASKED]]
-; CHECK:       def:
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret i8 -93
 ;
   switch i8 %a, label %def [
   i8 220, label %one
   i8 224, label %two
   i8 228, label %three
   i8 232, label %three
   ]

 }
 
 define i32 @test8(i32 %a) optsize {
 ; CHECK-LABEL: @test8(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub i32 [[A:%.*]], 97
 ; CHECK-NEXT:    [[TMP2:%.*]] = lshr i32 [[TMP1]], 2
 ; CHECK-NEXT:    [[TMP3:%.*]] = shl i32 [[TMP1]], 30
 ; CHECK-NEXT:    [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
-; CHECK-NEXT:    switch i32 [[TMP4]], label [[DEF:%.*]] [
+; CHECK-NEXT:    switch i32 [[TMP4]], label [[COMMON_RET:%.*]] [
 ; CHECK-NEXT:    i32 0, label [[ONE:%.*]]
 ; CHECK-NEXT:    i32 1, label [[TWO:%.*]]
 ; CHECK-NEXT:    i32 2, label [[THREE:%.*]]
 ; CHECK-NEXT:    i32 4, label [[THREE]]
 ; CHECK-NEXT:    ]
-; CHECK:       def:
-; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ 8867, [[TMP0:%.*]] ], [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ]
-; CHECK-NEXT:    ret i32 [[MERGE]]
 ; CHECK:       one:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       two:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       three:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ], [ 8867, [[TMP0:%.*]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ;
   switch i32 %a, label %def [
   i32 97, label %one
   i32 101, label %two
   i32 105, label %three
   i32 113, label %three
   ]
 

 }
 
 define i32 @test9(i32 %a) {
 ; CHECK-LABEL: @test9(
 ; CHECK-NEXT:    [[TMP1:%.*]] = sub i32 [[A:%.*]], 6
 ; CHECK-NEXT:    [[TMP2:%.*]] = lshr i32 [[TMP1]], 1
 ; CHECK-NEXT:    [[TMP3:%.*]] = shl i32 [[TMP1]], 31
 ; CHECK-NEXT:    [[TMP4:%.*]] = or i32 [[TMP2]], [[TMP3]]
-; CHECK-NEXT:    switch i32 [[TMP4]], label [[DEF:%.*]] [
+; CHECK-NEXT:    switch i32 [[TMP4]], label [[COMMON_RET:%.*]] [
 ; CHECK-NEXT:    i32 6, label [[ONE:%.*]]
 ; CHECK-NEXT:    i32 7, label [[TWO:%.*]]
 ; CHECK-NEXT:    i32 0, label [[THREE:%.*]]
 ; CHECK-NEXT:    i32 2, label [[THREE]]
 ; CHECK-NEXT:    ]
-; CHECK:       def:
-; CHECK-NEXT:    [[MERGE:%.*]] = phi i32 [ 8867, [[TMP0:%.*]] ], [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ]
-; CHECK-NEXT:    ret i32 [[MERGE]]
 ; CHECK:       one:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       two:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       three:
-; CHECK-NEXT:    br label [[DEF]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ 11984, [[ONE]] ], [ 1143, [[TWO]] ], [ 99783, [[THREE]] ], [ 8867, [[TMP0:%.*]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ;
   switch i32 %a, label %def [
   i32 18, label %one
   i32 20, label %two
   i32 6, label %three
   i32 10, label %three
   ]
 

llvm/test/Transforms/SimplifyCFG/suppress-zero-branch-weights.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s
 
 ; We're sign extending an 8-bit value.
 ; The switch condition must be in the range [-128, 127], so any cases outside of that range must be dead.
 ; Only the first case has a non-zero weight, but that gets eliminated. Note
 ; that this shouldn't have been the case in the first place, but the test here
 ; ensures that all-zero branch weights are not attached causing problems downstream.
 
 define i1 @repeated_signbits(i8 %condition) {
 ; CHECK-LABEL: @repeated_signbits(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[SEXT:%.*]] = sext i8 [[CONDITION:%.*]] to i32
 ; CHECK-NEXT:    switch i32 [[SEXT]], label [[DEFAULT:%.*]] [
-; CHECK-NEXT:    i32 0, label [[A:%.*]]
-; CHECK-NEXT:    i32 127, label [[A]]
-; CHECK-NEXT:    i32 -128, label [[A]]
-; CHECK-NEXT:    i32 -1, label [[A]]
+; CHECK-NEXT:    i32 0, label [[COMMON_RET:%.*]]
+; CHECK-NEXT:    i32 127, label [[COMMON_RET]]
+; CHECK-NEXT:    i32 -128, label [[COMMON_RET]]
+; CHECK-NEXT:    i32 -1, label [[COMMON_RET]]
 ; CHECK-NEXT:    ]
-; CHECK:       a:
-; CHECK-NEXT:    [[MERGE:%.*]] = phi i1 [ true, [[ENTRY:%.*]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ], [ false, [[DEFAULT]] ]
-; CHECK-NEXT:    ret i1 [[MERGE]]
 ; CHECK:       default:
-; CHECK-NEXT:    br label [[A]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i1 [ false, [[DEFAULT]] ], [ true, [[ENTRY:%.*]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ]
+; CHECK-NEXT:    ret i1 [[COMMON_RET_OP]]
 ;
 entry:
   %sext = sext i8 %condition to i32
   switch i32 %sext, label %default [
   i32 -2147483648, label %a
   i32 -129, label %a
   i32 -128, label %a
   i32 -1, label %a

llvm/test/Transforms/SimplifyCFG/switch-dead-default.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt %s -S -passes='simplify-cfg<switch-to-lookup>' -simplifycfg-require-and-preserve-domtree=1 | FileCheck %s
 
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 declare void @foo(i32)
 
 define void @test(i1 %a) {
 ; CHECK-LABEL: @test(
 ; CHECK-NEXT:    [[A_OFF:%.*]] = add i1 [[A:%.*]], true
 ; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i1 [[A_OFF]], true
 ; CHECK-NEXT:    br i1 [[SWITCH]], label [[TRUE:%.*]], label [[FALSE:%.*]]
 ; CHECK:       true:
 ; CHECK-NEXT:    call void @foo(i32 1)
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       false:
 ; CHECK-NEXT:    call void @foo(i32 3)
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   switch i1 %a, label %default [i1 1, label %true
   i1 0, label %false]
 true:
   call void @foo(i32 1)
   ret void
 false:

 ; CHECK-NEXT:    switch i2 [[A:%.*]], label [[DEFAULT1:%.*]] [
 ; CHECK-NEXT:    i2 0, label [[CASE0:%.*]]
 ; CHECK-NEXT:    i2 1, label [[CASE1:%.*]]
 ; CHECK-NEXT:    i2 -2, label [[CASE2:%.*]]
 ; CHECK-NEXT:    i2 -1, label [[CASE3:%.*]]
 ; CHECK-NEXT:    ]
 ; CHECK:       case0:
 ; CHECK-NEXT:    call void @foo(i32 0)
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       case1:
 ; CHECK-NEXT:    call void @foo(i32 1)
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       case2:
 ; CHECK-NEXT:    call void @foo(i32 2)
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       case3:
 ; CHECK-NEXT:    call void @foo(i32 3)
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       default1:
 ; CHECK-NEXT:    unreachable
+; CHECK:       common.ret:
+; CHECK-NEXT:    ret void
 ;
   switch i2 %a, label %default [i2 0, label %case0
   i2 1, label %case1
   i2 2, label %case2
   i2 3, label %case3]
 case0:
   call void @foo(i32 0)
   ret void

 ; CHECK-LABEL: @test3(
 ; CHECK-NEXT:    switch i2 [[A:%.*]], label [[DEFAULT:%.*]] [
 ; CHECK-NEXT:    i2 0, label [[CASE0:%.*]]
 ; CHECK-NEXT:    i2 1, label [[CASE1:%.*]]
 ; CHECK-NEXT:    i2 -2, label [[CASE2:%.*]]
 ; CHECK-NEXT:    ]
 ; CHECK:       case0:
 ; CHECK-NEXT:    call void @foo(i32 0)
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       case1:
 ; CHECK-NEXT:    call void @foo(i32 1)
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       case2:
 ; CHECK-NEXT:    call void @foo(i32 2)
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       default:
 ; CHECK-NEXT:    call void @foo(i32 3)
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   switch i2 %a, label %default [i2 0, label %case0
   i2 1, label %case1
   i2 2, label %case2]
 
 case0:
   call void @foo(i32 0)

 define void @test4(i128 %a) {
 ; CHECK-LABEL: @test4(
 ; CHECK-NEXT:    switch i128 [[A:%.*]], label [[DEFAULT:%.*]] [
 ; CHECK-NEXT:    i128 0, label [[CASE0:%.*]]
 ; CHECK-NEXT:    i128 1, label [[CASE1:%.*]]
 ; CHECK-NEXT:    ]
 ; CHECK:       case0:
 ; CHECK-NEXT:    call void @foo(i32 0)
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       case1:
 ; CHECK-NEXT:    call void @foo(i32 1)
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       default:
 ; CHECK-NEXT:    call void @foo(i32 2)
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   switch i128 %a, label %default [i128 0, label %case0
   i128 1, label %case1]
 
 case0:
   call void @foo(i32 0)
   ret void

 ; CHECK-LABEL: @test5(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i8 [[A:%.*]], 2
 ; CHECK-NEXT:    call void @llvm.assume(i1 [[CMP]])
 ; CHECK-NEXT:    [[A_OFF:%.*]] = add i8 [[A]], -1
 ; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i8 [[A_OFF]], 1
 ; CHECK-NEXT:    br i1 [[SWITCH]], label [[TRUE:%.*]], label [[FALSE:%.*]]
 ; CHECK:       true:
 ; CHECK-NEXT:    call void @foo(i32 1)
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       false:
 ; CHECK-NEXT:    call void @foo(i32 3)
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   %cmp = icmp ult i8 %a, 2
   call void @llvm.assume(i1 %cmp)
   switch i8 %a, label %default [i8 1, label %true
   i8 0, label %false]
 true:
   call void @foo(i32 1)

 ; CHECK-NEXT:    [[AND:%.*]] = and i8 [[A:%.*]], -2
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i8 [[AND]], -2
 ; CHECK-NEXT:    call void @llvm.assume(i1 [[CMP]])
 ; CHECK-NEXT:    [[A_OFF:%.*]] = add i8 [[A]], 1
 ; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i8 [[A_OFF]], 1
 ; CHECK-NEXT:    br i1 [[SWITCH]], label [[TRUE:%.*]], label [[FALSE:%.*]]
 ; CHECK:       true:
 ; CHECK-NEXT:    call void @foo(i32 1)
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       false:
 ; CHECK-NEXT:    call void @foo(i32 3)
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   %and = and i8 %a, 254
   %cmp = icmp eq i8 %and, 254
   call void @llvm.assume(i1 %cmp)
   switch i8 %a, label %default [i8 255, label %true
   i8 254, label %false]
 true:

 ; CHECK-NEXT:    [[AND:%.*]] = and i8 [[A:%.*]], -2
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i8 [[AND]], -2
 ; CHECK-NEXT:    call void @llvm.assume(i1 [[CMP]])
 ; CHECK-NEXT:    [[A_OFF:%.*]] = add i8 [[A]], 1
 ; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i8 [[A_OFF]], 1
 ; CHECK-NEXT:    br i1 [[SWITCH]], label [[TRUE:%.*]], label [[FALSE:%.*]]
 ; CHECK:       true:
 ; CHECK-NEXT:    call void @foo(i32 1)
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       false:
 ; CHECK-NEXT:    call void @foo(i32 3)
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   %and = and i8 %a, 254
   %cmp = icmp eq i8 %and, 254
   call void @llvm.assume(i1 %cmp)
   switch i8 %a, label %default [i8 255, label %true
   i8 254, label %false
   i8 0, label %also_dead]

llvm/test/Transforms/SimplifyCFG/switch-masked-bits.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s
 
 define i32 @test1(i32 %x) nounwind {
 ; CHECK-LABEL: @test1(
-; CHECK-NEXT:  a:
+; CHECK-NEXT:  common.ret:
 ; CHECK-NEXT:    [[I:%.*]] = shl i32 [[X:%.*]], 1
 ; CHECK-NEXT:    [[COND:%.*]] = icmp eq i32 [[I]], 24
-; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[COND]], i32 5, i32 0
-; CHECK-NEXT:    ret i32 [[SPEC_SELECT]]
+; CHECK-NEXT:    [[DOT:%.*]] = select i1 [[COND]], i32 5, i32 0
+; CHECK-NEXT:    ret i32 [[DOT]]
 ;
   %i = shl i32 %x, 1
   switch i32 %i, label %a [
   i32 21, label %b
   i32 24, label %c
   ]
 
 a:

 ; We're sign extending an 8-bit value.
 ; The switch condition must be in the range [-128, 127], so any cases outside of that range must be dead.
 
 define i1 @repeated_signbits(i8 %condition) {
 ; CHECK-LABEL: @repeated_signbits(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[SEXT:%.*]] = sext i8 [[CONDITION:%.*]] to i32
 ; CHECK-NEXT:    switch i32 [[SEXT]], label [[DEFAULT:%.*]] [
-; CHECK-NEXT:    i32 0, label [[A:%.*]]
-; CHECK-NEXT:    i32 127, label [[A]]
-; CHECK-NEXT:    i32 -128, label [[A]]
-; CHECK-NEXT:    i32 -1, label [[A]]
+; CHECK-NEXT:    i32 0, label [[COMMON_RET:%.*]]
+; CHECK-NEXT:    i32 127, label [[COMMON_RET]]
+; CHECK-NEXT:    i32 -128, label [[COMMON_RET]]
+; CHECK-NEXT:    i32 -1, label [[COMMON_RET]]
 ; CHECK-NEXT:    ]
-; CHECK:       a:
-; CHECK-NEXT:    [[MERGE:%.*]] = phi i1 [ true, [[ENTRY:%.*]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ], [ false, [[DEFAULT]] ]
-; CHECK-NEXT:    ret i1 [[MERGE]]
 ; CHECK:       default:
-; CHECK-NEXT:    br label [[A]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i1 [ false, [[DEFAULT]] ], [ true, [[ENTRY:%.*]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ], [ true, [[ENTRY]] ]
+; CHECK-NEXT:    ret i1 [[COMMON_RET_OP]]
 ;
 entry:
   %sext = sext i8 %condition to i32
   switch i32 %sext, label %default [
   i32 -2147483648, label %a
   i32 -129, label %a
   i32 -128, label %a
   i32 -1, label %a

llvm/test/Transforms/SimplifyCFG/switch-on-const-select.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s
 
 ; Test basic folding to a conditional branch.
 define i32 @foo(i64 %x, i64 %y) nounwind {
 ; CHECK-LABEL: @foo(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[EQ:%.*]] = icmp eq i64 [[X:%.*]], [[Y:%.*]]
 ; CHECK-NEXT:    br i1 [[EQ]], label [[B:%.*]], label [[SWITCH:%.*]]
 ; CHECK:       switch:
 ; CHECK-NEXT:    [[LT:%.*]] = icmp slt i64 [[X]], [[Y]]
 ; CHECK-NEXT:    br i1 [[LT]], label [[A:%.*]], label [[B]]
 ; CHECK:       a:
 ; CHECK-NEXT:    tail call void @bees.a() #[[ATTR0:[0-9]+]]
-; CHECK-NEXT:    ret i32 1
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       b:
 ; CHECK-NEXT:    [[RETVAL:%.*]] = phi i32 [ 0, [[SWITCH]] ], [ 2, [[ENTRY:%.*]] ]
 ; CHECK-NEXT:    tail call void @bees.b() #[[ATTR0]]
-; CHECK-NEXT:    ret i32 [[RETVAL]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ 1, [[A]] ], [ [[RETVAL]], [[B]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ;
 entry:
   %eq = icmp eq i64 %x, %y
   br i1 %eq, label %b, label %switch
 switch:
   %lt = icmp slt i64 %x, %y
   %qux = select i1 %lt, i32 0, i32 2
   switch i32 %qux, label %bees [
bees:
   unreachable
 }
 
 ; A final test, for phi node munging.
 define i32 @xyzzy(i64 %x, i64 %y) {
 ; CHECK-LABEL: @xyzzy(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[EQ:%.*]] = icmp eq i64 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:    br i1 [[EQ]], label [[COMMON_RET:%.*]], label [[CONT:%.*]]
+; CHECK:       cont:
 ; CHECK-NEXT:    [[LT:%.*]] = icmp slt i64 [[X]], [[Y]]
 ; CHECK-NEXT:    [[SPEC_SELECT:%.*]] = select i1 [[LT]], i32 -1, i32 1
-; CHECK-NEXT:    [[VAL:%.*]] = select i1 [[EQ]], i32 0, i32 [[SPEC_SELECT]]
-; CHECK-NEXT:    ret i32 [[VAL]]
+; CHECK-NEXT:    ret i32 [[SPEC_SELECT]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    ret i32 0
 ;
 entry:
   %eq = icmp eq i64 %x, %y
   br i1 %eq, label %r, label %cont
 cont:
   %lt = icmp slt i64 %x, %y
   %qux = select i1 %lt, i32 0, i32 2
   switch i32 %qux, label %bees [

llvm/test/Transforms/SimplifyCFG/switch-range-to-icmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s
 
 declare i32 @f(i32)
 
 define i32 @basic(i32 %x) {
 ; CHECK-LABEL: @basic(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[X_OFF:%.*]] = add i32 [[X:%.*]], -5
 ; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[X_OFF]], 3
 ; CHECK-NEXT:    br i1 [[SWITCH]], label [[A:%.*]], label [[DEFAULT:%.*]]
 ; CHECK:       default:
 ; CHECK-NEXT:    [[TMP0:%.*]] = call i32 @f(i32 0)
-; CHECK-NEXT:    ret i32 [[TMP0]]
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       a:
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @f(i32 1)
-; CHECK-NEXT:    ret i32 [[TMP1]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ [[TMP0]], [[DEFAULT]] ], [ [[TMP1]], [[A]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ;
 
 entry:
   switch i32 %x, label %default [
   i32 5, label %a
   i32 6, label %a
   i32 7, label %a
   ]

 define i32 @unreachable(i32 %x) {
 ; CHECK-LABEL: @unreachable(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[X_OFF:%.*]] = add i32 [[X:%.*]], -5
 ; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[X_OFF]], 3
 ; CHECK-NEXT:    br i1 [[SWITCH]], label [[A:%.*]], label [[B:%.*]]
 ; CHECK:       a:
 ; CHECK-NEXT:    [[TMP0:%.*]] = call i32 @f(i32 0)
-; CHECK-NEXT:    ret i32 [[TMP0]]
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       b:
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @f(i32 1)
-; CHECK-NEXT:    ret i32 [[TMP1]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ [[TMP0]], [[A]] ], [ [[TMP1]], [[B]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ;
 
 entry:
   switch i32 %x, label %unreachable [
   i32 5, label %a
   i32 6, label %a
   i32 7, label %a
   i32 10, label %b

 define i32 @unreachable2(i32 %x) {
 ; CHECK-LABEL: @unreachable2(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[X_OFF:%.*]] = add i32 [[X:%.*]], -5
 ; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[X_OFF]], 3
 ; CHECK-NEXT:    br i1 [[SWITCH]], label [[A:%.*]], label [[B:%.*]]
 ; CHECK:       a:
 ; CHECK-NEXT:    [[TMP0:%.*]] = call i32 @f(i32 0)
-; CHECK-NEXT:    ret i32 [[TMP0]]
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       b:
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @f(i32 1)
-; CHECK-NEXT:    ret i32 [[TMP1]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ [[TMP0]], [[A]] ], [ [[TMP1]], [[B]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ;
 
 entry:
   ; Note: folding the most popular case destination into the default
   ; would prevent switch-to-icmp here.
   switch i32 %x, label %unreachable [
   i32 5, label %a
   i32 6, label %a

llvm/test/Transforms/SimplifyCFG/switch_create-custom-dl.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s
 target datalayout="p:40:64:64:32"
 
 declare void @foo1()
 
 declare void @foo2()
 
 define void @test1(i32 %V) {
 ; CHECK-LABEL: @test1(
 ; CHECK-NEXT:    switch i32 [[V:%.*]], label [[F:%.*]] [
 ; CHECK-NEXT:    i32 17, label [[T:%.*]]
 ; CHECK-NEXT:    i32 4, label [[T]]
 ; CHECK-NEXT:    ]
 ; CHECK:       T:
 ; CHECK-NEXT:    call void @foo1()
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       F:
 ; CHECK-NEXT:    call void @foo2()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   %C1 = icmp eq i32 %V, 4         ; <i1> [#uses=1]
   %C2 = icmp eq i32 %V, 17                ; <i1> [#uses=1]
   %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
   br i1 %CN, label %T, label %F
 T:              ; preds = %0
   call void @foo1( )
   ret void
 F:              ; preds = %0
   call void @foo2( )
   ret void
 }
 
 define void @test1_ptr(i32* %V) {
 ; CHECK-LABEL: @test1_ptr(
 ; CHECK-NEXT:    [[MAGICPTR:%.*]] = ptrtoint i32* [[V:%.*]] to i40
 ; CHECK-NEXT:    switch i40 [[MAGICPTR]], label [[F:%.*]] [
 ; CHECK-NEXT:    i40 17, label [[T:%.*]]
 ; CHECK-NEXT:    i40 4, label [[T]]
 ; CHECK-NEXT:    ]
 ; CHECK:       T:
 ; CHECK-NEXT:    call void @foo1()
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       F:
 ; CHECK-NEXT:    call void @foo2()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   %C1 = icmp eq i32* %V, inttoptr (i32 4 to i32*)
   %C2 = icmp eq i32* %V, inttoptr (i32 17 to i32*)
   %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
   br i1 %CN, label %T, label %F
 T:              ; preds = %0
   call void @foo1( )
   ret void
 F:              ; preds = %0
   call void @foo2( )
   ret void
 }
 
 define void @test1_ptr_as1(i32 addrspace(1)* %V) {
 ; CHECK-LABEL: @test1_ptr_as1(
 ; CHECK-NEXT:    [[MAGICPTR:%.*]] = ptrtoint i32 addrspace(1)* [[V:%.*]] to i40
 ; CHECK-NEXT:    switch i40 [[MAGICPTR]], label [[F:%.*]] [
 ; CHECK-NEXT:    i40 17, label [[T:%.*]]
 ; CHECK-NEXT:    i40 4, label [[T]]
 ; CHECK-NEXT:    ]
 ; CHECK:       T:
 ; CHECK-NEXT:    call void @foo1()
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       F:
 ; CHECK-NEXT:    call void @foo2()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   %C1 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 4 to i32 addrspace(1)*)
   %C2 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 17 to i32 addrspace(1)*)
   %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
   br i1 %CN, label %T, label %F
 T:              ; preds = %0
   call void @foo1( )
   ret void
 F:              ; preds = %0
   call void @foo2( )
   ret void
 }
 
 define void @test2(i32 %V) {
 ; CHECK-LABEL: @test2(
 ; CHECK-NEXT:    switch i32 [[V:%.*]], label [[T:%.*]] [
 ; CHECK-NEXT:    i32 17, label [[F:%.*]]
 ; CHECK-NEXT:    i32 4, label [[F]]
 ; CHECK-NEXT:    ]
 ; CHECK:       T:
 ; CHECK-NEXT:    call void @foo1()
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       F:
 ; CHECK-NEXT:    call void @foo2()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   %C1 = icmp ne i32 %V, 4         ; <i1> [#uses=1]
   %C2 = icmp ne i32 %V, 17                ; <i1> [#uses=1]
   %CN = and i1 %C1, %C2           ; <i1> [#uses=1]
   br i1 %CN, label %T, label %F
 T:              ; preds = %0
   call void @foo1( )
   ret void
 F:              ; preds = %0
   call void @foo2( )
   ret void
 }
 
 define void @test3(i32 %V) {
 ; CHECK-LABEL: @test3(
 ; CHECK-NEXT:    switch i32 [[V:%.*]], label [[F:%.*]] [
 ; CHECK-NEXT:    i32 4, label [[T:%.*]]
 ; CHECK-NEXT:    i32 17, label [[T]]
 ; CHECK-NEXT:    ]
 ; CHECK:       T:
 ; CHECK-NEXT:    call void @foo1()
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       F:
 ; CHECK-NEXT:    call void @foo2()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   %C1 = icmp eq i32 %V, 4         ; <i1> [#uses=1]
   br i1 %C1, label %T, label %N
 N:              ; preds = %0
   %C2 = icmp eq i32 %V, 17                ; <i1> [#uses=1]
   br i1 %C2, label %T, label %F
 T:              ; preds = %N, %0

 }
 
 define void @test7(i8 zeroext %c, i32 %x) nounwind ssp noredzone {
 ; CHECK-LABEL: @test7(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 32
 ; CHECK-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[SWITCH_EARLY_TEST:%.*]]
 ; CHECK:       switch.early.test:
-; CHECK-NEXT:    switch i8 [[C:%.*]], label [[IF_END:%.*]] [
+; CHECK-NEXT:    switch i8 [[C:%.*]], label [[COMMON_RET:%.*]] [
 ; CHECK-NEXT:    i8 99, label [[IF_THEN]]
 ; CHECK-NEXT:    i8 97, label [[IF_THEN]]
 ; CHECK-NEXT:    ]
 ; CHECK:       if.then:
 ; CHECK-NEXT:    tail call void @foo1() #[[ATTR2:[0-9]+]]
-; CHECK-NEXT:    ret void
-; CHECK:       if.end:
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   %cmp = icmp ult i32 %x, 32
   %cmp4 = icmp eq i8 %c, 97
   %or.cond = or i1 %cmp, %cmp4
   %cmp9 = icmp eq i8 %c, 99
   %or.cond11 = or i1 %or.cond, %cmp9

 define i32 @test8(i8 zeroext %c, i32 %x, i1 %C) nounwind ssp noredzone {
 ; CHECK-LABEL: @test8(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br i1 [[C:%.*]], label [[N:%.*]], label [[IF_THEN:%.*]]
 ; CHECK:       N:
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 32
 ; CHECK-NEXT:    br i1 [[CMP]], label [[IF_THEN]], label [[SWITCH_EARLY_TEST:%.*]]
 ; CHECK:       switch.early.test:
-; CHECK-NEXT:    switch i8 [[C:%.*]], label [[IF_END:%.*]] [
+; CHECK-NEXT:    switch i8 [[C:%.*]], label [[COMMON_RET:%.*]] [
 ; CHECK-NEXT:    i8 99, label [[IF_THEN]]
 ; CHECK-NEXT:    i8 97, label [[IF_THEN]]
 ; CHECK-NEXT:    ]
 ; CHECK:       if.then:
 ; CHECK-NEXT:    [[A:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ 42, [[SWITCH_EARLY_TEST]] ], [ 42, [[N]] ], [ 42, [[SWITCH_EARLY_TEST]] ]
 ; CHECK-NEXT:    tail call void @foo1() #[[ATTR2]]
-; CHECK-NEXT:    ret i32 [[A]]
-; CHECK:       if.end:
-; CHECK-NEXT:    ret i32 0
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ [[A]], [[IF_THEN]] ], [ 0, [[SWITCH_EARLY_TEST]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ;
 entry:
   br i1 %C, label %N, label %if.then
 N:
   %cmp = icmp ult i32 %x, 32
   %cmp4 = icmp eq i8 %c, 97
   %or.cond = or i1 %cmp, %cmp4
   %cmp9 = icmp eq i8 %c, 99

 ; CHECK-NEXT:    br i1 [[COND:%.*]], label [[SWITCH_EARLY_TEST:%.*]], label [[F:%.*]]
 ; CHECK:       switch.early.test:
 ; CHECK-NEXT:    switch i32 [[MODE:%.*]], label [[T:%.*]] [
 ; CHECK-NEXT:    i32 51, label [[F]]
 ; CHECK-NEXT:    i32 0, label [[F]]
 ; CHECK-NEXT:    ]
 ; CHECK:       T:
 ; CHECK-NEXT:    call void @foo1()
-; CHECK-NEXT:    ret i32 123
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       F:
 ; CHECK-NEXT:    call void @foo2()
-; CHECK-NEXT:    ret i32 324
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ 123, [[T]] ], [ 324, [[F]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ;
   %A = icmp ne i32 %mode, 0
   %B = icmp ne i32 %mode, 51
   %C = and i1 %A, %B
   %D = and i1 %C, %Cond
   br i1 %D, label %T, label %F
 T:
   call void @foo1()

 }
 
 ; Check that we don't turn an icmp into a switch where it's not useful.
 define void @test17(i32 %x, i32 %y) {
 ; CHECK-LABEL: @test17(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 3
 ; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[Y:%.*]], 2
 ; CHECK-NEXT:    [[OR_COND775:%.*]] = or i1 [[CMP]], [[SWITCH]]
-; CHECK-NEXT:    br i1 [[OR_COND775]], label [[LOR_LHS_FALSE8:%.*]], label [[RETURN:%.*]]
+; CHECK-NEXT:    br i1 [[OR_COND775]], label [[LOR_LHS_FALSE8:%.*]], label [[COMMON_RET:%.*]]
 ; CHECK:       lor.lhs.false8:
 ; CHECK-NEXT:    tail call void @foo1()
-; CHECK-NEXT:    ret void
-; CHECK:       return:
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   %cmp = icmp ult i32 %x, 3
   %switch = icmp ult i32 %y, 2
   %or.cond775 = or i1 %cmp, %switch
   br i1 %or.cond775, label %lor.lhs.false8, label %return
 
 lor.lhs.false8:
if.then27:                                        ; preds = %entry
   unreachable
 
 if.end29:                                         ; preds = %entry
   ret void
 }
 
 define void @test19(i32 %arg) {
 ; CHECK-LABEL: @test19(
-; CHECK-NEXT:    switch i32 [[ARG:%.*]], label [[ELSE:%.*]] [
+; CHECK-NEXT:    switch i32 [[ARG:%.*]], label [[COMMON_RET:%.*]] [
 ; CHECK-NEXT:    i32 32, label [[IF:%.*]]
 ; CHECK-NEXT:    i32 13, label [[IF]]
 ; CHECK-NEXT:    i32 12, label [[IF]]
 ; CHECK-NEXT:    ]
 ; CHECK:       if:
 ; CHECK-NEXT:    call void @foo1()
-; CHECK-NEXT:    ret void
-; CHECK:       else:
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   %and = and i32 %arg, -2
   %cmp1 = icmp eq i32 %and, 12
   %cmp2 = icmp eq i32 %arg, 32
   %pred = or i1 %cmp1, %cmp2
   br i1 %pred, label %if, label %else
 
 if:
   call void @foo1()
   ret void
 
 else:
   ret void
 }
 
 ; Since %cmp1 is always false, a switch is never formed
 define void @test20(i32 %arg) {
 ; CHECK-LABEL: @test20(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[ARG:%.*]], -2
 ; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[AND]], 13
 ; CHECK-NEXT:    [[CMP2:%.*]] = icmp eq i32 [[ARG]], 32
 ; CHECK-NEXT:    [[PRED:%.*]] = or i1 [[CMP1]], [[CMP2]]
-; CHECK-NEXT:    br i1 [[PRED]], label [[IF:%.*]], label [[ELSE:%.*]]
+; CHECK-NEXT:    br i1 [[PRED]], label [[IF:%.*]], label [[COMMON_RET:%.*]]
 ; CHECK:       if:
 ; CHECK-NEXT:    call void @foo1()
-; CHECK-NEXT:    ret void
-; CHECK:       else:
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   %and = and i32 %arg, -2
   %cmp1 = icmp eq i32 %and, 13
   %cmp2 = icmp eq i32 %arg, 32
   %pred = or i1 %cmp1, %cmp2
   br i1 %pred, label %if, label %else
 
 if:
   call void @foo1()
   ret void
 
 else:
   ret void
 }
 
 ; Form a switch when or'ing a power of two
 define void @test21(i32 %arg) {
 ; CHECK-LABEL: @test21(
 ; CHECK-NEXT:    switch i32 [[ARG:%.*]], label [[IF:%.*]] [
-; CHECK-NEXT:    i32 32, label [[ELSE:%.*]]
-; CHECK-NEXT:    i32 13, label [[ELSE]]
-; CHECK-NEXT:    i32 12, label [[ELSE]]
+; CHECK-NEXT:    i32 32, label [[COMMON_RET:%.*]]
+; CHECK-NEXT:    i32 13, label [[COMMON_RET]]
+; CHECK-NEXT:    i32 12, label [[COMMON_RET]]
 ; CHECK-NEXT:    ]
 ; CHECK:       if:
 ; CHECK-NEXT:    call void @foo1()
-; CHECK-NEXT:    ret void
-; CHECK:       else:
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   %and = or i32 %arg, 1
   %cmp1 = icmp ne i32 %and, 13
   %cmp2 = icmp ne i32 %arg, 32
   %pred = and i1 %cmp1, %cmp2
   br i1 %pred, label %if, label %else
 
 if:
   call void @foo1()
   ret void
 
 else:
   ret void
 }
 
 ; Since %cmp1 is always false, a switch is never formed
 define void @test22(i32 %arg) {
 ; CHECK-LABEL: @test22(
 ; CHECK-NEXT:    [[AND:%.*]] = or i32 [[ARG:%.*]], 1
 ; CHECK-NEXT:    [[CMP1:%.*]] = icmp ne i32 [[AND]], 12
 ; CHECK-NEXT:    [[CMP2:%.*]] = icmp ne i32 [[ARG]], 32
 ; CHECK-NEXT:    [[PRED:%.*]] = and i1 [[CMP1]], [[CMP2]]
-; CHECK-NEXT:    br i1 [[PRED]], label [[IF:%.*]], label [[ELSE:%.*]]
+; CHECK-NEXT:    br i1 [[PRED]], label [[IF:%.*]], label [[COMMON_RET:%.*]]
 ; CHECK:       if:
 ; CHECK-NEXT:    call void @foo1()
-; CHECK-NEXT:    ret void
-; CHECK:       else:
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   %and = or i32 %arg, 1
   %cmp1 = icmp ne i32 %and, 12
   %cmp2 = icmp ne i32 %arg, 32
   %pred = and i1 %cmp1, %cmp2
   br i1 %pred, label %if, label %else
 
 if:
   call void @foo1()
   ret void
 
 else:
   ret void
 }

llvm/test/Transforms/SimplifyCFG/switch_create.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s
 ; RUN: opt -S -data-layout="p:32:32-p1:16:16" -simplifycfg -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=CHECK -check-prefix=DL %s
 
 declare void @foo1()
 
 declare void @foo2()
 
 define void @test1(i32 %V) {
 ; CHECK-LABEL: @test1(
 ; CHECK-NEXT:    switch i32 [[V:%.*]], label [[F:%.*]] [
 ; CHECK-NEXT:    i32 17, label [[T:%.*]]
 ; CHECK-NEXT:    i32 4, label [[T]]
 ; CHECK-NEXT:    ]
 ; CHECK:       T:
 ; CHECK-NEXT:    call void @foo1()
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       F:
 ; CHECK-NEXT:    call void @foo2()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   %C1 = icmp eq i32 %V, 4         ; <i1> [#uses=1]
   %C2 = icmp eq i32 %V, 17                ; <i1> [#uses=1]
   %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
   br i1 %CN, label %T, label %F
 T:              ; preds = %0
   call void @foo1( )
   ret void
 F:              ; preds = %0
   call void @foo2( )
   ret void
 }
 
 define void @test1_select(i32 %V) {
 ; CHECK-LABEL: @test1_select(
 ; CHECK-NEXT:    switch i32 [[V:%.*]], label [[F:%.*]] [
 ; CHECK-NEXT:    i32 17, label [[T:%.*]]
 ; CHECK-NEXT:    i32 4, label [[T]]
 ; CHECK-NEXT:    ]
 ; CHECK:       T:
 ; CHECK-NEXT:    call void @foo1()
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       F:
 ; CHECK-NEXT:    call void @foo2()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   %C1 = icmp eq i32 %V, 4
   %C2 = icmp eq i32 %V, 17
   %CN = select i1 %C1, i1 true, i1 %C2
   br i1 %CN, label %T, label %F
 T:
   call void @foo1( )
   ret void
 F:
   call void @foo2( )
   ret void
 }
 
 define void @test1_ptr(i32* %V) {
 ; DL-LABEL: @test1_ptr(
 ; DL-NEXT:    [[MAGICPTR:%.*]] = ptrtoint i32* [[V:%.*]] to i32
 ; DL-NEXT:    switch i32 [[MAGICPTR]], label [[F:%.*]] [
 ; DL-NEXT:    i32 17, label [[T:%.*]]
 ; DL-NEXT:    i32 4, label [[T]]
 ; DL-NEXT:    ]
 ; DL:       T:
 ; DL-NEXT:    call void @foo1()
-; DL-NEXT:    ret void
+; DL-NEXT:    br label [[COMMON_RET:%.*]]
 ; DL:       F:
 ; DL-NEXT:    call void @foo2()
+; DL-NEXT:    br label [[COMMON_RET]]
+; DL:       common.ret:
 ; DL-NEXT:    ret void
 ;
   %C1 = icmp eq i32* %V, inttoptr (i32 4 to i32*)
   %C2 = icmp eq i32* %V, inttoptr (i32 17 to i32*)
   %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
   br i1 %CN, label %T, label %F
 T:              ; preds = %0
   call void @foo1( )
   ret void
 F:              ; preds = %0
   call void @foo2( )
   ret void
 }
 
 define void @test1_ptr_as1(i32 addrspace(1)* %V) {
 ; DL-LABEL: @test1_ptr_as1(
 ; DL-NEXT:    [[MAGICPTR:%.*]] = ptrtoint i32 addrspace(1)* [[V:%.*]] to i16
 ; DL-NEXT:    switch i16 [[MAGICPTR]], label [[F:%.*]] [
 ; DL-NEXT:    i16 17, label [[T:%.*]]
 ; DL-NEXT:    i16 4, label [[T]]
 ; DL-NEXT:    ]
 ; DL:       T:
 ; DL-NEXT:    call void @foo1()
-; DL-NEXT:    ret void
+; DL-NEXT:    br label [[COMMON_RET:%.*]]
 ; DL:       F:
 ; DL-NEXT:    call void @foo2()
+; DL-NEXT:    br label [[COMMON_RET]]
+; DL:       common.ret:
 ; DL-NEXT:    ret void
 ;
   %C1 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 4 to i32 addrspace(1)*)
   %C2 = icmp eq i32 addrspace(1)* %V, inttoptr (i32 17 to i32 addrspace(1)*)
   %CN = or i1 %C1, %C2            ; <i1> [#uses=1]
   br i1 %CN, label %T, label %F
 T:              ; preds = %0
   call void @foo1( )
   ret void
 F:              ; preds = %0
   call void @foo2( )
   ret void
 }
 
 define void @test2(i32 %V) {
 ; CHECK-LABEL: @test2(
 ; CHECK-NEXT:    switch i32 [[V:%.*]], label [[T:%.*]] [
 ; CHECK-NEXT:    i32 17, label [[F:%.*]]
 ; CHECK-NEXT:    i32 4, label [[F]]
 ; CHECK-NEXT:    ]
 ; CHECK:       T:
 ; CHECK-NEXT:    call void @foo1()
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       F:
 ; CHECK-NEXT:    call void @foo2()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   %C1 = icmp ne i32 %V, 4         ; <i1> [#uses=1]
   %C2 = icmp ne i32 %V, 17                ; <i1> [#uses=1]
   %CN = and i1 %C1, %C2           ; <i1> [#uses=1]
   br i1 %CN, label %T, label %F
 T:              ; preds = %0
   call void @foo1( )
   ret void
 F:              ; preds = %0
   call void @foo2( )
   ret void
 }
 
 define void @test2_select(i32 %V) {
 ; CHECK-LABEL: @test2_select(
 ; CHECK-NEXT:    switch i32 [[V:%.*]], label [[T:%.*]] [
 ; CHECK-NEXT:    i32 17, label [[F:%.*]]
 ; CHECK-NEXT:    i32 4, label [[F]]
 ; CHECK-NEXT:    ]
 ; CHECK:       T:
 ; CHECK-NEXT:    call void @foo1()
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       F:
 ; CHECK-NEXT:    call void @foo2()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   %C1 = icmp ne i32 %V, 4
   %C2 = icmp ne i32 %V, 17
   %CN = select i1 %C1, i1 %C2, i1 false
   br i1 %CN, label %T, label %F
 T:
   call void @foo1( )
   ret void
 F:
   call void @foo2( )
   ret void
 }
 
 define void @test3(i32 %V) {
 ; CHECK-LABEL: @test3(
 ; CHECK-NEXT:    switch i32 [[V:%.*]], label [[F:%.*]] [
 ; CHECK-NEXT:    i32 4, label [[T:%.*]]
 ; CHECK-NEXT:    i32 17, label [[T]]
 ; CHECK-NEXT:    ]
 ; CHECK:       T:
 ; CHECK-NEXT:    call void @foo1()
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       F:
 ; CHECK-NEXT:    call void @foo2()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   %C1 = icmp eq i32 %V, 4         ; <i1> [#uses=1]
   br i1 %C1, label %T, label %N
 N:              ; preds = %0
   %C2 = icmp eq i32 %V, 17                ; <i1> [#uses=1]
   br i1 %C2, label %T, label %F
 T:              ; preds = %N, %0

 }
 
 define void @test7(i8 zeroext %c, i32 %x) nounwind ssp noredzone {
 ; CHECK-LABEL: @test7(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 32
 ; CHECK-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[SWITCH_EARLY_TEST:%.*]]
 ; CHECK:       switch.early.test:
-; CHECK-NEXT:    switch i8 [[C:%.*]], label [[IF_END:%.*]] [
+; CHECK-NEXT:    switch i8 [[C:%.*]], label [[COMMON_RET:%.*]] [
 ; CHECK-NEXT:    i8 99, label [[IF_THEN]]
 ; CHECK-NEXT:    i8 97, label [[IF_THEN]]
 ; CHECK-NEXT:    ]
 ; CHECK:       if.then:
 ; CHECK-NEXT:    tail call void @foo1() #[[ATTR2:[0-9]+]]
-; CHECK-NEXT:    ret void
-; CHECK:       if.end:
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
 entry:
   %cmp = icmp ult i32 %x, 32
   %cmp4 = icmp eq i8 %c, 97
   %or.cond = or i1 %cmp, %cmp4
   %cmp9 = icmp eq i8 %c, 99
   %or.cond11 = or i1 %or.cond, %cmp9

 define i32 @test8(i8 zeroext %c, i32 %x, i1 %C) nounwind ssp noredzone {
 ; CHECK-LABEL: @test8(
 ; CHECK-NEXT:  entry:
 ; CHECK-NEXT:    br i1 [[C:%.*]], label [[N:%.*]], label [[IF_THEN:%.*]]
 ; CHECK:       N:
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 32
 ; CHECK-NEXT:    br i1 [[CMP]], label [[IF_THEN]], label [[SWITCH_EARLY_TEST:%.*]]
 ; CHECK:       switch.early.test:
-; CHECK-NEXT:    switch i8 [[C:%.*]], label [[IF_END:%.*]] [
+; CHECK-NEXT:    switch i8 [[C:%.*]], label [[COMMON_RET:%.*]] [
 ; CHECK-NEXT:    i8 99, label [[IF_THEN]]
 ; CHECK-NEXT:    i8 97, label [[IF_THEN]]
 ; CHECK-NEXT:    ]
 ; CHECK:       if.then:
 ; CHECK-NEXT:    [[A:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ 42, [[SWITCH_EARLY_TEST]] ], [ 42, [[N]] ], [ 42, [[SWITCH_EARLY_TEST]] ]
 ; CHECK-NEXT:    tail call void @foo1() #[[ATTR2]]
-; CHECK-NEXT:    ret i32 [[A]]
-; CHECK:       if.end:
-; CHECK-NEXT:    ret i32 0
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ [[A]], [[IF_THEN]] ], [ 0, [[SWITCH_EARLY_TEST]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ;
 entry:
   br i1 %C, label %N, label %if.then
 N:
   %cmp = icmp ult i32 %x, 32
   %cmp4 = icmp eq i8 %c, 97
   %or.cond = or i1 %cmp, %cmp4
   %cmp9 = icmp eq i8 %c, 99

 ; CHECK-NEXT:    br i1 [[COND:%.*]], label [[SWITCH_EARLY_TEST:%.*]], label [[F:%.*]]
 ; CHECK:       switch.early.test:
 ; CHECK-NEXT:    switch i32 [[MODE:%.*]], label [[T:%.*]] [
 ; CHECK-NEXT:    i32 51, label [[F]]
 ; CHECK-NEXT:    i32 0, label [[F]]
 ; CHECK-NEXT:    ]
 ; CHECK:       T:
 ; CHECK-NEXT:    call void @foo1()
-; CHECK-NEXT:    ret i32 123
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       F:
 ; CHECK-NEXT:    call void @foo2()
-; CHECK-NEXT:    ret i32 324
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ 123, [[T]] ], [ 324, [[F]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ;
   %A = icmp ne i32 %mode, 0
   %B = icmp ne i32 %mode, 51
   %C = and i1 %A, %B
   %D = and i1 %C, %Cond
   br i1 %D, label %T, label %F
 T:
   call void @foo1()

 ; CHECK-NEXT:    br i1 [[COND:%.*]], label [[SWITCH_EARLY_TEST:%.*]], label [[F:%.*]]
 ; CHECK:       switch.early.test:
 ; CHECK-NEXT:    switch i32 [[MODE:%.*]], label [[T:%.*]] [
 ; CHECK-NEXT:    i32 51, label [[F]]
 ; CHECK-NEXT:    i32 0, label [[F]]
 ; CHECK-NEXT:    ]
 ; CHECK:       T:
 ; CHECK-NEXT:    call void @foo1()
-; CHECK-NEXT:    ret i32 123
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       F:
 ; CHECK-NEXT:    call void @foo2()
-; CHECK-NEXT:    ret i32 324
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ 123, [[T]] ], [ 324, [[F]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ;
   %A = icmp ne i32 %mode, 0
   %B = icmp ne i32 %mode, 51
   %C = select i1 %A, i1 %B, i1 false
   %D = select i1 %C, i1 %Cond, i1 false
   br i1 %D, label %T, label %F
 T:
   call void @foo1()

 ; CHECK-NEXT:    br i1 [[COND:%.*]], label [[SWITCH_EARLY_TEST:%.*]], label [[F:%.*]]
 ; CHECK:       switch.early.test:
 ; CHECK-NEXT:    switch i32 [[MODE:%.*]], label [[T:%.*]] [
 ; CHECK-NEXT:    i32 51, label [[F]]
 ; CHECK-NEXT:    i32 0, label [[F]]
 ; CHECK-NEXT:    ]
 ; CHECK:       T:
 ; CHECK-NEXT:    call void @foo1()
-; CHECK-NEXT:    ret i32 123
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       F:
 ; CHECK-NEXT:    call void @foo2()
-; CHECK-NEXT:    ret i32 324
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ 123, [[T]] ], [ 324, [[F]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ;
   %A = icmp ne i32 %mode, 0
   %B = icmp ne i32 %mode, 51
   %C = select i1 %A, i1 %B, i1 false
   %D = and i1 %C, %Cond
   br i1 %D, label %T, label %F
 T:
   call void @foo1()

 ; CHECK-NEXT:    br i1 [[COND:%.*]], label [[SWITCH_EARLY_TEST:%.*]], label [[F:%.*]]
 ; CHECK:       switch.early.test:
 ; CHECK-NEXT:    switch i32 [[MODE:%.*]], label [[T:%.*]] [
 ; CHECK-NEXT:    i32 51, label [[F]]
 ; CHECK-NEXT:    i32 0, label [[F]]
 ; CHECK-NEXT:    ]
 ; CHECK:       T:
 ; CHECK-NEXT:    call void @foo1()
-; CHECK-NEXT:    ret i32 123
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       F:
 ; CHECK-NEXT:    call void @foo2()
-; CHECK-NEXT:    ret i32 324
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
+; CHECK-NEXT:    [[COMMON_RET_OP:%.*]] = phi i32 [ 123, [[T]] ], [ 324, [[F]] ]
+; CHECK-NEXT:    ret i32 [[COMMON_RET_OP]]
 ;
   %A = icmp ne i32 %mode, 0
   %B = icmp ne i32 %mode, 51
   %C = select i1 %A, i1 %B, i1 false
   %D = select i1 %C, i1 %Cond, i1 false
   br i1 %D, label %T, label %F
 T:
   call void @foo1()

 }
 
 ; Check that we don't turn an icmp into a switch where it's not useful.
 define void @test17(i32 %x, i32 %y) {
 ; CHECK-LABEL: @test17(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 3
 ; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[Y:%.*]], 2
 ; CHECK-NEXT:    [[OR_COND775:%.*]] = or i1 [[CMP]], [[SWITCH]]
-; CHECK-NEXT:    br i1 [[OR_COND775]], label [[LOR_LHS_FALSE8:%.*]], label [[RETURN:%.*]]
+; CHECK-NEXT:    br i1 [[OR_COND775]], label [[LOR_LHS_FALSE8:%.*]], label [[COMMON_RET:%.*]]
 ; CHECK:       lor.lhs.false8:
 ; CHECK-NEXT:    tail call void @foo1()
-; CHECK-NEXT:    ret void
-; CHECK:       return:
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   %cmp = icmp ult i32 %x, 3
   %switch = icmp ult i32 %y, 2
   %or.cond775 = or i1 %cmp, %switch
   br i1 %or.cond775, label %lor.lhs.false8, label %return
 
 lor.lhs.false8:
   tail call void @foo1()
   ret void
 
 return:
   ret void
 
 }
 
 define void @test17_select(i32 %x, i32 %y) {
 ; CHECK-LABEL: @test17_select(
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i32 [[X:%.*]], 3
 ; CHECK-NEXT:    [[SWITCH:%.*]] = icmp ult i32 [[Y:%.*]], 2
 ; CHECK-NEXT:    [[OR_COND775:%.*]] = select i1 [[CMP]], i1 true, i1 [[SWITCH]]
-; CHECK-NEXT:    br i1 [[OR_COND775]], label [[LOR_LHS_FALSE8:%.*]], label [[RETURN:%.*]]
+; CHECK-NEXT:    br i1 [[OR_COND775]], label [[LOR_LHS_FALSE8:%.*]], label [[COMMON_RET:%.*]]
 ; CHECK:       lor.lhs.false8:
 ; CHECK-NEXT:    tail call void @foo1()
-; CHECK-NEXT:    ret void
-; CHECK:       return:
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   %cmp = icmp ult i32 %x, 3
   %switch = icmp ult i32 %y, 2
   %or.cond775 = select i1 %cmp, i1 true, i1 %switch
   br i1 %or.cond775, label %lor.lhs.false8, label %return
 
 lor.lhs.false8:

 
 if.end29:                                         ; preds = %entry
   ret void
 }
 
 ; Form a switch when and'ing a negated power of two
 define void @test19(i32 %arg) {
 ; CHECK-LABEL: @test19(
-; CHECK-NEXT:    switch i32 [[ARG:%.*]], label [[ELSE:%.*]] [
+; CHECK-NEXT:    switch i32 [[ARG:%.*]], label [[COMMON_RET:%.*]] [
 ; CHECK-NEXT:    i32 32, label [[IF:%.*]]
 ; CHECK-NEXT:    i32 13, label [[IF]]
 ; CHECK-NEXT:    i32 12, label [[IF]]
 ; CHECK-NEXT:    ]
 ; CHECK:       if:
 ; CHECK-NEXT:    call void @foo1()
-; CHECK-NEXT:    ret void
-; CHECK:       else:
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   %and = and i32 %arg, -2
   %cmp1 = icmp eq i32 %and, 12
   %cmp2 = icmp eq i32 %arg, 32
   %pred = or i1 %cmp1, %cmp2
   br i1 %pred, label %if, label %else
 
 if:
   call void @foo1()
   ret void
 
 else:
   ret void
 }
 
 define void @test19_select(i32 %arg) {
 ; CHECK-LABEL: @test19_select(
-; CHECK-NEXT:    switch i32 [[ARG:%.*]], label [[ELSE:%.*]] [
+; CHECK-NEXT:    switch i32 [[ARG:%.*]], label [[COMMON_RET:%.*]] [
 ; CHECK-NEXT:    i32 32, label [[IF:%.*]]
 ; CHECK-NEXT:    i32 13, label [[IF]]
 ; CHECK-NEXT:    i32 12, label [[IF]]
 ; CHECK-NEXT:    ]
 ; CHECK:       if:
 ; CHECK-NEXT:    call void @foo1()
-; CHECK-NEXT:    ret void
-; CHECK:       else:
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   %and = and i32 %arg, -2
   %cmp1 = icmp eq i32 %and, 12
   %cmp2 = icmp eq i32 %arg, 32
   %pred = select i1 %cmp1, i1 true, i1 %cmp2
   br i1 %pred, label %if, label %else
 
 if:
   call void @foo1()
   ret void
 
 else:
   ret void
 }
 
 ; Since %cmp1 is always false, a switch is never formed
 define void @test20(i32 %arg) {
 ; CHECK-LABEL: @test20(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 [[ARG:%.*]], -2
 ; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[AND]], 13
 ; CHECK-NEXT:    [[CMP2:%.*]] = icmp eq i32 [[ARG]], 32
 ; CHECK-NEXT:    [[PRED:%.*]] = or i1 [[CMP1]], [[CMP2]]
-; CHECK-NEXT:    br i1 [[PRED]], label [[IF:%.*]], label [[ELSE:%.*]]
+; CHECK-NEXT:    br i1 [[PRED]], label [[IF:%.*]], label [[COMMON_RET:%.*]]
 ; CHECK:       if:
 ; CHECK-NEXT:    call void @foo1()
-; CHECK-NEXT:    ret void
-; CHECK:       else:
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   %and = and i32 %arg, -2
   %cmp1 = icmp eq i32 %and, 13
   %cmp2 = icmp eq i32 %arg, 32
   %pred = or i1 %cmp1, %cmp2
   br i1 %pred, label %if, label %else
 
 if:
   call void @foo1()
   ret void
 
 else:
   ret void
 }
 
 ; Form a switch when or'ing a power of two
 define void @test21(i32 %arg) {
 ; CHECK-LABEL: @test21(
 ; CHECK-NEXT:    switch i32 [[ARG:%.*]], label [[IF:%.*]] [
-; CHECK-NEXT:    i32 32, label [[ELSE:%.*]]
-; CHECK-NEXT:    i32 13, label [[ELSE]]
-; CHECK-NEXT:    i32 12, label [[ELSE]]
+; CHECK-NEXT:    i32 32, label [[COMMON_RET:%.*]]
+; CHECK-NEXT:    i32 13, label [[COMMON_RET]]
+; CHECK-NEXT:    i32 12, label [[COMMON_RET]]
 ; CHECK-NEXT:    ]
 ; CHECK:       if:
 ; CHECK-NEXT:    call void @foo1()
-; CHECK-NEXT:    ret void
-; CHECK:       else:
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   %and = or i32 %arg, 1
   %cmp1 = icmp ne i32 %and, 13
   %cmp2 = icmp ne i32 %arg, 32
   %pred = and i1 %cmp1, %cmp2
   br i1 %pred, label %if, label %else
 
 if:
   call void @foo1()
   ret void
 
 else:
   ret void
 }
 
 ; Since %cmp1 is always false, a switch is never formed
 define void @test22(i32 %arg) {
 ; CHECK-LABEL: @test22(
 ; CHECK-NEXT:    [[AND:%.*]] = or i32 [[ARG:%.*]], 1
 ; CHECK-NEXT:    [[CMP1:%.*]] = icmp ne i32 [[AND]], 12
 ; CHECK-NEXT:    [[CMP2:%.*]] = icmp ne i32 [[ARG]], 32
 ; CHECK-NEXT:    [[PRED:%.*]] = and i1 [[CMP1]], [[CMP2]]
-; CHECK-NEXT:    br i1 [[PRED]], label [[IF:%.*]], label [[ELSE:%.*]]
+; CHECK-NEXT:    br i1 [[PRED]], label [[IF:%.*]], label [[COMMON_RET:%.*]]
 ; CHECK:       if:
 ; CHECK-NEXT:    call void @foo1()
-; CHECK-NEXT:    ret void
-; CHECK:       else:
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   %and = or i32 %arg, 1
   %cmp1 = icmp ne i32 %and, 12
   %cmp2 = icmp ne i32 %arg, 32
   %pred = and i1 %cmp1, %cmp2
   br i1 %pred, label %if, label %else
 
 if:
   call void @foo1()
   ret void
 
 else:
   ret void
 }

llvm/test/Transforms/SimplifyCFG/switch_switch_fold.ll

 ; CHECK-NEXT:    switch i32 [[V:%.*]], label [[INFLOOP:%.*]] [
 ; CHECK-NEXT:    i32 4, label [[A:%.*]]
 ; CHECK-NEXT:    i32 17, label [[B:%.*]]
 ; CHECK-NEXT:    i32 18, label [[B]]
 ; CHECK-NEXT:    i32 42, label [[D:%.*]]
 ; CHECK-NEXT:    ]
 ; CHECK:       A:
 ; CHECK-NEXT:    call void @foo1()
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       B:
 ; CHECK-NEXT:    call void @foo2()
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       D:
 ; CHECK-NEXT:    call void @foo4()
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ; CHECK:       infloop:
 ; CHECK-NEXT:    br label [[INFLOOP]]
 ;
   switch i32 %V, label %F [
   i32 4, label %T
   i32 17, label %T
   i32 5, label %T

llvm/test/Transforms/SimplifyCFG/switch_thread.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S | FileCheck %s
 
 ; Test that we can thread a simple known condition through switch statements.
 
 declare void @foo1()
 
 declare void @foo2()
 
 declare void @DEAD()
 
 define void @test1(i32 %V) {
 ; CHECK-LABEL: @test1(
 ; CHECK-NEXT:    switch i32 [[V:%.*]], label [[A:%.*]] [
 ; CHECK-NEXT:    i32 4, label [[T:%.*]]
-; CHECK-NEXT:    i32 17, label [[DONE:%.*]]
+; CHECK-NEXT:    i32 17, label [[COMMON_RET:%.*]]
 ; CHECK-NEXT:    ]
 ; CHECK:       T:
 ; CHECK-NEXT:    call void @foo1()
 ; CHECK-NEXT:    call void @foo2()
-; CHECK-NEXT:    br label [[DONE]]
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       A:
 ; CHECK-NEXT:    call void @foo1()
-; CHECK-NEXT:    br label [[DONE]]
-; CHECK:       Done:
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   switch i32 %V, label %A [
   i32 4, label %T
   i32 17, label %Done
   i32 1234, label %A
   ]
 ;; V == 4 if we get here.

 
 }
 
 define void @test2(i32 %V) {
 ; CHECK-LABEL: @test2(
 ; CHECK-NEXT:    switch i32 [[V:%.*]], label [[A:%.*]] [
 ; CHECK-NEXT:    i32 4, label [[T:%.*]]
 ; CHECK-NEXT:    i32 17, label [[D:%.*]]
-; CHECK-NEXT:    i32 1234, label [[E:%.*]]
+; CHECK-NEXT:    i32 1234, label [[COMMON_RET:%.*]]
 ; CHECK-NEXT:    ]
 ; CHECK:       A:
 ; CHECK-NEXT:    call void @foo1()
 ; CHECK-NEXT:    [[COND:%.*]] = icmp eq i32 [[V]], 42
-; CHECK-NEXT:    br i1 [[COND]], label [[D]], label [[E]]
+; CHECK-NEXT:    br i1 [[COND]], label [[D]], label [[COMMON_RET]]
 ; CHECK:       T:
 ; CHECK-NEXT:    call void @foo1()
 ; CHECK-NEXT:    call void @foo1()
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET]]
 ; CHECK:       D:
 ; CHECK-NEXT:    call void @foo1()
-; CHECK-NEXT:    ret void
-; CHECK:       E:
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   switch i32 %V, label %A [
   i32 4, label %T
   i32 17, label %D
   i32 1234, label %E
   ]
 ;; V != 4, 17, 1234 here.

llvm/test/Transforms/SimplifyCFG/unprofitable-pr.ll

 ; CHECK:       false1:
 ; CHECK-NEXT:    store volatile i64 1, i64* [[PTR:%.*]], align 4
 ; CHECK-NEXT:    [[PTRINT:%.*]] = ptrtoint i64* [[PTR]] to i64
 ; CHECK-NEXT:    [[MASKEDPTR:%.*]] = and i64 [[PTRINT]], 7
 ; CHECK-NEXT:    [[MASKCOND:%.*]] = icmp eq i64 [[MASKEDPTR]], 0
 ; CHECK-NEXT:    tail call void @llvm.assume(i1 [[MASKCOND]])
 ; CHECK-NEXT:    store volatile i64 0, i64* [[PTR]], align 8
 ; CHECK-NEXT:    store volatile i64 3, i64* [[PTR]], align 8
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       true2.critedge:
 ; CHECK-NEXT:    [[PTRINT_C:%.*]] = ptrtoint i64* [[PTR]] to i64
 ; CHECK-NEXT:    [[MASKEDPTR_C:%.*]] = and i64 [[PTRINT_C]], 7
 ; CHECK-NEXT:    [[MASKCOND_C:%.*]] = icmp eq i64 [[MASKEDPTR_C]], 0
 ; CHECK-NEXT:    tail call void @llvm.assume(i1 [[MASKCOND_C]])
 ; CHECK-NEXT:    store volatile i64 0, i64* [[PTR]], align 8
 ; CHECK-NEXT:    store volatile i64 2, i64* [[PTR]], align 8
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   br i1 %c, label %true1, label %false1
 
 true1:                                            ; preds = %false1, %0
   %ptrint = ptrtoint i64* %ptr to i64
   %maskedptr = and i64 %ptrint, 7
   %maskcond = icmp eq i64 %maskedptr, 0

 ; CHECK-NEXT:    tail call void @llvm.assume(i1 [[MASKCOND]])
 ; CHECK-NEXT:    store volatile i64 0, i64* [[PTR]], align 8
 ; CHECK-NEXT:    store volatile i64 -1, i64* [[PTR]], align 8
 ; CHECK-NEXT:    store volatile i64 -1, i64* [[PTR]], align 8
 ; CHECK-NEXT:    store volatile i64 -1, i64* [[PTR]], align 8
 ; CHECK-NEXT:    store volatile i64 -1, i64* [[PTR]], align 8
 ; CHECK-NEXT:    store volatile i64 -1, i64* [[PTR]], align 8
 ; CHECK-NEXT:    store volatile i64 3, i64* [[PTR]], align 8
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       true2.critedge:
 ; CHECK-NEXT:    [[PTRINT_C:%.*]] = ptrtoint i64* [[PTR]] to i64
 ; CHECK-NEXT:    [[MASKEDPTR_C:%.*]] = and i64 [[PTRINT_C]], 7
 ; CHECK-NEXT:    [[MASKCOND_C:%.*]] = icmp eq i64 [[MASKEDPTR_C]], 0
 ; CHECK-NEXT:    tail call void @llvm.assume(i1 [[MASKCOND_C]])
 ; CHECK-NEXT:    store volatile i64 0, i64* [[PTR]], align 8
 ; CHECK-NEXT:    store volatile i64 -1, i64* [[PTR]], align 8
 ; CHECK-NEXT:    store volatile i64 -1, i64* [[PTR]], align 8
 ; CHECK-NEXT:    store volatile i64 -1, i64* [[PTR]], align 8
 ; CHECK-NEXT:    store volatile i64 -1, i64* [[PTR]], align 8
 ; CHECK-NEXT:    store volatile i64 -1, i64* [[PTR]], align 8
 ; CHECK-NEXT:    store volatile i64 2, i64* [[PTR]], align 8
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   br i1 %c, label %true1, label %false1
 
 true1:                                            ; preds = %false1, %0
   %ptrint = ptrtoint i64* %ptr to i64
   %maskedptr = and i64 %ptrint, 7
   %maskcond = icmp eq i64 %maskedptr, 0

 ; CHECK-NEXT:    store volatile i64 -1, i64* [[PTR]], align 8
 ; CHECK-NEXT:    store volatile i64 -1, i64* [[PTR]], align 8
 ; CHECK-NEXT:    br i1 [[C]], label [[TRUE2:%.*]], label [[FALSE2:%.*]]
 ; CHECK:       false1:
 ; CHECK-NEXT:    store volatile i64 1, i64* [[PTR]], align 4
 ; CHECK-NEXT:    br label [[TRUE1]]
 ; CHECK:       true2:
 ; CHECK-NEXT:    store volatile i64 2, i64* [[PTR]], align 8
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       false2:
 ; CHECK-NEXT:    store volatile i64 3, i64* [[PTR]], align 8
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   br i1 %c, label %true1, label %false1
 
 true1:                                            ; preds = %false1, %0
   %ptrint = ptrtoint i64* %ptr to i64
   %maskedptr = and i64 %ptrint, 7
   %maskcond = icmp eq i64 %maskedptr, 0

 ; CHECK-NEXT:    tail call void @llvm.assume(i1 [[P]])
 ; CHECK-NEXT:    store volatile i64 0, i64* [[PTR]], align 8
 ; CHECK-NEXT:    store volatile i64 -1, i64* [[PTR]], align 8
 ; CHECK-NEXT:    store volatile i64 -1, i64* [[PTR]], align 8
 ; CHECK-NEXT:    store volatile i64 -1, i64* [[PTR]], align 8
 ; CHECK-NEXT:    store volatile i64 -1, i64* [[PTR]], align 8
 ; CHECK-NEXT:    store volatile i64 -1, i64* [[PTR]], align 8
 ; CHECK-NEXT:    store volatile i64 3, i64* [[PTR]], align 8
-; CHECK-NEXT:    ret void
+; CHECK-NEXT:    br label [[COMMON_RET:%.*]]
 ; CHECK:       true2.critedge:
 ; CHECK-NEXT:    [[VTABLEI8_C:%.*]] = bitcast [3 x i8*]* [[VTABLE]] to i8*
 ; CHECK-NEXT:    [[P_C:%.*]] = call i1 @llvm.type.test(i8* [[VTABLEI8_C]], metadata !"foo")
 ; CHECK-NEXT:    tail call void @llvm.assume(i1 [[P_C]])
 ; CHECK-NEXT:    store volatile i64 0, i64* [[PTR]], align 8
 ; CHECK-NEXT:    store volatile i64 -1, i64* [[PTR]], align 8
 ; CHECK-NEXT:    store volatile i64 -1, i64* [[PTR]], align 8
 ; CHECK-NEXT:    store volatile i64 -1, i64* [[PTR]], align 8
 ; CHECK-NEXT:    store volatile i64 -1, i64* [[PTR]], align 8
 ; CHECK-NEXT:    store volatile i64 -1, i64* [[PTR]], align 8
 ; CHECK-NEXT:    store volatile i64 2, i64* [[PTR]], align 8
+; CHECK-NEXT:    br label [[COMMON_RET]]
+; CHECK:       common.ret:
 ; CHECK-NEXT:    ret void
 ;
   br i1 %c, label %true1, label %false1
 
 true1:                                            ; preds = %false1, %0
   %vtablei8 = bitcast [3 x i8*]* %vtable to i8*
   %p = call i1 @llvm.type.test(i8* %vtablei8, metadata !"foo")
   tail call void @llvm.assume(i1 %p)