[DAG] Allow isNullOrNullSplat to see truncated zeroes

[dmgreen]

Summary

This sets the AllowTruncation flag on isConstOrConstSplat in isNullOrNullSplat, allowing it to see truncated constant zeroes on architectures such as AArch64, where only a i32.i64 are legal. As a truncation of 0 is always 0, this should always be valid, allowing some extra folding to happen including some of the cases from D103755.

Whilst I'm here also add a call to peekThroughBitcasts as bitcast Zero is still Zero, and removed a related TODO comment from isOneOrOneSplat as the bitcast of 1 isn't always still 1.

[RKSimon]

Whilst I'm here also add a call to peekThroughBitcasts as bitcast Zero is still Zero, and removed a related TODO comment from isOneOrOneSplat as the bitcast of 1 isn't always still 1.

Is this necessary for any of the test changes? I just wonder whether we should add this separately.

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

9605

/*AllowTruncation*/true ?

[dmgreen]

In D103756#2800940, @RKSimon wrote:

Whilst I'm here also add a call to peekThroughBitcasts as bitcast Zero is still Zero, and removed a related TODO comment from isOneOrOneSplat as the bitcast of 1 isn't always still 1.

Is this necessary for any of the test changes? I just wonder whether we should add this separately.

Sure, I can remove it from here, it won't effect any of the test cases. I believe we will already turn bitcast(buildvector(0's)) to buildvector(0's) already.

[RKSimon]

LGTM - cheers

Whilst I'm here also add a call to peekThroughBitcasts as bitcast Zero is still Zero, and removed a related TODO comment from isOneOrOneSplat as the bitcast of 1 isn't always still 1.

You need to update the patch summary.

[craig.topper]

RISCV changes LGTM

[dmgreen]

Thanks Folks.

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

if (CN && (UndefElements.none() || AllowUndefs))
       return CN;
   }
 
   return nullptr;
 }
 
 bool llvm::isNullOrNullSplat(SDValue N, bool AllowUndefs) {
   // TODO: may want to use peekThroughBitcast() here.
-  ConstantSDNode *C = isConstOrConstSplat(N, AllowUndefs);
+  ConstantSDNode *C =
+      isConstOrConstSplat(N, AllowUndefs, /*AllowTruncation=*/true);
   return C && C->isNullValue();
 }
 
 bool llvm::isOneOrOneSplat(SDValue N, bool AllowUndefs) {
   // TODO: may want to use peekThroughBitcast() here.
   unsigned BitWidth = N.getScalarValueSizeInBits();
   ConstantSDNode *C = isConstOrConstSplat(N, AllowUndefs);
   return C && C->isOne() && C->getValueSizeInBits(0) == BitWidth;

llvm/test/CodeGen/AArch64/neon-shift-neg.ll

entry:
   %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> poison, <4 x i32> <i32 undef, i32 0, i32 0, i32 0>
   %shr = ashr <4 x i32> %a, %splat.splat
   ret <4 x i32> %shr
 }
 
 define <8 x i16> @shr16x8(<8 x i16> %a, i16 %b) {
 ; CHECK-LABEL: shr16x8:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    neg w8, w0
-; CHECK-NEXT:    dup v1.8h, w8
-; CHECK-NEXT:    neg v1.8h, v1.8h
+; CHECK-NEXT:    dup v1.8h, w0
 ; CHECK-NEXT:    sshl v0.8h, v0.8h, v1.8h
 ; CHECK-NEXT:    ret
 entry:
   %sub = sub i16 0, %b
   %0 = insertelement <8 x i16> undef, i16 %sub, i32 0
   %sh_prom = shufflevector <8 x i16> %0, <8 x i16> undef, <8 x i32> zeroinitializer
   %shr = ashr <8 x i16> %a, %sh_prom
   ret <8 x i16> %shr
 }
 
 define <16 x i8> @shr8x16(<16 x i8> %a, i8 %b) {
 ; CHECK-LABEL: shr8x16:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    neg w8, w0
-; CHECK-NEXT:    dup v1.16b, w8
-; CHECK-NEXT:    neg v1.16b, v1.16b
+; CHECK-NEXT:    dup v1.16b, w0
 ; CHECK-NEXT:    sshl v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    ret
 entry:
   %sub = sub i8 0, %b
   %0 = insertelement <16 x i8> undef, i8 %sub, i32 0
   %sh_prom = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> zeroinitializer
   %shr = ashr <16 x i8> %a, %sh_prom
   ret <16 x i8> %shr
entry:
   %splat.splat = shufflevector <2 x i32> %splat.splatinsert, <2 x i32> poison, <2 x i32> zeroinitializer
   %shr = ashr <2 x i32> %a, %splat.splat
   ret <2 x i32> %shr
 }
 
 define <4 x i16> @shr16x4(<4 x i16> %a, i16 %b) {
 ; CHECK-LABEL: shr16x4:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    neg w8, w0
-; CHECK-NEXT:    dup v1.4h, w8
-; CHECK-NEXT:    neg v1.4h, v1.4h
+; CHECK-NEXT:    dup v1.4h, w0
 ; CHECK-NEXT:    sshl v0.4h, v0.4h, v1.4h
 ; CHECK-NEXT:    ret
 entry:
   %sub = sub i16 0, %b
   %0 = insertelement <4 x i16> undef, i16 %sub, i32 0
   %sh_prom = shufflevector <4 x i16> %0, <4 x i16> undef, <4 x i32> zeroinitializer
   %shr = ashr <4 x i16> %a, %sh_prom
   ret <4 x i16> %shr
 }
 
 define <8 x i8> @shr8x8(<8 x i8> %a, i8 %b) {
 ; CHECK-LABEL: shr8x8:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    neg w8, w0
-; CHECK-NEXT:    dup v1.8b, w8
-; CHECK-NEXT:    neg v1.8b, v1.8b
+; CHECK-NEXT:    dup v1.8b, w0
 ; CHECK-NEXT:    sshl v0.8b, v0.8b, v1.8b
 ; CHECK-NEXT:    ret
 entry:
   %sub = sub i8 0, %b
   %0 = insertelement <8 x i8> undef, i8 %sub, i32 0
   %sh_prom = shufflevector <8 x i8> %0, <8 x i8> undef, <8 x i32> zeroinitializer
   %shr = ashr <8 x i8> %a, %sh_prom
   ret <8 x i8> %shr

llvm/test/CodeGen/AArch64/vecreduce-bool.ll

; CHECK-NEXT:    ret
   %y = call i1 @llvm.vector.reduce.and.v16i1(<16 x i1> %x)
   %z = select i1 %y, i32 %a1, i32 %a2
   ret i32 %z
 }
 
 define i32 @reduce_and_v32(<32 x i8> %a0, i32 %a1, i32 %a2) nounwind {
 ; CHECK-LABEL: reduce_and_v32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    cmlt v1.16b, v1.16b, #0
-; CHECK-NEXT:    cmlt v0.16b, v0.16b, #0
 ; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    cmlt v0.16b, v0.16b, #0
 ; CHECK-NEXT:    uminv b0, v0.16b
 ; CHECK-NEXT:    fmov w8, s0
 ; CHECK-NEXT:    tst w8, #0x1
 ; CHECK-NEXT:    csel w0, w0, w1, ne
 ; CHECK-NEXT:    ret
   %x = icmp slt <32 x i8> %a0, zeroinitializer
   %y = call i1 @llvm.vector.reduce.and.v32i1(<32 x i1> %x)
   %z = select i1 %y, i32 %a1, i32 %a2
; CHECK-NEXT:    ret
   %y = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> %x)
   %z = select i1 %y, i32 %a1, i32 %a2
   ret i32 %z
 }
 
 define i32 @reduce_or_v32(<32 x i8> %a0, i32 %a1, i32 %a2) nounwind {
 ; CHECK-LABEL: reduce_or_v32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    cmlt v1.16b, v1.16b, #0
-; CHECK-NEXT:    cmlt v0.16b, v0.16b, #0
 ; CHECK-NEXT:    orr v0.16b, v0.16b, v1.16b
+; CHECK-NEXT:    cmlt v0.16b, v0.16b, #0
 ; CHECK-NEXT:    umaxv b0, v0.16b
 ; CHECK-NEXT:    fmov w8, s0
 ; CHECK-NEXT:    tst w8, #0x1
 ; CHECK-NEXT:    csel w0, w0, w1, ne
 ; CHECK-NEXT:    ret
   %x = icmp slt <32 x i8> %a0, zeroinitializer
   %y = call i1 @llvm.vector.reduce.or.v32i1(<32 x i1> %x)
   %z = select i1 %y, i32 %a1, i32 %a2
   ret i32 %z
 }

llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll

 }
 
 define <vscale x 1 x i8> @vdiv_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv1i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
-; CHECK-NEXT:    vrsub.vi v26, v8, 0
-; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsub.vv v25, v25, v8
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
 ; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i8> %va, %splat
   ret <vscale x 1 x i8> %vc

 }
 
 define <vscale x 2 x i8> @vdiv_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv2i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
-; CHECK-NEXT:    vrsub.vi v26, v8, 0
-; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsub.vv v25, v25, v8
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
 ; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i8> %va, %splat
   ret <vscale x 2 x i8> %vc

 }
 
 define <vscale x 4 x i8> @vdiv_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv4i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
-; CHECK-NEXT:    vrsub.vi v26, v8, 0
-; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsub.vv v25, v25, v8
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
 ; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i8> %va, %splat
   ret <vscale x 4 x i8> %vc

 }
 
 define <vscale x 8 x i8> @vdiv_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv8i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
-; CHECK-NEXT:    vrsub.vi v26, v8, 0
-; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsub.vv v25, v25, v8
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
 ; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i8> %vc

 }
 
 define <vscale x 16 x i8> @vdiv_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv16i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v26, v8, a0
-; CHECK-NEXT:    vrsub.vi v28, v8, 0
-; CHECK-NEXT:    vadd.vv v26, v26, v28
+; CHECK-NEXT:    vsub.vv v26, v26, v8
 ; CHECK-NEXT:    vsra.vi v26, v26, 2
 ; CHECK-NEXT:    vsrl.vi v28, v26, 7
 ; CHECK-NEXT:    vadd.vv v8, v26, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %vc = sdiv <vscale x 16 x i8> %va, %splat
   ret <vscale x 16 x i8> %vc

 }
 
 define <vscale x 32 x i8> @vdiv_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv32i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
 ; CHECK-NEXT:    vmulh.vx v28, v8, a0
-; CHECK-NEXT:    vrsub.vi v8, v8, 0
-; CHECK-NEXT:    vadd.vv v28, v28, v8
+; CHECK-NEXT:    vsub.vv v28, v28, v8
 ; CHECK-NEXT:    vsra.vi v28, v28, 2
 ; CHECK-NEXT:    vsrl.vi v8, v28, 7
 ; CHECK-NEXT:    vadd.vv v8, v28, v8
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
   %vc = sdiv <vscale x 32 x i8> %va, %splat
   ret <vscale x 32 x i8> %vc

 }
 
 define <vscale x 64 x i8> @vdiv_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv64i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
 ; CHECK-NEXT:    vmulh.vx v16, v8, a0
-; CHECK-NEXT:    vrsub.vi v8, v8, 0
-; CHECK-NEXT:    vadd.vv v8, v16, v8
+; CHECK-NEXT:    vsub.vv v8, v16, v8
 ; CHECK-NEXT:    vsra.vi v8, v8, 2
 ; CHECK-NEXT:    vsrl.vi v16, v8, 7
 ; CHECK-NEXT:    vadd.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
   %vc = sdiv <vscale x 64 x i8> %va, %splat
   ret <vscale x 64 x i8> %vc

llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll

 }
 
 define <vscale x 1 x i8> @vdiv_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv1i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
-; CHECK-NEXT:    vrsub.vi v26, v8, 0
-; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsub.vv v25, v25, v8
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
 ; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i8> %va, %splat
   ret <vscale x 1 x i8> %vc

 }
 
 define <vscale x 2 x i8> @vdiv_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv2i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
-; CHECK-NEXT:    vrsub.vi v26, v8, 0
-; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsub.vv v25, v25, v8
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
 ; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i8> %va, %splat
   ret <vscale x 2 x i8> %vc

 }
 
 define <vscale x 4 x i8> @vdiv_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv4i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
-; CHECK-NEXT:    vrsub.vi v26, v8, 0
-; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsub.vv v25, v25, v8
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
 ; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i8> %va, %splat
   ret <vscale x 4 x i8> %vc

 }
 
 define <vscale x 8 x i8> @vdiv_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv8i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
-; CHECK-NEXT:    vrsub.vi v26, v8, 0
-; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsub.vv v25, v25, v8
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
 ; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i8> %va, %splat
   ret <vscale x 8 x i8> %vc

 }
 
 define <vscale x 16 x i8> @vdiv_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv16i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v26, v8, a0
-; CHECK-NEXT:    vrsub.vi v28, v8, 0
-; CHECK-NEXT:    vadd.vv v26, v26, v28
+; CHECK-NEXT:    vsub.vv v26, v26, v8
 ; CHECK-NEXT:    vsra.vi v26, v26, 2
 ; CHECK-NEXT:    vsrl.vi v28, v26, 7
 ; CHECK-NEXT:    vadd.vv v8, v26, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 16 x i8> %head, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %vc = sdiv <vscale x 16 x i8> %va, %splat
   ret <vscale x 16 x i8> %vc

 }
 
 define <vscale x 32 x i8> @vdiv_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv32i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
 ; CHECK-NEXT:    vmulh.vx v28, v8, a0
-; CHECK-NEXT:    vrsub.vi v8, v8, 0
-; CHECK-NEXT:    vadd.vv v28, v28, v8
+; CHECK-NEXT:    vsub.vv v28, v28, v8
 ; CHECK-NEXT:    vsra.vi v28, v28, 2
 ; CHECK-NEXT:    vsrl.vi v8, v28, 7
 ; CHECK-NEXT:    vadd.vv v8, v28, v8
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 32 x i8> %head, <vscale x 32 x i8> undef, <vscale x 32 x i32> zeroinitializer
   %vc = sdiv <vscale x 32 x i8> %va, %splat
   ret <vscale x 32 x i8> %vc

 }
 
 define <vscale x 64 x i8> @vdiv_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv64i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
 ; CHECK-NEXT:    vmulh.vx v16, v8, a0
-; CHECK-NEXT:    vrsub.vi v8, v8, 0
-; CHECK-NEXT:    vadd.vv v8, v16, v8
+; CHECK-NEXT:    vsub.vv v8, v16, v8
 ; CHECK-NEXT:    vsra.vi v8, v8, 2
 ; CHECK-NEXT:    vsrl.vi v16, v8, 7
 ; CHECK-NEXT:    vadd.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0
   %splat = shufflevector <vscale x 64 x i8> %head, <vscale x 64 x i8> undef, <vscale x 64 x i32> zeroinitializer
   %vc = sdiv <vscale x 64 x i8> %va, %splat
   ret <vscale x 64 x i8> %vc

 
 define <vscale x 1 x i32> @vdiv_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv1i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 449390
 ; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
-; CHECK-NEXT:    vrsub.vi v26, v8, 0
-; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsub.vv v25, v25, v8
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 31
 ; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i32> %va, %splat
   ret <vscale x 1 x i32> %vc

 
 define <vscale x 2 x i32> @vdiv_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv2i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 449390
 ; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
-; CHECK-NEXT:    vrsub.vi v26, v8, 0
-; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsub.vv v25, v25, v8
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 31
 ; CHECK-NEXT:    vadd.vv v8, v25, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i32> %va, %splat
   ret <vscale x 2 x i32> %vc

 
 define <vscale x 4 x i32> @vdiv_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv4i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 449390
 ; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v26, v8, a0
-; CHECK-NEXT:    vrsub.vi v28, v8, 0
-; CHECK-NEXT:    vadd.vv v26, v26, v28
+; CHECK-NEXT:    vsub.vv v26, v26, v8
 ; CHECK-NEXT:    vsra.vi v26, v26, 2
 ; CHECK-NEXT:    vsrl.vi v28, v26, 31
 ; CHECK-NEXT:    vadd.vv v8, v26, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i32> %va, %splat
   ret <vscale x 4 x i32> %vc

 
 define <vscale x 8 x i32> @vdiv_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv8i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 449390
 ; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
 ; CHECK-NEXT:    vmulh.vx v28, v8, a0
-; CHECK-NEXT:    vrsub.vi v8, v8, 0
-; CHECK-NEXT:    vadd.vv v28, v28, v8
+; CHECK-NEXT:    vsub.vv v28, v28, v8
 ; CHECK-NEXT:    vsra.vi v28, v28, 2
 ; CHECK-NEXT:    vsrl.vi v8, v28, 31
 ; CHECK-NEXT:    vadd.vv v8, v28, v8
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i32> %va, %splat
   ret <vscale x 8 x i32> %vc

 
 define <vscale x 16 x i32> @vdiv_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
 ; CHECK-LABEL: vdiv_vi_nxv16i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 449390
 ; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
 ; CHECK-NEXT:    vmulh.vx v16, v8, a0
-; CHECK-NEXT:    vrsub.vi v8, v8, 0
-; CHECK-NEXT:    vadd.vv v8, v16, v8
+; CHECK-NEXT:    vsub.vv v8, v16, v8
 ; CHECK-NEXT:    vsra.vi v8, v8, 2
 ; CHECK-NEXT:    vsrl.vi v16, v8, 31
 ; CHECK-NEXT:    vadd.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = sdiv <vscale x 16 x i32> %va, %splat
   ret <vscale x 16 x i32> %vc

llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll

 }
 
 define <vscale x 1 x i8> @vrem_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv1i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
-; CHECK-NEXT:    vrsub.vi v26, v8, 0
-; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsub.vv v25, v25, v8
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0

 }
 
 define <vscale x 2 x i8> @vrem_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv2i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
-; CHECK-NEXT:    vrsub.vi v26, v8, 0
-; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsub.vv v25, v25, v8
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0

 }
 
 define <vscale x 4 x i8> @vrem_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv4i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
-; CHECK-NEXT:    vrsub.vi v26, v8, 0
-; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsub.vv v25, v25, v8
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0

 }
 
 define <vscale x 8 x i8> @vrem_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv8i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
-; CHECK-NEXT:    vrsub.vi v26, v8, 0
-; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsub.vv v25, v25, v8
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0

 }
 
 define <vscale x 16 x i8> @vrem_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv16i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v26, v8, a0
-; CHECK-NEXT:    vrsub.vi v28, v8, 0
-; CHECK-NEXT:    vadd.vv v26, v26, v28
+; CHECK-NEXT:    vsub.vv v26, v26, v8
 ; CHECK-NEXT:    vsra.vi v26, v26, 2
 ; CHECK-NEXT:    vsrl.vi v28, v26, 7
 ; CHECK-NEXT:    vadd.vv v26, v26, v28
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v26, v26, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0

 }
 
 define <vscale x 32 x i8> @vrem_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv32i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
 ; CHECK-NEXT:    vmulh.vx v28, v8, a0
-; CHECK-NEXT:    vrsub.vi v12, v8, 0
-; CHECK-NEXT:    vadd.vv v28, v28, v12
+; CHECK-NEXT:    vsub.vv v28, v28, v8
 ; CHECK-NEXT:    vsra.vi v28, v28, 2
 ; CHECK-NEXT:    vsrl.vi v12, v28, 7
 ; CHECK-NEXT:    vadd.vv v28, v28, v12
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v28, v28, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0

 }
 
 define <vscale x 64 x i8> @vrem_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv64i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
 ; CHECK-NEXT:    vmulh.vx v16, v8, a0
-; CHECK-NEXT:    vrsub.vi v24, v8, 0
-; CHECK-NEXT:    vadd.vv v16, v16, v24
+; CHECK-NEXT:    vsub.vv v16, v16, v8
 ; CHECK-NEXT:    vsra.vi v16, v16, 2
 ; CHECK-NEXT:    vsrl.vi v24, v16, 7
 ; CHECK-NEXT:    vadd.vv v16, v16, v24
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v16, v16, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0

llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv64.ll

 }
 
 define <vscale x 1 x i8> @vrem_vi_nxv1i8_0(<vscale x 1 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv1i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
-; CHECK-NEXT:    vrsub.vi v26, v8, 0
-; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsub.vv v25, v25, v8
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i8> undef, i8 -7, i32 0

 }
 
 define <vscale x 2 x i8> @vrem_vi_nxv2i8_0(<vscale x 2 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv2i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
-; CHECK-NEXT:    vrsub.vi v26, v8, 0
-; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsub.vv v25, v25, v8
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i8> undef, i8 -7, i32 0

 }
 
 define <vscale x 4 x i8> @vrem_vi_nxv4i8_0(<vscale x 4 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv4i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
-; CHECK-NEXT:    vrsub.vi v26, v8, 0
-; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsub.vv v25, v25, v8
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i8> undef, i8 -7, i32 0

 }
 
 define <vscale x 8 x i8> @vrem_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv8i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
-; CHECK-NEXT:    vrsub.vi v26, v8, 0
-; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsub.vv v25, v25, v8
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 7
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i8> undef, i8 -7, i32 0

 }
 
 define <vscale x 16 x i8> @vrem_vi_nxv16i8_0(<vscale x 16 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv16i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v26, v8, a0
-; CHECK-NEXT:    vrsub.vi v28, v8, 0
-; CHECK-NEXT:    vadd.vv v26, v26, v28
+; CHECK-NEXT:    vsub.vv v26, v26, v8
 ; CHECK-NEXT:    vsra.vi v26, v26, 2
 ; CHECK-NEXT:    vsrl.vi v28, v26, 7
 ; CHECK-NEXT:    vadd.vv v26, v26, v28
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v26, v26, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i8> undef, i8 -7, i32 0

 }
 
 define <vscale x 32 x i8> @vrem_vi_nxv32i8_0(<vscale x 32 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv32i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m4,ta,mu
 ; CHECK-NEXT:    vmulh.vx v28, v8, a0
-; CHECK-NEXT:    vrsub.vi v12, v8, 0
-; CHECK-NEXT:    vadd.vv v28, v28, v12
+; CHECK-NEXT:    vsub.vv v28, v28, v8
 ; CHECK-NEXT:    vsra.vi v28, v28, 2
 ; CHECK-NEXT:    vsrl.vi v12, v28, 7
 ; CHECK-NEXT:    vadd.vv v28, v28, v12
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v28, v28, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i8> undef, i8 -7, i32 0

 }
 
 define <vscale x 64 x i8> @vrem_vi_nxv64i8_0(<vscale x 64 x i8> %va) {
 ; CHECK-LABEL: vrem_vi_nxv64i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 109
 ; CHECK-NEXT:    vsetvli a1, zero, e8,m8,ta,mu
 ; CHECK-NEXT:    vmulh.vx v16, v8, a0
-; CHECK-NEXT:    vrsub.vi v24, v8, 0
-; CHECK-NEXT:    vadd.vv v16, v16, v24
+; CHECK-NEXT:    vsub.vv v16, v16, v8
 ; CHECK-NEXT:    vsra.vi v16, v16, 2
 ; CHECK-NEXT:    vsrl.vi v24, v16, 7
 ; CHECK-NEXT:    vadd.vv v16, v16, v24
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v16, v16, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 64 x i8> undef, i8 -7, i32 0

 
 define <vscale x 1 x i32> @vrem_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
 ; CHECK-LABEL: vrem_vi_nxv1i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 449390
 ; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
-; CHECK-NEXT:    vrsub.vi v26, v8, 0
-; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsub.vv v25, v25, v8
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 31
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0

 
 define <vscale x 2 x i32> @vrem_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
 ; CHECK-LABEL: vrem_vi_nxv2i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 449390
 ; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmulh.vx v25, v8, a0
-; CHECK-NEXT:    vrsub.vi v26, v8, 0
-; CHECK-NEXT:    vadd.vv v25, v25, v26
+; CHECK-NEXT:    vsub.vv v25, v25, v8
 ; CHECK-NEXT:    vsra.vi v25, v25, 2
 ; CHECK-NEXT:    vsrl.vi v26, v25, 31
 ; CHECK-NEXT:    vadd.vv v25, v25, v26
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v25, v25, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v25
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0

 
 define <vscale x 4 x i32> @vrem_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
 ; CHECK-LABEL: vrem_vi_nxv4i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 449390
 ; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vmulh.vx v26, v8, a0
-; CHECK-NEXT:    vrsub.vi v28, v8, 0
-; CHECK-NEXT:    vadd.vv v26, v26, v28
+; CHECK-NEXT:    vsub.vv v26, v26, v8
 ; CHECK-NEXT:    vsra.vi v26, v26, 2
 ; CHECK-NEXT:    vsrl.vi v28, v26, 31
 ; CHECK-NEXT:    vadd.vv v26, v26, v28
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v26, v26, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v26
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0

 
 define <vscale x 8 x i32> @vrem_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
 ; CHECK-LABEL: vrem_vi_nxv8i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 449390
 ; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m4,ta,mu
 ; CHECK-NEXT:    vmulh.vx v28, v8, a0
-; CHECK-NEXT:    vrsub.vi v12, v8, 0
-; CHECK-NEXT:    vadd.vv v28, v28, v12
+; CHECK-NEXT:    vsub.vv v28, v28, v8
 ; CHECK-NEXT:    vsra.vi v28, v28, 2
 ; CHECK-NEXT:    vsrl.vi v12, v28, 31
 ; CHECK-NEXT:    vadd.vv v28, v28, v12
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v28, v28, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v28
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0

 
 define <vscale x 16 x i32> @vrem_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
 ; CHECK-LABEL: vrem_vi_nxv16i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 449390
 ; CHECK-NEXT:    addiw a0, a0, -1171
 ; CHECK-NEXT:    vsetvli a1, zero, e32,m8,ta,mu
 ; CHECK-NEXT:    vmulh.vx v16, v8, a0
-; CHECK-NEXT:    vrsub.vi v24, v8, 0
-; CHECK-NEXT:    vadd.vv v16, v16, v24
+; CHECK-NEXT:    vsub.vv v16, v16, v8
 ; CHECK-NEXT:    vsra.vi v16, v16, 2
 ; CHECK-NEXT:    vsrl.vi v24, v16, 31
 ; CHECK-NEXT:    vadd.vv v16, v16, v24
 ; CHECK-NEXT:    addi a0, zero, -7
 ; CHECK-NEXT:    vmul.vx v16, v16, a0
 ; CHECK-NEXT:    vsub.vv v8, v8, v16
 ; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0