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Further improve register allocation for vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv.
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Authored by craig.topper on Jun 2 2021, 1:01 PM.

Details

Summary

The first source has the same EEW as the destination, but we're
using earlyclobber which prevents them from ever being the same
register. This patch attempts to work around this.

-For unmasked .wv, add a special TIED pseudo that pretends like
the first operand and the destination must be the same register. This
disables the earlyclobber for that source. Mark the instruction
as convertible to 3 address form which will switch it to the
original untied pseudo when the TwoAddressInstructionPass decides
that keeping them tied would require an extra copy. This uses
code in RISCVInstrInfo.cpp to do the conversion to the untied
opcode.

The untie test case show that we can generate the untied version.
Not sure it was profitable to do it in this case, but they have
really simple IR.

Diff Detail

Event Timeline

craig.topper created this revision.Jun 2 2021, 1:01 PM
craig.topper requested review of this revision.Jun 2 2021, 1:01 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 2 2021, 1:01 PM
Herald added a subscriber: MaskRay. · View Herald Transcript
arcbbb added inline comments.Jun 7 2021, 8:28 PM
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
916

GPR:$vl -> AVL:$vl

craig.topper added inline comments.Jun 7 2021, 9:07 PM
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
916

Thanks!

Use AVL instead of GPR. Use VLOpFrag

arcbbb accepted this revision.Jun 8 2021, 1:29 AM

LGTM!

This revision is now accepted and ready to land.Jun 8 2021, 1:29 AM
This revision was landed with ongoing or failed builds.Jun 8 2021, 9:44 AM
This revision was automatically updated to reflect the committed changes.