[NFCI] Move DEBUG_TYPE definition below #include of headers

[mdchen]

Summary

There're several places in the code base where DEBUG_TYPE definition is defined at the top of the file or around the #includes, which could result in conflicts when you try to define a new DEBUG_TYPE in a related header file.

[ChuanqiXu]

This fix looks good.

which could result in conflicts when you try to define a new DEBUG_TYPE in a related header file.

And I am wondering the reason you want to define DEBUG_TYPE in a header file. It isn't what we used to do.

[mdchen]

In D102594#2762526, @ChuanqiXu wrote:

And I am wondering the reason you want to define DEBUG_TYPE in a header file. It isn't what we used to do.

I don't think it's true. We can find many header files under llvm/include/ have their own DEBUG_TYPE, and it works well if you carefully undefine it at the end of the file.

[ChuanqiXu]

In D102594#2762590, @mdchen wrote:

In D102594#2762526, @ChuanqiXu wrote:

And I am wondering the reason you want to define DEBUG_TYPE in a header file. It isn't what we used to do.

I don't think it's true. We can find many header files under llvm/include/ have their own DEBUG_TYPE, and it works well if you carefully undefine it at the end of the file.

Yeah, the codes shows you are right. I find definitions for DEBUG_TYPE in some headers.

[mdchen]

Did a fully scan and modified more files that have the same issue.

[tejohnson]

lgtm. this seems fine to me, but presumably we would have a compile error if there was ever a conflict in practice with one of these files?

[mdchen]

In D102594#2766167, @tejohnson wrote:

lgtm. this seems fine to me, but presumably we would have a compile error if there was ever a conflict in practice with one of these files?

In practice it conflicts with macros defined in header files; if a conflict header file defines one but doesn't undefined it(which is unusual), the compiler throws a redefinition warning; in a general case, there'll be a compile error instead. Thanks for the review!

llvm/lib/Analysis/AssumeBundleQueries.cpp

 //===- AssumeBundleQueries.cpp - tool to query assume bundles ---*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
-#define DEBUG_TYPE "assume-queries"
-
 #include "llvm/Analysis/AssumeBundleQueries.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/Analysis/AssumptionCache.h"
 #include "llvm/Analysis/ValueTracking.h"
 #include "llvm/IR/Function.h"
 #include "llvm/IR/InstIterator.h"
 #include "llvm/IR/IntrinsicInst.h"
 #include "llvm/IR/PatternMatch.h"
 #include "llvm/Support/DebugCounter.h"
 
+#define DEBUG_TYPE "assume-queries"
+
 using namespace llvm;
 using namespace llvm::PatternMatch;
 
 STATISTIC(NumAssumeQueries, "Number of Queries into an assume assume bundles");
 STATISTIC(
     NumUsefullAssumeQueries,
     "Number of Queries into an assume assume bundles that were satisfied");
 

llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp

 //===-- AArch64PBQPRegAlloc.cpp - AArch64 specific PBQP constraints -------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 // This file contains the AArch64 / Cortex-A57 specific register allocation
 // constraints for use by the PBQP register allocator.
 //
 // It is essentially a transcription of what is contained in
 // AArch64A57FPLoadBalancing, which tries to use a balanced
 // mix of odd and even D-registers when performing a critical sequence of
 // independent, non-quadword FP/ASIMD floating-point multiply-accumulates.
 //===----------------------------------------------------------------------===//
 
-#define DEBUG_TYPE "aarch64-pbqp"
-
 #include "AArch64PBQPRegAlloc.h"
 #include "AArch64.h"
 #include "AArch64RegisterInfo.h"
 #include "llvm/CodeGen/LiveIntervals.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/RegAllocPBQP.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
 
+#define DEBUG_TYPE "aarch64-pbqp"
+
 using namespace llvm;
 
 namespace {
 
 #ifndef NDEBUG
 bool isFPReg(unsigned reg) {
   return AArch64::FPR32RegClass.contains(reg) ||
          AArch64::FPR64RegClass.contains(reg) ||

llvm/lib/Target/ARC/ARCBranchFinalize.cpp

 //===- ARCBranchFinalize.cpp - ARC conditional branches ---------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This pass takes existing conditional branches and expands them into longer
 // range conditional branches.
 //===----------------------------------------------------------------------===//
 
-#define DEBUG_TYPE "arc-branch-finalize"
-
 #include "ARCInstrInfo.h"
 #include "ARCTargetMachine.h"
 #include "MCTargetDesc/ARCInfo.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
 #include "llvm/InitializePasses.h"
 #include "llvm/Support/Debug.h"
 #include <vector>
 
+#define DEBUG_TYPE "arc-branch-finalize"
+
 using namespace llvm;
 
 namespace llvm {
 
 void initializeARCBranchFinalizePass(PassRegistry &Registry);
 FunctionPass *createARCBranchFinalizePass();
 
 } // end namespace llvm

llvm/lib/Target/AVR/MCTargetDesc/AVRMCELFStreamer.cpp

 //===--------- AVRMCELFStreamer.cpp - AVR subclass of MCELFStreamer -------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file is a stub that parses a MCInst bundle and passes the
 // instructions on to the real streamer.
 //
 //===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "avrmcelfstreamer"
-
 #include "MCTargetDesc/AVRMCELFStreamer.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/MC/MCObjectWriter.h"
 
+#define DEBUG_TYPE "avrmcelfstreamer"
+
 using namespace llvm;
 
 void AVRMCELFStreamer::emitValueForModiferKind(
     const MCSymbol *Sym, unsigned SizeInBytes, SMLoc Loc,
     AVRMCExpr::VariantKind ModifierKind) {
   MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_AVR_NONE;
   if (ModifierKind == AVRMCExpr::VK_AVR_None) {
     Kind = MCSymbolRefExpr::VK_AVR_DIFF8;

llvm/lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp

 //===-- HexagonAsmParser.cpp - Parse Hexagon asm to MCInst instructions----===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
-#define DEBUG_TYPE "mcasmparser"
-
 #include "HexagonTargetStreamer.h"
 #include "MCTargetDesc/HexagonMCChecker.h"
 #include "MCTargetDesc/HexagonMCELFStreamer.h"
 #include "MCTargetDesc/HexagonMCExpr.h"
 #include "MCTargetDesc/HexagonMCInstrInfo.h"
 #include "MCTargetDesc/HexagonMCTargetDesc.h"
 #include "MCTargetDesc/HexagonShuffler.h"
 #include "TargetInfo/HexagonTargetInfo.h"

 #include <cassert>
 #include <cctype>
 #include <cstddef>
 #include <cstdint>
 #include <memory>
 #include <string>
 #include <utility>
 
+#define DEBUG_TYPE "mcasmparser"
+
 using namespace llvm;
 
 static cl::opt<bool> WarnMissingParenthesis(
     "mwarn-missing-parenthesis",
     cl::desc("Warn for missing parenthesis around predicate registers"),
     cl::init(true));
 static cl::opt<bool> ErrorMissingParenthesis(
     "merror-missing-parenthesis",

llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp

 //===- HexagonDisassembler.cpp - Disassembler for Hexagon ISA -------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
-#define DEBUG_TYPE "hexagon-disassembler"
-
 #include "MCTargetDesc/HexagonBaseInfo.h"
 #include "MCTargetDesc/HexagonMCChecker.h"
 #include "MCTargetDesc/HexagonMCInstrInfo.h"
 #include "MCTargetDesc/HexagonMCTargetDesc.h"
 #include "TargetInfo/HexagonTargetInfo.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCFixedLenDisassembler.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/Endian.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/raw_ostream.h"
 #include <cassert>
 #include <cstddef>
 #include <cstdint>
 #include <memory>
 
+#define DEBUG_TYPE "hexagon-disassembler"
+
 using namespace llvm;
 using namespace Hexagon;
 
 using DecodeStatus = MCDisassembler::DecodeStatus;
 
 namespace {
 
 /// Hexagon disassembler for all Hexagon platforms.

llvm/lib/Target/Hexagon/HexagonBranchRelaxation.cpp

 //===--- HexagonBranchRelaxation.cpp - Identify and relax long jumps ------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
-#define DEBUG_TYPE "hexagon-brelax"
-
 #include "Hexagon.h"
 #include "HexagonInstrInfo.h"
 #include "HexagonSubtarget.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/Pass.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 #include <cassert>
 #include <cstdint>
 #include <cstdlib>
 #include <iterator>
 
+#define DEBUG_TYPE "hexagon-brelax"
+
 using namespace llvm;
 
 // Since we have no exact knowledge of code layout, allow some safety buffer
 // for jump target. This is measured in bytes.
 static cl::opt<uint32_t> BranchRelaxSafetyBuffer("branch-relax-safety-buffer",
   cl::init(200), cl::Hidden, cl::ZeroOrMore, cl::desc("safety buffer size"));
 
 namespace llvm {

llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp

 //===- HexagonConstPropagation.cpp ----------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
-#define DEBUG_TYPE "hcp"
-
 #include "HexagonInstrInfo.h"
 #include "HexagonRegisterInfo.h"
 #include "HexagonSubtarget.h"
 #include "llvm/ADT/APFloat.h"
 #include "llvm/ADT/APInt.h"
 #include "llvm/ADT/PostOrderIterator.h"
 #include "llvm/ADT/SetVector.h"
 #include "llvm/ADT/SmallVector.h"

 #include <cstring>
 #include <iterator>
 #include <map>
 #include <queue>
 #include <set>
 #include <utility>
 #include <vector>
 
+#define DEBUG_TYPE "hcp"
+
 using namespace llvm;
 
 namespace {
 
   // Properties of a value that are tracked by the propagation.
   // A property that is marked as present (i.e. bit is set) dentes that the
   // value is known (proven) to have this property. Not all combinations
   // of bits make sense, for example Zero and NonZero are mutually exclusive,

llvm/lib/Target/Hexagon/HexagonGenMux.cpp

 // This happens after exiting from the SSA form, but before the machine
 // instruction scheduler. After the scheduler and after the register
 // allocation there can be cases of pairs of conditional transfers
 // resulting from a MUX where neither of them was further predicated. If
 // these transfers are now placed far enough from the instruction defining
 // the predicate register, they cannot use the .new form. In such cases it
 // is better to collapse them back to a single MUX instruction.
 
-#define DEBUG_TYPE "hexmux"
-
 #include "HexagonInstrInfo.h"
 #include "HexagonRegisterInfo.h"
 #include "HexagonSubtarget.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/CodeGen/LivePhysRegs.h"

 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/MathExtras.h"
 #include <algorithm>
 #include <cassert>
 #include <iterator>
 #include <limits>
 #include <utility>
 
+#define DEBUG_TYPE "hexmux"
+
 using namespace llvm;
 
 namespace llvm {
 
   FunctionPass *createHexagonGenMux();
   void initializeHexagonGenMuxPass(PassRegistry& Registry);
 
 } // end namespace llvm

llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp

 //===- HexagonSplitDouble.cpp ---------------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
-#define DEBUG_TYPE "hsdr"
-
 #include "HexagonInstrInfo.h"
 #include "HexagonRegisterInfo.h"
 #include "HexagonSubtarget.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"

 #include <cassert>
 #include <cstdint>
 #include <limits>
 #include <map>
 #include <set>
 #include <utility>
 #include <vector>
 
+#define DEBUG_TYPE "hsdr"
+
 using namespace llvm;
 
 namespace llvm {
 
   FunctionPass *createHexagonSplitDoubleRegs();
   void initializeHexagonSplitDoubleRegsPass(PassRegistry&);
 
 } // end namespace llvm

llvm/lib/Target/Hexagon/HexagonTargetObjectFile.cpp

 //===-- HexagonTargetObjectFile.cpp ---------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the declarations of the HexagonTargetAsmInfo properties.
 //
 //===----------------------------------------------------------------------===//
 
-#define DEBUG_TYPE "hexagon-sdata"
-
 #include "HexagonTargetObjectFile.h"
 #include "llvm/ADT/SmallString.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/BinaryFormat/ELF.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/IR/DerivedTypes.h"
 #include "llvm/IR/GlobalObject.h"
 #include "llvm/IR/GlobalValue.h"
 #include "llvm/IR/GlobalVariable.h"
 #include "llvm/IR/Module.h"
 #include "llvm/IR/Type.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/SectionKind.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetMachine.h"
 
+#define DEBUG_TYPE "hexagon-sdata"
+
 using namespace llvm;
 
 static cl::opt<unsigned> SmallDataThreshold("hexagon-small-data-threshold",
   cl::init(8), cl::Hidden,
   cl::desc("The maximum size of an object in the sdata section"));
 
 static cl::opt<bool> NoSmallDataSorting("mno-sort-sda", cl::init(false),
   cl::Hidden, cl::desc("Disable small data sections sorting"));

llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp

 //=== HexagonMCELFStreamer.cpp - Hexagon subclass of MCELFStreamer -------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file is a stub that parses a MCInst bundle and passes the
 // instructions on to the real streamer.
 //
 //===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "hexagonmcelfstreamer"
 
 #include "MCTargetDesc/HexagonMCELFStreamer.h"
 #include "MCTargetDesc/HexagonMCInstrInfo.h"
 #include "MCTargetDesc/HexagonMCShuffler.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/BinaryFormat/ELF.h"
 #include "llvm/MC/MCAsmBackend.h"
 #include "llvm/MC/MCAssembler.h"

 #include "llvm/MC/MCSymbolELF.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MathExtras.h"
 #include <cassert>
 #include <cstdint>
 
+#define DEBUG_TYPE "hexagonmcelfstreamer"
+
 using namespace llvm;
 
 static cl::opt<unsigned> GPSize
   ("gpsize", cl::NotHidden,
    cl::desc("Global Pointer Addressing Size.  The default size is 8."),
    cl::Prefix,
    cl::init(8));
 

llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp

 //===----- HexagonMCShuffler.cpp - MC bundle shuffling --------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This implements the shuffling of insns inside a bundle according to the
 // packet formation rules of the Hexagon ISA.
 //
 //===----------------------------------------------------------------------===//
 
-#define DEBUG_TYPE "hexagon-shuffle"
-
 #include "MCTargetDesc/HexagonMCShuffler.h"
 #include "MCTargetDesc/HexagonMCInstrInfo.h"
 #include "MCTargetDesc/HexagonShuffler.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 #include <cassert>
 
+#define DEBUG_TYPE "hexagon-shuffle"
+
 using namespace llvm;
 
 static cl::opt<bool>
     DisableShuffle("disable-hexagon-shuffle", cl::Hidden, cl::init(false),
                    cl::desc("Disable Hexagon instruction shuffling"));
 
 void HexagonMCShuffler::init(MCInst &MCB) {
   if (HexagonMCInstrInfo::isBundle(MCB)) {

llvm/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp

 //===- HexagonShuffler.cpp - Instruction bundle shuffling -----------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This implements the shuffling of insns inside a bundle according to the
 // packet formation rules of the Hexagon ISA.
 //
 //===----------------------------------------------------------------------===//
 
-#define DEBUG_TYPE "hexagon-shuffle"
-
 #include "MCTargetDesc/HexagonShuffler.h"
 #include "MCTargetDesc/HexagonBaseInfo.h"
 #include "MCTargetDesc/HexagonMCInstrInfo.h"
 #include "MCTargetDesc/HexagonMCTargetDesc.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/SourceMgr.h"
 #include "llvm/Support/raw_ostream.h"
 #include <algorithm>
 #include <cassert>
 #include <utility>
 #include <vector>
 
+#define DEBUG_TYPE "hexagon-shuffle"
+
 using namespace llvm;
 
 namespace {
 
 // Insn shuffling priority.
 class HexagonBid {
   // The priority is directly proportional to how restricted the insn is based
   // on its flexibility to run on the available slots.  So, the fewer slots it

llvm/lib/Target/Lanai/Disassembler/LanaiDisassembler.h

 //===- LanaiDisassembler.cpp - Disassembler for Lanai -----------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file is part of the Lanai Disassembler.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_LANAI_DISASSEMBLER_LANAIDISASSEMBLER_H
 #define LLVM_LIB_TARGET_LANAI_DISASSEMBLER_LANAIDISASSEMBLER_H
 
-#define DEBUG_TYPE "lanai-disassembler"
-
 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
 
+#define DEBUG_TYPE "lanai-disassembler"
+
 namespace llvm {
 
 class LanaiDisassembler : public MCDisassembler {
 public:
   LanaiDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx);
 
   ~LanaiDisassembler() override = default;
 

llvm/lib/Target/M68k/M68kRegisterInfo.cpp

 //===-- M68kRegisterInfo.cpp - CPU0 Register Information -----*- C++ -*--===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
 /// This file contains the CPU0 implementation of the TargetRegisterInfo class.
 ///
 //===----------------------------------------------------------------------===//
 
-#define DEBUG_TYPE "m68k-reg-info"
-
 #include "M68kRegisterInfo.h"
 
 #include "M68k.h"
 #include "M68kMachineFunction.h"
 #include "M68kSubtarget.h"
 
 #include "MCTargetDesc/M68kMCTargetDesc.h"
 
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/IR/Function.h"
 #include "llvm/IR/Type.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
 
 #define GET_REGINFO_TARGET_DESC
 #include "M68kGenRegisterInfo.inc"
 
+#define DEBUG_TYPE "m68k-reg-info"
+
 using namespace llvm;
 
 static cl::opt<bool> EnableBasePointer(
     "m68k-use-base-pointer", cl::Hidden, cl::init(true),
     cl::desc("Enable use of a base pointer for complex stack frames"));
 
 // Pin the vtable to this file.
 void M68kRegisterInfo::anchor() {}

llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp

 //
 //    to look like this:
 //
 //    T *p = array[-1];
 //    for (int i = 0; i < n; ++i)
 //      *++p = c;
 //===----------------------------------------------------------------------===//
 
-#define DEBUG_TYPE "ppc-loop-instr-form-prep"
-
 #include "PPC.h"
 #include "PPCSubtarget.h"
 #include "PPCTargetMachine.h"
 #include "llvm/ADT/DepthFirstIterator.h"
 #include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/Statistic.h"

 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
 #include "llvm/Transforms/Utils/Local.h"
 #include "llvm/Transforms/Utils/LoopUtils.h"
 #include "llvm/Transforms/Utils/ScalarEvolutionExpander.h"
 #include <cassert>
 #include <iterator>
 #include <utility>
 
+#define DEBUG_TYPE "ppc-loop-instr-form-prep"
+
 using namespace llvm;
 
 static cl::opt<unsigned> MaxVarsPrep("ppc-formprep-max-vars",
                                  cl::Hidden, cl::init(24),
   cl::desc("Potential common base number threshold per function for PPC loop "
            "prep"));
 
 static cl::opt<bool> PreferUpdateForm("ppc-formprep-prefer-update",

llvm/lib/Transforms/Scalar/AlignmentFromAssumptions.cpp

 // expressions of assume intrinsics. The primary motivation is to handle
 // complex alignment assumptions that apply to vector loads and stores that
 // appear after vectorization and unrolling.
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/IR/Instructions.h"
 #include "llvm/InitializePasses.h"
-#define AA_NAME "alignment-from-assumptions"
-#define DEBUG_TYPE AA_NAME
 #include "llvm/Transforms/Scalar/AlignmentFromAssumptions.h"
 #include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/Analysis/AliasAnalysis.h"
 #include "llvm/Analysis/AssumptionCache.h"
 #include "llvm/Analysis/GlobalsModRef.h"
 #include "llvm/Analysis/LoopInfo.h"
 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
 #include "llvm/Analysis/ValueTracking.h"
 #include "llvm/IR/Constant.h"
 #include "llvm/IR/Dominators.h"
 #include "llvm/IR/Instruction.h"
 #include "llvm/IR/IntrinsicInst.h"
 #include "llvm/IR/Intrinsics.h"
 #include "llvm/IR/Module.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Transforms/Scalar.h"
+
+#define AA_NAME "alignment-from-assumptions"
+#define DEBUG_TYPE AA_NAME
 using namespace llvm;
 
 STATISTIC(NumLoadAlignChanged,
   "Number of loads changed by alignment assumptions");
 STATISTIC(NumStoreAlignChanged,
   "Number of stores changed by alignment assumptions");
 STATISTIC(NumMemIntAlignChanged,
   "Number of memory intrinsics changed by alignment assumptions");

llvm/lib/Transforms/Scalar/Float2Int.cpp

 //===- Float2Int.cpp - Demote floating point ops to work on integers ------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the Float2Int pass, which aims to demote floating
 // point operations to work on integers, where that is losslessly possible.
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/InitializePasses.h"
 #include "llvm/Support/CommandLine.h"
-#define DEBUG_TYPE "float2int"
-
 #include "llvm/Transforms/Scalar/Float2Int.h"
 #include "llvm/ADT/APInt.h"
 #include "llvm/ADT/APSInt.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Analysis/GlobalsModRef.h"
 #include "llvm/IR/Constants.h"
 #include "llvm/IR/IRBuilder.h"
 #include "llvm/IR/InstIterator.h"
 #include "llvm/IR/Instructions.h"
 #include "llvm/IR/Module.h"
 #include "llvm/Pass.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Transforms/Scalar.h"
 #include <deque>
 #include <functional> // For std::function
+
+#define DEBUG_TYPE "float2int"
+
 using namespace llvm;
 
 // The algorithm is simple. Start at instructions that convert from the
 // float to the int domain: fptoui, fptosi and fcmp. Walk up the def-use
 // graph, using an equivalence datastructure to unify graphs that interfere.
 //
 // Mappable instructions are those with an integer corrollary that, given
 // integer domain inputs, produce an integer output; fadd, for example.

llvm/lib/Transforms/Scalar/LoopDataPrefetch.cpp

 //===-------- LoopDataPrefetch.cpp - Loop Data Prefetching Pass -----------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements a Loop Data Prefetching Pass.
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/Transforms/Scalar/LoopDataPrefetch.h"
 #include "llvm/InitializePasses.h"
 
-#define DEBUG_TYPE "loop-data-prefetch"
 #include "llvm/ADT/DepthFirstIterator.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/Analysis/AssumptionCache.h"
 #include "llvm/Analysis/CodeMetrics.h"
 #include "llvm/Analysis/LoopInfo.h"
 #include "llvm/Analysis/OptimizationRemarkEmitter.h"
 #include "llvm/Analysis/ScalarEvolution.h"
 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
 #include "llvm/Analysis/TargetTransformInfo.h"
 #include "llvm/IR/CFG.h"
 #include "llvm/IR/Dominators.h"
 #include "llvm/IR/Function.h"
 #include "llvm/IR/Module.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Transforms/Scalar.h"
 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
 #include "llvm/Transforms/Utils/ScalarEvolutionExpander.h"
 #include "llvm/Transforms/Utils/ValueMapper.h"
+
+#define DEBUG_TYPE "loop-data-prefetch"
+
 using namespace llvm;
 
 // By default, we limit this to creating 16 PHIs (which is a little over half
 // of the allocatable register set).
 static cl::opt<bool>
 PrefetchWrites("loop-prefetch-writes", cl::Hidden, cl::init(false),
                cl::desc("Prefetch write addresses"));
 

llvm/utils/TableGen/DFAEmitter.cpp

 //
 // The generated code can run the DFA and produce an accepted / not accepted
 // state and also produce, given a sequence of transitions that results in an
 // accepted state, the sequence of intermediate states. This is useful if the
 // initial automaton was nondeterministic - it allows mapping back from the DFA
 // to the NFA.
 //
 //===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "dfa-emitter"
 
 #include "DFAEmitter.h"
 #include "CodeGenTarget.h"
 #include "SequenceToOffsetTable.h"
 #include "TableGenBackends.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/UniqueVector.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/TableGen/Record.h"
 #include "llvm/TableGen/TableGenBackend.h"
 #include <cassert>
 #include <cstdint>
 #include <map>
 #include <set>
 #include <string>
 #include <vector>
 
+#define DEBUG_TYPE "dfa-emitter"
+
 using namespace llvm;
 
 //===----------------------------------------------------------------------===//
 // DfaEmitter implementation. This is independent of the GenAutomaton backend.
 //===----------------------------------------------------------------------===//
 
 void DfaEmitter::addTransition(state_type From, state_type To, action_type A) {
   Actions.insert(A);

llvm/utils/TableGen/DFAPacketizerEmitter.cpp

 //===- DFAPacketizerEmitter.cpp - Packetization DFA for a VLIW machine ----===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This class parses the Schedule.td file and produces an API that can be used
 // to reason about whether an instruction can be added to a packet on a VLIW
 // architecture. The class internally generates a deterministic finite
 // automaton (DFA) that models all possible mappings of machine instructions
 // to functional units as instructions are added to a packet.
 //
 //===----------------------------------------------------------------------===//
 
-#define DEBUG_TYPE "dfa-emitter"
-
 #include "CodeGenSchedule.h"
 #include "CodeGenTarget.h"
 #include "DFAEmitter.h"
 #include "llvm/ADT/DenseSet.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/TableGen/Record.h"
 #include "llvm/TableGen/TableGenBackend.h"
 #include <cassert>
 #include <cstdint>
 #include <map>
 #include <set>
 #include <string>
 #include <unordered_map>
 #include <vector>
 
+#define DEBUG_TYPE "dfa-emitter"
+
 using namespace llvm;
 
 // We use a uint64_t to represent a resource bitmask.
 #define DFA_MAX_RESOURCES 64
 
 namespace {
 using ResourceVector = SmallVector<uint64_t, 4>;