[AArch64] Lower fpto*i.sat intrinsics.

[jbramley]

Summary

AArch64's fctv* instructions implement the saturating behaviour that the
fpto*i.sat intrinsics require, in cases where the destination width
matches the saturation width. Lowering them removes a lot of unnecessary
generated code.

Only scalar lowerings are supported for now.

[nikic]

For the record, there is also the somewhat stale D86078 for this.

[SjoerdMeijer]

In D102353#2755176, @nikic wrote:

For the record, there is also the somewhat stale D86078 for this.

Thanks for pointing that out. From a quick look, the author of that patch, @ebevhan, hasn't been active since Oct. 2020, so I am assuming this work can best be continued here.

[jbramley]

In D102353#2755176, @nikic wrote:

For the record, there is also the somewhat stale D86078 for this.

Thanks, I wasn't aware of that. At a glance, it looks like that patch implements DstWidth != SatWidth and vector types; I left that as a TODO, hoping to seek feedback on the overall approach first. I think they'll be fairly clean incremental changes but I can roll them into this patch if that's preferred.

By the way, the use-case for this is Rust, which has well-defined sematics for FP-to-integer casts so this becomes a fairly common operation.

[SjoerdMeijer]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

3304

Nit: I don't see precedent for checking opcodes again; I think this assert can be removed.

3315

Nit: "must be smaller or equal ...", or "cannot exceed ..."

3318

The other patch was doing this:

if (SrcVT.isVector()) {
  SDValue Vec = LowerVectorFP_TO_INT(Op, DAG);
  if (Vec != Op)
    return Vec;
}

Haven't looked into this, but does that make sense? Can we reuse that?

3322

Nit: the coding style says that we don't need brackets around ifs if they contain one statement. So to save some space we can remove the brackets and place the TODO before the if.

3328

Nit: remove the brackets, and just use dl(Op) directly as an argument.

3336

Same nit, don't need the brackets.

16025

Nit: the comment makes sense, I am not sure it belongs here though.

llvm/test/CodeGen/AArch64/round-fptosi-sat-scalar.ll

44

I haven't checked, but we don't have a f16 -> i32 variant of this?

195

A trunc from a f16 to a f16 should be a no-op? Do we need this? I see similar patterns below, so I must be missing something...

[SjoerdMeijer]

Thanks, I wasn't aware of that. At a glance, it looks like that patch implements DstWidth != SatWidth and vector types; I left that as a TODO, hoping to seek feedback on the overall approach first. I think they'll be fairly clean incremental changes but I can roll them into this patch if that's preferred.

I think the TODO is fine, and that could be addressed with a follow up.

[jbramley]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

3318

The other patch also extends LowerVectorFP_TO_INT to handle the saturating semantics. It's probably a reasonable approach, and didn't see any objections there.

llvm/test/CodeGen/AArch64/round-fptosi-sat-scalar.ll

44

Isn't that @llvm.fptosi.sat.i32.f16, in @testmswh, above?

195

We need it because trunc truncates to an integer, leaving the result in the same FP format (like frintz in the fallback machine instruction sequence). It's not a no-op.

All of the tests in this file are round + convert sequences, like round.conv.ll. I added other tests to fptosi-sat-scalar.ll (etc) for the simple, standalone conversions.

[SjoerdMeijer]

llvm/test/CodeGen/AArch64/round-fptosi-sat-scalar.ll

44

Yep, sorry, missed that!

195

Ah okay, thanks, and I see now. I read this too quickly.

[jbramley]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

16025

Agreed. It probably makes more sense near the setTargetDAGCombine configuration in AArch64TargetLowering.

[jbramley]

llvm/lib/Target/AArch64/AArch64ISelLowering.h

960

Can I just ignore these? Matching the de-facto convention seems appropriate, but I think these are responsible for the reported build failure.

[SjoerdMeijer]

llvm/lib/Target/AArch64/AArch64ISelLowering.h

960

Yep, this is an unhelpful message in this case; this is just following the convention/style in this file so is alright.
I had a quick look, but am not sure what the cause of the failure is as it seems all regression tests are passing, but somewhere it is doing an Exit 1. I would ignore this and blame it on a glitch or flaky bot.

[jbramley]

Addressed review comments.

This addresses all review comments, except for the one about SrcVT.isVector(),
which I think we agreed is Ok as a follow-up patch.

[SjoerdMeijer]

This LGTM as a first version.

[jbramley]

Thanks!

Could someone commit it for me please? I don't have access myself.

[SjoerdMeijer]

In D102353#2759485, @jbramley wrote:

Thanks!

Could someone commit it for me please? I don't have access myself.

Happy to commit this on your behalf, but requesting an account should be straightforward so that you can commit it yourself. That might be convenient because it sounds like you have some follow up patches in the pipeline.

llvm/lib/Target/AArch64/AArch64ISelLowering.h

private:
   SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
+  SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerXOR(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVSCALE(SDValue Op, SelectionDAG &DAG) const;

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::STRICT_UINT_TO_FP, MVT::i128, Custom);
   setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
   setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
   setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
   setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, Custom);
   setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Custom);
   setOperationAction(ISD::STRICT_FP_ROUND, MVT::f64, Custom);
 
+  setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i32, Custom);
+  setOperationAction(ISD::FP_TO_UINT_SAT, MVT::i64, Custom);
+  setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i32, Custom);
+  setOperationAction(ISD::FP_TO_SINT_SAT, MVT::i64, Custom);
+
   // Variable arguments.
   setOperationAction(ISD::VASTART, MVT::Other, Custom);
   setOperationAction(ISD::VAARG, MVT::Other, Custom);
   setOperationAction(ISD::VACOPY, MVT::Other, Custom);
   setOperationAction(ISD::VAEND, MVT::Other, Expand);
 
   // Variable-sized objects.
   setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
#undef LCALLNAME5
   setTargetDAGCombine(ISD::ADD);
   setTargetDAGCombine(ISD::ABS);
   setTargetDAGCombine(ISD::SUB);
   setTargetDAGCombine(ISD::SRL);
   setTargetDAGCombine(ISD::XOR);
   setTargetDAGCombine(ISD::SINT_TO_FP);
   setTargetDAGCombine(ISD::UINT_TO_FP);
 
+  // TODO: Do the same for FP_TO_*INT_SAT.
   setTargetDAGCombine(ISD::FP_TO_SINT);
   setTargetDAGCombine(ISD::FP_TO_UINT);
   setTargetDAGCombine(ISD::FDIV);
 
   setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
 
   setTargetDAGCombine(ISD::ANY_EXTEND);
   setTargetDAGCombine(ISD::ZERO_EXTEND);
SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
   if (SrcVal.getValueType() != MVT::f128) {
     // It's legal except when f128 is involved
     return Op;
   }
 
   return SDValue();
 }
 
+SDValue AArch64TargetLowering::LowerFP_TO_INT_SAT(SDValue Op,
+                                                  SelectionDAG &DAG) const {
+  // AArch64 FP-to-int conversions saturate to the destination register size, so
+  // we can lower common saturating conversions to simple instructions.
+  SDValue SrcVal = Op.getOperand(0);
+
+  EVT SrcVT = SrcVal.getValueType();
+  EVT DstVT = Op.getValueType();
+
+  EVT SatVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
+  uint64_t SatWidth = SatVT.getScalarSizeInBits();
+  uint64_t DstWidth = DstVT.getScalarSizeInBits();
+  assert(SatWidth <= DstWidth && "Saturation width cannot exceed result width");
+
+  // TODO: Support lowering of NEON and SVE conversions.
+  if (SrcVT.isVector())
+    return SDValue();
+
+  // TODO: Saturate to SatWidth explicitly.
+  if (SatWidth != DstWidth)
+    return SDValue();
+
+  // In the absence of FP16 support, promote f32 to f16, like LowerFP_TO_INT().
+  if (SrcVT == MVT::f16 && !Subtarget->hasFullFP16())
+    return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(),
+                       DAG.getNode(ISD::FP_EXTEND, SDLoc(Op), MVT::f32, SrcVal),
+                       Op.getOperand(1));
+
+  // Cases that we can emit directly.
+  if ((SrcVT == MVT::f64 || SrcVT == MVT::f32 ||
+       (SrcVT == MVT::f16 && Subtarget->hasFullFP16())) &&
+      (DstVT == MVT::i64 || DstVT == MVT::i32))
+    return Op;
+
+  // For all other cases, fall back on the expanded form.
+  return SDValue();
+}
+
 SDValue AArch64TargetLowering::LowerVectorINT_TO_FP(SDValue Op,
                                                     SelectionDAG &DAG) const {
   // Warning: We maintain cost tables in AArch64TargetTransformInfo.cpp.
   // Any additional optimization in this function should be recorded
   // in the cost tables.
   EVT VT = Op.getValueType();
   SDLoc dl(Op);
   SDValue In = Op.getOperand(0);
SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
   case ISD::STRICT_SINT_TO_FP:
   case ISD::STRICT_UINT_TO_FP:
     return LowerINT_TO_FP(Op, DAG);
   case ISD::FP_TO_SINT:
   case ISD::FP_TO_UINT:
   case ISD::STRICT_FP_TO_SINT:
   case ISD::STRICT_FP_TO_UINT:
     return LowerFP_TO_INT(Op, DAG);
+  case ISD::FP_TO_SINT_SAT:
+  case ISD::FP_TO_UINT_SAT:
+    return LowerFP_TO_INT_SAT(Op, DAG);
   case ISD::FSINCOS:
     return LowerFSINCOS(Op, DAG);
   case ISD::FLT_ROUNDS_:
     return LowerFLT_ROUNDS_(Op, DAG);
   case ISD::SET_ROUNDING:
     return LowerSET_ROUNDING(Op, DAG);
   case ISD::MUL:
     return LowerMUL(Op, DAG);
case ISD::XOR:
     return performXorCombine(N, DAG, DCI, Subtarget);
   case ISD::MUL:
     return performMulCombine(N, DAG, DCI, Subtarget);
   case ISD::SINT_TO_FP:
   case ISD::UINT_TO_FP:
     return performIntToFpCombine(N, DAG, Subtarget);
   case ISD::FP_TO_SINT:
   case ISD::FP_TO_UINT:
     return performFpToIntCombine(N, DAG, DCI, Subtarget);
   case ISD::FDIV:
     return performFDivCombine(N, DAG, DCI, Subtarget);
   case ISD::OR:
     return performORCombine(N, DCI, Subtarget);
   case ISD::AND:
     return performANDCombine(N, DCI);
   case ISD::SRL:
     return performSRLCombine(N, DCI);

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_aarch64_neon_fcvtnu>;
 defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_aarch64_neon_fcvtps>;
 defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_aarch64_neon_fcvtpu>;
 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", any_fp_to_sint>;
 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>;
 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", any_fp_to_sint>;
 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>;
 
+// AArch64's FCVT instructions saturate when out of range.
+multiclass FPToIntegerSatPats<SDNode to_int_sat, string INST> {
+  def : Pat<(i32 (to_int_sat f16:$Rn, i32)),
+            (!cast<Instruction>(INST # UWHr) f16:$Rn)>;
+  def : Pat<(i32 (to_int_sat f32:$Rn, i32)),
+            (!cast<Instruction>(INST # UWSr) f32:$Rn)>;
+  def : Pat<(i32 (to_int_sat f64:$Rn, i32)),
+            (!cast<Instruction>(INST # UWDr) f64:$Rn)>;
+  def : Pat<(i64 (to_int_sat f16:$Rn, i64)),
+            (!cast<Instruction>(INST # UXHr) f16:$Rn)>;
+  def : Pat<(i64 (to_int_sat f32:$Rn, i64)),
+            (!cast<Instruction>(INST # UXSr) f32:$Rn)>;
+  def : Pat<(i64 (to_int_sat f64:$Rn, i64)),
+            (!cast<Instruction>(INST # UXDr) f64:$Rn)>;
+}
+
+defm : FPToIntegerSatPats<fp_to_sint_sat, "FCVTZS">;
+defm : FPToIntegerSatPats<fp_to_uint_sat, "FCVTZU">;
+
 multiclass FPToIntegerIntPats<Intrinsic round, string INST> {
   def : Pat<(i32 (round f16:$Rn)), (!cast<Instruction>(INST # UWHr) $Rn)>;
   def : Pat<(i64 (round f16:$Rn)), (!cast<Instruction>(INST # UXHr) $Rn)>;
   def : Pat<(i32 (round f32:$Rn)), (!cast<Instruction>(INST # UWSr) $Rn)>;
   def : Pat<(i64 (round f32:$Rn)), (!cast<Instruction>(INST # UXSr) $Rn)>;
   def : Pat<(i32 (round f64:$Rn)), (!cast<Instruction>(INST # UWDr) $Rn)>;
   def : Pat<(i64 (round f64:$Rn)), (!cast<Instruction>(INST # UXDr) $Rn)>;
 
def : Pat<(i32 (round (fmul f64:$Rn, fixedpoint_f64_i32:$scale))),
             (!cast<Instruction>(INST # SWDri) $Rn, $scale)>;
   def : Pat<(i64 (round (fmul f64:$Rn, fixedpoint_f64_i64:$scale))),
             (!cast<Instruction>(INST # SXDri) $Rn, $scale)>;
 }
 
 defm : FPToIntegerIntPats<int_aarch64_neon_fcvtzs, "FCVTZS">;
 defm : FPToIntegerIntPats<int_aarch64_neon_fcvtzu, "FCVTZU">;
 
-multiclass FPToIntegerPats<SDNode to_int, SDNode round, string INST> {
+multiclass FPToIntegerPats<SDNode to_int, SDNode to_int_sat, SDNode round, string INST> {
   def : Pat<(i32 (to_int (round f32:$Rn))),
             (!cast<Instruction>(INST # UWSr) f32:$Rn)>;
   def : Pat<(i64 (to_int (round f32:$Rn))),
             (!cast<Instruction>(INST # UXSr) f32:$Rn)>;
   def : Pat<(i32 (to_int (round f64:$Rn))),
             (!cast<Instruction>(INST # UWDr) f64:$Rn)>;
   def : Pat<(i64 (to_int (round f64:$Rn))),
             (!cast<Instruction>(INST # UXDr) f64:$Rn)>;
+
+  // These instructions saturate like fp_to_[su]int_sat.
+  def : Pat<(i32 (to_int_sat (round f16:$Rn), i32)),
+            (!cast<Instruction>(INST # UWHr) f16:$Rn)>;
+  def : Pat<(i64 (to_int_sat (round f16:$Rn), i64)),
+            (!cast<Instruction>(INST # UXHr) f16:$Rn)>;
+  def : Pat<(i32 (to_int_sat (round f32:$Rn), i32)),
+            (!cast<Instruction>(INST # UWSr) f32:$Rn)>;
+  def : Pat<(i64 (to_int_sat (round f32:$Rn), i64)),
+            (!cast<Instruction>(INST # UXSr) f32:$Rn)>;
+  def : Pat<(i32 (to_int_sat (round f64:$Rn), i32)),
+            (!cast<Instruction>(INST # UWDr) f64:$Rn)>;
+  def : Pat<(i64 (to_int_sat (round f64:$Rn), i64)),
+            (!cast<Instruction>(INST # UXDr) f64:$Rn)>;
 }
 
-defm : FPToIntegerPats<fp_to_sint, fceil,  "FCVTPS">;
-defm : FPToIntegerPats<fp_to_uint, fceil,  "FCVTPU">;
-defm : FPToIntegerPats<fp_to_sint, ffloor, "FCVTMS">;
-defm : FPToIntegerPats<fp_to_uint, ffloor, "FCVTMU">;
-defm : FPToIntegerPats<fp_to_sint, ftrunc, "FCVTZS">;
-defm : FPToIntegerPats<fp_to_uint, ftrunc, "FCVTZU">;
-defm : FPToIntegerPats<fp_to_sint, fround, "FCVTAS">;
-defm : FPToIntegerPats<fp_to_uint, fround, "FCVTAU">;
+defm : FPToIntegerPats<fp_to_sint, fp_to_sint_sat, fceil,  "FCVTPS">;
+defm : FPToIntegerPats<fp_to_uint, fp_to_uint_sat, fceil,  "FCVTPU">;
+defm : FPToIntegerPats<fp_to_sint, fp_to_sint_sat, ffloor, "FCVTMS">;
+defm : FPToIntegerPats<fp_to_uint, fp_to_uint_sat, ffloor, "FCVTMU">;
+defm : FPToIntegerPats<fp_to_sint, fp_to_sint_sat, ftrunc, "FCVTZS">;
+defm : FPToIntegerPats<fp_to_uint, fp_to_uint_sat, ftrunc, "FCVTZU">;
+defm : FPToIntegerPats<fp_to_sint, fp_to_sint_sat, fround, "FCVTAS">;
+defm : FPToIntegerPats<fp_to_uint, fp_to_uint_sat, fround, "FCVTAU">;
+
+
 
 let Predicates = [HasFullFP16] in {
   def : Pat<(i32 (lround f16:$Rn)),
             (!cast<Instruction>(FCVTASUWHr) f16:$Rn)>;
   def : Pat<(i64 (lround f16:$Rn)),
             (!cast<Instruction>(FCVTASUXHr) f16:$Rn)>;
   def : Pat<(i64 (llround f16:$Rn)),
             (!cast<Instruction>(FCVTASUXHr) f16:$Rn)>;

llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-CVT
+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
 
 ;
 ; 32-bit float to signed integer
 ;
 
 declare   i1 @llvm.fptosi.sat.i1.f32  (float)
 declare   i8 @llvm.fptosi.sat.i8.f32  (float)
 declare  i13 @llvm.fptosi.sat.i13.f32 (float)

 ; CHECK-NEXT:    ret
     %x = call i19 @llvm.fptosi.sat.i19.f32(float %f)
     ret i19 %x
 }
 
 define i32 @test_signed_i32_f32(float %f) nounwind {
 ; CHECK-LABEL: test_signed_i32_f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w9, #-822083584
-; CHECK-NEXT:    mov w11, #1325400063
-; CHECK-NEXT:    fmov s1, w9
-; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    mov w10, #-2147483648
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    fmov s1, w11
-; CHECK-NEXT:    mov w12, #2147483647
-; CHECK-NEXT:    csel w8, w10, w8, lt
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    csel w8, w12, w8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w0, wzr, w8, vs
+; CHECK-NEXT:    fcvtzs w0, s0
 ; CHECK-NEXT:    ret
     %x = call i32 @llvm.fptosi.sat.i32.f32(float %f)
     ret i32 %x
 }
 
 define i50 @test_signed_i50_f32(float %f) nounwind {
 ; CHECK-LABEL: test_signed_i50_f32:
 ; CHECK:       // %bb.0:

 ; CHECK-NEXT:    ret
     %x = call i50 @llvm.fptosi.sat.i50.f32(float %f)
     ret i50 %x
 }
 
 define i64 @test_signed_i64_f32(float %f) nounwind {
 ; CHECK-LABEL: test_signed_i64_f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w9, #-553648128
-; CHECK-NEXT:    mov w11, #1593835519
-; CHECK-NEXT:    fmov s1, w9
-; CHECK-NEXT:    fcvtzs x8, s0
-; CHECK-NEXT:    mov x10, #-9223372036854775808
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    fmov s1, w11
-; CHECK-NEXT:    mov x12, #9223372036854775807
-; CHECK-NEXT:    csel x8, x10, x8, lt
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    csel x8, x12, x8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel x0, xzr, x8, vs
+; CHECK-NEXT:    fcvtzs x0, s0
 ; CHECK-NEXT:    ret
     %x = call i64 @llvm.fptosi.sat.i64.f32(float %f)
     ret i64 %x
 }
 
 define i100 @test_signed_i100_f32(float %f) nounwind {
 ; CHECK-LABEL: test_signed_i100_f32:
 ; CHECK:       // %bb.0:

 ; CHECK-NEXT:    ret
     %x = call i19 @llvm.fptosi.sat.i19.f64(double %f)
     ret i19 %x
 }
 
 define i32 @test_signed_i32_f64(double %f) nounwind {
 ; CHECK-LABEL: test_signed_i32_f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #-4476578029606273024
-; CHECK-NEXT:    mov x9, #281474972516352
-; CHECK-NEXT:    movk x9, #16863, lsl #48
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fmaxnm d1, d0, d1
-; CHECK-NEXT:    fmov d2, x9
-; CHECK-NEXT:    fminnm d1, d1, d2
-; CHECK-NEXT:    fcvtzs w8, d1
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    csel w0, wzr, w8, vs
+; CHECK-NEXT:    fcvtzs w0, d0
 ; CHECK-NEXT:    ret
     %x = call i32 @llvm.fptosi.sat.i32.f64(double %f)
     ret i32 %x
 }
 
 define i50 @test_signed_i50_f64(double %f) nounwind {
 ; CHECK-LABEL: test_signed_i50_f64:
 ; CHECK:       // %bb.0:

 ; CHECK-NEXT:    ret
     %x = call i50 @llvm.fptosi.sat.i50.f64(double %f)
     ret i50 %x
 }
 
 define i64 @test_signed_i64_f64(double %f) nounwind {
 ; CHECK-LABEL: test_signed_i64_f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x9, #-4332462841530417152
-; CHECK-NEXT:    mov x11, #4890909195324358655
-; CHECK-NEXT:    fmov d1, x9
-; CHECK-NEXT:    fcvtzs x8, d0
-; CHECK-NEXT:    mov x10, #-9223372036854775808
-; CHECK-NEXT:    fcmp d0, d1
-; CHECK-NEXT:    fmov d1, x11
-; CHECK-NEXT:    mov x12, #9223372036854775807
-; CHECK-NEXT:    csel x8, x10, x8, lt
-; CHECK-NEXT:    fcmp d0, d1
-; CHECK-NEXT:    csel x8, x12, x8, gt
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    csel x0, xzr, x8, vs
+; CHECK-NEXT:    fcvtzs x0, d0
 ; CHECK-NEXT:    ret
     %x = call i64 @llvm.fptosi.sat.i64.f64(double %f)
     ret i64 %x
 }
 
 define i100 @test_signed_i100_f64(double %f) nounwind {
 ; CHECK-LABEL: test_signed_i100_f64:
 ; CHECK:       // %bb.0:

 ; CHECK-NEXT:    fcmp s0, s0
 ; CHECK-NEXT:    csel w0, wzr, w8, vs
 ; CHECK-NEXT:    ret
     %x = call i19 @llvm.fptosi.sat.i19.f16(half %f)
     ret i19 %x
 }
 
 define i32 @test_signed_i32_f16(half %f) nounwind {
-; CHECK-LABEL: test_signed_i32_f16:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-822083584
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    mov w8, #1325400063
-; CHECK-NEXT:    mov w9, #-2147483648
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    mov w9, #2147483647
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    csel w8, w9, w8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w0, wzr, w8, vs
-; CHECK-NEXT:    ret
+; CHECK-CVT-LABEL: test_signed_i32_f16:
+; CHECK-CVT:       // %bb.0:
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    fcvtzs w0, s0
+; CHECK-CVT-NEXT:    ret
+;
+; CHECK-FP16-LABEL: test_signed_i32_f16:
+; CHECK-FP16:       // %bb.0:
+; CHECK-FP16-NEXT:    fcvtzs w0, h0
+; CHECK-FP16-NEXT:    ret
     %x = call i32 @llvm.fptosi.sat.i32.f16(half %f)
     ret i32 %x
 }
 
 define i50 @test_signed_i50_f16(half %f) nounwind {
 ; CHECK-LABEL: test_signed_i50_f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w8, #-671088640

 ; CHECK-NEXT:    fcmp s0, s0
 ; CHECK-NEXT:    csel x0, xzr, x8, vs
 ; CHECK-NEXT:    ret
     %x = call i50 @llvm.fptosi.sat.i50.f16(half %f)
     ret i50 %x
 }
 
 define i64 @test_signed_i64_f16(half %f) nounwind {
-; CHECK-LABEL: test_signed_i64_f16:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-553648128
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    mov w8, #1593835519
-; CHECK-NEXT:    mov x9, #-9223372036854775808
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fcvtzs x8, s0
-; CHECK-NEXT:    csel x8, x9, x8, lt
-; CHECK-NEXT:    mov x9, #9223372036854775807
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    csel x8, x9, x8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel x0, xzr, x8, vs
-; CHECK-NEXT:    ret
+; CHECK-CVT-LABEL: test_signed_i64_f16:
+; CHECK-CVT:       // %bb.0:
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    fcvtzs x0, s0
+; CHECK-CVT-NEXT:    ret
+;
+; CHECK-FP16-LABEL: test_signed_i64_f16:
+; CHECK-FP16:       // %bb.0:
+; CHECK-FP16-NEXT:    fcvtzs x0, h0
+; CHECK-FP16-NEXT:    ret
     %x = call i64 @llvm.fptosi.sat.i64.f16(half %f)
     ret i64 %x
 }
 
 define i100 @test_signed_i100_f16(half %f) nounwind {
 ; CHECK-LABEL: test_signed_i100_f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str d8, [sp, #-16]! // 8-byte Folded Spill

llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll

 declare <5 x i32> @llvm.fptosi.sat.v5f32.v5i32 (<5 x float>)
 declare <6 x i32> @llvm.fptosi.sat.v6f32.v6i32 (<6 x float>)
 declare <7 x i32> @llvm.fptosi.sat.v7f32.v7i32 (<7 x float>)
 declare <8 x i32> @llvm.fptosi.sat.v8f32.v8i32 (<8 x float>)
 
 define <1 x i32> @test_signed_v1f32_v1i32(<1 x float> %f) {
 ; CHECK-LABEL: test_signed_v1f32_v1i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-822083584
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    mov w10, #1325400063
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    mov w9, #-2147483648
-; CHECK-NEXT:    fmov s3, w10
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    mov w11, #2147483647
-; CHECK-NEXT:    csel w10, w9, w10, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    csel w10, w11, w10, gt
-; CHECK-NEXT:    fcmp s1, s1
 ; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    fcmp s0, s3
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w8, wzr, w8, vs
+; CHECK-NEXT:    mov s1, v0.s[1]
 ; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    mov v0.s[1], w10
+; CHECK-NEXT:    fcvtzs w8, s1
+; CHECK-NEXT:    mov v0.s[1], w8
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
 ; CHECK-NEXT:    ret
     %x = call <1 x i32> @llvm.fptosi.sat.v1f32.v1i32(<1 x float> %f)
     ret <1 x i32> %x
 }
 
 define <2 x i32> @test_signed_v2f32_v2i32(<2 x float> %f) {
 ; CHECK-LABEL: test_signed_v2f32_v2i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-822083584
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    mov w10, #1325400063
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    mov w9, #-2147483648
-; CHECK-NEXT:    fmov s3, w10
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    mov w11, #2147483647
-; CHECK-NEXT:    csel w10, w9, w10, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    csel w10, w11, w10, gt
-; CHECK-NEXT:    fcmp s1, s1
 ; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    fcmp s0, s3
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w8, wzr, w8, vs
+; CHECK-NEXT:    mov s1, v0.s[1]
 ; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    mov v0.s[1], w10
+; CHECK-NEXT:    fcvtzs w8, s1
+; CHECK-NEXT:    mov v0.s[1], w8
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
 ; CHECK-NEXT:    ret
     %x = call <2 x i32> @llvm.fptosi.sat.v2f32.v2i32(<2 x float> %f)
     ret <2 x i32> %x
 }
 
 define <3 x i32> @test_signed_v3f32_v3i32(<3 x float> %f) {
 ; CHECK-LABEL: test_signed_v3f32_v3i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-822083584
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    mov w10, #1325400063
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    mov w9, #-2147483648
-; CHECK-NEXT:    fmov s4, w10
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    mov w11, #2147483647
-; CHECK-NEXT:    csel w10, w9, w10, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    csel w10, w11, w10, gt
-; CHECK-NEXT:    fcmp s1, s1
 ; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    fcmp s0, s4
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    mov s3, v0.s[2]
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    mov s1, v0.s[3]
+; CHECK-NEXT:    mov s1, v0.s[1]
+; CHECK-NEXT:    mov s2, v0.s[2]
+; CHECK-NEXT:    mov s3, v0.s[3]
 ; CHECK-NEXT:    fmov s0, w8
+; CHECK-NEXT:    fcvtzs w8, s1
+; CHECK-NEXT:    fcvtzs w9, s2
+; CHECK-NEXT:    mov v0.s[1], w8
+; CHECK-NEXT:    mov v0.s[2], w9
 ; CHECK-NEXT:    fcvtzs w8, s3
-; CHECK-NEXT:    fcmp s3, s2
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    fcmp s3, s4
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s3, s3
-; CHECK-NEXT:    mov v0.s[1], w10
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    mov v0.s[2], w8
-; CHECK-NEXT:    csel w8, w9, w10, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    csel w8, wzr, w8, vs
 ; CHECK-NEXT:    mov v0.s[3], w8
 ; CHECK-NEXT:    ret
     %x = call <3 x i32> @llvm.fptosi.sat.v3f32.v3i32(<3 x float> %f)
     ret <3 x i32> %x
 }
 
 define <4 x i32> @test_signed_v4f32_v4i32(<4 x float> %f) {
 ; CHECK-LABEL: test_signed_v4f32_v4i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-822083584
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    mov w10, #1325400063
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    mov w9, #-2147483648
-; CHECK-NEXT:    fmov s4, w10
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    mov w11, #2147483647
-; CHECK-NEXT:    csel w10, w9, w10, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    csel w10, w11, w10, gt
-; CHECK-NEXT:    fcmp s1, s1
 ; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    fcmp s0, s4
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    mov s3, v0.s[2]
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    mov s1, v0.s[3]
+; CHECK-NEXT:    mov s1, v0.s[1]
+; CHECK-NEXT:    mov s2, v0.s[2]
+; CHECK-NEXT:    mov s3, v0.s[3]
 ; CHECK-NEXT:    fmov s0, w8
+; CHECK-NEXT:    fcvtzs w8, s1
+; CHECK-NEXT:    fcvtzs w9, s2
+; CHECK-NEXT:    mov v0.s[1], w8
+; CHECK-NEXT:    mov v0.s[2], w9
 ; CHECK-NEXT:    fcvtzs w8, s3
-; CHECK-NEXT:    fcmp s3, s2
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    fcmp s3, s4
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s3, s3
-; CHECK-NEXT:    mov v0.s[1], w10
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    mov v0.s[2], w8
-; CHECK-NEXT:    csel w8, w9, w10, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    csel w8, wzr, w8, vs
 ; CHECK-NEXT:    mov v0.s[3], w8
 ; CHECK-NEXT:    ret
     %x = call <4 x i32> @llvm.fptosi.sat.v4f32.v4i32(<4 x float> %f)
     ret <4 x i32> %x
 }
 
 define <5 x i32> @test_signed_v5f32_v5i32(<5 x float> %f) {
 ; CHECK-LABEL: test_signed_v5f32_v5i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w9, #-822083584
-; CHECK-NEXT:    mov w11, #1325400063
-; CHECK-NEXT:    fmov s5, w9
-; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    mov w10, #-2147483648
-; CHECK-NEXT:    fmov s6, w11
-; CHECK-NEXT:    fcmp s0, s5
-; CHECK-NEXT:    mov w12, #2147483647
-; CHECK-NEXT:    csel w8, w10, w8, lt
-; CHECK-NEXT:    fcmp s0, s6
-; CHECK-NEXT:    csel w8, w12, w8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    fcvtzs w13, s1
-; CHECK-NEXT:    csel w0, wzr, w8, vs
-; CHECK-NEXT:    fcmp s1, s5
-; CHECK-NEXT:    csel w8, w10, w13, lt
-; CHECK-NEXT:    fcmp s1, s6
-; CHECK-NEXT:    csel w8, w12, w8, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs w14, s2
-; CHECK-NEXT:    csel w1, wzr, w8, vs
-; CHECK-NEXT:    fcmp s2, s5
-; CHECK-NEXT:    csel w8, w10, w14, lt
-; CHECK-NEXT:    fcmp s2, s6
-; CHECK-NEXT:    csel w8, w12, w8, gt
-; CHECK-NEXT:    fcmp s2, s2
-; CHECK-NEXT:    fcvtzs w9, s3
-; CHECK-NEXT:    csel w2, wzr, w8, vs
-; CHECK-NEXT:    fcmp s3, s5
-; CHECK-NEXT:    csel w8, w10, w9, lt
-; CHECK-NEXT:    fcmp s3, s6
-; CHECK-NEXT:    csel w8, w12, w8, gt
-; CHECK-NEXT:    fcmp s3, s3
-; CHECK-NEXT:    fcvtzs w11, s4
-; CHECK-NEXT:    csel w3, wzr, w8, vs
-; CHECK-NEXT:    fcmp s4, s5
-; CHECK-NEXT:    csel w8, w10, w11, lt
-; CHECK-NEXT:    fcmp s4, s6
-; CHECK-NEXT:    csel w8, w12, w8, gt
-; CHECK-NEXT:    fcmp s4, s4
-; CHECK-NEXT:    csel w4, wzr, w8, vs
+; CHECK-NEXT:    fcvtzs w0, s0
+; CHECK-NEXT:    fcvtzs w1, s1
+; CHECK-NEXT:    fcvtzs w2, s2
+; CHECK-NEXT:    fcvtzs w3, s3
+; CHECK-NEXT:    fcvtzs w4, s4
 ; CHECK-NEXT:    ret
     %x = call <5 x i32> @llvm.fptosi.sat.v5f32.v5i32(<5 x float> %f)
     ret <5 x i32> %x
 }
 
 define <6 x i32> @test_signed_v6f32_v6i32(<6 x float> %f) {
 ; CHECK-LABEL: test_signed_v6f32_v6i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w9, #-822083584
-; CHECK-NEXT:    mov w11, #1325400063
-; CHECK-NEXT:    fmov s6, w9
-; CHECK-NEXT:    fcvtzs w8, s5
-; CHECK-NEXT:    mov w10, #-2147483648
-; CHECK-NEXT:    fcmp s5, s6
-; CHECK-NEXT:    fmov s7, w11
-; CHECK-NEXT:    mov w12, #2147483647
-; CHECK-NEXT:    csel w8, w10, w8, lt
-; CHECK-NEXT:    fcmp s5, s7
-; CHECK-NEXT:    csel w8, w12, w8, gt
-; CHECK-NEXT:    fcmp s5, s5
-; CHECK-NEXT:    fcvtzs w13, s4
-; CHECK-NEXT:    csel w5, wzr, w8, vs
-; CHECK-NEXT:    fcmp s4, s6
-; CHECK-NEXT:    csel w8, w10, w13, lt
-; CHECK-NEXT:    fcmp s4, s7
-; CHECK-NEXT:    csel w8, w12, w8, gt
-; CHECK-NEXT:    fcmp s4, s4
-; CHECK-NEXT:    fcvtzs w14, s0
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp s0, s6
-; CHECK-NEXT:    csel w13, w10, w14, lt
-; CHECK-NEXT:    fcmp s0, s7
-; CHECK-NEXT:    csel w13, w12, w13, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    fcvtzs w9, s1
-; CHECK-NEXT:    csel w0, wzr, w13, vs
-; CHECK-NEXT:    fcmp s1, s6
-; CHECK-NEXT:    csel w9, w10, w9, lt
-; CHECK-NEXT:    fcmp s1, s7
-; CHECK-NEXT:    csel w9, w12, w9, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs w11, s2
-; CHECK-NEXT:    csel w1, wzr, w9, vs
-; CHECK-NEXT:    fcmp s2, s6
-; CHECK-NEXT:    csel w9, w10, w11, lt
-; CHECK-NEXT:    fcmp s2, s7
-; CHECK-NEXT:    csel w9, w12, w9, gt
-; CHECK-NEXT:    fcmp s2, s2
-; CHECK-NEXT:    fmov s4, w8
-; CHECK-NEXT:    fcvtzs w8, s3
-; CHECK-NEXT:    csel w2, wzr, w9, vs
-; CHECK-NEXT:    fcmp s3, s6
-; CHECK-NEXT:    csel w8, w10, w8, lt
-; CHECK-NEXT:    fcmp s3, s7
-; CHECK-NEXT:    mov v4.s[1], w5
-; CHECK-NEXT:    csel w8, w12, w8, gt
-; CHECK-NEXT:    fcmp s3, s3
-; CHECK-NEXT:    csel w3, wzr, w8, vs
-; CHECK-NEXT:    fmov w4, s4
+; CHECK-NEXT:    fcvtzs w8, s4
+; CHECK-NEXT:    fcvtzs w5, s5
+; CHECK-NEXT:    fcvtzs w0, s0
+; CHECK-NEXT:    fmov s0, w8
+; CHECK-NEXT:    mov v0.s[1], w5
+; CHECK-NEXT:    fcvtzs w1, s1
+; CHECK-NEXT:    fcvtzs w2, s2
+; CHECK-NEXT:    fcvtzs w3, s3
+; CHECK-NEXT:    fmov w4, s0
 ; CHECK-NEXT:    ret
     %x = call <6 x i32> @llvm.fptosi.sat.v6f32.v6i32(<6 x float> %f)
     ret <6 x i32> %x
 }
 
 define <7 x i32> @test_signed_v7f32_v7i32(<7 x float> %f) {
 ; CHECK-LABEL: test_signed_v7f32_v7i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w9, #-822083584
-; CHECK-NEXT:    mov w11, #1325400063
-; CHECK-NEXT:    fmov s7, w9
-; CHECK-NEXT:    fcvtzs w8, s5
-; CHECK-NEXT:    mov w10, #-2147483648
-; CHECK-NEXT:    fcmp s5, s7
-; CHECK-NEXT:    fmov s16, w11
-; CHECK-NEXT:    mov w12, #2147483647
-; CHECK-NEXT:    csel w8, w10, w8, lt
-; CHECK-NEXT:    fcmp s5, s16
-; CHECK-NEXT:    csel w8, w12, w8, gt
-; CHECK-NEXT:    fcmp s5, s5
-; CHECK-NEXT:    fcvtzs w13, s4
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp s4, s7
-; CHECK-NEXT:    csel w11, w10, w13, lt
-; CHECK-NEXT:    fcmp s4, s16
-; CHECK-NEXT:    csel w11, w12, w11, gt
-; CHECK-NEXT:    fcmp s4, s4
-; CHECK-NEXT:    fcvtzs w14, s6
-; CHECK-NEXT:    csel w11, wzr, w11, vs
-; CHECK-NEXT:    fcmp s6, s7
-; CHECK-NEXT:    csel w14, w10, w14, lt
-; CHECK-NEXT:    fcmp s6, s16
-; CHECK-NEXT:    csel w14, w12, w14, gt
-; CHECK-NEXT:    fcmp s6, s6
-; CHECK-NEXT:    fcvtzs w9, s0
-; CHECK-NEXT:    csel w6, wzr, w14, vs
-; CHECK-NEXT:    fcmp s0, s7
-; CHECK-NEXT:    csel w9, w10, w9, lt
-; CHECK-NEXT:    fcmp s0, s16
-; CHECK-NEXT:    csel w9, w12, w9, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    fcvtzs w13, s1
-; CHECK-NEXT:    csel w0, wzr, w9, vs
-; CHECK-NEXT:    fcmp s1, s7
-; CHECK-NEXT:    csel w9, w10, w13, lt
-; CHECK-NEXT:    fcmp s1, s16
-; CHECK-NEXT:    csel w9, w12, w9, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fmov s4, w11
-; CHECK-NEXT:    fcvtzs w11, s2
-; CHECK-NEXT:    csel w1, wzr, w9, vs
-; CHECK-NEXT:    fcmp s2, s7
-; CHECK-NEXT:    csel w9, w10, w11, lt
-; CHECK-NEXT:    fcmp s2, s16
-; CHECK-NEXT:    csel w9, w12, w9, gt
-; CHECK-NEXT:    fcmp s2, s2
-; CHECK-NEXT:    mov v4.s[1], w8
-; CHECK-NEXT:    fcvtzs w8, s3
-; CHECK-NEXT:    csel w2, wzr, w9, vs
-; CHECK-NEXT:    fcmp s3, s7
-; CHECK-NEXT:    csel w8, w10, w8, lt
-; CHECK-NEXT:    fcmp s3, s16
-; CHECK-NEXT:    mov v4.s[2], w6
-; CHECK-NEXT:    csel w8, w12, w8, gt
-; CHECK-NEXT:    fcmp s3, s3
-; CHECK-NEXT:    csel w3, wzr, w8, vs
-; CHECK-NEXT:    mov w5, v4.s[1]
-; CHECK-NEXT:    fmov w4, s4
+; CHECK-NEXT:    fcvtzs w8, s4
+; CHECK-NEXT:    fcvtzs w9, s5
+; CHECK-NEXT:    fcvtzs w0, s0
+; CHECK-NEXT:    fmov s0, w8
+; CHECK-NEXT:    fcvtzs w6, s6
+; CHECK-NEXT:    mov v0.s[1], w9
+; CHECK-NEXT:    mov v0.s[2], w6
+; CHECK-NEXT:    fcvtzs w1, s1
+; CHECK-NEXT:    fcvtzs w2, s2
+; CHECK-NEXT:    fcvtzs w3, s3
+; CHECK-NEXT:    mov w5, v0.s[1]
+; CHECK-NEXT:    fmov w4, s0
 ; CHECK-NEXT:    ret
     %x = call <7 x i32> @llvm.fptosi.sat.v7f32.v7i32(<7 x float> %f)
     ret <7 x i32> %x
 }
 
 define <8 x i32> @test_signed_v8f32_v8i32(<8 x float> %f) {
 ; CHECK-LABEL: test_signed_v8f32_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w10, #-822083584
-; CHECK-NEXT:    mov s3, v0.s[1]
-; CHECK-NEXT:    mov w11, #1325400063
-; CHECK-NEXT:    fmov s2, w10
-; CHECK-NEXT:    mov w8, #-2147483648
-; CHECK-NEXT:    fmov s5, w11
+; CHECK-NEXT:    mov s2, v0.s[1]
+; CHECK-NEXT:    mov s3, v0.s[2]
+; CHECK-NEXT:    fcvtzs w8, s0
+; CHECK-NEXT:    fcvtzs w9, s1
+; CHECK-NEXT:    fcvtzs w10, s2
+; CHECK-NEXT:    mov s2, v1.s[1]
 ; CHECK-NEXT:    fcvtzs w11, s3
-; CHECK-NEXT:    fcmp s3, s2
-; CHECK-NEXT:    mov w9, #2147483647
-; CHECK-NEXT:    csel w11, w8, w11, lt
-; CHECK-NEXT:    fcmp s3, s5
-; CHECK-NEXT:    csel w11, w9, w11, gt
-; CHECK-NEXT:    fcmp s3, s3
-; CHECK-NEXT:    fcvtzs w10, s0
-; CHECK-NEXT:    csel w11, wzr, w11, vs
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csel w10, w8, w10, lt
-; CHECK-NEXT:    fcmp s0, s5
-; CHECK-NEXT:    csel w10, w9, w10, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    mov s4, v0.s[2]
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    mov s3, v0.s[3]
-; CHECK-NEXT:    fmov s0, w10
-; CHECK-NEXT:    fcvtzs w10, s4
-; CHECK-NEXT:    fcmp s4, s2
-; CHECK-NEXT:    csel w10, w8, w10, lt
-; CHECK-NEXT:    fcmp s4, s5
-; CHECK-NEXT:    csel w10, w9, w10, gt
-; CHECK-NEXT:    fcmp s4, s4
-; CHECK-NEXT:    mov v0.s[1], w11
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    mov v0.s[2], w10
-; CHECK-NEXT:    fcvtzs w10, s3
-; CHECK-NEXT:    fcmp s3, s2
-; CHECK-NEXT:    csel w10, w8, w10, lt
-; CHECK-NEXT:    fcmp s3, s5
-; CHECK-NEXT:    csel w10, w9, w10, gt
-; CHECK-NEXT:    fcmp s3, s3
-; CHECK-NEXT:    mov s4, v1.s[1]
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    mov v0.s[3], w10
-; CHECK-NEXT:    fcvtzs w10, s4
-; CHECK-NEXT:    fcmp s4, s2
-; CHECK-NEXT:    csel w10, w8, w10, lt
-; CHECK-NEXT:    fcmp s4, s5
-; CHECK-NEXT:    csel w10, w9, w10, gt
-; CHECK-NEXT:    fcmp s4, s4
-; CHECK-NEXT:    fcvtzs w11, s1
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    csel w11, w8, w11, lt
-; CHECK-NEXT:    fcmp s1, s5
-; CHECK-NEXT:    csel w11, w9, w11, gt
-; CHECK-NEXT:    fcmp s1, s1
 ; CHECK-NEXT:    mov s3, v1.s[2]
-; CHECK-NEXT:    csel w11, wzr, w11, vs
-; CHECK-NEXT:    mov s4, v1.s[3]
-; CHECK-NEXT:    fmov s1, w11
-; CHECK-NEXT:    fcvtzs w11, s3
-; CHECK-NEXT:    fcmp s3, s2
-; CHECK-NEXT:    csel w11, w8, w11, lt
-; CHECK-NEXT:    fcmp s3, s5
-; CHECK-NEXT:    csel w11, w9, w11, gt
-; CHECK-NEXT:    fcmp s3, s3
-; CHECK-NEXT:    mov v1.s[1], w10
-; CHECK-NEXT:    fcvtzs w10, s4
-; CHECK-NEXT:    csel w11, wzr, w11, vs
-; CHECK-NEXT:    fcmp s4, s2
-; CHECK-NEXT:    csel w8, w8, w10, lt
-; CHECK-NEXT:    fcmp s4, s5
-; CHECK-NEXT:    csel w8, w9, w8, gt
-; CHECK-NEXT:    fcmp s4, s4
-; CHECK-NEXT:    mov v1.s[2], w11
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    mov v1.s[3], w8
+; CHECK-NEXT:    fcvtzs w12, s2
+; CHECK-NEXT:    fmov s2, w8
+; CHECK-NEXT:    fcvtzs w8, s3
+; CHECK-NEXT:    fmov s3, w9
+; CHECK-NEXT:    mov v2.s[1], w10
+; CHECK-NEXT:    mov v3.s[1], w12
+; CHECK-NEXT:    mov s0, v0.s[3]
+; CHECK-NEXT:    mov v2.s[2], w11
+; CHECK-NEXT:    mov s1, v1.s[3]
+; CHECK-NEXT:    mov v3.s[2], w8
+; CHECK-NEXT:    fcvtzs w8, s0
+; CHECK-NEXT:    mov v2.s[3], w8
+; CHECK-NEXT:    fcvtzs w8, s1
+; CHECK-NEXT:    mov v3.s[3], w8
+; CHECK-NEXT:    mov v0.16b, v2.16b
+; CHECK-NEXT:    mov v1.16b, v3.16b
 ; CHECK-NEXT:    ret
     %x = call <8 x i32> @llvm.fptosi.sat.v8f32.v8i32(<8 x float> %f)
     ret <8 x i32> %x
 }
 
 ;
 ; Double to signed 32-bit -- Vector size variation
 ;
 
 declare <1 x i32> @llvm.fptosi.sat.v1f64.v1i32 (<1 x double>)
 declare <2 x i32> @llvm.fptosi.sat.v2f64.v2i32 (<2 x double>)
 declare <3 x i32> @llvm.fptosi.sat.v3f64.v3i32 (<3 x double>)
 declare <4 x i32> @llvm.fptosi.sat.v4f64.v4i32 (<4 x double>)
 declare <5 x i32> @llvm.fptosi.sat.v5f64.v5i32 (<5 x double>)
 declare <6 x i32> @llvm.fptosi.sat.v6f64.v6i32 (<6 x double>)
 
 define <1 x i32> @test_signed_v1f64_v1i32(<1 x double> %f) {
 ; CHECK-LABEL: test_signed_v1f64_v1i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #-4476578029606273024
-; CHECK-NEXT:    mov x9, #281474972516352
-; CHECK-NEXT:    movk x9, #16863, lsl #48
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fmaxnm d1, d0, d1
-; CHECK-NEXT:    fmov d2, x9
-; CHECK-NEXT:    fminnm d1, d1, d2
-; CHECK-NEXT:    fcvtzs w8, d1
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    csel w8, wzr, w8, vs
+; CHECK-NEXT:    fcvtzs w8, d0
 ; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    ret
     %x = call <1 x i32> @llvm.fptosi.sat.v1f64.v1i32(<1 x double> %f)
     ret <1 x i32> %x
 }
 
 define <2 x i32> @test_signed_v2f64_v2i32(<2 x double> %f) {
 ; CHECK-LABEL: test_signed_v2f64_v2i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #-4476578029606273024
-; CHECK-NEXT:    mov x9, #281474972516352
+; CHECK-NEXT:    fcvtzs w8, d0
 ; CHECK-NEXT:    mov d1, v0.d[1]
-; CHECK-NEXT:    movk x9, #16863, lsl #48
-; CHECK-NEXT:    fmov d2, x8
-; CHECK-NEXT:    fmaxnm d3, d1, d2
-; CHECK-NEXT:    fmov d4, x9
-; CHECK-NEXT:    fcmp d1, d1
-; CHECK-NEXT:    fmaxnm d1, d0, d2
-; CHECK-NEXT:    fminnm d2, d3, d4
-; CHECK-NEXT:    fminnm d1, d1, d4
-; CHECK-NEXT:    fcvtzs w8, d2
-; CHECK-NEXT:    fcvtzs w9, d1
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    csel w9, wzr, w9, vs
-; CHECK-NEXT:    fmov s0, w9
+; CHECK-NEXT:    fmov s0, w8
+; CHECK-NEXT:    fcvtzs w8, d1
 ; CHECK-NEXT:    mov v0.s[1], w8
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
 ; CHECK-NEXT:    ret
     %x = call <2 x i32> @llvm.fptosi.sat.v2f64.v2i32(<2 x double> %f)
     ret <2 x i32> %x
 }
 
 define <3 x i32> @test_signed_v3f64_v3i32(<3 x double> %f) {
 ; CHECK-LABEL: test_signed_v3f64_v3i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #-4476578029606273024
-; CHECK-NEXT:    mov x9, #281474972516352
-; CHECK-NEXT:    movk x9, #16863, lsl #48
-; CHECK-NEXT:    fmov d3, x8
-; CHECK-NEXT:    fcmp d1, d1
-; CHECK-NEXT:    fmaxnm d1, d1, d3
-; CHECK-NEXT:    fmov d4, x9
-; CHECK-NEXT:    fmaxnm d5, d0, d3
-; CHECK-NEXT:    fminnm d1, d1, d4
-; CHECK-NEXT:    fcvtzs w8, d1
-; CHECK-NEXT:    fminnm d5, d5, d4
-; CHECK-NEXT:    fcvtzs w9, d5
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    fmaxnm d1, d2, d3
-; CHECK-NEXT:    csel w9, wzr, w9, vs
-; CHECK-NEXT:    fmaxnm d3, d3, d0
-; CHECK-NEXT:    fminnm d1, d1, d4
-; CHECK-NEXT:    fmov s0, w9
-; CHECK-NEXT:    fminnm d3, d3, d4
+; CHECK-NEXT:    fcvtzs w8, d0
 ; CHECK-NEXT:    fcvtzs w9, d1
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    fcmp d2, d2
-; CHECK-NEXT:    fcvtzs w8, d3
-; CHECK-NEXT:    csel w9, wzr, w9, vs
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    mov v0.s[2], w9
-; CHECK-NEXT:    csel w8, wzr, w8, vs
+; CHECK-NEXT:    fmov s0, w8
+; CHECK-NEXT:    fcvtzs w10, d2
+; CHECK-NEXT:    mov v0.s[1], w9
+; CHECK-NEXT:    mov v0.s[2], w10
+; CHECK-NEXT:    fcvtzs w8, d0
 ; CHECK-NEXT:    mov v0.s[3], w8
 ; CHECK-NEXT:    ret
     %x = call <3 x i32> @llvm.fptosi.sat.v3f64.v3i32(<3 x double> %f)
     ret <3 x i32> %x
 }
 
 define <4 x i32> @test_signed_v4f64_v4i32(<4 x double> %f) {
 ; CHECK-LABEL: test_signed_v4f64_v4i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #-4476578029606273024
-; CHECK-NEXT:    mov x9, #281474972516352
+; CHECK-NEXT:    fcvtzs w8, d0
 ; CHECK-NEXT:    mov d2, v0.d[1]
-; CHECK-NEXT:    movk x9, #16863, lsl #48
-; CHECK-NEXT:    fmov d4, x8
-; CHECK-NEXT:    fmaxnm d5, d2, d4
-; CHECK-NEXT:    fcmp d2, d2
-; CHECK-NEXT:    fmov d2, x9
-; CHECK-NEXT:    fminnm d5, d5, d2
-; CHECK-NEXT:    fcvtzs w8, d5
-; CHECK-NEXT:    fmaxnm d5, d0, d4
-; CHECK-NEXT:    fminnm d5, d5, d2
-; CHECK-NEXT:    mov d3, v1.d[1]
-; CHECK-NEXT:    fcvtzs w9, d5
-; CHECK-NEXT:    fmaxnm d5, d1, d4
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    fmaxnm d4, d3, d4
-; CHECK-NEXT:    fminnm d5, d5, d2
-; CHECK-NEXT:    csel w9, wzr, w9, vs
-; CHECK-NEXT:    fminnm d2, d4, d2
-; CHECK-NEXT:    fmov s0, w9
-; CHECK-NEXT:    fcvtzs w9, d5
-; CHECK-NEXT:    fcmp d1, d1
-; CHECK-NEXT:    mov v0.s[1], w8
+; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    fcvtzs w8, d2
-; CHECK-NEXT:    csel w9, wzr, w9, vs
-; CHECK-NEXT:    fcmp d3, d3
+; CHECK-NEXT:    fcvtzs w9, d1
+; CHECK-NEXT:    mov d1, v1.d[1]
+; CHECK-NEXT:    mov v0.s[1], w8
 ; CHECK-NEXT:    mov v0.s[2], w9
-; CHECK-NEXT:    csel w8, wzr, w8, vs
+; CHECK-NEXT:    fcvtzs w8, d1
 ; CHECK-NEXT:    mov v0.s[3], w8
 ; CHECK-NEXT:    ret
     %x = call <4 x i32> @llvm.fptosi.sat.v4f64.v4i32(<4 x double> %f)
     ret <4 x i32> %x
 }
 
 define <5 x i32> @test_signed_v5f64_v5i32(<5 x double> %f) {
 ; CHECK-LABEL: test_signed_v5f64_v5i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #-4476578029606273024
-; CHECK-NEXT:    mov x9, #281474972516352
-; CHECK-NEXT:    movk x9, #16863, lsl #48
-; CHECK-NEXT:    fmov d5, x8
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    fmaxnm d0, d0, d5
-; CHECK-NEXT:    fmov d6, x9
-; CHECK-NEXT:    fmaxnm d7, d1, d5
-; CHECK-NEXT:    fminnm d0, d0, d6
-; CHECK-NEXT:    fmaxnm d16, d2, d5
-; CHECK-NEXT:    fminnm d7, d7, d6
-; CHECK-NEXT:    fcvtzs w8, d0
-; CHECK-NEXT:    fmaxnm d17, d3, d5
-; CHECK-NEXT:    fminnm d16, d16, d6
-; CHECK-NEXT:    fcvtzs w9, d7
-; CHECK-NEXT:    csel w0, wzr, w8, vs
-; CHECK-NEXT:    fcmp d1, d1
-; CHECK-NEXT:    fmaxnm d5, d4, d5
-; CHECK-NEXT:    fminnm d17, d17, d6
-; CHECK-NEXT:    fcvtzs w10, d16
-; CHECK-NEXT:    csel w1, wzr, w9, vs
-; CHECK-NEXT:    fcmp d2, d2
-; CHECK-NEXT:    fminnm d5, d5, d6
-; CHECK-NEXT:    fcvtzs w11, d17
-; CHECK-NEXT:    csel w2, wzr, w10, vs
-; CHECK-NEXT:    fcmp d3, d3
-; CHECK-NEXT:    fcvtzs w12, d5
-; CHECK-NEXT:    csel w3, wzr, w11, vs
-; CHECK-NEXT:    fcmp d4, d4
-; CHECK-NEXT:    csel w4, wzr, w12, vs
+; CHECK-NEXT:    fcvtzs w0, d0
+; CHECK-NEXT:    fcvtzs w1, d1
+; CHECK-NEXT:    fcvtzs w2, d2
+; CHECK-NEXT:    fcvtzs w3, d3
+; CHECK-NEXT:    fcvtzs w4, d4
 ; CHECK-NEXT:    ret
     %x = call <5 x i32> @llvm.fptosi.sat.v5f64.v5i32(<5 x double> %f)
     ret <5 x i32> %x
 }
 
 define <6 x i32> @test_signed_v6f64_v6i32(<6 x double> %f) {
 ; CHECK-LABEL: test_signed_v6f64_v6i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #-4476578029606273024
-; CHECK-NEXT:    mov x9, #281474972516352
-; CHECK-NEXT:    movk x9, #16863, lsl #48
-; CHECK-NEXT:    fmov d6, x8
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    fmaxnm d0, d0, d6
-; CHECK-NEXT:    fmov d7, x9
-; CHECK-NEXT:    fmaxnm d16, d1, d6
-; CHECK-NEXT:    fminnm d0, d0, d7
-; CHECK-NEXT:    fmaxnm d17, d2, d6
-; CHECK-NEXT:    fminnm d16, d16, d7
-; CHECK-NEXT:    fcvtzs w8, d0
-; CHECK-NEXT:    fmaxnm d18, d3, d6
-; CHECK-NEXT:    fminnm d17, d17, d7
-; CHECK-NEXT:    fcvtzs w9, d16
-; CHECK-NEXT:    csel w0, wzr, w8, vs
-; CHECK-NEXT:    fcmp d1, d1
-; CHECK-NEXT:    fmaxnm d19, d4, d6
-; CHECK-NEXT:    fminnm d18, d18, d7
-; CHECK-NEXT:    fcvtzs w10, d17
-; CHECK-NEXT:    csel w1, wzr, w9, vs
-; CHECK-NEXT:    fcmp d2, d2
-; CHECK-NEXT:    fmaxnm d6, d5, d6
-; CHECK-NEXT:    fminnm d19, d19, d7
-; CHECK-NEXT:    fcvtzs w11, d18
-; CHECK-NEXT:    csel w2, wzr, w10, vs
-; CHECK-NEXT:    fcmp d3, d3
-; CHECK-NEXT:    fminnm d6, d6, d7
-; CHECK-NEXT:    fcvtzs w12, d19
-; CHECK-NEXT:    csel w3, wzr, w11, vs
-; CHECK-NEXT:    fcmp d4, d4
-; CHECK-NEXT:    fcvtzs w13, d6
-; CHECK-NEXT:    csel w4, wzr, w12, vs
-; CHECK-NEXT:    fcmp d5, d5
-; CHECK-NEXT:    csel w5, wzr, w13, vs
+; CHECK-NEXT:    fcvtzs w0, d0
+; CHECK-NEXT:    fcvtzs w1, d1
+; CHECK-NEXT:    fcvtzs w2, d2
+; CHECK-NEXT:    fcvtzs w3, d3
+; CHECK-NEXT:    fcvtzs w4, d4
+; CHECK-NEXT:    fcvtzs w5, d5
 ; CHECK-NEXT:    ret
     %x = call <6 x i32> @llvm.fptosi.sat.v6f64.v6i32(<6 x double> %f)
     ret <6 x i32> %x
 }
 
 ;
 ; FP128 to signed 32-bit -- Vector size variation
 ;

 declare <5 x i32> @llvm.fptosi.sat.v5f16.v5i32 (<5 x half>)
 declare <6 x i32> @llvm.fptosi.sat.v6f16.v6i32 (<6 x half>)
 declare <7 x i32> @llvm.fptosi.sat.v7f16.v7i32 (<7 x half>)
 declare <8 x i32> @llvm.fptosi.sat.v8f16.v8i32 (<8 x half>)
 
 define <1 x i32> @test_signed_v1f16_v1i32(<1 x half> %f) {
 ; CHECK-LABEL: test_signed_v1f16_v1i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-822083584
 ; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    mov w8, #1325400063
-; CHECK-NEXT:    mov w9, #-2147483648
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    fmov s1, w8
 ; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    mov w9, #2147483647
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    csel w8, w9, w8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w8, wzr, w8, vs
 ; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    ret
     %x = call <1 x i32> @llvm.fptosi.sat.v1f16.v1i32(<1 x half> %f)
     ret <1 x i32> %x
 }
 
 define <2 x i32> @test_signed_v2f16_v2i32(<2 x half> %f) {
 ; CHECK-LABEL: test_signed_v2f16_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    mov w8, #-822083584
-; CHECK-NEXT:    mov w10, #1325400063
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    mov w9, #-2147483648
-; CHECK-NEXT:    fmov s3, w10
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    mov w11, #2147483647
-; CHECK-NEXT:    csel w10, w9, w10, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    csel w10, w11, w10, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    fcmp s0, s3
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w8, wzr, w8, vs
+; CHECK-NEXT:    fcvt s1, h0
+; CHECK-NEXT:    mov h0, v0.h[1]
+; CHECK-NEXT:    fcvtzs w8, s1
+; CHECK-NEXT:    fcvt s1, h0
 ; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    mov v0.s[1], w10
+; CHECK-NEXT:    fcvtzs w8, s1
+; CHECK-NEXT:    mov v0.s[1], w8
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
 ; CHECK-NEXT:    ret
     %x = call <2 x i32> @llvm.fptosi.sat.v2f16.v2i32(<2 x half> %f)
     ret <2 x i32> %x
 }
 
 define <3 x i32> @test_signed_v3f16_v3i32(<3 x half> %f) {
 ; CHECK-LABEL: test_signed_v3f16_v3i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    mov w8, #-822083584
-; CHECK-NEXT:    mov w10, #1325400063
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fmov s3, w8
-; CHECK-NEXT:    mov w9, #-2147483648
-; CHECK-NEXT:    fmov s4, w10
+; CHECK-NEXT:    fcvt s1, h0
+; CHECK-NEXT:    mov h2, v0.h[1]
 ; CHECK-NEXT:    fcvtzs w8, s1
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    mov w11, #2147483647
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs w10, s2
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    csel w10, w9, w10, lt
-; CHECK-NEXT:    fcmp s2, s4
-; CHECK-NEXT:    mov h1, v0.h[2]
-; CHECK-NEXT:    csel w10, w11, w10, gt
-; CHECK-NEXT:    fcmp s2, s2
+; CHECK-NEXT:    fcvt s2, h2
+; CHECK-NEXT:    fmov s1, w8
+; CHECK-NEXT:    fcvtzs w8, s2
+; CHECK-NEXT:    mov h2, v0.h[2]
 ; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    fmov s0, w10
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    csel w10, w9, w10, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    csel w10, w11, w10, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    mov v0.s[1], w8
+; CHECK-NEXT:    fcvt s2, h2
+; CHECK-NEXT:    fcvt s0, h0
+; CHECK-NEXT:    mov v1.s[1], w8
 ; CHECK-NEXT:    fcvtzs w8, s2
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    fcmp s2, s4
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s2, s2
-; CHECK-NEXT:    mov v0.s[2], w10
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    mov v0.s[3], w8
+; CHECK-NEXT:    mov v1.s[2], w8
+; CHECK-NEXT:    fcvtzs w8, s0
+; CHECK-NEXT:    mov v1.s[3], w8
+; CHECK-NEXT:    mov v0.16b, v1.16b
 ; CHECK-NEXT:    ret
     %x = call <3 x i32> @llvm.fptosi.sat.v3f16.v3i32(<3 x half> %f)
     ret <3 x i32> %x
 }
 
 define <4 x i32> @test_signed_v4f16_v4i32(<4 x half> %f) {
 ; CHECK-LABEL: test_signed_v4f16_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    mov w8, #-822083584
-; CHECK-NEXT:    mov w10, #1325400063
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fmov s3, w8
-; CHECK-NEXT:    mov w9, #-2147483648
-; CHECK-NEXT:    fmov s4, w10
+; CHECK-NEXT:    fcvt s1, h0
+; CHECK-NEXT:    mov h2, v0.h[1]
 ; CHECK-NEXT:    fcvtzs w8, s1
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    mov w11, #2147483647
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs w10, s2
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    csel w10, w9, w10, lt
-; CHECK-NEXT:    fcmp s2, s4
-; CHECK-NEXT:    mov h1, v0.h[2]
-; CHECK-NEXT:    csel w10, w11, w10, gt
-; CHECK-NEXT:    fcmp s2, s2
+; CHECK-NEXT:    fcvt s2, h2
+; CHECK-NEXT:    fmov s1, w8
+; CHECK-NEXT:    fcvtzs w8, s2
+; CHECK-NEXT:    mov h2, v0.h[2]
 ; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    fmov s0, w10
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    csel w10, w9, w10, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    csel w10, w11, w10, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    mov v0.s[1], w8
+; CHECK-NEXT:    fcvt s2, h2
+; CHECK-NEXT:    fcvt s0, h0
+; CHECK-NEXT:    mov v1.s[1], w8
 ; CHECK-NEXT:    fcvtzs w8, s2
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    fcmp s2, s4
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s2, s2
-; CHECK-NEXT:    mov v0.s[2], w10
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    mov v0.s[3], w8
+; CHECK-NEXT:    mov v1.s[2], w8
+; CHECK-NEXT:    fcvtzs w8, s0
+; CHECK-NEXT:    mov v1.s[3], w8
+; CHECK-NEXT:    mov v0.16b, v1.16b
 ; CHECK-NEXT:    ret
     %x = call <4 x i32> @llvm.fptosi.sat.v4f16.v4i32(<4 x half> %f)
     ret <4 x i32> %x
 }
 
 define <5 x i32> @test_signed_v5f16_v5i32(<5 x half> %f) {
 ; CHECK-LABEL: test_signed_v5f16_v5i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-822083584
 ; CHECK-NEXT:    fcvt s1, h0
-; CHECK-NEXT:    mov w10, #1325400063
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    mov w9, #-2147483648
-; CHECK-NEXT:    fcvtzs w12, s1
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    fmov s3, w10
-; CHECK-NEXT:    mov w11, #2147483647
-; CHECK-NEXT:    csel w8, w9, w12, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s1, s1
+; CHECK-NEXT:    fcvtzs w0, s1
+; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT:    fcvt s1, h1
+; CHECK-NEXT:    fcvtzs w4, s1
 ; CHECK-NEXT:    mov h1, v0.h[1]
 ; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    csel w0, wzr, w8, vs
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    csel w8, w9, w10, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s1, s1
+; CHECK-NEXT:    fcvtzs w1, s1
 ; CHECK-NEXT:    mov h1, v0.h[2]
+; CHECK-NEXT:    mov h0, v0.h[3]
 ; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    csel w1, wzr, w8, vs
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    csel w8, w9, w10, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    mov h1, v0.h[3]
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    csel w2, wzr, w8, vs
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT:    csel w8, w9, w10, lt
-; CHECK-NEXT:    fcmp s1, s3
 ; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs w12, s0
-; CHECK-NEXT:    csel w3, wzr, w8, vs
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csel w8, w9, w12, lt
-; CHECK-NEXT:    fcmp s0, s3
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w4, wzr, w8, vs
+; CHECK-NEXT:    fcvtzs w2, s1
+; CHECK-NEXT:    fcvtzs w3, s0
 ; CHECK-NEXT:    ret
     %x = call <5 x i32> @llvm.fptosi.sat.v5f16.v5i32(<5 x half> %f)
     ret <5 x i32> %x
 }
 
 define <6 x i32> @test_signed_v6f16_v6i32(<6 x half> %f) {
 ; CHECK-LABEL: test_signed_v6f16_v6i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT:    mov w8, #-822083584
-; CHECK-NEXT:    mov h2, v1.h[1]
-; CHECK-NEXT:    mov w10, #1325400063
-; CHECK-NEXT:    fmov s3, w8
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    mov w9, #-2147483648
-; CHECK-NEXT:    fmov s4, w10
-; CHECK-NEXT:    fcvtzs w8, s2
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    mov w11, #2147483647
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    fcmp s2, s4
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s2, s2
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    csel w5, wzr, w8, vs
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    csel w8, w9, w10, lt
-; CHECK-NEXT:    fcmp s1, s4
 ; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs w10, s2
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    csel w10, w9, w10, lt
-; CHECK-NEXT:    fcmp s2, s4
-; CHECK-NEXT:    csel w10, w11, w10, gt
-; CHECK-NEXT:    fcmp s2, s2
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvtzs w12, s1
-; CHECK-NEXT:    csel w0, wzr, w10, vs
-; CHECK-NEXT:    fcmp s1, s3
+; CHECK-NEXT:    fcvtzs w0, s2
+; CHECK-NEXT:    fcvt s2, h1
+; CHECK-NEXT:    fcvtzs w8, s2
+; CHECK-NEXT:    mov h2, v0.h[1]
+; CHECK-NEXT:    fcvt s2, h2
+; CHECK-NEXT:    fcvtzs w1, s2
 ; CHECK-NEXT:    mov h2, v0.h[2]
-; CHECK-NEXT:    csel w10, w9, w12, lt
-; CHECK-NEXT:    fcmp s1, s4
+; CHECK-NEXT:    mov h1, v1.h[1]
 ; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    csel w10, w11, w10, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs w13, s2
-; CHECK-NEXT:    csel w1, wzr, w10, vs
-; CHECK-NEXT:    fcmp s2, s3
+; CHECK-NEXT:    fcvt s1, h1
 ; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    csel w10, w9, w13, lt
-; CHECK-NEXT:    fcmp s2, s4
+; CHECK-NEXT:    fcvtzs w2, s2
+; CHECK-NEXT:    fmov s2, w8
+; CHECK-NEXT:    fcvtzs w5, s1
 ; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    csel w10, w11, w10, gt
-; CHECK-NEXT:    fcmp s2, s2
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    csel w2, wzr, w10, vs
-; CHECK-NEXT:    fcmp s0, s3
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    fcmp s0, s4
-; CHECK-NEXT:    mov v1.s[1], w5
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w3, wzr, w8, vs
-; CHECK-NEXT:    fmov w4, s1
+; CHECK-NEXT:    mov v2.s[1], w5
+; CHECK-NEXT:    fcvtzs w3, s0
+; CHECK-NEXT:    fmov w4, s2
 ; CHECK-NEXT:    ret
     %x = call <6 x i32> @llvm.fptosi.sat.v6f16.v6i32(<6 x half> %f)
     ret <6 x i32> %x
 }
 
 define <7 x i32> @test_signed_v7f16_v7i32(<7 x half> %f) {
 ; CHECK-LABEL: test_signed_v7f16_v7i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    ext v3.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT:    mov w10, #-822083584
-; CHECK-NEXT:    mov h4, v3.h[1]
-; CHECK-NEXT:    mov w11, #1325400063
-; CHECK-NEXT:    fmov s2, w10
-; CHECK-NEXT:    fcvt s4, h4
-; CHECK-NEXT:    mov w8, #-2147483648
-; CHECK-NEXT:    fmov s1, w11
-; CHECK-NEXT:    fcvtzs w10, s4
-; CHECK-NEXT:    fcmp s4, s2
-; CHECK-NEXT:    mov w9, #2147483647
-; CHECK-NEXT:    csel w10, w8, w10, lt
-; CHECK-NEXT:    fcmp s4, s1
-; CHECK-NEXT:    csel w10, w9, w10, gt
-; CHECK-NEXT:    fcmp s4, s4
-; CHECK-NEXT:    fcvt s4, h3
-; CHECK-NEXT:    fcvtzs w11, s4
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcmp s4, s2
-; CHECK-NEXT:    csel w11, w8, w11, lt
-; CHECK-NEXT:    fcmp s4, s1
-; CHECK-NEXT:    mov h3, v3.h[2]
-; CHECK-NEXT:    csel w11, w9, w11, gt
-; CHECK-NEXT:    fcmp s4, s4
-; CHECK-NEXT:    fcvt s3, h3
-; CHECK-NEXT:    fcvtzs w12, s3
-; CHECK-NEXT:    csel w11, wzr, w11, vs
-; CHECK-NEXT:    fcmp s3, s2
-; CHECK-NEXT:    csel w12, w8, w12, lt
-; CHECK-NEXT:    fcmp s3, s1
-; CHECK-NEXT:    fcvt s4, h0
-; CHECK-NEXT:    csel w12, w9, w12, gt
-; CHECK-NEXT:    fcmp s3, s3
-; CHECK-NEXT:    fcvtzs w13, s4
-; CHECK-NEXT:    csel w6, wzr, w12, vs
-; CHECK-NEXT:    fcmp s4, s2
+; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT:    fcvt s2, h0
 ; CHECK-NEXT:    mov h3, v0.h[1]
-; CHECK-NEXT:    csel w12, w8, w13, lt
-; CHECK-NEXT:    fcmp s4, s1
-; CHECK-NEXT:    csel w12, w9, w12, gt
-; CHECK-NEXT:    fcmp s4, s4
+; CHECK-NEXT:    fcvtzs w0, s2
+; CHECK-NEXT:    fcvt s2, h1
 ; CHECK-NEXT:    fcvt s3, h3
-; CHECK-NEXT:    fcvtzs w13, s3
-; CHECK-NEXT:    csel w0, wzr, w12, vs
-; CHECK-NEXT:    fcmp s3, s2
-; CHECK-NEXT:    mov h4, v0.h[2]
-; CHECK-NEXT:    csel w12, w8, w13, lt
-; CHECK-NEXT:    fcmp s3, s1
-; CHECK-NEXT:    fcvt s4, h4
-; CHECK-NEXT:    csel w12, w9, w12, gt
-; CHECK-NEXT:    fcmp s3, s3
-; CHECK-NEXT:    fmov s3, w11
-; CHECK-NEXT:    fcvtzs w11, s4
-; CHECK-NEXT:    csel w1, wzr, w12, vs
-; CHECK-NEXT:    fcmp s4, s2
+; CHECK-NEXT:    fcvtzs w8, s2
+; CHECK-NEXT:    mov h2, v0.h[2]
+; CHECK-NEXT:    fcvtzs w1, s3
+; CHECK-NEXT:    mov h3, v1.h[1]
+; CHECK-NEXT:    mov h1, v1.h[2]
+; CHECK-NEXT:    fcvt s2, h2
+; CHECK-NEXT:    fcvt s3, h3
+; CHECK-NEXT:    fcvt s1, h1
+; CHECK-NEXT:    fcvtzs w2, s2
+; CHECK-NEXT:    fmov s2, w8
+; CHECK-NEXT:    fcvtzs w8, s3
 ; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    csel w11, w8, w11, lt
-; CHECK-NEXT:    fcmp s4, s1
+; CHECK-NEXT:    fcvtzs w6, s1
+; CHECK-NEXT:    mov v2.s[1], w8
 ; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    csel w11, w9, w11, gt
-; CHECK-NEXT:    fcmp s4, s4
-; CHECK-NEXT:    mov v3.s[1], w10
-; CHECK-NEXT:    fcvtzs w10, s0
-; CHECK-NEXT:    csel w2, wzr, w11, vs
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csel w8, w8, w10, lt
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    mov v3.s[2], w6
-; CHECK-NEXT:    csel w8, w9, w8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w3, wzr, w8, vs
-; CHECK-NEXT:    mov w5, v3.s[1]
-; CHECK-NEXT:    fmov w4, s3
+; CHECK-NEXT:    mov v2.s[2], w6
+; CHECK-NEXT:    fcvtzs w3, s0
+; CHECK-NEXT:    mov w5, v2.s[1]
+; CHECK-NEXT:    fmov w4, s2
 ; CHECK-NEXT:    ret
     %x = call <7 x i32> @llvm.fptosi.sat.v7f16.v7i32(<7 x half> %f)
     ret <7 x i32> %x
 }
 
 define <8 x i32> @test_signed_v8f16_v8i32(<8 x half> %f) {
 ; CHECK-LABEL: test_signed_v8f16_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    mov w10, #-822083584
-; CHECK-NEXT:    mov w11, #1325400063
+; CHECK-NEXT:    ext v3.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT:    fcvt s1, h0
+; CHECK-NEXT:    fcvtzs w8, s1
+; CHECK-NEXT:    fcvt s1, h3
+; CHECK-NEXT:    mov h2, v0.h[1]
+; CHECK-NEXT:    fcvtzs w9, s1
+; CHECK-NEXT:    mov h1, v0.h[2]
+; CHECK-NEXT:    fcvt s2, h2
 ; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fmov s3, w10
-; CHECK-NEXT:    mov w8, #-2147483648
-; CHECK-NEXT:    fmov s2, w11
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    mov w9, #2147483647
-; CHECK-NEXT:    csel w10, w8, w10, lt
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    fcvt s4, h0
-; CHECK-NEXT:    csel w10, w9, w10, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs w11, s4
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcmp s4, s3
-; CHECK-NEXT:    csel w11, w8, w11, lt
-; CHECK-NEXT:    fcmp s4, s2
-; CHECK-NEXT:    mov h5, v0.h[2]
-; CHECK-NEXT:    csel w11, w9, w11, gt
-; CHECK-NEXT:    fcmp s4, s4
-; CHECK-NEXT:    fcvt s5, h5
-; CHECK-NEXT:    csel w11, wzr, w11, vs
-; CHECK-NEXT:    mov h1, v0.h[3]
-; CHECK-NEXT:    ext v6.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT:    fmov s0, w11
-; CHECK-NEXT:    fcvtzs w11, s5
-; CHECK-NEXT:    fcmp s5, s3
-; CHECK-NEXT:    csel w11, w8, w11, lt
-; CHECK-NEXT:    fcmp s5, s2
+; CHECK-NEXT:    fcvtzs w10, s2
+; CHECK-NEXT:    mov h2, v3.h[1]
+; CHECK-NEXT:    fcvtzs w11, s1
+; CHECK-NEXT:    mov h1, v3.h[2]
+; CHECK-NEXT:    fcvt s2, h2
 ; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    csel w11, w9, w11, gt
-; CHECK-NEXT:    fcmp s5, s5
-; CHECK-NEXT:    mov v0.s[1], w10
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    csel w11, wzr, w11, vs
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    mov h4, v6.h[1]
-; CHECK-NEXT:    csel w10, w8, w10, lt
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    csel w10, w9, w10, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvt s4, h4
-; CHECK-NEXT:    mov v0.s[2], w11
-; CHECK-NEXT:    fcvtzs w11, s4
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcmp s4, s3
-; CHECK-NEXT:    csel w11, w8, w11, lt
-; CHECK-NEXT:    fcmp s4, s2
-; CHECK-NEXT:    fcvt s1, h6
-; CHECK-NEXT:    csel w11, w9, w11, gt
-; CHECK-NEXT:    fcmp s4, s4
-; CHECK-NEXT:    mov v0.s[3], w10
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    csel w11, wzr, w11, vs
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    csel w10, w8, w10, lt
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    mov h4, v6.h[2]
-; CHECK-NEXT:    csel w10, w9, w10, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvt s4, h4
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fmov s1, w10
-; CHECK-NEXT:    fcvtzs w10, s4
-; CHECK-NEXT:    fcmp s4, s3
-; CHECK-NEXT:    mov h5, v6.h[3]
-; CHECK-NEXT:    csel w10, w8, w10, lt
-; CHECK-NEXT:    fcmp s4, s2
-; CHECK-NEXT:    fcvt s5, h5
-; CHECK-NEXT:    csel w10, w9, w10, gt
-; CHECK-NEXT:    fcmp s4, s4
-; CHECK-NEXT:    mov v1.s[1], w11
-; CHECK-NEXT:    fcvtzs w11, s5
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcmp s5, s3
-; CHECK-NEXT:    csel w8, w8, w11, lt
-; CHECK-NEXT:    fcmp s5, s2
-; CHECK-NEXT:    csel w8, w9, w8, gt
-; CHECK-NEXT:    fcmp s5, s5
-; CHECK-NEXT:    mov v1.s[2], w10
-; CHECK-NEXT:    csel w8, wzr, w8, vs
+; CHECK-NEXT:    fcvtzs w12, s2
+; CHECK-NEXT:    fmov s2, w8
+; CHECK-NEXT:    fcvtzs w8, s1
+; CHECK-NEXT:    fmov s1, w9
+; CHECK-NEXT:    mov h3, v3.h[3]
+; CHECK-NEXT:    mov v1.s[1], w12
+; CHECK-NEXT:    mov h0, v0.h[3]
+; CHECK-NEXT:    fcvt s3, h3
+; CHECK-NEXT:    mov v2.s[1], w10
+; CHECK-NEXT:    fcvt s0, h0
+; CHECK-NEXT:    mov v1.s[2], w8
+; CHECK-NEXT:    fcvtzs w8, s3
+; CHECK-NEXT:    mov v2.s[2], w11
 ; CHECK-NEXT:    mov v1.s[3], w8
+; CHECK-NEXT:    fcvtzs w8, s0
+; CHECK-NEXT:    mov v2.s[3], w8
+; CHECK-NEXT:    mov v0.16b, v2.16b
 ; CHECK-NEXT:    ret
     %x = call <8 x i32> @llvm.fptosi.sat.v8f16.v8i32(<8 x half> %f)
     ret <8 x i32> %x
 }
 
 ;
 ; 2-Vector float to signed integer -- result size variation
 ;

 ; CHECK-NEXT:    ret
     %x = call <2 x i19> @llvm.fptosi.sat.v2f32.v2i19(<2 x float> %f)
     ret <2 x i19> %x
 }
 
 define <2 x i32> @test_signed_v2f32_v2i32_duplicate(<2 x float> %f) {
 ; CHECK-LABEL: test_signed_v2f32_v2i32_duplicate:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-822083584
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    mov w10, #1325400063
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    mov w9, #-2147483648
-; CHECK-NEXT:    fmov s3, w10
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    mov w11, #2147483647
-; CHECK-NEXT:    csel w10, w9, w10, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    csel w10, w11, w10, gt
-; CHECK-NEXT:    fcmp s1, s1
 ; CHECK-NEXT:    fcvtzs w8, s0
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    fcmp s0, s3
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel w8, wzr, w8, vs
+; CHECK-NEXT:    mov s1, v0.s[1]
 ; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    mov v0.s[1], w10
+; CHECK-NEXT:    fcvtzs w8, s1
+; CHECK-NEXT:    mov v0.s[1], w8
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
 ; CHECK-NEXT:    ret
     %x = call <2 x i32> @llvm.fptosi.sat.v2f32.v2i32(<2 x float> %f)
     ret <2 x i32> %x
 }
 
 define <2 x i50> @test_signed_v2f32_v2i50(<2 x float> %f) {
 ; CHECK-LABEL: test_signed_v2f32_v2i50:

 ; CHECK-NEXT:    ret
     %x = call <2 x i50> @llvm.fptosi.sat.v2f32.v2i50(<2 x float> %f)
     ret <2 x i50> %x
 }
 
 define <2 x i64> @test_signed_v2f32_v2i64(<2 x float> %f) {
 ; CHECK-LABEL: test_signed_v2f32_v2i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-553648128
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    mov w10, #1593835519
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    mov x9, #-9223372036854775808
-; CHECK-NEXT:    fmov s3, w10
-; CHECK-NEXT:    fcvtzs x10, s1
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    mov x11, #9223372036854775807
-; CHECK-NEXT:    csel x10, x9, x10, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    csel x10, x11, x10, gt
-; CHECK-NEXT:    fcmp s1, s1
 ; CHECK-NEXT:    fcvtzs x8, s0
-; CHECK-NEXT:    csel x10, xzr, x10, vs
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csel x8, x9, x8, lt
-; CHECK-NEXT:    fcmp s0, s3
-; CHECK-NEXT:    csel x8, x11, x8, gt
-; CHECK-NEXT:    fcmp s0, s0
-; CHECK-NEXT:    csel x8, xzr, x8, vs
+; CHECK-NEXT:    mov s1, v0.s[1]
 ; CHECK-NEXT:    fmov d0, x8
-; CHECK-NEXT:    mov v0.d[1], x10
+; CHECK-NEXT:    fcvtzs x8, s1
+; CHECK-NEXT:    mov v0.d[1], x8
 ; CHECK-NEXT:    ret
     %x = call <2 x i64> @llvm.fptosi.sat.v2f32.v2i64(<2 x float> %f)
     ret <2 x i64> %x
 }
 
 define <2 x i100> @test_signed_v2f32_v2i100(<2 x float> %f) {
 ; CHECK-LABEL: test_signed_v2f32_v2i100:
 ; CHECK:       // %bb.0:

 ; CHECK-NEXT:    ret
     %x = call <2 x i19> @llvm.fptosi.sat.v2f64.v2i19(<2 x double> %f)
     ret <2 x i19> %x
 }
 
 define <2 x i32> @test_signed_v2f64_v2i32_duplicate(<2 x double> %f) {
 ; CHECK-LABEL: test_signed_v2f64_v2i32_duplicate:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #-4476578029606273024
-; CHECK-NEXT:    mov x9, #281474972516352
+; CHECK-NEXT:    fcvtzs w8, d0
 ; CHECK-NEXT:    mov d1, v0.d[1]
-; CHECK-NEXT:    movk x9, #16863, lsl #48
-; CHECK-NEXT:    fmov d2, x8
-; CHECK-NEXT:    fmaxnm d3, d1, d2
-; CHECK-NEXT:    fmov d4, x9
-; CHECK-NEXT:    fcmp d1, d1
-; CHECK-NEXT:    fmaxnm d1, d0, d2
-; CHECK-NEXT:    fminnm d2, d3, d4
-; CHECK-NEXT:    fminnm d1, d1, d4
-; CHECK-NEXT:    fcvtzs w8, d2
-; CHECK-NEXT:    fcvtzs w9, d1
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    csel w9, wzr, w9, vs
-; CHECK-NEXT:    fmov s0, w9
+; CHECK-NEXT:    fmov s0, w8
+; CHECK-NEXT:    fcvtzs w8, d1
 ; CHECK-NEXT:    mov v0.s[1], w8
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
 ; CHECK-NEXT:    ret
     %x = call <2 x i32> @llvm.fptosi.sat.v2f64.v2i32(<2 x double> %f)
     ret <2 x i32> %x
 }
 
 define <2 x i50> @test_signed_v2f64_v2i50(<2 x double> %f) {

 ; CHECK-NEXT:    ret
     %x = call <2 x i50> @llvm.fptosi.sat.v2f64.v2i50(<2 x double> %f)
     ret <2 x i50> %x
 }
 
 define <2 x i64> @test_signed_v2f64_v2i64(<2 x double> %f) {
 ; CHECK-LABEL: test_signed_v2f64_v2i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #-4332462841530417152
-; CHECK-NEXT:    mov d1, v0.d[1]
-; CHECK-NEXT:    mov x10, #4890909195324358655
-; CHECK-NEXT:    fmov d2, x8
-; CHECK-NEXT:    mov x9, #-9223372036854775808
-; CHECK-NEXT:    fmov d3, x10
-; CHECK-NEXT:    fcvtzs x10, d1
-; CHECK-NEXT:    fcmp d1, d2
-; CHECK-NEXT:    mov x11, #9223372036854775807
-; CHECK-NEXT:    csel x10, x9, x10, lt
-; CHECK-NEXT:    fcmp d1, d3
-; CHECK-NEXT:    csel x10, x11, x10, gt
-; CHECK-NEXT:    fcmp d1, d1
 ; CHECK-NEXT:    fcvtzs x8, d0
-; CHECK-NEXT:    csel x10, xzr, x10, vs
-; CHECK-NEXT:    fcmp d0, d2
-; CHECK-NEXT:    csel x8, x9, x8, lt
-; CHECK-NEXT:    fcmp d0, d3
-; CHECK-NEXT:    csel x8, x11, x8, gt
-; CHECK-NEXT:    fcmp d0, d0
-; CHECK-NEXT:    csel x8, xzr, x8, vs
+; CHECK-NEXT:    mov d1, v0.d[1]
 ; CHECK-NEXT:    fmov d0, x8
-; CHECK-NEXT:    mov v0.d[1], x10
+; CHECK-NEXT:    fcvtzs x8, d1
+; CHECK-NEXT:    mov v0.d[1], x8
 ; CHECK-NEXT:    ret
     %x = call <2 x i64> @llvm.fptosi.sat.v2f64.v2i64(<2 x double> %f)
     ret <2 x i64> %x
 }
 
 define <2 x i100> @test_signed_v2f64_v2i100(<2 x double> %f) {
 ; CHECK-LABEL: test_signed_v2f64_v2i100:
 ; CHECK:       // %bb.0:
; CHECK-NEXT:    ret
     %x = call <4 x i19> @llvm.fptosi.sat.v4f16.v4i19(<4 x half> %f)
     ret <4 x i19> %x
 }
 
 define <4 x i32> @test_signed_v4f16_v4i32_duplicate(<4 x half> %f) {
 ; CHECK-LABEL: test_signed_v4f16_v4i32_duplicate:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    mov w8, #-822083584
-; CHECK-NEXT:    mov w10, #1325400063
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fmov s3, w8
-; CHECK-NEXT:    mov w9, #-2147483648
-; CHECK-NEXT:    fmov s4, w10
+; CHECK-NEXT:    fcvt s1, h0
+; CHECK-NEXT:    mov h2, v0.h[1]
 ; CHECK-NEXT:    fcvtzs w8, s1
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    mov w11, #2147483647
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs w10, s2
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    csel w10, w9, w10, lt
-; CHECK-NEXT:    fcmp s2, s4
-; CHECK-NEXT:    mov h1, v0.h[2]
-; CHECK-NEXT:    csel w10, w11, w10, gt
-; CHECK-NEXT:    fcmp s2, s2
+; CHECK-NEXT:    fcvt s2, h2
+; CHECK-NEXT:    fmov s1, w8
+; CHECK-NEXT:    fcvtzs w8, s2
+; CHECK-NEXT:    mov h2, v0.h[2]
 ; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    fmov s0, w10
-; CHECK-NEXT:    fcvtzs w10, s1
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    csel w10, w9, w10, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    csel w10, w11, w10, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    mov v0.s[1], w8
+; CHECK-NEXT:    fcvt s2, h2
+; CHECK-NEXT:    fcvt s0, h0
+; CHECK-NEXT:    mov v1.s[1], w8
 ; CHECK-NEXT:    fcvtzs w8, s2
-; CHECK-NEXT:    csel w10, wzr, w10, vs
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    csel w8, w9, w8, lt
-; CHECK-NEXT:    fcmp s2, s4
-; CHECK-NEXT:    csel w8, w11, w8, gt
-; CHECK-NEXT:    fcmp s2, s2
-; CHECK-NEXT:    mov v0.s[2], w10
-; CHECK-NEXT:    csel w8, wzr, w8, vs
-; CHECK-NEXT:    mov v0.s[3], w8
+; CHECK-NEXT:    mov v1.s[2], w8
+; CHECK-NEXT:    fcvtzs w8, s0
+; CHECK-NEXT:    mov v1.s[3], w8
+; CHECK-NEXT:    mov v0.16b, v1.16b
 ; CHECK-NEXT:    ret
     %x = call <4 x i32> @llvm.fptosi.sat.v4f16.v4i32(<4 x half> %f)
     ret <4 x i32> %x
 }
 
 define <4 x i50> @test_signed_v4f16_v4i50(<4 x half> %f) {
 ; CHECK-LABEL: test_signed_v4f16_v4i50:
 ; CHECK:       // %bb.0:
; CHECK-NEXT:    ret
     %x = call <4 x i50> @llvm.fptosi.sat.v4f16.v4i50(<4 x half> %f)
     ret <4 x i50> %x
 }
 
 define <4 x i64> @test_signed_v4f16_v4i64(<4 x half> %f) {
 ; CHECK-LABEL: test_signed_v4f16_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    mov w8, #-553648128
-; CHECK-NEXT:    mov w10, #1593835519
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fmov s3, w8
-; CHECK-NEXT:    mov x9, #-9223372036854775808
-; CHECK-NEXT:    fmov s4, w10
+; CHECK-NEXT:    fcvt s1, h0
+; CHECK-NEXT:    mov h2, v0.h[1]
 ; CHECK-NEXT:    fcvtzs x8, s1
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    mov x11, #9223372036854775807
-; CHECK-NEXT:    csel x8, x9, x8, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    csel x8, x11, x8, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fcvtzs x10, s2
-; CHECK-NEXT:    csel x8, xzr, x8, vs
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    mov h1, v0.h[3]
-; CHECK-NEXT:    csel x10, x9, x10, lt
-; CHECK-NEXT:    fcmp s2, s4
+; CHECK-NEXT:    fcvt s1, h2
+; CHECK-NEXT:    fmov d2, x8
+; CHECK-NEXT:    fcvtzs x8, s1
+; CHECK-NEXT:    mov h1, v0.h[2]
+; CHECK-NEXT:    mov h0, v0.h[3]
 ; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    csel x10, x11, x10, gt
-; CHECK-NEXT:    fcmp s2, s2
-; CHECK-NEXT:    csel x10, xzr, x10, vs
-; CHECK-NEXT:    fcvtzs x12, s1
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    mov h0, v0.h[2]
-; CHECK-NEXT:    csel x12, x9, x12, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    fcvt s5, h0
-; CHECK-NEXT:    csel x12, x11, x12, gt
-; CHECK-NEXT:    fcmp s1, s1
-; CHECK-NEXT:    fmov d0, x10
-; CHECK-NEXT:    fcvtzs x10, s5
-; CHECK-NEXT:    csel x12, xzr, x12, vs
-; CHECK-NEXT:    fcmp s5, s3
-; CHECK-NEXT:    csel x9, x9, x10, lt
-; CHECK-NEXT:    fcmp s5, s4
-; CHECK-NEXT:    csel x9, x11, x9, gt
-; CHECK-NEXT:    fcmp s5, s5
-; CHECK-NEXT:    csel x9, xzr, x9, vs
-; CHECK-NEXT:    fmov d1, x9
-; CHECK-NEXT:    mov v0.d[1], x8
-; CHECK-NEXT:    mov v1.d[1], x12
+; CHECK-NEXT:    mov v2.d[1], x8
+; CHECK-NEXT:    fcvtzs x8, s1
+; CHECK-NEXT:    fcvt s0, h0
+; CHECK-NEXT:    fmov d1, x8
+; CHECK-NEXT:    fcvtzs x8, s0
+; CHECK-NEXT:    mov v1.d[1], x8
+; CHECK-NEXT:    mov v0.16b, v2.16b
 ; CHECK-NEXT:    ret
     %x = call <4 x i64> @llvm.fptosi.sat.v4f16.v4i64(<4 x half> %f)
     ret <4 x i64> %x
 }
 
 define <4 x i100> @test_signed_v4f16_v4i100(<4 x half> %f) {
 ; CHECK-LABEL: test_signed_v4f16_v4i100:
 ; CHECK:       // %bb.0:

llvm/test/CodeGen/AArch64/fptoui-sat-scalar.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-CVT
+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
 
 ;
 ; 32-bit float to unsigned integer
 ;
 
 declare   i1 @llvm.fptoui.sat.i1.f32  (float)
 declare   i8 @llvm.fptoui.sat.i8.f32  (float)
 declare  i13 @llvm.fptoui.sat.i13.f32 (float)

 ; CHECK-NEXT:    ret
     %x = call i19 @llvm.fptoui.sat.i19.f32(float %f)
     ret i19 %x
 }
 
 define i32 @test_unsigned_i32_f32(float %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i32_f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w9, #1333788671
-; CHECK-NEXT:    fcvtzu w8, s0
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    fmov s1, w9
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    csinv w0, w8, wzr, le
+; CHECK-NEXT:    fcvtzu w0, s0
 ; CHECK-NEXT:    ret
     %x = call i32 @llvm.fptoui.sat.i32.f32(float %f)
     ret i32 %x
 }
 
 define i50 @test_unsigned_i50_f32(float %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i50_f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w9, #1484783615
 ; CHECK-NEXT:    fcvtzu x8, s0
 ; CHECK-NEXT:    fcmp s0, #0.0
 ; CHECK-NEXT:    fmov s1, w9
 ; CHECK-NEXT:    csel x8, xzr, x8, lt
 ; CHECK-NEXT:    fcmp s0, s1
 ; CHECK-NEXT:    mov x9, #1125899906842623
 ; CHECK-NEXT:    csel x0, x9, x8, gt
 ; CHECK-NEXT:    ret
     %x = call i50 @llvm.fptoui.sat.i50.f32(float %f)
     ret i50 %x
 }
 
 define i64 @test_unsigned_i64_f32(float %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i64_f32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w9, #1602224127
-; CHECK-NEXT:    fcvtzu x8, s0
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    fmov s1, w9
-; CHECK-NEXT:    csel x8, xzr, x8, lt
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    csinv x0, x8, xzr, le
+; CHECK-NEXT:    fcvtzu x0, s0
 ; CHECK-NEXT:    ret
     %x = call i64 @llvm.fptoui.sat.i64.f32(float %f)
     ret i64 %x
 }
 
 define i100 @test_unsigned_i100_f32(float %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i100_f32:
 ; CHECK:       // %bb.0:

 ; CHECK-NEXT:    ret
     %x = call i19 @llvm.fptoui.sat.i19.f64(double %f)
     ret i19 %x
 }
 
 define i32 @test_unsigned_i32_f64(double %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i32_f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #281474974613504
-; CHECK-NEXT:    movi d1, #0000000000000000
-; CHECK-NEXT:    movk x8, #16879, lsl #48
-; CHECK-NEXT:    fmaxnm d0, d0, d1
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fminnm d0, d0, d1
 ; CHECK-NEXT:    fcvtzu w0, d0
 ; CHECK-NEXT:    ret
     %x = call i32 @llvm.fptoui.sat.i32.f64(double %f)
     ret i32 %x
 }
 
 define i50 @test_unsigned_i50_f64(double %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i50_f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov x8, #-8
 ; CHECK-NEXT:    movi d1, #0000000000000000
 ; CHECK-NEXT:    movk x8, #17167, lsl #48
 ; CHECK-NEXT:    fmaxnm d0, d0, d1
 ; CHECK-NEXT:    fmov d1, x8
 ; CHECK-NEXT:    fminnm d0, d0, d1
 ; CHECK-NEXT:    fcvtzu x0, d0
 ; CHECK-NEXT:    ret
     %x = call i50 @llvm.fptoui.sat.i50.f64(double %f)
     ret i50 %x
 }
 
 define i64 @test_unsigned_i64_f64(double %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i64_f64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x9, #4895412794951729151
-; CHECK-NEXT:    fcvtzu x8, d0
-; CHECK-NEXT:    fcmp d0, #0.0
-; CHECK-NEXT:    fmov d1, x9
-; CHECK-NEXT:    csel x8, xzr, x8, lt
-; CHECK-NEXT:    fcmp d0, d1
-; CHECK-NEXT:    csinv x0, x8, xzr, le
+; CHECK-NEXT:    fcvtzu x0, d0
 ; CHECK-NEXT:    ret
     %x = call i64 @llvm.fptoui.sat.i64.f64(double %f)
     ret i64 %x
 }
 
 define i100 @test_unsigned_i100_f64(double %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i100_f64:
 ; CHECK:       // %bb.0:

 ; CHECK-NEXT:    fminnm s0, s0, s1
 ; CHECK-NEXT:    fcvtzu w0, s0
 ; CHECK-NEXT:    ret
     %x = call i19 @llvm.fptoui.sat.i19.f16(half %f)
     ret i19 %x
 }
 
 define i32 @test_unsigned_i32_f16(half %f) nounwind {
-; CHECK-LABEL: test_unsigned_i32_f16:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    mov w8, #1333788671
-; CHECK-NEXT:    fcvtzu w9, s0
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    csel w8, wzr, w9, lt
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    csinv w0, w8, wzr, le
-; CHECK-NEXT:    ret
+; CHECK-CVT-LABEL: test_unsigned_i32_f16:
+; CHECK-CVT:       // %bb.0:
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    fcvtzu w0, s0
+; CHECK-CVT-NEXT:    ret
+;
+; CHECK-FP16-LABEL: test_unsigned_i32_f16:
+; CHECK-FP16:       // %bb.0:
+; CHECK-FP16-NEXT:    fcvtzu w0, h0
+; CHECK-FP16-NEXT:    ret
     %x = call i32 @llvm.fptoui.sat.i32.f16(half %f)
     ret i32 %x
 }
 
 define i50 @test_unsigned_i50_f16(half %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i50_f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvt s0, h0
 ; CHECK-NEXT:    mov w8, #1484783615
 ; CHECK-NEXT:    fcvtzu x9, s0
 ; CHECK-NEXT:    fcmp s0, #0.0
 ; CHECK-NEXT:    fmov s1, w8
 ; CHECK-NEXT:    csel x8, xzr, x9, lt
 ; CHECK-NEXT:    fcmp s0, s1
 ; CHECK-NEXT:    mov x9, #1125899906842623
 ; CHECK-NEXT:    csel x0, x9, x8, gt
 ; CHECK-NEXT:    ret
     %x = call i50 @llvm.fptoui.sat.i50.f16(half %f)
     ret i50 %x
 }
 
 define i64 @test_unsigned_i64_f16(half %f) nounwind {
-; CHECK-LABEL: test_unsigned_i64_f16:
-; CHECK:       // %bb.0:
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    mov w8, #1602224127
-; CHECK-NEXT:    fcvtzu x9, s0
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    csel x8, xzr, x9, lt
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    csinv x0, x8, xzr, le
-; CHECK-NEXT:    ret
+; CHECK-CVT-LABEL: test_unsigned_i64_f16:
+; CHECK-CVT:       // %bb.0:
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    fcvtzu x0, s0
+; CHECK-CVT-NEXT:    ret
+;
+; CHECK-FP16-LABEL: test_unsigned_i64_f16:
+; CHECK-FP16:       // %bb.0:
+; CHECK-FP16-NEXT:    fcvtzu x0, h0
+; CHECK-FP16-NEXT:    ret
     %x = call i64 @llvm.fptoui.sat.i64.f16(half %f)
     ret i64 %x
 }
 
 define i100 @test_unsigned_i100_f16(half %f) nounwind {
 ; CHECK-LABEL: test_unsigned_i100_f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str d8, [sp, #-16]! // 8-byte Folded Spill

llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll

 declare <6 x i32> @llvm.fptoui.sat.v6f32.v6i32 (<6 x float>)
 declare <7 x i32> @llvm.fptoui.sat.v7f32.v7i32 (<7 x float>)
 declare <8 x i32> @llvm.fptoui.sat.v8f32.v8i32 (<8 x float>)
 
 define <1 x i32> @test_unsigned_v1f32_v1i32(<1 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v1f32_v1i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    fcvtzu w8, s0
 ; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    mov w8, #1333788671
-; CHECK-NEXT:    fmov s2, w8
+; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    fcvtzu w9, s0
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    fmov s0, w9
 ; CHECK-NEXT:    mov v0.s[1], w8
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
 ; CHECK-NEXT:    ret
     %x = call <1 x i32> @llvm.fptoui.sat.v1f32.v1i32(<1 x float> %f)
     ret <1 x i32> %x
 }
 
 define <2 x i32> @test_unsigned_v2f32_v2i32(<2 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v2f32_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    fcvtzu w8, s0
 ; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    mov w8, #1333788671
-; CHECK-NEXT:    fmov s2, w8
+; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    fcvtzu w9, s0
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    fmov s0, w9
 ; CHECK-NEXT:    mov v0.s[1], w8
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
 ; CHECK-NEXT:    ret
     %x = call <2 x i32> @llvm.fptoui.sat.v2f32.v2i32(<2 x float> %f)
     ret <2 x i32> %x
 }
 
 define <3 x i32> @test_unsigned_v3f32_v3i32(<3 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v3f32_v3i32:
 ; CHECK:       // %bb.0:
+; CHECK-NEXT:    fcvtzu w8, s0
 ; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    mov w8, #1333788671
-; CHECK-NEXT:    fmov s3, w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    fcvtzu w9, s0
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s0, s3
 ; CHECK-NEXT:    mov s2, v0.s[2]
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    mov s1, v0.s[3]
-; CHECK-NEXT:    fmov s0, w9
+; CHECK-NEXT:    mov s3, v0.s[3]
+; CHECK-NEXT:    fmov s0, w8
+; CHECK-NEXT:    fcvtzu w8, s1
 ; CHECK-NEXT:    fcvtzu w9, s2
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s2, s3
 ; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s1, s3
 ; CHECK-NEXT:    mov v0.s[2], w9
-; CHECK-NEXT:    csinv w8, w8, wzr, le
+; CHECK-NEXT:    fcvtzu w8, s3
 ; CHECK-NEXT:    mov v0.s[3], w8
 ; CHECK-NEXT:    ret
     %x = call <3 x i32> @llvm.fptoui.sat.v3f32.v3i32(<3 x float> %f)
     ret <3 x i32> %x
 }
 
 define <4 x i32> @test_unsigned_v4f32_v4i32(<4 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v4f32_v4i32:
 ; CHECK:       // %bb.0:
+; CHECK-NEXT:    fcvtzu w8, s0
 ; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    mov w8, #1333788671
-; CHECK-NEXT:    fmov s3, w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    fcvtzu w9, s0
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s0, s3
 ; CHECK-NEXT:    mov s2, v0.s[2]
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    mov s1, v0.s[3]
-; CHECK-NEXT:    fmov s0, w9
+; CHECK-NEXT:    mov s3, v0.s[3]
+; CHECK-NEXT:    fmov s0, w8
+; CHECK-NEXT:    fcvtzu w8, s1
 ; CHECK-NEXT:    fcvtzu w9, s2
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s2, s3
 ; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s1, s3
 ; CHECK-NEXT:    mov v0.s[2], w9
-; CHECK-NEXT:    csinv w8, w8, wzr, le
+; CHECK-NEXT:    fcvtzu w8, s3
 ; CHECK-NEXT:    mov v0.s[3], w8
 ; CHECK-NEXT:    ret
     %x = call <4 x i32> @llvm.fptoui.sat.v4f32.v4i32(<4 x float> %f)
     ret <4 x i32> %x
 }
 
 define <5 x i32> @test_unsigned_v5f32_v5i32(<5 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v5f32_v5i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w9, #1333788671
-; CHECK-NEXT:    fcvtzu w8, s0
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    fmov s5, w9
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s0, s5
-; CHECK-NEXT:    fcvtzu w10, s1
-; CHECK-NEXT:    csinv w0, w8, wzr, le
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w8, wzr, w10, lt
-; CHECK-NEXT:    fcmp s1, s5
-; CHECK-NEXT:    fcvtzu w11, s2
-; CHECK-NEXT:    csinv w1, w8, wzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    csel w8, wzr, w11, lt
-; CHECK-NEXT:    fcmp s2, s5
-; CHECK-NEXT:    fcvtzu w12, s3
-; CHECK-NEXT:    csinv w2, w8, wzr, le
-; CHECK-NEXT:    fcmp s3, #0.0
-; CHECK-NEXT:    csel w8, wzr, w12, lt
-; CHECK-NEXT:    fcmp s3, s5
-; CHECK-NEXT:    fcvtzu w9, s4
-; CHECK-NEXT:    csinv w3, w8, wzr, le
-; CHECK-NEXT:    fcmp s4, #0.0
-; CHECK-NEXT:    csel w8, wzr, w9, lt
-; CHECK-NEXT:    fcmp s4, s5
-; CHECK-NEXT:    csinv w4, w8, wzr, le
+; CHECK-NEXT:    fcvtzu w0, s0
+; CHECK-NEXT:    fcvtzu w1, s1
+; CHECK-NEXT:    fcvtzu w2, s2
+; CHECK-NEXT:    fcvtzu w3, s3
+; CHECK-NEXT:    fcvtzu w4, s4
 ; CHECK-NEXT:    ret
     %x = call <5 x i32> @llvm.fptoui.sat.v5f32.v5i32(<5 x float> %f)
     ret <5 x i32> %x
 }
 
 define <6 x i32> @test_unsigned_v6f32_v6i32(<6 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v6f32_v6i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w9, #1333788671
-; CHECK-NEXT:    fcvtzu w8, s5
-; CHECK-NEXT:    fcmp s5, #0.0
-; CHECK-NEXT:    fmov s6, w9
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s5, s6
-; CHECK-NEXT:    fcvtzu w10, s4
-; CHECK-NEXT:    csinv w5, w8, wzr, le
-; CHECK-NEXT:    fcmp s4, #0.0
-; CHECK-NEXT:    csel w8, wzr, w10, lt
-; CHECK-NEXT:    fcmp s4, s6
-; CHECK-NEXT:    fcvtzu w11, s0
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    fmov s4, w8
-; CHECK-NEXT:    csel w8, wzr, w11, lt
-; CHECK-NEXT:    fcmp s0, s6
-; CHECK-NEXT:    fcvtzu w12, s1
-; CHECK-NEXT:    csinv w0, w8, wzr, le
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w8, wzr, w12, lt
-; CHECK-NEXT:    fcmp s1, s6
-; CHECK-NEXT:    fcvtzu w13, s2
-; CHECK-NEXT:    csinv w1, w8, wzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    csel w8, wzr, w13, lt
-; CHECK-NEXT:    fcmp s2, s6
-; CHECK-NEXT:    fcvtzu w9, s3
-; CHECK-NEXT:    csinv w2, w8, wzr, le
-; CHECK-NEXT:    fcmp s3, #0.0
-; CHECK-NEXT:    mov v4.s[1], w5
-; CHECK-NEXT:    csel w8, wzr, w9, lt
-; CHECK-NEXT:    fcmp s3, s6
-; CHECK-NEXT:    csinv w3, w8, wzr, le
-; CHECK-NEXT:    fmov w4, s4
+; CHECK-NEXT:    fcvtzu w8, s4
+; CHECK-NEXT:    fcvtzu w5, s5
+; CHECK-NEXT:    fcvtzu w0, s0
+; CHECK-NEXT:    fmov s0, w8
+; CHECK-NEXT:    mov v0.s[1], w5
+; CHECK-NEXT:    fcvtzu w1, s1
+; CHECK-NEXT:    fcvtzu w2, s2
+; CHECK-NEXT:    fcvtzu w3, s3
+; CHECK-NEXT:    fmov w4, s0
 ; CHECK-NEXT:    ret
     %x = call <6 x i32> @llvm.fptoui.sat.v6f32.v6i32(<6 x float> %f)
     ret <6 x i32> %x
 }
 
 define <7 x i32> @test_unsigned_v7f32_v7i32(<7 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v7f32_v7i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w9, #1333788671
-; CHECK-NEXT:    fcvtzu w8, s5
-; CHECK-NEXT:    fcmp s5, #0.0
-; CHECK-NEXT:    fmov s7, w9
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s5, s7
-; CHECK-NEXT:    fcvtzu w10, s4
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s4, #0.0
-; CHECK-NEXT:    csel w10, wzr, w10, lt
-; CHECK-NEXT:    fcmp s4, s7
-; CHECK-NEXT:    fcvtzu w11, s6
-; CHECK-NEXT:    csinv w10, w10, wzr, le
-; CHECK-NEXT:    fcmp s6, #0.0
-; CHECK-NEXT:    fmov s4, w10
-; CHECK-NEXT:    csel w10, wzr, w11, lt
-; CHECK-NEXT:    fcmp s6, s7
-; CHECK-NEXT:    fcvtzu w12, s0
-; CHECK-NEXT:    csinv w6, w10, wzr, le
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    mov v4.s[1], w8
-; CHECK-NEXT:    csel w8, wzr, w12, lt
-; CHECK-NEXT:    fcmp s0, s7
-; CHECK-NEXT:    fcvtzu w13, s1
-; CHECK-NEXT:    csinv w0, w8, wzr, le
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w8, wzr, w13, lt
-; CHECK-NEXT:    fcmp s1, s7
-; CHECK-NEXT:    fcvtzu w14, s2
-; CHECK-NEXT:    csinv w1, w8, wzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    csel w8, wzr, w14, lt
-; CHECK-NEXT:    fcmp s2, s7
-; CHECK-NEXT:    fcvtzu w9, s3
-; CHECK-NEXT:    csinv w2, w8, wzr, le
-; CHECK-NEXT:    fcmp s3, #0.0
-; CHECK-NEXT:    mov v4.s[2], w6
-; CHECK-NEXT:    csel w8, wzr, w9, lt
-; CHECK-NEXT:    fcmp s3, s7
-; CHECK-NEXT:    csinv w3, w8, wzr, le
-; CHECK-NEXT:    mov w5, v4.s[1]
-; CHECK-NEXT:    fmov w4, s4
+; CHECK-NEXT:    fcvtzu w8, s4
+; CHECK-NEXT:    fcvtzu w9, s5
+; CHECK-NEXT:    fcvtzu w0, s0
+; CHECK-NEXT:    fmov s0, w8
+; CHECK-NEXT:    fcvtzu w6, s6
+; CHECK-NEXT:    mov v0.s[1], w9
+; CHECK-NEXT:    mov v0.s[2], w6
+; CHECK-NEXT:    fcvtzu w1, s1
+; CHECK-NEXT:    fcvtzu w2, s2
+; CHECK-NEXT:    fcvtzu w3, s3
+; CHECK-NEXT:    mov w5, v0.s[1]
+; CHECK-NEXT:    fmov w4, s0
 ; CHECK-NEXT:    ret
     %x = call <7 x i32> @llvm.fptoui.sat.v7f32.v7i32(<7 x float> %f)
     ret <7 x i32> %x
 }
 
 define <8 x i32> @test_unsigned_v8f32_v8i32(<8 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v8f32_v8i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov s2, v0.s[1]
-; CHECK-NEXT:    mov w8, #1333788671
-; CHECK-NEXT:    fmov s4, w8
-; CHECK-NEXT:    fcvtzu w8, s2
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s2, s4
-; CHECK-NEXT:    fcvtzu w9, s0
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s0, s4
 ; CHECK-NEXT:    mov s3, v0.s[2]
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    mov s2, v0.s[3]
-; CHECK-NEXT:    fmov s0, w9
-; CHECK-NEXT:    fcvtzu w9, s3
-; CHECK-NEXT:    fcmp s3, #0.0
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s3, s4
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    mov v0.s[2], w9
-; CHECK-NEXT:    fcvtzu w9, s2
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s2, s4
-; CHECK-NEXT:    mov s3, v1.s[1]
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    mov v0.s[3], w9
-; CHECK-NEXT:    fcvtzu w9, s3
-; CHECK-NEXT:    fcmp s3, #0.0
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s3, s4
+; CHECK-NEXT:    fcvtzu w8, s0
+; CHECK-NEXT:    fcvtzu w9, s1
+; CHECK-NEXT:    fcvtzu w10, s2
+; CHECK-NEXT:    mov s2, v1.s[1]
+; CHECK-NEXT:    fcvtzu w11, s3
+; CHECK-NEXT:    mov s3, v1.s[2]
+; CHECK-NEXT:    fcvtzu w12, s2
+; CHECK-NEXT:    fmov s2, w8
+; CHECK-NEXT:    fcvtzu w8, s3
+; CHECK-NEXT:    fmov s3, w9
+; CHECK-NEXT:    mov v2.s[1], w10
+; CHECK-NEXT:    mov v3.s[1], w12
+; CHECK-NEXT:    mov s0, v0.s[3]
+; CHECK-NEXT:    mov v2.s[2], w11
+; CHECK-NEXT:    mov s1, v1.s[3]
+; CHECK-NEXT:    mov v3.s[2], w8
+; CHECK-NEXT:    fcvtzu w8, s0
+; CHECK-NEXT:    mov v2.s[3], w8
 ; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    mov s2, v1.s[2]
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    mov s3, v1.s[3]
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fcvtzu w8, s2
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s2, s4
-; CHECK-NEXT:    mov v1.s[1], w9
-; CHECK-NEXT:    fcvtzu w9, s3
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s3, #0.0
-; CHECK-NEXT:    mov v1.s[2], w8
-; CHECK-NEXT:    csel w8, wzr, w9, lt
-; CHECK-NEXT:    fcmp s3, s4
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    mov v1.s[3], w8
+; CHECK-NEXT:    mov v3.s[3], w8
+; CHECK-NEXT:    mov v0.16b, v2.16b
+; CHECK-NEXT:    mov v1.16b, v3.16b
 ; CHECK-NEXT:    ret
     %x = call <8 x i32> @llvm.fptoui.sat.v8f32.v8i32(<8 x float> %f)
     ret <8 x i32> %x
 }
 
 ;
 ; Double to unsigned 32-bit -- Vector size variation
 ;
 
 declare <1 x i32> @llvm.fptoui.sat.v1f64.v1i32 (<1 x double>)
 declare <2 x i32> @llvm.fptoui.sat.v2f64.v2i32 (<2 x double>)
 declare <3 x i32> @llvm.fptoui.sat.v3f64.v3i32 (<3 x double>)
 declare <4 x i32> @llvm.fptoui.sat.v4f64.v4i32 (<4 x double>)
 declare <5 x i32> @llvm.fptoui.sat.v5f64.v5i32 (<5 x double>)
 declare <6 x i32> @llvm.fptoui.sat.v6f64.v6i32 (<6 x double>)
 
 define <1 x i32> @test_unsigned_v1f64_v1i32(<1 x double> %f) {
 ; CHECK-LABEL: test_unsigned_v1f64_v1i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #281474974613504
-; CHECK-NEXT:    movi d1, #0000000000000000
-; CHECK-NEXT:    movk x8, #16879, lsl #48
-; CHECK-NEXT:    fmaxnm d0, d0, d1
-; CHECK-NEXT:    fmov d1, x8
-; CHECK-NEXT:    fminnm d0, d0, d1
 ; CHECK-NEXT:    fcvtzu w8, d0
 ; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    ret
     %x = call <1 x i32> @llvm.fptoui.sat.v1f64.v1i32(<1 x double> %f)
     ret <1 x i32> %x
 }
 
 define <2 x i32> @test_unsigned_v2f64_v2i32(<2 x double> %f) {
 ; CHECK-LABEL: test_unsigned_v2f64_v2i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #281474974613504
-; CHECK-NEXT:    movi d1, #0000000000000000
-; CHECK-NEXT:    movk x8, #16879, lsl #48
-; CHECK-NEXT:    mov d2, v0.d[1]
-; CHECK-NEXT:    fmaxnm d0, d0, d1
-; CHECK-NEXT:    fmov d3, x8
-; CHECK-NEXT:    fmaxnm d1, d2, d1
-; CHECK-NEXT:    fminnm d0, d0, d3
 ; CHECK-NEXT:    fcvtzu w8, d0
-; CHECK-NEXT:    fminnm d1, d1, d3
+; CHECK-NEXT:    mov d1, v0.d[1]
 ; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    fcvtzu w8, d1
 ; CHECK-NEXT:    mov v0.s[1], w8
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
 ; CHECK-NEXT:    ret
     %x = call <2 x i32> @llvm.fptoui.sat.v2f64.v2i32(<2 x double> %f)
     ret <2 x i32> %x
 }
 
 define <3 x i32> @test_unsigned_v3f64_v3i32(<3 x double> %f) {
 ; CHECK-LABEL: test_unsigned_v3f64_v3i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #281474974613504
-; CHECK-NEXT:    movi d3, #0000000000000000
-; CHECK-NEXT:    movk x8, #16879, lsl #48
-; CHECK-NEXT:    fmaxnm d0, d0, d3
-; CHECK-NEXT:    fmov d4, x8
-; CHECK-NEXT:    fmaxnm d1, d1, d3
-; CHECK-NEXT:    fmaxnm d2, d2, d3
-; CHECK-NEXT:    fmaxnm d3, d3, d0
-; CHECK-NEXT:    fminnm d0, d0, d4
-; CHECK-NEXT:    fminnm d1, d1, d4
 ; CHECK-NEXT:    fcvtzu w8, d0
-; CHECK-NEXT:    fminnm d2, d2, d4
+; CHECK-NEXT:    fcvtzu w9, d1
 ; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzu w8, d1
-; CHECK-NEXT:    fminnm d3, d3, d4
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    fcvtzu w8, d2
-; CHECK-NEXT:    mov v0.s[2], w8
-; CHECK-NEXT:    fcvtzu w8, d3
+; CHECK-NEXT:    fcvtzu w10, d2
+; CHECK-NEXT:    mov v0.s[1], w9
+; CHECK-NEXT:    mov v0.s[2], w10
+; CHECK-NEXT:    fcvtzu w8, d0
 ; CHECK-NEXT:    mov v0.s[3], w8
 ; CHECK-NEXT:    ret
     %x = call <3 x i32> @llvm.fptoui.sat.v3f64.v3i32(<3 x double> %f)
     ret <3 x i32> %x
 }
 
 define <4 x i32> @test_unsigned_v4f64_v4i32(<4 x double> %f) {
 ; CHECK-LABEL: test_unsigned_v4f64_v4i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #281474974613504
-; CHECK-NEXT:    movi d2, #0000000000000000
-; CHECK-NEXT:    movk x8, #16879, lsl #48
-; CHECK-NEXT:    mov d3, v0.d[1]
-; CHECK-NEXT:    mov d4, v1.d[1]
-; CHECK-NEXT:    fmaxnm d0, d0, d2
-; CHECK-NEXT:    fmaxnm d3, d3, d2
-; CHECK-NEXT:    fmaxnm d1, d1, d2
-; CHECK-NEXT:    fmaxnm d2, d4, d2
-; CHECK-NEXT:    fmov d4, x8
-; CHECK-NEXT:    fminnm d0, d0, d4
-; CHECK-NEXT:    fminnm d3, d3, d4
 ; CHECK-NEXT:    fcvtzu w8, d0
-; CHECK-NEXT:    fminnm d1, d1, d4
+; CHECK-NEXT:    mov d2, v0.d[1]
 ; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    fcvtzu w8, d3
-; CHECK-NEXT:    fminnm d2, d2, d4
+; CHECK-NEXT:    fcvtzu w8, d2
+; CHECK-NEXT:    fcvtzu w9, d1
+; CHECK-NEXT:    mov d1, v1.d[1]
 ; CHECK-NEXT:    mov v0.s[1], w8
+; CHECK-NEXT:    mov v0.s[2], w9
 ; CHECK-NEXT:    fcvtzu w8, d1
-; CHECK-NEXT:    mov v0.s[2], w8
-; CHECK-NEXT:    fcvtzu w8, d2
 ; CHECK-NEXT:    mov v0.s[3], w8
 ; CHECK-NEXT:    ret
     %x = call <4 x i32> @llvm.fptoui.sat.v4f64.v4i32(<4 x double> %f)
     ret <4 x i32> %x
 }
 
 define <5 x i32> @test_unsigned_v5f64_v5i32(<5 x double> %f) {
 ; CHECK-LABEL: test_unsigned_v5f64_v5i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #281474974613504
-; CHECK-NEXT:    movi d5, #0000000000000000
-; CHECK-NEXT:    movk x8, #16879, lsl #48
-; CHECK-NEXT:    fmaxnm d0, d0, d5
-; CHECK-NEXT:    fmov d6, x8
-; CHECK-NEXT:    fmaxnm d1, d1, d5
-; CHECK-NEXT:    fmaxnm d2, d2, d5
-; CHECK-NEXT:    fmaxnm d3, d3, d5
-; CHECK-NEXT:    fmaxnm d4, d4, d5
-; CHECK-NEXT:    fminnm d0, d0, d6
-; CHECK-NEXT:    fminnm d1, d1, d6
-; CHECK-NEXT:    fminnm d2, d2, d6
-; CHECK-NEXT:    fminnm d3, d3, d6
-; CHECK-NEXT:    fminnm d4, d4, d6
 ; CHECK-NEXT:    fcvtzu w0, d0
 ; CHECK-NEXT:    fcvtzu w1, d1
 ; CHECK-NEXT:    fcvtzu w2, d2
 ; CHECK-NEXT:    fcvtzu w3, d3
 ; CHECK-NEXT:    fcvtzu w4, d4
 ; CHECK-NEXT:    ret
     %x = call <5 x i32> @llvm.fptoui.sat.v5f64.v5i32(<5 x double> %f)
     ret <5 x i32> %x
 }
 
 define <6 x i32> @test_unsigned_v6f64_v6i32(<6 x double> %f) {
 ; CHECK-LABEL: test_unsigned_v6f64_v6i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #281474974613504
-; CHECK-NEXT:    movi d6, #0000000000000000
-; CHECK-NEXT:    movk x8, #16879, lsl #48
-; CHECK-NEXT:    fmaxnm d0, d0, d6
-; CHECK-NEXT:    fmov d7, x8
-; CHECK-NEXT:    fmaxnm d1, d1, d6
-; CHECK-NEXT:    fmaxnm d2, d2, d6
-; CHECK-NEXT:    fmaxnm d3, d3, d6
-; CHECK-NEXT:    fmaxnm d4, d4, d6
-; CHECK-NEXT:    fmaxnm d5, d5, d6
-; CHECK-NEXT:    fminnm d0, d0, d7
-; CHECK-NEXT:    fminnm d1, d1, d7
-; CHECK-NEXT:    fminnm d2, d2, d7
-; CHECK-NEXT:    fminnm d3, d3, d7
-; CHECK-NEXT:    fminnm d4, d4, d7
-; CHECK-NEXT:    fminnm d5, d5, d7
 ; CHECK-NEXT:    fcvtzu w0, d0
 ; CHECK-NEXT:    fcvtzu w1, d1
 ; CHECK-NEXT:    fcvtzu w2, d2
 ; CHECK-NEXT:    fcvtzu w3, d3
 ; CHECK-NEXT:    fcvtzu w4, d4
 ; CHECK-NEXT:    fcvtzu w5, d5
 ; CHECK-NEXT:    ret
     %x = call <6 x i32> @llvm.fptoui.sat.v6f64.v6i32(<6 x double> %f)

 declare <6 x i32> @llvm.fptoui.sat.v6f16.v6i32 (<6 x half>)
 declare <7 x i32> @llvm.fptoui.sat.v7f16.v7i32 (<7 x half>)
 declare <8 x i32> @llvm.fptoui.sat.v8f16.v8i32 (<8 x half>)
 
 define <1 x i32> @test_unsigned_v1f16_v1i32(<1 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v1f16_v1i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    mov w8, #1333788671
-; CHECK-NEXT:    fcvtzu w9, s0
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    csel w8, wzr, w9, lt
-; CHECK-NEXT:    fcmp s0, s1
-; CHECK-NEXT:    csinv w8, w8, wzr, le
+; CHECK-NEXT:    fcvtzu w8, s0
 ; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    ret
     %x = call <1 x i32> @llvm.fptoui.sat.v1f16.v1i32(<1 x half> %f)
     ret <1 x i32> %x
 }
 
 define <2 x i32> @test_unsigned_v2f16_v2i32(<2 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v2f16_v2i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    mov w8, #1333788671
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    fcvtzu w9, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    fcvtzu w8, s0
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csinv w8, w8, wzr, le
+; CHECK-NEXT:    fcvt s1, h0
+; CHECK-NEXT:    mov h0, v0.h[1]
+; CHECK-NEXT:    fcvtzu w8, s1
+; CHECK-NEXT:    fcvt s1, h0
 ; CHECK-NEXT:    fmov s0, w8
-; CHECK-NEXT:    mov v0.s[1], w9
+; CHECK-NEXT:    fcvtzu w8, s1
+; CHECK-NEXT:    mov v0.s[1], w8
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
 ; CHECK-NEXT:    ret
     %x = call <2 x i32> @llvm.fptoui.sat.v2f16.v2i32(<2 x half> %f)
     ret <2 x i32> %x
 }
 
 define <3 x i32> @test_unsigned_v3f16_v3i32(<3 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v3f16_v3i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    mov w8, #1333788671
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fmov s3, w8
+; CHECK-NEXT:    fcvt s1, h0
+; CHECK-NEXT:    mov h2, v0.h[1]
 ; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    fcvtzu w9, s2
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    mov h1, v0.h[2]
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s2, s3
+; CHECK-NEXT:    fcvt s2, h2
+; CHECK-NEXT:    fmov s1, w8
+; CHECK-NEXT:    fcvtzu w8, s2
+; CHECK-NEXT:    mov h2, v0.h[2]
 ; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    fmov s0, w9
-; CHECK-NEXT:    fcvtzu w9, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    mov v0.s[1], w8
+; CHECK-NEXT:    fcvt s2, h2
+; CHECK-NEXT:    fcvt s0, h0
+; CHECK-NEXT:    mov v1.s[1], w8
 ; CHECK-NEXT:    fcvtzu w8, s2
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    mov v0.s[2], w9
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    mov v0.s[3], w8
+; CHECK-NEXT:    mov v1.s[2], w8
+; CHECK-NEXT:    fcvtzu w8, s0
+; CHECK-NEXT:    mov v1.s[3], w8
+; CHECK-NEXT:    mov v0.16b, v1.16b
 ; CHECK-NEXT:    ret
     %x = call <3 x i32> @llvm.fptoui.sat.v3f16.v3i32(<3 x half> %f)
     ret <3 x i32> %x
 }
 
 define <4 x i32> @test_unsigned_v4f16_v4i32(<4 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v4f16_v4i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    mov w8, #1333788671
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fmov s3, w8
+; CHECK-NEXT:    fcvt s1, h0
+; CHECK-NEXT:    mov h2, v0.h[1]
 ; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    fcvtzu w9, s2
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    mov h1, v0.h[2]
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s2, s3
+; CHECK-NEXT:    fcvt s2, h2
+; CHECK-NEXT:    fmov s1, w8
+; CHECK-NEXT:    fcvtzu w8, s2
+; CHECK-NEXT:    mov h2, v0.h[2]
 ; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    fmov s0, w9
-; CHECK-NEXT:    fcvtzu w9, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    mov v0.s[1], w8
+; CHECK-NEXT:    fcvt s2, h2
+; CHECK-NEXT:    fcvt s0, h0
+; CHECK-NEXT:    mov v1.s[1], w8
 ; CHECK-NEXT:    fcvtzu w8, s2
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    mov v0.s[2], w9
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    mov v0.s[3], w8
+; CHECK-NEXT:    mov v1.s[2], w8
+; CHECK-NEXT:    fcvtzu w8, s0
+; CHECK-NEXT:    mov v1.s[3], w8
+; CHECK-NEXT:    mov v0.16b, v1.16b
 ; CHECK-NEXT:    ret
     %x = call <4 x i32> @llvm.fptoui.sat.v4f16.v4i32(<4 x half> %f)
     ret <4 x i32> %x
 }
 
 define <5 x i32> @test_unsigned_v5f16_v5i32(<5 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v5f16_v5i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvt s1, h0
-; CHECK-NEXT:    mov w8, #1333788671
-; CHECK-NEXT:    fcvtzu w9, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    fmov s2, w8
-; CHECK-NEXT:    csel w8, wzr, w9, lt
-; CHECK-NEXT:    fcmp s1, s2
+; CHECK-NEXT:    fcvtzu w0, s1
+; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT:    fcvt s1, h1
+; CHECK-NEXT:    fcvtzu w4, s1
 ; CHECK-NEXT:    mov h1, v0.h[1]
 ; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvtzu w9, s1
-; CHECK-NEXT:    csinv w0, w8, wzr, le
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w8, wzr, w9, lt
-; CHECK-NEXT:    fcmp s1, s2
+; CHECK-NEXT:    fcvtzu w1, s1
 ; CHECK-NEXT:    mov h1, v0.h[2]
+; CHECK-NEXT:    mov h0, v0.h[3]
 ; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvtzu w9, s1
-; CHECK-NEXT:    csinv w1, w8, wzr, le
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w8, wzr, w9, lt
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    mov h1, v0.h[3]
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    ext v0.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT:    fcvtzu w9, s1
-; CHECK-NEXT:    csinv w2, w8, wzr, le
-; CHECK-NEXT:    fcmp s1, #0.0
 ; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    csel w8, wzr, w9, lt
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    fcvtzu w10, s0
-; CHECK-NEXT:    csinv w3, w8, wzr, le
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    csel w8, wzr, w10, lt
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csinv w4, w8, wzr, le
+; CHECK-NEXT:    fcvtzu w2, s1
+; CHECK-NEXT:    fcvtzu w3, s0
 ; CHECK-NEXT:    ret
     %x = call <5 x i32> @llvm.fptoui.sat.v5f16.v5i32(<5 x half> %f)
     ret <5 x i32> %x
 }
 
 define <6 x i32> @test_unsigned_v6f16_v6i32(<6 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v6f16_v6i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT:    mov h2, v1.h[1]
-; CHECK-NEXT:    mov w8, #1333788671
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    fmov s3, w8
-; CHECK-NEXT:    fcvtzu w8, s2
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvtzu w9, s1
-; CHECK-NEXT:    csinv w5, w8, wzr, le
-; CHECK-NEXT:    fcmp s1, #0.0
 ; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    csel w8, wzr, w9, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    fcvtzu w9, s2
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    fcvt s1, h1
+; CHECK-NEXT:    fcvtzu w0, s2
+; CHECK-NEXT:    fcvt s2, h1
+; CHECK-NEXT:    fcvtzu w8, s2
+; CHECK-NEXT:    mov h2, v0.h[1]
+; CHECK-NEXT:    fcvt s2, h2
+; CHECK-NEXT:    fcvtzu w1, s2
 ; CHECK-NEXT:    mov h2, v0.h[2]
-; CHECK-NEXT:    fcvtzu w10, s1
-; CHECK-NEXT:    csinv w0, w9, wzr, le
-; CHECK-NEXT:    fcmp s1, #0.0
+; CHECK-NEXT:    mov h1, v1.h[1]
 ; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    csel w9, wzr, w10, lt
-; CHECK-NEXT:    fcmp s1, s3
+; CHECK-NEXT:    fcvt s1, h1
 ; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvtzu w11, s2
-; CHECK-NEXT:    csinv w1, w9, wzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
+; CHECK-NEXT:    fcvtzu w2, s2
+; CHECK-NEXT:    fmov s2, w8
+; CHECK-NEXT:    fcvtzu w5, s1
 ; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    csel w8, wzr, w11, lt
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    fcvtzu w12, s0
-; CHECK-NEXT:    csinv w2, w8, wzr, le
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    mov v1.s[1], w5
-; CHECK-NEXT:    csel w8, wzr, w12, lt
-; CHECK-NEXT:    fcmp s0, s3
-; CHECK-NEXT:    csinv w3, w8, wzr, le
-; CHECK-NEXT:    fmov w4, s1
+; CHECK-NEXT:    mov v2.s[1], w5
+; CHECK-NEXT:    fcvtzu w3, s0
+; CHECK-NEXT:    fmov w4, s2
 ; CHECK-NEXT:    ret
     %x = call <6 x i32> @llvm.fptoui.sat.v6f16.v6i32(<6 x half> %f)
     ret <6 x i32> %x
 }
 
 define <7 x i32> @test_unsigned_v7f16_v7i32(<7 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v7f16_v7i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT:    mov h2, v1.h[1]
-; CHECK-NEXT:    mov w8, #1333788671
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    fmov s3, w8
-; CHECK-NEXT:    fcvtzu w8, s2
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    fcvt s2, h1
-; CHECK-NEXT:    fcvtzu w9, s2
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    mov h1, v1.h[2]
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fcvtzu w10, s1
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    fcmp s1, #0.0
 ; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    csel w10, wzr, w10, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    fcvtzu w11, s2
-; CHECK-NEXT:    csinv w6, w10, wzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    csel w10, wzr, w11, lt
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    fcvt s1, h1
+; CHECK-NEXT:    mov h3, v0.h[1]
+; CHECK-NEXT:    fcvtzu w0, s2
+; CHECK-NEXT:    fcvt s2, h1
+; CHECK-NEXT:    fcvt s3, h3
+; CHECK-NEXT:    fcvtzu w8, s2
 ; CHECK-NEXT:    mov h2, v0.h[2]
-; CHECK-NEXT:    fcvtzu w11, s1
-; CHECK-NEXT:    csinv w0, w10, wzr, le
-; CHECK-NEXT:    fcmp s1, #0.0
+; CHECK-NEXT:    fcvtzu w1, s3
+; CHECK-NEXT:    mov h3, v1.h[1]
+; CHECK-NEXT:    mov h1, v1.h[2]
 ; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    csel w10, wzr, w11, lt
-; CHECK-NEXT:    fcmp s1, s3
+; CHECK-NEXT:    fcvt s3, h3
+; CHECK-NEXT:    fcvt s1, h1
+; CHECK-NEXT:    fcvtzu w2, s2
+; CHECK-NEXT:    fmov s2, w8
+; CHECK-NEXT:    fcvtzu w8, s3
 ; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvtzu w12, s2
-; CHECK-NEXT:    fmov s1, w9
-; CHECK-NEXT:    csinv w1, w10, wzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
+; CHECK-NEXT:    fcvtzu w6, s1
+; CHECK-NEXT:    mov v2.s[1], w8
 ; CHECK-NEXT:    fcvt s0, h0
-; CHECK-NEXT:    mov v1.s[1], w8
-; CHECK-NEXT:    csel w8, wzr, w12, lt
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    fcvtzu w13, s0
-; CHECK-NEXT:    csinv w2, w8, wzr, le
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    mov v1.s[2], w6
-; CHECK-NEXT:    csel w8, wzr, w13, lt
-; CHECK-NEXT:    fcmp s0, s3
-; CHECK-NEXT:    csinv w3, w8, wzr, le
-; CHECK-NEXT:    mov w5, v1.s[1]
-; CHECK-NEXT:    fmov w4, s1
+; CHECK-NEXT:    mov v2.s[2], w6
+; CHECK-NEXT:    fcvtzu w3, s0
+; CHECK-NEXT:    mov w5, v2.s[1]
+; CHECK-NEXT:    fmov w4, s2
 ; CHECK-NEXT:    ret
     %x = call <7 x i32> @llvm.fptoui.sat.v7f16.v7i32(<7 x half> %f)
     ret <7 x i32> %x
 }
 
 define <8 x i32> @test_unsigned_v8f16_v8i32(<8 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v8f16_v8i32:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    mov w8, #1333788671
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fmov s4, w8
+; CHECK-NEXT:    ext v3.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT:    fcvt s1, h0
 ; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    fcvtzu w9, s2
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    mov h3, v0.h[2]
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s2, s4
-; CHECK-NEXT:    fcvt s3, h3
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    mov h1, v0.h[3]
-; CHECK-NEXT:    ext v5.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT:    fmov s0, w9
-; CHECK-NEXT:    fcvtzu w9, s3
-; CHECK-NEXT:    fcmp s3, #0.0
+; CHECK-NEXT:    fcvt s1, h3
+; CHECK-NEXT:    mov h2, v0.h[1]
+; CHECK-NEXT:    fcvtzu w9, s1
+; CHECK-NEXT:    mov h1, v0.h[2]
+; CHECK-NEXT:    fcvt s2, h2
 ; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s3, s4
-; CHECK-NEXT:    mov h2, v5.h[1]
-; CHECK-NEXT:    mov v0.s[1], w8
-; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s1, s4
+; CHECK-NEXT:    fcvtzu w10, s2
+; CHECK-NEXT:    mov h2, v3.h[1]
+; CHECK-NEXT:    fcvtzu w11, s1
+; CHECK-NEXT:    mov h1, v3.h[2]
 ; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    mov v0.s[2], w9
-; CHECK-NEXT:    fcvtzu w9, s2
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    fcvt s1, h5
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s2, s4
-; CHECK-NEXT:    mov v0.s[3], w8
+; CHECK-NEXT:    fcvt s1, h1
+; CHECK-NEXT:    fcvtzu w12, s2
+; CHECK-NEXT:    fmov s2, w8
 ; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    mov h2, v5.h[2]
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s1, s4
-; CHECK-NEXT:    fcvt s2, h2
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    mov h3, v5.h[3]
-; CHECK-NEXT:    fmov s1, w8
-; CHECK-NEXT:    fcvtzu w8, s2
-; CHECK-NEXT:    fcmp s2, #0.0
+; CHECK-NEXT:    fmov s1, w9
+; CHECK-NEXT:    mov h3, v3.h[3]
+; CHECK-NEXT:    mov v1.s[1], w12
+; CHECK-NEXT:    mov h0, v0.h[3]
 ; CHECK-NEXT:    fcvt s3, h3
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s2, s4
-; CHECK-NEXT:    mov v1.s[1], w9
-; CHECK-NEXT:    fcvtzu w9, s3
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s3, #0.0
+; CHECK-NEXT:    mov v2.s[1], w10
+; CHECK-NEXT:    fcvt s0, h0
 ; CHECK-NEXT:    mov v1.s[2], w8
-; CHECK-NEXT:    csel w8, wzr, w9, lt
-; CHECK-NEXT:    fcmp s3, s4
-; CHECK-NEXT:    csinv w8, w8, wzr, le
+; CHECK-NEXT:    fcvtzu w8, s3
+; CHECK-NEXT:    mov v2.s[2], w11
 ; CHECK-NEXT:    mov v1.s[3], w8
+; CHECK-NEXT:    fcvtzu w8, s0
+; CHECK-NEXT:    mov v2.s[3], w8
+; CHECK-NEXT:    mov v0.16b, v2.16b
 ; CHECK-NEXT:    ret
     %x = call <8 x i32> @llvm.fptoui.sat.v8f16.v8i32(<8 x half> %f)
     ret <8 x i32> %x
 }
 
 ;
 ; 2-Vector float to unsigned integer -- result size variation
 ;
; CHECK-NEXT:    ret
     %x = call <2 x i19> @llvm.fptoui.sat.v2f32.v2i19(<2 x float> %f)
     ret <2 x i19> %x
 }
 
 define <2 x i32> @test_unsigned_v2f32_v2i32_duplicate(<2 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v2f32_v2i32_duplicate:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    fcvtzu w8, s0
 ; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    mov w8, #1333788671
-; CHECK-NEXT:    fmov s2, w8
+; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    fcvtzu w9, s0
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    fmov s0, w9
 ; CHECK-NEXT:    mov v0.s[1], w8
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
 ; CHECK-NEXT:    ret
     %x = call <2 x i32> @llvm.fptoui.sat.v2f32.v2i32(<2 x float> %f)
     ret <2 x i32> %x
 }
 
 define <2 x i50> @test_unsigned_v2f32_v2i50(<2 x float> %f) {
; CHECK-NEXT:    ret
     %x = call <2 x i50> @llvm.fptoui.sat.v2f32.v2i50(<2 x float> %f)
     ret <2 x i50> %x
 }
 
 define <2 x i64> @test_unsigned_v2f32_v2i64(<2 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v2f32_v2i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    fcvtzu x8, s0
 ; CHECK-NEXT:    mov s1, v0.s[1]
-; CHECK-NEXT:    mov w8, #1602224127
-; CHECK-NEXT:    fmov s2, w8
+; CHECK-NEXT:    fmov d0, x8
 ; CHECK-NEXT:    fcvtzu x8, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel x8, xzr, x8, lt
-; CHECK-NEXT:    fcmp s1, s2
-; CHECK-NEXT:    fcvtzu x9, s0
-; CHECK-NEXT:    csinv x8, x8, xzr, le
-; CHECK-NEXT:    fcmp s0, #0.0
-; CHECK-NEXT:    csel x9, xzr, x9, lt
-; CHECK-NEXT:    fcmp s0, s2
-; CHECK-NEXT:    csinv x9, x9, xzr, le
-; CHECK-NEXT:    fmov d0, x9
 ; CHECK-NEXT:    mov v0.d[1], x8
 ; CHECK-NEXT:    ret
     %x = call <2 x i64> @llvm.fptoui.sat.v2f32.v2i64(<2 x float> %f)
     ret <2 x i64> %x
 }
 
 define <2 x i100> @test_unsigned_v2f32_v2i100(<2 x float> %f) {
 ; CHECK-LABEL: test_unsigned_v2f32_v2i100:

 ; CHECK-NEXT:    ret
     %x = call <2 x i19> @llvm.fptoui.sat.v2f64.v2i19(<2 x double> %f)
     ret <2 x i19> %x
 }
 
 define <2 x i32> @test_unsigned_v2f64_v2i32_duplicate(<2 x double> %f) {
 ; CHECK-LABEL: test_unsigned_v2f64_v2i32_duplicate:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, #281474974613504
-; CHECK-NEXT:    movi d1, #0000000000000000
-; CHECK-NEXT:    movk x8, #16879, lsl #48
-; CHECK-NEXT:    mov d2, v0.d[1]
-; CHECK-NEXT:    fmaxnm d0, d0, d1
-; CHECK-NEXT:    fmov d3, x8
-; CHECK-NEXT:    fmaxnm d1, d2, d1
-; CHECK-NEXT:    fminnm d0, d0, d3
 ; CHECK-NEXT:    fcvtzu w8, d0
-; CHECK-NEXT:    fminnm d1, d1, d3
+; CHECK-NEXT:    mov d1, v0.d[1]
 ; CHECK-NEXT:    fmov s0, w8
 ; CHECK-NEXT:    fcvtzu w8, d1
 ; CHECK-NEXT:    mov v0.s[1], w8
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $q0
 ; CHECK-NEXT:    ret
     %x = call <2 x i32> @llvm.fptoui.sat.v2f64.v2i32(<2 x double> %f)
     ret <2 x i32> %x
 }

 ; CHECK-NEXT:    ret
     %x = call <2 x i50> @llvm.fptoui.sat.v2f64.v2i50(<2 x double> %f)
     ret <2 x i50> %x
 }
 
 define <2 x i64> @test_unsigned_v2f64_v2i64(<2 x double> %f) {
 ; CHECK-LABEL: test_unsigned_v2f64_v2i64:
 ; CHECK:       // %bb.0:
+; CHECK-NEXT:    fcvtzu x8, d0
 ; CHECK-NEXT:    mov d1, v0.d[1]
-; CHECK-NEXT:    mov x8, #4895412794951729151
-; CHECK-NEXT:    fmov d2, x8
+; CHECK-NEXT:    fmov d0, x8
 ; CHECK-NEXT:    fcvtzu x8, d1
-; CHECK-NEXT:    fcmp d1, #0.0
-; CHECK-NEXT:    csel x8, xzr, x8, lt
-; CHECK-NEXT:    fcmp d1, d2
-; CHECK-NEXT:    fcvtzu x9, d0
-; CHECK-NEXT:    csinv x8, x8, xzr, le
-; CHECK-NEXT:    fcmp d0, #0.0
-; CHECK-NEXT:    csel x9, xzr, x9, lt
-; CHECK-NEXT:    fcmp d0, d2
-; CHECK-NEXT:    csinv x9, x9, xzr, le
-; CHECK-NEXT:    fmov d0, x9
 ; CHECK-NEXT:    mov v0.d[1], x8
 ; CHECK-NEXT:    ret
     %x = call <2 x i64> @llvm.fptoui.sat.v2f64.v2i64(<2 x double> %f)
     ret <2 x i64> %x
 }
 
 define <2 x i100> @test_unsigned_v2f64_v2i100(<2 x double> %f) {
 ; CHECK-LABEL: test_unsigned_v2f64_v2i100:
; CHECK-NEXT:    ret
     %x = call <4 x i19> @llvm.fptoui.sat.v4f16.v4i19(<4 x half> %f)
     ret <4 x i19> %x
 }
 
 define <4 x i32> @test_unsigned_v4f16_v4i32_duplicate(<4 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v4f16_v4i32_duplicate:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    mov w8, #1333788671
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fmov s3, w8
+; CHECK-NEXT:    fcvt s1, h0
+; CHECK-NEXT:    mov h2, v0.h[1]
 ; CHECK-NEXT:    fcvtzu w8, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    fcvtzu w9, s2
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    mov h1, v0.h[2]
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s2, s3
+; CHECK-NEXT:    fcvt s2, h2
+; CHECK-NEXT:    fmov s1, w8
+; CHECK-NEXT:    fcvtzu w8, s2
+; CHECK-NEXT:    mov h2, v0.h[2]
 ; CHECK-NEXT:    mov h0, v0.h[3]
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    fmov s0, w9
-; CHECK-NEXT:    fcvtzu w9, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    csel w9, wzr, w9, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    mov v0.s[1], w8
+; CHECK-NEXT:    fcvt s2, h2
+; CHECK-NEXT:    fcvt s0, h0
+; CHECK-NEXT:    mov v1.s[1], w8
 ; CHECK-NEXT:    fcvtzu w8, s2
-; CHECK-NEXT:    csinv w9, w9, wzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
-; CHECK-NEXT:    csel w8, wzr, w8, lt
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    mov v0.s[2], w9
-; CHECK-NEXT:    csinv w8, w8, wzr, le
-; CHECK-NEXT:    mov v0.s[3], w8
+; CHECK-NEXT:    mov v1.s[2], w8
+; CHECK-NEXT:    fcvtzu w8, s0
+; CHECK-NEXT:    mov v1.s[3], w8
+; CHECK-NEXT:    mov v0.16b, v1.16b
 ; CHECK-NEXT:    ret
     %x = call <4 x i32> @llvm.fptoui.sat.v4f16.v4i32(<4 x half> %f)
     ret <4 x i32> %x
 }
 
 define <4 x i50> @test_unsigned_v4f16_v4i50(<4 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v4f16_v4i50:
 ; CHECK:       // %bb.0:
; CHECK-NEXT:    ret
     %x = call <4 x i50> @llvm.fptoui.sat.v4f16.v4i50(<4 x half> %f)
     ret <4 x i50> %x
 }
 
 define <4 x i64> @test_unsigned_v4f16_v4i64(<4 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v4f16_v4i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov h1, v0.h[1]
-; CHECK-NEXT:    mov w8, #1602224127
-; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    fmov s3, w8
+; CHECK-NEXT:    fcvt s1, h0
+; CHECK-NEXT:    mov h2, v0.h[1]
 ; CHECK-NEXT:    fcvtzu x8, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    fcvt s2, h0
-; CHECK-NEXT:    csel x8, xzr, x8, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    mov h1, v0.h[3]
-; CHECK-NEXT:    fcvtzu x9, s2
-; CHECK-NEXT:    csinv x8, x8, xzr, le
-; CHECK-NEXT:    fcmp s2, #0.0
+; CHECK-NEXT:    fcvt s1, h2
+; CHECK-NEXT:    fmov d2, x8
+; CHECK-NEXT:    fcvtzu x8, s1
+; CHECK-NEXT:    mov h1, v0.h[2]
+; CHECK-NEXT:    mov h0, v0.h[3]
 ; CHECK-NEXT:    fcvt s1, h1
-; CHECK-NEXT:    csel x9, xzr, x9, lt
-; CHECK-NEXT:    fcmp s2, s3
-; CHECK-NEXT:    mov h0, v0.h[2]
-; CHECK-NEXT:    csinv x9, x9, xzr, le
-; CHECK-NEXT:    fcvtzu x10, s1
-; CHECK-NEXT:    fcmp s1, #0.0
-; CHECK-NEXT:    fcvt s4, h0
-; CHECK-NEXT:    csel x10, xzr, x10, lt
-; CHECK-NEXT:    fcmp s1, s3
-; CHECK-NEXT:    fmov d0, x9
-; CHECK-NEXT:    fcvtzu x9, s4
-; CHECK-NEXT:    csinv x10, x10, xzr, le
-; CHECK-NEXT:    fcmp s4, #0.0
-; CHECK-NEXT:    csel x9, xzr, x9, lt
-; CHECK-NEXT:    fcmp s4, s3
-; CHECK-NEXT:    csinv x9, x9, xzr, le
-; CHECK-NEXT:    fmov d1, x9
-; CHECK-NEXT:    mov v0.d[1], x8
-; CHECK-NEXT:    mov v1.d[1], x10
+; CHECK-NEXT:    mov v2.d[1], x8
+; CHECK-NEXT:    fcvtzu x8, s1
+; CHECK-NEXT:    fcvt s0, h0
+; CHECK-NEXT:    fmov d1, x8
+; CHECK-NEXT:    fcvtzu x8, s0
+; CHECK-NEXT:    mov v1.d[1], x8
+; CHECK-NEXT:    mov v0.16b, v2.16b
 ; CHECK-NEXT:    ret
     %x = call <4 x i64> @llvm.fptoui.sat.v4f16.v4i64(<4 x half> %f)
     ret <4 x i64> %x
 }
 
 define <4 x i100> @test_unsigned_v4f16_v4i100(<4 x half> %f) {
 ; CHECK-LABEL: test_unsigned_v4f16_v4i100:
 ; CHECK:       // %bb.0:

llvm/test/CodeGen/AArch64/round-fptosi-sat-scalar.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-CVT
+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
+
+; Round towards minus infinity (fcvtms).
+
+define i32 @testmswh(half %a) {
+; CHECK-CVT-LABEL: testmswh:
+; CHECK-CVT:       // %bb.0: // %entry
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    frintm s0, s0
+; CHECK-CVT-NEXT:    fcvt h0, s0
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    fcvtzs w0, s0
+; CHECK-CVT-NEXT:    ret
+;
+; CHECK-FP16-LABEL: testmswh:
+; CHECK-FP16:       // %bb.0: // %entry
+; CHECK-FP16-NEXT:    fcvtms w0, h0
+; CHECK-FP16-NEXT:    ret
+entry:
+  %r = call half @llvm.floor.f16(half %a) nounwind readnone
+  %i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
+  ret i32 %i
+}
+
+define i64 @testmsxh(half %a) {
+; CHECK-CVT-LABEL: testmsxh:
+; CHECK-CVT:       // %bb.0: // %entry
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    frintm s0, s0
+; CHECK-CVT-NEXT:    fcvt h0, s0
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    fcvtzs x0, s0
+; CHECK-CVT-NEXT:    ret
+;
+; CHECK-FP16-LABEL: testmsxh:
+; CHECK-FP16:       // %bb.0: // %entry
+; CHECK-FP16-NEXT:    fcvtms x0, h0
+; CHECK-FP16-NEXT:    ret
+entry:
+  %r = call half @llvm.floor.f16(half %a) nounwind readnone
+  %i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
+  ret i64 %i
+}
+
+define i32 @testmsws(float %a) {
+; CHECK-LABEL: testmsws:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtms w0, s0
+; CHECK-NEXT:    ret
+entry:
+  %r = call float @floorf(float %a) nounwind readnone
+  %i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
+  ret i32 %i
+}
+
+define i64 @testmsxs(float %a) {
+; CHECK-LABEL: testmsxs:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtms x0, s0
+; CHECK-NEXT:    ret
+entry:
+  %r = call float @floorf(float %a) nounwind readnone
+  %i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
+  ret i64 %i
+}
+
+define i32 @testmswd(double %a) {
+; CHECK-LABEL: testmswd:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtms w0, d0
+; CHECK-NEXT:    ret
+entry:
+  %r = call double @floor(double %a) nounwind readnone
+  %i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
+  ret i32 %i
+}
+
+define i64 @testmsxd(double %a) {
+; CHECK-LABEL: testmsxd:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtms x0, d0
+; CHECK-NEXT:    ret
+entry:
+  %r = call double @floor(double %a) nounwind readnone
+  %i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
+  ret i64 %i
+}
+
+; Round towards plus infinity (fcvtps).
+
+define i32 @testpswh(half %a) {
+; CHECK-CVT-LABEL: testpswh:
+; CHECK-CVT:       // %bb.0: // %entry
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    frintp s0, s0
+; CHECK-CVT-NEXT:    fcvt h0, s0
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    fcvtzs w0, s0
+; CHECK-CVT-NEXT:    ret
+;
+; CHECK-FP16-LABEL: testpswh:
+; CHECK-FP16:       // %bb.0: // %entry
+; CHECK-FP16-NEXT:    fcvtps w0, h0
+; CHECK-FP16-NEXT:    ret
+entry:
+  %r = call half @llvm.ceil.f16(half %a) nounwind readnone
+  %i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
+  ret i32 %i
+}
+
+define i64 @testpsxh(half %a) {
+; CHECK-CVT-LABEL: testpsxh:
+; CHECK-CVT:       // %bb.0: // %entry
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    frintp s0, s0
+; CHECK-CVT-NEXT:    fcvt h0, s0
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    fcvtzs x0, s0
+; CHECK-CVT-NEXT:    ret
+;
+; CHECK-FP16-LABEL: testpsxh:
+; CHECK-FP16:       // %bb.0: // %entry
+; CHECK-FP16-NEXT:    fcvtps x0, h0
+; CHECK-FP16-NEXT:    ret
+entry:
+  %r = call half @llvm.ceil.f16(half %a) nounwind readnone
+  %i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
+  ret i64 %i
+}
+
+define i32 @testpsws(float %a) {
+; CHECK-LABEL: testpsws:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtps w0, s0
+; CHECK-NEXT:    ret
+entry:
+  %r = call float @ceilf(float %a) nounwind readnone
+  %i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
+  ret i32 %i
+}
+
+define i64 @testpsxs(float %a) {
+; CHECK-LABEL: testpsxs:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtps x0, s0
+; CHECK-NEXT:    ret
+entry:
+  %r = call float @ceilf(float %a) nounwind readnone
+  %i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
+  ret i64 %i
+}
+
+define i32 @testpswd(double %a) {
+; CHECK-LABEL: testpswd:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtps w0, d0
+; CHECK-NEXT:    ret
+entry:
+  %r = call double @ceil(double %a) nounwind readnone
+  %i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
+  ret i32 %i
+}
+
+define i64 @testpsxd(double %a) {
+; CHECK-LABEL: testpsxd:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtps x0, d0
+; CHECK-NEXT:    ret
+entry:
+  %r = call double @ceil(double %a) nounwind readnone
+  %i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
+  ret i64 %i
+}
+
+; Round towards zero (fcvtzs).
+
+define i32 @testzswh(half %a) {
+; CHECK-CVT-LABEL: testzswh:
+; CHECK-CVT:       // %bb.0: // %entry
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    frintz s0, s0
+; CHECK-CVT-NEXT:    fcvt h0, s0
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    fcvtzs w0, s0
+; CHECK-CVT-NEXT:    ret
+;
+; CHECK-FP16-LABEL: testzswh:
+; CHECK-FP16:       // %bb.0: // %entry
+; CHECK-FP16-NEXT:    fcvtzs w0, h0
+; CHECK-FP16-NEXT:    ret
+entry:
+  %r = call half @llvm.trunc.f16(half %a) nounwind readnone
+  %i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
+  ret i32 %i
+}
+
+define i64 @testzsxh(half %a) {
+; CHECK-CVT-LABEL: testzsxh:
+; CHECK-CVT:       // %bb.0: // %entry
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    frintz s0, s0
+; CHECK-CVT-NEXT:    fcvt h0, s0
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    fcvtzs x0, s0
+; CHECK-CVT-NEXT:    ret
+;
+; CHECK-FP16-LABEL: testzsxh:
+; CHECK-FP16:       // %bb.0: // %entry
+; CHECK-FP16-NEXT:    fcvtzs x0, h0
+; CHECK-FP16-NEXT:    ret
+entry:
+  %r = call half @llvm.trunc.f16(half %a) nounwind readnone
+  %i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
+  ret i64 %i
+}
+
+define i32 @testzsws(float %a) {
+; CHECK-LABEL: testzsws:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtzs w0, s0
+; CHECK-NEXT:    ret
+entry:
+  %r = call float @truncf(float %a) nounwind readnone
+  %i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
+  ret i32 %i
+}
+
+define i64 @testzsxs(float %a) {
+; CHECK-LABEL: testzsxs:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtzs x0, s0
+; CHECK-NEXT:    ret
+entry:
+  %r = call float @truncf(float %a) nounwind readnone
+  %i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
+  ret i64 %i
+}
+
+define i32 @testzswd(double %a) {
+; CHECK-LABEL: testzswd:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtzs w0, d0
+; CHECK-NEXT:    ret
+entry:
+  %r = call double @trunc(double %a) nounwind readnone
+  %i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
+  ret i32 %i
+}
+
+define i64 @testzsxd(double %a) {
+; CHECK-LABEL: testzsxd:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtzs x0, d0
+; CHECK-NEXT:    ret
+entry:
+  %r = call double @trunc(double %a) nounwind readnone
+  %i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
+  ret i64 %i
+}
+
+; Round to nearest, ties away from zero (fcvtas).
+
+define i32 @testaswh(half %a) {
+; CHECK-CVT-LABEL: testaswh:
+; CHECK-CVT:       // %bb.0: // %entry
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    frinta s0, s0
+; CHECK-CVT-NEXT:    fcvt h0, s0
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    fcvtzs w0, s0
+; CHECK-CVT-NEXT:    ret
+;
+; CHECK-FP16-LABEL: testaswh:
+; CHECK-FP16:       // %bb.0: // %entry
+; CHECK-FP16-NEXT:    fcvtas w0, h0
+; CHECK-FP16-NEXT:    ret
+entry:
+  %r = call half @llvm.round.f16(half %a) nounwind readnone
+  %i = call i32 @llvm.fptosi.sat.i32.f16(half %r)
+  ret i32 %i
+}
+
+define i64 @testasxh(half %a) {
+; CHECK-CVT-LABEL: testasxh:
+; CHECK-CVT:       // %bb.0: // %entry
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    frinta s0, s0
+; CHECK-CVT-NEXT:    fcvt h0, s0
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    fcvtzs x0, s0
+; CHECK-CVT-NEXT:    ret
+;
+; CHECK-FP16-LABEL: testasxh:
+; CHECK-FP16:       // %bb.0: // %entry
+; CHECK-FP16-NEXT:    fcvtas x0, h0
+; CHECK-FP16-NEXT:    ret
+entry:
+  %r = call half @llvm.round.f16(half %a) nounwind readnone
+  %i = call i64 @llvm.fptosi.sat.i64.f16(half %r)
+  ret i64 %i
+}
+
+define i32 @testasws(float %a) {
+; CHECK-LABEL: testasws:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtas w0, s0
+; CHECK-NEXT:    ret
+entry:
+  %r = call float @roundf(float %a) nounwind readnone
+  %i = call i32 @llvm.fptosi.sat.i32.f32(float %r)
+  ret i32 %i
+}
+
+define i64 @testasxs(float %a) {
+; CHECK-LABEL: testasxs:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtas x0, s0
+; CHECK-NEXT:    ret
+entry:
+  %r = call float @roundf(float %a) nounwind readnone
+  %i = call i64 @llvm.fptosi.sat.i64.f32(float %r)
+  ret i64 %i
+}
+
+define i32 @testaswd(double %a) {
+; CHECK-LABEL: testaswd:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtas w0, d0
+; CHECK-NEXT:    ret
+entry:
+  %r = call double @round(double %a) nounwind readnone
+  %i = call i32 @llvm.fptosi.sat.i32.f64(double %r)
+  ret i32 %i
+}
+
+define i64 @testasxd(double %a) {
+; CHECK-LABEL: testasxd:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtas x0, d0
+; CHECK-NEXT:    ret
+entry:
+  %r = call double @round(double %a) nounwind readnone
+  %i = call i64 @llvm.fptosi.sat.i64.f64(double %r)
+  ret i64 %i
+}
+
+declare i32 @llvm.fptosi.sat.i32.f16 (half)
+declare i64 @llvm.fptosi.sat.i64.f16 (half)
+declare i32 @llvm.fptosi.sat.i32.f32 (float)
+declare i64 @llvm.fptosi.sat.i64.f32 (float)
+declare i32 @llvm.fptosi.sat.i32.f64 (double)
+declare i64 @llvm.fptosi.sat.i64.f64 (double)
+
+declare half @llvm.floor.f16(half) nounwind readnone
+declare half @llvm.ceil.f16(half) nounwind readnone
+declare half @llvm.trunc.f16(half) nounwind readnone
+declare half @llvm.round.f16(half) nounwind readnone
+declare float @floorf(float) nounwind readnone
+declare float @ceilf(float) nounwind readnone
+declare float @truncf(float) nounwind readnone
+declare float @roundf(float) nounwind readnone
+declare double @floor(double) nounwind readnone
+declare double @ceil(double) nounwind readnone
+declare double @trunc(double) nounwind readnone
+declare double @round(double) nounwind readnone

llvm/test/CodeGen/AArch64/round-fptoui-sat-scalar.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-CVT
+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
+
+; Round towards minus infinity (fcvtmu).
+
+define i32 @testmuwh(half %a) {
+; CHECK-CVT-LABEL: testmuwh:
+; CHECK-CVT:       // %bb.0: // %entry
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    frintm s0, s0
+; CHECK-CVT-NEXT:    fcvt h0, s0
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    fcvtzu w0, s0
+; CHECK-CVT-NEXT:    ret
+;
+; CHECK-FP16-LABEL: testmuwh:
+; CHECK-FP16:       // %bb.0: // %entry
+; CHECK-FP16-NEXT:    fcvtmu w0, h0
+; CHECK-FP16-NEXT:    ret
+entry:
+  %r = call half @llvm.floor.f16(half %a) nounwind readnone
+  %i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
+  ret i32 %i
+}
+
+define i64 @testmuxh(half %a) {
+; CHECK-CVT-LABEL: testmuxh:
+; CHECK-CVT:       // %bb.0: // %entry
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    frintm s0, s0
+; CHECK-CVT-NEXT:    fcvt h0, s0
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    fcvtzu x0, s0
+; CHECK-CVT-NEXT:    ret
+;
+; CHECK-FP16-LABEL: testmuxh:
+; CHECK-FP16:       // %bb.0: // %entry
+; CHECK-FP16-NEXT:    fcvtmu x0, h0
+; CHECK-FP16-NEXT:    ret
+entry:
+  %r = call half @llvm.floor.f16(half %a) nounwind readnone
+  %i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
+  ret i64 %i
+}
+
+define i32 @testmuws(float %a) {
+; CHECK-LABEL: testmuws:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtmu w0, s0
+; CHECK-NEXT:    ret
+entry:
+  %r = call float @floorf(float %a) nounwind readnone
+  %i = call i32 @llvm.fptoui.sat.i32.f32(float %r)
+  ret i32 %i
+}
+
+define i64 @testmuxs(float %a) {
+; CHECK-LABEL: testmuxs:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtmu x0, s0
+; CHECK-NEXT:    ret
+entry:
+  %r = call float @floorf(float %a) nounwind readnone
+  %i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
+  ret i64 %i
+}
+
+define i32 @testmuwd(double %a) {
+; CHECK-LABEL: testmuwd:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtmu w0, d0
+; CHECK-NEXT:    ret
+entry:
+  %r = call double @floor(double %a) nounwind readnone
+  %i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
+  ret i32 %i
+}
+
+define i64 @testmuxd(double %a) {
+; CHECK-LABEL: testmuxd:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtmu x0, d0
+; CHECK-NEXT:    ret
+entry:
+  %r = call double @floor(double %a) nounwind readnone
+  %i = call i64 @llvm.fptoui.sat.i64.f64(double %r)
+  ret i64 %i
+}
+
+; Round towards plus infinity (fcvtpu).
+
+define i32 @testpuwh(half %a) {
+; CHECK-CVT-LABEL: testpuwh:
+; CHECK-CVT:       // %bb.0: // %entry
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    frintp s0, s0
+; CHECK-CVT-NEXT:    fcvt h0, s0
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    fcvtzu w0, s0
+; CHECK-CVT-NEXT:    ret
+;
+; CHECK-FP16-LABEL: testpuwh:
+; CHECK-FP16:       // %bb.0: // %entry
+; CHECK-FP16-NEXT:    fcvtpu w0, h0
+; CHECK-FP16-NEXT:    ret
+entry:
+  %r = call half @llvm.ceil.f16(half %a) nounwind readnone
+  %i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
+  ret i32 %i
+}
+
+define i64 @testpuxh(half %a) {
+; CHECK-CVT-LABEL: testpuxh:
+; CHECK-CVT:       // %bb.0: // %entry
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    frintp s0, s0
+; CHECK-CVT-NEXT:    fcvt h0, s0
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    fcvtzu x0, s0
+; CHECK-CVT-NEXT:    ret
+;
+; CHECK-FP16-LABEL: testpuxh:
+; CHECK-FP16:       // %bb.0: // %entry
+; CHECK-FP16-NEXT:    fcvtpu x0, h0
+; CHECK-FP16-NEXT:    ret
+entry:
+  %r = call half @llvm.ceil.f16(half %a) nounwind readnone
+  %i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
+  ret i64 %i
+}
+
+define i32 @testpuws(float %a) {
+; CHECK-LABEL: testpuws:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtpu w0, s0
+; CHECK-NEXT:    ret
+entry:
+  %r = call float @ceilf(float %a) nounwind readnone
+  %i = call i32 @llvm.fptoui.sat.i32.f32(float %r)
+  ret i32 %i
+}
+
+define i64 @testpuxs(float %a) {
+; CHECK-LABEL: testpuxs:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtpu x0, s0
+; CHECK-NEXT:    ret
+entry:
+  %r = call float @ceilf(float %a) nounwind readnone
+  %i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
+  ret i64 %i
+}
+
+define i32 @testpuwd(double %a) {
+; CHECK-LABEL: testpuwd:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtpu w0, d0
+; CHECK-NEXT:    ret
+entry:
+  %r = call double @ceil(double %a) nounwind readnone
+  %i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
+  ret i32 %i
+}
+
+define i64 @testpuxd(double %a) {
+; CHECK-LABEL: testpuxd:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtpu x0, d0
+; CHECK-NEXT:    ret
+entry:
+  %r = call double @ceil(double %a) nounwind readnone
+  %i = call i64 @llvm.fptoui.sat.i64.f64(double %r)
+  ret i64 %i
+}
+
+; Round towards zero (fcvtzu).
+
+define i32 @testzuwh(half %a) {
+; CHECK-CVT-LABEL: testzuwh:
+; CHECK-CVT:       // %bb.0: // %entry
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    frintz s0, s0
+; CHECK-CVT-NEXT:    fcvt h0, s0
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    fcvtzu w0, s0
+; CHECK-CVT-NEXT:    ret
+;
+; CHECK-FP16-LABEL: testzuwh:
+; CHECK-FP16:       // %bb.0: // %entry
+; CHECK-FP16-NEXT:    fcvtzu w0, h0
+; CHECK-FP16-NEXT:    ret
+entry:
+  %r = call half @llvm.trunc.f16(half %a) nounwind readnone
+  %i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
+  ret i32 %i
+}
+
+define i64 @testzuxh(half %a) {
+; CHECK-CVT-LABEL: testzuxh:
+; CHECK-CVT:       // %bb.0: // %entry
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    frintz s0, s0
+; CHECK-CVT-NEXT:    fcvt h0, s0
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    fcvtzu x0, s0
+; CHECK-CVT-NEXT:    ret
+;
+; CHECK-FP16-LABEL: testzuxh:
+; CHECK-FP16:       // %bb.0: // %entry
+; CHECK-FP16-NEXT:    fcvtzu x0, h0
+; CHECK-FP16-NEXT:    ret
+entry:
+  %r = call half @llvm.trunc.f16(half %a) nounwind readnone
+  %i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
+  ret i64 %i
+}
+
+define i32 @testzuws(float %a) {
+; CHECK-LABEL: testzuws:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtzu w0, s0
+; CHECK-NEXT:    ret
+entry:
+  %r = call float @truncf(float %a) nounwind readnone
+  %i = call i32 @llvm.fptoui.sat.i32.f32(float %r)
+  ret i32 %i
+}
+
+define i64 @testzuxs(float %a) {
+; CHECK-LABEL: testzuxs:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtzu x0, s0
+; CHECK-NEXT:    ret
+entry:
+  %r = call float @truncf(float %a) nounwind readnone
+  %i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
+  ret i64 %i
+}
+
+define i32 @testzuwd(double %a) {
+; CHECK-LABEL: testzuwd:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtzu w0, d0
+; CHECK-NEXT:    ret
+entry:
+  %r = call double @trunc(double %a) nounwind readnone
+  %i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
+  ret i32 %i
+}
+
+define i64 @testzuxd(double %a) {
+; CHECK-LABEL: testzuxd:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtzu x0, d0
+; CHECK-NEXT:    ret
+entry:
+  %r = call double @trunc(double %a) nounwind readnone
+  %i = call i64 @llvm.fptoui.sat.i64.f64(double %r)
+  ret i64 %i
+}
+
+; Round to nearest, ties away from zero (fcvtau).
+
+define i32 @testauwh(half %a) {
+; CHECK-CVT-LABEL: testauwh:
+; CHECK-CVT:       // %bb.0: // %entry
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    frinta s0, s0
+; CHECK-CVT-NEXT:    fcvt h0, s0
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    fcvtzu w0, s0
+; CHECK-CVT-NEXT:    ret
+;
+; CHECK-FP16-LABEL: testauwh:
+; CHECK-FP16:       // %bb.0: // %entry
+; CHECK-FP16-NEXT:    fcvtau w0, h0
+; CHECK-FP16-NEXT:    ret
+entry:
+  %r = call half @llvm.round.f16(half %a) nounwind readnone
+  %i = call i32 @llvm.fptoui.sat.i32.f16(half %r)
+  ret i32 %i
+}
+
+define i64 @testauxh(half %a) {
+; CHECK-CVT-LABEL: testauxh:
+; CHECK-CVT:       // %bb.0: // %entry
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    frinta s0, s0
+; CHECK-CVT-NEXT:    fcvt h0, s0
+; CHECK-CVT-NEXT:    fcvt s0, h0
+; CHECK-CVT-NEXT:    fcvtzu x0, s0
+; CHECK-CVT-NEXT:    ret
+;
+; CHECK-FP16-LABEL: testauxh:
+; CHECK-FP16:       // %bb.0: // %entry
+; CHECK-FP16-NEXT:    fcvtau x0, h0
+; CHECK-FP16-NEXT:    ret
+entry:
+  %r = call half @llvm.round.f16(half %a) nounwind readnone
+  %i = call i64 @llvm.fptoui.sat.i64.f16(half %r)
+  ret i64 %i
+}
+
+define i32 @testauws(float %a) {
+; CHECK-LABEL: testauws:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtau w0, s0
+; CHECK-NEXT:    ret
+entry:
+  %r = call float @roundf(float %a) nounwind readnone
+  %i = call i32 @llvm.fptoui.sat.i32.f32(float %r)
+  ret i32 %i
+}
+
+define i64 @testauxs(float %a) {
+; CHECK-LABEL: testauxs:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtau x0, s0
+; CHECK-NEXT:    ret
+entry:
+  %r = call float @roundf(float %a) nounwind readnone
+  %i = call i64 @llvm.fptoui.sat.i64.f32(float %r)
+  ret i64 %i
+}
+
+define i32 @testauwd(double %a) {
+; CHECK-LABEL: testauwd:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtau w0, d0
+; CHECK-NEXT:    ret
+entry:
+  %r = call double @round(double %a) nounwind readnone
+  %i = call i32 @llvm.fptoui.sat.i32.f64(double %r)
+  ret i32 %i
+}
+
+define i64 @testauxd(double %a) {
+; CHECK-LABEL: testauxd:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    fcvtau x0, d0
+; CHECK-NEXT:    ret
+entry:
+  %r = call double @round(double %a) nounwind readnone
+  %i = call i64 @llvm.fptoui.sat.i64.f64(double %r)
+  ret i64 %i
+}
+
+declare i32 @llvm.fptoui.sat.i32.f16 (half)
+declare i64 @llvm.fptoui.sat.i64.f16 (half)
+declare i32 @llvm.fptoui.sat.i32.f32 (float)
+declare i64 @llvm.fptoui.sat.i64.f32 (float)
+declare i32 @llvm.fptoui.sat.i32.f64 (double)
+declare i64 @llvm.fptoui.sat.i64.f64 (double)
+
+declare half @llvm.floor.f16(half) nounwind readnone
+declare half @llvm.ceil.f16(half) nounwind readnone
+declare half @llvm.trunc.f16(half) nounwind readnone
+declare half @llvm.round.f16(half) nounwind readnone
+declare float @floorf(float) nounwind readnone
+declare float @ceilf(float) nounwind readnone
+declare float @truncf(float) nounwind readnone
+declare float @roundf(float) nounwind readnone
+declare double @floor(double) nounwind readnone
+declare double @ceil(double) nounwind readnone
+declare double @trunc(double) nounwind readnone
+declare double @round(double) nounwind readnone