[RISCV] Use X0 as destination of inserted vsetvli when possible.

[craig.topper]

Summary

We aren't going to connect the result to anything so we might
as well avoid allocating a register.

[HsiangKai]

LGTM.

[HsiangKai]

To separate it from D101938, is it because the modification changes lots of test files?

[craig.topper]

In D102031#2743537, @HsiangKai wrote:

To separate it from D101938, is it because the modification changes lots of test files?

Yes. I was trying to make the test changes from D101938 easy to see.

[frasercrmck]

LGTM too. What a lot of changes.

[craig.topper]

Rebase on new insertion pass

[jrtc27]

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

361

Use the existing AVLReg variable rather than repeating the call?

[craig.topper]

Address review comment.

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags,
   return InstrInfo;
 }
 
 void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB, MachineInstr &MI,
                                        const VSETVLIInfo &Info) {
   DebugLoc DL = MI.getDebugLoc();
 
   if (Info.hasAVLImm()) {
-    // TODO: Use X0 as the destination.
-    Register DestReg = MRI->createVirtualRegister(&RISCV::GPRRegClass);
     BuildMI(MBB, MI, DL, TII->get(RISCV::PseudoVSETIVLI))
-        .addReg(DestReg, RegState::Define | RegState::Dead)
+        .addReg(RISCV::X0, RegState::Define | RegState::Dead)
         .addImm(Info.getAVLImm())
         .addImm(Info.encodeVTYPE());
     return;
   }
 
   Register AVLReg = Info.getAVLReg();
   if (AVLReg == RISCV::NoRegister) {
     BuildMI(MBB, MI, DL, TII->get(RISCV::PseudoVSETVLI))
         .addReg(RISCV::X0, RegState::Define | RegState::Dead)
         .addReg(RISCV::X0, RegState::Kill)
         .addImm(Info.encodeVTYPE())
         .addReg(RISCV::VL, RegState::Implicit);
     return;
   }
 
-  Register DestReg = MRI->createVirtualRegister(&RISCV::GPRRegClass);
+  // Use X0 as the DestReg unless AVLReg is X0.
+  Register DestReg = RISCV::X0;
+  if (AVLReg == RISCV::X0)
+    DestReg = MRI->createVirtualRegister(&RISCV::GPRRegClass);
   BuildMI(MBB, MI, DL, TII->get(RISCV::PseudoVSETVLI))
       .addReg(DestReg, RegState::Define | RegState::Dead)
-      .addReg(Info.getAVLReg())
+      .addReg(AVLReg)
       .addImm(Info.encodeVTYPE());
 }
 
 // Return a VSETVLIInfo representing the changes made by this VSETVLI or
 // VSETIVLI instruction.
 static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI) {
   VSETVLIInfo NewInfo;
   if (MI.getOpcode() == RISCV::PseudoVSETVLI) {