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Differential D101015

[RISCV] Have assembler check that the temp register is different than dest register for vmsgeu.vx pseudo.
ClosedPublic

Authored by craig.topper on Apr 21 2021, 8:09 PM.

Details

Reviewers
frasercrmck
evandro
HsiangKai
arcbbb
khchen
kito-cheng
Commits
rGfae1d31c0917: [RISCV] Have assembler check that the temp register is different than dest…

Diff Detail

Unit TestsFailed

TimeTest
50 msx64 debian > LLVM.MC/RISCV/rvv::invalid.s
0 msx64 debian > libomptarget.mapping::declare_mapper_nested_default_mappers_array.cpp
70 msx64 windows > LLVM.MC/RISCV/rvv::invalid.s

Event Timeline

craig.topper created this revision.Apr 21 2021, 8:09 PM
Herald added subscribers: StephenFan, vkmr, luismarques and 22 others. · View Herald TranscriptApr 21 2021, 8:09 PM
craig.topper requested review of this revision.Apr 21 2021, 8:09 PM
Herald added a project: Restricted Project. · View Herald TranscriptApr 21 2021, 8:09 PM
Herald added a subscriber: MaskRay. · View Herald Transcript
craig.topper updated this revision to Diff 339455.Apr 21 2021, 8:11 PM

Add the code change not just the test.

Herald added a subscriber: hiraditya. · View Herald TranscriptApr 21 2021, 8:11 PM
Harbormaster completed remote builds in B100143: Diff 339455.Apr 21 2021, 8:54 PM
Harbormaster completed remote builds in B100142: Diff 339454.Apr 21 2021, 9:21 PM
craig.topper retitled this revision from [RISCV] Add assembler check to make temp register is different than dest register for vmsgeu.vx pseudo. to [RISCV] Have assembler check that the temp register is different than dest register for vmsgeu.vx pseudo..Apr 22 2021, 9:12 PM
HsiangKai added a comment.Apr 23 2021, 12:01 AM

LGTM.

HsiangKai accepted this revision.Apr 23 2021, 12:55 AM
This revision is now accepted and ready to land.Apr 23 2021, 12:55 AM
This revision was landed with ongoing or failed builds.Apr 23 2021, 9:40 AM
Closed by commit rGfae1d31c0917: [RISCV] Have assembler check that the temp register is different than dest… (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rGfae1d31c0917: [RISCV] Have assembler check that the temp register is different than dest….

Revision Contents

PathSize
llvm/
test/
MC/
RISCV/
rvv/
6 lines

Diff 339454

llvm/test/MC/RISCV/rvv/invalid.s

Show First 20 Lines • Show All 660 Lines • ▼ Show 20 Lines
vs8r.v v7, (a0) vs8r.v v7, (a0)
# CHECK-ERROR: invalid operand for instruction # CHECK-ERROR: invalid operand for instruction
vmsge.vx v2, v4, a0, v0.t, v0 vmsge.vx v2, v4, a0, v0.t, v0
# CHECK-ERROR: invalid operand for instruction # CHECK-ERROR: invalid operand for instruction
vmsgeu.vx v2, v4, a0, v0.t, v0 vmsgeu.vx v2, v4, a0, v0.t, v0
# CHECK-ERROR: invalid operand for instruction # CHECK-ERROR: invalid operand for instruction
vmsge.vx v2, v4, a0, v0.t, v2
# CHECK-ERROR: The temporary vector register cannot be the same as the destination register.
vmsgeu.vx v2, v4, a0, v0.t, v2
# CHECK-ERROR: The temporary vector register cannot be the same as the destination register.