[AArch64] Adds memory operands for indexed loads.

[stelios-arm]

Summary

This patch adds memory operands for indexed loads so that certain optimizations can take place.

[SjoerdMeijer]

Thanks for fixing, this looks more correct to me (and consistent with other functions that transfer memops).

[stelios-arm]

Closed by git revision a655f250fef84795e3e46c0bcb824d7b5fbceec6.

llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

bool AArch64DAGToDAGISel::tryIndexedLoad(SDNode *N) {
   SDValue Base = LD->getBasePtr();
   ConstantSDNode *OffsetOp = cast<ConstantSDNode>(LD->getOffset());
   int OffsetVal = (int)OffsetOp->getZExtValue();
   SDLoc dl(N);
   SDValue Offset = CurDAG->getTargetConstant(OffsetVal, dl, MVT::i64);
   SDValue Ops[] = { Base, Offset, Chain };
   SDNode *Res = CurDAG->getMachineNode(Opcode, dl, MVT::i64, DstVT,
                                        MVT::Other, Ops);
+
+  // Transfer memoperands.
+  MachineMemOperand *MemOp = cast<MemSDNode>(N)->getMemOperand();
+  CurDAG->setNodeMemRefs(cast<MachineSDNode>(Res), {MemOp});
+
   // Either way, we're replacing the node, so tell the caller that.
   SDValue LoadedVal = SDValue(Res, 1);
   if (InsertTo64) {
     SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32);
     LoadedVal =
         SDValue(CurDAG->getMachineNode(
                     AArch64::SUBREG_TO_REG, dl, MVT::i64,
                     CurDAG->getTargetConstant(0, dl, MVT::i64), LoadedVal,

llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -consider-local-interval-cost -mtriple=aarch64-arm-none-eabi < %s | FileCheck %s
 
 @A = external dso_local local_unnamed_addr global [8 x [8 x i64]], align 8
 @B = external dso_local local_unnamed_addr global [8 x [8 x i64]], align 8
 @C = external dso_local local_unnamed_addr global [8 x [8 x i64]], align 8
 
 define dso_local void @run_test() local_unnamed_addr #0 {
 ; CHECK-LABEL: run_test:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    sub sp, sp, #80 // =80
-; CHECK-NEXT:    stp d15, d14, [sp, #16] // 16-byte Folded Spill
-; CHECK-NEXT:    stp d13, d12, [sp, #32] // 16-byte Folded Spill
-; CHECK-NEXT:    stp d11, d10, [sp, #48] // 16-byte Folded Spill
-; CHECK-NEXT:    stp d9, d8, [sp, #64] // 16-byte Folded Spill
-; CHECK-NEXT:    .cfi_def_cfa_offset 80
+; CHECK-NEXT:    stp d15, d14, [sp, #-64]! // 16-byte Folded Spill
+; CHECK-NEXT:    stp d13, d12, [sp, #16] // 16-byte Folded Spill
+; CHECK-NEXT:    stp d11, d10, [sp, #32] // 16-byte Folded Spill
+; CHECK-NEXT:    stp d9, d8, [sp, #48] // 16-byte Folded Spill
+; CHECK-NEXT:    .cfi_def_cfa_offset 64
 ; CHECK-NEXT:    .cfi_offset b8, -8
 ; CHECK-NEXT:    .cfi_offset b9, -16
 ; CHECK-NEXT:    .cfi_offset b10, -24
 ; CHECK-NEXT:    .cfi_offset b11, -32
 ; CHECK-NEXT:    .cfi_offset b12, -40
 ; CHECK-NEXT:    .cfi_offset b13, -48
 ; CHECK-NEXT:    .cfi_offset b14, -56
 ; CHECK-NEXT:    .cfi_offset b15, -64
 ; CHECK-NEXT:    adrp x10, B+48
 ; CHECK-NEXT:    adrp x11, A
 ; CHECK-NEXT:    mov x8, xzr
 ; CHECK-NEXT:    mov x9, xzr
 ; CHECK-NEXT:    movi v0.2d, #0000000000000000
 ; CHECK-NEXT:    add x10, x10, :lo12:B+48
 ; CHECK-NEXT:    add x11, x11, :lo12:A
-; CHECK-NEXT:    str q0, [sp] // 16-byte Folded Spill
 ; CHECK-NEXT:    // implicit-def: $q1
 ; CHECK-NEXT:    // implicit-def: $q2
 ; CHECK-NEXT:    // implicit-def: $q3
 ; CHECK-NEXT:    // implicit-def: $q4
 ; CHECK-NEXT:    // implicit-def: $q5
 ; CHECK-NEXT:    // implicit-def: $q6
 ; CHECK-NEXT:    // implicit-def: $q7
 ; CHECK-NEXT:    // implicit-def: $q16

 ; CHECK-NEXT:    // implicit-def: $q9
 ; CHECK-NEXT:    // implicit-def: $q10
 ; CHECK-NEXT:    // implicit-def: $q11
 ; CHECK-NEXT:    // implicit-def: $q12
 ; CHECK-NEXT:    // implicit-def: $q13
 ; CHECK-NEXT:  .LBB0_1: // %for.cond1.preheader
 ; CHECK-NEXT:    // =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    mov x12, xzr
-; CHECK-NEXT:    ldr q15, [x8]
 ; CHECK-NEXT:    ldr q14, [x12]
-; CHECK-NEXT:    ldr q0, [x10], #64
+; CHECK-NEXT:    ldr q15, [x8]
 ; CHECK-NEXT:    ldr x18, [x12]
+; CHECK-NEXT:    ldr x0, [x8]
+; CHECK-NEXT:    mov x12, v14.d[1]
+; CHECK-NEXT:    fmov x13, d14
+; CHECK-NEXT:    ldr q14, [x10], #64
 ; CHECK-NEXT:    fmov x15, d15
 ; CHECK-NEXT:    mov x14, v15.d[1]
-; CHECK-NEXT:    fmov x13, d14
 ; CHECK-NEXT:    mul x1, x15, x18
-; CHECK-NEXT:    mov x16, v0.d[1]
-; CHECK-NEXT:    fmov x17, d0
-; CHECK-NEXT:    fmov d0, x1
+; CHECK-NEXT:    mov x16, v14.d[1]
+; CHECK-NEXT:    fmov x17, d14
+; CHECK-NEXT:    fmov d14, x1
 ; CHECK-NEXT:    mul x1, x14, x18
-; CHECK-NEXT:    mov x12, v14.d[1]
-; CHECK-NEXT:    ldr x0, [x8]
-; CHECK-NEXT:    mov v0.d[1], x1
+; CHECK-NEXT:    mov v14.d[1], x1
 ; CHECK-NEXT:    mul x1, x13, x18
-; CHECK-NEXT:    add v12.2d, v12.2d, v0.2d
-; CHECK-NEXT:    fmov d0, x1
+; CHECK-NEXT:    add v12.2d, v12.2d, v14.2d
+; CHECK-NEXT:    fmov d14, x1
 ; CHECK-NEXT:    mul x1, x12, x18
-; CHECK-NEXT:    mov v0.d[1], x1
+; CHECK-NEXT:    mov v14.d[1], x1
 ; CHECK-NEXT:    mul x1, x17, x18
-; CHECK-NEXT:    add v13.2d, v13.2d, v0.2d
-; CHECK-NEXT:    add v11.2d, v11.2d, v0.2d
-; CHECK-NEXT:    fmov d0, x1
+; CHECK-NEXT:    add v13.2d, v13.2d, v14.2d
+; CHECK-NEXT:    add v11.2d, v11.2d, v14.2d
+; CHECK-NEXT:    fmov d14, x1
 ; CHECK-NEXT:    mul x18, x16, x18
-; CHECK-NEXT:    ldr q14, [sp] // 16-byte Folded Reload
-; CHECK-NEXT:    mov v0.d[1], x18
+; CHECK-NEXT:    mov v14.d[1], x18
 ; CHECK-NEXT:    mul x18, x15, x0
 ; CHECK-NEXT:    add x1, x11, x8
-; CHECK-NEXT:    add v10.2d, v10.2d, v0.2d
-; CHECK-NEXT:    fmov d0, x18
+; CHECK-NEXT:    add v10.2d, v10.2d, v14.2d
+; CHECK-NEXT:    fmov d14, x18
 ; CHECK-NEXT:    mul x18, x14, x0
 ; CHECK-NEXT:    ldr x1, [x1, #128]
-; CHECK-NEXT:    mov v0.d[1], x18
+; CHECK-NEXT:    mov v14.d[1], x18
 ; CHECK-NEXT:    mul x18, x13, x0
-; CHECK-NEXT:    add v8.2d, v8.2d, v0.2d
-; CHECK-NEXT:    add v25.2d, v25.2d, v0.2d
-; CHECK-NEXT:    add v22.2d, v22.2d, v0.2d
-; CHECK-NEXT:    add v18.2d, v18.2d, v0.2d
-; CHECK-NEXT:    add v6.2d, v6.2d, v0.2d
-; CHECK-NEXT:    add v14.2d, v14.2d, v0.2d
-; CHECK-NEXT:    fmov d0, x18
+; CHECK-NEXT:    add v8.2d, v8.2d, v14.2d
+; CHECK-NEXT:    add v25.2d, v25.2d, v14.2d
+; CHECK-NEXT:    add v22.2d, v22.2d, v14.2d
+; CHECK-NEXT:    add v18.2d, v18.2d, v14.2d
+; CHECK-NEXT:    add v6.2d, v6.2d, v14.2d
+; CHECK-NEXT:    add v0.2d, v0.2d, v14.2d
+; CHECK-NEXT:    fmov d14, x18
 ; CHECK-NEXT:    mul x18, x12, x0
-; CHECK-NEXT:    mov v0.d[1], x18
+; CHECK-NEXT:    mov v14.d[1], x18
 ; CHECK-NEXT:    mul x18, x17, x0
 ; CHECK-NEXT:    mul x0, x16, x0
-; CHECK-NEXT:    add v9.2d, v9.2d, v0.2d
-; CHECK-NEXT:    add v31.2d, v31.2d, v0.2d
-; CHECK-NEXT:    add v26.2d, v26.2d, v0.2d
-; CHECK-NEXT:    add v23.2d, v23.2d, v0.2d
-; CHECK-NEXT:    add v21.2d, v21.2d, v0.2d
-; CHECK-NEXT:    add v19.2d, v19.2d, v0.2d
-; CHECK-NEXT:    add v17.2d, v17.2d, v0.2d
-; CHECK-NEXT:    add v7.2d, v7.2d, v0.2d
-; CHECK-NEXT:    add v5.2d, v5.2d, v0.2d
-; CHECK-NEXT:    add v3.2d, v3.2d, v0.2d
-; CHECK-NEXT:    add v2.2d, v2.2d, v0.2d
-; CHECK-NEXT:    fmov d0, x18
+; CHECK-NEXT:    add v9.2d, v9.2d, v14.2d
+; CHECK-NEXT:    add v31.2d, v31.2d, v14.2d
+; CHECK-NEXT:    add v26.2d, v26.2d, v14.2d
+; CHECK-NEXT:    add v23.2d, v23.2d, v14.2d
+; CHECK-NEXT:    add v21.2d, v21.2d, v14.2d
+; CHECK-NEXT:    add v19.2d, v19.2d, v14.2d
+; CHECK-NEXT:    add v17.2d, v17.2d, v14.2d
+; CHECK-NEXT:    add v7.2d, v7.2d, v14.2d
+; CHECK-NEXT:    add v5.2d, v5.2d, v14.2d
+; CHECK-NEXT:    add v3.2d, v3.2d, v14.2d
+; CHECK-NEXT:    add v2.2d, v2.2d, v14.2d
+; CHECK-NEXT:    fmov d14, x18
 ; CHECK-NEXT:    mul x15, x15, x1
-; CHECK-NEXT:    mov v0.d[1], x0
+; CHECK-NEXT:    mov v14.d[1], x0
 ; CHECK-NEXT:    mul x14, x14, x1
-; CHECK-NEXT:    add v30.2d, v30.2d, v0.2d
-; CHECK-NEXT:    add v24.2d, v24.2d, v0.2d
-; CHECK-NEXT:    add v20.2d, v20.2d, v0.2d
-; CHECK-NEXT:    add v16.2d, v16.2d, v0.2d
-; CHECK-NEXT:    add v4.2d, v4.2d, v0.2d
-; CHECK-NEXT:    add v1.2d, v1.2d, v0.2d
-; CHECK-NEXT:    fmov d0, x15
+; CHECK-NEXT:    add v30.2d, v30.2d, v14.2d
+; CHECK-NEXT:    add v24.2d, v24.2d, v14.2d
+; CHECK-NEXT:    add v20.2d, v20.2d, v14.2d
+; CHECK-NEXT:    add v16.2d, v16.2d, v14.2d
+; CHECK-NEXT:    add v4.2d, v4.2d, v14.2d
+; CHECK-NEXT:    add v1.2d, v1.2d, v14.2d
+; CHECK-NEXT:    fmov d14, x15
 ; CHECK-NEXT:    mul x13, x13, x1
-; CHECK-NEXT:    mov v0.d[1], x14
+; CHECK-NEXT:    mov v14.d[1], x14
 ; CHECK-NEXT:    mul x12, x12, x1
-; CHECK-NEXT:    add v29.2d, v29.2d, v0.2d
-; CHECK-NEXT:    fmov d0, x13
+; CHECK-NEXT:    add v29.2d, v29.2d, v14.2d
+; CHECK-NEXT:    fmov d14, x13
 ; CHECK-NEXT:    mul x17, x17, x1
-; CHECK-NEXT:    mov v0.d[1], x12
+; CHECK-NEXT:    mov v14.d[1], x12
 ; CHECK-NEXT:    mul x16, x16, x1
-; CHECK-NEXT:    add v28.2d, v28.2d, v0.2d
-; CHECK-NEXT:    fmov d0, x17
-; CHECK-NEXT:    mov v0.d[1], x16
+; CHECK-NEXT:    add v28.2d, v28.2d, v14.2d
+; CHECK-NEXT:    fmov d14, x17
+; CHECK-NEXT:    mov v14.d[1], x16
 ; CHECK-NEXT:    add x8, x8, #8 // =8
-; CHECK-NEXT:    add v27.2d, v27.2d, v0.2d
+; CHECK-NEXT:    add v27.2d, v27.2d, v14.2d
 ; CHECK-NEXT:    cmp x8, #64 // =64
 ; CHECK-NEXT:    add x9, x9, #1 // =1
-; CHECK-NEXT:    str q14, [sp] // 16-byte Folded Spill
 ; CHECK-NEXT:    b.ne .LBB0_1
 ; CHECK-NEXT:  // %bb.2: // %for.cond.cleanup
 ; CHECK-NEXT:    adrp x8, C
 ; CHECK-NEXT:    add x8, x8, :lo12:C
-; CHECK-NEXT:    ldr q0, [sp] // 16-byte Folded Reload
 ; CHECK-NEXT:    stp q13, q12, [x8]
 ; CHECK-NEXT:    stp q11, q10, [x8, #32]
 ; CHECK-NEXT:    stp q9, q8, [x8, #64]
-; CHECK-NEXT:    ldp d9, d8, [sp, #64] // 16-byte Folded Reload
-; CHECK-NEXT:    ldp d11, d10, [sp, #48] // 16-byte Folded Reload
-; CHECK-NEXT:    ldp d13, d12, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT:    ldp d15, d14, [sp, #16] // 16-byte Folded Reload
+; CHECK-NEXT:    ldp d9, d8, [sp, #48] // 16-byte Folded Reload
+; CHECK-NEXT:    ldp d11, d10, [sp, #32] // 16-byte Folded Reload
+; CHECK-NEXT:    ldp d13, d12, [sp, #16] // 16-byte Folded Reload
 ; CHECK-NEXT:    stp q31, q30, [x8, #96]
 ; CHECK-NEXT:    stp q29, q28, [x8, #144]
 ; CHECK-NEXT:    stp q27, q26, [x8, #176]
 ; CHECK-NEXT:    str q25, [x8, #208]
 ; CHECK-NEXT:    stp q24, q23, [x8, #240]
 ; CHECK-NEXT:    stp q22, q21, [x8, #272]
 ; CHECK-NEXT:    stp q20, q19, [x8, #304]
 ; CHECK-NEXT:    stp q18, q17, [x8, #336]
 ; CHECK-NEXT:    stp q16, q7, [x8, #368]
 ; CHECK-NEXT:    stp q6, q5, [x8, #400]
 ; CHECK-NEXT:    stp q4, q3, [x8, #432]
 ; CHECK-NEXT:    stp q0, q2, [x8, #464]
 ; CHECK-NEXT:    str q1, [x8, #496]
-; CHECK-NEXT:    add sp, sp, #80 // =80
+; CHECK-NEXT:    ldp d15, d14, [sp], #64 // 16-byte Folded Reload
 ; CHECK-NEXT:    ret
 entry:
   br label %for.cond1.preheader
 
 for.cond1.preheader:                              ; preds = %for.cond1.preheader, %entry
   %0 = phi <2 x i64> [ undef, %entry ], [ %118, %for.cond1.preheader ]
   %1 = phi <2 x i64> [ undef, %entry ], [ %116, %for.cond1.preheader ]
   %2 = phi <2 x i64> [ zeroinitializer, %entry ], [ %114, %for.cond1.preheader ]