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Differential D100096

[RISCV] Support vector SET[U]LT and SET[U]GE with splatted immediates
ClosedPublic

Authored by frasercrmck on Apr 8 2021, 3:59 AM.

Details

Reviewers
craig.topper
evandro
rogfer01
HsiangKai
khchen
arcbbb
Commits
rGd737c4713736: [RISCV] Support vector SET[U]LT and SET[U]GE with splatted immediates
Summary

This patch adds more optimized codegen for the above SETCC forms,
by matching the '.vi' vector forms when the immediate is a 5-bit signed
immediate plus 1. The immediate can be decremented and the corresponding
SET[U]LE or SET[U]GT forms can be matched.

This work was left as a TODO from D94168.

Diff Detail

Event Timeline

frasercrmck created this revision.Apr 8 2021, 3:59 AM
Herald added subscribers: vkmr, luismarques, apazos and 22 others. · View Herald TranscriptApr 8 2021, 3:59 AM
frasercrmck requested review of this revision.Apr 8 2021, 3:59 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 8 2021, 3:59 AM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
frasercrmck retitled this revision from [RISCV] Support vector SET[U]LT and SET[U]GE with spatted immediates to [RISCV] Support vector SET[U]LT and SET[U]GE with splatted immediates.Apr 8 2021, 4:02 AM
frasercrmck added inline comments.Apr 8 2021, 4:16 AM
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
1153

I was unsure of this function pointer approach but duplicating all of what was selectVSplatSimm5 felt silly. It seemed to generate better code than using std::function<bool(int64_t)> but my X86 isn't where it should be.

Harbormaster completed remote builds in B97690: Diff 336055.Apr 8 2021, 4:36 AM
craig.topper added inline comments.Apr 8 2021, 9:55 AM
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
433

Are we confident that we'll never see SETULT/SETUGE with a 0 splat? It doesn't happen for simple cases, but I wonder if the constant can appear later and our target specific nodes like RISCVISD::VMV_V_X_VL or RISCVISD::SPLAT_VECTOR_I64 can prevent setcc optimizations from seeing it.

frasercrmck updated this revision to Diff 336795.Apr 12 2021, 3:37 AM
  • rebase
  • test and fix for unsigned comparisons with 0
frasercrmck marked an inline comment as done.Apr 12 2021, 3:38 AM
frasercrmck added inline comments.
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
433

Yes, you're right. I've fixed that now, and added a couple of tests using the vmv.v.x intrinsic to check it's not misoptimized.

Harbormaster completed remote builds in B98247: Diff 336795.Apr 12 2021, 4:17 AM
craig.topper accepted this revision.Apr 12 2021, 9:37 AM

LGTM

This revision is now accepted and ready to land.Apr 12 2021, 9:37 AM
Closed by commit rGd737c4713736: [RISCV] Support vector SET[U]LT and SET[U]GE with splatted immediates (authored by frasercrmck). · Explain WhyApr 12 2021, 10:43 AM
This revision was automatically updated to reflect the committed changes.
frasercrmck marked an inline comment as done.
frasercrmck added a commit: rGd737c4713736: [RISCV] Support vector SET[U]LT and SET[U]GE with splatted immediates.

Revision Contents

Diff 336055

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h

Show First 20 Lines • Show All 58 Lines • ▼ Show 20 Linespublic:
bool MatchSLLIUW(SDNode *N) const; bool MatchSLLIUW(SDNode *N) const;
bool selectVLOp(SDValue N, SDValue &VL); bool selectVLOp(SDValue N, SDValue &VL);
bool selectVSplat(SDValue N, SDValue &SplatVal); bool selectVSplat(SDValue N, SDValue &SplatVal);
bool selectVSplatSimm5(SDValue N, SDValue &SplatVal); bool selectVSplatSimm5(SDValue N, SDValue &SplatVal);
bool selectVSplatUimm5(SDValue N, SDValue &SplatVal); bool selectVSplatUimm5(SDValue N, SDValue &SplatVal);
bool selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal);
bool selectRVVSimm5(SDValue N, unsigned Width, SDValue &Imm); bool selectRVVSimm5(SDValue N, unsigned Width, SDValue &Imm);
template <unsigned Width> bool selectRVVSimm5(SDValue N, SDValue &Imm) { template <unsigned Width> bool selectRVVSimm5(SDValue N, SDValue &Imm) {
return selectRVVSimm5(N, Width, Imm); return selectRVVSimm5(N, Width, Imm);
} }
bool selectRVVUimm5(SDValue N, unsigned Width, SDValue &Imm); bool selectRVVUimm5(SDValue N, unsigned Width, SDValue &Imm);
template <unsigned Width> bool selectRVVUimm5(SDValue N, SDValue &Imm) { template <unsigned Width> bool selectRVVUimm5(SDValue N, SDValue &Imm) {
▲ Show 20 Lines • Show All 102 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Show First 20 Lines • Show All 1,144 Lines • ▼ Show 20 Linesbool RISCVDAGToDAGISel::selectVSplat(SDValue N, SDValue &SplatVal) {
if (N.getOpcode() != ISD::SPLAT_VECTOR && if (N.getOpcode() != ISD::SPLAT_VECTOR &&
N.getOpcode() != RISCVISD::SPLAT_VECTOR_I64 && N.getOpcode() != RISCVISD::SPLAT_VECTOR_I64 &&
N.getOpcode() != RISCVISD::VMV_V_X_VL) N.getOpcode() != RISCVISD::VMV_V_X_VL)
return false; return false;
SplatVal = N.getOperand(0); SplatVal = N.getOperand(0);
return true; return true;
} }
bool RISCVDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &SplatVal) { using ValidateFn = bool (*)(int64_t);
frasercrmckAuthorUnsubmitted
Done
ReplyInline Actions

I was unsure of this function pointer approach but duplicating all of what was selectVSplatSimm5 felt silly. It seemed to generate better code than using std::function<bool(int64_t)> but my X86 isn't where it should be.

frasercrmck: I was unsure of this function pointer approach but duplicating all of what was…
static bool selectVSplatSimmHelper(SDValue N, SDValue &SplatVal,
SelectionDAG &DAG,
const RISCVSubtarget &Subtarget,
ValidateFn ValidateImm) {
if ((N.getOpcode() != ISD::SPLAT_VECTOR && if ((N.getOpcode() != ISD::SPLAT_VECTOR &&
N.getOpcode() != RISCVISD::SPLAT_VECTOR_I64 && N.getOpcode() != RISCVISD::SPLAT_VECTOR_I64 &&
N.getOpcode() != RISCVISD::VMV_V_X_VL) || N.getOpcode() != RISCVISD::VMV_V_X_VL) ||
!isa<ConstantSDNode>(N.getOperand(0))) !isa<ConstantSDNode>(N.getOperand(0)))
return false; return false;
int64_t SplatImm = cast<ConstantSDNode>(N.getOperand(0))->getSExtValue(); int64_t SplatImm = cast<ConstantSDNode>(N.getOperand(0))->getSExtValue();
// Both ISD::SPLAT_VECTOR and RISCVISD::SPLAT_VECTOR_I64 share semantics when // ISD::SPLAT_VECTOR, RISCVISD::SPLAT_VECTOR_I64 and RISCVISD::VMV_V_X_VL
// the operand type is wider than the resulting vector element type: an // share semantics when the operand type is wider than the resulting vector
// implicit truncation first takes place. Therefore, perform a manual // element type: an implicit truncation first takes place. Therefore, perform
// truncation/sign-extension in order to ignore any truncated bits and catch // a manual truncation/sign-extension in order to ignore any truncated bits
// any zero-extended immediate. // and catch any zero-extended immediate.
// For example, we wish to match (i8 -1) -> (XLenVT 255) as a simm5 by first // For example, we wish to match (i8 -1) -> (XLenVT 255) as a simm5 by first
// sign-extending to (XLenVT -1). // sign-extending to (XLenVT -1).
MVT XLenVT = Subtarget->getXLenVT(); MVT XLenVT = Subtarget.getXLenVT();
assert(XLenVT == N.getOperand(0).getSimpleValueType() && assert(XLenVT == N.getOperand(0).getSimpleValueType() &&
"Unexpected splat operand type"); "Unexpected splat operand type");
MVT EltVT = N.getSimpleValueType().getVectorElementType(); MVT EltVT = N.getSimpleValueType().getVectorElementType();
if (EltVT.bitsLT(XLenVT)) { if (EltVT.bitsLT(XLenVT))
SplatImm = SignExtend64(SplatImm, EltVT.getSizeInBits()); SplatImm = SignExtend64(SplatImm, EltVT.getSizeInBits());
}
if (!isInt<5>(SplatImm)) if (!ValidateImm(SplatImm))
return false; return false;
SplatVal = CurDAG->getTargetConstant(SplatImm, SDLoc(N), XLenVT); SplatVal = DAG.getTargetConstant(SplatImm, SDLoc(N), XLenVT);
return true; return true;
} }
bool RISCVDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &SplatVal) {
return selectVSplatSimmHelper(N, SplatVal, *CurDAG, *Subtarget,
[](int64_t Imm) { return isInt<5>(Imm); });
}
bool RISCVDAGToDAGISel::selectVSplatSimm5Plus1(SDValue N, SDValue &SplatVal) {
return selectVSplatSimmHelper(
N, SplatVal, *CurDAG, *Subtarget,
[](int64_t Imm) { return (isInt<5>(Imm) && Imm != -16) || Imm == 16; });
}
bool RISCVDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &SplatVal) { bool RISCVDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &SplatVal) {
if ((N.getOpcode() != ISD::SPLAT_VECTOR && if ((N.getOpcode() != ISD::SPLAT_VECTOR &&
N.getOpcode() != RISCVISD::SPLAT_VECTOR_I64 && N.getOpcode() != RISCVISD::SPLAT_VECTOR_I64 &&
N.getOpcode() != RISCVISD::VMV_V_X_VL) || N.getOpcode() != RISCVISD::VMV_V_X_VL) ||
!isa<ConstantSDNode>(N.getOperand(0))) !isa<ConstantSDNode>(N.getOperand(0)))
return false; return false;
int64_t SplatImm = cast<ConstantSDNode>(N.getOperand(0))->getSExtValue(); int64_t SplatImm = cast<ConstantSDNode>(N.getOperand(0))->getSExtValue();
▲ Show 20 Lines • Show All 158 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Show All 26 Lines
]>; ]>;
def rv32_splat_i64 : SDNode<"RISCVISD::SPLAT_VECTOR_I64", SDTSplatI64>; def rv32_splat_i64 : SDNode<"RISCVISD::SPLAT_VECTOR_I64", SDTSplatI64>;
// Give explicit Complexity to prefer simm5/uimm5. // Give explicit Complexity to prefer simm5/uimm5.
def SplatPat : ComplexPattern<vAny, 1, "selectVSplat", [splat_vector, rv32_splat_i64], [], 1>; def SplatPat : ComplexPattern<vAny, 1, "selectVSplat", [splat_vector, rv32_splat_i64], [], 1>;
def SplatPat_simm5 : ComplexPattern<vAny, 1, "selectVSplatSimm5", [splat_vector, rv32_splat_i64], [], 2>; def SplatPat_simm5 : ComplexPattern<vAny, 1, "selectVSplatSimm5", [splat_vector, rv32_splat_i64], [], 2>;
def SplatPat_uimm5 : ComplexPattern<vAny, 1, "selectVSplatUimm5", [splat_vector, rv32_splat_i64], [], 2>; def SplatPat_uimm5 : ComplexPattern<vAny, 1, "selectVSplatUimm5", [splat_vector, rv32_splat_i64], [], 2>;
def SplatPat_simm5_plus1
: ComplexPattern<vAny, 1, "selectVSplatSimm5Plus1", [splat_vector, rv32_splat_i64], [], 2>;
class SwapHelper<dag Prefix, dag A, dag B, dag Suffix, bit swap> { class SwapHelper<dag Prefix, dag A, dag B, dag Suffix, bit swap> {
dag Value = !con(Prefix, !if(swap, B, A), !if(swap, A, B), Suffix); dag Value = !con(Prefix, !if(swap, B, A), !if(swap, A, B), Suffix);
} }
multiclass VPatUSLoadStoreSDNode<ValueType type, multiclass VPatUSLoadStoreSDNode<ValueType type,
int sew, int sew,
LMULInfo vlmul, LMULInfo vlmul,
▲ Show 20 Lines • Show All 207 Lines • ▼ Show 20 Linesmulticlass VPatIntegerSetCCSDNode_VX_VI<CondCode cc,
string instruction_name, string instruction_name,
bit swap = 0> { bit swap = 0> {
defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VX", defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VX",
SplatPat, GPR, swap>; SplatPat, GPR, swap>;
defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VI", defm : VPatIntegerSetCCSDNode_XI<cc, instruction_name, "VI",
SplatPat_simm5, simm5, swap>; SplatPat_simm5, simm5, swap>;
} }
multiclass VPatIntegerSetCCSDNode_VIPlus1<CondCode cc,
string instruction_name> {
foreach vti = AllIntegerVectors in {
defvar instruction = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX);
def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
(vti.Vector (SplatPat_simm5_plus1 simm5_plus1:$rs2)),
cc)),
(instruction vti.RegClass:$rs1, (DecImm simm5_plus1:$rs2),
vti.AVL, vti.SEW)>;
}
}
multiclass VPatFPSetCCSDNode_VV_VF_FV<CondCode cc, multiclass VPatFPSetCCSDNode_VV_VF_FV<CondCode cc,
string inst_name, string inst_name,
string swapped_op_inst_name> { string swapped_op_inst_name> {
foreach fvti = AllFloatVectors in { foreach fvti = AllFloatVectors in {
def : Pat<(fvti.Mask (setcc (fvti.Vector fvti.RegClass:$rs1), def : Pat<(fvti.Mask (setcc (fvti.Vector fvti.RegClass:$rs1),
(fvti.Vector fvti.RegClass:$rs2), (fvti.Vector fvti.RegClass:$rs2),
cc)), cc)),
(!cast<Instruction>(inst_name#"_VV_"#fvti.LMul.MX) (!cast<Instruction>(inst_name#"_VV_"#fvti.LMul.MX)
▲ Show 20 Lines • Show All 142 Lines • ▼ Show 20 Lines
defm "" : VPatBinarySDNode_VV_VX_VI<shl, "PseudoVSLL", uimm5>; defm "" : VPatBinarySDNode_VV_VX_VI<shl, "PseudoVSLL", uimm5>;
defm "" : VPatBinarySDNode_VV_VX_VI<srl, "PseudoVSRL", uimm5>; defm "" : VPatBinarySDNode_VV_VX_VI<srl, "PseudoVSRL", uimm5>;
defm "" : VPatBinarySDNode_VV_VX_VI<sra, "PseudoVSRA", uimm5>; defm "" : VPatBinarySDNode_VV_VX_VI<sra, "PseudoVSRA", uimm5>;
// 12.8. Vector Integer Comparison Instructions // 12.8. Vector Integer Comparison Instructions
defm "" : VPatIntegerSetCCSDNode_VV_VX_VI<SETEQ, "PseudoVMSEQ">; defm "" : VPatIntegerSetCCSDNode_VV_VX_VI<SETEQ, "PseudoVMSEQ">;
defm "" : VPatIntegerSetCCSDNode_VV_VX_VI<SETNE, "PseudoVMSNE">; defm "" : VPatIntegerSetCCSDNode_VV_VX_VI<SETNE, "PseudoVMSNE">;
// FIXME: Support immediate forms of these by choosing SLE decrementing the
// immediate
defm "" : VPatIntegerSetCCSDNode_VV_VX<SETLT, "PseudoVMSLT">; defm "" : VPatIntegerSetCCSDNode_VV_VX<SETLT, "PseudoVMSLT">;
defm "" : VPatIntegerSetCCSDNode_VV_VX<SETULT, "PseudoVMSLTU">; defm "" : VPatIntegerSetCCSDNode_VV_VX<SETULT, "PseudoVMSLTU">;
defm "" : VPatIntegerSetCCSDNode_VIPlus1<SETLT, "PseudoVMSLE">;
defm "" : VPatIntegerSetCCSDNode_VIPlus1<SETULT, "PseudoVMSLEU">;
craig.topperUnsubmitted
Done
ReplyInline Actions

Are we confident that we'll never see SETULT/SETUGE with a 0 splat? It doesn't happen for simple cases, but I wonder if the constant can appear later and our target specific nodes like RISCVISD::VMV_V_X_VL or RISCVISD::SPLAT_VECTOR_I64 can prevent setcc optimizations from seeing it.

craig.topper: Are we confident that we'll never see SETULT/SETUGE with a 0 splat? It doesn't happen for…
frasercrmckAuthorUnsubmitted
Done
ReplyInline Actions

Yes, you're right. I've fixed that now, and added a couple of tests using the vmv.v.x intrinsic to check it's not misoptimized.

frasercrmck: Yes, you're right. I've fixed that now, and added a couple of tests using the `vmv.v.x`…
defm "" : VPatIntegerSetCCSDNode_VV<SETGT, "PseudoVMSLT", /*swap*/1>; defm "" : VPatIntegerSetCCSDNode_VV<SETGT, "PseudoVMSLT", /*swap*/1>;
defm "" : VPatIntegerSetCCSDNode_VV<SETUGT, "PseudoVMSLTU", /*swap*/1>; defm "" : VPatIntegerSetCCSDNode_VV<SETUGT, "PseudoVMSLTU", /*swap*/1>;
defm "" : VPatIntegerSetCCSDNode_VX_VI<SETGT, "PseudoVMSGT">; defm "" : VPatIntegerSetCCSDNode_VX_VI<SETGT, "PseudoVMSGT">;
defm "" : VPatIntegerSetCCSDNode_VX_VI<SETUGT, "PseudoVMSGTU">; defm "" : VPatIntegerSetCCSDNode_VX_VI<SETUGT, "PseudoVMSGTU">;
defm "" : VPatIntegerSetCCSDNode_VV_VX_VI<SETLE, "PseudoVMSLE">; defm "" : VPatIntegerSetCCSDNode_VV_VX_VI<SETLE, "PseudoVMSLE">;
defm "" : VPatIntegerSetCCSDNode_VV_VX_VI<SETULE, "PseudoVMSLEU">; defm "" : VPatIntegerSetCCSDNode_VV_VX_VI<SETULE, "PseudoVMSLEU">;
// FIXME: Support immediate forms of these by choosing SGT and decrementing the
// immediate
defm "" : VPatIntegerSetCCSDNode_VV<SETGE, "PseudoVMSLE", /*swap*/1>; defm "" : VPatIntegerSetCCSDNode_VV<SETGE, "PseudoVMSLE", /*swap*/1>;
defm "" : VPatIntegerSetCCSDNode_VV<SETUGE, "PseudoVMSLEU", /*swap*/1>; defm "" : VPatIntegerSetCCSDNode_VV<SETUGE, "PseudoVMSLEU", /*swap*/1>;
defm "" : VPatIntegerSetCCSDNode_VIPlus1<SETGE, "PseudoVMSGT">;
defm "" : VPatIntegerSetCCSDNode_VIPlus1<SETUGE, "PseudoVMSGTU">;
// 12.9. Vector Integer Min/Max Instructions // 12.9. Vector Integer Min/Max Instructions
defm "" : VPatBinarySDNode_VV_VX<umin, "PseudoVMINU">; defm "" : VPatBinarySDNode_VV_VX<umin, "PseudoVMINU">;
defm "" : VPatBinarySDNode_VV_VX<smin, "PseudoVMIN">; defm "" : VPatBinarySDNode_VV_VX<smin, "PseudoVMIN">;
defm "" : VPatBinarySDNode_VV_VX<umax, "PseudoVMAXU">; defm "" : VPatBinarySDNode_VV_VX<umax, "PseudoVMAXU">;
defm "" : VPatBinarySDNode_VV_VX<smax, "PseudoVMAX">; defm "" : VPatBinarySDNode_VV_VX<smax, "PseudoVMAX">;
// 12.10. Vector Single-Width Integer Multiply Instructions // 12.10. Vector Single-Width Integer Multiply Instructions
▲ Show 20 Lines • Show All 295 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Show First 20 Lines • Show All 390 Lines • ▼ Show 20 Lines def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat GPR:$rs2),
(vti.Mask true_mask), (vti.Mask true_mask),
(XLenVT (VLOp GPR:$vl)))), (XLenVT (VLOp GPR:$vl)))),
(instruction vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.SEW)>; (instruction vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.SEW)>;
} }
multiclass VPatIntegerSetCCVL_VI_Swappable<VTypeInfo vti, string instruction_name, multiclass VPatIntegerSetCCVL_VI_Swappable<VTypeInfo vti, string instruction_name,
CondCode cc, CondCode invcc> { CondCode cc, CondCode invcc> {
defvar instruction = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX); defvar instruction = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX);
defvar ImmPat = !cast<ComplexPattern>("sew"#vti.SEW#"simm5");
def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1), def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
(SplatPat_simm5 simm5:$rs2), cc, (SplatPat_simm5 simm5:$rs2), cc,
(vti.Mask true_mask), (vti.Mask true_mask),
(XLenVT (VLOp GPR:$vl)))), (XLenVT (VLOp GPR:$vl)))),
(instruction vti.RegClass:$rs1, XLenVT:$rs2, GPR:$vl, vti.SEW)>; (instruction vti.RegClass:$rs1, XLenVT:$rs2, GPR:$vl, vti.SEW)>;
def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat_simm5 simm5:$rs2), def : Pat<(vti.Mask (riscv_setcc_vl (SplatPat_simm5 simm5:$rs2),
(vti.Vector vti.RegClass:$rs1), invcc, (vti.Vector vti.RegClass:$rs1), invcc,
(vti.Mask true_mask), (vti.Mask true_mask),
(XLenVT (VLOp GPR:$vl)))), (XLenVT (VLOp GPR:$vl)))),
(instruction vti.RegClass:$rs1, simm5:$rs2, GPR:$vl, vti.SEW)>; (instruction vti.RegClass:$rs1, simm5:$rs2, GPR:$vl, vti.SEW)>;
} }
multiclass VPatIntegerSetCCVL_VIPlus1<VTypeInfo vti, string instruction_name,
CondCode cc> {
defvar instruction = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX);
def : Pat<(vti.Mask (riscv_setcc_vl (vti.Vector vti.RegClass:$rs1),
(SplatPat_simm5_plus1 simm5:$rs2), cc,
(vti.Mask true_mask),
(XLenVT (VLOp GPR:$vl)))),
(instruction vti.RegClass:$rs1, (DecImm simm5:$rs2),
GPR:$vl, vti.SEW)>;
}
multiclass VPatFPSetCCVL_VV_VF_FV<CondCode cc, multiclass VPatFPSetCCVL_VV_VF_FV<CondCode cc,
string inst_name, string inst_name,
string swapped_op_inst_name> { string swapped_op_inst_name> {
foreach fvti = AllFloatVectors in { foreach fvti = AllFloatVectors in {
def : Pat<(fvti.Mask (riscv_setcc_vl (fvti.Vector fvti.RegClass:$rs1), def : Pat<(fvti.Mask (riscv_setcc_vl (fvti.Vector fvti.RegClass:$rs1),
fvti.RegClass:$rs2, fvti.RegClass:$rs2,
cc, cc,
(fvti.Mask true_mask), (fvti.Mask true_mask),
▲ Show 20 Lines • Show All 212 Lines • ▼ Show 20 Linesforeach vti = AllIntegerVectors in {
defm "" : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>; defm "" : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLT", SETLT, SETGT>;
defm "" : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>; defm "" : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>;
defm "" : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; defm "" : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>;
defm "" : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; defm "" : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>;
defm "" : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>; defm "" : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGT", SETGT, SETLT>;
defm "" : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>; defm "" : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>;
// There is no VMSGE(U)_VX instruction // There is no VMSGE(U)_VX instruction
// FIXME: Support immediate forms of these by choosing SGT and decrementing
// the immediate
defm "" : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSEQ", SETEQ, SETEQ>; defm "" : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSEQ", SETEQ, SETEQ>;
defm "" : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSNE", SETNE, SETNE>; defm "" : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSNE", SETNE, SETNE>;
defm "" : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>; defm "" : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLE", SETLE, SETGE>;
defm "" : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>; defm "" : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSLEU", SETULE, SETUGE>;
defm "" : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSLE", SETLT>;
defm "" : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSLEU", SETULT>;
defm "" : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSGT", SETGE>;
defm "" : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSGTU", SETUGE>;
} // foreach vti = AllIntegerVectors } // foreach vti = AllIntegerVectors
// 12.9. Vector Integer Min/Max Instructions // 12.9. Vector Integer Min/Max Instructions
defm "" : VPatBinaryVL_VV_VX<riscv_umin_vl, "PseudoVMINU">; defm "" : VPatBinaryVL_VV_VX<riscv_umin_vl, "PseudoVMINU">;
defm "" : VPatBinaryVL_VV_VX<riscv_smin_vl, "PseudoVMIN">; defm "" : VPatBinaryVL_VV_VX<riscv_smin_vl, "PseudoVMIN">;
defm "" : VPatBinaryVL_VV_VX<riscv_umax_vl, "PseudoVMAXU">; defm "" : VPatBinaryVL_VV_VX<riscv_umax_vl, "PseudoVMAXU">;
defm "" : VPatBinaryVL_VV_VX<riscv_smax_vl, "PseudoVMAX">; defm "" : VPatBinaryVL_VV_VX<riscv_smax_vl, "PseudoVMAX">;
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll

Show First 20 Lines • Show All 564 Lines • ▼ Show 20 Lines
} }
define void @setlt_vi_v128i8(<128 x i8>* %x, <128 x i1>* %z) { define void @setlt_vi_v128i8(<128 x i8>* %x, <128 x i1>* %z) {
; CHECK-LABEL: setlt_vi_v128i8: ; CHECK-LABEL: setlt_vi_v128i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 128 ; CHECK-NEXT: addi a2, zero, 128
; CHECK-NEXT: vsetvli a2, a2, e8,m8,ta,mu ; CHECK-NEXT: vsetvli a2, a2, e8,m8,ta,mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmslt.vx v25, v8, zero ; CHECK-NEXT: vmsle.vi v25, v8, -1
; CHECK-NEXT: vse1.v v25, (a1) ; CHECK-NEXT: vse1.v v25, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <128 x i8>, <128 x i8>* %x %a = load <128 x i8>, <128 x i8>* %x
%b = insertelement <128 x i8> undef, i8 0, i32 0 %b = insertelement <128 x i8> undef, i8 0, i32 0
%c = shufflevector <128 x i8> %b, <128 x i8> undef, <128 x i32> zeroinitializer %c = shufflevector <128 x i8> %b, <128 x i8> undef, <128 x i32> zeroinitializer
%d = icmp slt <128 x i8> %a, %c %d = icmp slt <128 x i8> %a, %c
store <128 x i1> %d, <128 x i1>* %z store <128 x i1> %d, <128 x i1>* %z
ret void ret void
} }
define void @setge_vi_v8i8(<8 x i8>* %x, <8 x i1>* %z) { define void @setge_vi_v8i8(<8 x i8>* %x, <8 x i1>* %z) {
; CHECK-LABEL: setge_vi_v8i8: ; CHECK-LABEL: setge_vi_v8i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a2, 8, e8,m1,ta,mu ; CHECK-NEXT: vsetivli a2, 8, e8,m1,ta,mu
; CHECK-NEXT: vle8.v v25, (a0) ; CHECK-NEXT: vle8.v v25, (a0)
; CHECK-NEXT: vmv.v.i v26, 0 ; CHECK-NEXT: vmsgt.vi v26, v25, -1
; CHECK-NEXT: vmsle.vv v27, v26, v25 ; CHECK-NEXT: vse1.v v26, (a1)
; CHECK-NEXT: vse1.v v27, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <8 x i8>, <8 x i8>* %x %a = load <8 x i8>, <8 x i8>* %x
%b = insertelement <8 x i8> undef, i8 0, i32 0 %b = insertelement <8 x i8> undef, i8 0, i32 0
%c = shufflevector <8 x i8> %b, <8 x i8> undef, <8 x i32> zeroinitializer %c = shufflevector <8 x i8> %b, <8 x i8> undef, <8 x i32> zeroinitializer
%d = icmp sge <8 x i8> %a, %c %d = icmp sge <8 x i8> %a, %c
store <8 x i1> %d, <8 x i1>* %z store <8 x i1> %d, <8 x i1>* %z
ret void ret void
} }
Show All 33 Lines
} }
define void @setult_vi_v64i8(<64 x i8>* %x, <64 x i1>* %z) { define void @setult_vi_v64i8(<64 x i8>* %x, <64 x i1>* %z) {
; CHECK-LABEL: setult_vi_v64i8: ; CHECK-LABEL: setult_vi_v64i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 64 ; CHECK-NEXT: addi a2, zero, 64
; CHECK-NEXT: vsetvli a2, a2, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a2, a2, e8,m4,ta,mu
; CHECK-NEXT: vle8.v v28, (a0) ; CHECK-NEXT: vle8.v v28, (a0)
; CHECK-NEXT: addi a0, zero, 5 ; CHECK-NEXT: vmsleu.vi v25, v28, 4
; CHECK-NEXT: vmsltu.vx v25, v28, a0
; CHECK-NEXT: vse1.v v25, (a1) ; CHECK-NEXT: vse1.v v25, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <64 x i8>, <64 x i8>* %x %a = load <64 x i8>, <64 x i8>* %x
%b = insertelement <64 x i8> undef, i8 5, i32 0 %b = insertelement <64 x i8> undef, i8 5, i32 0
%c = shufflevector <64 x i8> %b, <64 x i8> undef, <64 x i32> zeroinitializer %c = shufflevector <64 x i8> %b, <64 x i8> undef, <64 x i32> zeroinitializer
%d = icmp ult <64 x i8> %a, %c %d = icmp ult <64 x i8> %a, %c
store <64 x i1> %d, <64 x i1>* %z store <64 x i1> %d, <64 x i1>* %z
ret void ret void
} }
define void @setuge_vi_v128i8(<128 x i8>* %x, <128 x i1>* %z) { define void @setuge_vi_v128i8(<128 x i8>* %x, <128 x i1>* %z) {
; CHECK-LABEL: setuge_vi_v128i8: ; CHECK-LABEL: setuge_vi_v128i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 128 ; CHECK-NEXT: addi a2, zero, 128
; CHECK-NEXT: vsetvli a2, a2, e8,m8,ta,mu ; CHECK-NEXT: vsetvli a2, a2, e8,m8,ta,mu
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmv.v.i v16, 5 ; CHECK-NEXT: vmsgtu.vi v25, v8, 4
; CHECK-NEXT: vmsleu.vv v25, v16, v8
; CHECK-NEXT: vse1.v v25, (a1) ; CHECK-NEXT: vse1.v v25, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <128 x i8>, <128 x i8>* %x %a = load <128 x i8>, <128 x i8>* %x
%b = insertelement <128 x i8> undef, i8 5, i32 0 %b = insertelement <128 x i8> undef, i8 5, i32 0
%c = shufflevector <128 x i8> %b, <128 x i8> undef, <128 x i32> zeroinitializer %c = shufflevector <128 x i8> %b, <128 x i8> undef, <128 x i32> zeroinitializer
%d = icmp uge <128 x i8> %a, %c %d = icmp uge <128 x i8> %a, %c
store <128 x i1> %d, <128 x i1>* %z store <128 x i1> %d, <128 x i1>* %z
ret void ret void
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llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
declare { <vscale x 2 x i32>, <vscale x 2 x i1> } @llvm.sadd.with.overflow.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>) declare { <vscale x 2 x i32>, <vscale x 2 x i1> } @llvm.sadd.with.overflow.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>)
define <vscale x 2 x i32> @saddo_nvx2i32(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y) { define <vscale x 2 x i32> @saddo_nvx2i32(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y) {
; CHECK-LABEL: saddo_nvx2i32: ; CHECK-LABEL: saddo_nvx2i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vmslt.vx v25, v9, zero ; CHECK-NEXT: vadd.vv v25, v8, v9
; CHECK-NEXT: vadd.vv v26, v8, v9 ; CHECK-NEXT: vmslt.vv v26, v25, v8
; CHECK-NEXT: vmslt.vv v27, v26, v8 ; CHECK-NEXT: vmsle.vi v27, v9, -1
; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,mf4,ta,mu
; CHECK-NEXT: vmxor.mm v0, v25, v27 ; CHECK-NEXT: vmxor.mm v0, v27, v26
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vmerge.vim v8, v26, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v25, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call { <vscale x 2 x i32>, <vscale x 2 x i1> } @llvm.sadd.with.overflow.nxv2i32(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y) %a = call { <vscale x 2 x i32>, <vscale x 2 x i1> } @llvm.sadd.with.overflow.nxv2i32(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y)
%b = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i1> } %a, 0 %b = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i1> } %a, 0
%c = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i1> } %a, 1 %c = extractvalue { <vscale x 2 x i32>, <vscale x 2 x i1> } %a, 1
%d = select <vscale x 2 x i1> %c, <vscale x 2 x i32> zeroinitializer, <vscale x 2 x i32> %b %d = select <vscale x 2 x i1> %c, <vscale x 2 x i32> zeroinitializer, <vscale x 2 x i32> %b
ret <vscale x 2 x i32> %d ret <vscale x 2 x i32> %d
} }

llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll

Show First 20 Lines • Show All 217 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%vc = icmp uge <vscale x 8 x i8> %va, %splat %vc = icmp uge <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_1(<vscale x 8 x i8> %va) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i8_1: ; CHECK-LABEL: icmp_uge_vi_nxv8i8_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, 15 ; CHECK-NEXT: vmsgtu.vi v0, v8, 14
; CHECK-NEXT: vmsleu.vv v0, v25, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 15, i32 0 %head = insertelement <vscale x 8 x i8> undef, i8 15, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i8> %va, %splat %vc = icmp uge <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_iv_nxv8i8_1(<vscale x 8 x i8> %va) { define <vscale x 8 x i1> @icmp_uge_iv_nxv8i8_1(<vscale x 8 x i8> %va) {
Show All 19 Lines; CHECK-NEXT: ret
%vc = icmp uge <vscale x 8 x i8> %va, %splat %vc = icmp uge <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_3(<vscale x 8 x i8> %va) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_3(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i8_3: ; CHECK-LABEL: icmp_uge_vi_nxv8i8_3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, 1 ; CHECK-NEXT: vmsgtu.vi v0, v8, 0
; CHECK-NEXT: vmsleu.vv v0, v25, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 1, i32 0 %head = insertelement <vscale x 8 x i8> undef, i8 1, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i8> %va, %splat %vc = icmp uge <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_4(<vscale x 8 x i8> %va) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_4(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i8_4: ; CHECK-LABEL: icmp_uge_vi_nxv8i8_4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, -15 ; CHECK-NEXT: vmsgtu.vi v0, v8, -16
; CHECK-NEXT: vmsleu.vv v0, v25, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0 %head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i8> %va, %splat %vc = icmp uge <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_5(<vscale x 8 x i8> %va) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_5(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i8_5: ; CHECK-LABEL: icmp_uge_vi_nxv8i8_5:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmsgtu.vi v0, v8, 15
; CHECK-NEXT: vmv.v.x v25, a0
; CHECK-NEXT: vmsleu.vv v0, v25, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 16, i32 0 %head = insertelement <vscale x 8 x i8> undef, i8 16, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i8> %va, %splat %vc = icmp uge <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) { define <vscale x 8 x i1> @icmp_ult_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i8> %va, %splat %vc = icmp ult <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_1(<vscale x 8 x i8> %va) { define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_ult_vi_nxv8i8_1: ; CHECK-LABEL: icmp_ult_vi_nxv8i8_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -15 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmsleu.vi v0, v8, -16
; CHECK-NEXT: vmsltu.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0 %head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i8> %va, %splat %vc = icmp ult <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_iv_nxv8i8_1(<vscale x 8 x i8> %va) { define <vscale x 8 x i1> @icmp_ult_iv_nxv8i8_1(<vscale x 8 x i8> %va) {
Show All 30 Lines; CHECK-NEXT: ret
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i8> %va, %splat %vc = icmp ult <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_4(<vscale x 8 x i8> %va) { define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_4(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_ult_vi_nxv8i8_4: ; CHECK-LABEL: icmp_ult_vi_nxv8i8_4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmsleu.vi v0, v8, 15
; CHECK-NEXT: vmsltu.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 16, i32 0 %head = insertelement <vscale x 8 x i8> undef, i8 16, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i8> %va, %splat %vc = icmp ult <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ule_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) { define <vscale x 8 x i1> @icmp_ule_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
▲ Show 20 Lines • Show All 138 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%vc = icmp sge <vscale x 8 x i8> %va, %splat %vc = icmp sge <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_1(<vscale x 8 x i8> %va) { define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_sge_vi_nxv8i8_1: ; CHECK-LABEL: icmp_sge_vi_nxv8i8_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, -15 ; CHECK-NEXT: vmsgt.vi v0, v8, -16
; CHECK-NEXT: vmsle.vv v0, v25, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0 %head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i8> %va, %splat %vc = icmp sge <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_iv_nxv8i8_1(<vscale x 8 x i8> %va) { define <vscale x 8 x i1> @icmp_sge_iv_nxv8i8_1(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_sge_iv_nxv8i8_1: ; CHECK-LABEL: icmp_sge_iv_nxv8i8_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmsle.vi v0, v8, -15 ; CHECK-NEXT: vmsle.vi v0, v8, -15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0 %head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i8> %splat, %va %vc = icmp sge <vscale x 8 x i8> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_2(<vscale x 8 x i8> %va) { define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_2(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_sge_vi_nxv8i8_2: ; CHECK-LABEL: icmp_sge_vi_nxv8i8_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, 0 ; CHECK-NEXT: vmsgt.vi v0, v8, -1
; CHECK-NEXT: vmsle.vv v0, v25, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 0, i32 0 %head = insertelement <vscale x 8 x i8> undef, i8 0, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i8> %va, %splat %vc = icmp sge <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_3(<vscale x 8 x i8> %va) { define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_3(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_sge_vi_nxv8i8_3: ; CHECK-LABEL: icmp_sge_vi_nxv8i8_3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmsgt.vi v0, v8, 15
; CHECK-NEXT: vmv.v.x v25, a0
; CHECK-NEXT: vmsle.vv v0, v25, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 16, i32 0 %head = insertelement <vscale x 8 x i8> undef, i8 16, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i8> %va, %splat %vc = icmp sge <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) { define <vscale x 8 x i1> @icmp_slt_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i8> %va, %splat %vc = icmp slt <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_1(<vscale x 8 x i8> %va) { define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_slt_vi_nxv8i8_1: ; CHECK-LABEL: icmp_slt_vi_nxv8i8_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -15 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmsle.vi v0, v8, -16
; CHECK-NEXT: vmslt.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0 %head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i8> %va, %splat %vc = icmp slt <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_iv_nxv8i8_1(<vscale x 8 x i8> %va) { define <vscale x 8 x i1> @icmp_slt_iv_nxv8i8_1(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_slt_iv_nxv8i8_1: ; CHECK-LABEL: icmp_slt_iv_nxv8i8_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmsgt.vi v0, v8, -15 ; CHECK-NEXT: vmsgt.vi v0, v8, -15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0 %head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i8> %splat, %va %vc = icmp slt <vscale x 8 x i8> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_2(<vscale x 8 x i8> %va) { define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_2(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_slt_vi_nxv8i8_2: ; CHECK-LABEL: icmp_slt_vi_nxv8i8_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmslt.vx v0, v8, zero ; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 0, i32 0 %head = insertelement <vscale x 8 x i8> undef, i8 0, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i8> %va, %splat %vc = icmp slt <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_3(<vscale x 8 x i8> %va) { define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_3(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_slt_vi_nxv8i8_3: ; CHECK-LABEL: icmp_slt_vi_nxv8i8_3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmsle.vi v0, v8, 15
; CHECK-NEXT: vmslt.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 16, i32 0 %head = insertelement <vscale x 8 x i8> undef, i8 16, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i8> %va, %splat %vc = icmp slt <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sle_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) { define <vscale x 8 x i1> @icmp_sle_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
▲ Show 20 Lines • Show All 256 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%vc = icmp uge <vscale x 8 x i16> %va, %splat %vc = icmp uge <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_1(<vscale x 8 x i16> %va) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i16_1: ; CHECK-LABEL: icmp_uge_vi_nxv8i16_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmv.v.i v26, 15 ; CHECK-NEXT: vmsgtu.vi v0, v8, 14
; CHECK-NEXT: vmsleu.vv v0, v26, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 15, i32 0 %head = insertelement <vscale x 8 x i16> undef, i16 15, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i16> %va, %splat %vc = icmp uge <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_iv_nxv8i16_1(<vscale x 8 x i16> %va) { define <vscale x 8 x i1> @icmp_uge_iv_nxv8i16_1(<vscale x 8 x i16> %va) {
Show All 19 Lines; CHECK-NEXT: ret
%vc = icmp uge <vscale x 8 x i16> %va, %splat %vc = icmp uge <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_3(<vscale x 8 x i16> %va) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_3(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i16_3: ; CHECK-LABEL: icmp_uge_vi_nxv8i16_3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmv.v.i v26, 1 ; CHECK-NEXT: vmsgtu.vi v0, v8, 0
; CHECK-NEXT: vmsleu.vv v0, v26, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 1, i32 0 %head = insertelement <vscale x 8 x i16> undef, i16 1, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i16> %va, %splat %vc = icmp uge <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_4(<vscale x 8 x i16> %va) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_4(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i16_4: ; CHECK-LABEL: icmp_uge_vi_nxv8i16_4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmv.v.i v26, -15 ; CHECK-NEXT: vmsgtu.vi v0, v8, -16
; CHECK-NEXT: vmsleu.vv v0, v26, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0 %head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i16> %va, %splat %vc = icmp uge <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_5(<vscale x 8 x i16> %va) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_5(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i16_5: ; CHECK-LABEL: icmp_uge_vi_nxv8i16_5:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmsgtu.vi v0, v8, 15
; CHECK-NEXT: vmv.v.x v26, a0
; CHECK-NEXT: vmsleu.vv v0, v26, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 16, i32 0 %head = insertelement <vscale x 8 x i16> undef, i16 16, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i16> %va, %splat %vc = icmp uge <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) { define <vscale x 8 x i1> @icmp_ult_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i16> %va, %splat %vc = icmp ult <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_1(<vscale x 8 x i16> %va) { define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_ult_vi_nxv8i16_1: ; CHECK-LABEL: icmp_ult_vi_nxv8i16_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -15 ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmsleu.vi v0, v8, -16
; CHECK-NEXT: vmsltu.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0 %head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i16> %va, %splat %vc = icmp ult <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_iv_nxv8i16_1(<vscale x 8 x i16> %va) { define <vscale x 8 x i1> @icmp_ult_iv_nxv8i16_1(<vscale x 8 x i16> %va) {
Show All 30 Lines; CHECK-NEXT: ret
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i16> %va, %splat %vc = icmp ult <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_4(<vscale x 8 x i16> %va) { define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_4(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_ult_vi_nxv8i16_4: ; CHECK-LABEL: icmp_ult_vi_nxv8i16_4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmsleu.vi v0, v8, 15
; CHECK-NEXT: vmsltu.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 16, i32 0 %head = insertelement <vscale x 8 x i16> undef, i16 16, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i16> %va, %splat %vc = icmp ult <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ule_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) { define <vscale x 8 x i1> @icmp_ule_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
▲ Show 20 Lines • Show All 138 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%vc = icmp sge <vscale x 8 x i16> %va, %splat %vc = icmp sge <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_1(<vscale x 8 x i16> %va) { define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_sge_vi_nxv8i16_1: ; CHECK-LABEL: icmp_sge_vi_nxv8i16_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmv.v.i v26, -15 ; CHECK-NEXT: vmsgt.vi v0, v8, -16
; CHECK-NEXT: vmsle.vv v0, v26, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0 %head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i16> %va, %splat %vc = icmp sge <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_iv_nxv8i16_1(<vscale x 8 x i16> %va) { define <vscale x 8 x i1> @icmp_sge_iv_nxv8i16_1(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_sge_iv_nxv8i16_1: ; CHECK-LABEL: icmp_sge_iv_nxv8i16_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmsle.vi v0, v8, -15 ; CHECK-NEXT: vmsle.vi v0, v8, -15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0 %head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i16> %splat, %va %vc = icmp sge <vscale x 8 x i16> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_2(<vscale x 8 x i16> %va) { define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_2(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_sge_vi_nxv8i16_2: ; CHECK-LABEL: icmp_sge_vi_nxv8i16_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0 ; CHECK-NEXT: vmsgt.vi v0, v8, -1
; CHECK-NEXT: vmsle.vv v0, v26, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 0, i32 0 %head = insertelement <vscale x 8 x i16> undef, i16 0, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i16> %va, %splat %vc = icmp sge <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_3(<vscale x 8 x i16> %va) { define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_3(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_sge_vi_nxv8i16_3: ; CHECK-LABEL: icmp_sge_vi_nxv8i16_3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmsgt.vi v0, v8, 15
; CHECK-NEXT: vmv.v.x v26, a0
; CHECK-NEXT: vmsle.vv v0, v26, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 16, i32 0 %head = insertelement <vscale x 8 x i16> undef, i16 16, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i16> %va, %splat %vc = icmp sge <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) { define <vscale x 8 x i1> @icmp_slt_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i16> %va, %splat %vc = icmp slt <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_1(<vscale x 8 x i16> %va) { define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_slt_vi_nxv8i16_1: ; CHECK-LABEL: icmp_slt_vi_nxv8i16_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -15 ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmsle.vi v0, v8, -16
; CHECK-NEXT: vmslt.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0 %head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i16> %va, %splat %vc = icmp slt <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_iv_nxv8i16_1(<vscale x 8 x i16> %va) { define <vscale x 8 x i1> @icmp_slt_iv_nxv8i16_1(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_slt_iv_nxv8i16_1: ; CHECK-LABEL: icmp_slt_iv_nxv8i16_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmsgt.vi v0, v8, -15 ; CHECK-NEXT: vmsgt.vi v0, v8, -15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0 %head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i16> %splat, %va %vc = icmp slt <vscale x 8 x i16> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_2(<vscale x 8 x i16> %va) { define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_2(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_slt_vi_nxv8i16_2: ; CHECK-LABEL: icmp_slt_vi_nxv8i16_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmslt.vx v0, v8, zero ; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 0, i32 0 %head = insertelement <vscale x 8 x i16> undef, i16 0, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i16> %va, %splat %vc = icmp slt <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_3(<vscale x 8 x i16> %va) { define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_3(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_slt_vi_nxv8i16_3: ; CHECK-LABEL: icmp_slt_vi_nxv8i16_3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmsle.vi v0, v8, 15
; CHECK-NEXT: vmslt.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 16, i32 0 %head = insertelement <vscale x 8 x i16> undef, i16 16, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i16> %va, %splat %vc = icmp slt <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sle_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) { define <vscale x 8 x i1> @icmp_sle_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
▲ Show 20 Lines • Show All 256 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%vc = icmp uge <vscale x 8 x i32> %va, %splat %vc = icmp uge <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_1(<vscale x 8 x i32> %va) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i32_1: ; CHECK-LABEL: icmp_uge_vi_nxv8i32_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vmv.v.i v28, 15 ; CHECK-NEXT: vmsgtu.vi v0, v8, 14
; CHECK-NEXT: vmsleu.vv v0, v28, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 15, i32 0 %head = insertelement <vscale x 8 x i32> undef, i32 15, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i32> %va, %splat %vc = icmp uge <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_iv_nxv8i32_1(<vscale x 8 x i32> %va) { define <vscale x 8 x i1> @icmp_uge_iv_nxv8i32_1(<vscale x 8 x i32> %va) {
Show All 19 Lines; CHECK-NEXT: ret
%vc = icmp uge <vscale x 8 x i32> %va, %splat %vc = icmp uge <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_3(<vscale x 8 x i32> %va) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_3(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i32_3: ; CHECK-LABEL: icmp_uge_vi_nxv8i32_3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vmv.v.i v28, 1 ; CHECK-NEXT: vmsgtu.vi v0, v8, 0
; CHECK-NEXT: vmsleu.vv v0, v28, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 1, i32 0 %head = insertelement <vscale x 8 x i32> undef, i32 1, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i32> %va, %splat %vc = icmp uge <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_4(<vscale x 8 x i32> %va) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_4(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i32_4: ; CHECK-LABEL: icmp_uge_vi_nxv8i32_4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vmv.v.i v28, -15 ; CHECK-NEXT: vmsgtu.vi v0, v8, -16
; CHECK-NEXT: vmsleu.vv v0, v28, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0 %head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i32> %va, %splat %vc = icmp uge <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_5(<vscale x 8 x i32> %va) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_5(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i32_5: ; CHECK-LABEL: icmp_uge_vi_nxv8i32_5:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmsgtu.vi v0, v8, 15
; CHECK-NEXT: vmv.v.x v28, a0
; CHECK-NEXT: vmsleu.vv v0, v28, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 16, i32 0 %head = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i32> %va, %splat %vc = icmp uge <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) { define <vscale x 8 x i1> @icmp_ult_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i32> %va, %splat %vc = icmp ult <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_1(<vscale x 8 x i32> %va) { define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_ult_vi_nxv8i32_1: ; CHECK-LABEL: icmp_ult_vi_nxv8i32_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -15 ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmsleu.vi v0, v8, -16
; CHECK-NEXT: vmsltu.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0 %head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i32> %va, %splat %vc = icmp ult <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_iv_nxv8i32_1(<vscale x 8 x i32> %va) { define <vscale x 8 x i1> @icmp_ult_iv_nxv8i32_1(<vscale x 8 x i32> %va) {
Show All 30 Lines; CHECK-NEXT: ret
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i32> %va, %splat %vc = icmp ult <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_4(<vscale x 8 x i32> %va) { define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_4(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_ult_vi_nxv8i32_4: ; CHECK-LABEL: icmp_ult_vi_nxv8i32_4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmsleu.vi v0, v8, 15
; CHECK-NEXT: vmsltu.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 16, i32 0 %head = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i32> %va, %splat %vc = icmp ult <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ule_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) { define <vscale x 8 x i1> @icmp_ule_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
▲ Show 20 Lines • Show All 138 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%vc = icmp sge <vscale x 8 x i32> %va, %splat %vc = icmp sge <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_1(<vscale x 8 x i32> %va) { define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_sge_vi_nxv8i32_1: ; CHECK-LABEL: icmp_sge_vi_nxv8i32_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vmv.v.i v28, -15 ; CHECK-NEXT: vmsgt.vi v0, v8, -16
; CHECK-NEXT: vmsle.vv v0, v28, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0 %head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i32> %va, %splat %vc = icmp sge <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_iv_nxv8i32_1(<vscale x 8 x i32> %va) { define <vscale x 8 x i1> @icmp_sge_iv_nxv8i32_1(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_sge_iv_nxv8i32_1: ; CHECK-LABEL: icmp_sge_iv_nxv8i32_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vmsle.vi v0, v8, -15 ; CHECK-NEXT: vmsle.vi v0, v8, -15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0 %head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i32> %splat, %va %vc = icmp sge <vscale x 8 x i32> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_2(<vscale x 8 x i32> %va) { define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_2(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_sge_vi_nxv8i32_2: ; CHECK-LABEL: icmp_sge_vi_nxv8i32_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vmv.v.i v28, 0 ; CHECK-NEXT: vmsgt.vi v0, v8, -1
; CHECK-NEXT: vmsle.vv v0, v28, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 0, i32 0 %head = insertelement <vscale x 8 x i32> undef, i32 0, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i32> %va, %splat %vc = icmp sge <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_3(<vscale x 8 x i32> %va) { define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_3(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_sge_vi_nxv8i32_3: ; CHECK-LABEL: icmp_sge_vi_nxv8i32_3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmsgt.vi v0, v8, 15
; CHECK-NEXT: vmv.v.x v28, a0
; CHECK-NEXT: vmsle.vv v0, v28, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 16, i32 0 %head = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i32> %va, %splat %vc = icmp sge <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) { define <vscale x 8 x i1> @icmp_slt_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i32> %va, %splat %vc = icmp slt <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_1(<vscale x 8 x i32> %va) { define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_slt_vi_nxv8i32_1: ; CHECK-LABEL: icmp_slt_vi_nxv8i32_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -15 ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmsle.vi v0, v8, -16
; CHECK-NEXT: vmslt.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0 %head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i32> %va, %splat %vc = icmp slt <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_iv_nxv8i32_1(<vscale x 8 x i32> %va) { define <vscale x 8 x i1> @icmp_slt_iv_nxv8i32_1(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_slt_iv_nxv8i32_1: ; CHECK-LABEL: icmp_slt_iv_nxv8i32_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vmsgt.vi v0, v8, -15 ; CHECK-NEXT: vmsgt.vi v0, v8, -15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0 %head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i32> %splat, %va %vc = icmp slt <vscale x 8 x i32> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_2(<vscale x 8 x i32> %va) { define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_2(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_slt_vi_nxv8i32_2: ; CHECK-LABEL: icmp_slt_vi_nxv8i32_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vmslt.vx v0, v8, zero ; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 0, i32 0 %head = insertelement <vscale x 8 x i32> undef, i32 0, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i32> %va, %splat %vc = icmp slt <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_3(<vscale x 8 x i32> %va) { define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_3(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_slt_vi_nxv8i32_3: ; CHECK-LABEL: icmp_slt_vi_nxv8i32_3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmsle.vi v0, v8, 15
; CHECK-NEXT: vmslt.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 16, i32 0 %head = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i32> %va, %splat %vc = icmp slt <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sle_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) { define <vscale x 8 x i1> @icmp_sle_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
▲ Show 20 Lines • Show All 307 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%vc = icmp uge <vscale x 8 x i64> %va, %splat %vc = icmp uge <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_1(<vscale x 8 x i64> %va) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i64_1: ; CHECK-LABEL: icmp_uge_vi_nxv8i64_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vmv.v.i v16, 15 ; CHECK-NEXT: vmsgtu.vi v0, v8, 14
; CHECK-NEXT: vmsleu.vv v0, v16, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 15, i32 0 %head = insertelement <vscale x 8 x i64> undef, i64 15, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i64> %va, %splat %vc = icmp uge <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_iv_nxv8i64_1(<vscale x 8 x i64> %va) { define <vscale x 8 x i1> @icmp_uge_iv_nxv8i64_1(<vscale x 8 x i64> %va) {
Show All 19 Lines; CHECK-NEXT: ret
%vc = icmp uge <vscale x 8 x i64> %va, %splat %vc = icmp uge <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_3(<vscale x 8 x i64> %va) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_3(<vscale x 8 x i64> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i64_3: ; CHECK-LABEL: icmp_uge_vi_nxv8i64_3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vmv.v.i v16, 1 ; CHECK-NEXT: vmsgtu.vi v0, v8, 0
; CHECK-NEXT: vmsleu.vv v0, v16, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 1, i32 0 %head = insertelement <vscale x 8 x i64> undef, i64 1, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i64> %va, %splat %vc = icmp uge <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_4(<vscale x 8 x i64> %va) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_4(<vscale x 8 x i64> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i64_4: ; CHECK-LABEL: icmp_uge_vi_nxv8i64_4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vmv.v.i v16, -15 ; CHECK-NEXT: vmsgtu.vi v0, v8, -16
; CHECK-NEXT: vmsleu.vv v0, v16, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0 %head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i64> %va, %splat %vc = icmp uge <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_5(<vscale x 8 x i64> %va) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_5(<vscale x 8 x i64> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i64_5: ; CHECK-LABEL: icmp_uge_vi_nxv8i64_5:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu ; CHECK-NEXT: vmsgtu.vi v0, v8, 15
; CHECK-NEXT: vmv.v.x v16, a0
; CHECK-NEXT: vmsleu.vv v0, v16, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0 %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i64> %va, %splat %vc = icmp uge <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) { define <vscale x 8 x i1> @icmp_ult_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i64> %va, %splat %vc = icmp ult <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_1(<vscale x 8 x i64> %va) { define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
; CHECK-LABEL: icmp_ult_vi_nxv8i64_1: ; CHECK-LABEL: icmp_ult_vi_nxv8i64_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -15 ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu ; CHECK-NEXT: vmsleu.vi v0, v8, -16
; CHECK-NEXT: vmsltu.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0 %head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i64> %va, %splat %vc = icmp ult <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_iv_nxv8i64_1(<vscale x 8 x i64> %va) { define <vscale x 8 x i1> @icmp_ult_iv_nxv8i64_1(<vscale x 8 x i64> %va) {
Show All 30 Lines; CHECK-NEXT: ret
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i64> %va, %splat %vc = icmp ult <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_4(<vscale x 8 x i64> %va) { define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_4(<vscale x 8 x i64> %va) {
; CHECK-LABEL: icmp_ult_vi_nxv8i64_4: ; CHECK-LABEL: icmp_ult_vi_nxv8i64_4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu ; CHECK-NEXT: vmsleu.vi v0, v8, 15
; CHECK-NEXT: vmsltu.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0 %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i64> %va, %splat %vc = icmp ult <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ule_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) { define <vscale x 8 x i1> @icmp_ule_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
▲ Show 20 Lines • Show All 176 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%vc = icmp sge <vscale x 8 x i64> %va, %splat %vc = icmp sge <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_1(<vscale x 8 x i64> %va) { define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
; CHECK-LABEL: icmp_sge_vi_nxv8i64_1: ; CHECK-LABEL: icmp_sge_vi_nxv8i64_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vmv.v.i v16, -15 ; CHECK-NEXT: vmsgt.vi v0, v8, -16
; CHECK-NEXT: vmsle.vv v0, v16, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0 %head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i64> %va, %splat %vc = icmp sge <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_iv_nxv8i64_1(<vscale x 8 x i64> %va) { define <vscale x 8 x i1> @icmp_sge_iv_nxv8i64_1(<vscale x 8 x i64> %va) {
; CHECK-LABEL: icmp_sge_iv_nxv8i64_1: ; CHECK-LABEL: icmp_sge_iv_nxv8i64_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vmsle.vi v0, v8, -15 ; CHECK-NEXT: vmsle.vi v0, v8, -15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0 %head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i64> %splat, %va %vc = icmp sge <vscale x 8 x i64> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_2(<vscale x 8 x i64> %va) { define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
; CHECK-LABEL: icmp_sge_vi_nxv8i64_2: ; CHECK-LABEL: icmp_sge_vi_nxv8i64_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vmsgt.vi v0, v8, -1
; CHECK-NEXT: vmsle.vv v0, v16, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 0, i32 0 %head = insertelement <vscale x 8 x i64> undef, i64 0, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i64> %va, %splat %vc = icmp sge <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_3(<vscale x 8 x i64> %va) { define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_3(<vscale x 8 x i64> %va) {
; CHECK-LABEL: icmp_sge_vi_nxv8i64_3: ; CHECK-LABEL: icmp_sge_vi_nxv8i64_3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu ; CHECK-NEXT: vmsgt.vi v0, v8, 15
; CHECK-NEXT: vmv.v.x v16, a0
; CHECK-NEXT: vmsle.vv v0, v16, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0 %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i64> %va, %splat %vc = icmp sge <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) { define <vscale x 8 x i1> @icmp_slt_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
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%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i64> %va, %splat %vc = icmp slt <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_1(<vscale x 8 x i64> %va) { define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
; CHECK-LABEL: icmp_slt_vi_nxv8i64_1: ; CHECK-LABEL: icmp_slt_vi_nxv8i64_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -15 ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu ; CHECK-NEXT: vmsle.vi v0, v8, -16
; CHECK-NEXT: vmslt.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0 %head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i64> %va, %splat %vc = icmp slt <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_iv_nxv8i64_1(<vscale x 8 x i64> %va) { define <vscale x 8 x i1> @icmp_slt_iv_nxv8i64_1(<vscale x 8 x i64> %va) {
; CHECK-LABEL: icmp_slt_iv_nxv8i64_1: ; CHECK-LABEL: icmp_slt_iv_nxv8i64_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vmsgt.vi v0, v8, -15 ; CHECK-NEXT: vmsgt.vi v0, v8, -15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0 %head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i64> %splat, %va %vc = icmp slt <vscale x 8 x i64> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_2(<vscale x 8 x i64> %va) { define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
; CHECK-LABEL: icmp_slt_vi_nxv8i64_2: ; CHECK-LABEL: icmp_slt_vi_nxv8i64_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vmslt.vx v0, v8, zero ; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 0, i32 0 %head = insertelement <vscale x 8 x i64> undef, i64 0, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i64> %va, %splat %vc = icmp slt <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_3(<vscale x 8 x i64> %va) { define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_3(<vscale x 8 x i64> %va) {
; CHECK-LABEL: icmp_slt_vi_nxv8i64_3: ; CHECK-LABEL: icmp_slt_vi_nxv8i64_3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu ; CHECK-NEXT: vmsle.vi v0, v8, 15
; CHECK-NEXT: vmslt.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0 %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i64> %va, %splat %vc = icmp slt <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sle_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) { define <vscale x 8 x i1> @icmp_sle_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
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llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll

Show First 20 Lines • Show All 217 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%vc = icmp uge <vscale x 8 x i8> %va, %splat %vc = icmp uge <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_1(<vscale x 8 x i8> %va) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i8_1: ; CHECK-LABEL: icmp_uge_vi_nxv8i8_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, 15 ; CHECK-NEXT: vmsgtu.vi v0, v8, 14
; CHECK-NEXT: vmsleu.vv v0, v25, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 15, i32 0 %head = insertelement <vscale x 8 x i8> undef, i8 15, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i8> %va, %splat %vc = icmp uge <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_iv_nxv8i8_1(<vscale x 8 x i8> %va) { define <vscale x 8 x i1> @icmp_uge_iv_nxv8i8_1(<vscale x 8 x i8> %va) {
Show All 19 Lines; CHECK-NEXT: ret
%vc = icmp uge <vscale x 8 x i8> %va, %splat %vc = icmp uge <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_3(<vscale x 8 x i8> %va) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_3(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i8_3: ; CHECK-LABEL: icmp_uge_vi_nxv8i8_3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, 1 ; CHECK-NEXT: vmsgtu.vi v0, v8, 0
; CHECK-NEXT: vmsleu.vv v0, v25, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 1, i32 0 %head = insertelement <vscale x 8 x i8> undef, i8 1, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i8> %va, %splat %vc = icmp uge <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_4(<vscale x 8 x i8> %va) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_4(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i8_4: ; CHECK-LABEL: icmp_uge_vi_nxv8i8_4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, -15 ; CHECK-NEXT: vmsgtu.vi v0, v8, -16
; CHECK-NEXT: vmsleu.vv v0, v25, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0 %head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i8> %va, %splat %vc = icmp uge <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_5(<vscale x 8 x i8> %va) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_5(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i8_5: ; CHECK-LABEL: icmp_uge_vi_nxv8i8_5:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmsgtu.vi v0, v8, 15
; CHECK-NEXT: vmv.v.x v25, a0
; CHECK-NEXT: vmsleu.vv v0, v25, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 16, i32 0 %head = insertelement <vscale x 8 x i8> undef, i8 16, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i8> %va, %splat %vc = icmp uge <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) { define <vscale x 8 x i1> @icmp_ult_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i8> %va, %splat %vc = icmp ult <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_1(<vscale x 8 x i8> %va) { define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_ult_vi_nxv8i8_1: ; CHECK-LABEL: icmp_ult_vi_nxv8i8_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -15 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmsleu.vi v0, v8, -16
; CHECK-NEXT: vmsltu.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0 %head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i8> %va, %splat %vc = icmp ult <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_iv_nxv8i8_1(<vscale x 8 x i8> %va) { define <vscale x 8 x i1> @icmp_ult_iv_nxv8i8_1(<vscale x 8 x i8> %va) {
Show All 30 Lines; CHECK-NEXT: ret
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i8> %va, %splat %vc = icmp ult <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_4(<vscale x 8 x i8> %va) { define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_4(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_ult_vi_nxv8i8_4: ; CHECK-LABEL: icmp_ult_vi_nxv8i8_4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmsleu.vi v0, v8, 15
; CHECK-NEXT: vmsltu.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 16, i32 0 %head = insertelement <vscale x 8 x i8> undef, i8 16, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i8> %va, %splat %vc = icmp ult <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ule_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) { define <vscale x 8 x i1> @icmp_ule_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
▲ Show 20 Lines • Show All 138 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%vc = icmp sge <vscale x 8 x i8> %va, %splat %vc = icmp sge <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_1(<vscale x 8 x i8> %va) { define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_sge_vi_nxv8i8_1: ; CHECK-LABEL: icmp_sge_vi_nxv8i8_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, -15 ; CHECK-NEXT: vmsgt.vi v0, v8, -16
; CHECK-NEXT: vmsle.vv v0, v25, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0 %head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i8> %va, %splat %vc = icmp sge <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_iv_nxv8i8_1(<vscale x 8 x i8> %va) { define <vscale x 8 x i1> @icmp_sge_iv_nxv8i8_1(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_sge_iv_nxv8i8_1: ; CHECK-LABEL: icmp_sge_iv_nxv8i8_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmsle.vi v0, v8, -15 ; CHECK-NEXT: vmsle.vi v0, v8, -15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0 %head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i8> %splat, %va %vc = icmp sge <vscale x 8 x i8> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_2(<vscale x 8 x i8> %va) { define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_2(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_sge_vi_nxv8i8_2: ; CHECK-LABEL: icmp_sge_vi_nxv8i8_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmv.v.i v25, 0 ; CHECK-NEXT: vmsgt.vi v0, v8, -1
; CHECK-NEXT: vmsle.vv v0, v25, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 0, i32 0 %head = insertelement <vscale x 8 x i8> undef, i8 0, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i8> %va, %splat %vc = icmp sge <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_3(<vscale x 8 x i8> %va) { define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_3(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_sge_vi_nxv8i8_3: ; CHECK-LABEL: icmp_sge_vi_nxv8i8_3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmsgt.vi v0, v8, 15
; CHECK-NEXT: vmv.v.x v25, a0
; CHECK-NEXT: vmsle.vv v0, v25, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 16, i32 0 %head = insertelement <vscale x 8 x i8> undef, i8 16, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i8> %va, %splat %vc = icmp sge <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) { define <vscale x 8 x i1> @icmp_slt_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i8> %va, %splat %vc = icmp slt <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_1(<vscale x 8 x i8> %va) { define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_slt_vi_nxv8i8_1: ; CHECK-LABEL: icmp_slt_vi_nxv8i8_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -15 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmsle.vi v0, v8, -16
; CHECK-NEXT: vmslt.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0 %head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i8> %va, %splat %vc = icmp slt <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_iv_nxv8i8_1(<vscale x 8 x i8> %va) { define <vscale x 8 x i1> @icmp_slt_iv_nxv8i8_1(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_slt_iv_nxv8i8_1: ; CHECK-LABEL: icmp_slt_iv_nxv8i8_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmsgt.vi v0, v8, -15 ; CHECK-NEXT: vmsgt.vi v0, v8, -15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0 %head = insertelement <vscale x 8 x i8> undef, i8 -15, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i8> %splat, %va %vc = icmp slt <vscale x 8 x i8> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_2(<vscale x 8 x i8> %va) { define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_2(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_slt_vi_nxv8i8_2: ; CHECK-LABEL: icmp_slt_vi_nxv8i8_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vmslt.vx v0, v8, zero ; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 0, i32 0 %head = insertelement <vscale x 8 x i8> undef, i8 0, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i8> %va, %splat %vc = icmp slt <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_3(<vscale x 8 x i8> %va) { define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_3(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_slt_vi_nxv8i8_3: ; CHECK-LABEL: icmp_slt_vi_nxv8i8_3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a0, zero, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vmsle.vi v0, v8, 15
; CHECK-NEXT: vmslt.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 16, i32 0 %head = insertelement <vscale x 8 x i8> undef, i8 16, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i8> %va, %splat %vc = icmp slt <vscale x 8 x i8> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sle_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) { define <vscale x 8 x i1> @icmp_sle_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
▲ Show 20 Lines • Show All 256 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%vc = icmp uge <vscale x 8 x i16> %va, %splat %vc = icmp uge <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_1(<vscale x 8 x i16> %va) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i16_1: ; CHECK-LABEL: icmp_uge_vi_nxv8i16_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmv.v.i v26, 15 ; CHECK-NEXT: vmsgtu.vi v0, v8, 14
; CHECK-NEXT: vmsleu.vv v0, v26, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 15, i32 0 %head = insertelement <vscale x 8 x i16> undef, i16 15, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i16> %va, %splat %vc = icmp uge <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_iv_nxv8i16_1(<vscale x 8 x i16> %va) { define <vscale x 8 x i1> @icmp_uge_iv_nxv8i16_1(<vscale x 8 x i16> %va) {
Show All 19 Lines; CHECK-NEXT: ret
%vc = icmp uge <vscale x 8 x i16> %va, %splat %vc = icmp uge <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_3(<vscale x 8 x i16> %va) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_3(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i16_3: ; CHECK-LABEL: icmp_uge_vi_nxv8i16_3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmv.v.i v26, 1 ; CHECK-NEXT: vmsgtu.vi v0, v8, 0
; CHECK-NEXT: vmsleu.vv v0, v26, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 1, i32 0 %head = insertelement <vscale x 8 x i16> undef, i16 1, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i16> %va, %splat %vc = icmp uge <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_4(<vscale x 8 x i16> %va) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_4(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i16_4: ; CHECK-LABEL: icmp_uge_vi_nxv8i16_4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmv.v.i v26, -15 ; CHECK-NEXT: vmsgtu.vi v0, v8, -16
; CHECK-NEXT: vmsleu.vv v0, v26, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0 %head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i16> %va, %splat %vc = icmp uge <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_5(<vscale x 8 x i16> %va) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_5(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i16_5: ; CHECK-LABEL: icmp_uge_vi_nxv8i16_5:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmsgtu.vi v0, v8, 15
; CHECK-NEXT: vmv.v.x v26, a0
; CHECK-NEXT: vmsleu.vv v0, v26, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 16, i32 0 %head = insertelement <vscale x 8 x i16> undef, i16 16, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i16> %va, %splat %vc = icmp uge <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) { define <vscale x 8 x i1> @icmp_ult_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i16> %va, %splat %vc = icmp ult <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_1(<vscale x 8 x i16> %va) { define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_ult_vi_nxv8i16_1: ; CHECK-LABEL: icmp_ult_vi_nxv8i16_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -15 ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmsleu.vi v0, v8, -16
; CHECK-NEXT: vmsltu.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0 %head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i16> %va, %splat %vc = icmp ult <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_iv_nxv8i16_1(<vscale x 8 x i16> %va) { define <vscale x 8 x i1> @icmp_ult_iv_nxv8i16_1(<vscale x 8 x i16> %va) {
Show All 30 Lines; CHECK-NEXT: ret
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i16> %va, %splat %vc = icmp ult <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_4(<vscale x 8 x i16> %va) { define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_4(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_ult_vi_nxv8i16_4: ; CHECK-LABEL: icmp_ult_vi_nxv8i16_4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmsleu.vi v0, v8, 15
; CHECK-NEXT: vmsltu.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 16, i32 0 %head = insertelement <vscale x 8 x i16> undef, i16 16, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i16> %va, %splat %vc = icmp ult <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ule_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) { define <vscale x 8 x i1> @icmp_ule_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
▲ Show 20 Lines • Show All 138 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%vc = icmp sge <vscale x 8 x i16> %va, %splat %vc = icmp sge <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_1(<vscale x 8 x i16> %va) { define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_sge_vi_nxv8i16_1: ; CHECK-LABEL: icmp_sge_vi_nxv8i16_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmv.v.i v26, -15 ; CHECK-NEXT: vmsgt.vi v0, v8, -16
; CHECK-NEXT: vmsle.vv v0, v26, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0 %head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i16> %va, %splat %vc = icmp sge <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_iv_nxv8i16_1(<vscale x 8 x i16> %va) { define <vscale x 8 x i1> @icmp_sge_iv_nxv8i16_1(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_sge_iv_nxv8i16_1: ; CHECK-LABEL: icmp_sge_iv_nxv8i16_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmsle.vi v0, v8, -15 ; CHECK-NEXT: vmsle.vi v0, v8, -15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0 %head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i16> %splat, %va %vc = icmp sge <vscale x 8 x i16> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_2(<vscale x 8 x i16> %va) { define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_2(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_sge_vi_nxv8i16_2: ; CHECK-LABEL: icmp_sge_vi_nxv8i16_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0 ; CHECK-NEXT: vmsgt.vi v0, v8, -1
; CHECK-NEXT: vmsle.vv v0, v26, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 0, i32 0 %head = insertelement <vscale x 8 x i16> undef, i16 0, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i16> %va, %splat %vc = icmp sge <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_3(<vscale x 8 x i16> %va) { define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_3(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_sge_vi_nxv8i16_3: ; CHECK-LABEL: icmp_sge_vi_nxv8i16_3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmsgt.vi v0, v8, 15
; CHECK-NEXT: vmv.v.x v26, a0
; CHECK-NEXT: vmsle.vv v0, v26, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 16, i32 0 %head = insertelement <vscale x 8 x i16> undef, i16 16, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i16> %va, %splat %vc = icmp sge <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) { define <vscale x 8 x i1> @icmp_slt_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i16> %va, %splat %vc = icmp slt <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_1(<vscale x 8 x i16> %va) { define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_slt_vi_nxv8i16_1: ; CHECK-LABEL: icmp_slt_vi_nxv8i16_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -15 ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmsle.vi v0, v8, -16
; CHECK-NEXT: vmslt.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0 %head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i16> %va, %splat %vc = icmp slt <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_iv_nxv8i16_1(<vscale x 8 x i16> %va) { define <vscale x 8 x i1> @icmp_slt_iv_nxv8i16_1(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_slt_iv_nxv8i16_1: ; CHECK-LABEL: icmp_slt_iv_nxv8i16_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmsgt.vi v0, v8, -15 ; CHECK-NEXT: vmsgt.vi v0, v8, -15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0 %head = insertelement <vscale x 8 x i16> undef, i16 -15, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i16> %splat, %va %vc = icmp slt <vscale x 8 x i16> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_2(<vscale x 8 x i16> %va) { define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_2(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_slt_vi_nxv8i16_2: ; CHECK-LABEL: icmp_slt_vi_nxv8i16_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vmslt.vx v0, v8, zero ; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 0, i32 0 %head = insertelement <vscale x 8 x i16> undef, i16 0, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i16> %va, %splat %vc = icmp slt <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_3(<vscale x 8 x i16> %va) { define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_3(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_slt_vi_nxv8i16_3: ; CHECK-LABEL: icmp_slt_vi_nxv8i16_3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vmsle.vi v0, v8, 15
; CHECK-NEXT: vmslt.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 16, i32 0 %head = insertelement <vscale x 8 x i16> undef, i16 16, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i16> %va, %splat %vc = icmp slt <vscale x 8 x i16> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sle_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) { define <vscale x 8 x i1> @icmp_sle_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
▲ Show 20 Lines • Show All 256 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%vc = icmp uge <vscale x 8 x i32> %va, %splat %vc = icmp uge <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_1(<vscale x 8 x i32> %va) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i32_1: ; CHECK-LABEL: icmp_uge_vi_nxv8i32_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vmv.v.i v28, 15 ; CHECK-NEXT: vmsgtu.vi v0, v8, 14
; CHECK-NEXT: vmsleu.vv v0, v28, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 15, i32 0 %head = insertelement <vscale x 8 x i32> undef, i32 15, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i32> %va, %splat %vc = icmp uge <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_iv_nxv8i32_1(<vscale x 8 x i32> %va) { define <vscale x 8 x i1> @icmp_uge_iv_nxv8i32_1(<vscale x 8 x i32> %va) {
Show All 19 Lines; CHECK-NEXT: ret
%vc = icmp uge <vscale x 8 x i32> %va, %splat %vc = icmp uge <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_3(<vscale x 8 x i32> %va) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_3(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i32_3: ; CHECK-LABEL: icmp_uge_vi_nxv8i32_3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vmv.v.i v28, 1 ; CHECK-NEXT: vmsgtu.vi v0, v8, 0
; CHECK-NEXT: vmsleu.vv v0, v28, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 1, i32 0 %head = insertelement <vscale x 8 x i32> undef, i32 1, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i32> %va, %splat %vc = icmp uge <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_4(<vscale x 8 x i32> %va) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_4(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i32_4: ; CHECK-LABEL: icmp_uge_vi_nxv8i32_4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vmv.v.i v28, -15 ; CHECK-NEXT: vmsgtu.vi v0, v8, -16
; CHECK-NEXT: vmsleu.vv v0, v28, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0 %head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i32> %va, %splat %vc = icmp uge <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_5(<vscale x 8 x i32> %va) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_5(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i32_5: ; CHECK-LABEL: icmp_uge_vi_nxv8i32_5:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmsgtu.vi v0, v8, 15
; CHECK-NEXT: vmv.v.x v28, a0
; CHECK-NEXT: vmsleu.vv v0, v28, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 16, i32 0 %head = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i32> %va, %splat %vc = icmp uge <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) { define <vscale x 8 x i1> @icmp_ult_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i32> %va, %splat %vc = icmp ult <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_1(<vscale x 8 x i32> %va) { define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_ult_vi_nxv8i32_1: ; CHECK-LABEL: icmp_ult_vi_nxv8i32_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -15 ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmsleu.vi v0, v8, -16
; CHECK-NEXT: vmsltu.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0 %head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i32> %va, %splat %vc = icmp ult <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_iv_nxv8i32_1(<vscale x 8 x i32> %va) { define <vscale x 8 x i1> @icmp_ult_iv_nxv8i32_1(<vscale x 8 x i32> %va) {
Show All 30 Lines; CHECK-NEXT: ret
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i32> %va, %splat %vc = icmp ult <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_4(<vscale x 8 x i32> %va) { define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_4(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_ult_vi_nxv8i32_4: ; CHECK-LABEL: icmp_ult_vi_nxv8i32_4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmsleu.vi v0, v8, 15
; CHECK-NEXT: vmsltu.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 16, i32 0 %head = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i32> %va, %splat %vc = icmp ult <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ule_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) { define <vscale x 8 x i1> @icmp_ule_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
▲ Show 20 Lines • Show All 138 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%vc = icmp sge <vscale x 8 x i32> %va, %splat %vc = icmp sge <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_1(<vscale x 8 x i32> %va) { define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_sge_vi_nxv8i32_1: ; CHECK-LABEL: icmp_sge_vi_nxv8i32_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vmv.v.i v28, -15 ; CHECK-NEXT: vmsgt.vi v0, v8, -16
; CHECK-NEXT: vmsle.vv v0, v28, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0 %head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i32> %va, %splat %vc = icmp sge <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_iv_nxv8i32_1(<vscale x 8 x i32> %va) { define <vscale x 8 x i1> @icmp_sge_iv_nxv8i32_1(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_sge_iv_nxv8i32_1: ; CHECK-LABEL: icmp_sge_iv_nxv8i32_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vmsle.vi v0, v8, -15 ; CHECK-NEXT: vmsle.vi v0, v8, -15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0 %head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i32> %splat, %va %vc = icmp sge <vscale x 8 x i32> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_2(<vscale x 8 x i32> %va) { define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_2(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_sge_vi_nxv8i32_2: ; CHECK-LABEL: icmp_sge_vi_nxv8i32_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vmv.v.i v28, 0 ; CHECK-NEXT: vmsgt.vi v0, v8, -1
; CHECK-NEXT: vmsle.vv v0, v28, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 0, i32 0 %head = insertelement <vscale x 8 x i32> undef, i32 0, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i32> %va, %splat %vc = icmp sge <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_3(<vscale x 8 x i32> %va) { define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_3(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_sge_vi_nxv8i32_3: ; CHECK-LABEL: icmp_sge_vi_nxv8i32_3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmsgt.vi v0, v8, 15
; CHECK-NEXT: vmv.v.x v28, a0
; CHECK-NEXT: vmsle.vv v0, v28, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 16, i32 0 %head = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i32> %va, %splat %vc = icmp sge <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) { define <vscale x 8 x i1> @icmp_slt_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i32> %va, %splat %vc = icmp slt <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_1(<vscale x 8 x i32> %va) { define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_slt_vi_nxv8i32_1: ; CHECK-LABEL: icmp_slt_vi_nxv8i32_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -15 ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmsle.vi v0, v8, -16
; CHECK-NEXT: vmslt.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0 %head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i32> %va, %splat %vc = icmp slt <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_iv_nxv8i32_1(<vscale x 8 x i32> %va) { define <vscale x 8 x i1> @icmp_slt_iv_nxv8i32_1(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_slt_iv_nxv8i32_1: ; CHECK-LABEL: icmp_slt_iv_nxv8i32_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vmsgt.vi v0, v8, -15 ; CHECK-NEXT: vmsgt.vi v0, v8, -15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0 %head = insertelement <vscale x 8 x i32> undef, i32 -15, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i32> %splat, %va %vc = icmp slt <vscale x 8 x i32> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_2(<vscale x 8 x i32> %va) { define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_2(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_slt_vi_nxv8i32_2: ; CHECK-LABEL: icmp_slt_vi_nxv8i32_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vmslt.vx v0, v8, zero ; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 0, i32 0 %head = insertelement <vscale x 8 x i32> undef, i32 0, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i32> %va, %splat %vc = icmp slt <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_3(<vscale x 8 x i32> %va) { define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_3(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_slt_vi_nxv8i32_3: ; CHECK-LABEL: icmp_slt_vi_nxv8i32_3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vmsle.vi v0, v8, 15
; CHECK-NEXT: vmslt.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 16, i32 0 %head = insertelement <vscale x 8 x i32> undef, i32 16, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i32> %va, %splat %vc = icmp slt <vscale x 8 x i32> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sle_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) { define <vscale x 8 x i1> @icmp_sle_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
▲ Show 20 Lines • Show All 256 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%vc = icmp uge <vscale x 8 x i64> %va, %splat %vc = icmp uge <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_1(<vscale x 8 x i64> %va) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i64_1: ; CHECK-LABEL: icmp_uge_vi_nxv8i64_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vmv.v.i v16, 15 ; CHECK-NEXT: vmsgtu.vi v0, v8, 14
; CHECK-NEXT: vmsleu.vv v0, v16, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 15, i32 0 %head = insertelement <vscale x 8 x i64> undef, i64 15, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i64> %va, %splat %vc = icmp uge <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_iv_nxv8i64_1(<vscale x 8 x i64> %va) { define <vscale x 8 x i1> @icmp_uge_iv_nxv8i64_1(<vscale x 8 x i64> %va) {
Show All 19 Lines; CHECK-NEXT: ret
%vc = icmp uge <vscale x 8 x i64> %va, %splat %vc = icmp uge <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_3(<vscale x 8 x i64> %va) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_3(<vscale x 8 x i64> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i64_3: ; CHECK-LABEL: icmp_uge_vi_nxv8i64_3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vmv.v.i v16, 1 ; CHECK-NEXT: vmsgtu.vi v0, v8, 0
; CHECK-NEXT: vmsleu.vv v0, v16, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 1, i32 0 %head = insertelement <vscale x 8 x i64> undef, i64 1, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i64> %va, %splat %vc = icmp uge <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_4(<vscale x 8 x i64> %va) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_4(<vscale x 8 x i64> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i64_4: ; CHECK-LABEL: icmp_uge_vi_nxv8i64_4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vmv.v.i v16, -15 ; CHECK-NEXT: vmsgtu.vi v0, v8, -16
; CHECK-NEXT: vmsleu.vv v0, v16, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0 %head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i64> %va, %splat %vc = icmp uge <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_5(<vscale x 8 x i64> %va) { define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_5(<vscale x 8 x i64> %va) {
; CHECK-LABEL: icmp_uge_vi_nxv8i64_5: ; CHECK-LABEL: icmp_uge_vi_nxv8i64_5:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu ; CHECK-NEXT: vmsgtu.vi v0, v8, 15
; CHECK-NEXT: vmv.v.x v16, a0
; CHECK-NEXT: vmsleu.vv v0, v16, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0 %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp uge <vscale x 8 x i64> %va, %splat %vc = icmp uge <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) { define <vscale x 8 x i1> @icmp_ult_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i64> %va, %splat %vc = icmp ult <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_1(<vscale x 8 x i64> %va) { define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
; CHECK-LABEL: icmp_ult_vi_nxv8i64_1: ; CHECK-LABEL: icmp_ult_vi_nxv8i64_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -15 ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu ; CHECK-NEXT: vmsleu.vi v0, v8, -16
; CHECK-NEXT: vmsltu.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0 %head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i64> %va, %splat %vc = icmp ult <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_iv_nxv8i64_1(<vscale x 8 x i64> %va) { define <vscale x 8 x i1> @icmp_ult_iv_nxv8i64_1(<vscale x 8 x i64> %va) {
Show All 30 Lines; CHECK-NEXT: ret
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i64> %va, %splat %vc = icmp ult <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_4(<vscale x 8 x i64> %va) { define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_4(<vscale x 8 x i64> %va) {
; CHECK-LABEL: icmp_ult_vi_nxv8i64_4: ; CHECK-LABEL: icmp_ult_vi_nxv8i64_4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu ; CHECK-NEXT: vmsleu.vi v0, v8, 15
; CHECK-NEXT: vmsltu.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0 %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp ult <vscale x 8 x i64> %va, %splat %vc = icmp ult <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_ule_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) { define <vscale x 8 x i1> @icmp_ule_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
▲ Show 20 Lines • Show All 138 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%vc = icmp sge <vscale x 8 x i64> %va, %splat %vc = icmp sge <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_1(<vscale x 8 x i64> %va) { define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
; CHECK-LABEL: icmp_sge_vi_nxv8i64_1: ; CHECK-LABEL: icmp_sge_vi_nxv8i64_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vmv.v.i v16, -15 ; CHECK-NEXT: vmsgt.vi v0, v8, -16
; CHECK-NEXT: vmsle.vv v0, v16, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0 %head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i64> %va, %splat %vc = icmp sge <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_iv_nxv8i64_1(<vscale x 8 x i64> %va) { define <vscale x 8 x i1> @icmp_sge_iv_nxv8i64_1(<vscale x 8 x i64> %va) {
; CHECK-LABEL: icmp_sge_iv_nxv8i64_1: ; CHECK-LABEL: icmp_sge_iv_nxv8i64_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vmsle.vi v0, v8, -15 ; CHECK-NEXT: vmsle.vi v0, v8, -15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0 %head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i64> %splat, %va %vc = icmp sge <vscale x 8 x i64> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_2(<vscale x 8 x i64> %va) { define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
; CHECK-LABEL: icmp_sge_vi_nxv8i64_2: ; CHECK-LABEL: icmp_sge_vi_nxv8i64_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vmsgt.vi v0, v8, -1
; CHECK-NEXT: vmsle.vv v0, v16, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 0, i32 0 %head = insertelement <vscale x 8 x i64> undef, i64 0, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i64> %va, %splat %vc = icmp sge <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_3(<vscale x 8 x i64> %va) { define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_3(<vscale x 8 x i64> %va) {
; CHECK-LABEL: icmp_sge_vi_nxv8i64_3: ; CHECK-LABEL: icmp_sge_vi_nxv8i64_3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu ; CHECK-NEXT: vmsgt.vi v0, v8, 15
; CHECK-NEXT: vmv.v.x v16, a0
; CHECK-NEXT: vmsle.vv v0, v16, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0 %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp sge <vscale x 8 x i64> %va, %splat %vc = icmp sge <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) { define <vscale x 8 x i1> @icmp_slt_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
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%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i64> %va, %splat %vc = icmp slt <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_1(<vscale x 8 x i64> %va) { define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
; CHECK-LABEL: icmp_slt_vi_nxv8i64_1: ; CHECK-LABEL: icmp_slt_vi_nxv8i64_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -15 ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu ; CHECK-NEXT: vmsle.vi v0, v8, -16
; CHECK-NEXT: vmslt.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0 %head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i64> %va, %splat %vc = icmp slt <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_iv_nxv8i64_1(<vscale x 8 x i64> %va) { define <vscale x 8 x i1> @icmp_slt_iv_nxv8i64_1(<vscale x 8 x i64> %va) {
; CHECK-LABEL: icmp_slt_iv_nxv8i64_1: ; CHECK-LABEL: icmp_slt_iv_nxv8i64_1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vmsgt.vi v0, v8, -15 ; CHECK-NEXT: vmsgt.vi v0, v8, -15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0 %head = insertelement <vscale x 8 x i64> undef, i64 -15, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i64> %splat, %va %vc = icmp slt <vscale x 8 x i64> %splat, %va
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_2(<vscale x 8 x i64> %va) { define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
; CHECK-LABEL: icmp_slt_vi_nxv8i64_2: ; CHECK-LABEL: icmp_slt_vi_nxv8i64_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vmslt.vx v0, v8, zero ; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 0, i32 0 %head = insertelement <vscale x 8 x i64> undef, i64 0, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i64> %va, %splat %vc = icmp slt <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_3(<vscale x 8 x i64> %va) { define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_3(<vscale x 8 x i64> %va) {
; CHECK-LABEL: icmp_slt_vi_nxv8i64_3: ; CHECK-LABEL: icmp_slt_vi_nxv8i64_3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 16 ; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu ; CHECK-NEXT: vmsle.vi v0, v8, 15
; CHECK-NEXT: vmslt.vx v0, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0 %head = insertelement <vscale x 8 x i64> undef, i64 16, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
%vc = icmp slt <vscale x 8 x i64> %va, %splat %vc = icmp slt <vscale x 8 x i64> %va, %splat
ret <vscale x 8 x i1> %vc ret <vscale x 8 x i1> %vc
} }
define <vscale x 8 x i1> @icmp_sle_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) { define <vscale x 8 x i1> @icmp_sle_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
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