[CodeGen][AArch64] Fix isel crash for truncating FP stores

[david-arm]

Summary

When attempting to truncate a FP vector and store the result out
to memory we crashed because we had no pattern for truncating FP
stores. In fact, we don't support these types of stores and the
correct fix is to stop marking these truncating stores as legal.

Tests have been added here:

CodeGen/AArch64/sve-fptrunc-store.ll

[joechrisellis]

LGTM. 😄

[sdesmalen]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

1183

nit: could you leave a comment explaining why this is set to Expand?

llvm/test/CodeGen/AArch64/sve-fptrunc-store.ll

4

This check for a warning is no longer necessary since D98856

[david-arm]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

1183

Sure, there is no comment for the Neon case that I can borrow from, but I can write something like this if that seems reasonable?

// Avoid marking truncating FP stores as legal to prevent the DAGCombiner from creating
// unsupported truncating stores.

[david-arm]

• Added a comment and removed warnings check from test.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

for (auto VT : {MVT::nxv16i1, MVT::nxv8i1, MVT::nxv4i1, MVT::nxv2i1}) {
       if (VT != MVT::nxv16i1) {
         setOperationAction(ISD::SINT_TO_FP, VT, Custom);
         setOperationAction(ISD::UINT_TO_FP, VT, Custom);
       }
     }
 
     for (auto VT : {MVT::nxv2f16, MVT::nxv4f16, MVT::nxv8f16, MVT::nxv2f32,
                     MVT::nxv4f32, MVT::nxv2f64}) {
+      for (auto InnerVT : {MVT::nxv2f16, MVT::nxv4f16, MVT::nxv8f16,
+                           MVT::nxv2f32, MVT::nxv4f32, MVT::nxv2f64}) {
+        // Avoid marking truncating FP stores as legal to prevent the
+        // DAGCombiner from creating unsupported truncating stores.
+        setTruncStoreAction(VT, InnerVT, Expand);
+      }
+
       setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
       setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
       setOperationAction(ISD::MGATHER, VT, Custom);
       setOperationAction(ISD::MSCATTER, VT, Custom);
       setOperationAction(ISD::SPLAT_VECTOR, VT, Custom);
       setOperationAction(ISD::SELECT, VT, Custom);
       setOperationAction(ISD::FADD, VT, Custom);
       setOperationAction(ISD::FDIV, VT, Custom);

llvm/test/CodeGen/AArch64/sve-fptrunc-store.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve < %s | FileCheck %s
+
+define void @fptrunc2_f64_f32(<vscale x 2 x float> *%dst, <vscale x 2 x double> *%src) {
+; CHECK-LABEL: fptrunc2_f64_f32:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ptrue p0.d
+; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x1]
+; CHECK-NEXT:    fcvt z0.s, p0/m, z0.d
+; CHECK-NEXT:    st1w { z0.d }, p0, [x0]
+; CHECK-NEXT:    ret
+entry:
+  %0 = load <vscale x 2 x double>, <vscale x 2 x double>* %src, align 8
+  %1 = fptrunc <vscale x 2 x double> %0 to <vscale x 2 x float>
+  store <vscale x 2 x float> %1, <vscale x 2 x float>* %dst, align 4
+  ret void
+}
+
+define void @fptrunc2_f64_f16(<vscale x 2 x half> *%dst, <vscale x 2 x double> *%src) {
+; CHECK-LABEL: fptrunc2_f64_f16:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ptrue p0.d
+; CHECK-NEXT:    ld1d { z0.d }, p0/z, [x1]
+; CHECK-NEXT:    fcvt z0.h, p0/m, z0.d
+; CHECK-NEXT:    st1h { z0.d }, p0, [x0]
+; CHECK-NEXT:    ret
+entry:
+  %0 = load <vscale x 2 x double>, <vscale x 2 x double>* %src, align 8
+  %1 = fptrunc <vscale x 2 x double> %0 to <vscale x 2 x half>
+  store <vscale x 2 x half> %1, <vscale x 2 x half>* %dst, align 2
+  ret void
+}
+
+define void @fptrunc4_f32_f16(<vscale x 4 x half> *%dst, <vscale x 4 x float> *%src) {
+; CHECK-LABEL: fptrunc4_f32_f16:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    ld1w { z0.s }, p0/z, [x1]
+; CHECK-NEXT:    fcvt z0.h, p0/m, z0.s
+; CHECK-NEXT:    st1h { z0.s }, p0, [x0]
+; CHECK-NEXT:    ret
+entry:
+  %0 = load <vscale x 4 x float>, <vscale x 4 x float>* %src, align 8
+  %1 = fptrunc <vscale x 4 x float> %0 to <vscale x 4 x half>
+  store <vscale x 4 x half> %1, <vscale x 4 x half>* %dst, align 2
+  ret void
+}
+
+define void @fptrunc2_f32_f16(<vscale x 2 x half> *%dst, <vscale x 2 x float> *%src) {
+; CHECK-LABEL: fptrunc2_f32_f16:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ptrue p0.d
+; CHECK-NEXT:    ld1w { z0.d }, p0/z, [x1]
+; CHECK-NEXT:    fcvt z0.h, p0/m, z0.s
+; CHECK-NEXT:    st1h { z0.d }, p0, [x0]
+; CHECK-NEXT:    ret
+entry:
+  %0 = load <vscale x 2 x float>, <vscale x 2 x float>* %src, align 8
+  %1 = fptrunc <vscale x 2 x float> %0 to <vscale x 2 x half>
+  store <vscale x 2 x half> %1, <vscale x 2 x half>* %dst, align 2
+  ret void
+}