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Differential D99637

[RISCV] Add isel patterns to select vsub_vx intrinsic to vadd.vi if it uses a small enough immediate
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Authored by craig.topper on Mar 30 2021, 9:50 PM.

Details

Reviewers
khchen
HsiangKai
frasercrmck
evandro
arcbbb
Commits
rG04f10ab367b5: [RISCV] Add isel patterns to select vsub_vx intrinsic to vadd.vi if it uses a…
Summary

Also modify the simm5_plus1 check because Imm-1 is UB if Imm happens
to be INT64_MIN. I don't think the compiler would optimize based on that in this
usage, but it could fail UBSan or -ftrapv.

Diff Detail

Unit TestsFailed

TimeTest
200 msx64 debian > LLVM.CodeGen/RISCV/rvv::vsub-rv32.ll
260 msx64 debian > LLVM.CodeGen/RISCV/rvv::vsub-rv64.ll
330 msx64 windows > LLVM.CodeGen/RISCV/rvv::vsub-rv32.ll
290 msx64 windows > LLVM.CodeGen/RISCV/rvv::vsub-rv64.ll

Event Timeline

craig.topper created this revision.Mar 30 2021, 9:50 PM
Herald added subscribers: StephenFan, vkmr, luismarques and 23 others. · View Herald TranscriptMar 30 2021, 9:50 PM
craig.topper requested review of this revision.Mar 30 2021, 9:50 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 30 2021, 9:50 PM
Herald added a subscriber: MaskRay. · View Herald Transcript
craig.topper updated this revision to Diff 334341.Mar 30 2021, 9:51 PM

Upload the patterns too.

Herald added a subscriber: hiraditya. · View Herald TranscriptMar 30 2021, 9:51 PM
craig.topper retitled this revision from [RISCV] Add isel patterns to select vsub_vx intrinsic to vadd.vi if the immediate is small enough. to [RISCV] Add isel patterns to select vsub_vx intrinsic to vadd.vi if it uses a small enough immediate.Mar 30 2021, 9:55 PM
craig.topper edited the summary of this revision. (Show Details)
Harbormaster completed remote builds in B96455: Diff 334340.Mar 30 2021, 10:22 PM
Harbormaster completed remote builds in B96456: Diff 334341.Mar 30 2021, 10:31 PM
HsiangKai accepted this revision.Mar 31 2021, 2:06 AM

LGTM.

This revision is now accepted and ready to land.Mar 31 2021, 2:06 AM
frasercrmck accepted this revision.Mar 31 2021, 2:29 AM
Closed by commit rG04f10ab367b5: [RISCV] Add isel patterns to select vsub_vx intrinsic to vadd.vi if it uses a… (authored by craig.topper). · Explain WhyMar 31 2021, 9:27 AM
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG04f10ab367b5: [RISCV] Add isel patterns to select vsub_vx intrinsic to vadd.vi if it uses a….

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
rvv/
576 lines
704 lines

Diff 334340

llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll

Show First 20 Lines • Show All 1,581 Lines • ▼ Show 20 Lines %a = call <vscale x 16 x i32> @llvm.riscv.vsub.mask.nxv16i32.i32(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
i32 %2, i32 %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
define <vscale x 1 x i8> @intrinsic_vsub_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8(
<vscale x 1 x i8> %0,
i8 9,
i32 %1)
ret <vscale x 1 x i8> %a
}
define <vscale x 1 x i8> @intrinsic_vsub_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu
; CHECK-NEXT: vadd.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsub.mask.nxv1i8.i8(
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
i8 -9,
<vscale x 1 x i1> %2,
i32 %3)
ret <vscale x 1 x i8> %a
}
define <vscale x 2 x i8> @intrinsic_vsub_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8(
<vscale x 2 x i8> %0,
i8 9,
i32 %1)
ret <vscale x 2 x i8> %a
}
define <vscale x 2 x i8> @intrinsic_vsub_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu
; CHECK-NEXT: vadd.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vsub.mask.nxv2i8.i8(
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
i8 -9,
<vscale x 2 x i1> %2,
i32 %3)
ret <vscale x 2 x i8> %a
}
define <vscale x 4 x i8> @intrinsic_vsub_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8(
<vscale x 4 x i8> %0,
i8 9,
i32 %1)
ret <vscale x 4 x i8> %a
}
define <vscale x 4 x i8> @intrinsic_vsub_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu
; CHECK-NEXT: vadd.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vsub.mask.nxv4i8.i8(
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
i8 -9,
<vscale x 4 x i1> %2,
i32 %3)
ret <vscale x 4 x i8> %a
}
define <vscale x 8 x i8> @intrinsic_vsub_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8(
<vscale x 8 x i8> %0,
i8 9,
i32 %1)
ret <vscale x 8 x i8> %a
}
define <vscale x 8 x i8> @intrinsic_vsub_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu
; CHECK-NEXT: vadd.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vsub.mask.nxv8i8.i8(
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
i8 -9,
<vscale x 8 x i1> %2,
i32 %3)
ret <vscale x 8 x i8> %a
}
define <vscale x 16 x i8> @intrinsic_vsub_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.i8(
<vscale x 16 x i8> %0,
i8 9,
i32 %1)
ret <vscale x 16 x i8> %a
}
define <vscale x 16 x i8> @intrinsic_vsub_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu
; CHECK-NEXT: vadd.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vsub.mask.nxv16i8.i8(
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
i8 -9,
<vscale x 16 x i1> %2,
i32 %3)
ret <vscale x 16 x i8> %a
}
define <vscale x 32 x i8> @intrinsic_vsub_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vsub.nxv32i8.i8(
<vscale x 32 x i8> %0,
i8 9,
i32 %1)
ret <vscale x 32 x i8> %a
}
define <vscale x 32 x i8> @intrinsic_vsub_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu
; CHECK-NEXT: vadd.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vsub.mask.nxv32i8.i8(
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
i8 -9,
<vscale x 32 x i1> %2,
i32 %3)
ret <vscale x 32 x i8> %a
}
define <vscale x 64 x i8> @intrinsic_vsub_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, 9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsub.nxv64i8.i8(
<vscale x 64 x i8> %0,
i8 -9,
i32 %1)
ret <vscale x 64 x i8> %a
}
define <vscale x 64 x i8> @intrinsic_vsub_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu
; CHECK-NEXT: vadd.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsub.mask.nxv64i8.i8(
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
i8 -9,
<vscale x 64 x i1> %2,
i32 %3)
ret <vscale x 64 x i8> %a
}
define <vscale x 1 x i16> @intrinsic_vsub_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsub.nxv1i16.i16(
<vscale x 1 x i16> %0,
i16 9,
i32 %1)
ret <vscale x 1 x i16> %a
}
define <vscale x 1 x i16> @intrinsic_vsub_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vadd.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsub.mask.nxv1i16.i16(
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
i16 -9,
<vscale x 1 x i1> %2,
i32 %3)
ret <vscale x 1 x i16> %a
}
define <vscale x 2 x i16> @intrinsic_vsub_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsub.nxv2i16.i16(
<vscale x 2 x i16> %0,
i16 9,
i32 %1)
ret <vscale x 2 x i16> %a
}
define <vscale x 2 x i16> @intrinsic_vsub_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vadd.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsub.mask.nxv2i16.i16(
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
i16 -9,
<vscale x 2 x i1> %2,
i32 %3)
ret <vscale x 2 x i16> %a
}
define <vscale x 4 x i16> @intrinsic_vsub_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsub.nxv4i16.i16(
<vscale x 4 x i16> %0,
i16 9,
i32 %1)
ret <vscale x 4 x i16> %a
}
define <vscale x 4 x i16> @intrinsic_vsub_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vadd.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsub.mask.nxv4i16.i16(
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
i16 -9,
<vscale x 4 x i1> %2,
i32 %3)
ret <vscale x 4 x i16> %a
}
define <vscale x 8 x i16> @intrinsic_vsub_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsub.nxv8i16.i16(
<vscale x 8 x i16> %0,
i16 9,
i32 %1)
ret <vscale x 8 x i16> %a
}
define <vscale x 8 x i16> @intrinsic_vsub_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vadd.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsub.mask.nxv8i16.i16(
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
i16 -9,
<vscale x 8 x i1> %2,
i32 %3)
ret <vscale x 8 x i16> %a
}
define <vscale x 16 x i16> @intrinsic_vsub_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsub.nxv16i16.i16(
<vscale x 16 x i16> %0,
i16 9,
i32 %1)
ret <vscale x 16 x i16> %a
}
define <vscale x 16 x i16> @intrinsic_vsub_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vadd.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsub.mask.nxv16i16.i16(
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
i16 -9,
<vscale x 16 x i1> %2,
i32 %3)
ret <vscale x 16 x i16> %a
}
define <vscale x 32 x i16> @intrinsic_vsub_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsub.nxv32i16.i16(
<vscale x 32 x i16> %0,
i16 9,
i32 %1)
ret <vscale x 32 x i16> %a
}
define <vscale x 32 x i16> @intrinsic_vsub_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu
; CHECK-NEXT: vadd.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsub.mask.nxv32i16.i16(
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
i16 -9,
<vscale x 32 x i1> %2,
i32 %3)
ret <vscale x 32 x i16> %a
}
define <vscale x 1 x i32> @intrinsic_vsub_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsub.nxv1i32.i32(
<vscale x 1 x i32> %0,
i32 9,
i32 %1)
ret <vscale x 1 x i32> %a
}
define <vscale x 1 x i32> @intrinsic_vsub_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vadd.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsub.mask.nxv1i32.i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
i32 -9,
<vscale x 1 x i1> %2,
i32 %3)
ret <vscale x 1 x i32> %a
}
define <vscale x 2 x i32> @intrinsic_vsub_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsub.nxv2i32.i32(
<vscale x 2 x i32> %0,
i32 9,
i32 %1)
ret <vscale x 2 x i32> %a
}
define <vscale x 2 x i32> @intrinsic_vsub_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vadd.vi v8, v9, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsub.mask.nxv2i32.i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
i32 -9,
<vscale x 2 x i1> %2,
i32 %3)
ret <vscale x 2 x i32> %a
}
define <vscale x 4 x i32> @intrinsic_vsub_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsub.nxv4i32.i32(
<vscale x 4 x i32> %0,
i32 9,
i32 %1)
ret <vscale x 4 x i32> %a
}
define <vscale x 4 x i32> @intrinsic_vsub_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vadd.vi v8, v10, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsub.mask.nxv4i32.i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
i32 -9,
<vscale x 4 x i1> %2,
i32 %3)
ret <vscale x 4 x i32> %a
}
define <vscale x 8 x i32> @intrinsic_vsub_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsub.nxv8i32.i32(
<vscale x 8 x i32> %0,
i32 9,
i32 %1)
ret <vscale x 8 x i32> %a
}
define <vscale x 8 x i32> @intrinsic_vsub_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vadd.vi v8, v12, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsub.mask.nxv8i32.i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
i32 -9,
<vscale x 8 x i1> %2,
i32 %3)
ret <vscale x 8 x i32> %a
}
define <vscale x 16 x i32> @intrinsic_vsub_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i32 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsub.nxv16i32.i32(
<vscale x 16 x i32> %0,
i32 9,
i32 %1)
ret <vscale x 16 x i32> %a
}
define <vscale x 16 x i32> @intrinsic_vsub_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu
; CHECK-NEXT: vadd.vi v8, v16, 9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsub.mask.nxv16i32.i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
i32 -9,
<vscale x 16 x i1> %2,
i32 %3)
ret <vscale x 16 x i32> %a
}

llvm/test/CodeGen/RISCV/rvv/vsub-rv64.ll

Show First 20 Lines • Show All 1,934 Lines • ▼ Show 20 Lines %a = call <vscale x 8 x i64> @llvm.riscv.vsub.mask.nxv8i64.i64(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
i64 %2, i64 %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
define <vscale x 1 x i8> @intrinsic_vsub_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsub.nxv1i8.i8(
<vscale x 1 x i8> %0,
i8 9,
i64 %1)
ret <vscale x 1 x i8> %a
}
define <vscale x 1 x i8> @intrinsic_vsub_mask_vi_nxv1i8_nxv1i8_i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv1i8_nxv1i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu
; CHECK-NEXT: vadd.vi v8, v9, -9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vsub.mask.nxv1i8.i8(
<vscale x 1 x i8> %0,
<vscale x 1 x i8> %1,
i8 9,
<vscale x 1 x i1> %2,
i64 %3)
ret <vscale x 1 x i8> %a
}
define <vscale x 2 x i8> @intrinsic_vsub_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vsub.nxv2i8.i8(
<vscale x 2 x i8> %0,
i8 9,
i64 %1)
ret <vscale x 2 x i8> %a
}
define <vscale x 2 x i8> @intrinsic_vsub_mask_vi_nxv2i8_nxv2i8_i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv2i8_nxv2i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu
; CHECK-NEXT: vadd.vi v8, v9, -9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vsub.mask.nxv2i8.i8(
<vscale x 2 x i8> %0,
<vscale x 2 x i8> %1,
i8 9,
<vscale x 2 x i1> %2,
i64 %3)
ret <vscale x 2 x i8> %a
}
define <vscale x 4 x i8> @intrinsic_vsub_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vsub.nxv4i8.i8(
<vscale x 4 x i8> %0,
i8 9,
i64 %1)
ret <vscale x 4 x i8> %a
}
define <vscale x 4 x i8> @intrinsic_vsub_mask_vi_nxv4i8_nxv4i8_i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv4i8_nxv4i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu
; CHECK-NEXT: vadd.vi v8, v9, -9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vsub.mask.nxv4i8.i8(
<vscale x 4 x i8> %0,
<vscale x 4 x i8> %1,
i8 9,
<vscale x 4 x i1> %2,
i64 %3)
ret <vscale x 4 x i8> %a
}
define <vscale x 8 x i8> @intrinsic_vsub_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vsub.nxv8i8.i8(
<vscale x 8 x i8> %0,
i8 9,
i64 %1)
ret <vscale x 8 x i8> %a
}
define <vscale x 8 x i8> @intrinsic_vsub_mask_vi_nxv8i8_nxv8i8_i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv8i8_nxv8i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu
; CHECK-NEXT: vadd.vi v8, v9, -9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vsub.mask.nxv8i8.i8(
<vscale x 8 x i8> %0,
<vscale x 8 x i8> %1,
i8 9,
<vscale x 8 x i1> %2,
i64 %3)
ret <vscale x 8 x i8> %a
}
define <vscale x 16 x i8> @intrinsic_vsub_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vsub.nxv16i8.i8(
<vscale x 16 x i8> %0,
i8 9,
i64 %1)
ret <vscale x 16 x i8> %a
}
define <vscale x 16 x i8> @intrinsic_vsub_mask_vi_nxv16i8_nxv16i8_i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv16i8_nxv16i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu
; CHECK-NEXT: vadd.vi v8, v10, -9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vsub.mask.nxv16i8.i8(
<vscale x 16 x i8> %0,
<vscale x 16 x i8> %1,
i8 9,
<vscale x 16 x i1> %2,
i64 %3)
ret <vscale x 16 x i8> %a
}
define <vscale x 32 x i8> @intrinsic_vsub_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vsub.nxv32i8.i8(
<vscale x 32 x i8> %0,
i8 9,
i64 %1)
ret <vscale x 32 x i8> %a
}
define <vscale x 32 x i8> @intrinsic_vsub_mask_vi_nxv32i8_nxv32i8_i8(<vscale x 32 x i8> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv32i8_nxv32i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu
; CHECK-NEXT: vadd.vi v8, v12, -9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vsub.mask.nxv32i8.i8(
<vscale x 32 x i8> %0,
<vscale x 32 x i8> %1,
i8 9,
<vscale x 32 x i1> %2,
i64 %3)
ret <vscale x 32 x i8> %a
}
define <vscale x 64 x i8> @intrinsic_vsub_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m8,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsub.nxv64i8.i8(
<vscale x 64 x i8> %0,
i8 9,
i64 %1)
ret <vscale x 64 x i8> %a
}
define <vscale x 64 x i8> @intrinsic_vsub_mask_vi_nxv64i8_nxv64i8_i8(<vscale x 64 x i8> %0, <vscale x 64 x i8> %1, <vscale x 64 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv64i8_nxv64i8_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e8,m8,tu,mu
; CHECK-NEXT: vadd.vi v8, v16, -9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vsub.mask.nxv64i8.i8(
<vscale x 64 x i8> %0,
<vscale x 64 x i8> %1,
i8 9,
<vscale x 64 x i1> %2,
i64 %3)
ret <vscale x 64 x i8> %a
}
define <vscale x 1 x i16> @intrinsic_vsub_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsub.nxv1i16.i16(
<vscale x 1 x i16> %0,
i16 9,
i64 %1)
ret <vscale x 1 x i16> %a
}
define <vscale x 1 x i16> @intrinsic_vsub_mask_vi_nxv1i16_nxv1i16_i16(<vscale x 1 x i16> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv1i16_nxv1i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
; CHECK-NEXT: vadd.vi v8, v9, -9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vsub.mask.nxv1i16.i16(
<vscale x 1 x i16> %0,
<vscale x 1 x i16> %1,
i16 9,
<vscale x 1 x i1> %2,
i64 %3)
ret <vscale x 1 x i16> %a
}
define <vscale x 2 x i16> @intrinsic_vsub_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsub.nxv2i16.i16(
<vscale x 2 x i16> %0,
i16 9,
i64 %1)
ret <vscale x 2 x i16> %a
}
define <vscale x 2 x i16> @intrinsic_vsub_mask_vi_nxv2i16_nxv2i16_i16(<vscale x 2 x i16> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv2i16_nxv2i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
; CHECK-NEXT: vadd.vi v8, v9, -9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vsub.mask.nxv2i16.i16(
<vscale x 2 x i16> %0,
<vscale x 2 x i16> %1,
i16 9,
<vscale x 2 x i1> %2,
i64 %3)
ret <vscale x 2 x i16> %a
}
define <vscale x 4 x i16> @intrinsic_vsub_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsub.nxv4i16.i16(
<vscale x 4 x i16> %0,
i16 9,
i64 %1)
ret <vscale x 4 x i16> %a
}
define <vscale x 4 x i16> @intrinsic_vsub_mask_vi_nxv4i16_nxv4i16_i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv4i16_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
; CHECK-NEXT: vadd.vi v8, v9, -9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vsub.mask.nxv4i16.i16(
<vscale x 4 x i16> %0,
<vscale x 4 x i16> %1,
i16 9,
<vscale x 4 x i1> %2,
i64 %3)
ret <vscale x 4 x i16> %a
}
define <vscale x 8 x i16> @intrinsic_vsub_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsub.nxv8i16.i16(
<vscale x 8 x i16> %0,
i16 9,
i64 %1)
ret <vscale x 8 x i16> %a
}
define <vscale x 8 x i16> @intrinsic_vsub_mask_vi_nxv8i16_nxv8i16_i16(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv8i16_nxv8i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
; CHECK-NEXT: vadd.vi v8, v10, -9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vsub.mask.nxv8i16.i16(
<vscale x 8 x i16> %0,
<vscale x 8 x i16> %1,
i16 9,
<vscale x 8 x i1> %2,
i64 %3)
ret <vscale x 8 x i16> %a
}
define <vscale x 16 x i16> @intrinsic_vsub_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsub.nxv16i16.i16(
<vscale x 16 x i16> %0,
i16 9,
i64 %1)
ret <vscale x 16 x i16> %a
}
define <vscale x 16 x i16> @intrinsic_vsub_mask_vi_nxv16i16_nxv16i16_i16(<vscale x 16 x i16> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv16i16_nxv16i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
; CHECK-NEXT: vadd.vi v8, v12, -9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vsub.mask.nxv16i16.i16(
<vscale x 16 x i16> %0,
<vscale x 16 x i16> %1,
i16 9,
<vscale x 16 x i1> %2,
i64 %3)
ret <vscale x 16 x i16> %a
}
define <vscale x 32 x i16> @intrinsic_vsub_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsub.nxv32i16.i16(
<vscale x 32 x i16> %0,
i16 9,
i64 %1)
ret <vscale x 32 x i16> %a
}
define <vscale x 32 x i16> @intrinsic_vsub_mask_vi_nxv32i16_nxv32i16_i16(<vscale x 32 x i16> %0, <vscale x 32 x i16> %1, <vscale x 32 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv32i16_nxv32i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e16,m8,tu,mu
; CHECK-NEXT: vadd.vi v8, v16, -9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vsub.mask.nxv32i16.i16(
<vscale x 32 x i16> %0,
<vscale x 32 x i16> %1,
i16 9,
<vscale x 32 x i1> %2,
i64 %3)
ret <vscale x 32 x i16> %a
}
define <vscale x 1 x i32> @intrinsic_vsub_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsub.nxv1i32.i32(
<vscale x 1 x i32> %0,
i32 9,
i64 %1)
ret <vscale x 1 x i32> %a
}
define <vscale x 1 x i32> @intrinsic_vsub_mask_vi_nxv1i32_nxv1i32_i32(<vscale x 1 x i32> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv1i32_nxv1i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
; CHECK-NEXT: vadd.vi v8, v9, -9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vsub.mask.nxv1i32.i32(
<vscale x 1 x i32> %0,
<vscale x 1 x i32> %1,
i32 9,
<vscale x 1 x i1> %2,
i64 %3)
ret <vscale x 1 x i32> %a
}
define <vscale x 2 x i32> @intrinsic_vsub_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsub.nxv2i32.i32(
<vscale x 2 x i32> %0,
i32 9,
i64 %1)
ret <vscale x 2 x i32> %a
}
define <vscale x 2 x i32> @intrinsic_vsub_mask_vi_nxv2i32_nxv2i32_i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv2i32_nxv2i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
; CHECK-NEXT: vadd.vi v8, v9, -9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vsub.mask.nxv2i32.i32(
<vscale x 2 x i32> %0,
<vscale x 2 x i32> %1,
i32 9,
<vscale x 2 x i1> %2,
i64 %3)
ret <vscale x 2 x i32> %a
}
define <vscale x 4 x i32> @intrinsic_vsub_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsub.nxv4i32.i32(
<vscale x 4 x i32> %0,
i32 9,
i64 %1)
ret <vscale x 4 x i32> %a
}
define <vscale x 4 x i32> @intrinsic_vsub_mask_vi_nxv4i32_nxv4i32_i32(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv4i32_nxv4i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
; CHECK-NEXT: vadd.vi v8, v10, -9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vsub.mask.nxv4i32.i32(
<vscale x 4 x i32> %0,
<vscale x 4 x i32> %1,
i32 9,
<vscale x 4 x i1> %2,
i64 %3)
ret <vscale x 4 x i32> %a
}
define <vscale x 8 x i32> @intrinsic_vsub_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsub.nxv8i32.i32(
<vscale x 8 x i32> %0,
i32 9,
i64 %1)
ret <vscale x 8 x i32> %a
}
define <vscale x 8 x i32> @intrinsic_vsub_mask_vi_nxv8i32_nxv8i32_i32(<vscale x 8 x i32> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv8i32_nxv8i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
; CHECK-NEXT: vadd.vi v8, v12, -9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vsub.mask.nxv8i32.i32(
<vscale x 8 x i32> %0,
<vscale x 8 x i32> %1,
i32 9,
<vscale x 8 x i1> %2,
i64 %3)
ret <vscale x 8 x i32> %a
}
define <vscale x 16 x i32> @intrinsic_vsub_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsub.nxv16i32.i32(
<vscale x 16 x i32> %0,
i32 9,
i64 %1)
ret <vscale x 16 x i32> %a
}
define <vscale x 16 x i32> @intrinsic_vsub_mask_vi_nxv16i32_nxv16i32_i32(<vscale x 16 x i32> %0, <vscale x 16 x i32> %1, <vscale x 16 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv16i32_nxv16i32_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e32,m8,tu,mu
; CHECK-NEXT: vadd.vi v8, v16, -9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vsub.mask.nxv16i32.i32(
<vscale x 16 x i32> %0,
<vscale x 16 x i32> %1,
i32 9,
<vscale x 16 x i1> %2,
i64 %3)
ret <vscale x 16 x i32> %a
}
define <vscale x 1 x i64> @intrinsic_vsub_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsub.nxv1i64.i64(
<vscale x 1 x i64> %0,
i64 9,
i64 %1)
ret <vscale x 1 x i64> %a
}
define <vscale x 1 x i64> @intrinsic_vsub_mask_vi_nxv1i64_nxv1i64_i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv1i64_nxv1i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m1,tu,mu
; CHECK-NEXT: vadd.vi v8, v9, -9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vsub.mask.nxv1i64.i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64> %1,
i64 9,
<vscale x 1 x i1> %2,
i64 %3)
ret <vscale x 1 x i64> %a
}
define <vscale x 2 x i64> @intrinsic_vsub_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsub.nxv2i64.i64(
<vscale x 2 x i64> %0,
i64 9,
i64 %1)
ret <vscale x 2 x i64> %a
}
define <vscale x 2 x i64> @intrinsic_vsub_mask_vi_nxv2i64_nxv2i64_i64(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv2i64_nxv2i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m2,tu,mu
; CHECK-NEXT: vadd.vi v8, v10, -9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vsub.mask.nxv2i64.i64(
<vscale x 2 x i64> %0,
<vscale x 2 x i64> %1,
i64 9,
<vscale x 2 x i1> %2,
i64 %3)
ret <vscale x 2 x i64> %a
}
define <vscale x 4 x i64> @intrinsic_vsub_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsub.nxv4i64.i64(
<vscale x 4 x i64> %0,
i64 9,
i64 %1)
ret <vscale x 4 x i64> %a
}
define <vscale x 4 x i64> @intrinsic_vsub_mask_vi_nxv4i64_nxv4i64_i64(<vscale x 4 x i64> %0, <vscale x 4 x i64> %1, <vscale x 4 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv4i64_nxv4i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m4,tu,mu
; CHECK-NEXT: vadd.vi v8, v12, -9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vsub.mask.nxv4i64.i64(
<vscale x 4 x i64> %0,
<vscale x 4 x i64> %1,
i64 9,
<vscale x 4 x i1> %2,
i64 %3)
ret <vscale x 4 x i64> %a
}
define <vscale x 8 x i64> @intrinsic_vsub_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, i64 %1) nounwind {
; CHECK-LABEL: intrinsic_vsub_vi_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,ta,mu
; CHECK-NEXT: vadd.vi v8, v8, -9
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsub.nxv8i64.i64(
<vscale x 8 x i64> %0,
i64 9,
i64 %1)
ret <vscale x 8 x i64> %a
}
define <vscale x 8 x i64> @intrinsic_vsub_mask_vi_nxv8i64_nxv8i64_i64(<vscale x 8 x i64> %0, <vscale x 8 x i64> %1, <vscale x 8 x i1> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsub_mask_vi_nxv8i64_nxv8i64_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, a0, e64,m8,tu,mu
; CHECK-NEXT: vadd.vi v8, v16, -9, v0.t
; CHECK-NEXT: jalr zero, 0(ra)
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vsub.mask.nxv8i64.i64(
<vscale x 8 x i64> %0,
<vscale x 8 x i64> %1,
i64 9,
<vscale x 8 x i1> %2,
i64 %3)
ret <vscale x 8 x i64> %a
}