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Differential D99460

[X86][update_llc_test_checks] Use a less greedy regular expression for replacing constant pool labels in tests.
ClosedPublic

Authored by craig.topper on Mar 27 2021, 4:47 PM.

Details

Reviewers
RKSimon
spatel
MaskRay
pengfei
Commits
rG0248e2407166: [X86][update_llc_test_checks] Use a less greedy regular expression for…
Summary

While working on D97208 I noticed that these greedy regular
expressions prevent tests from failing when (%rip) appears after
a constant pool label when it didn't before.

Diff Detail

Unit TestsFailed

TimeTest
26,400 msx64 windows > Clang.Driver::linux-ld.c

Event Timeline

craig.topper created this revision.Mar 27 2021, 4:47 PM
Herald added subscribers: pengfei, arphaman, arichardson. · View Herald TranscriptMar 27 2021, 4:47 PM
craig.topper requested review of this revision.Mar 27 2021, 4:47 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 27 2021, 4:47 PM
craig.topper mentioned this in D97208: [X86] Always use rip-relative addressing on 64-bit when rematerializing all zeros/ones registers using a folded load..Mar 27 2021, 4:58 PM
craig.topper added a child revision: D97208: [X86] Always use rip-relative addressing on 64-bit when rematerializing all zeros/ones registers using a folded load..Mar 27 2021, 4:58 PM
Harbormaster completed remote builds in B95987: Diff 333701.Mar 27 2021, 5:26 PM
pengfei added a comment.Mar 27 2021, 8:34 PM

Are these changed manually? Can we update them with --no_x86_scrub_rip, i.e.

llvm/utils/update_llc_test_checks.py llvm/test/CodeGen/X86/WidenArith.ll --no_x86_scrub_rip
pengfei added a comment.Mar 27 2021, 8:42 PM
In D99460#2654420, @pengfei wrote:

Are these changed manually? Can we update them with --no_x86_scrub_rip, i.e.

llvm/utils/update_llc_test_checks.py llvm/test/CodeGen/X86/WidenArith.ll --no_x86_scrub_rip

Oh, I saw the change on script. LGTM~

craig.topper added a comment.Mar 27 2021, 8:54 PM
In D99460#2654420, @pengfei wrote:

Are these changed manually? Can we update them with --no_x86_scrub_rip, i.e.

llvm/utils/update_llc_test_checks.py llvm/test/CodeGen/X86/WidenArith.ll --no_x86_scrub_rip

I modified asm.py and made it print this now. Most of the affected tests are 32-bit tests that don't use %rip so -no_x86_scrub_rip wouldn't affect them.

For 64-bit tests scrubbing rip replaces any tests before (%rip) with a regular expression like {{.*}}(%rip). The test check line will always contain %rip if it is part of the assembly. This matches before the LCP match. So for most 64-bit tests the presence of %rip prevents the LCP from being replaced with {{\.LCPI.*}}.

For cases affected by D97208, %rip is not currently present so the LCP scrub kicks in. Producing {{\.LCPI.*}} followed by a comma. Because that regex is greedy it will match up to the next comma. So whether there is an %rip in asm or not the regex will alway match. If you apply the X86InstrInfo.cpp and run the script on avx-cmp.ll and mmx-fold-zero.ll you'll get

{{.*}}(%rip)

If you add -no_x86_scrub_rip you'll get

{{LCPI.*}}(%rip)
pengfei added a comment.Mar 27 2021, 9:47 PM
In D99460#2654427, @craig.topper wrote:
In D99460#2654420, @pengfei wrote:

Are these changed manually? Can we update them with --no_x86_scrub_rip, i.e.

llvm/utils/update_llc_test_checks.py llvm/test/CodeGen/X86/WidenArith.ll --no_x86_scrub_rip

I modified asm.py and made it print this now. Most of the affected tests are 32-bit tests that don't use %rip so -no_x86_scrub_rip wouldn't affect them.

For 64-bit tests scrubbing rip replaces any tests before (%rip) with a regular expression like {{.*}}(%rip). The test check line will always contain %rip if it is part of the assembly. This matches before the LCP match. So for most 64-bit tests the presence of %rip prevents the LCP from being replaced with {{\.LCPI.*}}.

For cases affected by D97208, %rip is not currently present so the LCP scrub kicks in. Producing {{\.LCPI.*}} followed by a comma. Because that regex is greedy it will match up to the next comma. So whether there is an %rip in asm or not the regex will alway match. If you apply the X86InstrInfo.cpp and run the script on avx-cmp.ll and mmx-fold-zero.ll you'll get

{{.*}}(%rip)

If you add -no_x86_scrub_rip you'll get

{{LCPI.*}}(%rip)

I see, thanks.

llvm/test/CodeGen/X86/WidenArith.ll
14

Nit: Should this be simplified to [0-9_]+?

craig.topper added inline comments.Mar 27 2021, 10:43 PM
llvm/test/CodeGen/X86/WidenArith.ll
14

We could but I thought it was best to keep it in sync with the scrub regex

SCRUB_X86_LCP_RE = re.compile(r'\.LCPI[0-9]+_[0-9]+')
pengfei accepted this revision.Mar 28 2021, 1:48 AM

LGTM.

llvm/test/CodeGen/X86/WidenArith.ll
14

Agreed.

This revision is now accepted and ready to land.Mar 28 2021, 1:48 AM
RKSimon accepted this revision.Mar 28 2021, 3:47 AM

LGTM

This revision was landed with ongoing or failed builds.Mar 28 2021, 11:40 AM
Closed by commit rG0248e2407166: [X86][update_llc_test_checks] Use a less greedy regular expression for… (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG0248e2407166: [X86][update_llc_test_checks] Use a less greedy regular expression for….

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UpdateTestChecks/
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Diff 333701

llvm/test/CodeGen/X86/WidenArith.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X86 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X64
define <8 x i32> @test(<8 x float> %a, <8 x float> %b) { define <8 x i32> @test(<8 x float> %a, <8 x float> %b) {
; X86-LABEL: test: ; X86-LABEL: test:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vaddps %ymm1, %ymm0, %ymm2 ; X86-NEXT: vaddps %ymm1, %ymm0, %ymm2
; X86-NEXT: vmulps %ymm0, %ymm1, %ymm1 ; X86-NEXT: vmulps %ymm0, %ymm1, %ymm1
; X86-NEXT: vsubps %ymm2, %ymm1, %ymm3 ; X86-NEXT: vsubps %ymm2, %ymm1, %ymm3
; X86-NEXT: vcmpltps %ymm1, %ymm0, %ymm0 ; X86-NEXT: vcmpltps %ymm1, %ymm0, %ymm0
; X86-NEXT: vcmpltps %ymm3, %ymm2, %ymm1 ; X86-NEXT: vcmpltps %ymm3, %ymm2, %ymm1
; X86-NEXT: vandps %ymm1, %ymm0, %ymm0 ; X86-NEXT: vandps %ymm1, %ymm0, %ymm0
; X86-NEXT: vandps {{\.LCPI.*}}, %ymm0, %ymm0 ; X86-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
pengfeiUnsubmitted
Not Done
ReplyInline Actions

Nit: Should this be simplified to [0-9_]+?

pengfei: Nit: Should this be simplified to [0-9_]+?
craig.topperAuthorUnsubmitted
Done
ReplyInline Actions

We could but I thought it was best to keep it in sync with the scrub regex

SCRUB_X86_LCP_RE = re.compile(r'\.LCPI[0-9]+_[0-9]+')
craig.topper: We could but I thought it was best to keep it in sync with the scrub regex ```…
pengfeiUnsubmitted
Not Done
ReplyInline Actions

Agreed.

pengfei: Agreed.
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: test: ; X64-LABEL: test:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vaddps %ymm1, %ymm0, %ymm2 ; X64-NEXT: vaddps %ymm1, %ymm0, %ymm2
; X64-NEXT: vmulps %ymm0, %ymm1, %ymm1 ; X64-NEXT: vmulps %ymm0, %ymm1, %ymm1
; X64-NEXT: vsubps %ymm2, %ymm1, %ymm3 ; X64-NEXT: vsubps %ymm2, %ymm1, %ymm3
; X64-NEXT: vcmpltps %ymm1, %ymm0, %ymm0 ; X64-NEXT: vcmpltps %ymm1, %ymm0, %ymm0
Show All 15 Lines

llvm/test/CodeGen/X86/addsub-constant-folding.ll

Show First 20 Lines • Show All 58 Lines • ▼ Show 20 Lines; X64-NEXT: retq
call void @use(i32 %t0) call void @use(i32 %t0)
%t1 = add i32 %t0, 2 %t1 = add i32 %t0, 2
ret i32 %t1 ret i32 %t1
} }
define <4 x i32> @vec_add_const_add_const(<4 x i32> %arg) { define <4 x i32> @vec_add_const_add_const(<4 x i32> %arg) {
; X86-LABEL: vec_add_const_add_const: ; X86-LABEL: vec_add_const_add_const:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: paddd {{\.LCPI.*}}, %xmm0 ; X86-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: vec_add_const_add_const: ; X64-LABEL: vec_add_const_add_const:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: paddd {{.*}}(%rip), %xmm0 ; X64-NEXT: paddd {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8> %t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
%t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @vec_add_const_add_const_extrause(<4 x i32> %arg) { define <4 x i32> @vec_add_const_add_const_extrause(<4 x i32> %arg) {
; X86-LABEL: vec_add_const_add_const_extrause: ; X86-LABEL: vec_add_const_add_const_extrause:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: subl $28, %esp ; X86-NEXT: subl $28, %esp
; X86-NEXT: .cfi_def_cfa_offset 32 ; X86-NEXT: .cfi_def_cfa_offset 32
; X86-NEXT: movdqa %xmm0, %xmm1 ; X86-NEXT: movdqa %xmm0, %xmm1
; X86-NEXT: movdqu %xmm0, (%esp) # 16-byte Spill ; X86-NEXT: movdqu %xmm0, (%esp) # 16-byte Spill
; X86-NEXT: movdqa {{.*#+}} xmm0 = [8,8,8,8] ; X86-NEXT: movdqa {{.*#+}} xmm0 = [8,8,8,8]
; X86-NEXT: paddd %xmm1, %xmm0 ; X86-NEXT: paddd %xmm1, %xmm0
; X86-NEXT: calll vec_use@PLT ; X86-NEXT: calll vec_use@PLT
; X86-NEXT: movdqu (%esp), %xmm0 # 16-byte Reload ; X86-NEXT: movdqu (%esp), %xmm0 # 16-byte Reload
; X86-NEXT: paddd {{\.LCPI.*}}, %xmm0 ; X86-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: addl $28, %esp ; X86-NEXT: addl $28, %esp
; X86-NEXT: .cfi_def_cfa_offset 4 ; X86-NEXT: .cfi_def_cfa_offset 4
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: vec_add_const_add_const_extrause: ; X64-LABEL: vec_add_const_add_const_extrause:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: subq $24, %rsp ; X64-NEXT: subq $24, %rsp
; X64-NEXT: .cfi_def_cfa_offset 32 ; X64-NEXT: .cfi_def_cfa_offset 32
Show All 11 Lines; X64-NEXT: retq
call void @vec_use(<4 x i32> %t0) call void @vec_use(<4 x i32> %t0)
%t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @vec_add_const_add_const_nonsplat(<4 x i32> %arg) { define <4 x i32> @vec_add_const_add_const_nonsplat(<4 x i32> %arg) {
; X86-LABEL: vec_add_const_add_const_nonsplat: ; X86-LABEL: vec_add_const_add_const_nonsplat:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: paddd {{\.LCPI.*}}, %xmm0 ; X86-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: vec_add_const_add_const_nonsplat: ; X64-LABEL: vec_add_const_add_const_nonsplat:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: paddd {{.*}}(%rip), %xmm0 ; X64-NEXT: paddd {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%t0 = add <4 x i32> %arg, <i32 21, i32 undef, i32 8, i32 8> %t0 = add <4 x i32> %arg, <i32 21, i32 undef, i32 8, i32 8>
%t1 = add <4 x i32> %t0, <i32 2, i32 3, i32 undef, i32 2> %t1 = add <4 x i32> %t0, <i32 2, i32 3, i32 undef, i32 2>
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines; X64-NEXT: retq
call void @use(i32 %t0) call void @use(i32 %t0)
%t1 = sub i32 %t0, 2 %t1 = sub i32 %t0, 2
ret i32 %t1 ret i32 %t1
} }
define <4 x i32> @vec_add_const_sub_const(<4 x i32> %arg) { define <4 x i32> @vec_add_const_sub_const(<4 x i32> %arg) {
; X86-LABEL: vec_add_const_sub_const: ; X86-LABEL: vec_add_const_sub_const:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: paddd {{\.LCPI.*}}, %xmm0 ; X86-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: vec_add_const_sub_const: ; X64-LABEL: vec_add_const_sub_const:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: paddd {{.*}}(%rip), %xmm0 ; X64-NEXT: paddd {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8> %t0 = add <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
%t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @vec_add_const_sub_const_extrause(<4 x i32> %arg) { define <4 x i32> @vec_add_const_sub_const_extrause(<4 x i32> %arg) {
; X86-LABEL: vec_add_const_sub_const_extrause: ; X86-LABEL: vec_add_const_sub_const_extrause:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: subl $28, %esp ; X86-NEXT: subl $28, %esp
; X86-NEXT: .cfi_def_cfa_offset 32 ; X86-NEXT: .cfi_def_cfa_offset 32
; X86-NEXT: movdqa %xmm0, %xmm1 ; X86-NEXT: movdqa %xmm0, %xmm1
; X86-NEXT: movdqu %xmm0, (%esp) # 16-byte Spill ; X86-NEXT: movdqu %xmm0, (%esp) # 16-byte Spill
; X86-NEXT: movdqa {{.*#+}} xmm0 = [8,8,8,8] ; X86-NEXT: movdqa {{.*#+}} xmm0 = [8,8,8,8]
; X86-NEXT: paddd %xmm1, %xmm0 ; X86-NEXT: paddd %xmm1, %xmm0
; X86-NEXT: calll vec_use@PLT ; X86-NEXT: calll vec_use@PLT
; X86-NEXT: movdqu (%esp), %xmm0 # 16-byte Reload ; X86-NEXT: movdqu (%esp), %xmm0 # 16-byte Reload
; X86-NEXT: paddd {{\.LCPI.*}}, %xmm0 ; X86-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: addl $28, %esp ; X86-NEXT: addl $28, %esp
; X86-NEXT: .cfi_def_cfa_offset 4 ; X86-NEXT: .cfi_def_cfa_offset 4
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: vec_add_const_sub_const_extrause: ; X64-LABEL: vec_add_const_sub_const_extrause:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: subq $24, %rsp ; X64-NEXT: subq $24, %rsp
; X64-NEXT: .cfi_def_cfa_offset 32 ; X64-NEXT: .cfi_def_cfa_offset 32
Show All 11 Lines; X64-NEXT: retq
call void @vec_use(<4 x i32> %t0) call void @vec_use(<4 x i32> %t0)
%t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @vec_add_const_sub_const_nonsplat(<4 x i32> %arg) { define <4 x i32> @vec_add_const_sub_const_nonsplat(<4 x i32> %arg) {
; X86-LABEL: vec_add_const_sub_const_nonsplat: ; X86-LABEL: vec_add_const_sub_const_nonsplat:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: paddd {{\.LCPI.*}}, %xmm0 ; X86-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: vec_add_const_sub_const_nonsplat: ; X64-LABEL: vec_add_const_sub_const_nonsplat:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: paddd {{.*}}(%rip), %xmm0 ; X64-NEXT: paddd {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%t0 = add <4 x i32> %arg, <i32 21, i32 undef, i32 8, i32 8> %t0 = add <4 x i32> %arg, <i32 21, i32 undef, i32 8, i32 8>
%t1 = sub <4 x i32> %t0, <i32 2, i32 3, i32 undef, i32 2> %t1 = sub <4 x i32> %t0, <i32 2, i32 3, i32 undef, i32 2>
▲ Show 20 Lines • Show All 186 Lines • ▼ Show 20 Lines; X64-NEXT: retq
call void @use(i32 %t0) call void @use(i32 %t0)
%t1 = add i32 %t0, 2 %t1 = add i32 %t0, 2
ret i32 %t1 ret i32 %t1
} }
define <4 x i32> @vec_sub_const_add_const(<4 x i32> %arg) { define <4 x i32> @vec_sub_const_add_const(<4 x i32> %arg) {
; X86-LABEL: vec_sub_const_add_const: ; X86-LABEL: vec_sub_const_add_const:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: paddd {{\.LCPI.*}}, %xmm0 ; X86-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: vec_sub_const_add_const: ; X64-LABEL: vec_sub_const_add_const:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: paddd {{.*}}(%rip), %xmm0 ; X64-NEXT: paddd {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%t0 = sub <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8> %t0 = sub <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
%t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @vec_sub_const_add_const_extrause(<4 x i32> %arg) { define <4 x i32> @vec_sub_const_add_const_extrause(<4 x i32> %arg) {
; X86-LABEL: vec_sub_const_add_const_extrause: ; X86-LABEL: vec_sub_const_add_const_extrause:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: subl $28, %esp ; X86-NEXT: subl $28, %esp
; X86-NEXT: .cfi_def_cfa_offset 32 ; X86-NEXT: .cfi_def_cfa_offset 32
; X86-NEXT: movdqu %xmm0, (%esp) # 16-byte Spill ; X86-NEXT: movdqu %xmm0, (%esp) # 16-byte Spill
; X86-NEXT: psubd {{\.LCPI.*}}, %xmm0 ; X86-NEXT: psubd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: calll vec_use@PLT ; X86-NEXT: calll vec_use@PLT
; X86-NEXT: movdqu (%esp), %xmm0 # 16-byte Reload ; X86-NEXT: movdqu (%esp), %xmm0 # 16-byte Reload
; X86-NEXT: paddd {{\.LCPI.*}}, %xmm0 ; X86-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: addl $28, %esp ; X86-NEXT: addl $28, %esp
; X86-NEXT: .cfi_def_cfa_offset 4 ; X86-NEXT: .cfi_def_cfa_offset 4
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: vec_sub_const_add_const_extrause: ; X64-LABEL: vec_sub_const_add_const_extrause:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: subq $24, %rsp ; X64-NEXT: subq $24, %rsp
; X64-NEXT: .cfi_def_cfa_offset 32 ; X64-NEXT: .cfi_def_cfa_offset 32
Show All 9 Lines; X64-NEXT: retq
call void @vec_use(<4 x i32> %t0) call void @vec_use(<4 x i32> %t0)
%t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = add <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @vec_sub_const_add_const_nonsplat(<4 x i32> %arg) { define <4 x i32> @vec_sub_const_add_const_nonsplat(<4 x i32> %arg) {
; X86-LABEL: vec_sub_const_add_const_nonsplat: ; X86-LABEL: vec_sub_const_add_const_nonsplat:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: paddd {{\.LCPI.*}}, %xmm0 ; X86-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: vec_sub_const_add_const_nonsplat: ; X64-LABEL: vec_sub_const_add_const_nonsplat:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: paddd {{.*}}(%rip), %xmm0 ; X64-NEXT: paddd {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%t0 = sub <4 x i32> %arg, <i32 21, i32 undef, i32 8, i32 8> %t0 = sub <4 x i32> %arg, <i32 21, i32 undef, i32 8, i32 8>
%t1 = add <4 x i32> %t0, <i32 2, i32 3, i32 undef, i32 2> %t1 = add <4 x i32> %t0, <i32 2, i32 3, i32 undef, i32 2>
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines; X64-NEXT: retq
call void @use(i32 %t0) call void @use(i32 %t0)
%t1 = sub i32 %t0, 2 %t1 = sub i32 %t0, 2
ret i32 %t1 ret i32 %t1
} }
define <4 x i32> @vec_sub_const_sub_const(<4 x i32> %arg) { define <4 x i32> @vec_sub_const_sub_const(<4 x i32> %arg) {
; X86-LABEL: vec_sub_const_sub_const: ; X86-LABEL: vec_sub_const_sub_const:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: psubd {{\.LCPI.*}}, %xmm0 ; X86-NEXT: psubd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: vec_sub_const_sub_const: ; X64-LABEL: vec_sub_const_sub_const:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: psubd {{.*}}(%rip), %xmm0 ; X64-NEXT: psubd {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%t0 = sub <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8> %t0 = sub <4 x i32> %arg, <i32 8, i32 8, i32 8, i32 8>
%t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @vec_sub_const_sub_const_extrause(<4 x i32> %arg) { define <4 x i32> @vec_sub_const_sub_const_extrause(<4 x i32> %arg) {
; X86-LABEL: vec_sub_const_sub_const_extrause: ; X86-LABEL: vec_sub_const_sub_const_extrause:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: subl $28, %esp ; X86-NEXT: subl $28, %esp
; X86-NEXT: .cfi_def_cfa_offset 32 ; X86-NEXT: .cfi_def_cfa_offset 32
; X86-NEXT: movdqu %xmm0, (%esp) # 16-byte Spill ; X86-NEXT: movdqu %xmm0, (%esp) # 16-byte Spill
; X86-NEXT: psubd {{\.LCPI.*}}, %xmm0 ; X86-NEXT: psubd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: calll vec_use@PLT ; X86-NEXT: calll vec_use@PLT
; X86-NEXT: movdqu (%esp), %xmm0 # 16-byte Reload ; X86-NEXT: movdqu (%esp), %xmm0 # 16-byte Reload
; X86-NEXT: psubd {{\.LCPI.*}}, %xmm0 ; X86-NEXT: psubd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: addl $28, %esp ; X86-NEXT: addl $28, %esp
; X86-NEXT: .cfi_def_cfa_offset 4 ; X86-NEXT: .cfi_def_cfa_offset 4
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: vec_sub_const_sub_const_extrause: ; X64-LABEL: vec_sub_const_sub_const_extrause:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: subq $24, %rsp ; X64-NEXT: subq $24, %rsp
; X64-NEXT: .cfi_def_cfa_offset 32 ; X64-NEXT: .cfi_def_cfa_offset 32
Show All 9 Lines; X64-NEXT: retq
call void @vec_use(<4 x i32> %t0) call void @vec_use(<4 x i32> %t0)
%t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2> %t1 = sub <4 x i32> %t0, <i32 2, i32 2, i32 2, i32 2>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @vec_sub_const_sub_const_nonsplat(<4 x i32> %arg) { define <4 x i32> @vec_sub_const_sub_const_nonsplat(<4 x i32> %arg) {
; X86-LABEL: vec_sub_const_sub_const_nonsplat: ; X86-LABEL: vec_sub_const_sub_const_nonsplat:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: psubd {{\.LCPI.*}}, %xmm0 ; X86-NEXT: psubd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: vec_sub_const_sub_const_nonsplat: ; X64-LABEL: vec_sub_const_sub_const_nonsplat:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: psubd {{.*}}(%rip), %xmm0 ; X64-NEXT: psubd {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%t0 = sub <4 x i32> %arg, <i32 21, i32 undef, i32 8, i32 8> %t0 = sub <4 x i32> %arg, <i32 21, i32 undef, i32 8, i32 8>
%t1 = sub <4 x i32> %t0, <i32 2, i32 3, i32 undef, i32 2> %t1 = sub <4 x i32> %t0, <i32 2, i32 3, i32 undef, i32 2>
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Lines; X64-NEXT: retq
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @vec_sub_const_const_sub_extrause(<4 x i32> %arg) { define <4 x i32> @vec_sub_const_const_sub_extrause(<4 x i32> %arg) {
; X86-LABEL: vec_sub_const_const_sub_extrause: ; X86-LABEL: vec_sub_const_const_sub_extrause:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: subl $28, %esp ; X86-NEXT: subl $28, %esp
; X86-NEXT: .cfi_def_cfa_offset 32 ; X86-NEXT: .cfi_def_cfa_offset 32
; X86-NEXT: psubd {{\.LCPI.*}}, %xmm0 ; X86-NEXT: psubd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: movdqu %xmm0, (%esp) # 16-byte Spill ; X86-NEXT: movdqu %xmm0, (%esp) # 16-byte Spill
; X86-NEXT: calll vec_use@PLT ; X86-NEXT: calll vec_use@PLT
; X86-NEXT: movdqa {{.*#+}} xmm0 = [2,2,2,2] ; X86-NEXT: movdqa {{.*#+}} xmm0 = [2,2,2,2]
; X86-NEXT: movdqu (%esp), %xmm1 # 16-byte Reload ; X86-NEXT: movdqu (%esp), %xmm1 # 16-byte Reload
; X86-NEXT: psubd %xmm1, %xmm0 ; X86-NEXT: psubd %xmm1, %xmm0
; X86-NEXT: addl $28, %esp ; X86-NEXT: addl $28, %esp
; X86-NEXT: .cfi_def_cfa_offset 4 ; X86-NEXT: .cfi_def_cfa_offset 4
; X86-NEXT: retl ; X86-NEXT: retl
▲ Show 20 Lines • Show All 359 Lines • ▼ Show 20 Lines; X64-NEXT: retq
call void @use(i32 %t0) call void @use(i32 %t0)
%t1 = sub i32 2, %t0 %t1 = sub i32 2, %t0
ret i32 %t1 ret i32 %t1
} }
define <4 x i32> @vec_const_sub_const_sub(<4 x i32> %arg) { define <4 x i32> @vec_const_sub_const_sub(<4 x i32> %arg) {
; X86-LABEL: vec_const_sub_const_sub: ; X86-LABEL: vec_const_sub_const_sub:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: paddd {{\.LCPI.*}}, %xmm0 ; X86-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: vec_const_sub_const_sub: ; X64-LABEL: vec_const_sub_const_sub:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: paddd {{.*}}(%rip), %xmm0 ; X64-NEXT: paddd {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%t0 = sub <4 x i32> <i32 8, i32 8, i32 8, i32 8>, %arg %t0 = sub <4 x i32> <i32 8, i32 8, i32 8, i32 8>, %arg
%t1 = sub <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %t0 %t1 = sub <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %t0
Show All 35 Lines; X64-NEXT: retq
call void @vec_use(<4 x i32> %t0) call void @vec_use(<4 x i32> %t0)
%t1 = sub <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %t0 %t1 = sub <4 x i32> <i32 2, i32 2, i32 2, i32 2>, %t0
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @vec_const_sub_const_sub_nonsplat(<4 x i32> %arg) { define <4 x i32> @vec_const_sub_const_sub_nonsplat(<4 x i32> %arg) {
; X86-LABEL: vec_const_sub_const_sub_nonsplat: ; X86-LABEL: vec_const_sub_const_sub_nonsplat:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: paddd {{\.LCPI.*}}, %xmm0 ; X86-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: vec_const_sub_const_sub_nonsplat: ; X64-LABEL: vec_const_sub_const_sub_nonsplat:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: paddd {{.*}}(%rip), %xmm0 ; X64-NEXT: paddd {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%t0 = sub <4 x i32> <i32 21, i32 undef, i32 8, i32 8>, %arg %t0 = sub <4 x i32> <i32 21, i32 undef, i32 8, i32 8>, %arg
%t1 = sub <4 x i32> <i32 2, i32 3, i32 undef, i32 2>, %t0 %t1 = sub <4 x i32> <i32 2, i32 3, i32 undef, i32 2>, %t0
ret <4 x i32> %t1 ret <4 x i32> %t1
} }

llvm/test/CodeGen/X86/atomic-fp.ll

Show First 20 Lines • Show All 194 Lines • ▼ Show 20 Lines
; X86-NOSSE-NEXT: retl ; X86-NOSSE-NEXT: retl
; ;
; X86-SSE1-LABEL: fadd_32g: ; X86-SSE1-LABEL: fadd_32g:
; X86-SSE1: # %bb.0: ; X86-SSE1: # %bb.0:
; X86-SSE1-NEXT: subl $8, %esp ; X86-SSE1-NEXT: subl $8, %esp
; X86-SSE1-NEXT: movl glob32, %eax ; X86-SSE1-NEXT: movl glob32, %eax
; X86-SSE1-NEXT: movl %eax, (%esp) ; X86-SSE1-NEXT: movl %eax, (%esp)
; X86-SSE1-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-SSE1-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE1-NEXT: addss {{\.LCPI.*}}, %xmm0 ; X86-SSE1-NEXT: addss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE1-NEXT: movss %xmm0, {{[0-9]+}}(%esp) ; X86-SSE1-NEXT: movss %xmm0, {{[0-9]+}}(%esp)
; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE1-NEXT: movl %eax, glob32 ; X86-SSE1-NEXT: movl %eax, glob32
; X86-SSE1-NEXT: addl $8, %esp ; X86-SSE1-NEXT: addl $8, %esp
; X86-SSE1-NEXT: retl ; X86-SSE1-NEXT: retl
; ;
; X86-SSE2-LABEL: fadd_32g: ; X86-SSE2-LABEL: fadd_32g:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
; ;
; X86-SSE2-LABEL: fadd_64g: ; X86-SSE2-LABEL: fadd_64g:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pushl %ebp ; X86-SSE2-NEXT: pushl %ebp
; X86-SSE2-NEXT: movl %esp, %ebp ; X86-SSE2-NEXT: movl %esp, %ebp
; X86-SSE2-NEXT: andl $-8, %esp ; X86-SSE2-NEXT: andl $-8, %esp
; X86-SSE2-NEXT: subl $8, %esp ; X86-SSE2-NEXT: subl $8, %esp
; X86-SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; X86-SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE2-NEXT: addsd {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: addsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: movsd %xmm0, (%esp) ; X86-SSE2-NEXT: movsd %xmm0, (%esp)
; X86-SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; X86-SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE2-NEXT: movlps %xmm0, glob64 ; X86-SSE2-NEXT: movlps %xmm0, glob64
; X86-SSE2-NEXT: movl %ebp, %esp ; X86-SSE2-NEXT: movl %ebp, %esp
; X86-SSE2-NEXT: popl %ebp ; X86-SSE2-NEXT: popl %ebp
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: fadd_64g: ; X86-AVX-LABEL: fadd_64g:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: pushl %ebp ; X86-AVX-NEXT: pushl %ebp
; X86-AVX-NEXT: movl %esp, %ebp ; X86-AVX-NEXT: movl %esp, %ebp
; X86-AVX-NEXT: andl $-8, %esp ; X86-AVX-NEXT: andl $-8, %esp
; X86-AVX-NEXT: subl $8, %esp ; X86-AVX-NEXT: subl $8, %esp
; X86-AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; X86-AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; X86-AVX-NEXT: vaddsd {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vaddsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vmovsd %xmm0, (%esp) ; X86-AVX-NEXT: vmovsd %xmm0, (%esp)
; X86-AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; X86-AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; X86-AVX-NEXT: vmovlps %xmm0, glob64 ; X86-AVX-NEXT: vmovlps %xmm0, glob64
; X86-AVX-NEXT: movl %ebp, %esp ; X86-AVX-NEXT: movl %ebp, %esp
; X86-AVX-NEXT: popl %ebp ; X86-AVX-NEXT: popl %ebp
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE-LABEL: fadd_64g: ; X64-SSE-LABEL: fadd_64g:
Show All 33 Lines
; X86-NOSSE-NEXT: retl ; X86-NOSSE-NEXT: retl
; ;
; X86-SSE1-LABEL: fadd_32imm: ; X86-SSE1-LABEL: fadd_32imm:
; X86-SSE1: # %bb.0: ; X86-SSE1: # %bb.0:
; X86-SSE1-NEXT: subl $8, %esp ; X86-SSE1-NEXT: subl $8, %esp
; X86-SSE1-NEXT: movl -559038737, %eax ; X86-SSE1-NEXT: movl -559038737, %eax
; X86-SSE1-NEXT: movl %eax, (%esp) ; X86-SSE1-NEXT: movl %eax, (%esp)
; X86-SSE1-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-SSE1-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE1-NEXT: addss {{\.LCPI.*}}, %xmm0 ; X86-SSE1-NEXT: addss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE1-NEXT: movss %xmm0, {{[0-9]+}}(%esp) ; X86-SSE1-NEXT: movss %xmm0, {{[0-9]+}}(%esp)
; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE1-NEXT: movl %eax, -559038737 ; X86-SSE1-NEXT: movl %eax, -559038737
; X86-SSE1-NEXT: addl $8, %esp ; X86-SSE1-NEXT: addl $8, %esp
; X86-SSE1-NEXT: retl ; X86-SSE1-NEXT: retl
; ;
; X86-SSE2-LABEL: fadd_32imm: ; X86-SSE2-LABEL: fadd_32imm:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
▲ Show 20 Lines • Show All 81 Lines • ▼ Show 20 Lines
; ;
; X86-SSE2-LABEL: fadd_64imm: ; X86-SSE2-LABEL: fadd_64imm:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pushl %ebp ; X86-SSE2-NEXT: pushl %ebp
; X86-SSE2-NEXT: movl %esp, %ebp ; X86-SSE2-NEXT: movl %esp, %ebp
; X86-SSE2-NEXT: andl $-8, %esp ; X86-SSE2-NEXT: andl $-8, %esp
; X86-SSE2-NEXT: subl $8, %esp ; X86-SSE2-NEXT: subl $8, %esp
; X86-SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; X86-SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE2-NEXT: addsd {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: addsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: movsd %xmm0, (%esp) ; X86-SSE2-NEXT: movsd %xmm0, (%esp)
; X86-SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; X86-SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE2-NEXT: movlps %xmm0, -559038737 ; X86-SSE2-NEXT: movlps %xmm0, -559038737
; X86-SSE2-NEXT: movl %ebp, %esp ; X86-SSE2-NEXT: movl %ebp, %esp
; X86-SSE2-NEXT: popl %ebp ; X86-SSE2-NEXT: popl %ebp
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: fadd_64imm: ; X86-AVX-LABEL: fadd_64imm:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: pushl %ebp ; X86-AVX-NEXT: pushl %ebp
; X86-AVX-NEXT: movl %esp, %ebp ; X86-AVX-NEXT: movl %esp, %ebp
; X86-AVX-NEXT: andl $-8, %esp ; X86-AVX-NEXT: andl $-8, %esp
; X86-AVX-NEXT: subl $8, %esp ; X86-AVX-NEXT: subl $8, %esp
; X86-AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; X86-AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; X86-AVX-NEXT: vaddsd {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vaddsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vmovsd %xmm0, (%esp) ; X86-AVX-NEXT: vmovsd %xmm0, (%esp)
; X86-AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; X86-AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; X86-AVX-NEXT: vmovlps %xmm0, -559038737 ; X86-AVX-NEXT: vmovlps %xmm0, -559038737
; X86-AVX-NEXT: movl %ebp, %esp ; X86-AVX-NEXT: movl %ebp, %esp
; X86-AVX-NEXT: popl %ebp ; X86-AVX-NEXT: popl %ebp
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE-LABEL: fadd_64imm: ; X64-SSE-LABEL: fadd_64imm:
Show All 35 Lines
; X86-NOSSE-NEXT: retl ; X86-NOSSE-NEXT: retl
; ;
; X86-SSE1-LABEL: fadd_32stack: ; X86-SSE1-LABEL: fadd_32stack:
; X86-SSE1: # %bb.0: ; X86-SSE1: # %bb.0:
; X86-SSE1-NEXT: subl $12, %esp ; X86-SSE1-NEXT: subl $12, %esp
; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE1-NEXT: movl %eax, (%esp) ; X86-SSE1-NEXT: movl %eax, (%esp)
; X86-SSE1-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-SSE1-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE1-NEXT: addss {{\.LCPI.*}}, %xmm0 ; X86-SSE1-NEXT: addss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE1-NEXT: movss %xmm0, {{[0-9]+}}(%esp) ; X86-SSE1-NEXT: movss %xmm0, {{[0-9]+}}(%esp)
; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE1-NEXT: movl %eax, {{[0-9]+}}(%esp) ; X86-SSE1-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X86-SSE1-NEXT: addl $12, %esp ; X86-SSE1-NEXT: addl $12, %esp
; X86-SSE1-NEXT: retl ; X86-SSE1-NEXT: retl
; ;
; X86-SSE2-LABEL: fadd_32stack: ; X86-SSE2-LABEL: fadd_32stack:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
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; ;
; X86-SSE2-LABEL: fadd_64stack: ; X86-SSE2-LABEL: fadd_64stack:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pushl %ebp ; X86-SSE2-NEXT: pushl %ebp
; X86-SSE2-NEXT: movl %esp, %ebp ; X86-SSE2-NEXT: movl %esp, %ebp
; X86-SSE2-NEXT: andl $-8, %esp ; X86-SSE2-NEXT: andl $-8, %esp
; X86-SSE2-NEXT: subl $16, %esp ; X86-SSE2-NEXT: subl $16, %esp
; X86-SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; X86-SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE2-NEXT: addsd {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: addsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: movsd %xmm0, (%esp) ; X86-SSE2-NEXT: movsd %xmm0, (%esp)
; X86-SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; X86-SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE2-NEXT: movlps %xmm0, {{[0-9]+}}(%esp) ; X86-SSE2-NEXT: movlps %xmm0, {{[0-9]+}}(%esp)
; X86-SSE2-NEXT: movl %ebp, %esp ; X86-SSE2-NEXT: movl %ebp, %esp
; X86-SSE2-NEXT: popl %ebp ; X86-SSE2-NEXT: popl %ebp
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: fadd_64stack: ; X86-AVX-LABEL: fadd_64stack:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: pushl %ebp ; X86-AVX-NEXT: pushl %ebp
; X86-AVX-NEXT: movl %esp, %ebp ; X86-AVX-NEXT: movl %esp, %ebp
; X86-AVX-NEXT: andl $-8, %esp ; X86-AVX-NEXT: andl $-8, %esp
; X86-AVX-NEXT: subl $16, %esp ; X86-AVX-NEXT: subl $16, %esp
; X86-AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; X86-AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; X86-AVX-NEXT: vaddsd {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vaddsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vmovsd %xmm0, (%esp) ; X86-AVX-NEXT: vmovsd %xmm0, (%esp)
; X86-AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; X86-AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; X86-AVX-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp) ; X86-AVX-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)
; X86-AVX-NEXT: movl %ebp, %esp ; X86-AVX-NEXT: movl %ebp, %esp
; X86-AVX-NEXT: popl %ebp ; X86-AVX-NEXT: popl %ebp
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE-LABEL: fadd_64stack: ; X64-SSE-LABEL: fadd_64stack:
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llvm/test/CodeGen/X86/avx-cmp.ll

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; CHECK-NEXT: # %bb.3: # %for.cond5 ; CHECK-NEXT: # %bb.3: # %for.cond5
; CHECK-NEXT: # in Loop: Header=BB2_2 Depth=1 ; CHECK-NEXT: # in Loop: Header=BB2_2 Depth=1
; CHECK-NEXT: testb %bpl, %bpl ; CHECK-NEXT: testb %bpl, %bpl
; CHECK-NEXT: jne .LBB2_2 ; CHECK-NEXT: jne .LBB2_2
; CHECK-NEXT: # %bb.4: # %for.body33.preheader ; CHECK-NEXT: # %bb.4: # %for.body33.preheader
; CHECK-NEXT: # in Loop: Header=BB2_2 Depth=1 ; CHECK-NEXT: # in Loop: Header=BB2_2 Depth=1
; CHECK-NEXT: vmovsd (%rsp), %xmm0 # 8-byte Reload ; CHECK-NEXT: vmovsd (%rsp), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero ; CHECK-NEXT: # xmm0 = mem[0],zero
; CHECK-NEXT: vucomisd {{\.LCPI.*}}, %xmm0 ; CHECK-NEXT: vucomisd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; CHECK-NEXT: jne .LBB2_5 ; CHECK-NEXT: jne .LBB2_5
; CHECK-NEXT: jnp .LBB2_2 ; CHECK-NEXT: jnp .LBB2_2
; CHECK-NEXT: .LBB2_5: # %if.then ; CHECK-NEXT: .LBB2_5: # %if.then
; CHECK-NEXT: # in Loop: Header=BB2_2 Depth=1 ; CHECK-NEXT: # in Loop: Header=BB2_2 Depth=1
; CHECK-NEXT: callq scale@PLT ; CHECK-NEXT: callq scale@PLT
; CHECK-NEXT: jmp .LBB2_2 ; CHECK-NEXT: jmp .LBB2_2
; CHECK-NEXT: .LBB2_6: # %for.end52 ; CHECK-NEXT: .LBB2_6: # %for.end52
; CHECK-NEXT: addq $8, %rsp ; CHECK-NEXT: addq $8, %rsp
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llvm/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll

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define void @test_x86_sse2_storeu_pd(i8* %a0, <2 x double> %a1) { define void @test_x86_sse2_storeu_pd(i8* %a0, <2 x double> %a1) {
; fadd operation forces the execution domain. ; fadd operation forces the execution domain.
; X86-AVX-LABEL: test_x86_sse2_storeu_pd: ; X86-AVX-LABEL: test_x86_sse2_storeu_pd:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04] ; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
; X86-AVX-NEXT: vxorpd %xmm1, %xmm1, %xmm1 # encoding: [0xc5,0xf1,0x57,0xc9] ; X86-AVX-NEXT: vxorpd %xmm1, %xmm1, %xmm1 # encoding: [0xc5,0xf1,0x57,0xc9]
; X86-AVX-NEXT: vmovhpd {{\.LCPI.*}}, %xmm1, %xmm1 # encoding: [0xc5,0xf1,0x16,0x0d,A,A,A,A] ; X86-AVX-NEXT: vmovhpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1 # encoding: [0xc5,0xf1,0x16,0x0d,A,A,A,A]
; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: # xmm1 = xmm1[0],mem[0] ; X86-AVX-NEXT: # xmm1 = xmm1[0],mem[0]
; X86-AVX-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf9,0x58,0xc1] ; X86-AVX-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf9,0x58,0xc1]
; X86-AVX-NEXT: vmovupd %xmm0, (%eax) # encoding: [0xc5,0xf9,0x11,0x00] ; X86-AVX-NEXT: vmovupd %xmm0, (%eax) # encoding: [0xc5,0xf9,0x11,0x00]
; X86-AVX-NEXT: retl # encoding: [0xc3] ; X86-AVX-NEXT: retl # encoding: [0xc3]
; ;
; X86-AVX512VL-LABEL: test_x86_sse2_storeu_pd: ; X86-AVX512VL-LABEL: test_x86_sse2_storeu_pd:
; X86-AVX512VL: # %bb.0: ; X86-AVX512VL: # %bb.0:
; X86-AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04] ; X86-AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
; X86-AVX512VL-NEXT: vxorpd %xmm1, %xmm1, %xmm1 # EVEX TO VEX Compression encoding: [0xc5,0xf1,0x57,0xc9] ; X86-AVX512VL-NEXT: vxorpd %xmm1, %xmm1, %xmm1 # EVEX TO VEX Compression encoding: [0xc5,0xf1,0x57,0xc9]
; X86-AVX512VL-NEXT: vmovhpd {{\.LCPI.*}}, %xmm1, %xmm1 # EVEX TO VEX Compression encoding: [0xc5,0xf1,0x16,0x0d,A,A,A,A] ; X86-AVX512VL-NEXT: vmovhpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1 # EVEX TO VEX Compression encoding: [0xc5,0xf1,0x16,0x0d,A,A,A,A]
; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: # xmm1 = xmm1[0],mem[0] ; X86-AVX512VL-NEXT: # xmm1 = xmm1[0],mem[0]
; X86-AVX512VL-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x58,0xc1] ; X86-AVX512VL-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x58,0xc1]
; X86-AVX512VL-NEXT: vmovupd %xmm0, (%eax) # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x11,0x00] ; X86-AVX512VL-NEXT: vmovupd %xmm0, (%eax) # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x11,0x00]
; X86-AVX512VL-NEXT: retl # encoding: [0xc3] ; X86-AVX512VL-NEXT: retl # encoding: [0xc3]
; ;
; X64-AVX-LABEL: test_x86_sse2_storeu_pd: ; X64-AVX-LABEL: test_x86_sse2_storeu_pd:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vxorpd %xmm1, %xmm1, %xmm1 # encoding: [0xc5,0xf1,0x57,0xc9] ; X64-AVX-NEXT: vxorpd %xmm1, %xmm1, %xmm1 # encoding: [0xc5,0xf1,0x57,0xc9]
; X64-AVX-NEXT: vmovhpd {{.*}}(%rip), %xmm1, %xmm1 # encoding: [0xc5,0xf1,0x16,0x0d,A,A,A,A] ; X64-AVX-NEXT: vmovhpd {{.*}}(%rip), %xmm1, %xmm1 # encoding: [0xc5,0xf1,0x16,0x0d,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: # xmm1 = xmm1[0],mem[0] ; X64-AVX-NEXT: # xmm1 = xmm1[0],mem[0]
; X64-AVX-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf9,0x58,0xc1] ; X64-AVX-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf9,0x58,0xc1]
; X64-AVX-NEXT: vmovupd %xmm0, (%rdi) # encoding: [0xc5,0xf9,0x11,0x07] ; X64-AVX-NEXT: vmovupd %xmm0, (%rdi) # encoding: [0xc5,0xf9,0x11,0x07]
; X64-AVX-NEXT: retq # encoding: [0xc3] ; X64-AVX-NEXT: retq # encoding: [0xc3]
; ;
; X64-AVX512VL-LABEL: test_x86_sse2_storeu_pd: ; X64-AVX512VL-LABEL: test_x86_sse2_storeu_pd:
; X64-AVX512VL: # %bb.0: ; X64-AVX512VL: # %bb.0:
; X64-AVX512VL-NEXT: vxorpd %xmm1, %xmm1, %xmm1 # EVEX TO VEX Compression encoding: [0xc5,0xf1,0x57,0xc9] ; X64-AVX512VL-NEXT: vxorpd %xmm1, %xmm1, %xmm1 # EVEX TO VEX Compression encoding: [0xc5,0xf1,0x57,0xc9]
; X64-AVX512VL-NEXT: vmovhpd {{.*}}(%rip), %xmm1, %xmm1 # EVEX TO VEX Compression encoding: [0xc5,0xf1,0x16,0x0d,A,A,A,A] ; X64-AVX512VL-NEXT: vmovhpd {{.*}}(%rip), %xmm1, %xmm1 # EVEX TO VEX Compression encoding: [0xc5,0xf1,0x16,0x0d,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: # xmm1 = xmm1[0],mem[0] ; X64-AVX512VL-NEXT: # xmm1 = xmm1[0],mem[0]
; X64-AVX512VL-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x58,0xc1] ; X64-AVX512VL-NEXT: vaddpd %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x58,0xc1]
; X64-AVX512VL-NEXT: vmovupd %xmm0, (%rdi) # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x11,0x07] ; X64-AVX512VL-NEXT: vmovupd %xmm0, (%rdi) # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x11,0x07]
; X64-AVX512VL-NEXT: retq # encoding: [0xc3] ; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
%a2 = fadd <2 x double> %a1, <double 0x0, double 0x4200000000000000> %a2 = fadd <2 x double> %a1, <double 0x0, double 0x4200000000000000>
call void @llvm.x86.sse2.storeu.pd(i8* %a0, <2 x double> %a2) call void @llvm.x86.sse2.storeu.pd(i8* %a0, <2 x double> %a2)
ret void ret void
} }
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llvm/test/CodeGen/X86/avx2-arith.ll

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} }
define <16 x i8> @mul_v16i8(<16 x i8> %i, <16 x i8> %j) nounwind readnone { define <16 x i8> @mul_v16i8(<16 x i8> %i, <16 x i8> %j) nounwind readnone {
; X32-LABEL: mul_v16i8: ; X32-LABEL: mul_v16i8:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero ; X32-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
; X32-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero ; X32-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
; X32-NEXT: vpmullw %ymm1, %ymm0, %ymm0 ; X32-NEXT: vpmullw %ymm1, %ymm0, %ymm0
; X32-NEXT: vpand {{\.LCPI.*}}, %ymm0, %ymm0 ; X32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: vextracti128 $1, %ymm0, %xmm1 ; X32-NEXT: vextracti128 $1, %ymm0, %xmm1
; X32-NEXT: vpackuswb %xmm1, %xmm0, %xmm0 ; X32-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; X32-NEXT: vzeroupper ; X32-NEXT: vzeroupper
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: mul_v16i8: ; X64-LABEL: mul_v16i8:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero ; X64-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
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; X64-NEXT: retq ; X64-NEXT: retq
%y = mul <8 x i32> %x, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> %y = mul <8 x i32> %x, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
ret <8 x i32> %y ret <8 x i32> %y
} }
define <8 x i32> @mul_const6(<8 x i32> %x) { define <8 x i32> @mul_const6(<8 x i32> %x) {
; X32-LABEL: mul_const6: ; X32-LABEL: mul_const6:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: vpmulld {{\.LCPI.*}}, %ymm0, %ymm0 ; X32-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: mul_const6: ; X64-LABEL: mul_const6:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpmulld {{.*}}(%rip), %ymm0, %ymm0 ; X64-NEXT: vpmulld {{.*}}(%rip), %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%y = mul <8 x i32> %x, <i32 0, i32 0, i32 0, i32 2, i32 0, i32 2, i32 0, i32 0> %y = mul <8 x i32> %x, <i32 0, i32 0, i32 0, i32 2, i32 0, i32 2, i32 0, i32 0>
ret <8 x i32> %y ret <8 x i32> %y
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llvm/test/CodeGen/X86/avx2-conversions.ll

Show First 20 Lines • Show All 153 Lines • ▼ Show 20 Lines
; X64-NEXT: retq ; X64-NEXT: retq
%t = sext <16 x i8> %z to <16 x i16> %t = sext <16 x i8> %z to <16 x i16>
ret <16 x i16> %t ret <16 x i16> %t
} }
define <16 x i8> @trunc_16i16_16i8(<16 x i16> %z) { define <16 x i8> @trunc_16i16_16i8(<16 x i16> %z) {
; X32-LABEL: trunc_16i16_16i8: ; X32-LABEL: trunc_16i16_16i8:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: vpand {{\.LCPI.*}}, %ymm0, %ymm0 ; X32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: vextracti128 $1, %ymm0, %xmm1 ; X32-NEXT: vextracti128 $1, %ymm0, %xmm1
; X32-NEXT: vpackuswb %xmm1, %xmm0, %xmm0 ; X32-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
; X32-NEXT: vzeroupper ; X32-NEXT: vzeroupper
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: trunc_16i16_16i8: ; X64-LABEL: trunc_16i16_16i8:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0 ; X64-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
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llvm/test/CodeGen/X86/avx2-intrinsics-x86.ll

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declare <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32>, <8 x i32>) nounwind readnone declare <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32>, <8 x i32>) nounwind readnone
define <16 x i16> @test_x86_avx2_packssdw_fold() { define <16 x i16> @test_x86_avx2_packssdw_fold() {
; X86-AVX-LABEL: test_x86_avx2_packssdw_fold: ; X86-AVX-LABEL: test_x86_avx2_packssdw_fold:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,0,255,32767,32767,65535,0,0,0,0,32769,32768,0,65280] ; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,0,255,32767,32767,65535,0,0,0,0,32769,32768,0,65280]
; X86-AVX-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A] ; X86-AVX-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: retl # encoding: [0xc3] ; X86-AVX-NEXT: retl # encoding: [0xc3]
; ;
; X86-AVX512VL-LABEL: test_x86_avx2_packssdw_fold: ; X86-AVX512VL-LABEL: test_x86_avx2_packssdw_fold:
; X86-AVX512VL: # %bb.0: ; X86-AVX512VL: # %bb.0:
; X86-AVX512VL-NEXT: vmovaps {{\.LCPI.*}}, %ymm0 # EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,32767,65535,0,0,0,0,32769,32768,0,65280] ; X86-AVX512VL-NEXT: vmovaps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,32767,65535,0,0,0,0,32769,32768,0,65280]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A] ; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: retl # encoding: [0xc3] ; X86-AVX512VL-NEXT: retl # encoding: [0xc3]
; ;
; X64-AVX-LABEL: test_x86_avx2_packssdw_fold: ; X64-AVX-LABEL: test_x86_avx2_packssdw_fold:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,0,255,32767,32767,65535,0,0,0,0,32769,32768,0,65280] ; X64-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,0,255,32767,32767,65535,0,0,0,0,32769,32768,0,65280]
; X64-AVX-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A] ; X64-AVX-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: retq # encoding: [0xc3] ; X64-AVX-NEXT: retq # encoding: [0xc3]
; ;
; X64-AVX512VL-LABEL: test_x86_avx2_packssdw_fold: ; X64-AVX512VL-LABEL: test_x86_avx2_packssdw_fold:
; X64-AVX512VL: # %bb.0: ; X64-AVX512VL: # %bb.0:
; X64-AVX512VL-NEXT: vmovaps {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,32767,65535,0,0,0,0,32769,32768,0,65280] ; X64-AVX512VL-NEXT: vmovaps {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,32767,65535,0,0,0,0,32769,32768,0,65280]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A] ; X64-AVX512VL-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: retq # encoding: [0xc3] ; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> zeroinitializer, <8 x i32> <i32 255, i32 32767, i32 65535, i32 -1, i32 -32767, i32 -65535, i32 0, i32 -256>) %res = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> zeroinitializer, <8 x i32> <i32 255, i32 32767, i32 65535, i32 -1, i32 -32767, i32 -65535, i32 0, i32 -256>)
ret <16 x i16> %res ret <16 x i16> %res
} }
define <32 x i8> @test_x86_avx2_packsswb(<16 x i16> %a0, <16 x i16> %a1) { define <32 x i8> @test_x86_avx2_packsswb(<16 x i16> %a0, <16 x i16> %a1) {
; AVX2-LABEL: test_x86_avx2_packsswb: ; AVX2-LABEL: test_x86_avx2_packsswb:
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declare <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16>, <16 x i16>) nounwind readnone declare <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16>, <16 x i16>) nounwind readnone
define <32 x i8> @test_x86_avx2_packsswb_fold() { define <32 x i8> @test_x86_avx2_packsswb_fold() {
; X86-AVX-LABEL: test_x86_avx2_packsswb_fold: ; X86-AVX-LABEL: test_x86_avx2_packsswb_fold:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0,0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0] ; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0,0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
; X86-AVX-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A] ; X86-AVX-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: retl # encoding: [0xc3] ; X86-AVX-NEXT: retl # encoding: [0xc3]
; ;
; X86-AVX512VL-LABEL: test_x86_avx2_packsswb_fold: ; X86-AVX512VL-LABEL: test_x86_avx2_packsswb_fold:
; X86-AVX512VL: # %bb.0: ; X86-AVX512VL: # %bb.0:
; X86-AVX512VL-NEXT: vmovaps {{\.LCPI.*}}, %ymm0 # EVEX TO VEX Compression ymm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0,0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0] ; X86-AVX512VL-NEXT: vmovaps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0,0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A] ; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: retl # encoding: [0xc3] ; X86-AVX512VL-NEXT: retl # encoding: [0xc3]
; ;
; X64-AVX-LABEL: test_x86_avx2_packsswb_fold: ; X64-AVX-LABEL: test_x86_avx2_packsswb_fold:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0,0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0] ; X64-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0,0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
; X64-AVX-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A] ; X64-AVX-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: retq # encoding: [0xc3] ; X64-AVX-NEXT: retq # encoding: [0xc3]
; ;
; X64-AVX512VL-LABEL: test_x86_avx2_packsswb_fold: ; X64-AVX512VL-LABEL: test_x86_avx2_packsswb_fold:
; X64-AVX512VL: # %bb.0: ; X64-AVX512VL: # %bb.0:
; X64-AVX512VL-NEXT: vmovaps {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0,0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0] ; X64-AVX512VL-NEXT: vmovaps {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0,0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A] ; X64-AVX512VL-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: retq # encoding: [0xc3] ; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> <i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678, i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678>, <16 x i16> zeroinitializer) %res = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> <i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678, i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678>, <16 x i16> zeroinitializer)
ret <32 x i8> %res ret <32 x i8> %res
} }
define <32 x i8> @test_x86_avx2_packuswb(<16 x i16> %a0, <16 x i16> %a1) { define <32 x i8> @test_x86_avx2_packuswb(<16 x i16> %a0, <16 x i16> %a1) {
; AVX2-LABEL: test_x86_avx2_packuswb: ; AVX2-LABEL: test_x86_avx2_packuswb:
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declare <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16>, <16 x i16>) nounwind readnone declare <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16>, <16 x i16>) nounwind readnone
define <32 x i8> @test_x86_avx2_packuswb_fold() { define <32 x i8> @test_x86_avx2_packuswb_fold() {
; X86-AVX-LABEL: test_x86_avx2_packuswb_fold: ; X86-AVX-LABEL: test_x86_avx2_packuswb_fold:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0] ; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
; X86-AVX-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A] ; X86-AVX-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: retl # encoding: [0xc3] ; X86-AVX-NEXT: retl # encoding: [0xc3]
; ;
; X86-AVX512VL-LABEL: test_x86_avx2_packuswb_fold: ; X86-AVX512VL-LABEL: test_x86_avx2_packuswb_fold:
; X86-AVX512VL: # %bb.0: ; X86-AVX512VL: # %bb.0:
; X86-AVX512VL-NEXT: vmovaps {{\.LCPI.*}}, %ymm0 # EVEX TO VEX Compression ymm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0] ; X86-AVX512VL-NEXT: vmovaps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A] ; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: retl # encoding: [0xc3] ; X86-AVX512VL-NEXT: retl # encoding: [0xc3]
; ;
; X64-AVX-LABEL: test_x86_avx2_packuswb_fold: ; X64-AVX-LABEL: test_x86_avx2_packuswb_fold:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0] ; X64-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
; X64-AVX-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A] ; X64-AVX-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: retq # encoding: [0xc3] ; X64-AVX-NEXT: retq # encoding: [0xc3]
; ;
; X64-AVX512VL-LABEL: test_x86_avx2_packuswb_fold: ; X64-AVX512VL-LABEL: test_x86_avx2_packuswb_fold:
; X64-AVX512VL: # %bb.0: ; X64-AVX512VL: # %bb.0:
; X64-AVX512VL-NEXT: vmovaps {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0] ; X64-AVX512VL-NEXT: vmovaps {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0,0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A] ; X64-AVX512VL-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: retq # encoding: [0xc3] ; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> <i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678, i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678>, <16 x i16> zeroinitializer) %res = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> <i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678, i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678>, <16 x i16> zeroinitializer)
ret <32 x i8> %res ret <32 x i8> %res
} }
define <32 x i8> @test_x86_avx2_pavg_b(<32 x i8> %a0, <32 x i8> %a1) { define <32 x i8> @test_x86_avx2_pavg_b(<32 x i8> %a0, <32 x i8> %a1) {
; AVX2-LABEL: test_x86_avx2_pavg_b: ; AVX2-LABEL: test_x86_avx2_pavg_b:
▲ Show 20 Lines • Show All 592 Lines • ▼ Show 20 Lines
declare <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32>, <8 x i32>) nounwind readnone declare <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32>, <8 x i32>) nounwind readnone
define <16 x i16> @test_x86_avx2_packusdw_fold() { define <16 x i16> @test_x86_avx2_packusdw_fold() {
; X86-AVX-LABEL: test_x86_avx2_packusdw_fold: ; X86-AVX-LABEL: test_x86_avx2_packusdw_fold:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0] ; X86-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0]
; X86-AVX-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A] ; X86-AVX-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: retl # encoding: [0xc3] ; X86-AVX-NEXT: retl # encoding: [0xc3]
; ;
; X86-AVX512VL-LABEL: test_x86_avx2_packusdw_fold: ; X86-AVX512VL-LABEL: test_x86_avx2_packusdw_fold:
; X86-AVX512VL: # %bb.0: ; X86-AVX512VL: # %bb.0:
; X86-AVX512VL-NEXT: vmovaps {{\.LCPI.*}}, %ymm0 # EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0] ; X86-AVX512VL-NEXT: vmovaps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A] ; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: retl # encoding: [0xc3] ; X86-AVX512VL-NEXT: retl # encoding: [0xc3]
; ;
; X64-AVX-LABEL: test_x86_avx2_packusdw_fold: ; X64-AVX-LABEL: test_x86_avx2_packusdw_fold:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0] ; X64-AVX-NEXT: vmovaps {{.*#+}} ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0]
; X64-AVX-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A] ; X64-AVX-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: retq # encoding: [0xc3] ; X64-AVX-NEXT: retq # encoding: [0xc3]
; ;
; X64-AVX512VL-LABEL: test_x86_avx2_packusdw_fold: ; X64-AVX512VL-LABEL: test_x86_avx2_packusdw_fold:
; X64-AVX512VL: # %bb.0: ; X64-AVX512VL: # %bb.0:
; X64-AVX512VL-NEXT: vmovaps {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0] ; X64-AVX512VL-NEXT: vmovaps {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [0,0,0,0,255,32767,65535,0,0,0,0,0,0,0,0,0]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A] ; X64-AVX512VL-NEXT: # encoding: [0xc5,0xfc,0x28,0x05,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: retq # encoding: [0xc3] ; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> zeroinitializer, <8 x i32> <i32 255, i32 32767, i32 65535, i32 -1, i32 -32767, i32 -65535, i32 0, i32 -256>) %res = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> zeroinitializer, <8 x i32> <i32 255, i32 32767, i32 65535, i32 -1, i32 -32767, i32 -65535, i32 0, i32 -256>)
ret <16 x i16> %res ret <16 x i16> %res
} }
define <32 x i8> @test_x86_avx2_pblendvb(<32 x i8> %a0, <32 x i8> %a1, <32 x i8> %a2) { define <32 x i8> @test_x86_avx2_pblendvb(<32 x i8> %a0, <32 x i8> %a1, <32 x i8> %a2) {
; CHECK-LABEL: test_x86_avx2_pblendvb: ; CHECK-LABEL: test_x86_avx2_pblendvb:
▲ Show 20 Lines • Show All 234 Lines • ▼ Show 20 Lines; AVX512VL-NEXT: ret{{[l|q]}} # encoding: [0xc3]
ret <4 x i32> %res ret <4 x i32> %res
} }
define <4 x i32> @test_x86_avx2_psllv_d_const() { define <4 x i32> @test_x86_avx2_psllv_d_const() {
; X86-AVX-LABEL: test_x86_avx2_psllv_d_const: ; X86-AVX-LABEL: test_x86_avx2_psllv_d_const:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [2,9,0,4294967295] ; X86-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [2,9,0,4294967295]
; X86-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A] ; X86-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: vpsllvd {{\.LCPI.*}}, %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x79,0x47,0x05,A,A,A,A] ; X86-AVX-NEXT: vpsllvd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x79,0x47,0x05,A,A,A,A]
; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [1,1,1,4294967295] ; X86-AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [1,1,1,4294967295]
; X86-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x0d,A,A,A,A] ; X86-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x0d,A,A,A,A]
; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: vpsllvd %xmm1, %xmm1, %xmm1 # encoding: [0xc4,0xe2,0x71,0x47,0xc9] ; X86-AVX-NEXT: vpsllvd %xmm1, %xmm1, %xmm1 # encoding: [0xc4,0xe2,0x71,0x47,0xc9]
; X86-AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf9,0xfe,0xc1] ; X86-AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf9,0xfe,0xc1]
; X86-AVX-NEXT: retl # encoding: [0xc3] ; X86-AVX-NEXT: retl # encoding: [0xc3]
; ;
; X86-AVX512VL-LABEL: test_x86_avx2_psllv_d_const: ; X86-AVX512VL-LABEL: test_x86_avx2_psllv_d_const:
; X86-AVX512VL: # %bb.0: ; X86-AVX512VL: # %bb.0:
; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI.*}}, %xmm0 # EVEX TO VEX Compression xmm0 = [2,9,0,4294967295] ; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %xmm0 # EVEX TO VEX Compression xmm0 = [2,9,0,4294967295]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A] ; X86-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: vpsllvd {{\.LCPI.*}}, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x47,0x05,A,A,A,A] ; X86-AVX512VL-NEXT: vpsllvd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x47,0x05,A,A,A,A]
; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI.*}}, %xmm1 # EVEX TO VEX Compression xmm1 = [1,1,1,4294967295] ; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %xmm1 # EVEX TO VEX Compression xmm1 = [1,1,1,4294967295]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x0d,A,A,A,A] ; X86-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x0d,A,A,A,A]
; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: vpsllvd %xmm1, %xmm1, %xmm1 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x71,0x47,0xc9] ; X86-AVX512VL-NEXT: vpsllvd %xmm1, %xmm1, %xmm1 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x71,0x47,0xc9]
; X86-AVX512VL-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0xfe,0xc1] ; X86-AVX512VL-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0xfe,0xc1]
; X86-AVX512VL-NEXT: retl # encoding: [0xc3] ; X86-AVX512VL-NEXT: retl # encoding: [0xc3]
; ;
; X64-AVX-LABEL: test_x86_avx2_psllv_d_const: ; X64-AVX-LABEL: test_x86_avx2_psllv_d_const:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [2,9,0,4294967295] ; X64-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [2,9,0,4294967295]
; X64-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A] ; X64-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x79,0x47,0x05,A,A,A,A] ; X64-AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x79,0x47,0x05,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [1,1,1,4294967295] ; X64-AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [1,1,1,4294967295]
; X64-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x0d,A,A,A,A] ; X64-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x0d,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: vpsllvd %xmm1, %xmm1, %xmm1 # encoding: [0xc4,0xe2,0x71,0x47,0xc9] ; X64-AVX-NEXT: vpsllvd %xmm1, %xmm1, %xmm1 # encoding: [0xc4,0xe2,0x71,0x47,0xc9]
; X64-AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf9,0xfe,0xc1] ; X64-AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf9,0xfe,0xc1]
; X64-AVX-NEXT: retq # encoding: [0xc3] ; X64-AVX-NEXT: retq # encoding: [0xc3]
; ;
; X64-AVX512VL-LABEL: test_x86_avx2_psllv_d_const: ; X64-AVX512VL-LABEL: test_x86_avx2_psllv_d_const:
; X64-AVX512VL: # %bb.0: ; X64-AVX512VL: # %bb.0:
; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [2,9,0,4294967295] ; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [2,9,0,4294967295]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A] ; X64-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x47,0x05,A,A,A,A] ; X64-AVX512VL-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x47,0x05,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %xmm1 # EVEX TO VEX Compression xmm1 = [1,1,1,4294967295] ; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %xmm1 # EVEX TO VEX Compression xmm1 = [1,1,1,4294967295]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x0d,A,A,A,A] ; X64-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x0d,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: vpsllvd %xmm1, %xmm1, %xmm1 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x71,0x47,0xc9] ; X64-AVX512VL-NEXT: vpsllvd %xmm1, %xmm1, %xmm1 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x71,0x47,0xc9]
; X64-AVX512VL-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0xfe,0xc1] ; X64-AVX512VL-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0xfe,0xc1]
; X64-AVX512VL-NEXT: retq # encoding: [0xc3] ; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
%res0 = call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> <i32 2, i32 9, i32 0, i32 -1>, <4 x i32> <i32 1, i32 0, i32 33, i32 -1>) %res0 = call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> <i32 2, i32 9, i32 0, i32 -1>, <4 x i32> <i32 1, i32 0, i32 33, i32 -1>)
%res1 = call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> <i32 1, i32 1, i32 1, i32 -1>, <4 x i32> <i32 1, i32 1, i32 1, i32 -1>) %res1 = call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> <i32 1, i32 1, i32 1, i32 -1>, <4 x i32> <i32 1, i32 1, i32 1, i32 -1>)
%res2 = add <4 x i32> %res0, %res1 %res2 = add <4 x i32> %res0, %res1
ret <4 x i32> %res2 ret <4 x i32> %res2
} }
Show All 14 Lines; AVX512VL-NEXT: ret{{[l|q]}} # encoding: [0xc3]
ret <8 x i32> %res ret <8 x i32> %res
} }
define <8 x i32> @test_x86_avx2_psllv_d_256_const() { define <8 x i32> @test_x86_avx2_psllv_d_256_const() {
; X86-AVX-LABEL: test_x86_avx2_psllv_d_256_const: ; X86-AVX-LABEL: test_x86_avx2_psllv_d_256_const:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [2,9,0,4294967295,3,7,4294967295,0] ; X86-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [2,9,0,4294967295,3,7,4294967295,0]
; X86-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A] ; X86-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: vpsllvd {{\.LCPI.*}}, %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x47,0x05,A,A,A,A] ; X86-AVX-NEXT: vpsllvd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x47,0x05,A,A,A,A]
; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,4,4,4,4,4,4,4294967295] ; X86-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,4,4,4,4,4,4,4294967295]
; X86-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x0d,A,A,A,A] ; X86-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x0d,A,A,A,A]
; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: vpsllvd {{\.LCPI.*}}, %ymm1, %ymm1 # encoding: [0xc4,0xe2,0x75,0x47,0x0d,A,A,A,A] ; X86-AVX-NEXT: vpsllvd {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm1 # encoding: [0xc4,0xe2,0x75,0x47,0x0d,A,A,A,A]
; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # encoding: [0xc5,0xfd,0xfe,0xc1] ; X86-AVX-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # encoding: [0xc5,0xfd,0xfe,0xc1]
; X86-AVX-NEXT: retl # encoding: [0xc3] ; X86-AVX-NEXT: retl # encoding: [0xc3]
; ;
; X86-AVX512VL-LABEL: test_x86_avx2_psllv_d_256_const: ; X86-AVX512VL-LABEL: test_x86_avx2_psllv_d_256_const:
; X86-AVX512VL: # %bb.0: ; X86-AVX512VL: # %bb.0:
; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI.*}}, %ymm0 # EVEX TO VEX Compression ymm0 = [2,9,0,4294967295,3,7,4294967295,0] ; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [2,9,0,4294967295,3,7,4294967295,0]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A] ; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: vpsllvd {{\.LCPI.*}}, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x47,0x05,A,A,A,A] ; X86-AVX512VL-NEXT: vpsllvd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x47,0x05,A,A,A,A]
; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI.*}}, %ymm1 # EVEX TO VEX Compression ymm1 = [4,4,4,4,4,4,4,4294967295] ; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %ymm1 # EVEX TO VEX Compression ymm1 = [4,4,4,4,4,4,4,4294967295]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x0d,A,A,A,A] ; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x0d,A,A,A,A]
; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: vpsllvd {{\.LCPI.*}}, %ymm1, %ymm1 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x47,0x0d,A,A,A,A] ; X86-AVX512VL-NEXT: vpsllvd {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm1 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x47,0x0d,A,A,A,A]
; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0xfe,0xc1] ; X86-AVX512VL-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0xfe,0xc1]
; X86-AVX512VL-NEXT: retl # encoding: [0xc3] ; X86-AVX512VL-NEXT: retl # encoding: [0xc3]
; ;
; X64-AVX-LABEL: test_x86_avx2_psllv_d_256_const: ; X64-AVX-LABEL: test_x86_avx2_psllv_d_256_const:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [2,9,0,4294967295,3,7,4294967295,0] ; X64-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [2,9,0,4294967295,3,7,4294967295,0]
; X64-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A] ; X64-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: vpsllvd {{.*}}(%rip), %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x47,0x05,A,A,A,A] ; X64-AVX-NEXT: vpsllvd {{.*}}(%rip), %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x47,0x05,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,4,4,4,4,4,4,4294967295] ; X64-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,4,4,4,4,4,4,4294967295]
; X64-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x0d,A,A,A,A] ; X64-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x0d,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: vpsllvd {{.*}}(%rip), %ymm1, %ymm1 # encoding: [0xc4,0xe2,0x75,0x47,0x0d,A,A,A,A] ; X64-AVX-NEXT: vpsllvd {{.*}}(%rip), %ymm1, %ymm1 # encoding: [0xc4,0xe2,0x75,0x47,0x0d,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # encoding: [0xc5,0xfd,0xfe,0xc1] ; X64-AVX-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # encoding: [0xc5,0xfd,0xfe,0xc1]
; X64-AVX-NEXT: retq # encoding: [0xc3] ; X64-AVX-NEXT: retq # encoding: [0xc3]
; ;
; X64-AVX512VL-LABEL: test_x86_avx2_psllv_d_256_const: ; X64-AVX512VL-LABEL: test_x86_avx2_psllv_d_256_const:
; X64-AVX512VL: # %bb.0: ; X64-AVX512VL: # %bb.0:
; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [2,9,0,4294967295,3,7,4294967295,0] ; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [2,9,0,4294967295,3,7,4294967295,0]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A] ; X64-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: vpsllvd {{.*}}(%rip), %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x47,0x05,A,A,A,A] ; X64-AVX512VL-NEXT: vpsllvd {{.*}}(%rip), %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x47,0x05,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %ymm1 # EVEX TO VEX Compression ymm1 = [4,4,4,4,4,4,4,4294967295] ; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %ymm1 # EVEX TO VEX Compression ymm1 = [4,4,4,4,4,4,4,4294967295]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x0d,A,A,A,A] ; X64-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x0d,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: vpsllvd {{.*}}(%rip), %ymm1, %ymm1 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x47,0x0d,A,A,A,A] ; X64-AVX512VL-NEXT: vpsllvd {{.*}}(%rip), %ymm1, %ymm1 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x47,0x0d,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0xfe,0xc1] ; X64-AVX512VL-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0xfe,0xc1]
; X64-AVX512VL-NEXT: retq # encoding: [0xc3] ; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
%res0 = call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> <i32 2, i32 9, i32 0, i32 -1, i32 3, i32 7, i32 -1, i32 0>, <8 x i32> <i32 1, i32 0, i32 33, i32 -1,i32 2, i32 0, i32 34, i32 -2>) %res0 = call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> <i32 2, i32 9, i32 0, i32 -1, i32 3, i32 7, i32 -1, i32 0>, <8 x i32> <i32 1, i32 0, i32 33, i32 -1,i32 2, i32 0, i32 34, i32 -2>)
%res1 = call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> <i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 -1>, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 -1>) %res1 = call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> <i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 -1>, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 -1>)
%res2 = add <8 x i32> %res0, %res1 %res2 = add <8 x i32> %res0, %res1
ret <8 x i32> %res2 ret <8 x i32> %res2
} }
declare <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32>, <8 x i32>) nounwind readnone declare <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32>, <8 x i32>) nounwind readnone
Show All 12 Lines; AVX512VL-NEXT: ret{{[l|q]}} # encoding: [0xc3]
%res = call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1] %res = call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]
ret <2 x i64> %res ret <2 x i64> %res
} }
define <2 x i64> @test_x86_avx2_psllv_q_const() { define <2 x i64> @test_x86_avx2_psllv_q_const() {
; X86-AVX-LABEL: test_x86_avx2_psllv_q_const: ; X86-AVX-LABEL: test_x86_avx2_psllv_q_const:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4,0,4294967295,4294967295] ; X86-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4,0,4294967295,4294967295]
; X86-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A] ; X86-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: vpsllvq {{\.LCPI.*}}, %xmm0, %xmm0 # encoding: [0xc4,0xe2,0xf9,0x47,0x05,A,A,A,A] ; X86-AVX-NEXT: vpsllvq {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # encoding: [0xc4,0xe2,0xf9,0x47,0x05,A,A,A,A]
; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: retl # encoding: [0xc3] ; X86-AVX-NEXT: retl # encoding: [0xc3]
; ;
; X86-AVX512VL-LABEL: test_x86_avx2_psllv_q_const: ; X86-AVX512VL-LABEL: test_x86_avx2_psllv_q_const:
; X86-AVX512VL: # %bb.0: ; X86-AVX512VL: # %bb.0:
; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI.*}}, %xmm0 # EVEX TO VEX Compression xmm0 = [4,0,4294967295,4294967295] ; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %xmm0 # EVEX TO VEX Compression xmm0 = [4,0,4294967295,4294967295]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A] ; X86-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: vpsllvq {{\.LCPI.*}}, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xf9,0x47,0x05,A,A,A,A] ; X86-AVX512VL-NEXT: vpsllvq {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xf9,0x47,0x05,A,A,A,A]
; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: retl # encoding: [0xc3] ; X86-AVX512VL-NEXT: retl # encoding: [0xc3]
; ;
; X64-AVX-LABEL: test_x86_avx2_psllv_q_const: ; X64-AVX-LABEL: test_x86_avx2_psllv_q_const:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4,18446744073709551615] ; X64-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4,18446744073709551615]
; X64-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A] ; X64-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: vpsllvq {{.*}}(%rip), %xmm0, %xmm0 # encoding: [0xc4,0xe2,0xf9,0x47,0x05,A,A,A,A] ; X64-AVX-NEXT: vpsllvq {{.*}}(%rip), %xmm0, %xmm0 # encoding: [0xc4,0xe2,0xf9,0x47,0x05,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: retq # encoding: [0xc3] ; X64-AVX-NEXT: retq # encoding: [0xc3]
; ;
; X64-AVX512VL-LABEL: test_x86_avx2_psllv_q_const: ; X64-AVX512VL-LABEL: test_x86_avx2_psllv_q_const:
; X64-AVX512VL: # %bb.0: ; X64-AVX512VL: # %bb.0:
; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [4,18446744073709551615] ; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [4,18446744073709551615]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A] ; X64-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: vpsllvq {{.*}}(%rip), %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xf9,0x47,0x05,A,A,A,A] ; X64-AVX512VL-NEXT: vpsllvq {{.*}}(%rip), %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xf9,0x47,0x05,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: retq # encoding: [0xc3] ; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
%res = call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> <i64 4, i64 -1>, <2 x i64> <i64 1, i64 -1>) %res = call <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64> <i64 4, i64 -1>, <2 x i64> <i64 1, i64 -1>)
ret <2 x i64> %res ret <2 x i64> %res
} }
declare <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64>, <2 x i64>) nounwind readnone declare <2 x i64> @llvm.x86.avx2.psllv.q(<2 x i64>, <2 x i64>) nounwind readnone
define <4 x i64> @test_x86_avx2_psllv_q_256(<4 x i64> %a0, <4 x i64> %a1) { define <4 x i64> @test_x86_avx2_psllv_q_256(<4 x i64> %a0, <4 x i64> %a1) {
Show All 10 Lines; AVX512VL-NEXT: ret{{[l|q]}} # encoding: [0xc3]
ret <4 x i64> %res ret <4 x i64> %res
} }
define <4 x i64> @test_x86_avx2_psllv_q_256_const() { define <4 x i64> @test_x86_avx2_psllv_q_256_const() {
; X86-AVX-LABEL: test_x86_avx2_psllv_q_256_const: ; X86-AVX-LABEL: test_x86_avx2_psllv_q_256_const:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [4,0,4,0,4,0,4294967295,4294967295] ; X86-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [4,0,4,0,4,0,4294967295,4294967295]
; X86-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A] ; X86-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: vpsllvq {{\.LCPI.*}}, %ymm0, %ymm0 # encoding: [0xc4,0xe2,0xfd,0x47,0x05,A,A,A,A] ; X86-AVX-NEXT: vpsllvq {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # encoding: [0xc4,0xe2,0xfd,0x47,0x05,A,A,A,A]
; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: retl # encoding: [0xc3] ; X86-AVX-NEXT: retl # encoding: [0xc3]
; ;
; X86-AVX512VL-LABEL: test_x86_avx2_psllv_q_256_const: ; X86-AVX512VL-LABEL: test_x86_avx2_psllv_q_256_const:
; X86-AVX512VL: # %bb.0: ; X86-AVX512VL: # %bb.0:
; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI.*}}, %ymm0 # EVEX TO VEX Compression ymm0 = [4,0,4,0,4,0,4294967295,4294967295] ; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [4,0,4,0,4,0,4294967295,4294967295]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A] ; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: vpsllvq {{\.LCPI.*}}, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xfd,0x47,0x05,A,A,A,A] ; X86-AVX512VL-NEXT: vpsllvq {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xfd,0x47,0x05,A,A,A,A]
; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: retl # encoding: [0xc3] ; X86-AVX512VL-NEXT: retl # encoding: [0xc3]
; ;
; X64-AVX-LABEL: test_x86_avx2_psllv_q_256_const: ; X64-AVX-LABEL: test_x86_avx2_psllv_q_256_const:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [4,4,4,18446744073709551615] ; X64-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [4,4,4,18446744073709551615]
; X64-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A] ; X64-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: vpsllvq {{.*}}(%rip), %ymm0, %ymm0 # encoding: [0xc4,0xe2,0xfd,0x47,0x05,A,A,A,A] ; X64-AVX-NEXT: vpsllvq {{.*}}(%rip), %ymm0, %ymm0 # encoding: [0xc4,0xe2,0xfd,0x47,0x05,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: retq # encoding: [0xc3] ; X64-AVX-NEXT: retq # encoding: [0xc3]
; ;
; X64-AVX512VL-LABEL: test_x86_avx2_psllv_q_256_const: ; X64-AVX512VL-LABEL: test_x86_avx2_psllv_q_256_const:
; X64-AVX512VL: # %bb.0: ; X64-AVX512VL: # %bb.0:
; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [4,4,4,18446744073709551615] ; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [4,4,4,18446744073709551615]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A] ; X64-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: vpsllvq {{.*}}(%rip), %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xfd,0x47,0x05,A,A,A,A] ; X64-AVX512VL-NEXT: vpsllvq {{.*}}(%rip), %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xfd,0x47,0x05,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: retq # encoding: [0xc3] ; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> <i64 4, i64 4, i64 4, i64 -1>, <4 x i64> <i64 1, i64 1, i64 1, i64 -1>) %res = call <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64> <i64 4, i64 4, i64 4, i64 -1>, <4 x i64> <i64 1, i64 1, i64 1, i64 -1>)
ret <4 x i64> %res ret <4 x i64> %res
} }
declare <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64>, <4 x i64>) nounwind readnone declare <4 x i64> @llvm.x86.avx2.psllv.q.256(<4 x i64>, <4 x i64>) nounwind readnone
define <4 x i32> @test_x86_avx2_psrlv_d(<4 x i32> %a0, <4 x i32> %a1) { define <4 x i32> @test_x86_avx2_psrlv_d(<4 x i32> %a0, <4 x i32> %a1) {
Show All 10 Lines; AVX512VL-NEXT: ret{{[l|q]}} # encoding: [0xc3]
ret <4 x i32> %res ret <4 x i32> %res
} }
define <4 x i32> @test_x86_avx2_psrlv_d_const() { define <4 x i32> @test_x86_avx2_psrlv_d_const() {
; X86-AVX-LABEL: test_x86_avx2_psrlv_d_const: ; X86-AVX-LABEL: test_x86_avx2_psrlv_d_const:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [2,9,0,4294967295] ; X86-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [2,9,0,4294967295]
; X86-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A] ; X86-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: vpsrlvd {{\.LCPI.*}}, %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x79,0x45,0x05,A,A,A,A] ; X86-AVX-NEXT: vpsrlvd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x79,0x45,0x05,A,A,A,A]
; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [4,4,4,4294967295] ; X86-AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [4,4,4,4294967295]
; X86-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x0d,A,A,A,A] ; X86-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x0d,A,A,A,A]
; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: vpsrlvd {{\.LCPI.*}}, %xmm1, %xmm1 # encoding: [0xc4,0xe2,0x71,0x45,0x0d,A,A,A,A] ; X86-AVX-NEXT: vpsrlvd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1 # encoding: [0xc4,0xe2,0x71,0x45,0x0d,A,A,A,A]
; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf9,0xfe,0xc1] ; X86-AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf9,0xfe,0xc1]
; X86-AVX-NEXT: retl # encoding: [0xc3] ; X86-AVX-NEXT: retl # encoding: [0xc3]
; ;
; X86-AVX512VL-LABEL: test_x86_avx2_psrlv_d_const: ; X86-AVX512VL-LABEL: test_x86_avx2_psrlv_d_const:
; X86-AVX512VL: # %bb.0: ; X86-AVX512VL: # %bb.0:
; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI.*}}, %xmm0 # EVEX TO VEX Compression xmm0 = [2,9,0,4294967295] ; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %xmm0 # EVEX TO VEX Compression xmm0 = [2,9,0,4294967295]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A] ; X86-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: vpsrlvd {{\.LCPI.*}}, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x45,0x05,A,A,A,A] ; X86-AVX512VL-NEXT: vpsrlvd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x45,0x05,A,A,A,A]
; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI.*}}, %xmm1 # EVEX TO VEX Compression xmm1 = [4,4,4,4294967295] ; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %xmm1 # EVEX TO VEX Compression xmm1 = [4,4,4,4294967295]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x0d,A,A,A,A] ; X86-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x0d,A,A,A,A]
; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: vpsrlvd {{\.LCPI.*}}, %xmm1, %xmm1 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x71,0x45,0x0d,A,A,A,A] ; X86-AVX512VL-NEXT: vpsrlvd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x71,0x45,0x0d,A,A,A,A]
; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0xfe,0xc1] ; X86-AVX512VL-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0xfe,0xc1]
; X86-AVX512VL-NEXT: retl # encoding: [0xc3] ; X86-AVX512VL-NEXT: retl # encoding: [0xc3]
; ;
; X64-AVX-LABEL: test_x86_avx2_psrlv_d_const: ; X64-AVX-LABEL: test_x86_avx2_psrlv_d_const:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [2,9,0,4294967295] ; X64-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [2,9,0,4294967295]
; X64-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A] ; X64-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x79,0x45,0x05,A,A,A,A] ; X64-AVX-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x79,0x45,0x05,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [4,4,4,4294967295] ; X64-AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [4,4,4,4294967295]
; X64-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x0d,A,A,A,A] ; X64-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x0d,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: vpsrlvd {{.*}}(%rip), %xmm1, %xmm1 # encoding: [0xc4,0xe2,0x71,0x45,0x0d,A,A,A,A] ; X64-AVX-NEXT: vpsrlvd {{.*}}(%rip), %xmm1, %xmm1 # encoding: [0xc4,0xe2,0x71,0x45,0x0d,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf9,0xfe,0xc1] ; X64-AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf9,0xfe,0xc1]
; X64-AVX-NEXT: retq # encoding: [0xc3] ; X64-AVX-NEXT: retq # encoding: [0xc3]
; ;
; X64-AVX512VL-LABEL: test_x86_avx2_psrlv_d_const: ; X64-AVX512VL-LABEL: test_x86_avx2_psrlv_d_const:
; X64-AVX512VL: # %bb.0: ; X64-AVX512VL: # %bb.0:
; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [2,9,0,4294967295] ; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [2,9,0,4294967295]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A] ; X64-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x45,0x05,A,A,A,A] ; X64-AVX512VL-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x45,0x05,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %xmm1 # EVEX TO VEX Compression xmm1 = [4,4,4,4294967295] ; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %xmm1 # EVEX TO VEX Compression xmm1 = [4,4,4,4294967295]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x0d,A,A,A,A] ; X64-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x0d,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: vpsrlvd {{.*}}(%rip), %xmm1, %xmm1 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x71,0x45,0x0d,A,A,A,A] ; X64-AVX512VL-NEXT: vpsrlvd {{.*}}(%rip), %xmm1, %xmm1 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x71,0x45,0x0d,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0xfe,0xc1] ; X64-AVX512VL-NEXT: vpaddd %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0xfe,0xc1]
; X64-AVX512VL-NEXT: retq # encoding: [0xc3] ; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
%res0 = call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> <i32 2, i32 9, i32 0, i32 -1>, <4 x i32> <i32 1, i32 0, i32 33, i32 -1>) %res0 = call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> <i32 2, i32 9, i32 0, i32 -1>, <4 x i32> <i32 1, i32 0, i32 33, i32 -1>)
%res1 = call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> <i32 4, i32 4, i32 4, i32 -1>, <4 x i32> <i32 1, i32 1, i32 1, i32 -1>) %res1 = call <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32> <i32 4, i32 4, i32 4, i32 -1>, <4 x i32> <i32 1, i32 1, i32 1, i32 -1>)
%res2 = add <4 x i32> %res0, %res1 %res2 = add <4 x i32> %res0, %res1
ret <4 x i32> %res2 ret <4 x i32> %res2
} }
declare <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32>, <4 x i32>) nounwind readnone declare <4 x i32> @llvm.x86.avx2.psrlv.d(<4 x i32>, <4 x i32>) nounwind readnone
Show All 13 Lines; AVX512VL-NEXT: ret{{[l|q]}} # encoding: [0xc3]
ret <8 x i32> %res ret <8 x i32> %res
} }
define <8 x i32> @test_x86_avx2_psrlv_d_256_const() { define <8 x i32> @test_x86_avx2_psrlv_d_256_const() {
; X86-AVX-LABEL: test_x86_avx2_psrlv_d_256_const: ; X86-AVX-LABEL: test_x86_avx2_psrlv_d_256_const:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [2,9,0,4294967295,3,7,4294967295,0] ; X86-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [2,9,0,4294967295,3,7,4294967295,0]
; X86-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A] ; X86-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: vpsrlvd {{\.LCPI.*}}, %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x45,0x05,A,A,A,A] ; X86-AVX-NEXT: vpsrlvd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x45,0x05,A,A,A,A]
; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,4,4,4,4,4,4,4294967295] ; X86-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,4,4,4,4,4,4,4294967295]
; X86-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x0d,A,A,A,A] ; X86-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x0d,A,A,A,A]
; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: vpsrlvd {{\.LCPI.*}}, %ymm1, %ymm1 # encoding: [0xc4,0xe2,0x75,0x45,0x0d,A,A,A,A] ; X86-AVX-NEXT: vpsrlvd {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm1 # encoding: [0xc4,0xe2,0x75,0x45,0x0d,A,A,A,A]
; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # encoding: [0xc5,0xfd,0xfe,0xc1] ; X86-AVX-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # encoding: [0xc5,0xfd,0xfe,0xc1]
; X86-AVX-NEXT: retl # encoding: [0xc3] ; X86-AVX-NEXT: retl # encoding: [0xc3]
; ;
; X86-AVX512VL-LABEL: test_x86_avx2_psrlv_d_256_const: ; X86-AVX512VL-LABEL: test_x86_avx2_psrlv_d_256_const:
; X86-AVX512VL: # %bb.0: ; X86-AVX512VL: # %bb.0:
; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI.*}}, %ymm0 # EVEX TO VEX Compression ymm0 = [2,9,0,4294967295,3,7,4294967295,0] ; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [2,9,0,4294967295,3,7,4294967295,0]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A] ; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: vpsrlvd {{\.LCPI.*}}, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x45,0x05,A,A,A,A] ; X86-AVX512VL-NEXT: vpsrlvd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x45,0x05,A,A,A,A]
; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI.*}}, %ymm1 # EVEX TO VEX Compression ymm1 = [4,4,4,4,4,4,4,4294967295] ; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %ymm1 # EVEX TO VEX Compression ymm1 = [4,4,4,4,4,4,4,4294967295]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x0d,A,A,A,A] ; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x0d,A,A,A,A]
; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: vpsrlvd {{\.LCPI.*}}, %ymm1, %ymm1 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x45,0x0d,A,A,A,A] ; X86-AVX512VL-NEXT: vpsrlvd {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm1 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x45,0x0d,A,A,A,A]
; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0xfe,0xc1] ; X86-AVX512VL-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0xfe,0xc1]
; X86-AVX512VL-NEXT: retl # encoding: [0xc3] ; X86-AVX512VL-NEXT: retl # encoding: [0xc3]
; ;
; X64-AVX-LABEL: test_x86_avx2_psrlv_d_256_const: ; X64-AVX-LABEL: test_x86_avx2_psrlv_d_256_const:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [2,9,0,4294967295,3,7,4294967295,0] ; X64-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [2,9,0,4294967295,3,7,4294967295,0]
; X64-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A] ; X64-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: vpsrlvd {{.*}}(%rip), %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x45,0x05,A,A,A,A] ; X64-AVX-NEXT: vpsrlvd {{.*}}(%rip), %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x45,0x05,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,4,4,4,4,4,4,4294967295] ; X64-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,4,4,4,4,4,4,4294967295]
; X64-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x0d,A,A,A,A] ; X64-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x0d,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: vpsrlvd {{.*}}(%rip), %ymm1, %ymm1 # encoding: [0xc4,0xe2,0x75,0x45,0x0d,A,A,A,A] ; X64-AVX-NEXT: vpsrlvd {{.*}}(%rip), %ymm1, %ymm1 # encoding: [0xc4,0xe2,0x75,0x45,0x0d,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # encoding: [0xc5,0xfd,0xfe,0xc1] ; X64-AVX-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # encoding: [0xc5,0xfd,0xfe,0xc1]
; X64-AVX-NEXT: retq # encoding: [0xc3] ; X64-AVX-NEXT: retq # encoding: [0xc3]
; ;
; X64-AVX512VL-LABEL: test_x86_avx2_psrlv_d_256_const: ; X64-AVX512VL-LABEL: test_x86_avx2_psrlv_d_256_const:
; X64-AVX512VL: # %bb.0: ; X64-AVX512VL: # %bb.0:
; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [2,9,0,4294967295,3,7,4294967295,0] ; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [2,9,0,4294967295,3,7,4294967295,0]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A] ; X64-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: vpsrlvd {{.*}}(%rip), %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x45,0x05,A,A,A,A] ; X64-AVX512VL-NEXT: vpsrlvd {{.*}}(%rip), %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x45,0x05,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %ymm1 # EVEX TO VEX Compression ymm1 = [4,4,4,4,4,4,4,4294967295] ; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %ymm1 # EVEX TO VEX Compression ymm1 = [4,4,4,4,4,4,4,4294967295]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x0d,A,A,A,A] ; X64-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x0d,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: vpsrlvd {{.*}}(%rip), %ymm1, %ymm1 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x45,0x0d,A,A,A,A] ; X64-AVX512VL-NEXT: vpsrlvd {{.*}}(%rip), %ymm1, %ymm1 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x75,0x45,0x0d,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0xfe,0xc1] ; X64-AVX512VL-NEXT: vpaddd %ymm1, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0xfe,0xc1]
; X64-AVX512VL-NEXT: retq # encoding: [0xc3] ; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
%res0 = call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> <i32 2, i32 9, i32 0, i32 -1, i32 3, i32 7, i32 -1, i32 0>, <8 x i32> <i32 1, i32 0, i32 33, i32 -1,i32 2, i32 0, i32 34, i32 -2>) %res0 = call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> <i32 2, i32 9, i32 0, i32 -1, i32 3, i32 7, i32 -1, i32 0>, <8 x i32> <i32 1, i32 0, i32 33, i32 -1,i32 2, i32 0, i32 34, i32 -2>)
%res1 = call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> <i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 -1>, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 -1>) %res1 = call <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32> <i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 -1>, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 -1>)
%res2 = add <8 x i32> %res0, %res1 %res2 = add <8 x i32> %res0, %res1
ret <8 x i32> %res2 ret <8 x i32> %res2
} }
declare <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32>, <8 x i32>) nounwind readnone declare <8 x i32> @llvm.x86.avx2.psrlv.d.256(<8 x i32>, <8 x i32>) nounwind readnone
Show All 13 Lines; AVX512VL-NEXT: ret{{[l|q]}} # encoding: [0xc3]
ret <2 x i64> %res ret <2 x i64> %res
} }
define <2 x i64> @test_x86_avx2_psrlv_q_const() { define <2 x i64> @test_x86_avx2_psrlv_q_const() {
; X86-AVX-LABEL: test_x86_avx2_psrlv_q_const: ; X86-AVX-LABEL: test_x86_avx2_psrlv_q_const:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4,0,4,0] ; X86-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4,0,4,0]
; X86-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A] ; X86-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: vpsrlvq {{\.LCPI.*}}, %xmm0, %xmm0 # encoding: [0xc4,0xe2,0xf9,0x45,0x05,A,A,A,A] ; X86-AVX-NEXT: vpsrlvq {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # encoding: [0xc4,0xe2,0xf9,0x45,0x05,A,A,A,A]
; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: retl # encoding: [0xc3] ; X86-AVX-NEXT: retl # encoding: [0xc3]
; ;
; X86-AVX512VL-LABEL: test_x86_avx2_psrlv_q_const: ; X86-AVX512VL-LABEL: test_x86_avx2_psrlv_q_const:
; X86-AVX512VL: # %bb.0: ; X86-AVX512VL: # %bb.0:
; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI.*}}, %xmm0 # EVEX TO VEX Compression xmm0 = [4,0,4,0] ; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %xmm0 # EVEX TO VEX Compression xmm0 = [4,0,4,0]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A] ; X86-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: vpsrlvq {{\.LCPI.*}}, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xf9,0x45,0x05,A,A,A,A] ; X86-AVX512VL-NEXT: vpsrlvq {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xf9,0x45,0x05,A,A,A,A]
; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: retl # encoding: [0xc3] ; X86-AVX512VL-NEXT: retl # encoding: [0xc3]
; ;
; X64-AVX-LABEL: test_x86_avx2_psrlv_q_const: ; X64-AVX-LABEL: test_x86_avx2_psrlv_q_const:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4,4] ; X64-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [4,4]
; X64-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A] ; X64-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: vpsrlvq {{.*}}(%rip), %xmm0, %xmm0 # encoding: [0xc4,0xe2,0xf9,0x45,0x05,A,A,A,A] ; X64-AVX-NEXT: vpsrlvq {{.*}}(%rip), %xmm0, %xmm0 # encoding: [0xc4,0xe2,0xf9,0x45,0x05,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: retq # encoding: [0xc3] ; X64-AVX-NEXT: retq # encoding: [0xc3]
; ;
; X64-AVX512VL-LABEL: test_x86_avx2_psrlv_q_const: ; X64-AVX512VL-LABEL: test_x86_avx2_psrlv_q_const:
; X64-AVX512VL: # %bb.0: ; X64-AVX512VL: # %bb.0:
; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [4,4] ; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [4,4]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A] ; X64-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: vpsrlvq {{.*}}(%rip), %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xf9,0x45,0x05,A,A,A,A] ; X64-AVX512VL-NEXT: vpsrlvq {{.*}}(%rip), %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xf9,0x45,0x05,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: retq # encoding: [0xc3] ; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
%res = call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> <i64 4, i64 4>, <2 x i64> <i64 1, i64 -1>) %res = call <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64> <i64 4, i64 4>, <2 x i64> <i64 1, i64 -1>)
ret <2 x i64> %res ret <2 x i64> %res
} }
declare <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64>, <2 x i64>) nounwind readnone declare <2 x i64> @llvm.x86.avx2.psrlv.q(<2 x i64>, <2 x i64>) nounwind readnone
define <4 x i64> @test_x86_avx2_psrlv_q_256(<4 x i64> %a0, <4 x i64> %a1) { define <4 x i64> @test_x86_avx2_psrlv_q_256(<4 x i64> %a0, <4 x i64> %a1) {
Show All 11 Lines
} }
define <4 x i64> @test_x86_avx2_psrlv_q_256_const() { define <4 x i64> @test_x86_avx2_psrlv_q_256_const() {
; X86-AVX-LABEL: test_x86_avx2_psrlv_q_256_const: ; X86-AVX-LABEL: test_x86_avx2_psrlv_q_256_const:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [4,0,4,0,4,0,4,0] ; X86-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [4,0,4,0,4,0,4,0]
; X86-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A] ; X86-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: vpsrlvq {{\.LCPI.*}}, %ymm0, %ymm0 # encoding: [0xc4,0xe2,0xfd,0x45,0x05,A,A,A,A] ; X86-AVX-NEXT: vpsrlvq {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # encoding: [0xc4,0xe2,0xfd,0x45,0x05,A,A,A,A]
; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: retl # encoding: [0xc3] ; X86-AVX-NEXT: retl # encoding: [0xc3]
; ;
; X86-AVX512VL-LABEL: test_x86_avx2_psrlv_q_256_const: ; X86-AVX512VL-LABEL: test_x86_avx2_psrlv_q_256_const:
; X86-AVX512VL: # %bb.0: ; X86-AVX512VL: # %bb.0:
; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI.*}}, %ymm0 # EVEX TO VEX Compression ymm0 = [4,0,4,0,4,0,4,0] ; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [4,0,4,0,4,0,4,0]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A] ; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: vpsrlvq {{\.LCPI.*}}, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xfd,0x45,0x05,A,A,A,A] ; X86-AVX512VL-NEXT: vpsrlvq {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xfd,0x45,0x05,A,A,A,A]
; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: retl # encoding: [0xc3] ; X86-AVX512VL-NEXT: retl # encoding: [0xc3]
; ;
; X64-AVX-LABEL: test_x86_avx2_psrlv_q_256_const: ; X64-AVX-LABEL: test_x86_avx2_psrlv_q_256_const:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpbroadcastq {{.*#+}} ymm0 = [4,4,4,4] ; X64-AVX-NEXT: vpbroadcastq {{.*#+}} ymm0 = [4,4,4,4]
; X64-AVX-NEXT: # encoding: [0xc4,0xe2,0x7d,0x59,0x05,A,A,A,A] ; X64-AVX-NEXT: # encoding: [0xc4,0xe2,0x7d,0x59,0x05,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: vpsrlvq {{.*}}(%rip), %ymm0, %ymm0 # encoding: [0xc4,0xe2,0xfd,0x45,0x05,A,A,A,A] ; X64-AVX-NEXT: vpsrlvq {{.*}}(%rip), %ymm0, %ymm0 # encoding: [0xc4,0xe2,0xfd,0x45,0x05,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: retq # encoding: [0xc3] ; X64-AVX-NEXT: retq # encoding: [0xc3]
; ;
; X64-AVX512VL-LABEL: test_x86_avx2_psrlv_q_256_const: ; X64-AVX512VL-LABEL: test_x86_avx2_psrlv_q_256_const:
; X64-AVX512VL: # %bb.0: ; X64-AVX512VL: # %bb.0:
; X64-AVX512VL-NEXT: vpbroadcastq {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [4,4,4,4] ; X64-AVX512VL-NEXT: vpbroadcastq {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [4,4,4,4]
; X64-AVX512VL-NEXT: # encoding: [0xc4,0xe2,0x7d,0x59,0x05,A,A,A,A] ; X64-AVX512VL-NEXT: # encoding: [0xc4,0xe2,0x7d,0x59,0x05,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: vpsrlvq {{.*}}(%rip), %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xfd,0x45,0x05,A,A,A,A] ; X64-AVX512VL-NEXT: vpsrlvq {{.*}}(%rip), %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0xfd,0x45,0x05,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: retq # encoding: [0xc3] ; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
%res = call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> <i64 4, i64 4, i64 4, i64 4>, <4 x i64> <i64 1, i64 1, i64 1, i64 -1>) %res = call <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64> <i64 4, i64 4, i64 4, i64 4>, <4 x i64> <i64 1, i64 1, i64 1, i64 -1>)
ret <4 x i64> %res ret <4 x i64> %res
} }
declare <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64>, <4 x i64>) nounwind readnone declare <4 x i64> @llvm.x86.avx2.psrlv.q.256(<4 x i64>, <4 x i64>) nounwind readnone
define <4 x i32> @test_x86_avx2_psrav_d(<4 x i32> %a0, <4 x i32> %a1) { define <4 x i32> @test_x86_avx2_psrav_d(<4 x i32> %a0, <4 x i32> %a1) {
Show All 10 Lines; AVX512VL-NEXT: ret{{[l|q]}} # encoding: [0xc3]
ret <4 x i32> %res ret <4 x i32> %res
} }
define <4 x i32> @test_x86_avx2_psrav_d_const() { define <4 x i32> @test_x86_avx2_psrav_d_const() {
; X86-AVX-LABEL: test_x86_avx2_psrav_d_const: ; X86-AVX-LABEL: test_x86_avx2_psrav_d_const:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [2,9,4294967284,23] ; X86-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [2,9,4294967284,23]
; X86-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A] ; X86-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: vpsravd {{\.LCPI.*}}, %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A] ; X86-AVX-NEXT: vpsravd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A]
; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: retl # encoding: [0xc3] ; X86-AVX-NEXT: retl # encoding: [0xc3]
; ;
; X86-AVX512VL-LABEL: test_x86_avx2_psrav_d_const: ; X86-AVX512VL-LABEL: test_x86_avx2_psrav_d_const:
; X86-AVX512VL: # %bb.0: ; X86-AVX512VL: # %bb.0:
; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI.*}}, %xmm0 # EVEX TO VEX Compression xmm0 = [2,9,4294967284,23] ; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %xmm0 # EVEX TO VEX Compression xmm0 = [2,9,4294967284,23]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A] ; X86-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: vpsravd {{\.LCPI.*}}, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A] ; X86-AVX512VL-NEXT: vpsravd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A]
; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: retl # encoding: [0xc3] ; X86-AVX512VL-NEXT: retl # encoding: [0xc3]
; ;
; X64-AVX-LABEL: test_x86_avx2_psrav_d_const: ; X64-AVX-LABEL: test_x86_avx2_psrav_d_const:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [2,9,4294967284,23] ; X64-AVX-NEXT: vmovdqa {{.*#+}} xmm0 = [2,9,4294967284,23]
; X64-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A] ; X64-AVX-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A] ; X64-AVX-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: retq # encoding: [0xc3] ; X64-AVX-NEXT: retq # encoding: [0xc3]
; ;
; X64-AVX512VL-LABEL: test_x86_avx2_psrav_d_const: ; X64-AVX512VL-LABEL: test_x86_avx2_psrav_d_const:
; X64-AVX512VL: # %bb.0: ; X64-AVX512VL: # %bb.0:
; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [2,9,4294967284,23] ; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [2,9,4294967284,23]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A] ; X64-AVX512VL-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A] ; X64-AVX512VL-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x46,0x05,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: retq # encoding: [0xc3] ; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
%res = call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> <i32 2, i32 9, i32 -12, i32 23>, <4 x i32> <i32 1, i32 18, i32 35, i32 52>) %res = call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> <i32 2, i32 9, i32 -12, i32 23>, <4 x i32> <i32 1, i32 18, i32 35, i32 52>)
ret <4 x i32> %res ret <4 x i32> %res
} }
declare <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32>, <4 x i32>) nounwind readnone declare <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32>, <4 x i32>) nounwind readnone
define <8 x i32> @test_x86_avx2_psrav_d_256(<8 x i32> %a0, <8 x i32> %a1) { define <8 x i32> @test_x86_avx2_psrav_d_256(<8 x i32> %a0, <8 x i32> %a1) {
; AVX2-LABEL: test_x86_avx2_psrav_d_256: ; AVX2-LABEL: test_x86_avx2_psrav_d_256:
Show All 9 Lines; AVX512VL-NEXT: ret{{[l|q]}} # encoding: [0xc3]
ret <8 x i32> %res ret <8 x i32> %res
} }
define <8 x i32> @test_x86_avx2_psrav_d_256_const() { define <8 x i32> @test_x86_avx2_psrav_d_256_const() {
; X86-AVX-LABEL: test_x86_avx2_psrav_d_256_const: ; X86-AVX-LABEL: test_x86_avx2_psrav_d_256_const:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51] ; X86-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
; X86-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A] ; X86-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: vpsravd {{\.LCPI.*}}, %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A] ; X86-AVX-NEXT: vpsravd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX-NEXT: retl # encoding: [0xc3] ; X86-AVX-NEXT: retl # encoding: [0xc3]
; ;
; X86-AVX512VL-LABEL: test_x86_avx2_psrav_d_256_const: ; X86-AVX512VL-LABEL: test_x86_avx2_psrav_d_256_const:
; X86-AVX512VL: # %bb.0: ; X86-AVX512VL: # %bb.0:
; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI.*}}, %ymm0 # EVEX TO VEX Compression ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51] ; X86-AVX512VL-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A] ; X86-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: vpsravd {{\.LCPI.*}}, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A] ; X86-AVX512VL-NEXT: vpsravd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-AVX512VL-NEXT: retl # encoding: [0xc3] ; X86-AVX512VL-NEXT: retl # encoding: [0xc3]
; ;
; X64-AVX-LABEL: test_x86_avx2_psrav_d_256_const: ; X64-AVX-LABEL: test_x86_avx2_psrav_d_256_const:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51] ; X64-AVX-NEXT: vmovdqa {{.*#+}} ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
; X64-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A] ; X64-AVX-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: vpsravd {{.*}}(%rip), %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A] ; X64-AVX-NEXT: vpsravd {{.*}}(%rip), %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: retq # encoding: [0xc3] ; X64-AVX-NEXT: retq # encoding: [0xc3]
; ;
; X64-AVX512VL-LABEL: test_x86_avx2_psrav_d_256_const: ; X64-AVX512VL-LABEL: test_x86_avx2_psrav_d_256_const:
; X64-AVX512VL: # %bb.0: ; X64-AVX512VL: # %bb.0:
; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51] ; X64-AVX512VL-NEXT: vmovdqa {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A] ; X64-AVX512VL-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: vpsravd {{.*}}(%rip), %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A] ; X64-AVX512VL-NEXT: vpsravd {{.*}}(%rip), %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: retq # encoding: [0xc3] ; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> <i32 2, i32 9, i32 -12, i32 23, i32 -26, i32 37, i32 -40, i32 51>, <8 x i32> <i32 1, i32 18, i32 35, i32 52, i32 69, i32 15, i32 32, i32 49>) %res = call <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32> <i32 2, i32 9, i32 -12, i32 23, i32 -26, i32 37, i32 -40, i32 51>, <8 x i32> <i32 1, i32 18, i32 35, i32 52, i32 69, i32 15, i32 32, i32 49>)
ret <8 x i32> %res ret <8 x i32> %res
} }
declare <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32>, <8 x i32>) nounwind readnone declare <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32>, <8 x i32>) nounwind readnone
define <2 x double> @test_x86_avx2_gather_d_pd(<2 x double> %a0, i8* %a1, <4 x i32> %idx, <2 x double> %mask) { define <2 x double> @test_x86_avx2_gather_d_pd(<2 x double> %a0, i8* %a1, <4 x i32> %idx, <2 x double> %mask) {
; X86-LABEL: test_x86_avx2_gather_d_pd: ; X86-LABEL: test_x86_avx2_gather_d_pd:
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llvm/test/CodeGen/X86/avx2-nontemporal.ll

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; X32-NEXT: andl $-32, %esp ; X32-NEXT: andl $-32, %esp
; X32-NEXT: subl $32, %esp ; X32-NEXT: subl $32, %esp
; X32-NEXT: vmovdqa 104(%ebp), %ymm3 ; X32-NEXT: vmovdqa 104(%ebp), %ymm3
; X32-NEXT: vmovdqa 72(%ebp), %ymm4 ; X32-NEXT: vmovdqa 72(%ebp), %ymm4
; X32-NEXT: vmovdqa 40(%ebp), %ymm5 ; X32-NEXT: vmovdqa 40(%ebp), %ymm5
; X32-NEXT: movl 8(%ebp), %ecx ; X32-NEXT: movl 8(%ebp), %ecx
; X32-NEXT: movl 136(%ebp), %edx ; X32-NEXT: movl 136(%ebp), %edx
; X32-NEXT: movl (%edx), %eax ; X32-NEXT: movl (%edx), %eax
; X32-NEXT: vaddps {{\.LCPI.*}}, %ymm0, %ymm0 ; X32-NEXT: vaddps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: vmovntps %ymm0, (%ecx) ; X32-NEXT: vmovntps %ymm0, (%ecx)
; X32-NEXT: vpaddq {{\.LCPI.*}}, %ymm2, %ymm0 ; X32-NEXT: vpaddq {{\.LCPI[0-9]+_[0-9]+}}, %ymm2, %ymm0
; X32-NEXT: addl (%edx), %eax ; X32-NEXT: addl (%edx), %eax
; X32-NEXT: vmovntdq %ymm0, (%ecx) ; X32-NEXT: vmovntdq %ymm0, (%ecx)
; X32-NEXT: vaddpd {{\.LCPI.*}}, %ymm1, %ymm0 ; X32-NEXT: vaddpd {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0
; X32-NEXT: addl (%edx), %eax ; X32-NEXT: addl (%edx), %eax
; X32-NEXT: vmovntpd %ymm0, (%ecx) ; X32-NEXT: vmovntpd %ymm0, (%ecx)
; X32-NEXT: vpaddd {{\.LCPI.*}}, %ymm5, %ymm0 ; X32-NEXT: vpaddd {{\.LCPI[0-9]+_[0-9]+}}, %ymm5, %ymm0
; X32-NEXT: addl (%edx), %eax ; X32-NEXT: addl (%edx), %eax
; X32-NEXT: vmovntdq %ymm0, (%ecx) ; X32-NEXT: vmovntdq %ymm0, (%ecx)
; X32-NEXT: vpaddw {{\.LCPI.*}}, %ymm4, %ymm0 ; X32-NEXT: vpaddw {{\.LCPI[0-9]+_[0-9]+}}, %ymm4, %ymm0
; X32-NEXT: addl (%edx), %eax ; X32-NEXT: addl (%edx), %eax
; X32-NEXT: vmovntdq %ymm0, (%ecx) ; X32-NEXT: vmovntdq %ymm0, (%ecx)
; X32-NEXT: vpaddb {{\.LCPI.*}}, %ymm3, %ymm0 ; X32-NEXT: vpaddb {{\.LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm0
; X32-NEXT: addl (%edx), %eax ; X32-NEXT: addl (%edx), %eax
; X32-NEXT: vmovntdq %ymm0, (%ecx) ; X32-NEXT: vmovntdq %ymm0, (%ecx)
; X32-NEXT: movl %ebp, %esp ; X32-NEXT: movl %ebp, %esp
; X32-NEXT: popl %ebp ; X32-NEXT: popl %ebp
; X32-NEXT: vzeroupper ; X32-NEXT: vzeroupper
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: f: ; X64-LABEL: f:
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llvm/test/CodeGen/X86/avx2-shift.ll

Show First 20 Lines • Show All 418 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%k = lshr <4 x i64> %x, %y1 %k = lshr <4 x i64> %x, %y1
ret <4 x i64> %k ret <4 x i64> %k
} }
define <32 x i8> @shl9(<32 x i8> %A) nounwind { define <32 x i8> @shl9(<32 x i8> %A) nounwind {
; X32-LABEL: shl9: ; X32-LABEL: shl9:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: vpsllw $3, %ymm0, %ymm0 ; X32-NEXT: vpsllw $3, %ymm0, %ymm0
; X32-NEXT: vpand {{\.LCPI.*}}, %ymm0, %ymm0 ; X32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: shl9: ; X64-LABEL: shl9:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpsllw $3, %ymm0, %ymm0 ; X64-NEXT: vpsllw $3, %ymm0, %ymm0
; X64-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0 ; X64-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%B = shl <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> %B = shl <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <32 x i8> %B ret <32 x i8> %B
} }
define <32 x i8> @shr9(<32 x i8> %A) nounwind { define <32 x i8> @shr9(<32 x i8> %A) nounwind {
; X32-LABEL: shr9: ; X32-LABEL: shr9:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: vpsrlw $3, %ymm0, %ymm0 ; X32-NEXT: vpsrlw $3, %ymm0, %ymm0
; X32-NEXT: vpand {{\.LCPI.*}}, %ymm0, %ymm0 ; X32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: shr9: ; X64-LABEL: shr9:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpsrlw $3, %ymm0, %ymm0 ; X64-NEXT: vpsrlw $3, %ymm0, %ymm0
; X64-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0 ; X64-NEXT: vpand {{.*}}(%rip), %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%B = lshr <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> %B = lshr <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
Show All 15 Lines; X64-NEXT: retq
%B = ashr <32 x i8> %A, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> %B = ashr <32 x i8> %A, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
ret <32 x i8> %B ret <32 x i8> %B
} }
define <32 x i8> @sra_v32i8(<32 x i8> %A) nounwind { define <32 x i8> @sra_v32i8(<32 x i8> %A) nounwind {
; X32-LABEL: sra_v32i8: ; X32-LABEL: sra_v32i8:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: vpsrlw $3, %ymm0, %ymm0 ; X32-NEXT: vpsrlw $3, %ymm0, %ymm0
; X32-NEXT: vpand {{\.LCPI.*}}, %ymm0, %ymm0 ; X32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: vmovdqa {{.*#+}} ymm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16] ; X32-NEXT: vmovdqa {{.*#+}} ymm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
; X32-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; X32-NEXT: vpxor %ymm1, %ymm0, %ymm0
; X32-NEXT: vpsubb %ymm1, %ymm0, %ymm0 ; X32-NEXT: vpsubb %ymm1, %ymm0, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: sra_v32i8: ; X64-LABEL: sra_v32i8:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpsrlw $3, %ymm0, %ymm0 ; X64-NEXT: vpsrlw $3, %ymm0, %ymm0
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llvm/test/CodeGen/X86/avx2-vbroadcasti128.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=X32 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=X64
define <4 x double> @test_broadcast_2f64_4f64(<2 x double> *%p) nounwind { define <4 x double> @test_broadcast_2f64_4f64(<2 x double> *%p) nounwind {
; X32-LABEL: test_broadcast_2f64_4f64: ; X32-LABEL: test_broadcast_2f64_4f64:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1] ; X32-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
; X32-NEXT: vaddpd {{\.LCPI.*}}, %ymm0, %ymm0 ; X32-NEXT: vaddpd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_broadcast_2f64_4f64: ; X64-LABEL: test_broadcast_2f64_4f64:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1] ; X64-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
; X64-NEXT: vaddpd {{.*}}(%rip), %ymm0, %ymm0 ; X64-NEXT: vaddpd {{.*}}(%rip), %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = load <2 x double>, <2 x double> *%p %1 = load <2 x double>, <2 x double> *%p
%2 = shufflevector <2 x double> %1, <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1> %2 = shufflevector <2 x double> %1, <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
%3 = fadd <4 x double> %2, <double 1.0, double 2.0, double 3.0, double 4.0> %3 = fadd <4 x double> %2, <double 1.0, double 2.0, double 3.0, double 4.0>
ret <4 x double> %3 ret <4 x double> %3
} }
define <4 x i64> @test_broadcast_2i64_4i64(<2 x i64> *%p) nounwind { define <4 x i64> @test_broadcast_2i64_4i64(<2 x i64> *%p) nounwind {
; X32-LABEL: test_broadcast_2i64_4i64: ; X32-LABEL: test_broadcast_2i64_4i64:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1] ; X32-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
; X32-NEXT: vpaddq {{\.LCPI.*}}, %ymm0, %ymm0 ; X32-NEXT: vpaddq {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_broadcast_2i64_4i64: ; X64-LABEL: test_broadcast_2i64_4i64:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1] ; X64-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
; X64-NEXT: vpaddq {{.*}}(%rip), %ymm0, %ymm0 ; X64-NEXT: vpaddq {{.*}}(%rip), %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = load <2 x i64>, <2 x i64> *%p %1 = load <2 x i64>, <2 x i64> *%p
%2 = shufflevector <2 x i64> %1, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1> %2 = shufflevector <2 x i64> %1, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
%3 = add <4 x i64> %2, <i64 1, i64 2, i64 3, i64 4> %3 = add <4 x i64> %2, <i64 1, i64 2, i64 3, i64 4>
ret <4 x i64> %3 ret <4 x i64> %3
} }
define <8 x float> @test_broadcast_4f32_8f32(<4 x float> *%p) nounwind { define <8 x float> @test_broadcast_4f32_8f32(<4 x float> *%p) nounwind {
; X32-LABEL: test_broadcast_4f32_8f32: ; X32-LABEL: test_broadcast_4f32_8f32:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1] ; X32-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
; X32-NEXT: vaddps {{\.LCPI.*}}, %ymm0, %ymm0 ; X32-NEXT: vaddps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_broadcast_4f32_8f32: ; X64-LABEL: test_broadcast_4f32_8f32:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1] ; X64-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
; X64-NEXT: vaddps {{.*}}(%rip), %ymm0, %ymm0 ; X64-NEXT: vaddps {{.*}}(%rip), %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = load <4 x float>, <4 x float> *%p %1 = load <4 x float>, <4 x float> *%p
%2 = shufflevector <4 x float> %1, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3> %2 = shufflevector <4 x float> %1, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
%3 = fadd <8 x float> %2, <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0> %3 = fadd <8 x float> %2, <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0>
ret <8 x float> %3 ret <8 x float> %3
} }
define <8 x i32> @test_broadcast_4i32_8i32(<4 x i32> *%p) nounwind { define <8 x i32> @test_broadcast_4i32_8i32(<4 x i32> *%p) nounwind {
; X32-LABEL: test_broadcast_4i32_8i32: ; X32-LABEL: test_broadcast_4i32_8i32:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1] ; X32-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
; X32-NEXT: vpaddd {{\.LCPI.*}}, %ymm0, %ymm0 ; X32-NEXT: vpaddd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_broadcast_4i32_8i32: ; X64-LABEL: test_broadcast_4i32_8i32:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1] ; X64-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
; X64-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0 ; X64-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = load <4 x i32>, <4 x i32> *%p %1 = load <4 x i32>, <4 x i32> *%p
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3> %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
%3 = add <8 x i32> %2, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8> %3 = add <8 x i32> %2, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
ret <8 x i32> %3 ret <8 x i32> %3
} }
define <16 x i16> @test_broadcast_8i16_16i16(<8 x i16> *%p) nounwind { define <16 x i16> @test_broadcast_8i16_16i16(<8 x i16> *%p) nounwind {
; X32-LABEL: test_broadcast_8i16_16i16: ; X32-LABEL: test_broadcast_8i16_16i16:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1] ; X32-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
; X32-NEXT: vpaddw {{\.LCPI.*}}, %ymm0, %ymm0 ; X32-NEXT: vpaddw {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_broadcast_8i16_16i16: ; X64-LABEL: test_broadcast_8i16_16i16:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1] ; X64-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
; X64-NEXT: vpaddw {{.*}}(%rip), %ymm0, %ymm0 ; X64-NEXT: vpaddw {{.*}}(%rip), %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = load <8 x i16>, <8 x i16> *%p %1 = load <8 x i16>, <8 x i16> *%p
%2 = shufflevector <8 x i16> %1, <8 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%3 = add <16 x i16> %2, <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 16> %3 = add <16 x i16> %2, <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 16>
ret <16 x i16> %3 ret <16 x i16> %3
} }
define <32 x i8> @test_broadcast_16i8_32i8(<16 x i8> *%p) nounwind { define <32 x i8> @test_broadcast_16i8_32i8(<16 x i8> *%p) nounwind {
; X32-LABEL: test_broadcast_16i8_32i8: ; X32-LABEL: test_broadcast_16i8_32i8:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1] ; X32-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
; X32-NEXT: vpaddb {{\.LCPI.*}}, %ymm0, %ymm0 ; X32-NEXT: vpaddb {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_broadcast_16i8_32i8: ; X64-LABEL: test_broadcast_16i8_32i8:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1] ; X64-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
; X64-NEXT: vpaddb {{.*}}(%rip), %ymm0, %ymm0 ; X64-NEXT: vpaddb {{.*}}(%rip), %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = load <16 x i8>, <16 x i8> *%p %1 = load <16 x i8>, <16 x i8> *%p
%2 = shufflevector <16 x i8> %1, <16 x i8> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%3 = add <32 x i8> %2, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32> %3 = add <32 x i8> %2, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32>
ret <32 x i8> %3 ret <32 x i8> %3
} }
define <4 x double> @test_broadcast_2f64_4f64_reuse(<2 x double>* %p0, <2 x double>* %p1) { define <4 x double> @test_broadcast_2f64_4f64_reuse(<2 x double>* %p0, <2 x double>* %p1) {
; X32-LABEL: test_broadcast_2f64_4f64_reuse: ; X32-LABEL: test_broadcast_2f64_4f64_reuse:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: vbroadcastf128 {{.*#+}} ymm1 = mem[0,1,0,1] ; X32-NEXT: vbroadcastf128 {{.*#+}} ymm1 = mem[0,1,0,1]
; X32-NEXT: vaddpd {{\.LCPI.*}}, %ymm1, %ymm0 ; X32-NEXT: vaddpd {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0
; X32-NEXT: vmovapd %xmm1, (%eax) ; X32-NEXT: vmovapd %xmm1, (%eax)
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_broadcast_2f64_4f64_reuse: ; X64-LABEL: test_broadcast_2f64_4f64_reuse:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vbroadcastf128 {{.*#+}} ymm1 = mem[0,1,0,1] ; X64-NEXT: vbroadcastf128 {{.*#+}} ymm1 = mem[0,1,0,1]
; X64-NEXT: vaddpd {{.*}}(%rip), %ymm1, %ymm0 ; X64-NEXT: vaddpd {{.*}}(%rip), %ymm1, %ymm0
; X64-NEXT: vmovapd %xmm1, (%rsi) ; X64-NEXT: vmovapd %xmm1, (%rsi)
; X64-NEXT: retq ; X64-NEXT: retq
%1 = load <2 x double>, <2 x double>* %p0 %1 = load <2 x double>, <2 x double>* %p0
%2 = shufflevector <2 x double> %1, <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1> %2 = shufflevector <2 x double> %1, <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
%3 = fadd <4 x double> %2, <double 1.0, double 2.0, double 3.0, double 4.0> %3 = fadd <4 x double> %2, <double 1.0, double 2.0, double 3.0, double 4.0>
store <2 x double> %1, <2 x double>* %p1 store <2 x double> %1, <2 x double>* %p1
ret <4 x double> %3 ret <4 x double> %3
} }
define <4 x i64> @test_broadcast_2i64_4i64_reuse(<2 x i64>* %p0, <2 x i64>* %p1) { define <4 x i64> @test_broadcast_2i64_4i64_reuse(<2 x i64>* %p0, <2 x i64>* %p1) {
; X32-LABEL: test_broadcast_2i64_4i64_reuse: ; X32-LABEL: test_broadcast_2i64_4i64_reuse:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1] ; X32-NEXT: vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1]
; X32-NEXT: vpaddq {{\.LCPI.*}}, %ymm1, %ymm0 ; X32-NEXT: vpaddq {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0
; X32-NEXT: vmovdqa %xmm1, (%eax) ; X32-NEXT: vmovdqa %xmm1, (%eax)
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_broadcast_2i64_4i64_reuse: ; X64-LABEL: test_broadcast_2i64_4i64_reuse:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1] ; X64-NEXT: vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1]
; X64-NEXT: vpaddq {{.*}}(%rip), %ymm1, %ymm0 ; X64-NEXT: vpaddq {{.*}}(%rip), %ymm1, %ymm0
; X64-NEXT: vmovdqa %xmm1, (%rsi) ; X64-NEXT: vmovdqa %xmm1, (%rsi)
; X64-NEXT: retq ; X64-NEXT: retq
%1 = load <2 x i64>, <2 x i64>* %p0 %1 = load <2 x i64>, <2 x i64>* %p0
%2 = shufflevector <2 x i64> %1, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1> %2 = shufflevector <2 x i64> %1, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
%3 = add <4 x i64> %2, <i64 1, i64 2, i64 3, i64 4> %3 = add <4 x i64> %2, <i64 1, i64 2, i64 3, i64 4>
store <2 x i64> %1, <2 x i64>* %p1 store <2 x i64> %1, <2 x i64>* %p1
ret <4 x i64> %3 ret <4 x i64> %3
} }
define <8 x float> @test_broadcast_4f32_8f32_reuse(<4 x float>* %p0, <4 x float>* %p1) { define <8 x float> @test_broadcast_4f32_8f32_reuse(<4 x float>* %p0, <4 x float>* %p1) {
; X32-LABEL: test_broadcast_4f32_8f32_reuse: ; X32-LABEL: test_broadcast_4f32_8f32_reuse:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: vbroadcastf128 {{.*#+}} ymm1 = mem[0,1,0,1] ; X32-NEXT: vbroadcastf128 {{.*#+}} ymm1 = mem[0,1,0,1]
; X32-NEXT: vaddps {{\.LCPI.*}}, %ymm1, %ymm0 ; X32-NEXT: vaddps {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0
; X32-NEXT: vmovaps %xmm1, (%eax) ; X32-NEXT: vmovaps %xmm1, (%eax)
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_broadcast_4f32_8f32_reuse: ; X64-LABEL: test_broadcast_4f32_8f32_reuse:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vbroadcastf128 {{.*#+}} ymm1 = mem[0,1,0,1] ; X64-NEXT: vbroadcastf128 {{.*#+}} ymm1 = mem[0,1,0,1]
; X64-NEXT: vaddps {{.*}}(%rip), %ymm1, %ymm0 ; X64-NEXT: vaddps {{.*}}(%rip), %ymm1, %ymm0
; X64-NEXT: vmovaps %xmm1, (%rsi) ; X64-NEXT: vmovaps %xmm1, (%rsi)
; X64-NEXT: retq ; X64-NEXT: retq
%1 = load <4 x float>, <4 x float>* %p0 %1 = load <4 x float>, <4 x float>* %p0
%2 = shufflevector <4 x float> %1, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3> %2 = shufflevector <4 x float> %1, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
%3 = fadd <8 x float> %2, <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0> %3 = fadd <8 x float> %2, <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0>
store <4 x float> %1, <4 x float>* %p1 store <4 x float> %1, <4 x float>* %p1
ret <8 x float> %3 ret <8 x float> %3
} }
define <8 x i32> @test_broadcast_4i32_8i32_reuse(<4 x i32>* %p0, <4 x i32>* %p1) { define <8 x i32> @test_broadcast_4i32_8i32_reuse(<4 x i32>* %p0, <4 x i32>* %p1) {
; X32-LABEL: test_broadcast_4i32_8i32_reuse: ; X32-LABEL: test_broadcast_4i32_8i32_reuse:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1] ; X32-NEXT: vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1]
; X32-NEXT: vpaddd {{\.LCPI.*}}, %ymm1, %ymm0 ; X32-NEXT: vpaddd {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0
; X32-NEXT: vmovdqa %xmm1, (%eax) ; X32-NEXT: vmovdqa %xmm1, (%eax)
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_broadcast_4i32_8i32_reuse: ; X64-LABEL: test_broadcast_4i32_8i32_reuse:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1] ; X64-NEXT: vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1]
; X64-NEXT: vpaddd {{.*}}(%rip), %ymm1, %ymm0 ; X64-NEXT: vpaddd {{.*}}(%rip), %ymm1, %ymm0
; X64-NEXT: vmovdqa %xmm1, (%rsi) ; X64-NEXT: vmovdqa %xmm1, (%rsi)
; X64-NEXT: retq ; X64-NEXT: retq
%1 = load <4 x i32>, <4 x i32>* %p0 %1 = load <4 x i32>, <4 x i32>* %p0
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3> %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
%3 = add <8 x i32> %2, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8> %3 = add <8 x i32> %2, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
store <4 x i32> %1, <4 x i32>* %p1 store <4 x i32> %1, <4 x i32>* %p1
ret <8 x i32> %3 ret <8 x i32> %3
} }
define <16 x i16> @test_broadcast_8i16_16i16_reuse(<8 x i16> *%p0, <8 x i16> *%p1) nounwind { define <16 x i16> @test_broadcast_8i16_16i16_reuse(<8 x i16> *%p0, <8 x i16> *%p1) nounwind {
; X32-LABEL: test_broadcast_8i16_16i16_reuse: ; X32-LABEL: test_broadcast_8i16_16i16_reuse:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1] ; X32-NEXT: vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1]
; X32-NEXT: vpaddw {{\.LCPI.*}}, %ymm1, %ymm0 ; X32-NEXT: vpaddw {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0
; X32-NEXT: vmovdqa %xmm1, (%eax) ; X32-NEXT: vmovdqa %xmm1, (%eax)
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_broadcast_8i16_16i16_reuse: ; X64-LABEL: test_broadcast_8i16_16i16_reuse:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1] ; X64-NEXT: vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1]
; X64-NEXT: vpaddw {{.*}}(%rip), %ymm1, %ymm0 ; X64-NEXT: vpaddw {{.*}}(%rip), %ymm1, %ymm0
; X64-NEXT: vmovdqa %xmm1, (%rsi) ; X64-NEXT: vmovdqa %xmm1, (%rsi)
; X64-NEXT: retq ; X64-NEXT: retq
%1 = load <8 x i16>, <8 x i16> *%p0 %1 = load <8 x i16>, <8 x i16> *%p0
%2 = shufflevector <8 x i16> %1, <8 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%3 = add <16 x i16> %2, <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 16> %3 = add <16 x i16> %2, <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 16>
store <8 x i16> %1, <8 x i16>* %p1 store <8 x i16> %1, <8 x i16>* %p1
ret <16 x i16> %3 ret <16 x i16> %3
} }
define <32 x i8> @test_broadcast_16i8_32i8_reuse(<16 x i8> *%p0, <16 x i8> *%p1) nounwind { define <32 x i8> @test_broadcast_16i8_32i8_reuse(<16 x i8> *%p0, <16 x i8> *%p1) nounwind {
; X32-LABEL: test_broadcast_16i8_32i8_reuse: ; X32-LABEL: test_broadcast_16i8_32i8_reuse:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1] ; X32-NEXT: vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1]
; X32-NEXT: vpaddb {{\.LCPI.*}}, %ymm1, %ymm0 ; X32-NEXT: vpaddb {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0
; X32-NEXT: vmovdqa %xmm1, (%eax) ; X32-NEXT: vmovdqa %xmm1, (%eax)
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: test_broadcast_16i8_32i8_reuse: ; X64-LABEL: test_broadcast_16i8_32i8_reuse:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1] ; X64-NEXT: vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1]
; X64-NEXT: vpaddb {{.*}}(%rip), %ymm1, %ymm0 ; X64-NEXT: vpaddb {{.*}}(%rip), %ymm1, %ymm0
; X64-NEXT: vmovdqa %xmm1, (%rsi) ; X64-NEXT: vmovdqa %xmm1, (%rsi)
Show All 29 Lines

llvm/test/CodeGen/X86/avx2-vector-shifts.ll

Show First 20 Lines • Show All 480 Lines • ▼ Show 20 Lines; X64-NEXT: retq
ret <16 x i16> %shl ret <16 x i16> %shl
} }
define <32 x i8> @shl_32i8(<32 x i8> %r, <32 x i8> %a) nounwind { define <32 x i8> @shl_32i8(<32 x i8> %r, <32 x i8> %a) nounwind {
; X32-LABEL: shl_32i8: ; X32-LABEL: shl_32i8:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: vpsllw $5, %ymm1, %ymm1 ; X32-NEXT: vpsllw $5, %ymm1, %ymm1
; X32-NEXT: vpsllw $4, %ymm0, %ymm2 ; X32-NEXT: vpsllw $4, %ymm0, %ymm2
; X32-NEXT: vpand {{\.LCPI.*}}, %ymm2, %ymm2 ; X32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm2, %ymm2
; X32-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0 ; X32-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; X32-NEXT: vpsllw $2, %ymm0, %ymm2 ; X32-NEXT: vpsllw $2, %ymm0, %ymm2
; X32-NEXT: vpand {{\.LCPI.*}}, %ymm2, %ymm2 ; X32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm2, %ymm2
; X32-NEXT: vpaddb %ymm1, %ymm1, %ymm1 ; X32-NEXT: vpaddb %ymm1, %ymm1, %ymm1
; X32-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0 ; X32-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; X32-NEXT: vpaddb %ymm0, %ymm0, %ymm2 ; X32-NEXT: vpaddb %ymm0, %ymm0, %ymm2
; X32-NEXT: vpaddb %ymm1, %ymm1, %ymm1 ; X32-NEXT: vpaddb %ymm1, %ymm1, %ymm1
; X32-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0 ; X32-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: shl_32i8: ; X64-LABEL: shl_32i8:
▲ Show 20 Lines • Show All 186 Lines • ▼ Show 20 Lines; X64-NEXT: retq
ret <16 x i16> %lshr ret <16 x i16> %lshr
} }
define <32 x i8> @lshr_32i8(<32 x i8> %r, <32 x i8> %a) nounwind { define <32 x i8> @lshr_32i8(<32 x i8> %r, <32 x i8> %a) nounwind {
; X32-LABEL: lshr_32i8: ; X32-LABEL: lshr_32i8:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: vpsllw $5, %ymm1, %ymm1 ; X32-NEXT: vpsllw $5, %ymm1, %ymm1
; X32-NEXT: vpsrlw $4, %ymm0, %ymm2 ; X32-NEXT: vpsrlw $4, %ymm0, %ymm2
; X32-NEXT: vpand {{\.LCPI.*}}, %ymm2, %ymm2 ; X32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm2, %ymm2
; X32-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0 ; X32-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; X32-NEXT: vpsrlw $2, %ymm0, %ymm2 ; X32-NEXT: vpsrlw $2, %ymm0, %ymm2
; X32-NEXT: vpand {{\.LCPI.*}}, %ymm2, %ymm2 ; X32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm2, %ymm2
; X32-NEXT: vpaddb %ymm1, %ymm1, %ymm1 ; X32-NEXT: vpaddb %ymm1, %ymm1, %ymm1
; X32-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0 ; X32-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; X32-NEXT: vpsrlw $1, %ymm0, %ymm2 ; X32-NEXT: vpsrlw $1, %ymm0, %ymm2
; X32-NEXT: vpand {{\.LCPI.*}}, %ymm2, %ymm2 ; X32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm2, %ymm2
; X32-NEXT: vpaddb %ymm1, %ymm1, %ymm1 ; X32-NEXT: vpaddb %ymm1, %ymm1, %ymm1
; X32-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0 ; X32-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: lshr_32i8: ; X64-LABEL: lshr_32i8:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpsllw $5, %ymm1, %ymm1 ; X64-NEXT: vpsllw $5, %ymm1, %ymm1
; X64-NEXT: vpsrlw $4, %ymm0, %ymm2 ; X64-NEXT: vpsrlw $4, %ymm0, %ymm2
Show All 14 Lines

llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,834 Lines • ▼ Show 20 Lines
} }
define <2 x double> @test_mm_cvtu64_sd(<2 x double> %__A, i64 %__B) { define <2 x double> @test_mm_cvtu64_sd(<2 x double> %__A, i64 %__B) {
; X86-LABEL: test_mm_cvtu64_sd: ; X86-LABEL: test_mm_cvtu64_sd:
; X86: # %bb.0: # %entry ; X86: # %bb.0: # %entry
; X86-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X86-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X86-NEXT: vpinsrd $1, {{[0-9]+}}(%esp), %xmm1, %xmm1 ; X86-NEXT: vpinsrd $1, {{[0-9]+}}(%esp), %xmm1, %xmm1
; X86-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1] ; X86-NEXT: vpunpckldq {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
; X86-NEXT: vsubpd {{\.LCPI.*}}, %xmm1, %xmm1 ; X86-NEXT: vsubpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1
; X86-NEXT: vpermilpd {{.*#+}} xmm2 = xmm1[1,0] ; X86-NEXT: vpermilpd {{.*#+}} xmm2 = xmm1[1,0]
; X86-NEXT: vaddsd %xmm1, %xmm2, %xmm1 ; X86-NEXT: vaddsd %xmm1, %xmm2, %xmm1
; X86-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1] ; X86-NEXT: vblendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: test_mm_cvtu64_sd: ; X64-LABEL: test_mm_cvtu64_sd:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: vcvtusi2sd %rdi, %xmm0, %xmm0 ; X64-NEXT: vcvtusi2sd %rdi, %xmm0, %xmm0
Show All 31 Lines
; X86-NEXT: andl $-8, %esp ; X86-NEXT: andl $-8, %esp
; X86-NEXT: subl $16, %esp ; X86-NEXT: subl $16, %esp
; X86-NEXT: movl 12(%ebp), %eax ; X86-NEXT: movl 12(%ebp), %eax
; X86-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X86-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X86-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1 ; X86-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1
; X86-NEXT: vmovq %xmm1, {{[0-9]+}}(%esp) ; X86-NEXT: vmovq %xmm1, {{[0-9]+}}(%esp)
; X86-NEXT: shrl $31, %eax ; X86-NEXT: shrl $31, %eax
; X86-NEXT: fildll {{[0-9]+}}(%esp) ; X86-NEXT: fildll {{[0-9]+}}(%esp)
; X86-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; X86-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; X86-NEXT: fstps {{[0-9]+}}(%esp) ; X86-NEXT: fstps {{[0-9]+}}(%esp)
; X86-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X86-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X86-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] ; X86-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
; X86-NEXT: movl %ebp, %esp ; X86-NEXT: movl %ebp, %esp
; X86-NEXT: popl %ebp ; X86-NEXT: popl %ebp
; X86-NEXT: .cfi_def_cfa %esp, 4 ; X86-NEXT: .cfi_def_cfa %esp, 4
; X86-NEXT: retl ; X86-NEXT: retl
; ;
▲ Show 20 Lines • Show All 1,213 Lines • ▼ Show 20 Linesentry:
%1 = bitcast i8 %__U to <8 x i1> %1 = bitcast i8 %__U to <8 x i1>
%2 = select <8 x i1> %1, <8 x double> %0, <8 x double> zeroinitializer %2 = select <8 x i1> %1, <8 x double> %0, <8 x double> zeroinitializer
ret <8 x double> %2 ret <8 x double> %2
} }
define <8 x double> @test_mm512_fmsub_round_pd(<8 x double> %__A, <8 x double> %__B, <8 x double> %__C) { define <8 x double> @test_mm512_fmsub_round_pd(<8 x double> %__A, <8 x double> %__B, <8 x double> %__C) {
; X86-LABEL: test_mm512_fmsub_round_pd: ; X86-LABEL: test_mm512_fmsub_round_pd:
; X86: # %bb.0: # %entry ; X86: # %bb.0: # %entry
; X86-NEXT: vpxorq {{\.LCPI.*}}{1to8}, %zmm2, %zmm2 ; X86-NEXT: vpxorq {{\.LCPI[0-9]+_[0-9]+}}{1to8}, %zmm2, %zmm2
; X86-NEXT: vfmadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0 ; X86-NEXT: vfmadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: test_mm512_fmsub_round_pd: ; X64-LABEL: test_mm512_fmsub_round_pd:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: vpxorq {{.*}}(%rip){1to8}, %zmm2, %zmm2 ; X64-NEXT: vpxorq {{.*}}(%rip){1to8}, %zmm2, %zmm2
; X64-NEXT: vfmadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0 ; X64-NEXT: vfmadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0
; X64-NEXT: retq ; X64-NEXT: retq
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Linesentry:
%1 = bitcast i8 %__U to <8 x i1> %1 = bitcast i8 %__U to <8 x i1>
%2 = select <8 x i1> %1, <8 x double> %0, <8 x double> zeroinitializer %2 = select <8 x i1> %1, <8 x double> %0, <8 x double> zeroinitializer
ret <8 x double> %2 ret <8 x double> %2
} }
define <8 x double> @test_mm512_fnmadd_round_pd(<8 x double> %__A, <8 x double> %__B, <8 x double> %__C) { define <8 x double> @test_mm512_fnmadd_round_pd(<8 x double> %__A, <8 x double> %__B, <8 x double> %__C) {
; X86-LABEL: test_mm512_fnmadd_round_pd: ; X86-LABEL: test_mm512_fnmadd_round_pd:
; X86: # %bb.0: # %entry ; X86: # %bb.0: # %entry
; X86-NEXT: vpxorq {{\.LCPI.*}}{1to8}, %zmm0, %zmm0 ; X86-NEXT: vpxorq {{\.LCPI[0-9]+_[0-9]+}}{1to8}, %zmm0, %zmm0
; X86-NEXT: vfmadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0 ; X86-NEXT: vfmadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: test_mm512_fnmadd_round_pd: ; X64-LABEL: test_mm512_fnmadd_round_pd:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: vpxorq {{.*}}(%rip){1to8}, %zmm0, %zmm0 ; X64-NEXT: vpxorq {{.*}}(%rip){1to8}, %zmm0, %zmm0
; X64-NEXT: vfmadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0 ; X64-NEXT: vfmadd213pd {rn-sae}, %zmm2, %zmm1, %zmm0
; X64-NEXT: retq ; X64-NEXT: retq
▲ Show 20 Lines • Show All 154 Lines • ▼ Show 20 Linesentry:
%1 = bitcast i8 %__U to <8 x i1> %1 = bitcast i8 %__U to <8 x i1>
%2 = select <8 x i1> %1, <8 x double> %0, <8 x double> zeroinitializer %2 = select <8 x i1> %1, <8 x double> %0, <8 x double> zeroinitializer
ret <8 x double> %2 ret <8 x double> %2
} }
define <8 x double> @test_mm512_fmsub_pd(<8 x double> %__A, <8 x double> %__B, <8 x double> %__C) { define <8 x double> @test_mm512_fmsub_pd(<8 x double> %__A, <8 x double> %__B, <8 x double> %__C) {
; X86-LABEL: test_mm512_fmsub_pd: ; X86-LABEL: test_mm512_fmsub_pd:
; X86: # %bb.0: # %entry ; X86: # %bb.0: # %entry
; X86-NEXT: vpxorq {{\.LCPI.*}}{1to8}, %zmm2, %zmm2 ; X86-NEXT: vpxorq {{\.LCPI[0-9]+_[0-9]+}}{1to8}, %zmm2, %zmm2
; X86-NEXT: vfmadd213pd {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2 ; X86-NEXT: vfmadd213pd {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: test_mm512_fmsub_pd: ; X64-LABEL: test_mm512_fmsub_pd:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: vpxorq {{.*}}(%rip){1to8}, %zmm2, %zmm2 ; X64-NEXT: vpxorq {{.*}}(%rip){1to8}, %zmm2, %zmm2
; X64-NEXT: vfmadd213pd {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2 ; X64-NEXT: vfmadd213pd {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2
; X64-NEXT: retq ; X64-NEXT: retq
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Linesentry:
%1 = bitcast i8 %__U to <8 x i1> %1 = bitcast i8 %__U to <8 x i1>
%2 = select <8 x i1> %1, <8 x double> %0, <8 x double> zeroinitializer %2 = select <8 x i1> %1, <8 x double> %0, <8 x double> zeroinitializer
ret <8 x double> %2 ret <8 x double> %2
} }
define <8 x double> @test_mm512_fnmadd_pd(<8 x double> %__A, <8 x double> %__B, <8 x double> %__C) { define <8 x double> @test_mm512_fnmadd_pd(<8 x double> %__A, <8 x double> %__B, <8 x double> %__C) {
; X86-LABEL: test_mm512_fnmadd_pd: ; X86-LABEL: test_mm512_fnmadd_pd:
; X86: # %bb.0: # %entry ; X86: # %bb.0: # %entry
; X86-NEXT: vpxorq {{\.LCPI.*}}{1to8}, %zmm0, %zmm0 ; X86-NEXT: vpxorq {{\.LCPI[0-9]+_[0-9]+}}{1to8}, %zmm0, %zmm0
; X86-NEXT: vfmadd213pd {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2 ; X86-NEXT: vfmadd213pd {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: test_mm512_fnmadd_pd: ; X64-LABEL: test_mm512_fnmadd_pd:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: vpxorq {{.*}}(%rip){1to8}, %zmm0, %zmm0 ; X64-NEXT: vpxorq {{.*}}(%rip){1to8}, %zmm0, %zmm0
; X64-NEXT: vfmadd213pd {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2 ; X64-NEXT: vfmadd213pd {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2
; X64-NEXT: retq ; X64-NEXT: retq
▲ Show 20 Lines • Show All 156 Lines • ▼ Show 20 Linesentry:
%1 = bitcast i16 %__U to <16 x i1> %1 = bitcast i16 %__U to <16 x i1>
%2 = select <16 x i1> %1, <16 x float> %0, <16 x float> zeroinitializer %2 = select <16 x i1> %1, <16 x float> %0, <16 x float> zeroinitializer
ret <16 x float> %2 ret <16 x float> %2
} }
define <16 x float> @test_mm512_fmsub_round_ps(<16 x float> %__A, <16 x float> %__B, <16 x float> %__C) { define <16 x float> @test_mm512_fmsub_round_ps(<16 x float> %__A, <16 x float> %__B, <16 x float> %__C) {
; X86-LABEL: test_mm512_fmsub_round_ps: ; X86-LABEL: test_mm512_fmsub_round_ps:
; X86: # %bb.0: # %entry ; X86: # %bb.0: # %entry
; X86-NEXT: vpxord {{\.LCPI.*}}{1to16}, %zmm2, %zmm2 ; X86-NEXT: vpxord {{\.LCPI[0-9]+_[0-9]+}}{1to16}, %zmm2, %zmm2
; X86-NEXT: vfmadd213ps {rn-sae}, %zmm2, %zmm1, %zmm0 ; X86-NEXT: vfmadd213ps {rn-sae}, %zmm2, %zmm1, %zmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: test_mm512_fmsub_round_ps: ; X64-LABEL: test_mm512_fmsub_round_ps:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: vpxord {{.*}}(%rip){1to16}, %zmm2, %zmm2 ; X64-NEXT: vpxord {{.*}}(%rip){1to16}, %zmm2, %zmm2
; X64-NEXT: vfmadd213ps {rn-sae}, %zmm2, %zmm1, %zmm0 ; X64-NEXT: vfmadd213ps {rn-sae}, %zmm2, %zmm1, %zmm0
; X64-NEXT: retq ; X64-NEXT: retq
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Linesentry:
%1 = bitcast i16 %__U to <16 x i1> %1 = bitcast i16 %__U to <16 x i1>
%2 = select <16 x i1> %1, <16 x float> %0, <16 x float> zeroinitializer %2 = select <16 x i1> %1, <16 x float> %0, <16 x float> zeroinitializer
ret <16 x float> %2 ret <16 x float> %2
} }
define <16 x float> @test_mm512_fnmadd_round_ps(<16 x float> %__A, <16 x float> %__B, <16 x float> %__C) { define <16 x float> @test_mm512_fnmadd_round_ps(<16 x float> %__A, <16 x float> %__B, <16 x float> %__C) {
; X86-LABEL: test_mm512_fnmadd_round_ps: ; X86-LABEL: test_mm512_fnmadd_round_ps:
; X86: # %bb.0: # %entry ; X86: # %bb.0: # %entry
; X86-NEXT: vpxord {{\.LCPI.*}}{1to16}, %zmm0, %zmm0 ; X86-NEXT: vpxord {{\.LCPI[0-9]+_[0-9]+}}{1to16}, %zmm0, %zmm0
; X86-NEXT: vfmadd213ps {rn-sae}, %zmm2, %zmm1, %zmm0 ; X86-NEXT: vfmadd213ps {rn-sae}, %zmm2, %zmm1, %zmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: test_mm512_fnmadd_round_ps: ; X64-LABEL: test_mm512_fnmadd_round_ps:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: vpxord {{.*}}(%rip){1to16}, %zmm0, %zmm0 ; X64-NEXT: vpxord {{.*}}(%rip){1to16}, %zmm0, %zmm0
; X64-NEXT: vfmadd213ps {rn-sae}, %zmm2, %zmm1, %zmm0 ; X64-NEXT: vfmadd213ps {rn-sae}, %zmm2, %zmm1, %zmm0
; X64-NEXT: retq ; X64-NEXT: retq
▲ Show 20 Lines • Show All 154 Lines • ▼ Show 20 Linesentry:
%1 = bitcast i16 %__U to <16 x i1> %1 = bitcast i16 %__U to <16 x i1>
%2 = select <16 x i1> %1, <16 x float> %0, <16 x float> zeroinitializer %2 = select <16 x i1> %1, <16 x float> %0, <16 x float> zeroinitializer
ret <16 x float> %2 ret <16 x float> %2
} }
define <16 x float> @test_mm512_fmsub_ps(<16 x float> %__A, <16 x float> %__B, <16 x float> %__C) { define <16 x float> @test_mm512_fmsub_ps(<16 x float> %__A, <16 x float> %__B, <16 x float> %__C) {
; X86-LABEL: test_mm512_fmsub_ps: ; X86-LABEL: test_mm512_fmsub_ps:
; X86: # %bb.0: # %entry ; X86: # %bb.0: # %entry
; X86-NEXT: vpxord {{\.LCPI.*}}{1to16}, %zmm2, %zmm2 ; X86-NEXT: vpxord {{\.LCPI[0-9]+_[0-9]+}}{1to16}, %zmm2, %zmm2
; X86-NEXT: vfmadd213ps {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2 ; X86-NEXT: vfmadd213ps {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: test_mm512_fmsub_ps: ; X64-LABEL: test_mm512_fmsub_ps:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: vpxord {{.*}}(%rip){1to16}, %zmm2, %zmm2 ; X64-NEXT: vpxord {{.*}}(%rip){1to16}, %zmm2, %zmm2
; X64-NEXT: vfmadd213ps {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2 ; X64-NEXT: vfmadd213ps {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2
; X64-NEXT: retq ; X64-NEXT: retq
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Linesentry:
%1 = bitcast i16 %__U to <16 x i1> %1 = bitcast i16 %__U to <16 x i1>
%2 = select <16 x i1> %1, <16 x float> %0, <16 x float> zeroinitializer %2 = select <16 x i1> %1, <16 x float> %0, <16 x float> zeroinitializer
ret <16 x float> %2 ret <16 x float> %2
} }
define <16 x float> @test_mm512_fnmadd_ps(<16 x float> %__A, <16 x float> %__B, <16 x float> %__C) { define <16 x float> @test_mm512_fnmadd_ps(<16 x float> %__A, <16 x float> %__B, <16 x float> %__C) {
; X86-LABEL: test_mm512_fnmadd_ps: ; X86-LABEL: test_mm512_fnmadd_ps:
; X86: # %bb.0: # %entry ; X86: # %bb.0: # %entry
; X86-NEXT: vpxord {{\.LCPI.*}}{1to16}, %zmm0, %zmm0 ; X86-NEXT: vpxord {{\.LCPI[0-9]+_[0-9]+}}{1to16}, %zmm0, %zmm0
; X86-NEXT: vfmadd213ps {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2 ; X86-NEXT: vfmadd213ps {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: test_mm512_fnmadd_ps: ; X64-LABEL: test_mm512_fnmadd_ps:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: vpxord {{.*}}(%rip){1to16}, %zmm0, %zmm0 ; X64-NEXT: vpxord {{.*}}(%rip){1to16}, %zmm0, %zmm0
; X64-NEXT: vfmadd213ps {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2 ; X64-NEXT: vfmadd213ps {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2
; X64-NEXT: retq ; X64-NEXT: retq
▲ Show 20 Lines • Show All 156 Lines • ▼ Show 20 Linesentry:
%1 = bitcast i8 %__U to <8 x i1> %1 = bitcast i8 %__U to <8 x i1>
%2 = select <8 x i1> %1, <8 x double> %0, <8 x double> zeroinitializer %2 = select <8 x i1> %1, <8 x double> %0, <8 x double> zeroinitializer
ret <8 x double> %2 ret <8 x double> %2
} }
define <8 x double> @test_mm512_fmsubadd_round_pd(<8 x double> %__A, <8 x double> %__B, <8 x double> %__C) { define <8 x double> @test_mm512_fmsubadd_round_pd(<8 x double> %__A, <8 x double> %__B, <8 x double> %__C) {
; X86-LABEL: test_mm512_fmsubadd_round_pd: ; X86-LABEL: test_mm512_fmsubadd_round_pd:
; X86: # %bb.0: # %entry ; X86: # %bb.0: # %entry
; X86-NEXT: vpxorq {{\.LCPI.*}}{1to8}, %zmm2, %zmm2 ; X86-NEXT: vpxorq {{\.LCPI[0-9]+_[0-9]+}}{1to8}, %zmm2, %zmm2
; X86-NEXT: vfmaddsub213pd {rn-sae}, %zmm2, %zmm1, %zmm0 ; X86-NEXT: vfmaddsub213pd {rn-sae}, %zmm2, %zmm1, %zmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: test_mm512_fmsubadd_round_pd: ; X64-LABEL: test_mm512_fmsubadd_round_pd:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: vpxorq {{.*}}(%rip){1to8}, %zmm2, %zmm2 ; X64-NEXT: vpxorq {{.*}}(%rip){1to8}, %zmm2, %zmm2
; X64-NEXT: vfmaddsub213pd {rn-sae}, %zmm2, %zmm1, %zmm0 ; X64-NEXT: vfmaddsub213pd {rn-sae}, %zmm2, %zmm1, %zmm0
; X64-NEXT: retq ; X64-NEXT: retq
▲ Show 20 Lines • Show All 260 Lines • ▼ Show 20 Linesentry:
%1 = bitcast i16 %__U to <16 x i1> %1 = bitcast i16 %__U to <16 x i1>
%2 = select <16 x i1> %1, <16 x float> %0, <16 x float> zeroinitializer %2 = select <16 x i1> %1, <16 x float> %0, <16 x float> zeroinitializer
ret <16 x float> %2 ret <16 x float> %2
} }
define <16 x float> @test_mm512_fmsubadd_round_ps(<16 x float> %__A, <16 x float> %__B, <16 x float> %__C) { define <16 x float> @test_mm512_fmsubadd_round_ps(<16 x float> %__A, <16 x float> %__B, <16 x float> %__C) {
; X86-LABEL: test_mm512_fmsubadd_round_ps: ; X86-LABEL: test_mm512_fmsubadd_round_ps:
; X86: # %bb.0: # %entry ; X86: # %bb.0: # %entry
; X86-NEXT: vpxord {{\.LCPI.*}}{1to16}, %zmm2, %zmm2 ; X86-NEXT: vpxord {{\.LCPI[0-9]+_[0-9]+}}{1to16}, %zmm2, %zmm2
; X86-NEXT: vfmaddsub213ps {rn-sae}, %zmm2, %zmm1, %zmm0 ; X86-NEXT: vfmaddsub213ps {rn-sae}, %zmm2, %zmm1, %zmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: test_mm512_fmsubadd_round_ps: ; X64-LABEL: test_mm512_fmsubadd_round_ps:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: vpxord {{.*}}(%rip){1to16}, %zmm2, %zmm2 ; X64-NEXT: vpxord {{.*}}(%rip){1to16}, %zmm2, %zmm2
; X64-NEXT: vfmaddsub213ps {rn-sae}, %zmm2, %zmm1, %zmm0 ; X64-NEXT: vfmaddsub213ps {rn-sae}, %zmm2, %zmm1, %zmm0
; X64-NEXT: retq ; X64-NEXT: retq
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llvm/test/CodeGen/X86/avx512-intrinsics.ll

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Show First 20 Lines • Show All 7,112 Lines • ▼ Show 20 Lines
; X64-NEXT: vmovdqa64 {{.*#+}} zmm1 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4294967295] ; X64-NEXT: vmovdqa64 {{.*#+}} zmm1 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4294967295]
; X64-NEXT: vpsllvd {{.*}}(%rip), %zmm1, %zmm1 ; X64-NEXT: vpsllvd {{.*}}(%rip), %zmm1, %zmm1
; X64-NEXT: vpaddd %zmm1, %zmm0, %zmm0 ; X64-NEXT: vpaddd %zmm1, %zmm0, %zmm0
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-LABEL: test_x86_avx512_psllv_d_512_const: ; X86-LABEL: test_x86_avx512_psllv_d_512_const:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vmovdqa64 {{.*#+}} zmm0 = [2,9,0,4294967295,3,7,4294967295,0,4,5,4294967294,0,5,3,4294967293,0] ; X86-NEXT: vmovdqa64 {{.*#+}} zmm0 = [2,9,0,4294967295,3,7,4294967295,0,4,5,4294967294,0,5,3,4294967293,0]
; X86-NEXT: vpsllvd {{\.LCPI.*}}, %zmm0, %zmm0 ; X86-NEXT: vpsllvd {{\.LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0
; X86-NEXT: vmovdqa64 {{.*#+}} zmm1 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4294967295] ; X86-NEXT: vmovdqa64 {{.*#+}} zmm1 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4294967295]
; X86-NEXT: vpsllvd {{\.LCPI.*}}, %zmm1, %zmm1 ; X86-NEXT: vpsllvd {{\.LCPI[0-9]+_[0-9]+}}, %zmm1, %zmm1
; X86-NEXT: vpaddd %zmm1, %zmm0, %zmm0 ; X86-NEXT: vpaddd %zmm1, %zmm0, %zmm0
; X86-NEXT: retl ; X86-NEXT: retl
%res0 = call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> <i32 2, i32 9, i32 0, i32 -1, i32 3, i32 7, i32 -1, i32 0, i32 4, i32 5, i32 -2, i32 0, i32 5, i32 3, i32 -3, i32 0>, <16 x i32> <i32 1, i32 0, i32 33, i32 -1,i32 2, i32 0, i32 34, i32 -2, i32 3, i32 0, i32 35, i32 -1, i32 4, i32 0, i32 36, i32 -3>) %res0 = call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> <i32 2, i32 9, i32 0, i32 -1, i32 3, i32 7, i32 -1, i32 0, i32 4, i32 5, i32 -2, i32 0, i32 5, i32 3, i32 -3, i32 0>, <16 x i32> <i32 1, i32 0, i32 33, i32 -1,i32 2, i32 0, i32 34, i32 -2, i32 3, i32 0, i32 35, i32 -1, i32 4, i32 0, i32 36, i32 -3>)
%res1 = call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> <i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 -1>, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 -1>) %res1 = call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> <i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 -1>, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 -1>)
%res2 = add <16 x i32> %res0, %res1 %res2 = add <16 x i32> %res0, %res1
ret <16 x i32> %res2 ret <16 x i32> %res2
} }
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; X64-NEXT: vmovdqa64 {{.*#+}} zmm1 = [4,4,4,4,4,4,4,18446744073709551615] ; X64-NEXT: vmovdqa64 {{.*#+}} zmm1 = [4,4,4,4,4,4,4,18446744073709551615]
; X64-NEXT: vpsllvq {{.*}}(%rip), %zmm1, %zmm1 ; X64-NEXT: vpsllvq {{.*}}(%rip), %zmm1, %zmm1
; X64-NEXT: vpaddq %zmm1, %zmm0, %zmm0 ; X64-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-LABEL: test_x86_avx512_psllv_q_512_const: ; X86-LABEL: test_x86_avx512_psllv_q_512_const:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vmovdqa64 {{.*#+}} zmm0 = [2,0,9,0,0,0,4294967295,4294967295,3,0,7,0,4294967295,4294967295,0,0] ; X86-NEXT: vmovdqa64 {{.*#+}} zmm0 = [2,0,9,0,0,0,4294967295,4294967295,3,0,7,0,4294967295,4294967295,0,0]
; X86-NEXT: vpsllvq {{\.LCPI.*}}, %zmm0, %zmm0 ; X86-NEXT: vpsllvq {{\.LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0
; X86-NEXT: vmovdqa64 {{.*#+}} zmm1 = [4,0,4,0,4,0,4,0,4,0,4,0,4,0,4294967295,4294967295] ; X86-NEXT: vmovdqa64 {{.*#+}} zmm1 = [4,0,4,0,4,0,4,0,4,0,4,0,4,0,4294967295,4294967295]
; X86-NEXT: vpsllvq {{\.LCPI.*}}, %zmm1, %zmm1 ; X86-NEXT: vpsllvq {{\.LCPI[0-9]+_[0-9]+}}, %zmm1, %zmm1
; X86-NEXT: vpaddq %zmm1, %zmm0, %zmm0 ; X86-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; X86-NEXT: retl ; X86-NEXT: retl
%res0 = call <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64> <i64 2, i64 9, i64 0, i64 -1, i64 3, i64 7, i64 -1, i64 0>, <8 x i64> <i64 1, i64 0, i64 33, i64 -1,i64 2, i64 0, i64 34, i64 -2>) %res0 = call <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64> <i64 2, i64 9, i64 0, i64 -1, i64 3, i64 7, i64 -1, i64 0>, <8 x i64> <i64 1, i64 0, i64 33, i64 -1,i64 2, i64 0, i64 34, i64 -2>)
%res1 = call <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64> <i64 4, i64 4, i64 4, i64 4, i64 4, i64 4, i64 4, i64 -1>, <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 -1>) %res1 = call <8 x i64> @llvm.x86.avx512.psllv.q.512(<8 x i64> <i64 4, i64 4, i64 4, i64 4, i64 4, i64 4, i64 4, i64 -1>, <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 -1>)
%res2 = add <8 x i64> %res0, %res1 %res2 = add <8 x i64> %res0, %res1
ret <8 x i64> %res2 ret <8 x i64> %res2
} }
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; X64-NEXT: vmovdqa64 {{.*#+}} zmm1 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4294967295] ; X64-NEXT: vmovdqa64 {{.*#+}} zmm1 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4294967295]
; X64-NEXT: vpsrlvd {{.*}}(%rip), %zmm1, %zmm1 ; X64-NEXT: vpsrlvd {{.*}}(%rip), %zmm1, %zmm1
; X64-NEXT: vpaddd %zmm1, %zmm0, %zmm0 ; X64-NEXT: vpaddd %zmm1, %zmm0, %zmm0
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-LABEL: test_x86_avx512_psrlv_d_512_const: ; X86-LABEL: test_x86_avx512_psrlv_d_512_const:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vmovdqa64 {{.*#+}} zmm0 = [2,9,0,4294967295,3,7,4294967295,0,4,5,4294967294,0,5,3,4294967293,0] ; X86-NEXT: vmovdqa64 {{.*#+}} zmm0 = [2,9,0,4294967295,3,7,4294967295,0,4,5,4294967294,0,5,3,4294967293,0]
; X86-NEXT: vpsrlvd {{\.LCPI.*}}, %zmm0, %zmm0 ; X86-NEXT: vpsrlvd {{\.LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0
; X86-NEXT: vmovdqa64 {{.*#+}} zmm1 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4294967295] ; X86-NEXT: vmovdqa64 {{.*#+}} zmm1 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4294967295]
; X86-NEXT: vpsrlvd {{\.LCPI.*}}, %zmm1, %zmm1 ; X86-NEXT: vpsrlvd {{\.LCPI[0-9]+_[0-9]+}}, %zmm1, %zmm1
; X86-NEXT: vpaddd %zmm1, %zmm0, %zmm0 ; X86-NEXT: vpaddd %zmm1, %zmm0, %zmm0
; X86-NEXT: retl ; X86-NEXT: retl
%res0 = call <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32> <i32 2, i32 9, i32 0, i32 -1, i32 3, i32 7, i32 -1, i32 0, i32 4, i32 5, i32 -2, i32 0, i32 5, i32 3, i32 -3, i32 0>, <16 x i32> <i32 1, i32 0, i32 33, i32 -1,i32 2, i32 0, i32 34, i32 -2, i32 3, i32 0, i32 35, i32 -1, i32 4, i32 0, i32 36, i32 -3>) %res0 = call <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32> <i32 2, i32 9, i32 0, i32 -1, i32 3, i32 7, i32 -1, i32 0, i32 4, i32 5, i32 -2, i32 0, i32 5, i32 3, i32 -3, i32 0>, <16 x i32> <i32 1, i32 0, i32 33, i32 -1,i32 2, i32 0, i32 34, i32 -2, i32 3, i32 0, i32 35, i32 -1, i32 4, i32 0, i32 36, i32 -3>)
%res1 = call <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32> <i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 -1>, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 -1 >) %res1 = call <16 x i32> @llvm.x86.avx512.psrlv.d.512(<16 x i32> <i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4, i32 -1>, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 -1 >)
%res2 = add <16 x i32> %res0, %res1 %res2 = add <16 x i32> %res0, %res1
ret <16 x i32> %res2 ret <16 x i32> %res2
} }
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; X64-NEXT: vmovdqa64 {{.*#+}} zmm1 = [4,4,4,4,4,4,4,18446744073709551615] ; X64-NEXT: vmovdqa64 {{.*#+}} zmm1 = [4,4,4,4,4,4,4,18446744073709551615]
; X64-NEXT: vpsrlvq {{.*}}(%rip), %zmm1, %zmm1 ; X64-NEXT: vpsrlvq {{.*}}(%rip), %zmm1, %zmm1
; X64-NEXT: vpaddq %zmm1, %zmm0, %zmm0 ; X64-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-LABEL: test_x86_avx512_psrlv_q_512_const: ; X86-LABEL: test_x86_avx512_psrlv_q_512_const:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vmovdqa64 {{.*#+}} zmm0 = [2,0,9,0,0,0,4294967295,4294967295,3,0,7,0,4294967295,4294967295,0,0] ; X86-NEXT: vmovdqa64 {{.*#+}} zmm0 = [2,0,9,0,0,0,4294967295,4294967295,3,0,7,0,4294967295,4294967295,0,0]
; X86-NEXT: vpsrlvq {{\.LCPI.*}}, %zmm0, %zmm0 ; X86-NEXT: vpsrlvq {{\.LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0
; X86-NEXT: vmovdqa64 {{.*#+}} zmm1 = [4,0,4,0,4,0,4,0,4,0,4,0,4,0,4294967295,4294967295] ; X86-NEXT: vmovdqa64 {{.*#+}} zmm1 = [4,0,4,0,4,0,4,0,4,0,4,0,4,0,4294967295,4294967295]
; X86-NEXT: vpsrlvq {{\.LCPI.*}}, %zmm1, %zmm1 ; X86-NEXT: vpsrlvq {{\.LCPI[0-9]+_[0-9]+}}, %zmm1, %zmm1
; X86-NEXT: vpaddq %zmm1, %zmm0, %zmm0 ; X86-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; X86-NEXT: retl ; X86-NEXT: retl
%res0 = call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> <i64 2, i64 9, i64 0, i64 -1, i64 3, i64 7, i64 -1, i64 0>, <8 x i64> <i64 1, i64 0, i64 33, i64 -1,i64 2, i64 0, i64 34, i64 -2>) %res0 = call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> <i64 2, i64 9, i64 0, i64 -1, i64 3, i64 7, i64 -1, i64 0>, <8 x i64> <i64 1, i64 0, i64 33, i64 -1,i64 2, i64 0, i64 34, i64 -2>)
%res1 = call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> <i64 4, i64 4, i64 4, i64 4, i64 4, i64 4, i64 4, i64 -1>, <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 -1>) %res1 = call <8 x i64> @llvm.x86.avx512.psrlv.q.512(<8 x i64> <i64 4, i64 4, i64 4, i64 4, i64 4, i64 4, i64 4, i64 -1>, <8 x i64> <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 -1>)
%res2 = add <8 x i64> %res0, %res1 %res2 = add <8 x i64> %res0, %res1
ret <8 x i64> %res2 ret <8 x i64> %res2
} }
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llvm/test/CodeGen/X86/avx512bw-intrinsics.ll

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declare <32 x i16> @llvm.x86.avx512.psrlv.w.512(<32 x i16>, <32 x i16>) nounwind readnone declare <32 x i16> @llvm.x86.avx512.psrlv.w.512(<32 x i16>, <32 x i16>) nounwind readnone
define <32 x i16> @test_x86_avx512_psrlv_w_512_const() optsize { define <32 x i16> @test_x86_avx512_psrlv_w_512_const() optsize {
; X86-LABEL: test_x86_avx512_psrlv_w_512_const: ; X86-LABEL: test_x86_avx512_psrlv_w_512_const:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vmovdqa64 {{.*#+}} zmm0 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,65535] ; X86-NEXT: vmovdqa64 {{.*#+}} zmm0 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,65535]
; X86-NEXT: # encoding: [0x62,0xf1,0xfd,0x48,0x6f,0x05,A,A,A,A] ; X86-NEXT: # encoding: [0x62,0xf1,0xfd,0x48,0x6f,0x05,A,A,A,A]
; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-NEXT: vpsrlvw {{\.LCPI.*}}, %zmm0, %zmm0 # encoding: [0x62,0xf2,0xfd,0x48,0x10,0x05,A,A,A,A] ; X86-NEXT: vpsrlvw {{\.LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0 # encoding: [0x62,0xf2,0xfd,0x48,0x10,0x05,A,A,A,A]
; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-NEXT: retl # encoding: [0xc3] ; X86-NEXT: retl # encoding: [0xc3]
; ;
; X64-LABEL: test_x86_avx512_psrlv_w_512_const: ; X64-LABEL: test_x86_avx512_psrlv_w_512_const:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vmovdqa64 {{.*#+}} zmm0 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,65535] ; X64-NEXT: vmovdqa64 {{.*#+}} zmm0 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,65535]
; X64-NEXT: # encoding: [0x62,0xf1,0xfd,0x48,0x6f,0x05,A,A,A,A] ; X64-NEXT: # encoding: [0x62,0xf1,0xfd,0x48,0x6f,0x05,A,A,A,A]
; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-NEXT: vpsrlvw {{.*}}(%rip), %zmm0, %zmm0 # encoding: [0x62,0xf2,0xfd,0x48,0x10,0x05,A,A,A,A] ; X64-NEXT: vpsrlvw {{.*}}(%rip), %zmm0, %zmm0 # encoding: [0x62,0xf2,0xfd,0x48,0x10,0x05,A,A,A,A]
; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-NEXT: retq # encoding: [0xc3] ; X64-NEXT: retq # encoding: [0xc3]
%res1 = call <32 x i16> @llvm.x86.avx512.psrlv.w.512(<32 x i16> <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 -1>, <32 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 -1>) %res1 = call <32 x i16> @llvm.x86.avx512.psrlv.w.512(<32 x i16> <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 -1>, <32 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 -1>)
ret <32 x i16> %res1 ret <32 x i16> %res1
} }
define <32 x i16>@test_int_x86_avx512_psrlv32hi(<32 x i16> %x0, <32 x i16> %x1) { define <32 x i16>@test_int_x86_avx512_psrlv32hi(<32 x i16> %x0, <32 x i16> %x1) {
; CHECK-LABEL: test_int_x86_avx512_psrlv32hi: ; CHECK-LABEL: test_int_x86_avx512_psrlv32hi:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
▲ Show 20 Lines • Show All 90 Lines • ▼ Show 20 Lines; X64-NEXT: retq # encoding: [0xc3]
ret <32 x i16> %3 ret <32 x i16> %3
} }
define <32 x i16>@test_int_x86_avx512_mask_psrav32_hi_const(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3) { define <32 x i16>@test_int_x86_avx512_mask_psrav32_hi_const(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3) {
; X86-LABEL: test_int_x86_avx512_mask_psrav32_hi_const: ; X86-LABEL: test_int_x86_avx512_mask_psrav32_hi_const:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vmovdqa64 {{.*#+}} zmm0 = [2,9,65524,23,65510,37,65496,51,2,9,65524,23,65510,37,65496,51,2,9,65524,23,65510,37,65496,51,2,9,65524,23,65510,37,65496,51] ; X86-NEXT: vmovdqa64 {{.*#+}} zmm0 = [2,9,65524,23,65510,37,65496,51,2,9,65524,23,65510,37,65496,51,2,9,65524,23,65510,37,65496,51,2,9,65524,23,65510,37,65496,51]
; X86-NEXT: # encoding: [0x62,0xf1,0xfd,0x48,0x6f,0x05,A,A,A,A] ; X86-NEXT: # encoding: [0x62,0xf1,0xfd,0x48,0x6f,0x05,A,A,A,A]
; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-NEXT: vpsravw {{\.LCPI.*}}, %zmm0, %zmm0 # encoding: [0x62,0xf2,0xfd,0x48,0x11,0x05,A,A,A,A] ; X86-NEXT: vpsravw {{\.LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0 # encoding: [0x62,0xf2,0xfd,0x48,0x11,0x05,A,A,A,A]
; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-NEXT: retl # encoding: [0xc3] ; X86-NEXT: retl # encoding: [0xc3]
; ;
; X64-LABEL: test_int_x86_avx512_mask_psrav32_hi_const: ; X64-LABEL: test_int_x86_avx512_mask_psrav32_hi_const:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vmovdqa64 {{.*#+}} zmm0 = [2,9,65524,23,65510,37,65496,51,2,9,65524,23,65510,37,65496,51,2,9,65524,23,65510,37,65496,51,2,9,65524,23,65510,37,65496,51] ; X64-NEXT: vmovdqa64 {{.*#+}} zmm0 = [2,9,65524,23,65510,37,65496,51,2,9,65524,23,65510,37,65496,51,2,9,65524,23,65510,37,65496,51,2,9,65524,23,65510,37,65496,51]
; X64-NEXT: # encoding: [0x62,0xf1,0xfd,0x48,0x6f,0x05,A,A,A,A] ; X64-NEXT: # encoding: [0x62,0xf1,0xfd,0x48,0x6f,0x05,A,A,A,A]
; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-NEXT: vpsravw {{.*}}(%rip), %zmm0, %zmm0 # encoding: [0x62,0xf2,0xfd,0x48,0x11,0x05,A,A,A,A] ; X64-NEXT: vpsravw {{.*}}(%rip), %zmm0, %zmm0 # encoding: [0x62,0xf2,0xfd,0x48,0x11,0x05,A,A,A,A]
; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-NEXT: retq # encoding: [0xc3] ; X64-NEXT: retq # encoding: [0xc3]
%1 = call <32 x i16> @llvm.x86.avx512.psrav.w.512(<32 x i16> <i16 2, i16 9, i16 -12, i16 23, i16 -26, i16 37, i16 -40, i16 51, i16 2, i16 9, i16 -12, i16 23, i16 -26, i16 37, i16 -40, i16 51, i16 2, i16 9, i16 -12, i16 23, i16 -26, i16 37, i16 -40, i16 51, i16 2, i16 9, i16 -12, i16 23, i16 -26, i16 37, i16 -40, i16 51>, <32 x i16> <i16 1, i16 10, i16 35, i16 52, i16 69, i16 9, i16 16, i16 49, i16 1, i16 10, i16 35, i16 52, i16 69, i16 9, i16 16, i16 49, i16 1, i16 10, i16 35, i16 52, i16 69, i16 9, i16 16, i16 49, i16 1, i16 10, i16 35, i16 52, i16 69, i16 9, i16 16, i16 49>) %1 = call <32 x i16> @llvm.x86.avx512.psrav.w.512(<32 x i16> <i16 2, i16 9, i16 -12, i16 23, i16 -26, i16 37, i16 -40, i16 51, i16 2, i16 9, i16 -12, i16 23, i16 -26, i16 37, i16 -40, i16 51, i16 2, i16 9, i16 -12, i16 23, i16 -26, i16 37, i16 -40, i16 51, i16 2, i16 9, i16 -12, i16 23, i16 -26, i16 37, i16 -40, i16 51>, <32 x i16> <i16 1, i16 10, i16 35, i16 52, i16 69, i16 9, i16 16, i16 49, i16 1, i16 10, i16 35, i16 52, i16 69, i16 9, i16 16, i16 49, i16 1, i16 10, i16 35, i16 52, i16 69, i16 9, i16 16, i16 49, i16 1, i16 10, i16 35, i16 52, i16 69, i16 9, i16 16, i16 49>)
ret <32 x i16> %1 ret <32 x i16> %1
} }
define <32 x i16>@test_int_x86_avx512_psllv32hi(<32 x i16> %x0, <32 x i16> %x1) { define <32 x i16>@test_int_x86_avx512_psllv32hi(<32 x i16> %x0, <32 x i16> %x1) {
; CHECK-LABEL: test_int_x86_avx512_psllv32hi: ; CHECK-LABEL: test_int_x86_avx512_psllv32hi:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
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declare <32 x i16> @llvm.x86.avx512.psll.w.512(<32 x i16>, <8 x i16>) nounwind readnone declare <32 x i16> @llvm.x86.avx512.psll.w.512(<32 x i16>, <8 x i16>) nounwind readnone
define <32 x i16> @test_x86_avx512_psllv_w_512_const() optsize { define <32 x i16> @test_x86_avx512_psllv_w_512_const() optsize {
; X86-LABEL: test_x86_avx512_psllv_w_512_const: ; X86-LABEL: test_x86_avx512_psllv_w_512_const:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vmovdqa64 {{.*#+}} zmm0 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,65535] ; X86-NEXT: vmovdqa64 {{.*#+}} zmm0 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,65535]
; X86-NEXT: # encoding: [0x62,0xf1,0xfd,0x48,0x6f,0x05,A,A,A,A] ; X86-NEXT: # encoding: [0x62,0xf1,0xfd,0x48,0x6f,0x05,A,A,A,A]
; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-NEXT: vpsllvw {{\.LCPI.*}}, %zmm0, %zmm0 # encoding: [0x62,0xf2,0xfd,0x48,0x12,0x05,A,A,A,A] ; X86-NEXT: vpsllvw {{\.LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0 # encoding: [0x62,0xf2,0xfd,0x48,0x12,0x05,A,A,A,A]
; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-NEXT: retl # encoding: [0xc3] ; X86-NEXT: retl # encoding: [0xc3]
; ;
; X64-LABEL: test_x86_avx512_psllv_w_512_const: ; X64-LABEL: test_x86_avx512_psllv_w_512_const:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vmovdqa64 {{.*#+}} zmm0 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,65535] ; X64-NEXT: vmovdqa64 {{.*#+}} zmm0 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,65535]
; X64-NEXT: # encoding: [0x62,0xf1,0xfd,0x48,0x6f,0x05,A,A,A,A] ; X64-NEXT: # encoding: [0x62,0xf1,0xfd,0x48,0x6f,0x05,A,A,A,A]
; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-NEXT: vpsllvw {{.*}}(%rip), %zmm0, %zmm0 # encoding: [0x62,0xf2,0xfd,0x48,0x12,0x05,A,A,A,A] ; X64-NEXT: vpsllvw {{.*}}(%rip), %zmm0, %zmm0 # encoding: [0x62,0xf2,0xfd,0x48,0x12,0x05,A,A,A,A]
; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-NEXT: retq # encoding: [0xc3] ; X64-NEXT: retq # encoding: [0xc3]
%res1 = call <32 x i16> @llvm.x86.avx512.psllv.w.512(<32 x i16> <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 -1>, <32 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 -1>) %res1 = call <32 x i16> @llvm.x86.avx512.psllv.w.512(<32 x i16> <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 -1>, <32 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 -1>)
ret <32 x i16> %res1 ret <32 x i16> %res1
} }
declare <32 x i16> @llvm.x86.avx512.psllv.w.512(<32 x i16>, <32 x i16>) nounwind readnone declare <32 x i16> @llvm.x86.avx512.psllv.w.512(<32 x i16>, <32 x i16>) nounwind readnone
define <32 x i16> @test_x86_avx512_pslli_w_512(<32 x i16> %a0) { define <32 x i16> @test_x86_avx512_pslli_w_512(<32 x i16> %a0) {
; CHECK-LABEL: test_x86_avx512_pslli_w_512: ; CHECK-LABEL: test_x86_avx512_pslli_w_512:
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llvm/test/CodeGen/X86/avx512bwvl-intrinsics.ll

Show First 20 Lines • Show All 2,147 Lines • ▼ Show 20 Lines; X64-NEXT: retq # encoding: [0xc3]
%res = call <8 x i16> @llvm.x86.avx512.mask.psrlv8.hi(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> zeroinitializer, i8 %x3) %res = call <8 x i16> @llvm.x86.avx512.mask.psrlv8.hi(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> zeroinitializer, i8 %x3)
ret <8 x i16> %res ret <8 x i16> %res
} }
define <8 x i16> @test_int_x86_avx512_psrlv_w_128_const() optsize { define <8 x i16> @test_int_x86_avx512_psrlv_w_128_const() optsize {
; X86-LABEL: test_int_x86_avx512_psrlv_w_128_const: ; X86-LABEL: test_int_x86_avx512_psrlv_w_128_const:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vmovdqa {{\.LCPI.*}}, %xmm0 # EVEX TO VEX Compression xmm0 = [4,4,4,4,4,4,4,65535] ; X86-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %xmm0 # EVEX TO VEX Compression xmm0 = [4,4,4,4,4,4,4,65535]
; X86-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A] ; X86-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
; X86-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-NEXT: vpsrlvw {{\.LCPI.*}}, %xmm0, %xmm0 # encoding: [0x62,0xf2,0xfd,0x08,0x10,0x05,A,A,A,A] ; X86-NEXT: vpsrlvw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # encoding: [0x62,0xf2,0xfd,0x08,0x10,0x05,A,A,A,A]
; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-NEXT: retl # encoding: [0xc3] ; X86-NEXT: retl # encoding: [0xc3]
; ;
; X64-LABEL: test_int_x86_avx512_psrlv_w_128_const: ; X64-LABEL: test_int_x86_avx512_psrlv_w_128_const:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vmovdqa {{.*}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [4,4,4,4,4,4,4,65535] ; X64-NEXT: vmovdqa {{.*}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [4,4,4,4,4,4,4,65535]
; X64-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A] ; X64-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
; X64-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-NEXT: vpsrlvw {{.*}}(%rip), %xmm0, %xmm0 # encoding: [0x62,0xf2,0xfd,0x08,0x10,0x05,A,A,A,A] ; X64-NEXT: vpsrlvw {{.*}}(%rip), %xmm0, %xmm0 # encoding: [0x62,0xf2,0xfd,0x08,0x10,0x05,A,A,A,A]
; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-NEXT: retq # encoding: [0xc3] ; X64-NEXT: retq # encoding: [0xc3]
%res = call <8 x i16> @llvm.x86.avx512.psrlv.w.128(<8 x i16> <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 -1>, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 -1>) %res = call <8 x i16> @llvm.x86.avx512.psrlv.w.128(<8 x i16> <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 -1>, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 -1>)
ret <8 x i16> %res ret <8 x i16> %res
} }
declare <8 x i16> @llvm.x86.avx512.psrlv.w.128(<8 x i16>, <8 x i16>) declare <8 x i16> @llvm.x86.avx512.psrlv.w.128(<8 x i16>, <8 x i16>)
define <16 x i16> @test_int_x86_avx512_psrlv_w_256_const() optsize { define <16 x i16> @test_int_x86_avx512_psrlv_w_256_const() optsize {
; X86-LABEL: test_int_x86_avx512_psrlv_w_256_const: ; X86-LABEL: test_int_x86_avx512_psrlv_w_256_const:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vmovdqa {{\.LCPI.*}}, %ymm0 # EVEX TO VEX Compression ymm0 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,65535] ; X86-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,65535]
; X86-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A] ; X86-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
; X86-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-NEXT: vpsrlvw {{\.LCPI.*}}, %ymm0, %ymm0 # encoding: [0x62,0xf2,0xfd,0x28,0x10,0x05,A,A,A,A] ; X86-NEXT: vpsrlvw {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # encoding: [0x62,0xf2,0xfd,0x28,0x10,0x05,A,A,A,A]
; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-NEXT: retl # encoding: [0xc3] ; X86-NEXT: retl # encoding: [0xc3]
; ;
; X64-LABEL: test_int_x86_avx512_psrlv_w_256_const: ; X64-LABEL: test_int_x86_avx512_psrlv_w_256_const:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vmovdqa {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,65535] ; X64-NEXT: vmovdqa {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,65535]
; X64-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A] ; X64-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
; X64-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-NEXT: vpsrlvw {{.*}}(%rip), %ymm0, %ymm0 # encoding: [0x62,0xf2,0xfd,0x28,0x10,0x05,A,A,A,A] ; X64-NEXT: vpsrlvw {{.*}}(%rip), %ymm0, %ymm0 # encoding: [0x62,0xf2,0xfd,0x28,0x10,0x05,A,A,A,A]
; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-NEXT: retq # encoding: [0xc3] ; X64-NEXT: retq # encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx512.psrlv.w.256(<16 x i16> <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 -1>, <16 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 -1>) %res = call <16 x i16> @llvm.x86.avx512.psrlv.w.256(<16 x i16> <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 -1>, <16 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 -1>)
ret <16 x i16> %res ret <16 x i16> %res
} }
declare <16 x i16> @llvm.x86.avx512.psrlv.w.256(<16 x i16>, <16 x i16>) declare <16 x i16> @llvm.x86.avx512.psrlv.w.256(<16 x i16>, <16 x i16>)
declare <16 x i16> @llvm.x86.avx512.psrav.w.256(<16 x i16>, <16 x i16>) declare <16 x i16> @llvm.x86.avx512.psrav.w.256(<16 x i16>, <16 x i16>)
▲ Show 20 Lines • Show All 190 Lines • ▼ Show 20 Lines; X64-NEXT: retq # encoding: [0xc3]
%2 = bitcast i8 %x3 to <8 x i1> %2 = bitcast i8 %x3 to <8 x i1>
%3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> zeroinitializer %3 = select <8 x i1> %2, <8 x i16> %1, <8 x i16> zeroinitializer
ret <8 x i16> %3 ret <8 x i16> %3
} }
define <8 x i16> @test_int_x86_avx512_psllv_w_128_const() optsize { define <8 x i16> @test_int_x86_avx512_psllv_w_128_const() optsize {
; X86-LABEL: test_int_x86_avx512_psllv_w_128_const: ; X86-LABEL: test_int_x86_avx512_psllv_w_128_const:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vmovdqa {{\.LCPI.*}}, %xmm0 # EVEX TO VEX Compression xmm0 = [4,4,4,4,4,4,4,65535] ; X86-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %xmm0 # EVEX TO VEX Compression xmm0 = [4,4,4,4,4,4,4,65535]
; X86-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A] ; X86-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
; X86-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-NEXT: vpsllvw {{\.LCPI.*}}, %xmm0, %xmm0 # encoding: [0x62,0xf2,0xfd,0x08,0x12,0x05,A,A,A,A] ; X86-NEXT: vpsllvw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # encoding: [0x62,0xf2,0xfd,0x08,0x12,0x05,A,A,A,A]
; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-NEXT: retl # encoding: [0xc3] ; X86-NEXT: retl # encoding: [0xc3]
; ;
; X64-LABEL: test_int_x86_avx512_psllv_w_128_const: ; X64-LABEL: test_int_x86_avx512_psllv_w_128_const:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vmovdqa {{.*}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [4,4,4,4,4,4,4,65535] ; X64-NEXT: vmovdqa {{.*}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [4,4,4,4,4,4,4,65535]
; X64-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A] ; X64-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
; X64-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-NEXT: vpsllvw {{.*}}(%rip), %xmm0, %xmm0 # encoding: [0x62,0xf2,0xfd,0x08,0x12,0x05,A,A,A,A] ; X64-NEXT: vpsllvw {{.*}}(%rip), %xmm0, %xmm0 # encoding: [0x62,0xf2,0xfd,0x08,0x12,0x05,A,A,A,A]
; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-NEXT: retq # encoding: [0xc3] ; X64-NEXT: retq # encoding: [0xc3]
%res = call <8 x i16> @llvm.x86.avx512.psllv.w.128(<8 x i16> <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 -1>, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 -1>) %res = call <8 x i16> @llvm.x86.avx512.psllv.w.128(<8 x i16> <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 -1>, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 -1>)
ret <8 x i16> %res ret <8 x i16> %res
} }
declare <8 x i16> @llvm.x86.avx512.psllv.w.128(<8 x i16>, <8 x i16>) declare <8 x i16> @llvm.x86.avx512.psllv.w.128(<8 x i16>, <8 x i16>)
define <16 x i16> @test_int_x86_avx512_psllv_w_256_const() optsize { define <16 x i16> @test_int_x86_avx512_psllv_w_256_const() optsize {
; X86-LABEL: test_int_x86_avx512_psllv_w_256_const: ; X86-LABEL: test_int_x86_avx512_psllv_w_256_const:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vmovdqa {{\.LCPI.*}}, %ymm0 # EVEX TO VEX Compression ymm0 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,65535] ; X86-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,65535]
; X86-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A] ; X86-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
; X86-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-NEXT: vpsllvw {{\.LCPI.*}}, %ymm0, %ymm0 # encoding: [0x62,0xf2,0xfd,0x28,0x12,0x05,A,A,A,A] ; X86-NEXT: vpsllvw {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # encoding: [0x62,0xf2,0xfd,0x28,0x12,0x05,A,A,A,A]
; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-NEXT: retl # encoding: [0xc3] ; X86-NEXT: retl # encoding: [0xc3]
; ;
; X64-LABEL: test_int_x86_avx512_psllv_w_256_const: ; X64-LABEL: test_int_x86_avx512_psllv_w_256_const:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vmovdqa {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,65535] ; X64-NEXT: vmovdqa {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,65535]
; X64-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A] ; X64-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
; X64-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-NEXT: vpsllvw {{.*}}(%rip), %ymm0, %ymm0 # encoding: [0x62,0xf2,0xfd,0x28,0x12,0x05,A,A,A,A] ; X64-NEXT: vpsllvw {{.*}}(%rip), %ymm0, %ymm0 # encoding: [0x62,0xf2,0xfd,0x28,0x12,0x05,A,A,A,A]
; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-NEXT: retq # encoding: [0xc3] ; X64-NEXT: retq # encoding: [0xc3]
%res = call <16 x i16> @llvm.x86.avx512.psllv.w.256(<16 x i16> <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 -1>, <16 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 -1>) %res = call <16 x i16> @llvm.x86.avx512.psllv.w.256(<16 x i16> <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 -1>, <16 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 -1>)
ret <16 x i16> %res ret <16 x i16> %res
} }
declare <16 x i16> @llvm.x86.avx512.psllv.w.256(<16 x i16>, <16 x i16>) declare <16 x i16> @llvm.x86.avx512.psllv.w.256(<16 x i16>, <16 x i16>)
▲ Show 20 Lines • Show All 100 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/avx512vbmi2-funnel-shifts.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512vbmi2 | FileCheck %s --check-prefixes=CHECK,X86 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512vbmi2 | FileCheck %s --check-prefixes=CHECK,X86
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vbmi2 -| FileCheck %s --check-prefixes=CHECK,X64 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vbmi2 -| FileCheck %s --check-prefixes=CHECK,X64
define <8 x i64> @avx512_funnel_shift_q_512(<8 x i64> %a0, <8 x i64> %a1) { define <8 x i64> @avx512_funnel_shift_q_512(<8 x i64> %a0, <8 x i64> %a1) {
; X86-LABEL: avx512_funnel_shift_q_512: ; X86-LABEL: avx512_funnel_shift_q_512:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vpshldvq {{\.LCPI.*}}, %zmm1, %zmm0 ; X86-NEXT: vpshldvq {{\.LCPI[0-9]+_[0-9]+}}, %zmm1, %zmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: avx512_funnel_shift_q_512: ; X64-LABEL: avx512_funnel_shift_q_512:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpshldvq {{.*}}(%rip), %zmm1, %zmm0 ; X64-NEXT: vpshldvq {{.*}}(%rip), %zmm1, %zmm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = shl <8 x i64> %a0, <i64 31, i64 33, i64 31, i64 33, i64 31, i64 33, i64 31, i64 33> %1 = shl <8 x i64> %a0, <i64 31, i64 33, i64 31, i64 33, i64 31, i64 33, i64 31, i64 33>
%2 = lshr <8 x i64> %a1, <i64 33, i64 31, i64 33, i64 31, i64 33, i64 31, i64 33, i64 31> %2 = lshr <8 x i64> %a1, <i64 33, i64 31, i64 33, i64 31, i64 33, i64 31, i64 33, i64 31>
Show All 10 Lines; CHECK-NEXT: ret{{[l|q]}}
%2 = lshr <8 x i64> %a1, <i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33> %2 = lshr <8 x i64> %a1, <i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33, i64 33>
%3 = or <8 x i64> %1, %2 %3 = or <8 x i64> %1, %2
ret <8 x i64> %3 ret <8 x i64> %3
} }
define <16 x i32> @avx512_funnel_shift_d_512(<16 x i32> %a0, <16 x i32> %a1) { define <16 x i32> @avx512_funnel_shift_d_512(<16 x i32> %a0, <16 x i32> %a1) {
; X86-LABEL: avx512_funnel_shift_d_512: ; X86-LABEL: avx512_funnel_shift_d_512:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vpshldvd {{\.LCPI.*}}, %zmm1, %zmm0 ; X86-NEXT: vpshldvd {{\.LCPI[0-9]+_[0-9]+}}, %zmm1, %zmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: avx512_funnel_shift_d_512: ; X64-LABEL: avx512_funnel_shift_d_512:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpshldvd {{.*}}(%rip), %zmm1, %zmm0 ; X64-NEXT: vpshldvd {{.*}}(%rip), %zmm1, %zmm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = shl <16 x i32> %a0, <i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17> %1 = shl <16 x i32> %a0, <i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17>
%2 = lshr <16 x i32> %a1, <i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15> %2 = lshr <16 x i32> %a1, <i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15>
Show All 10 Lines; CHECK-NEXT: ret{{[l|q]}}
%2 = lshr <16 x i32> %a1, <i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17> %2 = lshr <16 x i32> %a1, <i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17>
%3 = or <16 x i32> %1, %2 %3 = or <16 x i32> %1, %2
ret <16 x i32> %3 ret <16 x i32> %3
} }
define <32 x i16> @avx512_funnel_shift_w_512(<32 x i16> %a0, <32 x i16> %a1) { define <32 x i16> @avx512_funnel_shift_w_512(<32 x i16> %a0, <32 x i16> %a1) {
; X86-LABEL: avx512_funnel_shift_w_512: ; X86-LABEL: avx512_funnel_shift_w_512:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vpshldvw {{\.LCPI.*}}, %zmm1, %zmm0 ; X86-NEXT: vpshldvw {{\.LCPI[0-9]+_[0-9]+}}, %zmm1, %zmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: avx512_funnel_shift_w_512: ; X64-LABEL: avx512_funnel_shift_w_512:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpshldvw {{.*}}(%rip), %zmm1, %zmm0 ; X64-NEXT: vpshldvw {{.*}}(%rip), %zmm1, %zmm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = shl <32 x i16> %a0, <i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9> %1 = shl <32 x i16> %a0, <i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9>
%2 = lshr <32 x i16> %a1, <i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7> %2 = lshr <32 x i16> %a1, <i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7>
Show All 16 Lines

llvm/test/CodeGen/X86/avx512vbmi2vl-funnel-shifts.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512vbmi2,+avx512vl | FileCheck %s --check-prefixes=CHECK,X86 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512vbmi2,+avx512vl | FileCheck %s --check-prefixes=CHECK,X86
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vbmi2,+avx512vl -| FileCheck %s --check-prefixes=CHECK,X64 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vbmi2,+avx512vl -| FileCheck %s --check-prefixes=CHECK,X64
define <2 x i64> @avx512_funnel_shift_q_128(<2 x i64> %a0, <2 x i64> %a1) { define <2 x i64> @avx512_funnel_shift_q_128(<2 x i64> %a0, <2 x i64> %a1) {
; X86-LABEL: avx512_funnel_shift_q_128: ; X86-LABEL: avx512_funnel_shift_q_128:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vpshldvq {{\.LCPI.*}}, %xmm1, %xmm0 ; X86-NEXT: vpshldvq {{\.LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: avx512_funnel_shift_q_128: ; X64-LABEL: avx512_funnel_shift_q_128:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpshldvq {{.*}}(%rip), %xmm1, %xmm0 ; X64-NEXT: vpshldvq {{.*}}(%rip), %xmm1, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = shl <2 x i64> %a0, <i64 31, i64 33> %1 = shl <2 x i64> %a0, <i64 31, i64 33>
%2 = lshr <2 x i64> %a1, <i64 33, i64 31> %2 = lshr <2 x i64> %a1, <i64 33, i64 31>
%3 = or <2 x i64> %1, %2 %3 = or <2 x i64> %1, %2
ret <2 x i64> %3 ret <2 x i64> %3
} }
define <4 x i64> @avx512_funnel_shift_q_256(<4 x i64> %a0, <4 x i64> %a1) { define <4 x i64> @avx512_funnel_shift_q_256(<4 x i64> %a0, <4 x i64> %a1) {
; X86-LABEL: avx512_funnel_shift_q_256: ; X86-LABEL: avx512_funnel_shift_q_256:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vpshldvq {{\.LCPI.*}}, %ymm1, %ymm0 ; X86-NEXT: vpshldvq {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: avx512_funnel_shift_q_256: ; X64-LABEL: avx512_funnel_shift_q_256:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpshldvq {{.*}}(%rip), %ymm1, %ymm0 ; X64-NEXT: vpshldvq {{.*}}(%rip), %ymm1, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = shl <4 x i64> %a0, <i64 31, i64 33, i64 31, i64 33> %1 = shl <4 x i64> %a0, <i64 31, i64 33, i64 31, i64 33>
%2 = lshr <4 x i64> %a1, <i64 33, i64 31, i64 33, i64 31> %2 = lshr <4 x i64> %a1, <i64 33, i64 31, i64 33, i64 31>
Show All 21 Lines; CHECK-NEXT: ret{{[l|q]}}
%2 = lshr <4 x i64> %a1, <i64 33, i64 33, i64 33, i64 33> %2 = lshr <4 x i64> %a1, <i64 33, i64 33, i64 33, i64 33>
%3 = or <4 x i64> %1, %2 %3 = or <4 x i64> %1, %2
ret <4 x i64> %3 ret <4 x i64> %3
} }
define <4 x i32> @avx512_funnel_shift_d_128(<4 x i32> %a0, <4 x i32> %a1) { define <4 x i32> @avx512_funnel_shift_d_128(<4 x i32> %a0, <4 x i32> %a1) {
; X86-LABEL: avx512_funnel_shift_d_128: ; X86-LABEL: avx512_funnel_shift_d_128:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vpshldvd {{\.LCPI.*}}, %xmm1, %xmm0 ; X86-NEXT: vpshldvd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: avx512_funnel_shift_d_128: ; X64-LABEL: avx512_funnel_shift_d_128:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpshldvd {{.*}}(%rip), %xmm1, %xmm0 ; X64-NEXT: vpshldvd {{.*}}(%rip), %xmm1, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = shl <4 x i32> %a0, <i32 15, i32 17, i32 15, i32 17> %1 = shl <4 x i32> %a0, <i32 15, i32 17, i32 15, i32 17>
%2 = lshr <4 x i32> %a1, <i32 17, i32 15, i32 17, i32 15> %2 = lshr <4 x i32> %a1, <i32 17, i32 15, i32 17, i32 15>
%3 = or <4 x i32> %1, %2 %3 = or <4 x i32> %1, %2
ret <4 x i32> %3 ret <4 x i32> %3
} }
define <8 x i32> @avx512_funnel_shift_d_256(<8 x i32> %a0, <8 x i32> %a1) { define <8 x i32> @avx512_funnel_shift_d_256(<8 x i32> %a0, <8 x i32> %a1) {
; X86-LABEL: avx512_funnel_shift_d_256: ; X86-LABEL: avx512_funnel_shift_d_256:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vpshldvd {{\.LCPI.*}}, %ymm1, %ymm0 ; X86-NEXT: vpshldvd {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: avx512_funnel_shift_d_256: ; X64-LABEL: avx512_funnel_shift_d_256:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpshldvd {{.*}}(%rip), %ymm1, %ymm0 ; X64-NEXT: vpshldvd {{.*}}(%rip), %ymm1, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = shl <8 x i32> %a0, <i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17> %1 = shl <8 x i32> %a0, <i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17>
%2 = lshr <8 x i32> %a1, <i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15> %2 = lshr <8 x i32> %a1, <i32 17, i32 15, i32 17, i32 15, i32 17, i32 15, i32 17, i32 15>
Show All 21 Lines; CHECK-NEXT: ret{{[l|q]}}
%2 = lshr <8 x i32> %a1, <i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17> %2 = lshr <8 x i32> %a1, <i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17>
%3 = or <8 x i32> %1, %2 %3 = or <8 x i32> %1, %2
ret <8 x i32> %3 ret <8 x i32> %3
} }
define <8 x i16> @avx512_funnel_shift_w_128(<8 x i16> %a0, <8 x i16> %a1) { define <8 x i16> @avx512_funnel_shift_w_128(<8 x i16> %a0, <8 x i16> %a1) {
; X86-LABEL: avx512_funnel_shift_w_128: ; X86-LABEL: avx512_funnel_shift_w_128:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vpshldvw {{\.LCPI.*}}, %xmm1, %xmm0 ; X86-NEXT: vpshldvw {{\.LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: avx512_funnel_shift_w_128: ; X64-LABEL: avx512_funnel_shift_w_128:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpshldvw {{.*}}(%rip), %xmm1, %xmm0 ; X64-NEXT: vpshldvw {{.*}}(%rip), %xmm1, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = shl <8 x i16> %a0, <i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9> %1 = shl <8 x i16> %a0, <i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9>
%2 = lshr <8 x i16> %a1, <i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7> %2 = lshr <8 x i16> %a1, <i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7>
%3 = or <8 x i16> %1, %2 %3 = or <8 x i16> %1, %2
ret <8 x i16> %3 ret <8 x i16> %3
} }
define <16 x i16> @avx512_funnel_shift_w_256(<16 x i16> %a0, <16 x i16> %a1) { define <16 x i16> @avx512_funnel_shift_w_256(<16 x i16> %a0, <16 x i16> %a1) {
; X86-LABEL: avx512_funnel_shift_w_256: ; X86-LABEL: avx512_funnel_shift_w_256:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vpshldvw {{\.LCPI.*}}, %ymm1, %ymm0 ; X86-NEXT: vpshldvw {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: avx512_funnel_shift_w_256: ; X64-LABEL: avx512_funnel_shift_w_256:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpshldvw {{.*}}(%rip), %ymm1, %ymm0 ; X64-NEXT: vpshldvw {{.*}}(%rip), %ymm1, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = shl <16 x i16> %a0, <i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9> %1 = shl <16 x i16> %a0, <i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9>
%2 = lshr <16 x i16> %a1, <i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7> %2 = lshr <16 x i16> %a1, <i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7, i16 9, i16 7>
Show All 27 Lines

llvm/test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,899 Lines • ▼ Show 20 Linesentry:
ret i8 %4 ret i8 %4
} }
define <2 x i64> @test_mm_mask_set1_epi32(<2 x i64> %__O, i8 zeroext %__M) { define <2 x i64> @test_mm_mask_set1_epi32(<2 x i64> %__O, i8 zeroext %__M) {
; X86-LABEL: test_mm_mask_set1_epi32: ; X86-LABEL: test_mm_mask_set1_epi32:
; X86: # %bb.0: # %entry ; X86: # %bb.0: # %entry
; X86-NEXT: movb {{[0-9]+}}(%esp), %al ; X86-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-NEXT: kmovw %eax, %k1 ; X86-NEXT: kmovw %eax, %k1
; X86-NEXT: vpbroadcastd {{\.LCPI.*}}, %xmm0 {%k1} ; X86-NEXT: vpbroadcastd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0 {%k1}
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: test_mm_mask_set1_epi32: ; X64-LABEL: test_mm_mask_set1_epi32:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: kmovw %edi, %k1
; X64-NEXT: vpbroadcastd {{.*}}(%rip), %xmm0 {%k1} ; X64-NEXT: vpbroadcastd {{.*}}(%rip), %xmm0 {%k1}
; X64-NEXT: retq ; X64-NEXT: retq
entry: entry:
%0 = bitcast <2 x i64> %__O to <4 x i32> %0 = bitcast <2 x i64> %__O to <4 x i32>
%1 = bitcast i8 %__M to <8 x i1> %1 = bitcast i8 %__M to <8 x i1>
%extract.i = shufflevector <8 x i1> %1, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %extract.i = shufflevector <8 x i1> %1, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%2 = select <4 x i1> %extract.i, <4 x i32> <i32 5, i32 5, i32 5, i32 5>, <4 x i32> %0 %2 = select <4 x i1> %extract.i, <4 x i32> <i32 5, i32 5, i32 5, i32 5>, <4 x i32> %0
%3 = bitcast <4 x i32> %2 to <2 x i64> %3 = bitcast <4 x i32> %2 to <2 x i64>
ret <2 x i64> %3 ret <2 x i64> %3
} }
define <2 x i64> @test_mm_maskz_set1_epi32(i8 zeroext %__M) { define <2 x i64> @test_mm_maskz_set1_epi32(i8 zeroext %__M) {
; X86-LABEL: test_mm_maskz_set1_epi32: ; X86-LABEL: test_mm_maskz_set1_epi32:
; X86: # %bb.0: # %entry ; X86: # %bb.0: # %entry
; X86-NEXT: movb {{[0-9]+}}(%esp), %al ; X86-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-NEXT: kmovw %eax, %k1 ; X86-NEXT: kmovw %eax, %k1
; X86-NEXT: vpbroadcastd {{\.LCPI.*}}, %xmm0 {%k1} {z} ; X86-NEXT: vpbroadcastd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0 {%k1} {z}
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: test_mm_maskz_set1_epi32: ; X64-LABEL: test_mm_maskz_set1_epi32:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: kmovw %edi, %k1
; X64-NEXT: vpbroadcastd {{.*}}(%rip), %xmm0 {%k1} {z} ; X64-NEXT: vpbroadcastd {{.*}}(%rip), %xmm0 {%k1} {z}
; X64-NEXT: retq ; X64-NEXT: retq
entry: entry:
%0 = bitcast i8 %__M to <8 x i1> %0 = bitcast i8 %__M to <8 x i1>
%extract.i = shufflevector <8 x i1> %0, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %extract.i = shufflevector <8 x i1> %0, <8 x i1> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%1 = select <4 x i1> %extract.i, <4 x i32> <i32 5, i32 5, i32 5, i32 5>, <4 x i32> zeroinitializer %1 = select <4 x i1> %extract.i, <4 x i32> <i32 5, i32 5, i32 5, i32 5>, <4 x i32> zeroinitializer
%2 = bitcast <4 x i32> %1 to <2 x i64> %2 = bitcast <4 x i32> %1 to <2 x i64>
ret <2 x i64> %2 ret <2 x i64> %2
} }
define <4 x i64> @test_mm256_mask_set1_epi32(<4 x i64> %__O, i8 zeroext %__M) { define <4 x i64> @test_mm256_mask_set1_epi32(<4 x i64> %__O, i8 zeroext %__M) {
; X86-LABEL: test_mm256_mask_set1_epi32: ; X86-LABEL: test_mm256_mask_set1_epi32:
; X86: # %bb.0: # %entry ; X86: # %bb.0: # %entry
; X86-NEXT: movb {{[0-9]+}}(%esp), %al ; X86-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-NEXT: kmovw %eax, %k1 ; X86-NEXT: kmovw %eax, %k1
; X86-NEXT: vpbroadcastd {{\.LCPI.*}}, %ymm0 {%k1} ; X86-NEXT: vpbroadcastd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0 {%k1}
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: test_mm256_mask_set1_epi32: ; X64-LABEL: test_mm256_mask_set1_epi32:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: kmovw %edi, %k1
; X64-NEXT: vpbroadcastd {{.*}}(%rip), %ymm0 {%k1} ; X64-NEXT: vpbroadcastd {{.*}}(%rip), %ymm0 {%k1}
; X64-NEXT: retq ; X64-NEXT: retq
entry: entry:
%0 = bitcast <4 x i64> %__O to <8 x i32> %0 = bitcast <4 x i64> %__O to <8 x i32>
%1 = bitcast i8 %__M to <8 x i1> %1 = bitcast i8 %__M to <8 x i1>
%2 = select <8 x i1> %1, <8 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>, <8 x i32> %0 %2 = select <8 x i1> %1, <8 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>, <8 x i32> %0
%3 = bitcast <8 x i32> %2 to <4 x i64> %3 = bitcast <8 x i32> %2 to <4 x i64>
ret <4 x i64> %3 ret <4 x i64> %3
} }
define <4 x i64> @test_mm256_maskz_set1_epi32(i8 zeroext %__M) { define <4 x i64> @test_mm256_maskz_set1_epi32(i8 zeroext %__M) {
; X86-LABEL: test_mm256_maskz_set1_epi32: ; X86-LABEL: test_mm256_maskz_set1_epi32:
; X86: # %bb.0: # %entry ; X86: # %bb.0: # %entry
; X86-NEXT: movb {{[0-9]+}}(%esp), %al ; X86-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-NEXT: kmovw %eax, %k1 ; X86-NEXT: kmovw %eax, %k1
; X86-NEXT: vpbroadcastd {{\.LCPI.*}}, %ymm0 {%k1} {z} ; X86-NEXT: vpbroadcastd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0 {%k1} {z}
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: test_mm256_maskz_set1_epi32: ; X64-LABEL: test_mm256_maskz_set1_epi32:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: kmovw %edi, %k1
; X64-NEXT: vpbroadcastd {{.*}}(%rip), %ymm0 {%k1} {z} ; X64-NEXT: vpbroadcastd {{.*}}(%rip), %ymm0 {%k1} {z}
; X64-NEXT: retq ; X64-NEXT: retq
entry: entry:
▲ Show 20 Lines • Show All 5,680 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 7,315 Lines • ▼ Show 20 Lines
; X64-NEXT: retq # encoding: [0xc3] ; X64-NEXT: retq # encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx512.mask.psrav8.si(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> zeroinitializer, i8 %x3) %res = call <8 x i32> @llvm.x86.avx512.mask.psrav8.si(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> zeroinitializer, i8 %x3)
ret <8 x i32> %res ret <8 x i32> %res
} }
define <8 x i32>@test_int_x86_avx512_mask_psrav8_si_const() { define <8 x i32>@test_int_x86_avx512_mask_psrav8_si_const() {
; X86-LABEL: test_int_x86_avx512_mask_psrav8_si_const: ; X86-LABEL: test_int_x86_avx512_mask_psrav8_si_const:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vmovdqa {{\.LCPI.*}}, %ymm0 # EVEX TO VEX Compression ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51] ; X86-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %ymm0 # EVEX TO VEX Compression ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
; X86-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A] ; X86-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
; X86-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-NEXT: vpsravd {{\.LCPI.*}}, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A] ; X86-NEXT: vpsravd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
; X86-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-NEXT: retl # encoding: [0xc3] ; X86-NEXT: retl # encoding: [0xc3]
; ;
; X64-LABEL: test_int_x86_avx512_mask_psrav8_si_const: ; X64-LABEL: test_int_x86_avx512_mask_psrav8_si_const:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vmovdqa {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51] ; X64-NEXT: vmovdqa {{.*}}(%rip), %ymm0 # EVEX TO VEX Compression ymm0 = [2,9,4294967284,23,4294967270,37,4294967256,51]
; X64-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A] ; X64-NEXT: # encoding: [0xc5,0xfd,0x6f,0x05,A,A,A,A]
; X64-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-NEXT: vpsravd {{.*}}(%rip), %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A] ; X64-NEXT: vpsravd {{.*}}(%rip), %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x46,0x05,A,A,A,A]
; X64-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-NEXT: retq # encoding: [0xc3] ; X64-NEXT: retq # encoding: [0xc3]
%res = call <8 x i32> @llvm.x86.avx512.mask.psrav8.si(<8 x i32> <i32 2, i32 9, i32 -12, i32 23, i32 -26, i32 37, i32 -40, i32 51>, <8 x i32> <i32 1, i32 18, i32 35, i32 52, i32 69, i32 15, i32 32, i32 49>, <8 x i32> zeroinitializer, i8 -1) %res = call <8 x i32> @llvm.x86.avx512.mask.psrav8.si(<8 x i32> <i32 2, i32 9, i32 -12, i32 23, i32 -26, i32 37, i32 -40, i32 51>, <8 x i32> <i32 1, i32 18, i32 35, i32 52, i32 69, i32 15, i32 32, i32 49>, <8 x i32> zeroinitializer, i8 -1)
ret <8 x i32> %res ret <8 x i32> %res
} }
declare <2 x i64> @llvm.x86.avx512.mask.psllv2.di(<2 x i64>, <2 x i64>, <2 x i64>, i8) declare <2 x i64> @llvm.x86.avx512.mask.psllv2.di(<2 x i64>, <2 x i64>, <2 x i64>, i8)
define <2 x i64>@test_int_x86_avx512_psllv2_di(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2) { define <2 x i64>@test_int_x86_avx512_psllv2_di(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2) {
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; X64-NEXT: retq # encoding: [0xc3] ; X64-NEXT: retq # encoding: [0xc3]
%res = call <2 x i64> @llvm.x86.avx512.mask.psrav.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3) %res = call <2 x i64> @llvm.x86.avx512.mask.psrav.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> zeroinitializer, i8 %x3)
ret <2 x i64> %res ret <2 x i64> %res
} }
define <2 x i64>@test_int_x86_avx512_mask_psrav_q_128_const(i8 %x3) { define <2 x i64>@test_int_x86_avx512_mask_psrav_q_128_const(i8 %x3) {
; X86-LABEL: test_int_x86_avx512_mask_psrav_q_128_const: ; X86-LABEL: test_int_x86_avx512_mask_psrav_q_128_const:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vmovdqa {{\.LCPI.*}}, %xmm0 # EVEX TO VEX Compression xmm0 = [2,0,4294967287,4294967295] ; X86-NEXT: vmovdqa {{\.LCPI[0-9]+_[0-9]+}}, %xmm0 # EVEX TO VEX Compression xmm0 = [2,0,4294967287,4294967295]
; X86-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A] ; X86-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
; X86-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-NEXT: vpsravq {{\.LCPI.*}}, %xmm0, %xmm0 # encoding: [0x62,0xf2,0xfd,0x08,0x46,0x05,A,A,A,A] ; X86-NEXT: vpsravq {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0 # encoding: [0x62,0xf2,0xfd,0x08,0x46,0x05,A,A,A,A]
; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X86-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X86-NEXT: retl # encoding: [0xc3] ; X86-NEXT: retl # encoding: [0xc3]
; ;
; X64-LABEL: test_int_x86_avx512_mask_psrav_q_128_const: ; X64-LABEL: test_int_x86_avx512_mask_psrav_q_128_const:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vmovdqa {{.*}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [2,18446744073709551607] ; X64-NEXT: vmovdqa {{.*}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [2,18446744073709551607]
; X64-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A] ; X64-NEXT: # encoding: [0xc5,0xf9,0x6f,0x05,A,A,A,A]
; X64-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-NEXT: vpsravq {{.*}}(%rip), %xmm0, %xmm0 # encoding: [0x62,0xf2,0xfd,0x08,0x46,0x05,A,A,A,A] ; X64-NEXT: vpsravq {{.*}}(%rip), %xmm0, %xmm0 # encoding: [0x62,0xf2,0xfd,0x08,0x46,0x05,A,A,A,A]
; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-NEXT: # fixup A - offset: 6, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-NEXT: retq # encoding: [0xc3] ; X64-NEXT: retq # encoding: [0xc3]
%res = call <2 x i64> @llvm.x86.avx512.mask.psrav.q.128(<2 x i64> <i64 2, i64 -9>, <2 x i64> <i64 1, i64 90>, <2 x i64> zeroinitializer, i8 -1) %res = call <2 x i64> @llvm.x86.avx512.mask.psrav.q.128(<2 x i64> <i64 2, i64 -9>, <2 x i64> <i64 1, i64 90>, <2 x i64> zeroinitializer, i8 -1)
ret <2 x i64> %res ret <2 x i64> %res
} }
declare <4 x i64> @llvm.x86.avx512.mask.psrav.q.256(<4 x i64>, <4 x i64>, <4 x i64>, i8) declare <4 x i64> @llvm.x86.avx512.mask.psrav.q.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)
define <4 x i64>@test_int_x86_avx512_psrav_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2) { define <4 x i64>@test_int_x86_avx512_psrav_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2) {
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llvm/test/CodeGen/X86/bitreverse.ll

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; X64-NEXT: paddb %xmm1, %xmm1 ; X64-NEXT: paddb %xmm1, %xmm1
; X64-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-NEXT: pand {{.*}}(%rip), %xmm0
; X64-NEXT: psrlw $1, %xmm0 ; X64-NEXT: psrlw $1, %xmm0
; X64-NEXT: por %xmm1, %xmm0 ; X64-NEXT: por %xmm1, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86XOP-LABEL: test_bitreverse_v2i16: ; X86XOP-LABEL: test_bitreverse_v2i16:
; X86XOP: # %bb.0: ; X86XOP: # %bb.0:
; X86XOP-NEXT: vpperm {{\.LCPI.*}}, %xmm0, %xmm0, %xmm0 ; X86XOP-NEXT: vpperm {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0, %xmm0
; X86XOP-NEXT: retl ; X86XOP-NEXT: retl
%b = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %a) %b = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %a)
ret <2 x i16> %b ret <2 x i16> %b
} }
declare i64 @llvm.bitreverse.i64(i64) readnone declare i64 @llvm.bitreverse.i64(i64) readnone
define i64 @test_bitreverse_i64(i64 %a) nounwind { define i64 @test_bitreverse_i64(i64 %a) nounwind {
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; X64-NEXT: andq %rax, %rdx ; X64-NEXT: andq %rax, %rdx
; X64-NEXT: shrq %rdx ; X64-NEXT: shrq %rdx
; X64-NEXT: leaq (%rdx,%rcx,2), %rax ; X64-NEXT: leaq (%rdx,%rcx,2), %rax
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86XOP-LABEL: test_bitreverse_i64: ; X86XOP-LABEL: test_bitreverse_i64:
; X86XOP: # %bb.0: ; X86XOP: # %bb.0:
; X86XOP-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero ; X86XOP-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
; X86XOP-NEXT: vpperm {{\.LCPI.*}}, %xmm0, %xmm0, %xmm0 ; X86XOP-NEXT: vpperm {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0, %xmm0
; X86XOP-NEXT: vmovd %xmm0, %eax ; X86XOP-NEXT: vmovd %xmm0, %eax
; X86XOP-NEXT: vpextrd $1, %xmm0, %edx ; X86XOP-NEXT: vpextrd $1, %xmm0, %edx
; X86XOP-NEXT: retl ; X86XOP-NEXT: retl
%b = call i64 @llvm.bitreverse.i64(i64 %a) %b = call i64 @llvm.bitreverse.i64(i64 %a)
ret i64 %b ret i64 %b
} }
declare i32 @llvm.bitreverse.i32(i32) readnone declare i32 @llvm.bitreverse.i32(i32) readnone
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; X64-NEXT: andl $-1431655766, %eax # imm = 0xAAAAAAAA ; X64-NEXT: andl $-1431655766, %eax # imm = 0xAAAAAAAA
; X64-NEXT: shrl %eax ; X64-NEXT: shrl %eax
; X64-NEXT: leal (%rax,%rcx,2), %eax ; X64-NEXT: leal (%rax,%rcx,2), %eax
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86XOP-LABEL: test_bitreverse_i32: ; X86XOP-LABEL: test_bitreverse_i32:
; X86XOP: # %bb.0: ; X86XOP: # %bb.0:
; X86XOP-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86XOP-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86XOP-NEXT: vpperm {{\.LCPI.*}}, %xmm0, %xmm0, %xmm0 ; X86XOP-NEXT: vpperm {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0, %xmm0
; X86XOP-NEXT: vmovd %xmm0, %eax ; X86XOP-NEXT: vmovd %xmm0, %eax
; X86XOP-NEXT: retl ; X86XOP-NEXT: retl
%b = call i32 @llvm.bitreverse.i32(i32 %a) %b = call i32 @llvm.bitreverse.i32(i32 %a)
ret i32 %b ret i32 %b
} }
declare i24 @llvm.bitreverse.i24(i24) readnone declare i24 @llvm.bitreverse.i24(i24) readnone
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; X64-NEXT: shrl %eax ; X64-NEXT: shrl %eax
; X64-NEXT: leal (%rax,%rcx,2), %eax ; X64-NEXT: leal (%rax,%rcx,2), %eax
; X64-NEXT: shrl $8, %eax ; X64-NEXT: shrl $8, %eax
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86XOP-LABEL: test_bitreverse_i24: ; X86XOP-LABEL: test_bitreverse_i24:
; X86XOP: # %bb.0: ; X86XOP: # %bb.0:
; X86XOP-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86XOP-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86XOP-NEXT: vpperm {{\.LCPI.*}}, %xmm0, %xmm0, %xmm0 ; X86XOP-NEXT: vpperm {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0, %xmm0
; X86XOP-NEXT: vmovd %xmm0, %eax ; X86XOP-NEXT: vmovd %xmm0, %eax
; X86XOP-NEXT: shrl $8, %eax ; X86XOP-NEXT: shrl $8, %eax
; X86XOP-NEXT: retl ; X86XOP-NEXT: retl
%b = call i24 @llvm.bitreverse.i24(i24 %a) %b = call i24 @llvm.bitreverse.i24(i24 %a)
ret i24 %b ret i24 %b
} }
declare i16 @llvm.bitreverse.i16(i16) readnone declare i16 @llvm.bitreverse.i16(i16) readnone
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; X64-NEXT: shrl %eax ; X64-NEXT: shrl %eax
; X64-NEXT: leal (%rax,%rcx,2), %eax ; X64-NEXT: leal (%rax,%rcx,2), %eax
; X64-NEXT: # kill: def $ax killed $ax killed $eax ; X64-NEXT: # kill: def $ax killed $ax killed $eax
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86XOP-LABEL: test_bitreverse_i16: ; X86XOP-LABEL: test_bitreverse_i16:
; X86XOP: # %bb.0: ; X86XOP: # %bb.0:
; X86XOP-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86XOP-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86XOP-NEXT: vpperm {{\.LCPI.*}}, %xmm0, %xmm0, %xmm0 ; X86XOP-NEXT: vpperm {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0, %xmm0
; X86XOP-NEXT: vmovd %xmm0, %eax ; X86XOP-NEXT: vmovd %xmm0, %eax
; X86XOP-NEXT: # kill: def $ax killed $ax killed $eax ; X86XOP-NEXT: # kill: def $ax killed $ax killed $eax
; X86XOP-NEXT: retl ; X86XOP-NEXT: retl
%b = call i16 @llvm.bitreverse.i16(i16 %a) %b = call i16 @llvm.bitreverse.i16(i16 %a)
ret i16 %b ret i16 %b
} }
declare i8 @llvm.bitreverse.i8(i8) readnone declare i8 @llvm.bitreverse.i8(i8) readnone
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; X64-NEXT: shrb %dil ; X64-NEXT: shrb %dil
; X64-NEXT: addl %edi, %eax ; X64-NEXT: addl %edi, %eax
; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: # kill: def $al killed $al killed $eax
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86XOP-LABEL: test_bitreverse_i8: ; X86XOP-LABEL: test_bitreverse_i8:
; X86XOP: # %bb.0: ; X86XOP: # %bb.0:
; X86XOP-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86XOP-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86XOP-NEXT: vpperm {{\.LCPI.*}}, %xmm0, %xmm0, %xmm0 ; X86XOP-NEXT: vpperm {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0, %xmm0
; X86XOP-NEXT: vmovd %xmm0, %eax ; X86XOP-NEXT: vmovd %xmm0, %eax
; X86XOP-NEXT: # kill: def $al killed $al killed $eax ; X86XOP-NEXT: # kill: def $al killed $al killed $eax
; X86XOP-NEXT: retl ; X86XOP-NEXT: retl
%b = call i8 @llvm.bitreverse.i8(i8 %a) %b = call i8 @llvm.bitreverse.i8(i8 %a)
ret i8 %b ret i8 %b
} }
declare i4 @llvm.bitreverse.i4(i4) readnone declare i4 @llvm.bitreverse.i4(i4) readnone
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; X64-NEXT: addl %edi, %eax ; X64-NEXT: addl %edi, %eax
; X64-NEXT: shrb $4, %al ; X64-NEXT: shrb $4, %al
; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: # kill: def $al killed $al killed $eax
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86XOP-LABEL: test_bitreverse_i4: ; X86XOP-LABEL: test_bitreverse_i4:
; X86XOP: # %bb.0: ; X86XOP: # %bb.0:
; X86XOP-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86XOP-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86XOP-NEXT: vpperm {{\.LCPI.*}}, %xmm0, %xmm0, %xmm0 ; X86XOP-NEXT: vpperm {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0, %xmm0
; X86XOP-NEXT: vmovd %xmm0, %eax ; X86XOP-NEXT: vmovd %xmm0, %eax
; X86XOP-NEXT: shrb $4, %al ; X86XOP-NEXT: shrb $4, %al
; X86XOP-NEXT: # kill: def $al killed $al killed $eax ; X86XOP-NEXT: # kill: def $al killed $al killed $eax
; X86XOP-NEXT: retl ; X86XOP-NEXT: retl
%b = call i4 @llvm.bitreverse.i4(i4 %a) %b = call i4 @llvm.bitreverse.i4(i4 %a)
ret i4 %b ret i4 %b
} }
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llvm/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll

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define <32 x i8> @f32xi8_i16(<32 x i8> %a) { define <32 x i8> @f32xi8_i16(<32 x i8> %a) {
; AVX-LABEL: f32xi8_i16: ; AVX-LABEL: f32xi8_i16:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1] ; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1]
; AVX-NEXT: vpaddb %xmm2, %xmm1, %xmm1 ; AVX-NEXT: vpaddb %xmm2, %xmm1, %xmm1
; AVX-NEXT: vpaddb %xmm2, %xmm0, %xmm0 ; AVX-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX-NEXT: vandps {{\.LCPI.*}}, %ymm0, %ymm0 ; AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; AVX-NEXT: retl ; AVX-NEXT: retl
; ;
; ALL32-LABEL: f32xi8_i16: ; ALL32-LABEL: f32xi8_i16:
; ALL32: # %bb.0: ; ALL32: # %bb.0:
; ALL32-NEXT: vpbroadcastw {{.*#+}} ymm1 = [256,256,256,256,256,256,256,256,256,256,256,256,256,256,256,256] ; ALL32-NEXT: vpbroadcastw {{.*#+}} ymm1 = [256,256,256,256,256,256,256,256,256,256,256,256,256,256,256,256]
; ALL32-NEXT: vpaddb %ymm1, %ymm0, %ymm0 ; ALL32-NEXT: vpaddb %ymm1, %ymm0, %ymm0
; ALL32-NEXT: vpand %ymm1, %ymm0, %ymm0 ; ALL32-NEXT: vpand %ymm1, %ymm0, %ymm0
; ALL32-NEXT: retl ; ALL32-NEXT: retl
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define <32 x i8> @f32xi8_i32(<32 x i8> %a) { define <32 x i8> @f32xi8_i32(<32 x i8> %a) {
; AVX-LABEL: f32xi8_i32: ; AVX-LABEL: f32xi8_i32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX-NEXT: vbroadcastss {{.*#+}} xmm2 = [50462976,50462976,50462976,50462976] ; AVX-NEXT: vbroadcastss {{.*#+}} xmm2 = [50462976,50462976,50462976,50462976]
; AVX-NEXT: vpaddb %xmm2, %xmm1, %xmm1 ; AVX-NEXT: vpaddb %xmm2, %xmm1, %xmm1
; AVX-NEXT: vpaddb %xmm2, %xmm0, %xmm0 ; AVX-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX-NEXT: vandps {{\.LCPI.*}}, %ymm0, %ymm0 ; AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; AVX-NEXT: retl ; AVX-NEXT: retl
; ;
; ALL32-LABEL: f32xi8_i32: ; ALL32-LABEL: f32xi8_i32:
; ALL32: # %bb.0: ; ALL32: # %bb.0:
; ALL32-NEXT: vpbroadcastd {{.*#+}} ymm1 = [50462976,50462976,50462976,50462976,50462976,50462976,50462976,50462976] ; ALL32-NEXT: vpbroadcastd {{.*#+}} ymm1 = [50462976,50462976,50462976,50462976,50462976,50462976,50462976,50462976]
; ALL32-NEXT: vpaddb %ymm1, %ymm0, %ymm0 ; ALL32-NEXT: vpaddb %ymm1, %ymm0, %ymm0
; ALL32-NEXT: vpand %ymm1, %ymm0, %ymm0 ; ALL32-NEXT: vpand %ymm1, %ymm0, %ymm0
; ALL32-NEXT: retl ; ALL32-NEXT: retl
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; AVX-LABEL: f32xi8_i64: ; AVX-LABEL: f32xi8_i64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX-NEXT: vmovddup {{.*#+}} xmm2 = [506097522914230528,506097522914230528] ; AVX-NEXT: vmovddup {{.*#+}} xmm2 = [506097522914230528,506097522914230528]
; AVX-NEXT: # xmm2 = mem[0,0] ; AVX-NEXT: # xmm2 = mem[0,0]
; AVX-NEXT: vpaddb %xmm2, %xmm1, %xmm1 ; AVX-NEXT: vpaddb %xmm2, %xmm1, %xmm1
; AVX-NEXT: vpaddb %xmm2, %xmm0, %xmm0 ; AVX-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX-NEXT: vandps {{\.LCPI.*}}, %ymm0, %ymm0 ; AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; AVX-NEXT: retl ; AVX-NEXT: retl
; ;
; ALL32-LABEL: f32xi8_i64: ; ALL32-LABEL: f32xi8_i64:
; ALL32: # %bb.0: ; ALL32: # %bb.0:
; ALL32-NEXT: vpbroadcastq {{.*#+}} ymm1 = [506097522914230528,506097522914230528,506097522914230528,506097522914230528] ; ALL32-NEXT: vpbroadcastq {{.*#+}} ymm1 = [506097522914230528,506097522914230528,506097522914230528,506097522914230528]
; ALL32-NEXT: vpaddb %ymm1, %ymm0, %ymm0 ; ALL32-NEXT: vpaddb %ymm1, %ymm0, %ymm0
; ALL32-NEXT: vpand %ymm1, %ymm0, %ymm0 ; ALL32-NEXT: vpand %ymm1, %ymm0, %ymm0
; ALL32-NEXT: retl ; ALL32-NEXT: retl
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define <32 x i8> @f32xi8_i128(<32 x i8> %a) { define <32 x i8> @f32xi8_i128(<32 x i8> %a) {
; AVX-LABEL: f32xi8_i128: ; AVX-LABEL: f32xi8_i128:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15] ; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]
; AVX-NEXT: vpaddb %xmm2, %xmm1, %xmm1 ; AVX-NEXT: vpaddb %xmm2, %xmm1, %xmm1
; AVX-NEXT: vpaddb %xmm2, %xmm0, %xmm0 ; AVX-NEXT: vpaddb %xmm2, %xmm0, %xmm0
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX-NEXT: vandps {{\.LCPI.*}}, %ymm0, %ymm0 ; AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; AVX-NEXT: retl ; AVX-NEXT: retl
; ;
; ALL32-LABEL: f32xi8_i128: ; ALL32-LABEL: f32xi8_i128:
; ALL32: # %bb.0: ; ALL32: # %bb.0:
; ALL32-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15] ; ALL32-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]
; ALL32-NEXT: # ymm1 = mem[0,1,0,1] ; ALL32-NEXT: # ymm1 = mem[0,1,0,1]
; ALL32-NEXT: vpaddb %ymm1, %ymm0, %ymm0 ; ALL32-NEXT: vpaddb %ymm1, %ymm0, %ymm0
; ALL32-NEXT: vpand %ymm1, %ymm0, %ymm0 ; ALL32-NEXT: vpand %ymm1, %ymm0, %ymm0
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define <16 x i16> @f16xi16_i32(<16 x i16> %a) { define <16 x i16> @f16xi16_i32(<16 x i16> %a) {
; AVX-LABEL: f16xi16_i32: ; AVX-LABEL: f16xi16_i32:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX-NEXT: vbroadcastss {{.*#+}} xmm2 = [65536,65536,65536,65536] ; AVX-NEXT: vbroadcastss {{.*#+}} xmm2 = [65536,65536,65536,65536]
; AVX-NEXT: vpaddw %xmm2, %xmm1, %xmm1 ; AVX-NEXT: vpaddw %xmm2, %xmm1, %xmm1
; AVX-NEXT: vpaddw %xmm2, %xmm0, %xmm0 ; AVX-NEXT: vpaddw %xmm2, %xmm0, %xmm0
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX-NEXT: vandps {{\.LCPI.*}}, %ymm0, %ymm0 ; AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; AVX-NEXT: retl ; AVX-NEXT: retl
; ;
; ALL32-LABEL: f16xi16_i32: ; ALL32-LABEL: f16xi16_i32:
; ALL32: # %bb.0: ; ALL32: # %bb.0:
; ALL32-NEXT: vpbroadcastd {{.*#+}} ymm1 = [65536,65536,65536,65536,65536,65536,65536,65536] ; ALL32-NEXT: vpbroadcastd {{.*#+}} ymm1 = [65536,65536,65536,65536,65536,65536,65536,65536]
; ALL32-NEXT: vpaddw %ymm1, %ymm0, %ymm0 ; ALL32-NEXT: vpaddw %ymm1, %ymm0, %ymm0
; ALL32-NEXT: vpand %ymm1, %ymm0, %ymm0 ; ALL32-NEXT: vpand %ymm1, %ymm0, %ymm0
; ALL32-NEXT: retl ; ALL32-NEXT: retl
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; AVX-LABEL: f16xi16_i64: ; AVX-LABEL: f16xi16_i64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX-NEXT: vmovddup {{.*#+}} xmm2 = [844433520132096,844433520132096] ; AVX-NEXT: vmovddup {{.*#+}} xmm2 = [844433520132096,844433520132096]
; AVX-NEXT: # xmm2 = mem[0,0] ; AVX-NEXT: # xmm2 = mem[0,0]
; AVX-NEXT: vpaddw %xmm2, %xmm1, %xmm1 ; AVX-NEXT: vpaddw %xmm2, %xmm1, %xmm1
; AVX-NEXT: vpaddw %xmm2, %xmm0, %xmm0 ; AVX-NEXT: vpaddw %xmm2, %xmm0, %xmm0
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX-NEXT: vandps {{\.LCPI.*}}, %ymm0, %ymm0 ; AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; AVX-NEXT: retl ; AVX-NEXT: retl
; ;
; ALL32-LABEL: f16xi16_i64: ; ALL32-LABEL: f16xi16_i64:
; ALL32: # %bb.0: ; ALL32: # %bb.0:
; ALL32-NEXT: vpbroadcastq {{.*#+}} ymm1 = [844433520132096,844433520132096,844433520132096,844433520132096] ; ALL32-NEXT: vpbroadcastq {{.*#+}} ymm1 = [844433520132096,844433520132096,844433520132096,844433520132096]
; ALL32-NEXT: vpaddw %ymm1, %ymm0, %ymm0 ; ALL32-NEXT: vpaddw %ymm1, %ymm0, %ymm0
; ALL32-NEXT: vpand %ymm1, %ymm0, %ymm0 ; ALL32-NEXT: vpand %ymm1, %ymm0, %ymm0
; ALL32-NEXT: retl ; ALL32-NEXT: retl
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define <16 x i16> @f16xi16_i128(<16 x i16> %a) { define <16 x i16> @f16xi16_i128(<16 x i16> %a) {
; AVX-LABEL: f16xi16_i128: ; AVX-LABEL: f16xi16_i128:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,2,3,4,5,6,7] ; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,2,3,4,5,6,7]
; AVX-NEXT: vpaddw %xmm2, %xmm1, %xmm1 ; AVX-NEXT: vpaddw %xmm2, %xmm1, %xmm1
; AVX-NEXT: vpaddw %xmm2, %xmm0, %xmm0 ; AVX-NEXT: vpaddw %xmm2, %xmm0, %xmm0
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX-NEXT: vandps {{\.LCPI.*}}, %ymm0, %ymm0 ; AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; AVX-NEXT: retl ; AVX-NEXT: retl
; ;
; ALL32-LABEL: f16xi16_i128: ; ALL32-LABEL: f16xi16_i128:
; ALL32: # %bb.0: ; ALL32: # %bb.0:
; ALL32-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7] ; ALL32-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [0,1,2,3,4,5,6,7,0,1,2,3,4,5,6,7]
; ALL32-NEXT: # ymm1 = mem[0,1,0,1] ; ALL32-NEXT: # ymm1 = mem[0,1,0,1]
; ALL32-NEXT: vpaddw %ymm1, %ymm0, %ymm0 ; ALL32-NEXT: vpaddw %ymm1, %ymm0, %ymm0
; ALL32-NEXT: vpand %ymm1, %ymm0, %ymm0 ; ALL32-NEXT: vpand %ymm1, %ymm0, %ymm0
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; AVX-LABEL: f8xi32_i64: ; AVX-LABEL: f8xi32_i64:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX-NEXT: vmovddup {{.*#+}} xmm2 = [4294967296,4294967296] ; AVX-NEXT: vmovddup {{.*#+}} xmm2 = [4294967296,4294967296]
; AVX-NEXT: # xmm2 = mem[0,0] ; AVX-NEXT: # xmm2 = mem[0,0]
; AVX-NEXT: vpaddd %xmm2, %xmm1, %xmm1 ; AVX-NEXT: vpaddd %xmm2, %xmm1, %xmm1
; AVX-NEXT: vpaddd %xmm2, %xmm0, %xmm0 ; AVX-NEXT: vpaddd %xmm2, %xmm0, %xmm0
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX-NEXT: vandps {{\.LCPI.*}}, %ymm0, %ymm0 ; AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; AVX-NEXT: retl ; AVX-NEXT: retl
; ;
; ALL32-LABEL: f8xi32_i64: ; ALL32-LABEL: f8xi32_i64:
; ALL32: # %bb.0: ; ALL32: # %bb.0:
; ALL32-NEXT: vpbroadcastq {{.*#+}} ymm1 = [4294967296,4294967296,4294967296,4294967296] ; ALL32-NEXT: vpbroadcastq {{.*#+}} ymm1 = [4294967296,4294967296,4294967296,4294967296]
; ALL32-NEXT: vpaddd %ymm1, %ymm0, %ymm0 ; ALL32-NEXT: vpaddd %ymm1, %ymm0, %ymm0
; ALL32-NEXT: vpand %ymm1, %ymm0, %ymm0 ; ALL32-NEXT: vpand %ymm1, %ymm0, %ymm0
; ALL32-NEXT: retl ; ALL32-NEXT: retl
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define <8 x i32> @f8xi32_i128(<8 x i32> %a) { define <8 x i32> @f8xi32_i128(<8 x i32> %a) {
; AVX-LABEL: f8xi32_i128: ; AVX-LABEL: f8xi32_i128:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,2,3] ; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,2,3]
; AVX-NEXT: vpaddd %xmm2, %xmm1, %xmm1 ; AVX-NEXT: vpaddd %xmm2, %xmm1, %xmm1
; AVX-NEXT: vpaddd %xmm2, %xmm0, %xmm0 ; AVX-NEXT: vpaddd %xmm2, %xmm0, %xmm0
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX-NEXT: vandps {{\.LCPI.*}}, %ymm0, %ymm0 ; AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; AVX-NEXT: retl ; AVX-NEXT: retl
; ;
; ALL32-LABEL: f8xi32_i128: ; ALL32-LABEL: f8xi32_i128:
; ALL32: # %bb.0: ; ALL32: # %bb.0:
; ALL32-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [0,1,2,3,0,1,2,3] ; ALL32-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [0,1,2,3,0,1,2,3]
; ALL32-NEXT: # ymm1 = mem[0,1,0,1] ; ALL32-NEXT: # ymm1 = mem[0,1,0,1]
; ALL32-NEXT: vpaddd %ymm1, %ymm0, %ymm0 ; ALL32-NEXT: vpaddd %ymm1, %ymm0, %ymm0
; ALL32-NEXT: vpand %ymm1, %ymm0, %ymm0 ; ALL32-NEXT: vpand %ymm1, %ymm0, %ymm0
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define <4 x i64> @f4xi64_i128(<4 x i64> %a) { define <4 x i64> @f4xi64_i128(<4 x i64> %a) {
; AVX-LABEL: f4xi64_i128: ; AVX-LABEL: f4xi64_i128:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [0,0,1,0] ; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [0,0,1,0]
; AVX-NEXT: vpaddq %xmm2, %xmm1, %xmm1 ; AVX-NEXT: vpaddq %xmm2, %xmm1, %xmm1
; AVX-NEXT: vpaddq %xmm2, %xmm0, %xmm0 ; AVX-NEXT: vpaddq %xmm2, %xmm0, %xmm0
; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX-NEXT: vandps {{\.LCPI.*}}, %ymm0, %ymm0 ; AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; AVX-NEXT: retl ; AVX-NEXT: retl
; ;
; ALL32-LABEL: f4xi64_i128: ; ALL32-LABEL: f4xi64_i128:
; ALL32: # %bb.0: ; ALL32: # %bb.0:
; ALL32-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [0,0,1,0,0,0,1,0] ; ALL32-NEXT: vbroadcasti128 {{.*#+}} ymm1 = [0,0,1,0,0,0,1,0]
; ALL32-NEXT: # ymm1 = mem[0,1,0,1] ; ALL32-NEXT: # ymm1 = mem[0,1,0,1]
; ALL32-NEXT: vpaddq %ymm1, %ymm0, %ymm0 ; ALL32-NEXT: vpaddq %ymm1, %ymm0, %ymm0
; ALL32-NEXT: vpand %ymm1, %ymm0, %ymm0 ; ALL32-NEXT: vpand %ymm1, %ymm0, %ymm0
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llvm/test/CodeGen/X86/cmov-fp.ll

Show All 26 Lines
; SSE-NEXT: popl %ebp ; SSE-NEXT: popl %ebp
; SSE-NEXT: retl ; SSE-NEXT: retl
; ;
; NOSSE2-LABEL: test1: ; NOSSE2-LABEL: test1:
; NOSSE2: # %bb.0: ; NOSSE2: # %bb.0:
; NOSSE2-NEXT: fldl {{[0-9]+}}(%esp) ; NOSSE2-NEXT: fldl {{[0-9]+}}(%esp)
; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: flds {{\.LCPI.*}} ; NOSSE2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE2-NEXT: fxch %st(1) ; NOSSE2-NEXT: fxch %st(1)
; NOSSE2-NEXT: fcmovnbe %st(1), %st ; NOSSE2-NEXT: fcmovnbe %st(1), %st
; NOSSE2-NEXT: fstp %st(1) ; NOSSE2-NEXT: fstp %st(1)
; NOSSE2-NEXT: retl ; NOSSE2-NEXT: retl
; ;
; NOSSE1-LABEL: test1: ; NOSSE1-LABEL: test1:
; NOSSE1: # %bb.0: ; NOSSE1: # %bb.0:
; NOSSE1-NEXT: fldl {{[0-9]+}}(%esp) ; NOSSE1-NEXT: fldl {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: flds {{\.LCPI.*}} ; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1) ; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovnbe %st(1), %st ; NOSSE1-NEXT: fcmovnbe %st(1), %st
; NOSSE1-NEXT: fstp %st(1) ; NOSSE1-NEXT: fstp %st(1)
; NOSSE1-NEXT: retl ; NOSSE1-NEXT: retl
; ;
; NOCMOV-LABEL: test1: ; NOCMOV-LABEL: test1:
; NOCMOV: # %bb.0: ; NOCMOV: # %bb.0:
; NOCMOV-NEXT: fldl {{[0-9]+}}(%esp) ; NOCMOV-NEXT: fldl {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: flds {{\.LCPI.*}} ; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: ja .LBB0_2 ; NOCMOV-NEXT: ja .LBB0_2
; NOCMOV-NEXT: # %bb.1: ; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0) ; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz ; NOCMOV-NEXT: fldz
; NOCMOV-NEXT: fxch %st(1) ; NOCMOV-NEXT: fxch %st(1)
; NOCMOV-NEXT: .LBB0_2: ; NOCMOV-NEXT: .LBB0_2:
; NOCMOV-NEXT: fstp %st(1) ; NOCMOV-NEXT: fstp %st(1)
; NOCMOV-NEXT: retl ; NOCMOV-NEXT: retl
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; SSE-NEXT: popl %ebp ; SSE-NEXT: popl %ebp
; SSE-NEXT: retl ; SSE-NEXT: retl
; ;
; NOSSE2-LABEL: test2: ; NOSSE2-LABEL: test2:
; NOSSE2: # %bb.0: ; NOSSE2: # %bb.0:
; NOSSE2-NEXT: fldl {{[0-9]+}}(%esp) ; NOSSE2-NEXT: fldl {{[0-9]+}}(%esp)
; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: flds {{\.LCPI.*}} ; NOSSE2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE2-NEXT: fxch %st(1) ; NOSSE2-NEXT: fxch %st(1)
; NOSSE2-NEXT: fcmovnb %st(1), %st ; NOSSE2-NEXT: fcmovnb %st(1), %st
; NOSSE2-NEXT: fstp %st(1) ; NOSSE2-NEXT: fstp %st(1)
; NOSSE2-NEXT: retl ; NOSSE2-NEXT: retl
; ;
; NOSSE1-LABEL: test2: ; NOSSE1-LABEL: test2:
; NOSSE1: # %bb.0: ; NOSSE1: # %bb.0:
; NOSSE1-NEXT: fldl {{[0-9]+}}(%esp) ; NOSSE1-NEXT: fldl {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: flds {{\.LCPI.*}} ; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1) ; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovnb %st(1), %st ; NOSSE1-NEXT: fcmovnb %st(1), %st
; NOSSE1-NEXT: fstp %st(1) ; NOSSE1-NEXT: fstp %st(1)
; NOSSE1-NEXT: retl ; NOSSE1-NEXT: retl
; ;
; NOCMOV-LABEL: test2: ; NOCMOV-LABEL: test2:
; NOCMOV: # %bb.0: ; NOCMOV: # %bb.0:
; NOCMOV-NEXT: fldl {{[0-9]+}}(%esp) ; NOCMOV-NEXT: fldl {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: flds {{\.LCPI.*}} ; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jae .LBB1_2 ; NOCMOV-NEXT: jae .LBB1_2
; NOCMOV-NEXT: # %bb.1: ; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0) ; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz ; NOCMOV-NEXT: fldz
; NOCMOV-NEXT: fxch %st(1) ; NOCMOV-NEXT: fxch %st(1)
; NOCMOV-NEXT: .LBB1_2: ; NOCMOV-NEXT: .LBB1_2:
; NOCMOV-NEXT: fstp %st(1) ; NOCMOV-NEXT: fstp %st(1)
; NOCMOV-NEXT: retl ; NOCMOV-NEXT: retl
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; SSE-NEXT: popl %ebp ; SSE-NEXT: popl %ebp
; SSE-NEXT: retl ; SSE-NEXT: retl
; ;
; NOSSE2-LABEL: test3: ; NOSSE2-LABEL: test3:
; NOSSE2: # %bb.0: ; NOSSE2: # %bb.0:
; NOSSE2-NEXT: fldl {{[0-9]+}}(%esp) ; NOSSE2-NEXT: fldl {{[0-9]+}}(%esp)
; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: flds {{\.LCPI.*}} ; NOSSE2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE2-NEXT: fxch %st(1) ; NOSSE2-NEXT: fxch %st(1)
; NOSSE2-NEXT: fcmovb %st(1), %st ; NOSSE2-NEXT: fcmovb %st(1), %st
; NOSSE2-NEXT: fstp %st(1) ; NOSSE2-NEXT: fstp %st(1)
; NOSSE2-NEXT: retl ; NOSSE2-NEXT: retl
; ;
; NOSSE1-LABEL: test3: ; NOSSE1-LABEL: test3:
; NOSSE1: # %bb.0: ; NOSSE1: # %bb.0:
; NOSSE1-NEXT: fldl {{[0-9]+}}(%esp) ; NOSSE1-NEXT: fldl {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: flds {{\.LCPI.*}} ; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1) ; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovb %st(1), %st ; NOSSE1-NEXT: fcmovb %st(1), %st
; NOSSE1-NEXT: fstp %st(1) ; NOSSE1-NEXT: fstp %st(1)
; NOSSE1-NEXT: retl ; NOSSE1-NEXT: retl
; ;
; NOCMOV-LABEL: test3: ; NOCMOV-LABEL: test3:
; NOCMOV: # %bb.0: ; NOCMOV: # %bb.0:
; NOCMOV-NEXT: fldl {{[0-9]+}}(%esp) ; NOCMOV-NEXT: fldl {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: flds {{\.LCPI.*}} ; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jb .LBB2_2 ; NOCMOV-NEXT: jb .LBB2_2
; NOCMOV-NEXT: # %bb.1: ; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0) ; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz ; NOCMOV-NEXT: fldz
; NOCMOV-NEXT: fxch %st(1) ; NOCMOV-NEXT: fxch %st(1)
; NOCMOV-NEXT: .LBB2_2: ; NOCMOV-NEXT: .LBB2_2:
; NOCMOV-NEXT: fstp %st(1) ; NOCMOV-NEXT: fstp %st(1)
; NOCMOV-NEXT: retl ; NOCMOV-NEXT: retl
Show All 24 Lines
; SSE-NEXT: popl %ebp ; SSE-NEXT: popl %ebp
; SSE-NEXT: retl ; SSE-NEXT: retl
; ;
; NOSSE2-LABEL: test4: ; NOSSE2-LABEL: test4:
; NOSSE2: # %bb.0: ; NOSSE2: # %bb.0:
; NOSSE2-NEXT: fldl {{[0-9]+}}(%esp) ; NOSSE2-NEXT: fldl {{[0-9]+}}(%esp)
; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: flds {{\.LCPI.*}} ; NOSSE2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE2-NEXT: fxch %st(1) ; NOSSE2-NEXT: fxch %st(1)
; NOSSE2-NEXT: fcmovbe %st(1), %st ; NOSSE2-NEXT: fcmovbe %st(1), %st
; NOSSE2-NEXT: fstp %st(1) ; NOSSE2-NEXT: fstp %st(1)
; NOSSE2-NEXT: retl ; NOSSE2-NEXT: retl
; ;
; NOSSE1-LABEL: test4: ; NOSSE1-LABEL: test4:
; NOSSE1: # %bb.0: ; NOSSE1: # %bb.0:
; NOSSE1-NEXT: fldl {{[0-9]+}}(%esp) ; NOSSE1-NEXT: fldl {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: flds {{\.LCPI.*}} ; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1) ; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovbe %st(1), %st ; NOSSE1-NEXT: fcmovbe %st(1), %st
; NOSSE1-NEXT: fstp %st(1) ; NOSSE1-NEXT: fstp %st(1)
; NOSSE1-NEXT: retl ; NOSSE1-NEXT: retl
; ;
; NOCMOV-LABEL: test4: ; NOCMOV-LABEL: test4:
; NOCMOV: # %bb.0: ; NOCMOV: # %bb.0:
; NOCMOV-NEXT: fldl {{[0-9]+}}(%esp) ; NOCMOV-NEXT: fldl {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: flds {{\.LCPI.*}} ; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jbe .LBB3_2 ; NOCMOV-NEXT: jbe .LBB3_2
; NOCMOV-NEXT: # %bb.1: ; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0) ; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz ; NOCMOV-NEXT: fldz
; NOCMOV-NEXT: fxch %st(1) ; NOCMOV-NEXT: fxch %st(1)
; NOCMOV-NEXT: .LBB3_2: ; NOCMOV-NEXT: .LBB3_2:
; NOCMOV-NEXT: fstp %st(1) ; NOCMOV-NEXT: fstp %st(1)
; NOCMOV-NEXT: retl ; NOCMOV-NEXT: retl
Show All 26 Lines
; ;
; NOSSE2-LABEL: test5: ; NOSSE2-LABEL: test5:
; NOSSE2: # %bb.0: ; NOSSE2: # %bb.0:
; NOSSE2-NEXT: fldl {{[0-9]+}}(%esp) ; NOSSE2-NEXT: fldl {{[0-9]+}}(%esp)
; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: setg %al ; NOSSE2-NEXT: setg %al
; NOSSE2-NEXT: testb %al, %al ; NOSSE2-NEXT: testb %al, %al
; NOSSE2-NEXT: flds {{\.LCPI.*}} ; NOSSE2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE2-NEXT: fxch %st(1) ; NOSSE2-NEXT: fxch %st(1)
; NOSSE2-NEXT: fcmovne %st(1), %st ; NOSSE2-NEXT: fcmovne %st(1), %st
; NOSSE2-NEXT: fstp %st(1) ; NOSSE2-NEXT: fstp %st(1)
; NOSSE2-NEXT: retl ; NOSSE2-NEXT: retl
; ;
; NOSSE1-LABEL: test5: ; NOSSE1-LABEL: test5:
; NOSSE1: # %bb.0: ; NOSSE1: # %bb.0:
; NOSSE1-NEXT: fldl {{[0-9]+}}(%esp) ; NOSSE1-NEXT: fldl {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: setg %al ; NOSSE1-NEXT: setg %al
; NOSSE1-NEXT: testb %al, %al ; NOSSE1-NEXT: testb %al, %al
; NOSSE1-NEXT: flds {{\.LCPI.*}} ; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1) ; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovne %st(1), %st ; NOSSE1-NEXT: fcmovne %st(1), %st
; NOSSE1-NEXT: fstp %st(1) ; NOSSE1-NEXT: fstp %st(1)
; NOSSE1-NEXT: retl ; NOSSE1-NEXT: retl
; ;
; NOCMOV-LABEL: test5: ; NOCMOV-LABEL: test5:
; NOCMOV: # %bb.0: ; NOCMOV: # %bb.0:
; NOCMOV-NEXT: fldl {{[0-9]+}}(%esp) ; NOCMOV-NEXT: fldl {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: flds {{\.LCPI.*}} ; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jg .LBB4_2 ; NOCMOV-NEXT: jg .LBB4_2
; NOCMOV-NEXT: # %bb.1: ; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0) ; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz ; NOCMOV-NEXT: fldz
; NOCMOV-NEXT: fxch %st(1) ; NOCMOV-NEXT: fxch %st(1)
; NOCMOV-NEXT: .LBB4_2: ; NOCMOV-NEXT: .LBB4_2:
; NOCMOV-NEXT: fstp %st(1) ; NOCMOV-NEXT: fstp %st(1)
; NOCMOV-NEXT: retl ; NOCMOV-NEXT: retl
Show All 26 Lines
; ;
; NOSSE2-LABEL: test6: ; NOSSE2-LABEL: test6:
; NOSSE2: # %bb.0: ; NOSSE2: # %bb.0:
; NOSSE2-NEXT: fldl {{[0-9]+}}(%esp) ; NOSSE2-NEXT: fldl {{[0-9]+}}(%esp)
; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: setge %al ; NOSSE2-NEXT: setge %al
; NOSSE2-NEXT: testb %al, %al ; NOSSE2-NEXT: testb %al, %al
; NOSSE2-NEXT: flds {{\.LCPI.*}} ; NOSSE2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE2-NEXT: fxch %st(1) ; NOSSE2-NEXT: fxch %st(1)
; NOSSE2-NEXT: fcmovne %st(1), %st ; NOSSE2-NEXT: fcmovne %st(1), %st
; NOSSE2-NEXT: fstp %st(1) ; NOSSE2-NEXT: fstp %st(1)
; NOSSE2-NEXT: retl ; NOSSE2-NEXT: retl
; ;
; NOSSE1-LABEL: test6: ; NOSSE1-LABEL: test6:
; NOSSE1: # %bb.0: ; NOSSE1: # %bb.0:
; NOSSE1-NEXT: fldl {{[0-9]+}}(%esp) ; NOSSE1-NEXT: fldl {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: setge %al ; NOSSE1-NEXT: setge %al
; NOSSE1-NEXT: testb %al, %al ; NOSSE1-NEXT: testb %al, %al
; NOSSE1-NEXT: flds {{\.LCPI.*}} ; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1) ; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovne %st(1), %st ; NOSSE1-NEXT: fcmovne %st(1), %st
; NOSSE1-NEXT: fstp %st(1) ; NOSSE1-NEXT: fstp %st(1)
; NOSSE1-NEXT: retl ; NOSSE1-NEXT: retl
; ;
; NOCMOV-LABEL: test6: ; NOCMOV-LABEL: test6:
; NOCMOV: # %bb.0: ; NOCMOV: # %bb.0:
; NOCMOV-NEXT: fldl {{[0-9]+}}(%esp) ; NOCMOV-NEXT: fldl {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: flds {{\.LCPI.*}} ; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jge .LBB5_2 ; NOCMOV-NEXT: jge .LBB5_2
; NOCMOV-NEXT: # %bb.1: ; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0) ; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz ; NOCMOV-NEXT: fldz
; NOCMOV-NEXT: fxch %st(1) ; NOCMOV-NEXT: fxch %st(1)
; NOCMOV-NEXT: .LBB5_2: ; NOCMOV-NEXT: .LBB5_2:
; NOCMOV-NEXT: fstp %st(1) ; NOCMOV-NEXT: fstp %st(1)
; NOCMOV-NEXT: retl ; NOCMOV-NEXT: retl
Show All 26 Lines
; ;
; NOSSE2-LABEL: test7: ; NOSSE2-LABEL: test7:
; NOSSE2: # %bb.0: ; NOSSE2: # %bb.0:
; NOSSE2-NEXT: fldl {{[0-9]+}}(%esp) ; NOSSE2-NEXT: fldl {{[0-9]+}}(%esp)
; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: setl %al ; NOSSE2-NEXT: setl %al
; NOSSE2-NEXT: testb %al, %al ; NOSSE2-NEXT: testb %al, %al
; NOSSE2-NEXT: flds {{\.LCPI.*}} ; NOSSE2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE2-NEXT: fxch %st(1) ; NOSSE2-NEXT: fxch %st(1)
; NOSSE2-NEXT: fcmovne %st(1), %st ; NOSSE2-NEXT: fcmovne %st(1), %st
; NOSSE2-NEXT: fstp %st(1) ; NOSSE2-NEXT: fstp %st(1)
; NOSSE2-NEXT: retl ; NOSSE2-NEXT: retl
; ;
; NOSSE1-LABEL: test7: ; NOSSE1-LABEL: test7:
; NOSSE1: # %bb.0: ; NOSSE1: # %bb.0:
; NOSSE1-NEXT: fldl {{[0-9]+}}(%esp) ; NOSSE1-NEXT: fldl {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: setl %al ; NOSSE1-NEXT: setl %al
; NOSSE1-NEXT: testb %al, %al ; NOSSE1-NEXT: testb %al, %al
; NOSSE1-NEXT: flds {{\.LCPI.*}} ; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1) ; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovne %st(1), %st ; NOSSE1-NEXT: fcmovne %st(1), %st
; NOSSE1-NEXT: fstp %st(1) ; NOSSE1-NEXT: fstp %st(1)
; NOSSE1-NEXT: retl ; NOSSE1-NEXT: retl
; ;
; NOCMOV-LABEL: test7: ; NOCMOV-LABEL: test7:
; NOCMOV: # %bb.0: ; NOCMOV: # %bb.0:
; NOCMOV-NEXT: fldl {{[0-9]+}}(%esp) ; NOCMOV-NEXT: fldl {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: flds {{\.LCPI.*}} ; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jl .LBB6_2 ; NOCMOV-NEXT: jl .LBB6_2
; NOCMOV-NEXT: # %bb.1: ; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0) ; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz ; NOCMOV-NEXT: fldz
; NOCMOV-NEXT: fxch %st(1) ; NOCMOV-NEXT: fxch %st(1)
; NOCMOV-NEXT: .LBB6_2: ; NOCMOV-NEXT: .LBB6_2:
; NOCMOV-NEXT: fstp %st(1) ; NOCMOV-NEXT: fstp %st(1)
; NOCMOV-NEXT: retl ; NOCMOV-NEXT: retl
Show All 26 Lines
; ;
; NOSSE2-LABEL: test8: ; NOSSE2-LABEL: test8:
; NOSSE2: # %bb.0: ; NOSSE2: # %bb.0:
; NOSSE2-NEXT: fldl {{[0-9]+}}(%esp) ; NOSSE2-NEXT: fldl {{[0-9]+}}(%esp)
; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: setle %al ; NOSSE2-NEXT: setle %al
; NOSSE2-NEXT: testb %al, %al ; NOSSE2-NEXT: testb %al, %al
; NOSSE2-NEXT: flds {{\.LCPI.*}} ; NOSSE2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE2-NEXT: fxch %st(1) ; NOSSE2-NEXT: fxch %st(1)
; NOSSE2-NEXT: fcmovne %st(1), %st ; NOSSE2-NEXT: fcmovne %st(1), %st
; NOSSE2-NEXT: fstp %st(1) ; NOSSE2-NEXT: fstp %st(1)
; NOSSE2-NEXT: retl ; NOSSE2-NEXT: retl
; ;
; NOSSE1-LABEL: test8: ; NOSSE1-LABEL: test8:
; NOSSE1: # %bb.0: ; NOSSE1: # %bb.0:
; NOSSE1-NEXT: fldl {{[0-9]+}}(%esp) ; NOSSE1-NEXT: fldl {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: setle %al ; NOSSE1-NEXT: setle %al
; NOSSE1-NEXT: testb %al, %al ; NOSSE1-NEXT: testb %al, %al
; NOSSE1-NEXT: flds {{\.LCPI.*}} ; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1) ; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovne %st(1), %st ; NOSSE1-NEXT: fcmovne %st(1), %st
; NOSSE1-NEXT: fstp %st(1) ; NOSSE1-NEXT: fstp %st(1)
; NOSSE1-NEXT: retl ; NOSSE1-NEXT: retl
; ;
; NOCMOV-LABEL: test8: ; NOCMOV-LABEL: test8:
; NOCMOV: # %bb.0: ; NOCMOV: # %bb.0:
; NOCMOV-NEXT: fldl {{[0-9]+}}(%esp) ; NOCMOV-NEXT: fldl {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: flds {{\.LCPI.*}} ; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jle .LBB7_2 ; NOCMOV-NEXT: jle .LBB7_2
; NOCMOV-NEXT: # %bb.1: ; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0) ; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz ; NOCMOV-NEXT: fldz
; NOCMOV-NEXT: fxch %st(1) ; NOCMOV-NEXT: fxch %st(1)
; NOCMOV-NEXT: .LBB7_2: ; NOCMOV-NEXT: .LBB7_2:
; NOCMOV-NEXT: fstp %st(1) ; NOCMOV-NEXT: fstp %st(1)
; NOCMOV-NEXT: retl ; NOCMOV-NEXT: retl
Show All 37 Lines
; NOSSE2-NEXT: popl %eax ; NOSSE2-NEXT: popl %eax
; NOSSE2-NEXT: retl ; NOSSE2-NEXT: retl
; ;
; NOSSE1-LABEL: test9: ; NOSSE1-LABEL: test9:
; NOSSE1: # %bb.0: ; NOSSE1: # %bb.0:
; NOSSE1-NEXT: flds {{[0-9]+}}(%esp) ; NOSSE1-NEXT: flds {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: flds {{\.LCPI.*}} ; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1) ; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovnbe %st(1), %st ; NOSSE1-NEXT: fcmovnbe %st(1), %st
; NOSSE1-NEXT: fstp %st(1) ; NOSSE1-NEXT: fstp %st(1)
; NOSSE1-NEXT: retl ; NOSSE1-NEXT: retl
; ;
; NOCMOV-LABEL: test9: ; NOCMOV-LABEL: test9:
; NOCMOV: # %bb.0: ; NOCMOV: # %bb.0:
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp) ; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: flds {{\.LCPI.*}} ; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: ja .LBB8_2 ; NOCMOV-NEXT: ja .LBB8_2
; NOCMOV-NEXT: # %bb.1: ; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0) ; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz ; NOCMOV-NEXT: fldz
; NOCMOV-NEXT: fxch %st(1) ; NOCMOV-NEXT: fxch %st(1)
; NOCMOV-NEXT: .LBB8_2: ; NOCMOV-NEXT: .LBB8_2:
; NOCMOV-NEXT: fstp %st(1) ; NOCMOV-NEXT: fstp %st(1)
; NOCMOV-NEXT: retl ; NOCMOV-NEXT: retl
Show All 37 Lines
; NOSSE2-NEXT: popl %eax ; NOSSE2-NEXT: popl %eax
; NOSSE2-NEXT: retl ; NOSSE2-NEXT: retl
; ;
; NOSSE1-LABEL: test10: ; NOSSE1-LABEL: test10:
; NOSSE1: # %bb.0: ; NOSSE1: # %bb.0:
; NOSSE1-NEXT: flds {{[0-9]+}}(%esp) ; NOSSE1-NEXT: flds {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: flds {{\.LCPI.*}} ; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1) ; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovnb %st(1), %st ; NOSSE1-NEXT: fcmovnb %st(1), %st
; NOSSE1-NEXT: fstp %st(1) ; NOSSE1-NEXT: fstp %st(1)
; NOSSE1-NEXT: retl ; NOSSE1-NEXT: retl
; ;
; NOCMOV-LABEL: test10: ; NOCMOV-LABEL: test10:
; NOCMOV: # %bb.0: ; NOCMOV: # %bb.0:
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp) ; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: flds {{\.LCPI.*}} ; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jae .LBB9_2 ; NOCMOV-NEXT: jae .LBB9_2
; NOCMOV-NEXT: # %bb.1: ; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0) ; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz ; NOCMOV-NEXT: fldz
; NOCMOV-NEXT: fxch %st(1) ; NOCMOV-NEXT: fxch %st(1)
; NOCMOV-NEXT: .LBB9_2: ; NOCMOV-NEXT: .LBB9_2:
; NOCMOV-NEXT: fstp %st(1) ; NOCMOV-NEXT: fstp %st(1)
; NOCMOV-NEXT: retl ; NOCMOV-NEXT: retl
Show All 37 Lines
; NOSSE2-NEXT: popl %eax ; NOSSE2-NEXT: popl %eax
; NOSSE2-NEXT: retl ; NOSSE2-NEXT: retl
; ;
; NOSSE1-LABEL: test11: ; NOSSE1-LABEL: test11:
; NOSSE1: # %bb.0: ; NOSSE1: # %bb.0:
; NOSSE1-NEXT: flds {{[0-9]+}}(%esp) ; NOSSE1-NEXT: flds {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: flds {{\.LCPI.*}} ; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1) ; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovb %st(1), %st ; NOSSE1-NEXT: fcmovb %st(1), %st
; NOSSE1-NEXT: fstp %st(1) ; NOSSE1-NEXT: fstp %st(1)
; NOSSE1-NEXT: retl ; NOSSE1-NEXT: retl
; ;
; NOCMOV-LABEL: test11: ; NOCMOV-LABEL: test11:
; NOCMOV: # %bb.0: ; NOCMOV: # %bb.0:
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp) ; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: flds {{\.LCPI.*}} ; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jb .LBB10_2 ; NOCMOV-NEXT: jb .LBB10_2
; NOCMOV-NEXT: # %bb.1: ; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0) ; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz ; NOCMOV-NEXT: fldz
; NOCMOV-NEXT: fxch %st(1) ; NOCMOV-NEXT: fxch %st(1)
; NOCMOV-NEXT: .LBB10_2: ; NOCMOV-NEXT: .LBB10_2:
; NOCMOV-NEXT: fstp %st(1) ; NOCMOV-NEXT: fstp %st(1)
; NOCMOV-NEXT: retl ; NOCMOV-NEXT: retl
Show All 37 Lines
; NOSSE2-NEXT: popl %eax ; NOSSE2-NEXT: popl %eax
; NOSSE2-NEXT: retl ; NOSSE2-NEXT: retl
; ;
; NOSSE1-LABEL: test12: ; NOSSE1-LABEL: test12:
; NOSSE1: # %bb.0: ; NOSSE1: # %bb.0:
; NOSSE1-NEXT: flds {{[0-9]+}}(%esp) ; NOSSE1-NEXT: flds {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: flds {{\.LCPI.*}} ; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1) ; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovbe %st(1), %st ; NOSSE1-NEXT: fcmovbe %st(1), %st
; NOSSE1-NEXT: fstp %st(1) ; NOSSE1-NEXT: fstp %st(1)
; NOSSE1-NEXT: retl ; NOSSE1-NEXT: retl
; ;
; NOCMOV-LABEL: test12: ; NOCMOV-LABEL: test12:
; NOCMOV: # %bb.0: ; NOCMOV: # %bb.0:
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp) ; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: flds {{\.LCPI.*}} ; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jbe .LBB11_2 ; NOCMOV-NEXT: jbe .LBB11_2
; NOCMOV-NEXT: # %bb.1: ; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0) ; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz ; NOCMOV-NEXT: fldz
; NOCMOV-NEXT: fxch %st(1) ; NOCMOV-NEXT: fxch %st(1)
; NOCMOV-NEXT: .LBB11_2: ; NOCMOV-NEXT: .LBB11_2:
; NOCMOV-NEXT: fstp %st(1) ; NOCMOV-NEXT: fstp %st(1)
; NOCMOV-NEXT: retl ; NOCMOV-NEXT: retl
Show All 39 Lines
; ;
; NOSSE1-LABEL: test13: ; NOSSE1-LABEL: test13:
; NOSSE1: # %bb.0: ; NOSSE1: # %bb.0:
; NOSSE1-NEXT: flds {{[0-9]+}}(%esp) ; NOSSE1-NEXT: flds {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: setg %al ; NOSSE1-NEXT: setg %al
; NOSSE1-NEXT: testb %al, %al ; NOSSE1-NEXT: testb %al, %al
; NOSSE1-NEXT: flds {{\.LCPI.*}} ; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1) ; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovne %st(1), %st ; NOSSE1-NEXT: fcmovne %st(1), %st
; NOSSE1-NEXT: fstp %st(1) ; NOSSE1-NEXT: fstp %st(1)
; NOSSE1-NEXT: retl ; NOSSE1-NEXT: retl
; ;
; NOCMOV-LABEL: test13: ; NOCMOV-LABEL: test13:
; NOCMOV: # %bb.0: ; NOCMOV: # %bb.0:
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp) ; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: flds {{\.LCPI.*}} ; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jg .LBB12_2 ; NOCMOV-NEXT: jg .LBB12_2
; NOCMOV-NEXT: # %bb.1: ; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0) ; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz ; NOCMOV-NEXT: fldz
; NOCMOV-NEXT: fxch %st(1) ; NOCMOV-NEXT: fxch %st(1)
; NOCMOV-NEXT: .LBB12_2: ; NOCMOV-NEXT: .LBB12_2:
; NOCMOV-NEXT: fstp %st(1) ; NOCMOV-NEXT: fstp %st(1)
; NOCMOV-NEXT: retl ; NOCMOV-NEXT: retl
Show All 39 Lines
; ;
; NOSSE1-LABEL: test14: ; NOSSE1-LABEL: test14:
; NOSSE1: # %bb.0: ; NOSSE1: # %bb.0:
; NOSSE1-NEXT: flds {{[0-9]+}}(%esp) ; NOSSE1-NEXT: flds {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: setge %al ; NOSSE1-NEXT: setge %al
; NOSSE1-NEXT: testb %al, %al ; NOSSE1-NEXT: testb %al, %al
; NOSSE1-NEXT: flds {{\.LCPI.*}} ; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1) ; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovne %st(1), %st ; NOSSE1-NEXT: fcmovne %st(1), %st
; NOSSE1-NEXT: fstp %st(1) ; NOSSE1-NEXT: fstp %st(1)
; NOSSE1-NEXT: retl ; NOSSE1-NEXT: retl
; ;
; NOCMOV-LABEL: test14: ; NOCMOV-LABEL: test14:
; NOCMOV: # %bb.0: ; NOCMOV: # %bb.0:
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp) ; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: flds {{\.LCPI.*}} ; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jge .LBB13_2 ; NOCMOV-NEXT: jge .LBB13_2
; NOCMOV-NEXT: # %bb.1: ; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0) ; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz ; NOCMOV-NEXT: fldz
; NOCMOV-NEXT: fxch %st(1) ; NOCMOV-NEXT: fxch %st(1)
; NOCMOV-NEXT: .LBB13_2: ; NOCMOV-NEXT: .LBB13_2:
; NOCMOV-NEXT: fstp %st(1) ; NOCMOV-NEXT: fstp %st(1)
; NOCMOV-NEXT: retl ; NOCMOV-NEXT: retl
Show All 39 Lines
; ;
; NOSSE1-LABEL: test15: ; NOSSE1-LABEL: test15:
; NOSSE1: # %bb.0: ; NOSSE1: # %bb.0:
; NOSSE1-NEXT: flds {{[0-9]+}}(%esp) ; NOSSE1-NEXT: flds {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: setl %al ; NOSSE1-NEXT: setl %al
; NOSSE1-NEXT: testb %al, %al ; NOSSE1-NEXT: testb %al, %al
; NOSSE1-NEXT: flds {{\.LCPI.*}} ; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1) ; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovne %st(1), %st ; NOSSE1-NEXT: fcmovne %st(1), %st
; NOSSE1-NEXT: fstp %st(1) ; NOSSE1-NEXT: fstp %st(1)
; NOSSE1-NEXT: retl ; NOSSE1-NEXT: retl
; ;
; NOCMOV-LABEL: test15: ; NOCMOV-LABEL: test15:
; NOCMOV: # %bb.0: ; NOCMOV: # %bb.0:
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp) ; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: flds {{\.LCPI.*}} ; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jl .LBB14_2 ; NOCMOV-NEXT: jl .LBB14_2
; NOCMOV-NEXT: # %bb.1: ; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0) ; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz ; NOCMOV-NEXT: fldz
; NOCMOV-NEXT: fxch %st(1) ; NOCMOV-NEXT: fxch %st(1)
; NOCMOV-NEXT: .LBB14_2: ; NOCMOV-NEXT: .LBB14_2:
; NOCMOV-NEXT: fstp %st(1) ; NOCMOV-NEXT: fstp %st(1)
; NOCMOV-NEXT: retl ; NOCMOV-NEXT: retl
Show All 39 Lines
; ;
; NOSSE1-LABEL: test16: ; NOSSE1-LABEL: test16:
; NOSSE1: # %bb.0: ; NOSSE1: # %bb.0:
; NOSSE1-NEXT: flds {{[0-9]+}}(%esp) ; NOSSE1-NEXT: flds {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: setle %al ; NOSSE1-NEXT: setle %al
; NOSSE1-NEXT: testb %al, %al ; NOSSE1-NEXT: testb %al, %al
; NOSSE1-NEXT: flds {{\.LCPI.*}} ; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1) ; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovne %st(1), %st ; NOSSE1-NEXT: fcmovne %st(1), %st
; NOSSE1-NEXT: fstp %st(1) ; NOSSE1-NEXT: fstp %st(1)
; NOSSE1-NEXT: retl ; NOSSE1-NEXT: retl
; ;
; NOCMOV-LABEL: test16: ; NOCMOV-LABEL: test16:
; NOCMOV: # %bb.0: ; NOCMOV: # %bb.0:
; NOCMOV-NEXT: flds {{[0-9]+}}(%esp) ; NOCMOV-NEXT: flds {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: flds {{\.LCPI.*}} ; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jle .LBB15_2 ; NOCMOV-NEXT: jle .LBB15_2
; NOCMOV-NEXT: # %bb.1: ; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0) ; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz ; NOCMOV-NEXT: fldz
; NOCMOV-NEXT: fxch %st(1) ; NOCMOV-NEXT: fxch %st(1)
; NOCMOV-NEXT: .LBB15_2: ; NOCMOV-NEXT: .LBB15_2:
; NOCMOV-NEXT: fstp %st(1) ; NOCMOV-NEXT: fstp %st(1)
; NOCMOV-NEXT: retl ; NOCMOV-NEXT: retl
%cmp = icmp sle i32 %a, %b %cmp = icmp sle i32 %a, %b
%sel = select i1 %cmp, float 99.0, float %x %sel = select i1 %cmp, float 99.0, float %x
ret float %sel ret float %sel
} }
define x86_fp80 @test17(i32 %a, i32 %b, x86_fp80 %x) nounwind { define x86_fp80 @test17(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; SSE-LABEL: test17: ; SSE-LABEL: test17:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: fldt {{[0-9]+}}(%esp) ; SSE-NEXT: fldt {{[0-9]+}}(%esp)
; SSE-NEXT: flds {{\.LCPI.*}} ; SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; SSE-NEXT: fxch %st(1) ; SSE-NEXT: fxch %st(1)
; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: fcmovnbe %st(1), %st ; SSE-NEXT: fcmovnbe %st(1), %st
; SSE-NEXT: fstp %st(1) ; SSE-NEXT: fstp %st(1)
; SSE-NEXT: retl ; SSE-NEXT: retl
; ;
; NOSSE2-LABEL: test17: ; NOSSE2-LABEL: test17:
; NOSSE2: # %bb.0: ; NOSSE2: # %bb.0:
; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp) ; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp)
; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: flds {{\.LCPI.*}} ; NOSSE2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE2-NEXT: fxch %st(1) ; NOSSE2-NEXT: fxch %st(1)
; NOSSE2-NEXT: fcmovnbe %st(1), %st ; NOSSE2-NEXT: fcmovnbe %st(1), %st
; NOSSE2-NEXT: fstp %st(1) ; NOSSE2-NEXT: fstp %st(1)
; NOSSE2-NEXT: retl ; NOSSE2-NEXT: retl
; ;
; NOSSE1-LABEL: test17: ; NOSSE1-LABEL: test17:
; NOSSE1: # %bb.0: ; NOSSE1: # %bb.0:
; NOSSE1-NEXT: fldt {{[0-9]+}}(%esp) ; NOSSE1-NEXT: fldt {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: flds {{\.LCPI.*}} ; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1) ; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovnbe %st(1), %st ; NOSSE1-NEXT: fcmovnbe %st(1), %st
; NOSSE1-NEXT: fstp %st(1) ; NOSSE1-NEXT: fstp %st(1)
; NOSSE1-NEXT: retl ; NOSSE1-NEXT: retl
; ;
; NOCMOV-LABEL: test17: ; NOCMOV-LABEL: test17:
; NOCMOV: # %bb.0: ; NOCMOV: # %bb.0:
; NOCMOV-NEXT: fldt {{[0-9]+}}(%esp) ; NOCMOV-NEXT: fldt {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: flds {{\.LCPI.*}} ; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: ja .LBB16_2 ; NOCMOV-NEXT: ja .LBB16_2
; NOCMOV-NEXT: # %bb.1: ; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0) ; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz ; NOCMOV-NEXT: fldz
; NOCMOV-NEXT: fxch %st(1) ; NOCMOV-NEXT: fxch %st(1)
; NOCMOV-NEXT: .LBB16_2: ; NOCMOV-NEXT: .LBB16_2:
; NOCMOV-NEXT: fstp %st(1) ; NOCMOV-NEXT: fstp %st(1)
; NOCMOV-NEXT: retl ; NOCMOV-NEXT: retl
%cmp = icmp ugt i32 %a, %b %cmp = icmp ugt i32 %a, %b
%sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
ret x86_fp80 %sel ret x86_fp80 %sel
} }
define x86_fp80 @test18(i32 %a, i32 %b, x86_fp80 %x) nounwind { define x86_fp80 @test18(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; SSE-LABEL: test18: ; SSE-LABEL: test18:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: fldt {{[0-9]+}}(%esp) ; SSE-NEXT: fldt {{[0-9]+}}(%esp)
; SSE-NEXT: flds {{\.LCPI.*}} ; SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; SSE-NEXT: fxch %st(1) ; SSE-NEXT: fxch %st(1)
; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: fcmovnb %st(1), %st ; SSE-NEXT: fcmovnb %st(1), %st
; SSE-NEXT: fstp %st(1) ; SSE-NEXT: fstp %st(1)
; SSE-NEXT: retl ; SSE-NEXT: retl
; ;
; NOSSE2-LABEL: test18: ; NOSSE2-LABEL: test18:
; NOSSE2: # %bb.0: ; NOSSE2: # %bb.0:
; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp) ; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp)
; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: flds {{\.LCPI.*}} ; NOSSE2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE2-NEXT: fxch %st(1) ; NOSSE2-NEXT: fxch %st(1)
; NOSSE2-NEXT: fcmovnb %st(1), %st ; NOSSE2-NEXT: fcmovnb %st(1), %st
; NOSSE2-NEXT: fstp %st(1) ; NOSSE2-NEXT: fstp %st(1)
; NOSSE2-NEXT: retl ; NOSSE2-NEXT: retl
; ;
; NOSSE1-LABEL: test18: ; NOSSE1-LABEL: test18:
; NOSSE1: # %bb.0: ; NOSSE1: # %bb.0:
; NOSSE1-NEXT: fldt {{[0-9]+}}(%esp) ; NOSSE1-NEXT: fldt {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: flds {{\.LCPI.*}} ; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1) ; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovnb %st(1), %st ; NOSSE1-NEXT: fcmovnb %st(1), %st
; NOSSE1-NEXT: fstp %st(1) ; NOSSE1-NEXT: fstp %st(1)
; NOSSE1-NEXT: retl ; NOSSE1-NEXT: retl
; ;
; NOCMOV-LABEL: test18: ; NOCMOV-LABEL: test18:
; NOCMOV: # %bb.0: ; NOCMOV: # %bb.0:
; NOCMOV-NEXT: fldt {{[0-9]+}}(%esp) ; NOCMOV-NEXT: fldt {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: flds {{\.LCPI.*}} ; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jae .LBB17_2 ; NOCMOV-NEXT: jae .LBB17_2
; NOCMOV-NEXT: # %bb.1: ; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0) ; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz ; NOCMOV-NEXT: fldz
; NOCMOV-NEXT: fxch %st(1) ; NOCMOV-NEXT: fxch %st(1)
; NOCMOV-NEXT: .LBB17_2: ; NOCMOV-NEXT: .LBB17_2:
; NOCMOV-NEXT: fstp %st(1) ; NOCMOV-NEXT: fstp %st(1)
; NOCMOV-NEXT: retl ; NOCMOV-NEXT: retl
%cmp = icmp uge i32 %a, %b %cmp = icmp uge i32 %a, %b
%sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
ret x86_fp80 %sel ret x86_fp80 %sel
} }
define x86_fp80 @test19(i32 %a, i32 %b, x86_fp80 %x) nounwind { define x86_fp80 @test19(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; SSE-LABEL: test19: ; SSE-LABEL: test19:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: fldt {{[0-9]+}}(%esp) ; SSE-NEXT: fldt {{[0-9]+}}(%esp)
; SSE-NEXT: flds {{\.LCPI.*}} ; SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; SSE-NEXT: fxch %st(1) ; SSE-NEXT: fxch %st(1)
; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: fcmovb %st(1), %st ; SSE-NEXT: fcmovb %st(1), %st
; SSE-NEXT: fstp %st(1) ; SSE-NEXT: fstp %st(1)
; SSE-NEXT: retl ; SSE-NEXT: retl
; ;
; NOSSE2-LABEL: test19: ; NOSSE2-LABEL: test19:
; NOSSE2: # %bb.0: ; NOSSE2: # %bb.0:
; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp) ; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp)
; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: flds {{\.LCPI.*}} ; NOSSE2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE2-NEXT: fxch %st(1) ; NOSSE2-NEXT: fxch %st(1)
; NOSSE2-NEXT: fcmovb %st(1), %st ; NOSSE2-NEXT: fcmovb %st(1), %st
; NOSSE2-NEXT: fstp %st(1) ; NOSSE2-NEXT: fstp %st(1)
; NOSSE2-NEXT: retl ; NOSSE2-NEXT: retl
; ;
; NOSSE1-LABEL: test19: ; NOSSE1-LABEL: test19:
; NOSSE1: # %bb.0: ; NOSSE1: # %bb.0:
; NOSSE1-NEXT: fldt {{[0-9]+}}(%esp) ; NOSSE1-NEXT: fldt {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: flds {{\.LCPI.*}} ; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1) ; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovb %st(1), %st ; NOSSE1-NEXT: fcmovb %st(1), %st
; NOSSE1-NEXT: fstp %st(1) ; NOSSE1-NEXT: fstp %st(1)
; NOSSE1-NEXT: retl ; NOSSE1-NEXT: retl
; ;
; NOCMOV-LABEL: test19: ; NOCMOV-LABEL: test19:
; NOCMOV: # %bb.0: ; NOCMOV: # %bb.0:
; NOCMOV-NEXT: fldt {{[0-9]+}}(%esp) ; NOCMOV-NEXT: fldt {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: flds {{\.LCPI.*}} ; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jb .LBB18_2 ; NOCMOV-NEXT: jb .LBB18_2
; NOCMOV-NEXT: # %bb.1: ; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0) ; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz ; NOCMOV-NEXT: fldz
; NOCMOV-NEXT: fxch %st(1) ; NOCMOV-NEXT: fxch %st(1)
; NOCMOV-NEXT: .LBB18_2: ; NOCMOV-NEXT: .LBB18_2:
; NOCMOV-NEXT: fstp %st(1) ; NOCMOV-NEXT: fstp %st(1)
; NOCMOV-NEXT: retl ; NOCMOV-NEXT: retl
%cmp = icmp ult i32 %a, %b %cmp = icmp ult i32 %a, %b
%sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
ret x86_fp80 %sel ret x86_fp80 %sel
} }
define x86_fp80 @test20(i32 %a, i32 %b, x86_fp80 %x) nounwind { define x86_fp80 @test20(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; SSE-LABEL: test20: ; SSE-LABEL: test20:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: fldt {{[0-9]+}}(%esp) ; SSE-NEXT: fldt {{[0-9]+}}(%esp)
; SSE-NEXT: flds {{\.LCPI.*}} ; SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; SSE-NEXT: fxch %st(1) ; SSE-NEXT: fxch %st(1)
; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: fcmovbe %st(1), %st ; SSE-NEXT: fcmovbe %st(1), %st
; SSE-NEXT: fstp %st(1) ; SSE-NEXT: fstp %st(1)
; SSE-NEXT: retl ; SSE-NEXT: retl
; ;
; NOSSE2-LABEL: test20: ; NOSSE2-LABEL: test20:
; NOSSE2: # %bb.0: ; NOSSE2: # %bb.0:
; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp) ; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp)
; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: flds {{\.LCPI.*}} ; NOSSE2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE2-NEXT: fxch %st(1) ; NOSSE2-NEXT: fxch %st(1)
; NOSSE2-NEXT: fcmovbe %st(1), %st ; NOSSE2-NEXT: fcmovbe %st(1), %st
; NOSSE2-NEXT: fstp %st(1) ; NOSSE2-NEXT: fstp %st(1)
; NOSSE2-NEXT: retl ; NOSSE2-NEXT: retl
; ;
; NOSSE1-LABEL: test20: ; NOSSE1-LABEL: test20:
; NOSSE1: # %bb.0: ; NOSSE1: # %bb.0:
; NOSSE1-NEXT: fldt {{[0-9]+}}(%esp) ; NOSSE1-NEXT: fldt {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: flds {{\.LCPI.*}} ; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1) ; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovbe %st(1), %st ; NOSSE1-NEXT: fcmovbe %st(1), %st
; NOSSE1-NEXT: fstp %st(1) ; NOSSE1-NEXT: fstp %st(1)
; NOSSE1-NEXT: retl ; NOSSE1-NEXT: retl
; ;
; NOCMOV-LABEL: test20: ; NOCMOV-LABEL: test20:
; NOCMOV: # %bb.0: ; NOCMOV: # %bb.0:
; NOCMOV-NEXT: fldt {{[0-9]+}}(%esp) ; NOCMOV-NEXT: fldt {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: flds {{\.LCPI.*}} ; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jbe .LBB19_2 ; NOCMOV-NEXT: jbe .LBB19_2
; NOCMOV-NEXT: # %bb.1: ; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0) ; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz ; NOCMOV-NEXT: fldz
; NOCMOV-NEXT: fxch %st(1) ; NOCMOV-NEXT: fxch %st(1)
; NOCMOV-NEXT: .LBB19_2: ; NOCMOV-NEXT: .LBB19_2:
; NOCMOV-NEXT: fstp %st(1) ; NOCMOV-NEXT: fstp %st(1)
; NOCMOV-NEXT: retl ; NOCMOV-NEXT: retl
%cmp = icmp ule i32 %a, %b %cmp = icmp ule i32 %a, %b
%sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
ret x86_fp80 %sel ret x86_fp80 %sel
} }
define x86_fp80 @test21(i32 %a, i32 %b, x86_fp80 %x) nounwind { define x86_fp80 @test21(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; SSE-LABEL: test21: ; SSE-LABEL: test21:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: fldt {{[0-9]+}}(%esp) ; SSE-NEXT: fldt {{[0-9]+}}(%esp)
; SSE-NEXT: flds {{\.LCPI.*}} ; SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; SSE-NEXT: fxch %st(1) ; SSE-NEXT: fxch %st(1)
; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: setg %al ; SSE-NEXT: setg %al
; SSE-NEXT: testb %al, %al ; SSE-NEXT: testb %al, %al
; SSE-NEXT: fcmovne %st(1), %st ; SSE-NEXT: fcmovne %st(1), %st
; SSE-NEXT: fstp %st(1) ; SSE-NEXT: fstp %st(1)
; SSE-NEXT: retl ; SSE-NEXT: retl
; ;
; NOSSE2-LABEL: test21: ; NOSSE2-LABEL: test21:
; NOSSE2: # %bb.0: ; NOSSE2: # %bb.0:
; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp) ; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp)
; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: setg %al ; NOSSE2-NEXT: setg %al
; NOSSE2-NEXT: testb %al, %al ; NOSSE2-NEXT: testb %al, %al
; NOSSE2-NEXT: flds {{\.LCPI.*}} ; NOSSE2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE2-NEXT: fxch %st(1) ; NOSSE2-NEXT: fxch %st(1)
; NOSSE2-NEXT: fcmovne %st(1), %st ; NOSSE2-NEXT: fcmovne %st(1), %st
; NOSSE2-NEXT: fstp %st(1) ; NOSSE2-NEXT: fstp %st(1)
; NOSSE2-NEXT: retl ; NOSSE2-NEXT: retl
; ;
; NOSSE1-LABEL: test21: ; NOSSE1-LABEL: test21:
; NOSSE1: # %bb.0: ; NOSSE1: # %bb.0:
; NOSSE1-NEXT: fldt {{[0-9]+}}(%esp) ; NOSSE1-NEXT: fldt {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: setg %al ; NOSSE1-NEXT: setg %al
; NOSSE1-NEXT: testb %al, %al ; NOSSE1-NEXT: testb %al, %al
; NOSSE1-NEXT: flds {{\.LCPI.*}} ; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1) ; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovne %st(1), %st ; NOSSE1-NEXT: fcmovne %st(1), %st
; NOSSE1-NEXT: fstp %st(1) ; NOSSE1-NEXT: fstp %st(1)
; NOSSE1-NEXT: retl ; NOSSE1-NEXT: retl
; ;
; NOCMOV-LABEL: test21: ; NOCMOV-LABEL: test21:
; NOCMOV: # %bb.0: ; NOCMOV: # %bb.0:
; NOCMOV-NEXT: fldt {{[0-9]+}}(%esp) ; NOCMOV-NEXT: fldt {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: flds {{\.LCPI.*}} ; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jg .LBB20_2 ; NOCMOV-NEXT: jg .LBB20_2
; NOCMOV-NEXT: # %bb.1: ; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0) ; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz ; NOCMOV-NEXT: fldz
; NOCMOV-NEXT: fxch %st(1) ; NOCMOV-NEXT: fxch %st(1)
; NOCMOV-NEXT: .LBB20_2: ; NOCMOV-NEXT: .LBB20_2:
; NOCMOV-NEXT: fstp %st(1) ; NOCMOV-NEXT: fstp %st(1)
; NOCMOV-NEXT: retl ; NOCMOV-NEXT: retl
; We don't emit a branch for fp80, why? ; We don't emit a branch for fp80, why?
%cmp = icmp sgt i32 %a, %b %cmp = icmp sgt i32 %a, %b
%sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
ret x86_fp80 %sel ret x86_fp80 %sel
} }
define x86_fp80 @test22(i32 %a, i32 %b, x86_fp80 %x) nounwind { define x86_fp80 @test22(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; SSE-LABEL: test22: ; SSE-LABEL: test22:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: fldt {{[0-9]+}}(%esp) ; SSE-NEXT: fldt {{[0-9]+}}(%esp)
; SSE-NEXT: flds {{\.LCPI.*}} ; SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; SSE-NEXT: fxch %st(1) ; SSE-NEXT: fxch %st(1)
; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: setge %al ; SSE-NEXT: setge %al
; SSE-NEXT: testb %al, %al ; SSE-NEXT: testb %al, %al
; SSE-NEXT: fcmovne %st(1), %st ; SSE-NEXT: fcmovne %st(1), %st
; SSE-NEXT: fstp %st(1) ; SSE-NEXT: fstp %st(1)
; SSE-NEXT: retl ; SSE-NEXT: retl
; ;
; NOSSE2-LABEL: test22: ; NOSSE2-LABEL: test22:
; NOSSE2: # %bb.0: ; NOSSE2: # %bb.0:
; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp) ; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp)
; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: setge %al ; NOSSE2-NEXT: setge %al
; NOSSE2-NEXT: testb %al, %al ; NOSSE2-NEXT: testb %al, %al
; NOSSE2-NEXT: flds {{\.LCPI.*}} ; NOSSE2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE2-NEXT: fxch %st(1) ; NOSSE2-NEXT: fxch %st(1)
; NOSSE2-NEXT: fcmovne %st(1), %st ; NOSSE2-NEXT: fcmovne %st(1), %st
; NOSSE2-NEXT: fstp %st(1) ; NOSSE2-NEXT: fstp %st(1)
; NOSSE2-NEXT: retl ; NOSSE2-NEXT: retl
; ;
; NOSSE1-LABEL: test22: ; NOSSE1-LABEL: test22:
; NOSSE1: # %bb.0: ; NOSSE1: # %bb.0:
; NOSSE1-NEXT: fldt {{[0-9]+}}(%esp) ; NOSSE1-NEXT: fldt {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: setge %al ; NOSSE1-NEXT: setge %al
; NOSSE1-NEXT: testb %al, %al ; NOSSE1-NEXT: testb %al, %al
; NOSSE1-NEXT: flds {{\.LCPI.*}} ; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1) ; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovne %st(1), %st ; NOSSE1-NEXT: fcmovne %st(1), %st
; NOSSE1-NEXT: fstp %st(1) ; NOSSE1-NEXT: fstp %st(1)
; NOSSE1-NEXT: retl ; NOSSE1-NEXT: retl
; ;
; NOCMOV-LABEL: test22: ; NOCMOV-LABEL: test22:
; NOCMOV: # %bb.0: ; NOCMOV: # %bb.0:
; NOCMOV-NEXT: fldt {{[0-9]+}}(%esp) ; NOCMOV-NEXT: fldt {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: flds {{\.LCPI.*}} ; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jge .LBB21_2 ; NOCMOV-NEXT: jge .LBB21_2
; NOCMOV-NEXT: # %bb.1: ; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0) ; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz ; NOCMOV-NEXT: fldz
; NOCMOV-NEXT: fxch %st(1) ; NOCMOV-NEXT: fxch %st(1)
; NOCMOV-NEXT: .LBB21_2: ; NOCMOV-NEXT: .LBB21_2:
; NOCMOV-NEXT: fstp %st(1) ; NOCMOV-NEXT: fstp %st(1)
; NOCMOV-NEXT: retl ; NOCMOV-NEXT: retl
%cmp = icmp sge i32 %a, %b %cmp = icmp sge i32 %a, %b
%sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
ret x86_fp80 %sel ret x86_fp80 %sel
} }
define x86_fp80 @test23(i32 %a, i32 %b, x86_fp80 %x) nounwind { define x86_fp80 @test23(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; SSE-LABEL: test23: ; SSE-LABEL: test23:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: fldt {{[0-9]+}}(%esp) ; SSE-NEXT: fldt {{[0-9]+}}(%esp)
; SSE-NEXT: flds {{\.LCPI.*}} ; SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; SSE-NEXT: fxch %st(1) ; SSE-NEXT: fxch %st(1)
; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: setl %al ; SSE-NEXT: setl %al
; SSE-NEXT: testb %al, %al ; SSE-NEXT: testb %al, %al
; SSE-NEXT: fcmovne %st(1), %st ; SSE-NEXT: fcmovne %st(1), %st
; SSE-NEXT: fstp %st(1) ; SSE-NEXT: fstp %st(1)
; SSE-NEXT: retl ; SSE-NEXT: retl
; ;
; NOSSE2-LABEL: test23: ; NOSSE2-LABEL: test23:
; NOSSE2: # %bb.0: ; NOSSE2: # %bb.0:
; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp) ; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp)
; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: setl %al ; NOSSE2-NEXT: setl %al
; NOSSE2-NEXT: testb %al, %al ; NOSSE2-NEXT: testb %al, %al
; NOSSE2-NEXT: flds {{\.LCPI.*}} ; NOSSE2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE2-NEXT: fxch %st(1) ; NOSSE2-NEXT: fxch %st(1)
; NOSSE2-NEXT: fcmovne %st(1), %st ; NOSSE2-NEXT: fcmovne %st(1), %st
; NOSSE2-NEXT: fstp %st(1) ; NOSSE2-NEXT: fstp %st(1)
; NOSSE2-NEXT: retl ; NOSSE2-NEXT: retl
; ;
; NOSSE1-LABEL: test23: ; NOSSE1-LABEL: test23:
; NOSSE1: # %bb.0: ; NOSSE1: # %bb.0:
; NOSSE1-NEXT: fldt {{[0-9]+}}(%esp) ; NOSSE1-NEXT: fldt {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: setl %al ; NOSSE1-NEXT: setl %al
; NOSSE1-NEXT: testb %al, %al ; NOSSE1-NEXT: testb %al, %al
; NOSSE1-NEXT: flds {{\.LCPI.*}} ; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1) ; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovne %st(1), %st ; NOSSE1-NEXT: fcmovne %st(1), %st
; NOSSE1-NEXT: fstp %st(1) ; NOSSE1-NEXT: fstp %st(1)
; NOSSE1-NEXT: retl ; NOSSE1-NEXT: retl
; ;
; NOCMOV-LABEL: test23: ; NOCMOV-LABEL: test23:
; NOCMOV: # %bb.0: ; NOCMOV: # %bb.0:
; NOCMOV-NEXT: fldt {{[0-9]+}}(%esp) ; NOCMOV-NEXT: fldt {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: flds {{\.LCPI.*}} ; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jl .LBB22_2 ; NOCMOV-NEXT: jl .LBB22_2
; NOCMOV-NEXT: # %bb.1: ; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0) ; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz ; NOCMOV-NEXT: fldz
; NOCMOV-NEXT: fxch %st(1) ; NOCMOV-NEXT: fxch %st(1)
; NOCMOV-NEXT: .LBB22_2: ; NOCMOV-NEXT: .LBB22_2:
; NOCMOV-NEXT: fstp %st(1) ; NOCMOV-NEXT: fstp %st(1)
; NOCMOV-NEXT: retl ; NOCMOV-NEXT: retl
%cmp = icmp slt i32 %a, %b %cmp = icmp slt i32 %a, %b
%sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
ret x86_fp80 %sel ret x86_fp80 %sel
} }
define x86_fp80 @test24(i32 %a, i32 %b, x86_fp80 %x) nounwind { define x86_fp80 @test24(i32 %a, i32 %b, x86_fp80 %x) nounwind {
; SSE-LABEL: test24: ; SSE-LABEL: test24:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: fldt {{[0-9]+}}(%esp) ; SSE-NEXT: fldt {{[0-9]+}}(%esp)
; SSE-NEXT: flds {{\.LCPI.*}} ; SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; SSE-NEXT: fxch %st(1) ; SSE-NEXT: fxch %st(1)
; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; SSE-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; SSE-NEXT: setle %al ; SSE-NEXT: setle %al
; SSE-NEXT: testb %al, %al ; SSE-NEXT: testb %al, %al
; SSE-NEXT: fcmovne %st(1), %st ; SSE-NEXT: fcmovne %st(1), %st
; SSE-NEXT: fstp %st(1) ; SSE-NEXT: fstp %st(1)
; SSE-NEXT: retl ; SSE-NEXT: retl
; ;
; NOSSE2-LABEL: test24: ; NOSSE2-LABEL: test24:
; NOSSE2: # %bb.0: ; NOSSE2: # %bb.0:
; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp) ; NOSSE2-NEXT: fldt {{[0-9]+}}(%esp)
; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE2-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE2-NEXT: setle %al ; NOSSE2-NEXT: setle %al
; NOSSE2-NEXT: testb %al, %al ; NOSSE2-NEXT: testb %al, %al
; NOSSE2-NEXT: flds {{\.LCPI.*}} ; NOSSE2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE2-NEXT: fxch %st(1) ; NOSSE2-NEXT: fxch %st(1)
; NOSSE2-NEXT: fcmovne %st(1), %st ; NOSSE2-NEXT: fcmovne %st(1), %st
; NOSSE2-NEXT: fstp %st(1) ; NOSSE2-NEXT: fstp %st(1)
; NOSSE2-NEXT: retl ; NOSSE2-NEXT: retl
; ;
; NOSSE1-LABEL: test24: ; NOSSE1-LABEL: test24:
; NOSSE1: # %bb.0: ; NOSSE1: # %bb.0:
; NOSSE1-NEXT: fldt {{[0-9]+}}(%esp) ; NOSSE1-NEXT: fldt {{[0-9]+}}(%esp)
; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOSSE1-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOSSE1-NEXT: setle %al ; NOSSE1-NEXT: setle %al
; NOSSE1-NEXT: testb %al, %al ; NOSSE1-NEXT: testb %al, %al
; NOSSE1-NEXT: flds {{\.LCPI.*}} ; NOSSE1-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOSSE1-NEXT: fxch %st(1) ; NOSSE1-NEXT: fxch %st(1)
; NOSSE1-NEXT: fcmovne %st(1), %st ; NOSSE1-NEXT: fcmovne %st(1), %st
; NOSSE1-NEXT: fstp %st(1) ; NOSSE1-NEXT: fstp %st(1)
; NOSSE1-NEXT: retl ; NOSSE1-NEXT: retl
; ;
; NOCMOV-LABEL: test24: ; NOCMOV-LABEL: test24:
; NOCMOV: # %bb.0: ; NOCMOV: # %bb.0:
; NOCMOV-NEXT: fldt {{[0-9]+}}(%esp) ; NOCMOV-NEXT: fldt {{[0-9]+}}(%esp)
; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: movl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax ; NOCMOV-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; NOCMOV-NEXT: flds {{\.LCPI.*}} ; NOCMOV-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; NOCMOV-NEXT: jle .LBB23_2 ; NOCMOV-NEXT: jle .LBB23_2
; NOCMOV-NEXT: # %bb.1: ; NOCMOV-NEXT: # %bb.1:
; NOCMOV-NEXT: fstp %st(0) ; NOCMOV-NEXT: fstp %st(0)
; NOCMOV-NEXT: fldz ; NOCMOV-NEXT: fldz
; NOCMOV-NEXT: fxch %st(1) ; NOCMOV-NEXT: fxch %st(1)
; NOCMOV-NEXT: .LBB23_2: ; NOCMOV-NEXT: .LBB23_2:
; NOCMOV-NEXT: fstp %st(1) ; NOCMOV-NEXT: fstp %st(1)
; NOCMOV-NEXT: retl ; NOCMOV-NEXT: retl
%cmp = icmp sle i32 %a, %b %cmp = icmp sle i32 %a, %b
%sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
ret x86_fp80 %sel ret x86_fp80 %sel
} }

llvm/test/CodeGen/X86/cmp.ll

Show First 20 Lines • Show All 102 Lines • ▼ Show 20 Linesentry:
%r = zext i1 %t to i64 %r = zext i1 %t to i64
ret i64 %r ret i64 %r
} }
define dso_local i32 @test5(double %A) nounwind { define dso_local i32 @test5(double %A) nounwind {
; CHECK-LABEL: test5: ; CHECK-LABEL: test5:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ucomisd {{.*}}(%rip), %xmm0 # encoding: [0x66,0x0f,0x2e,0x05,A,A,A,A] ; CHECK-NEXT: ucomisd {{.*}}(%rip), %xmm0 # encoding: [0x66,0x0f,0x2e,0x05,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; CHECK-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; CHECK-NEXT: ja .LBB5_3 # encoding: [0x77,A] ; CHECK-NEXT: ja .LBB5_3 # encoding: [0x77,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB5_3-1, kind: FK_PCRel_1 ; CHECK-NEXT: # fixup A - offset: 1, value: .LBB5_3-1, kind: FK_PCRel_1
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: ucomisd {{.*}}(%rip), %xmm0 # encoding: [0x66,0x0f,0x2e,0x05,A,A,A,A] ; CHECK-NEXT: ucomisd {{.*}}(%rip), %xmm0 # encoding: [0x66,0x0f,0x2e,0x05,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; CHECK-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; CHECK-NEXT: jb .LBB5_3 # encoding: [0x72,A] ; CHECK-NEXT: jb .LBB5_3 # encoding: [0x72,A]
; CHECK-NEXT: # fixup A - offset: 1, value: .LBB5_3-1, kind: FK_PCRel_1 ; CHECK-NEXT: # fixup A - offset: 1, value: .LBB5_3-1, kind: FK_PCRel_1
; CHECK-NEXT: # %bb.2: # %bb12 ; CHECK-NEXT: # %bb.2: # %bb12
; CHECK-NEXT: movl $32, %eax # encoding: [0xb8,0x20,0x00,0x00,0x00] ; CHECK-NEXT: movl $32, %eax # encoding: [0xb8,0x20,0x00,0x00,0x00]
; CHECK-NEXT: retq # encoding: [0xc3] ; CHECK-NEXT: retq # encoding: [0xc3]
; CHECK-NEXT: .LBB5_3: # %bb8 ; CHECK-NEXT: .LBB5_3: # %bb8
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
; CHECK-NEXT: jmp foo # TAILCALL ; CHECK-NEXT: jmp foo # TAILCALL
▲ Show 20 Lines • Show All 400 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/code-model-elf.ll

Show First 20 Lines • Show All 411 Lines • ▼ Show 20 Lines
define dso_local float @load_constant_pool(float %x) #0 { define dso_local float @load_constant_pool(float %x) #0 {
; SMALL-STATIC-LABEL: load_constant_pool: ; SMALL-STATIC-LABEL: load_constant_pool:
; SMALL-STATIC: # %bb.0: ; SMALL-STATIC: # %bb.0:
; SMALL-STATIC-NEXT: addss {{.*}}(%rip), %xmm0 ; SMALL-STATIC-NEXT: addss {{.*}}(%rip), %xmm0
; SMALL-STATIC-NEXT: retq ; SMALL-STATIC-NEXT: retq
; ;
; MEDIUM-STATIC-LABEL: load_constant_pool: ; MEDIUM-STATIC-LABEL: load_constant_pool:
; MEDIUM-STATIC: # %bb.0: ; MEDIUM-STATIC: # %bb.0:
; MEDIUM-STATIC-NEXT: movabsq ${{\.LCPI.*}}, %rax ; MEDIUM-STATIC-NEXT: movabsq ${{\.LCPI[0-9]+_[0-9]+}}, %rax
; MEDIUM-STATIC-NEXT: addss (%rax), %xmm0 ; MEDIUM-STATIC-NEXT: addss (%rax), %xmm0
; MEDIUM-STATIC-NEXT: retq ; MEDIUM-STATIC-NEXT: retq
; ;
; LARGE-STATIC-LABEL: load_constant_pool: ; LARGE-STATIC-LABEL: load_constant_pool:
; LARGE-STATIC: # %bb.0: ; LARGE-STATIC: # %bb.0:
; LARGE-STATIC-NEXT: movabsq ${{\.LCPI.*}}, %rax ; LARGE-STATIC-NEXT: movabsq ${{\.LCPI[0-9]+_[0-9]+}}, %rax
; LARGE-STATIC-NEXT: addss (%rax), %xmm0 ; LARGE-STATIC-NEXT: addss (%rax), %xmm0
; LARGE-STATIC-NEXT: retq ; LARGE-STATIC-NEXT: retq
; ;
; SMALL-PIC-LABEL: load_constant_pool: ; SMALL-PIC-LABEL: load_constant_pool:
; SMALL-PIC: # %bb.0: ; SMALL-PIC: # %bb.0:
; SMALL-PIC-NEXT: addss {{.*}}(%rip), %xmm0 ; SMALL-PIC-NEXT: addss {{.*}}(%rip), %xmm0
; SMALL-PIC-NEXT: retq ; SMALL-PIC-NEXT: retq
; ;
; MEDIUM-PIC-LABEL: load_constant_pool: ; MEDIUM-PIC-LABEL: load_constant_pool:
; MEDIUM-PIC: # %bb.0: ; MEDIUM-PIC: # %bb.0:
; MEDIUM-PIC-NEXT: leaq {{.*}}(%rip), %rax ; MEDIUM-PIC-NEXT: leaq {{.*}}(%rip), %rax
; MEDIUM-PIC-NEXT: movabsq ${{\.LCPI.*}}@GOTOFF, %rcx ; MEDIUM-PIC-NEXT: movabsq ${{\.LCPI[0-9]+_[0-9]+}}@GOTOFF, %rcx
; MEDIUM-PIC-NEXT: addss (%rax,%rcx), %xmm0 ; MEDIUM-PIC-NEXT: addss (%rax,%rcx), %xmm0
; MEDIUM-PIC-NEXT: retq ; MEDIUM-PIC-NEXT: retq
; ;
; LARGE-PIC-LABEL: load_constant_pool: ; LARGE-PIC-LABEL: load_constant_pool:
; LARGE-PIC: # %bb.0: ; LARGE-PIC: # %bb.0:
; LARGE-PIC-NEXT: .L11$pb: ; LARGE-PIC-NEXT: .L11$pb:
; LARGE-PIC-NEXT: leaq .L11${{.*}}(%rip), %rax ; LARGE-PIC-NEXT: leaq .L11${{.*}}(%rip), %rax
; LARGE-PIC-NEXT: movabsq $_GLOBAL_OFFSET_TABLE_-.L11$pb, %rcx ; LARGE-PIC-NEXT: movabsq $_GLOBAL_OFFSET_TABLE_-.L11$pb, %rcx
; LARGE-PIC-NEXT: addq %rax, %rcx ; LARGE-PIC-NEXT: addq %rax, %rcx
; LARGE-PIC-NEXT: movabsq ${{\.LCPI.*}}@GOTOFF, %rax ; LARGE-PIC-NEXT: movabsq ${{\.LCPI[0-9]+_[0-9]+}}@GOTOFF, %rax
; LARGE-PIC-NEXT: addss (%rcx,%rax), %xmm0 ; LARGE-PIC-NEXT: addss (%rcx,%rax), %xmm0
; LARGE-PIC-NEXT: retq ; LARGE-PIC-NEXT: retq
%a = fadd float %x, 1.0 %a = fadd float %x, 1.0
ret float %a ret float %a
} }
attributes #0 = { noinline nounwind uwtable } attributes #0 = { noinline nounwind uwtable }
!llvm.module.flags = !{!0, !1, !2} !llvm.module.flags = !{!0, !1, !2}
!llvm.ident = !{!3} !llvm.ident = !{!3}
!0 = !{i32 1, !"wchar_size", i32 4} !0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 7, !"PIC Level", i32 2} !1 = !{i32 7, !"PIC Level", i32 2}
!2 = !{i32 7, !"PIE Level", i32 2} !2 = !{i32 7, !"PIE Level", i32 2}
!3 = !{!"clang version 7.0.0 "} !3 = !{!"clang version 7.0.0 "}

llvm/test/CodeGen/X86/combine-bextr.ll

Show All 34 Lines
define float @bextr_uitofp(i32 %x, i32 %y) { define float @bextr_uitofp(i32 %x, i32 %y) {
; X32-LABEL: bextr_uitofp: ; X32-LABEL: bextr_uitofp:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: movl $3855, %eax # imm = 0xF0F ; X32-NEXT: movl $3855, %eax # imm = 0xF0F
; X32-NEXT: bextrl %eax, {{[0-9]+}}(%esp), %eax ; X32-NEXT: bextrl %eax, {{[0-9]+}}(%esp), %eax
; X32-NEXT: movd %eax, %xmm0 ; X32-NEXT: movd %eax, %xmm0
; X32-NEXT: por {{\.LCPI.*}}, %xmm0 ; X32-NEXT: por {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: subsd {{\.LCPI.*}}, %xmm0 ; X32-NEXT: subsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: cvtsd2ss %xmm0, %xmm0 ; X32-NEXT: cvtsd2ss %xmm0, %xmm0
; X32-NEXT: movss %xmm0, (%esp) ; X32-NEXT: movss %xmm0, (%esp)
; X32-NEXT: flds (%esp) ; X32-NEXT: flds (%esp)
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
; X32-NEXT: .cfi_def_cfa_offset 4 ; X32-NEXT: .cfi_def_cfa_offset 4
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: bextr_uitofp: ; X64-LABEL: bextr_uitofp:
Show All 9 Lines

llvm/test/CodeGen/X86/combine-bitreverse.ll

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; X86-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[3,2,1,0,4,5,6,7] ; X86-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[3,2,1,0,4,5,6,7]
; X86-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,7,6,5,4] ; X86-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,7,6,5,4]
; X86-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] ; X86-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; X86-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7] ; X86-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7]
; X86-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4] ; X86-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
; X86-NEXT: packuswb %xmm2, %xmm0 ; X86-NEXT: packuswb %xmm2, %xmm0
; X86-NEXT: movdqa %xmm0, %xmm1 ; X86-NEXT: movdqa %xmm0, %xmm1
; X86-NEXT: psllw $4, %xmm1 ; X86-NEXT: psllw $4, %xmm1
; X86-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-NEXT: psrlw $4, %xmm0 ; X86-NEXT: psrlw $4, %xmm0
; X86-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: por %xmm1, %xmm0 ; X86-NEXT: por %xmm1, %xmm0
; X86-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; X86-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; X86-NEXT: pand %xmm0, %xmm1 ; X86-NEXT: pand %xmm0, %xmm1
; X86-NEXT: psllw $2, %xmm1 ; X86-NEXT: psllw $2, %xmm1
; X86-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: psrlw $2, %xmm0 ; X86-NEXT: psrlw $2, %xmm0
; X86-NEXT: por %xmm1, %xmm0 ; X86-NEXT: por %xmm1, %xmm0
; X86-NEXT: movdqa {{.*#+}} xmm1 = [85,85,85,85,85,85,85,85,85,85,85,85,85,85,85,85] ; X86-NEXT: movdqa {{.*#+}} xmm1 = [85,85,85,85,85,85,85,85,85,85,85,85,85,85,85,85]
; X86-NEXT: pand %xmm0, %xmm1 ; X86-NEXT: pand %xmm0, %xmm1
; X86-NEXT: paddb %xmm1, %xmm1 ; X86-NEXT: paddb %xmm1, %xmm1
; X86-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: psrlw $1, %xmm0 ; X86-NEXT: psrlw $1, %xmm0
; X86-NEXT: por %xmm1, %xmm0 ; X86-NEXT: por %xmm1, %xmm0
; X86-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: test_demandedbits_bitreverse: ; X64-LABEL: test_demandedbits_bitreverse:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12] ; X64-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12]
; X64-NEXT: vmovdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] ; X64-NEXT: vmovdqa {{.*#+}} xmm1 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
; X64-NEXT: vpand %xmm1, %xmm0, %xmm2 ; X64-NEXT: vpand %xmm1, %xmm0, %xmm2
; X64-NEXT: vmovdqa {{.*#+}} xmm3 = [0,128,64,192,32,160,96,224,16,144,80,208,48,176,112,240] ; X64-NEXT: vmovdqa {{.*#+}} xmm3 = [0,128,64,192,32,160,96,224,16,144,80,208,48,176,112,240]
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llvm/test/CodeGen/X86/combine-multiplies.ll

Show First 20 Lines • Show All 110 Lines • ▼ Show 20 Lines
; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; CHECK-NEXT: pmuludq %xmm2, %xmm0 ; CHECK-NEXT: pmuludq %xmm2, %xmm0
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; CHECK-NEXT: pmuludq %xmm2, %xmm3 ; CHECK-NEXT: pmuludq %xmm2, %xmm3
; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm3[0,2,2,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm3[0,2,2,3]
; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] ; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [242,242,242,242] ; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [242,242,242,242]
; CHECK-NEXT: paddd %xmm0, %xmm2 ; CHECK-NEXT: paddd %xmm0, %xmm2
; CHECK-NEXT: paddd {{\.LCPI.*}}, %xmm0 ; CHECK-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; CHECK-NEXT: movdqa %xmm2, v2 ; CHECK-NEXT: movdqa %xmm2, v2
; CHECK-NEXT: movdqa %xmm0, v3 ; CHECK-NEXT: movdqa %xmm0, v3
; CHECK-NEXT: movdqa %xmm1, x ; CHECK-NEXT: movdqa %xmm1, x
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
%add1 = add <4 x i32> %v1, <i32 11, i32 11, i32 11, i32 11> %add1 = add <4 x i32> %v1, <i32 11, i32 11, i32 11, i32 11>
%mul1 = mul <4 x i32> %add1, <i32 22, i32 22, i32 22, i32 22> %mul1 = mul <4 x i32> %add1, <i32 22, i32 22, i32 22, i32 22>
%add2 = add <4 x i32> %v1, <i32 33, i32 33, i32 33, i32 33> %add2 = add <4 x i32> %v1, <i32 33, i32 33, i32 33, i32 33>
Show All 18 Lines
; CHECK-NEXT: pmuludq %xmm2, %xmm0 ; CHECK-NEXT: pmuludq %xmm2, %xmm0
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; CHECK-NEXT: pmuludq %xmm3, %xmm2 ; CHECK-NEXT: pmuludq %xmm3, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] ; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] ; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [242,726,1452,2420] ; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [242,726,1452,2420]
; CHECK-NEXT: paddd %xmm0, %xmm2 ; CHECK-NEXT: paddd %xmm0, %xmm2
; CHECK-NEXT: paddd {{\.LCPI.*}}, %xmm0 ; CHECK-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; CHECK-NEXT: movdqa %xmm2, v2 ; CHECK-NEXT: movdqa %xmm2, v2
; CHECK-NEXT: movdqa %xmm0, v3 ; CHECK-NEXT: movdqa %xmm0, v3
; CHECK-NEXT: movdqa %xmm1, x ; CHECK-NEXT: movdqa %xmm1, x
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
%add1 = add <4 x i32> %v1, <i32 11, i32 22, i32 33, i32 44> %add1 = add <4 x i32> %v1, <i32 11, i32 22, i32 33, i32 44>
%mul1 = mul <4 x i32> %add1, <i32 22, i32 33, i32 44, i32 55> %mul1 = mul <4 x i32> %add1, <i32 22, i32 33, i32 44, i32 55>
%add2 = add <4 x i32> %v1, <i32 33, i32 44, i32 55, i32 66> %add2 = add <4 x i32> %v1, <i32 33, i32 44, i32 55, i32 66>
%mul2 = mul <4 x i32> %add2, <i32 22, i32 33, i32 44, i32 55> %mul2 = mul <4 x i32> %add2, <i32 22, i32 33, i32 44, i32 55>
store <4 x i32> %mul1, <4 x i32>* @v2, align 16 store <4 x i32> %mul1, <4 x i32>* @v2, align 16
store <4 x i32> %mul2, <4 x i32>* @v3, align 16 store <4 x i32> %mul2, <4 x i32>* @v3, align 16
store <4 x i32> %add1, <4 x i32>* @x, align 16 store <4 x i32> %add1, <4 x i32>* @x, align 16
ret void ret void
} }

llvm/test/CodeGen/X86/extractelement-fp.ll

Show First 20 Lines • Show All 322 Lines • ▼ Show 20 Lines
; X64-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero ; X64-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
; X64-NEXT: vandpd %xmm2, %xmm1, %xmm1 ; X64-NEXT: vandpd %xmm2, %xmm1, %xmm1
; X64-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; X64-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; X64-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,3,3] ; X64-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,3,3]
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-LABEL: extvselectsetcc_crash: ; X86-LABEL: extvselectsetcc_crash:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vcmpeqpd {{\.LCPI.*}}, %xmm0, %xmm1 ; X86-NEXT: vcmpeqpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm1
; X86-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero ; X86-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
; X86-NEXT: vandpd %xmm2, %xmm1, %xmm1 ; X86-NEXT: vandpd %xmm2, %xmm1, %xmm1
; X86-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; X86-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; X86-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,3,3] ; X86-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,3,3]
; X86-NEXT: retl ; X86-NEXT: retl
%cmp = fcmp oeq <2 x double> %x, <double 5.0, double 5.0> %cmp = fcmp oeq <2 x double> %x, <double 5.0, double 5.0>
%s = select <2 x i1> %cmp, <2 x double> <double 1.0, double undef>, <2 x double> <double 0.0, double undef> %s = select <2 x i1> %cmp, <2 x double> <double 1.0, double undef>, <2 x double> <double 0.0, double undef>
%r = shufflevector <2 x double> %s, <2 x double> %x, <3 x i32> <i32 0, i32 2, i32 3> %r = shufflevector <2 x double> %s, <2 x double> %x, <3 x i32> <i32 0, i32 2, i32 3>
▲ Show 20 Lines • Show All 211 Lines • ▼ Show 20 Lines
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-LABEL: fabs_v4f64: ; X86-LABEL: fabs_v4f64:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: pushl %ebp ; X86-NEXT: pushl %ebp
; X86-NEXT: movl %esp, %ebp ; X86-NEXT: movl %esp, %ebp
; X86-NEXT: andl $-8, %esp ; X86-NEXT: andl $-8, %esp
; X86-NEXT: subl $8, %esp ; X86-NEXT: subl $8, %esp
; X86-NEXT: vandps {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-NEXT: vmovlps %xmm0, (%esp) ; X86-NEXT: vmovlps %xmm0, (%esp)
; X86-NEXT: fldl (%esp) ; X86-NEXT: fldl (%esp)
; X86-NEXT: movl %ebp, %esp ; X86-NEXT: movl %ebp, %esp
; X86-NEXT: popl %ebp ; X86-NEXT: popl %ebp
; X86-NEXT: vzeroupper ; X86-NEXT: vzeroupper
; X86-NEXT: retl ; X86-NEXT: retl
%v = call <4 x double> @llvm.fabs.v4f64(<4 x double> %x) %v = call <4 x double> @llvm.fabs.v4f64(<4 x double> %x)
%r = extractelement <4 x double> %v, i32 0 %r = extractelement <4 x double> %v, i32 0
▲ Show 20 Lines • Show All 257 Lines • ▼ Show 20 Lines
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-LABEL: copysign_v4f64: ; X86-LABEL: copysign_v4f64:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: pushl %ebp ; X86-NEXT: pushl %ebp
; X86-NEXT: movl %esp, %ebp ; X86-NEXT: movl %esp, %ebp
; X86-NEXT: andl $-8, %esp ; X86-NEXT: andl $-8, %esp
; X86-NEXT: subl $8, %esp ; X86-NEXT: subl $8, %esp
; X86-NEXT: vandps {{\.LCPI.*}}, %xmm1, %xmm1 ; X86-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1
; X86-NEXT: vandps {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-NEXT: vorps %xmm1, %xmm0, %xmm0 ; X86-NEXT: vorps %xmm1, %xmm0, %xmm0
; X86-NEXT: vmovlps %xmm0, (%esp) ; X86-NEXT: vmovlps %xmm0, (%esp)
; X86-NEXT: fldl (%esp) ; X86-NEXT: fldl (%esp)
; X86-NEXT: movl %ebp, %esp ; X86-NEXT: movl %ebp, %esp
; X86-NEXT: popl %ebp ; X86-NEXT: popl %ebp
; X86-NEXT: vzeroupper ; X86-NEXT: vzeroupper
; X86-NEXT: retl ; X86-NEXT: retl
%v = call <4 x double> @llvm.copysign.v4f64(<4 x double> %x, <4 x double> %y) %v = call <4 x double> @llvm.copysign.v4f64(<4 x double> %x, <4 x double> %y)
▲ Show 20 Lines • Show All 263 Lines • ▼ Show 20 Lines
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-LABEL: round_v4f64: ; X86-LABEL: round_v4f64:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: pushl %ebp ; X86-NEXT: pushl %ebp
; X86-NEXT: movl %esp, %ebp ; X86-NEXT: movl %esp, %ebp
; X86-NEXT: andl $-8, %esp ; X86-NEXT: andl $-8, %esp
; X86-NEXT: subl $8, %esp ; X86-NEXT: subl $8, %esp
; X86-NEXT: vandpd {{\.LCPI.*}}, %xmm0, %xmm1 ; X86-NEXT: vandpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm1
; X86-NEXT: vmovddup {{.*#+}} xmm2 = [4.9999999999999994E-1,4.9999999999999994E-1] ; X86-NEXT: vmovddup {{.*#+}} xmm2 = [4.9999999999999994E-1,4.9999999999999994E-1]
; X86-NEXT: # xmm2 = mem[0,0] ; X86-NEXT: # xmm2 = mem[0,0]
; X86-NEXT: vorpd %xmm1, %xmm2, %xmm1 ; X86-NEXT: vorpd %xmm1, %xmm2, %xmm1
; X86-NEXT: vaddsd %xmm1, %xmm0, %xmm0 ; X86-NEXT: vaddsd %xmm1, %xmm0, %xmm0
; X86-NEXT: vroundsd $11, %xmm0, %xmm0, %xmm0 ; X86-NEXT: vroundsd $11, %xmm0, %xmm0, %xmm0
; X86-NEXT: vmovsd %xmm0, (%esp) ; X86-NEXT: vmovsd %xmm0, (%esp)
; X86-NEXT: fldl (%esp) ; X86-NEXT: fldl (%esp)
; X86-NEXT: movl %ebp, %esp ; X86-NEXT: movl %ebp, %esp
▲ Show 20 Lines • Show All 125 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/fast-isel-fneg.ll

Show All 12 Lines
; ;
; SSE2-LABEL: fneg_f64: ; SSE2-LABEL: fneg_f64:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: pushl %ebp ; SSE2-NEXT: pushl %ebp
; SSE2-NEXT: movl %esp, %ebp ; SSE2-NEXT: movl %esp, %ebp
; SSE2-NEXT: andl $-8, %esp ; SSE2-NEXT: andl $-8, %esp
; SSE2-NEXT: subl $8, %esp ; SSE2-NEXT: subl $8, %esp
; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; SSE2-NEXT: xorps {{\.LCPI.*}}, %xmm0 ; SSE2-NEXT: xorps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE2-NEXT: movlps %xmm0, (%esp) ; SSE2-NEXT: movlps %xmm0, (%esp)
; SSE2-NEXT: fldl (%esp) ; SSE2-NEXT: fldl (%esp)
; SSE2-NEXT: movl %ebp, %esp ; SSE2-NEXT: movl %ebp, %esp
; SSE2-NEXT: popl %ebp ; SSE2-NEXT: popl %ebp
; SSE2-NEXT: retl ; SSE2-NEXT: retl
%y = fneg double %x %y = fneg double %x
ret double %y ret double %y
} }
define float @fneg_f32(float %x) nounwind { define float @fneg_f32(float %x) nounwind {
; CHECK-LABEL: fneg_f32: ; CHECK-LABEL: fneg_f32:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
; CHECK-NEXT: movd %xmm0, %eax ; CHECK-NEXT: movd %xmm0, %eax
; CHECK-NEXT: xorl $2147483648, %eax ## imm = 0x80000000 ; CHECK-NEXT: xorl $2147483648, %eax ## imm = 0x80000000
; CHECK-NEXT: movd %eax, %xmm0 ; CHECK-NEXT: movd %eax, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; SSE2-LABEL: fneg_f32: ; SSE2-LABEL: fneg_f32:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: pushl %eax ; SSE2-NEXT: pushl %eax
; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: xorps {{\.LCPI.*}}, %xmm0 ; SSE2-NEXT: xorps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE2-NEXT: movss %xmm0, (%esp) ; SSE2-NEXT: movss %xmm0, (%esp)
; SSE2-NEXT: flds (%esp) ; SSE2-NEXT: flds (%esp)
; SSE2-NEXT: popl %eax ; SSE2-NEXT: popl %eax
; SSE2-NEXT: retl ; SSE2-NEXT: retl
%y = fneg float %x %y = fneg float %x
ret float %y ret float %y
} }
define void @fneg_f64_mem(double* %x, double* %y) nounwind { define void @fneg_f64_mem(double* %x, double* %y) nounwind {
; CHECK-LABEL: fneg_f64_mem: ; CHECK-LABEL: fneg_f64_mem:
; CHECK: ## %bb.0: ; CHECK: ## %bb.0:
; CHECK-NEXT: movq {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: movq %xmm0, %rax ; CHECK-NEXT: movq %xmm0, %rax
; CHECK-NEXT: movabsq $-9223372036854775808, %rcx ## imm = 0x8000000000000000 ; CHECK-NEXT: movabsq $-9223372036854775808, %rcx ## imm = 0x8000000000000000
; CHECK-NEXT: xorq %rax, %rcx ; CHECK-NEXT: xorq %rax, %rcx
; CHECK-NEXT: movq %rcx, %xmm0 ; CHECK-NEXT: movq %rcx, %xmm0
; CHECK-NEXT: movq %xmm0, (%rsi) ; CHECK-NEXT: movq %xmm0, (%rsi)
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; SSE2-LABEL: fneg_f64_mem: ; SSE2-LABEL: fneg_f64_mem:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
; SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx ; SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx
; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; SSE2-NEXT: xorps {{\.LCPI.*}}, %xmm0 ; SSE2-NEXT: xorps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE2-NEXT: movsd %xmm0, (%eax) ; SSE2-NEXT: movsd %xmm0, (%eax)
; SSE2-NEXT: retl ; SSE2-NEXT: retl
%a = load double, double* %x %a = load double, double* %x
%b = fneg double %a %b = fneg double %a
store double %b, double* %y store double %b, double* %y
ret void ret void
} }
Show All 25 Lines

llvm/test/CodeGen/X86/fildll.ll

Show All 30 Lines
; CHECK-NEXT: movl %esp, %ebp ; CHECK-NEXT: movl %esp, %ebp
; CHECK-NEXT: .cfi_def_cfa_register %ebp ; CHECK-NEXT: .cfi_def_cfa_register %ebp
; CHECK-NEXT: andl $-8, %esp ; CHECK-NEXT: andl $-8, %esp
; CHECK-NEXT: subl $16, %esp ; CHECK-NEXT: subl $16, %esp
; CHECK-NEXT: movl %edx, {{[0-9]+}}(%esp) ; CHECK-NEXT: movl %edx, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl %ecx, (%esp) ; CHECK-NEXT: movl %ecx, (%esp)
; CHECK-NEXT: shrl $31, %edx ; CHECK-NEXT: shrl $31, %edx
; CHECK-NEXT: fildll (%esp) ; CHECK-NEXT: fildll (%esp)
; CHECK-NEXT: fadds {{\.LCPI.*}}(,%edx,4) ; CHECK-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%edx,4)
; CHECK-NEXT: fstpl {{[0-9]+}}(%esp) ; CHECK-NEXT: fstpl {{[0-9]+}}(%esp)
; CHECK-NEXT: fldl {{[0-9]+}}(%esp) ; CHECK-NEXT: fldl {{[0-9]+}}(%esp)
; CHECK-NEXT: movl %ebp, %esp ; CHECK-NEXT: movl %ebp, %esp
; CHECK-NEXT: popl %ebp ; CHECK-NEXT: popl %ebp
; CHECK-NEXT: .cfi_def_cfa %esp, 4 ; CHECK-NEXT: .cfi_def_cfa %esp, 4
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%R = uitofp i64 %X to double ; <double> [#uses=1] %R = uitofp i64 %X to double ; <double> [#uses=1]
ret double %R ret double %R
} }

llvm/test/CodeGen/X86/fma-scalar-combine.ll

Show First 20 Lines • Show All 542 Lines • ▼ Show 20 Linesentry:
ret <2 x double> %8 ret <2 x double> %8
} }
; Don't fold into (fmul x, c1+c2) if reassoc not set ; Don't fold into (fmul x, c1+c2) if reassoc not set
define float @fma_const_fmul(float %x) { define float @fma_const_fmul(float %x) {
; CHECK-LABEL: fma_const_fmul: ; CHECK-LABEL: fma_const_fmul:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm1 # EVEX TO VEX Compression encoding: [0xc5,0xfa,0x59,0x0d,A,A,A,A] ; CHECK-NEXT: vmulss {{.*}}(%rip), %xmm0, %xmm1 # EVEX TO VEX Compression encoding: [0xc5,0xfa,0x59,0x0d,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; CHECK-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; CHECK-NEXT: vfmadd132ss {{.*}}(%rip), %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x71,0x99,0x05,A,A,A,A] ; CHECK-NEXT: vfmadd132ss {{.*}}(%rip), %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x71,0x99,0x05,A,A,A,A]
; CHECK-NEXT: # fixup A - offset: 5, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; CHECK-NEXT: # fixup A - offset: 5, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; CHECK-NEXT: # xmm0 = (xmm0 * mem) + xmm1 ; CHECK-NEXT: # xmm0 = (xmm0 * mem) + xmm1
; CHECK-NEXT: retq # encoding: [0xc3] ; CHECK-NEXT: retq # encoding: [0xc3]
%mul1 = fmul contract float %x, 10.0 %mul1 = fmul contract float %x, 10.0
%mul2 = fmul contract float %x, 11.0 %mul2 = fmul contract float %x, 11.0
%add1 = fadd contract float %mul1, %mul2 %add1 = fadd contract float %mul1, %mul2
ret float %add1 ret float %add1
} }

llvm/test/CodeGen/X86/fmf-flags.ll

Show All 32 Lines
; X64-LABEL: fast_fmuladd_opts: ; X64-LABEL: fast_fmuladd_opts:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: mulss {{.*}}(%rip), %xmm0 ; X64-NEXT: mulss {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-LABEL: fast_fmuladd_opts: ; X86-LABEL: fast_fmuladd_opts:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: flds {{[0-9]+}}(%esp) ; X86-NEXT: flds {{[0-9]+}}(%esp)
; X86-NEXT: fmuls {{\.LCPI.*}} ; X86-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; X86-NEXT: retl ; X86-NEXT: retl
%res = call fast float @llvm.fmuladd.f32(float %a, float 2.0, float %a) %res = call fast float @llvm.fmuladd.f32(float %a, float 2.0, float %a)
ret float %res ret float %res
} }
; The multiply is strict. ; The multiply is strict.
@mul1 = common dso_local global double 0.000000e+00, align 4 @mul1 = common dso_local global double 0.000000e+00, align 4
define dso_local double @not_so_fast_mul_add(double %x) { define dso_local double @not_so_fast_mul_add(double %x) {
; X64-LABEL: not_so_fast_mul_add: ; X64-LABEL: not_so_fast_mul_add:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero ; X64-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; X64-NEXT: mulsd %xmm0, %xmm1 ; X64-NEXT: mulsd %xmm0, %xmm1
; X64-NEXT: mulsd {{.*}}(%rip), %xmm0 ; X64-NEXT: mulsd {{.*}}(%rip), %xmm0
; X64-NEXT: movsd %xmm1, {{.*}}(%rip) ; X64-NEXT: movsd %xmm1, {{.*}}(%rip)
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-LABEL: not_so_fast_mul_add: ; X86-LABEL: not_so_fast_mul_add:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: fldl {{[0-9]+}}(%esp) ; X86-NEXT: fldl {{[0-9]+}}(%esp)
; X86-NEXT: fld %st(0) ; X86-NEXT: fld %st(0)
; X86-NEXT: fmull {{\.LCPI.*}} ; X86-NEXT: fmull {{\.LCPI[0-9]+_[0-9]+}}
; X86-NEXT: fxch %st(1) ; X86-NEXT: fxch %st(1)
; X86-NEXT: fmull {{\.LCPI.*}} ; X86-NEXT: fmull {{\.LCPI[0-9]+_[0-9]+}}
; X86-NEXT: fxch %st(1) ; X86-NEXT: fxch %st(1)
; X86-NEXT: fstpl mul1 ; X86-NEXT: fstpl mul1
; X86-NEXT: retl ; X86-NEXT: retl
%m = fmul double %x, 4.2 %m = fmul double %x, 4.2
%a = fadd fast double %m, %x %a = fadd fast double %m, %x
store double %m, double* @mul1, align 4 store double %m, double* @mul1, align 4
ret double %a ret double %a
} }
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; ;
; X86-LABEL: div_arcp_by_const: ; X86-LABEL: div_arcp_by_const:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: pushl %eax ; X86-NEXT: pushl %eax
; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl %eax, (%esp) ; X86-NEXT: movl %eax, (%esp)
; X86-NEXT: calll __gnu_h2f_ieee ; X86-NEXT: calll __gnu_h2f_ieee
; X86-NEXT: fmuls {{\.LCPI.*}} ; X86-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; X86-NEXT: fstps (%esp) ; X86-NEXT: fstps (%esp)
; X86-NEXT: calll __gnu_f2h_ieee ; X86-NEXT: calll __gnu_f2h_ieee
; X86-NEXT: movzwl %ax, %eax ; X86-NEXT: movzwl %ax, %eax
; X86-NEXT: movl %eax, (%esp) ; X86-NEXT: movl %eax, (%esp)
; X86-NEXT: calll __gnu_h2f_ieee ; X86-NEXT: calll __gnu_h2f_ieee
; X86-NEXT: popl %eax ; X86-NEXT: popl %eax
; X86-NEXT: .cfi_def_cfa_offset 4 ; X86-NEXT: .cfi_def_cfa_offset 4
; X86-NEXT: retl ; X86-NEXT: retl
%rcp = fdiv arcp half %x, 10.0 %rcp = fdiv arcp half %x, 10.0
%z = fpext half %rcp to float %z = fpext half %rcp to float
ret float %z ret float %z
} }

llvm/test/CodeGen/X86/fp-cvt.ll

Show First 20 Lines • Show All 437 Lines • ▼ Show 20 Lines
define i64 @fptoui_i64_fp80(x86_fp80 %a0) nounwind { define i64 @fptoui_i64_fp80(x86_fp80 %a0) nounwind {
; X86-LABEL: fptoui_i64_fp80: ; X86-LABEL: fptoui_i64_fp80:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: pushl %ebp ; X86-NEXT: pushl %ebp
; X86-NEXT: movl %esp, %ebp ; X86-NEXT: movl %esp, %ebp
; X86-NEXT: andl $-8, %esp ; X86-NEXT: andl $-8, %esp
; X86-NEXT: subl $16, %esp ; X86-NEXT: subl $16, %esp
; X86-NEXT: fldt 8(%ebp) ; X86-NEXT: fldt 8(%ebp)
; X86-NEXT: flds {{\.LCPI.*}} ; X86-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-NEXT: fucom %st(1) ; X86-NEXT: fucom %st(1)
; X86-NEXT: fnstsw %ax ; X86-NEXT: fnstsw %ax
; X86-NEXT: xorl %edx, %edx ; X86-NEXT: xorl %edx, %edx
; X86-NEXT: # kill: def $ah killed $ah killed $ax ; X86-NEXT: # kill: def $ah killed $ah killed $ax
; X86-NEXT: sahf ; X86-NEXT: sahf
; X86-NEXT: setbe %al ; X86-NEXT: setbe %al
; X86-NEXT: fldz ; X86-NEXT: fldz
; X86-NEXT: jbe .LBB10_2 ; X86-NEXT: jbe .LBB10_2
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; X86-LABEL: fptoui_i64_fp80_ld: ; X86-LABEL: fptoui_i64_fp80_ld:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: pushl %ebp ; X86-NEXT: pushl %ebp
; X86-NEXT: movl %esp, %ebp ; X86-NEXT: movl %esp, %ebp
; X86-NEXT: andl $-8, %esp ; X86-NEXT: andl $-8, %esp
; X86-NEXT: subl $16, %esp ; X86-NEXT: subl $16, %esp
; X86-NEXT: movl 8(%ebp), %eax ; X86-NEXT: movl 8(%ebp), %eax
; X86-NEXT: fldt (%eax) ; X86-NEXT: fldt (%eax)
; X86-NEXT: flds {{\.LCPI.*}} ; X86-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-NEXT: fucom %st(1) ; X86-NEXT: fucom %st(1)
; X86-NEXT: fnstsw %ax ; X86-NEXT: fnstsw %ax
; X86-NEXT: xorl %edx, %edx ; X86-NEXT: xorl %edx, %edx
; X86-NEXT: # kill: def $ah killed $ah killed $ax ; X86-NEXT: # kill: def $ah killed $ah killed $ax
; X86-NEXT: sahf ; X86-NEXT: sahf
; X86-NEXT: setbe %al ; X86-NEXT: setbe %al
; X86-NEXT: fldz ; X86-NEXT: fldz
; X86-NEXT: jbe .LBB11_2 ; X86-NEXT: jbe .LBB11_2
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; X86-NEXT: andl $-8, %esp ; X86-NEXT: andl $-8, %esp
; X86-NEXT: subl $8, %esp ; X86-NEXT: subl $8, %esp
; X86-NEXT: movl 8(%ebp), %eax ; X86-NEXT: movl 8(%ebp), %eax
; X86-NEXT: movl 12(%ebp), %ecx ; X86-NEXT: movl 12(%ebp), %ecx
; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) ; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X86-NEXT: movl %eax, (%esp) ; X86-NEXT: movl %eax, (%esp)
; X86-NEXT: shrl $31, %ecx ; X86-NEXT: shrl $31, %ecx
; X86-NEXT: fildll (%esp) ; X86-NEXT: fildll (%esp)
; X86-NEXT: fadds {{\.LCPI.*}}(,%ecx,4) ; X86-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; X86-NEXT: movl %ebp, %esp ; X86-NEXT: movl %ebp, %esp
; X86-NEXT: popl %ebp ; X86-NEXT: popl %ebp
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: uitofp_fp80_i64: ; X64-LABEL: uitofp_fp80_i64:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movq %rdi, -{{[0-9]+}}(%rsp) ; X64-NEXT: movq %rdi, -{{[0-9]+}}(%rsp)
; X64-NEXT: xorl %eax, %eax ; X64-NEXT: xorl %eax, %eax
; X64-NEXT: testq %rdi, %rdi ; X64-NEXT: testq %rdi, %rdi
; X64-NEXT: sets %al ; X64-NEXT: sets %al
; X64-NEXT: fildll -{{[0-9]+}}(%rsp) ; X64-NEXT: fildll -{{[0-9]+}}(%rsp)
; X64-NEXT: fadds {{\.LCPI.*}}(,%rax,4) ; X64-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%rax,4)
; X64-NEXT: retq ; X64-NEXT: retq
%1 = uitofp i64 %a0 to x86_fp80 %1 = uitofp i64 %a0 to x86_fp80
ret x86_fp80 %1 ret x86_fp80 %1
} }
define x86_fp80 @uitofp_fp80_i64_ld(i64 *%a0) nounwind { define x86_fp80 @uitofp_fp80_i64_ld(i64 *%a0) nounwind {
; X86-LABEL: uitofp_fp80_i64_ld: ; X86-LABEL: uitofp_fp80_i64_ld:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: pushl %ebp ; X86-NEXT: pushl %ebp
; X86-NEXT: movl %esp, %ebp ; X86-NEXT: movl %esp, %ebp
; X86-NEXT: andl $-8, %esp ; X86-NEXT: andl $-8, %esp
; X86-NEXT: subl $8, %esp ; X86-NEXT: subl $8, %esp
; X86-NEXT: movl 8(%ebp), %eax ; X86-NEXT: movl 8(%ebp), %eax
; X86-NEXT: movl (%eax), %ecx ; X86-NEXT: movl (%eax), %ecx
; X86-NEXT: movl 4(%eax), %eax ; X86-NEXT: movl 4(%eax), %eax
; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; X86-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X86-NEXT: movl %ecx, (%esp) ; X86-NEXT: movl %ecx, (%esp)
; X86-NEXT: shrl $31, %eax ; X86-NEXT: shrl $31, %eax
; X86-NEXT: fildll (%esp) ; X86-NEXT: fildll (%esp)
; X86-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; X86-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; X86-NEXT: movl %ebp, %esp ; X86-NEXT: movl %ebp, %esp
; X86-NEXT: popl %ebp ; X86-NEXT: popl %ebp
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: uitofp_fp80_i64_ld: ; X64-LABEL: uitofp_fp80_i64_ld:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movq (%rdi), %rax ; X64-NEXT: movq (%rdi), %rax
; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) ; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
; X64-NEXT: xorl %ecx, %ecx ; X64-NEXT: xorl %ecx, %ecx
; X64-NEXT: testq %rax, %rax ; X64-NEXT: testq %rax, %rax
; X64-NEXT: sets %cl ; X64-NEXT: sets %cl
; X64-NEXT: fildll -{{[0-9]+}}(%rsp) ; X64-NEXT: fildll -{{[0-9]+}}(%rsp)
; X64-NEXT: fadds {{\.LCPI.*}}(,%rcx,4) ; X64-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%rcx,4)
; X64-NEXT: retq ; X64-NEXT: retq
%1 = load i64, i64 *%a0 %1 = load i64, i64 *%a0
%2 = uitofp i64 %1 to x86_fp80 %2 = uitofp i64 %1 to x86_fp80
ret x86_fp80 %2 ret x86_fp80 %2
} }
; ;
; floor ; floor
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llvm/test/CodeGen/X86/fp-intrinsics.ll

Show All 12 Lines
; // Because 0.1 cannot be represented exactly, this shouldn't be folded. ; // Because 0.1 cannot be represented exactly, this shouldn't be folded.
; return 1.0/10.0; ; return 1.0/10.0;
; } ; }
; ;
define double @f1() #0 { define double @f1() #0 {
; X87-LABEL: f1: ; X87-LABEL: f1:
; X87: # %bb.0: # %entry ; X87: # %bb.0: # %entry
; X87-NEXT: fld1 ; X87-NEXT: fld1
; X87-NEXT: fdivs {{\.LCPI.*}} ; X87-NEXT: fdivs {{\.LCPI[0-9]+_[0-9]+}}
; X87-NEXT: wait ; X87-NEXT: wait
; X87-NEXT: retl ; X87-NEXT: retl
; ;
; X86-SSE-LABEL: f1: ; X86-SSE-LABEL: f1:
; X86-SSE: # %bb.0: # %entry ; X86-SSE: # %bb.0: # %entry
; X86-SSE-NEXT: subl $12, %esp ; X86-SSE-NEXT: subl $12, %esp
; X86-SSE-NEXT: .cfi_def_cfa_offset 16 ; X86-SSE-NEXT: .cfi_def_cfa_offset 16
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE-NEXT: divsd {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: divsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movsd %xmm0, (%esp) ; X86-SSE-NEXT: movsd %xmm0, (%esp)
; X86-SSE-NEXT: fldl (%esp) ; X86-SSE-NEXT: fldl (%esp)
; X86-SSE-NEXT: wait ; X86-SSE-NEXT: wait
; X86-SSE-NEXT: addl $12, %esp ; X86-SSE-NEXT: addl $12, %esp
; X86-SSE-NEXT: .cfi_def_cfa_offset 4 ; X86-SSE-NEXT: .cfi_def_cfa_offset 4
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; SSE-LABEL: f1: ; SSE-LABEL: f1:
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; X86-SSE-LABEL: f4: ; X86-SSE-LABEL: f4:
; X86-SSE: # %bb.0: # %entry ; X86-SSE: # %bb.0: # %entry
; X86-SSE-NEXT: subl $12, %esp ; X86-SSE-NEXT: subl $12, %esp
; X86-SSE-NEXT: .cfi_def_cfa_offset 16 ; X86-SSE-NEXT: .cfi_def_cfa_offset 16
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE-NEXT: cmpl $0, {{[0-9]+}}(%esp) ; X86-SSE-NEXT: cmpl $0, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: jle .LBB3_2 ; X86-SSE-NEXT: jle .LBB3_2
; X86-SSE-NEXT: # %bb.1: # %if.then ; X86-SSE-NEXT: # %bb.1: # %if.then
; X86-SSE-NEXT: addsd {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: addsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: .LBB3_2: # %if.end ; X86-SSE-NEXT: .LBB3_2: # %if.end
; X86-SSE-NEXT: movsd %xmm0, (%esp) ; X86-SSE-NEXT: movsd %xmm0, (%esp)
; X86-SSE-NEXT: fldl (%esp) ; X86-SSE-NEXT: fldl (%esp)
; X86-SSE-NEXT: wait ; X86-SSE-NEXT: wait
; X86-SSE-NEXT: addl $12, %esp ; X86-SSE-NEXT: addl $12, %esp
; X86-SSE-NEXT: .cfi_def_cfa_offset 4 ; X86-SSE-NEXT: .cfi_def_cfa_offset 4
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
Show All 29 Linesif.end:
%a.0 = phi double [%add, %if.then], [ %a, %entry ] %a.0 = phi double [%add, %if.then], [ %a, %entry ]
ret double %a.0 ret double %a.0
} }
; Verify that sqrt(42.0) isn't simplified when the rounding mode is unknown. ; Verify that sqrt(42.0) isn't simplified when the rounding mode is unknown.
define double @f5() #0 { define double @f5() #0 {
; X87-LABEL: f5: ; X87-LABEL: f5:
; X87: # %bb.0: # %entry ; X87: # %bb.0: # %entry
; X87-NEXT: flds {{\.LCPI.*}} ; X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fsqrt ; X87-NEXT: fsqrt
; X87-NEXT: wait ; X87-NEXT: wait
; X87-NEXT: retl ; X87-NEXT: retl
; ;
; X86-SSE-LABEL: f5: ; X86-SSE-LABEL: f5:
; X86-SSE: # %bb.0: # %entry ; X86-SSE: # %bb.0: # %entry
; X86-SSE-NEXT: subl $12, %esp ; X86-SSE-NEXT: subl $12, %esp
; X86-SSE-NEXT: .cfi_def_cfa_offset 16 ; X86-SSE-NEXT: .cfi_def_cfa_offset 16
Show All 25 Lines
} }
; Verify that pow(42.1, 3.0) isn't simplified when the rounding mode is unknown. ; Verify that pow(42.1, 3.0) isn't simplified when the rounding mode is unknown.
define double @f6() #0 { define double @f6() #0 {
; X87-LABEL: f6: ; X87-LABEL: f6:
; X87: # %bb.0: # %entry ; X87: # %bb.0: # %entry
; X87-NEXT: subl $28, %esp ; X87-NEXT: subl $28, %esp
; X87-NEXT: .cfi_def_cfa_offset 32 ; X87-NEXT: .cfi_def_cfa_offset 32
; X87-NEXT: flds {{\.LCPI.*}} ; X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fstpl {{[0-9]+}}(%esp) ; X87-NEXT: fstpl {{[0-9]+}}(%esp)
; X87-NEXT: fldl {{\.LCPI.*}} ; X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fstpl (%esp) ; X87-NEXT: fstpl (%esp)
; X87-NEXT: wait ; X87-NEXT: wait
; X87-NEXT: calll pow ; X87-NEXT: calll pow
; X87-NEXT: addl $28, %esp ; X87-NEXT: addl $28, %esp
; X87-NEXT: .cfi_def_cfa_offset 4 ; X87-NEXT: .cfi_def_cfa_offset 4
; X87-NEXT: retl ; X87-NEXT: retl
; ;
; X86-SSE-LABEL: f6: ; X86-SSE-LABEL: f6:
Show All 39 Lines
} }
; Verify that powi(42.1, 3) isn't simplified when the rounding mode is unknown. ; Verify that powi(42.1, 3) isn't simplified when the rounding mode is unknown.
define double @f7() #0 { define double @f7() #0 {
; X87-LABEL: f7: ; X87-LABEL: f7:
; X87: # %bb.0: # %entry ; X87: # %bb.0: # %entry
; X87-NEXT: subl $12, %esp ; X87-NEXT: subl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 16 ; X87-NEXT: .cfi_def_cfa_offset 16
; X87-NEXT: fldl {{\.LCPI.*}} ; X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fstpl (%esp) ; X87-NEXT: fstpl (%esp)
; X87-NEXT: wait ; X87-NEXT: wait
; X87-NEXT: movl $3, {{[0-9]+}}(%esp) ; X87-NEXT: movl $3, {{[0-9]+}}(%esp)
; X87-NEXT: calll __powidf2 ; X87-NEXT: calll __powidf2
; X87-NEXT: addl $12, %esp ; X87-NEXT: addl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 4 ; X87-NEXT: .cfi_def_cfa_offset 4
; X87-NEXT: retl ; X87-NEXT: retl
; ;
Show All 39 Lines
} }
; Verify that sin(42.0) isn't simplified when the rounding mode is unknown. ; Verify that sin(42.0) isn't simplified when the rounding mode is unknown.
define double @f8() #0 { define double @f8() #0 {
; X87-LABEL: f8: ; X87-LABEL: f8:
; X87: # %bb.0: # %entry ; X87: # %bb.0: # %entry
; X87-NEXT: subl $12, %esp ; X87-NEXT: subl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 16 ; X87-NEXT: .cfi_def_cfa_offset 16
; X87-NEXT: flds {{\.LCPI.*}} ; X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fstpl (%esp) ; X87-NEXT: fstpl (%esp)
; X87-NEXT: wait ; X87-NEXT: wait
; X87-NEXT: calll sin ; X87-NEXT: calll sin
; X87-NEXT: addl $12, %esp ; X87-NEXT: addl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 4 ; X87-NEXT: .cfi_def_cfa_offset 4
; X87-NEXT: retl ; X87-NEXT: retl
; ;
; X86-SSE-LABEL: f8: ; X86-SSE-LABEL: f8:
Show All 34 Lines
} }
; Verify that cos(42.0) isn't simplified when the rounding mode is unknown. ; Verify that cos(42.0) isn't simplified when the rounding mode is unknown.
define double @f9() #0 { define double @f9() #0 {
; X87-LABEL: f9: ; X87-LABEL: f9:
; X87: # %bb.0: # %entry ; X87: # %bb.0: # %entry
; X87-NEXT: subl $12, %esp ; X87-NEXT: subl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 16 ; X87-NEXT: .cfi_def_cfa_offset 16
; X87-NEXT: flds {{\.LCPI.*}} ; X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fstpl (%esp) ; X87-NEXT: fstpl (%esp)
; X87-NEXT: wait ; X87-NEXT: wait
; X87-NEXT: calll cos ; X87-NEXT: calll cos
; X87-NEXT: addl $12, %esp ; X87-NEXT: addl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 4 ; X87-NEXT: .cfi_def_cfa_offset 4
; X87-NEXT: retl ; X87-NEXT: retl
; ;
; X86-SSE-LABEL: f9: ; X86-SSE-LABEL: f9:
Show All 34 Lines
} }
; Verify that exp(42.0) isn't simplified when the rounding mode is unknown. ; Verify that exp(42.0) isn't simplified when the rounding mode is unknown.
define double @f10() #0 { define double @f10() #0 {
; X87-LABEL: f10: ; X87-LABEL: f10:
; X87: # %bb.0: # %entry ; X87: # %bb.0: # %entry
; X87-NEXT: subl $12, %esp ; X87-NEXT: subl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 16 ; X87-NEXT: .cfi_def_cfa_offset 16
; X87-NEXT: flds {{\.LCPI.*}} ; X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fstpl (%esp) ; X87-NEXT: fstpl (%esp)
; X87-NEXT: wait ; X87-NEXT: wait
; X87-NEXT: calll exp ; X87-NEXT: calll exp
; X87-NEXT: addl $12, %esp ; X87-NEXT: addl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 4 ; X87-NEXT: .cfi_def_cfa_offset 4
; X87-NEXT: retl ; X87-NEXT: retl
; ;
; X86-SSE-LABEL: f10: ; X86-SSE-LABEL: f10:
Show All 34 Lines
} }
; Verify that exp2(42.1) isn't simplified when the rounding mode is unknown. ; Verify that exp2(42.1) isn't simplified when the rounding mode is unknown.
define double @f11() #0 { define double @f11() #0 {
; X87-LABEL: f11: ; X87-LABEL: f11:
; X87: # %bb.0: # %entry ; X87: # %bb.0: # %entry
; X87-NEXT: subl $12, %esp ; X87-NEXT: subl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 16 ; X87-NEXT: .cfi_def_cfa_offset 16
; X87-NEXT: fldl {{\.LCPI.*}} ; X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fstpl (%esp) ; X87-NEXT: fstpl (%esp)
; X87-NEXT: wait ; X87-NEXT: wait
; X87-NEXT: calll exp2 ; X87-NEXT: calll exp2
; X87-NEXT: addl $12, %esp ; X87-NEXT: addl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 4 ; X87-NEXT: .cfi_def_cfa_offset 4
; X87-NEXT: retl ; X87-NEXT: retl
; ;
; X86-SSE-LABEL: f11: ; X86-SSE-LABEL: f11:
Show All 34 Lines
} }
; Verify that log(42.0) isn't simplified when the rounding mode is unknown. ; Verify that log(42.0) isn't simplified when the rounding mode is unknown.
define double @f12() #0 { define double @f12() #0 {
; X87-LABEL: f12: ; X87-LABEL: f12:
; X87: # %bb.0: # %entry ; X87: # %bb.0: # %entry
; X87-NEXT: subl $12, %esp ; X87-NEXT: subl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 16 ; X87-NEXT: .cfi_def_cfa_offset 16
; X87-NEXT: flds {{\.LCPI.*}} ; X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fstpl (%esp) ; X87-NEXT: fstpl (%esp)
; X87-NEXT: wait ; X87-NEXT: wait
; X87-NEXT: calll log ; X87-NEXT: calll log
; X87-NEXT: addl $12, %esp ; X87-NEXT: addl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 4 ; X87-NEXT: .cfi_def_cfa_offset 4
; X87-NEXT: retl ; X87-NEXT: retl
; ;
; X86-SSE-LABEL: f12: ; X86-SSE-LABEL: f12:
Show All 34 Lines
} }
; Verify that log10(42.0) isn't simplified when the rounding mode is unknown. ; Verify that log10(42.0) isn't simplified when the rounding mode is unknown.
define double @f13() #0 { define double @f13() #0 {
; X87-LABEL: f13: ; X87-LABEL: f13:
; X87: # %bb.0: # %entry ; X87: # %bb.0: # %entry
; X87-NEXT: subl $12, %esp ; X87-NEXT: subl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 16 ; X87-NEXT: .cfi_def_cfa_offset 16
; X87-NEXT: flds {{\.LCPI.*}} ; X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fstpl (%esp) ; X87-NEXT: fstpl (%esp)
; X87-NEXT: wait ; X87-NEXT: wait
; X87-NEXT: calll log10 ; X87-NEXT: calll log10
; X87-NEXT: addl $12, %esp ; X87-NEXT: addl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 4 ; X87-NEXT: .cfi_def_cfa_offset 4
; X87-NEXT: retl ; X87-NEXT: retl
; ;
; X86-SSE-LABEL: f13: ; X86-SSE-LABEL: f13:
Show All 34 Lines
} }
; Verify that log2(42.0) isn't simplified when the rounding mode is unknown. ; Verify that log2(42.0) isn't simplified when the rounding mode is unknown.
define double @f14() #0 { define double @f14() #0 {
; X87-LABEL: f14: ; X87-LABEL: f14:
; X87: # %bb.0: # %entry ; X87: # %bb.0: # %entry
; X87-NEXT: subl $12, %esp ; X87-NEXT: subl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 16 ; X87-NEXT: .cfi_def_cfa_offset 16
; X87-NEXT: flds {{\.LCPI.*}} ; X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fstpl (%esp) ; X87-NEXT: fstpl (%esp)
; X87-NEXT: wait ; X87-NEXT: wait
; X87-NEXT: calll log2 ; X87-NEXT: calll log2
; X87-NEXT: addl $12, %esp ; X87-NEXT: addl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 4 ; X87-NEXT: .cfi_def_cfa_offset 4
; X87-NEXT: retl ; X87-NEXT: retl
; ;
; X86-SSE-LABEL: f14: ; X86-SSE-LABEL: f14:
Show All 34 Lines
} }
; Verify that rint(42.1) isn't simplified when the rounding mode is unknown. ; Verify that rint(42.1) isn't simplified when the rounding mode is unknown.
define double @f15() #0 { define double @f15() #0 {
; X87-LABEL: f15: ; X87-LABEL: f15:
; X87: # %bb.0: # %entry ; X87: # %bb.0: # %entry
; X87-NEXT: subl $12, %esp ; X87-NEXT: subl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 16 ; X87-NEXT: .cfi_def_cfa_offset 16
; X87-NEXT: fldl {{\.LCPI.*}} ; X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fstpl (%esp) ; X87-NEXT: fstpl (%esp)
; X87-NEXT: wait ; X87-NEXT: wait
; X87-NEXT: calll rint ; X87-NEXT: calll rint
; X87-NEXT: addl $12, %esp ; X87-NEXT: addl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 4 ; X87-NEXT: .cfi_def_cfa_offset 4
; X87-NEXT: retl ; X87-NEXT: retl
; ;
; X86-SSE-LABEL: f15: ; X86-SSE-LABEL: f15:
Show All 31 Lines
; Verify that nearbyint(42.1) isn't simplified when the rounding mode is ; Verify that nearbyint(42.1) isn't simplified when the rounding mode is
; unknown. ; unknown.
define double @f16() #0 { define double @f16() #0 {
; X87-LABEL: f16: ; X87-LABEL: f16:
; X87: # %bb.0: # %entry ; X87: # %bb.0: # %entry
; X87-NEXT: subl $12, %esp ; X87-NEXT: subl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 16 ; X87-NEXT: .cfi_def_cfa_offset 16
; X87-NEXT: fldl {{\.LCPI.*}} ; X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fstpl (%esp) ; X87-NEXT: fstpl (%esp)
; X87-NEXT: wait ; X87-NEXT: wait
; X87-NEXT: calll nearbyint ; X87-NEXT: calll nearbyint
; X87-NEXT: addl $12, %esp ; X87-NEXT: addl $12, %esp
; X87-NEXT: .cfi_def_cfa_offset 4 ; X87-NEXT: .cfi_def_cfa_offset 4
; X87-NEXT: retl ; X87-NEXT: retl
; ;
; X86-SSE-LABEL: f16: ; X86-SSE-LABEL: f16:
Show All 30 Linesentry:
ret double %result ret double %result
} }
define double @f19() #0 { define double @f19() #0 {
; X87-LABEL: f19: ; X87-LABEL: f19:
; X87: # %bb.0: # %entry ; X87: # %bb.0: # %entry
; X87-NEXT: subl $28, %esp ; X87-NEXT: subl $28, %esp
; X87-NEXT: .cfi_def_cfa_offset 32 ; X87-NEXT: .cfi_def_cfa_offset 32
; X87-NEXT: flds {{\.LCPI.*}} ; X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fstpl {{[0-9]+}}(%esp) ; X87-NEXT: fstpl {{[0-9]+}}(%esp)
; X87-NEXT: wait ; X87-NEXT: wait
; X87-NEXT: movl $1072693248, {{[0-9]+}}(%esp) # imm = 0x3FF00000 ; X87-NEXT: movl $1072693248, {{[0-9]+}}(%esp) # imm = 0x3FF00000
; X87-NEXT: movl $0, (%esp) ; X87-NEXT: movl $0, (%esp)
; X87-NEXT: calll fmod ; X87-NEXT: calll fmod
; X87-NEXT: addl $28, %esp ; X87-NEXT: addl $28, %esp
; X87-NEXT: .cfi_def_cfa_offset 4 ; X87-NEXT: .cfi_def_cfa_offset 4
; X87-NEXT: retl ; X87-NEXT: retl
▲ Show 20 Lines • Show All 476 Lines • ▼ Show 20 Lines
; Verify that no gross errors happen. ; Verify that no gross errors happen.
; FIXME: This code generates spurious inexact exceptions. ; FIXME: This code generates spurious inexact exceptions.
define i64 @f20u64(double %x) #0 { define i64 @f20u64(double %x) #0 {
; X87-LABEL: f20u64: ; X87-LABEL: f20u64:
; X87: # %bb.0: # %entry ; X87: # %bb.0: # %entry
; X87-NEXT: subl $20, %esp ; X87-NEXT: subl $20, %esp
; X87-NEXT: .cfi_def_cfa_offset 24 ; X87-NEXT: .cfi_def_cfa_offset 24
; X87-NEXT: fldl {{[0-9]+}}(%esp) ; X87-NEXT: fldl {{[0-9]+}}(%esp)
; X87-NEXT: flds {{\.LCPI.*}} ; X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X87-NEXT: wait ; X87-NEXT: wait
; X87-NEXT: xorl %edx, %edx ; X87-NEXT: xorl %edx, %edx
; X87-NEXT: fcomi %st(1), %st ; X87-NEXT: fcomi %st(1), %st
; X87-NEXT: wait ; X87-NEXT: wait
; X87-NEXT: setbe %dl ; X87-NEXT: setbe %dl
; X87-NEXT: fldz ; X87-NEXT: fldz
; X87-NEXT: fcmovbe %st(1), %st ; X87-NEXT: fcmovbe %st(1), %st
; X87-NEXT: fstp %st(1) ; X87-NEXT: fstp %st(1)
▲ Show 20 Lines • Show All 168 Lines • ▼ Show 20 Lines
; Verify that round(42.1) isn't simplified when the rounding mode is ; Verify that round(42.1) isn't simplified when the rounding mode is
; unknown. ; unknown.
; Verify that no gross errors happen. ; Verify that no gross errors happen.
define float @f21() #0 { define float @f21() #0 {
; X87-LABEL: f21: ; X87-LABEL: f21:
; X87: # %bb.0: # %entry ; X87: # %bb.0: # %entry
; X87-NEXT: pushl %eax ; X87-NEXT: pushl %eax
; X87-NEXT: .cfi_def_cfa_offset 8 ; X87-NEXT: .cfi_def_cfa_offset 8
; X87-NEXT: fldl {{\.LCPI.*}} ; X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fstps (%esp) ; X87-NEXT: fstps (%esp)
; X87-NEXT: flds (%esp) ; X87-NEXT: flds (%esp)
; X87-NEXT: wait ; X87-NEXT: wait
; X87-NEXT: popl %eax ; X87-NEXT: popl %eax
; X87-NEXT: .cfi_def_cfa_offset 4 ; X87-NEXT: .cfi_def_cfa_offset 4
; X87-NEXT: retl ; X87-NEXT: retl
; ;
; X86-SSE-LABEL: f21: ; X86-SSE-LABEL: f21:
▲ Show 20 Lines • Show All 879 Lines • ▼ Show 20 Lines
; X87-NEXT: .cfi_def_cfa_offset 4 ; X87-NEXT: .cfi_def_cfa_offset 4
; X87-NEXT: retl ; X87-NEXT: retl
; ;
; X86-SSE-LABEL: uifdi: ; X86-SSE-LABEL: uifdi:
; X86-SSE: # %bb.0: # %entry ; X86-SSE: # %bb.0: # %entry
; X86-SSE-NEXT: subl $12, %esp ; X86-SSE-NEXT: subl $12, %esp
; X86-SSE-NEXT: .cfi_def_cfa_offset 16 ; X86-SSE-NEXT: .cfi_def_cfa_offset 16
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: orpd {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: orpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: subsd {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: subsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movsd %xmm0, (%esp) ; X86-SSE-NEXT: movsd %xmm0, (%esp)
; X86-SSE-NEXT: fldl (%esp) ; X86-SSE-NEXT: fldl (%esp)
; X86-SSE-NEXT: wait ; X86-SSE-NEXT: wait
; X86-SSE-NEXT: addl $12, %esp ; X86-SSE-NEXT: addl $12, %esp
; X86-SSE-NEXT: .cfi_def_cfa_offset 4 ; X86-SSE-NEXT: .cfi_def_cfa_offset 4
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; SSE-LABEL: uifdi: ; SSE-LABEL: uifdi:
Show All 25 Lines
; X87-NEXT: subl $20, %esp ; X87-NEXT: subl $20, %esp
; X87-NEXT: .cfi_def_cfa_offset 24 ; X87-NEXT: .cfi_def_cfa_offset 24
; X87-NEXT: movl {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
; X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp) ; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X87-NEXT: movl %eax, (%esp) ; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: shrl $31, %ecx ; X87-NEXT: shrl $31, %ecx
; X87-NEXT: fildll (%esp) ; X87-NEXT: fildll (%esp)
; X87-NEXT: fadds {{\.LCPI.*}}(,%ecx,4) ; X87-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; X87-NEXT: fstpl {{[0-9]+}}(%esp) ; X87-NEXT: fstpl {{[0-9]+}}(%esp)
; X87-NEXT: fldl {{[0-9]+}}(%esp) ; X87-NEXT: fldl {{[0-9]+}}(%esp)
; X87-NEXT: wait ; X87-NEXT: wait
; X87-NEXT: addl $20, %esp ; X87-NEXT: addl $20, %esp
; X87-NEXT: .cfi_def_cfa_offset 4 ; X87-NEXT: .cfi_def_cfa_offset 4
; X87-NEXT: retl ; X87-NEXT: retl
; ;
; X86-SSE-LABEL: uifdl: ; X86-SSE-LABEL: uifdl:
; X86-SSE: # %bb.0: # %entry ; X86-SSE: # %bb.0: # %entry
; X86-SSE-NEXT: subl $28, %esp ; X86-SSE-NEXT: subl $28, %esp
; X86-SSE-NEXT: .cfi_def_cfa_offset 32 ; X86-SSE-NEXT: .cfi_def_cfa_offset 32
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE-NEXT: movlps %xmm0, {{[0-9]+}}(%esp) ; X86-SSE-NEXT: movlps %xmm0, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: shrl $31, %eax ; X86-SSE-NEXT: shrl $31, %eax
; X86-SSE-NEXT: fildll {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fildll {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; X86-SSE-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; X86-SSE-NEXT: fstpl {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fstpl {{[0-9]+}}(%esp)
; X86-SSE-NEXT: wait ; X86-SSE-NEXT: wait
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE-NEXT: movsd %xmm0, (%esp) ; X86-SSE-NEXT: movsd %xmm0, (%esp)
; X86-SSE-NEXT: fldl (%esp) ; X86-SSE-NEXT: fldl (%esp)
; X86-SSE-NEXT: wait ; X86-SSE-NEXT: wait
; X86-SSE-NEXT: addl $28, %esp ; X86-SSE-NEXT: addl $28, %esp
; X86-SSE-NEXT: .cfi_def_cfa_offset 4 ; X86-SSE-NEXT: .cfi_def_cfa_offset 4
▲ Show 20 Lines • Show All 144 Lines • ▼ Show 20 Lines
; X87-NEXT: .cfi_def_cfa_offset 4 ; X87-NEXT: .cfi_def_cfa_offset 4
; X87-NEXT: retl ; X87-NEXT: retl
; ;
; X86-SSE-LABEL: uiffi: ; X86-SSE-LABEL: uiffi:
; X86-SSE: # %bb.0: # %entry ; X86-SSE: # %bb.0: # %entry
; X86-SSE-NEXT: pushl %eax ; X86-SSE-NEXT: pushl %eax
; X86-SSE-NEXT: .cfi_def_cfa_offset 8 ; X86-SSE-NEXT: .cfi_def_cfa_offset 8
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: orpd {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: orpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: subsd {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: subsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: cvtsd2ss %xmm0, %xmm0 ; X86-SSE-NEXT: cvtsd2ss %xmm0, %xmm0
; X86-SSE-NEXT: movss %xmm0, (%esp) ; X86-SSE-NEXT: movss %xmm0, (%esp)
; X86-SSE-NEXT: flds (%esp) ; X86-SSE-NEXT: flds (%esp)
; X86-SSE-NEXT: wait ; X86-SSE-NEXT: wait
; X86-SSE-NEXT: popl %eax ; X86-SSE-NEXT: popl %eax
; X86-SSE-NEXT: .cfi_def_cfa_offset 4 ; X86-SSE-NEXT: .cfi_def_cfa_offset 4
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
Show All 26 Lines
; X87-NEXT: subl $20, %esp ; X87-NEXT: subl $20, %esp
; X87-NEXT: .cfi_def_cfa_offset 24 ; X87-NEXT: .cfi_def_cfa_offset 24
; X87-NEXT: movl {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
; X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp) ; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X87-NEXT: movl %eax, {{[0-9]+}}(%esp) ; X87-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X87-NEXT: shrl $31, %ecx ; X87-NEXT: shrl $31, %ecx
; X87-NEXT: fildll {{[0-9]+}}(%esp) ; X87-NEXT: fildll {{[0-9]+}}(%esp)
; X87-NEXT: fadds {{\.LCPI.*}}(,%ecx,4) ; X87-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; X87-NEXT: fstps {{[0-9]+}}(%esp) ; X87-NEXT: fstps {{[0-9]+}}(%esp)
; X87-NEXT: flds {{[0-9]+}}(%esp) ; X87-NEXT: flds {{[0-9]+}}(%esp)
; X87-NEXT: wait ; X87-NEXT: wait
; X87-NEXT: addl $20, %esp ; X87-NEXT: addl $20, %esp
; X87-NEXT: .cfi_def_cfa_offset 4 ; X87-NEXT: .cfi_def_cfa_offset 4
; X87-NEXT: retl ; X87-NEXT: retl
; ;
; X86-SSE-LABEL: uiffl: ; X86-SSE-LABEL: uiffl:
; X86-SSE: # %bb.0: # %entry ; X86-SSE: # %bb.0: # %entry
; X86-SSE-NEXT: subl $20, %esp ; X86-SSE-NEXT: subl $20, %esp
; X86-SSE-NEXT: .cfi_def_cfa_offset 24 ; X86-SSE-NEXT: .cfi_def_cfa_offset 24
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE-NEXT: movlps %xmm0, {{[0-9]+}}(%esp) ; X86-SSE-NEXT: movlps %xmm0, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: shrl $31, %eax ; X86-SSE-NEXT: shrl $31, %eax
; X86-SSE-NEXT: fildll {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fildll {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; X86-SSE-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; X86-SSE-NEXT: fstps {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fstps {{[0-9]+}}(%esp)
; X86-SSE-NEXT: wait ; X86-SSE-NEXT: wait
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: movss %xmm0, (%esp) ; X86-SSE-NEXT: movss %xmm0, (%esp)
; X86-SSE-NEXT: flds (%esp) ; X86-SSE-NEXT: flds (%esp)
; X86-SSE-NEXT: wait ; X86-SSE-NEXT: wait
; X86-SSE-NEXT: addl $20, %esp ; X86-SSE-NEXT: addl $20, %esp
; X86-SSE-NEXT: .cfi_def_cfa_offset 4 ; X86-SSE-NEXT: .cfi_def_cfa_offset 4
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llvm/test/CodeGen/X86/fp-stack-set-st1.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s ; RUN: llc < %s -mtriple=i686-- | FileCheck %s
define i32 @main() nounwind { define i32 @main() nounwind {
; CHECK-LABEL: main: ; CHECK-LABEL: main:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fldl {{\.LCPI.*}} ; CHECK-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
; CHECK-NEXT: fldl {{\.LCPI.*}} ; CHECK-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
; CHECK-NEXT: fxch %st(1) ; CHECK-NEXT: fxch %st(1)
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: fmul %st(1), %st ; CHECK-NEXT: fmul %st(1), %st
; CHECK-NEXT: fst %st(1) ; CHECK-NEXT: fst %st(1)
; CHECK-NEXT: frndint ; CHECK-NEXT: frndint
; CHECK-NEXT: fxch %st(1) ; CHECK-NEXT: fxch %st(1)
; CHECK-NEXT: fsub %st(1), %st ; CHECK-NEXT: fsub %st(1), %st
; CHECK-NEXT: f2xm1 ; CHECK-NEXT: f2xm1
; CHECK-EMPTY: ; CHECK-EMPTY:
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: fstp %st(0) ; CHECK-NEXT: fstp %st(0)
; CHECK-NEXT: fstp %st(0) ; CHECK-NEXT: fstp %st(0)
entry: entry:
%asmtmp = tail call { double, double } asm sideeffect "fmul\09%st(1),%st\0A\09fst\09%st(1)\0A\09frndint\0A\09fxch %st(1)\0A\09fsub\09%st(1),%st\0A\09f2xm1\0A\09", "={st},={st(1)},0,1,~{dirflag},~{fpsr},~{flags}"(double 0x4030FEFBD582097D, double 4.620000e+01) nounwind ; <{ double, double }> [#uses=0] %asmtmp = tail call { double, double } asm sideeffect "fmul\09%st(1),%st\0A\09fst\09%st(1)\0A\09frndint\0A\09fxch %st(1)\0A\09fsub\09%st(1),%st\0A\09f2xm1\0A\09", "={st},={st(1)},0,1,~{dirflag},~{fpsr},~{flags}"(double 0x4030FEFBD582097D, double 4.620000e+01) nounwind ; <{ double, double }> [#uses=0]
unreachable unreachable
} }

llvm/test/CodeGen/X86/fp-strict-scalar-fptoint.ll

Show First 20 Lines • Show All 673 Lines • ▼ Show 20 Lines
; X87-NEXT: pushl %ebp ; X87-NEXT: pushl %ebp
; X87-NEXT: .cfi_def_cfa_offset 8 ; X87-NEXT: .cfi_def_cfa_offset 8
; X87-NEXT: .cfi_offset %ebp, -8 ; X87-NEXT: .cfi_offset %ebp, -8
; X87-NEXT: movl %esp, %ebp ; X87-NEXT: movl %esp, %ebp
; X87-NEXT: .cfi_def_cfa_register %ebp ; X87-NEXT: .cfi_def_cfa_register %ebp
; X87-NEXT: andl $-8, %esp ; X87-NEXT: andl $-8, %esp
; X87-NEXT: subl $16, %esp ; X87-NEXT: subl $16, %esp
; X87-NEXT: flds 8(%ebp) ; X87-NEXT: flds 8(%ebp)
; X87-NEXT: flds {{\.LCPI.*}} ; X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fcom %st(1) ; X87-NEXT: fcom %st(1)
; X87-NEXT: wait ; X87-NEXT: wait
; X87-NEXT: fnstsw %ax ; X87-NEXT: fnstsw %ax
; X87-NEXT: xorl %edx, %edx ; X87-NEXT: xorl %edx, %edx
; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax
; X87-NEXT: sahf ; X87-NEXT: sahf
; X87-NEXT: setbe %al ; X87-NEXT: setbe %al
; X87-NEXT: fldz ; X87-NEXT: fldz
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; X87-NEXT: pushl %ebp ; X87-NEXT: pushl %ebp
; X87-NEXT: .cfi_def_cfa_offset 8 ; X87-NEXT: .cfi_def_cfa_offset 8
; X87-NEXT: .cfi_offset %ebp, -8 ; X87-NEXT: .cfi_offset %ebp, -8
; X87-NEXT: movl %esp, %ebp ; X87-NEXT: movl %esp, %ebp
; X87-NEXT: .cfi_def_cfa_register %ebp ; X87-NEXT: .cfi_def_cfa_register %ebp
; X87-NEXT: andl $-8, %esp ; X87-NEXT: andl $-8, %esp
; X87-NEXT: subl $16, %esp ; X87-NEXT: subl $16, %esp
; X87-NEXT: fldl 8(%ebp) ; X87-NEXT: fldl 8(%ebp)
; X87-NEXT: flds {{\.LCPI.*}} ; X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X87-NEXT: fcom %st(1) ; X87-NEXT: fcom %st(1)
; X87-NEXT: wait ; X87-NEXT: wait
; X87-NEXT: fnstsw %ax ; X87-NEXT: fnstsw %ax
; X87-NEXT: xorl %edx, %edx ; X87-NEXT: xorl %edx, %edx
; X87-NEXT: # kill: def $ah killed $ah killed $ax ; X87-NEXT: # kill: def $ah killed $ah killed $ax
; X87-NEXT: sahf ; X87-NEXT: sahf
; X87-NEXT: setbe %al ; X87-NEXT: setbe %al
; X87-NEXT: fldz ; X87-NEXT: fldz
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llvm/test/CodeGen/X86/fp-strict-scalar-inttofp.ll

Show First 20 Lines • Show All 482 Lines • ▼ Show 20 Lines
} }
define float @uitofp_i32tof32(i32 %x) #0 { define float @uitofp_i32tof32(i32 %x) #0 {
; SSE-X86-LABEL: uitofp_i32tof32: ; SSE-X86-LABEL: uitofp_i32tof32:
; SSE-X86: # %bb.0: ; SSE-X86: # %bb.0:
; SSE-X86-NEXT: pushl %eax ; SSE-X86-NEXT: pushl %eax
; SSE-X86-NEXT: .cfi_def_cfa_offset 8 ; SSE-X86-NEXT: .cfi_def_cfa_offset 8
; SSE-X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE-X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE-X86-NEXT: orpd {{\.LCPI.*}}, %xmm0 ; SSE-X86-NEXT: orpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE-X86-NEXT: subsd {{\.LCPI.*}}, %xmm0 ; SSE-X86-NEXT: subsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE-X86-NEXT: cvtsd2ss %xmm0, %xmm0 ; SSE-X86-NEXT: cvtsd2ss %xmm0, %xmm0
; SSE-X86-NEXT: movss %xmm0, (%esp) ; SSE-X86-NEXT: movss %xmm0, (%esp)
; SSE-X86-NEXT: flds (%esp) ; SSE-X86-NEXT: flds (%esp)
; SSE-X86-NEXT: wait ; SSE-X86-NEXT: wait
; SSE-X86-NEXT: popl %eax ; SSE-X86-NEXT: popl %eax
; SSE-X86-NEXT: .cfi_def_cfa_offset 4 ; SSE-X86-NEXT: .cfi_def_cfa_offset 4
; SSE-X86-NEXT: retl ; SSE-X86-NEXT: retl
; ;
; SSE-X64-LABEL: uitofp_i32tof32: ; SSE-X64-LABEL: uitofp_i32tof32:
; SSE-X64: # %bb.0: ; SSE-X64: # %bb.0:
; SSE-X64-NEXT: movl %edi, %eax ; SSE-X64-NEXT: movl %edi, %eax
; SSE-X64-NEXT: cvtsi2ss %rax, %xmm0 ; SSE-X64-NEXT: cvtsi2ss %rax, %xmm0
; SSE-X64-NEXT: retq ; SSE-X64-NEXT: retq
; ;
; AVX1-X86-LABEL: uitofp_i32tof32: ; AVX1-X86-LABEL: uitofp_i32tof32:
; AVX1-X86: # %bb.0: ; AVX1-X86: # %bb.0:
; AVX1-X86-NEXT: pushl %eax ; AVX1-X86-NEXT: pushl %eax
; AVX1-X86-NEXT: .cfi_def_cfa_offset 8 ; AVX1-X86-NEXT: .cfi_def_cfa_offset 8
; AVX1-X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; AVX1-X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX1-X86-NEXT: vorpd {{\.LCPI.*}}, %xmm0, %xmm0 ; AVX1-X86-NEXT: vorpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX1-X86-NEXT: vsubsd {{\.LCPI.*}}, %xmm0, %xmm0 ; AVX1-X86-NEXT: vsubsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX1-X86-NEXT: vcvtsd2ss %xmm0, %xmm0, %xmm0 ; AVX1-X86-NEXT: vcvtsd2ss %xmm0, %xmm0, %xmm0
; AVX1-X86-NEXT: vmovss %xmm0, (%esp) ; AVX1-X86-NEXT: vmovss %xmm0, (%esp)
; AVX1-X86-NEXT: flds (%esp) ; AVX1-X86-NEXT: flds (%esp)
; AVX1-X86-NEXT: wait ; AVX1-X86-NEXT: wait
; AVX1-X86-NEXT: popl %eax ; AVX1-X86-NEXT: popl %eax
; AVX1-X86-NEXT: .cfi_def_cfa_offset 4 ; AVX1-X86-NEXT: .cfi_def_cfa_offset 4
; AVX1-X86-NEXT: retl ; AVX1-X86-NEXT: retl
; ;
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; SSE-X86-NEXT: .cfi_def_cfa_register %ebp ; SSE-X86-NEXT: .cfi_def_cfa_register %ebp
; SSE-X86-NEXT: andl $-8, %esp ; SSE-X86-NEXT: andl $-8, %esp
; SSE-X86-NEXT: subl $16, %esp ; SSE-X86-NEXT: subl $16, %esp
; SSE-X86-NEXT: movl 12(%ebp), %eax ; SSE-X86-NEXT: movl 12(%ebp), %eax
; SSE-X86-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE-X86-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; SSE-X86-NEXT: movlps %xmm0, {{[0-9]+}}(%esp) ; SSE-X86-NEXT: movlps %xmm0, {{[0-9]+}}(%esp)
; SSE-X86-NEXT: shrl $31, %eax ; SSE-X86-NEXT: shrl $31, %eax
; SSE-X86-NEXT: fildll {{[0-9]+}}(%esp) ; SSE-X86-NEXT: fildll {{[0-9]+}}(%esp)
; SSE-X86-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; SSE-X86-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; SSE-X86-NEXT: fstps {{[0-9]+}}(%esp) ; SSE-X86-NEXT: fstps {{[0-9]+}}(%esp)
; SSE-X86-NEXT: wait ; SSE-X86-NEXT: wait
; SSE-X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE-X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE-X86-NEXT: movss %xmm0, (%esp) ; SSE-X86-NEXT: movss %xmm0, (%esp)
; SSE-X86-NEXT: flds (%esp) ; SSE-X86-NEXT: flds (%esp)
; SSE-X86-NEXT: wait ; SSE-X86-NEXT: wait
; SSE-X86-NEXT: movl %ebp, %esp ; SSE-X86-NEXT: movl %ebp, %esp
; SSE-X86-NEXT: popl %ebp ; SSE-X86-NEXT: popl %ebp
Show All 25 Lines
; AVX-X86-NEXT: .cfi_def_cfa_register %ebp ; AVX-X86-NEXT: .cfi_def_cfa_register %ebp
; AVX-X86-NEXT: andl $-8, %esp ; AVX-X86-NEXT: andl $-8, %esp
; AVX-X86-NEXT: subl $16, %esp ; AVX-X86-NEXT: subl $16, %esp
; AVX-X86-NEXT: movl 12(%ebp), %eax ; AVX-X86-NEXT: movl 12(%ebp), %eax
; AVX-X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; AVX-X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX-X86-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp) ; AVX-X86-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)
; AVX-X86-NEXT: shrl $31, %eax ; AVX-X86-NEXT: shrl $31, %eax
; AVX-X86-NEXT: fildll {{[0-9]+}}(%esp) ; AVX-X86-NEXT: fildll {{[0-9]+}}(%esp)
; AVX-X86-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; AVX-X86-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX-X86-NEXT: fstps {{[0-9]+}}(%esp) ; AVX-X86-NEXT: fstps {{[0-9]+}}(%esp)
; AVX-X86-NEXT: wait ; AVX-X86-NEXT: wait
; AVX-X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; AVX-X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX-X86-NEXT: vmovss %xmm0, (%esp) ; AVX-X86-NEXT: vmovss %xmm0, (%esp)
; AVX-X86-NEXT: flds (%esp) ; AVX-X86-NEXT: flds (%esp)
; AVX-X86-NEXT: wait ; AVX-X86-NEXT: wait
; AVX-X86-NEXT: movl %ebp, %esp ; AVX-X86-NEXT: movl %ebp, %esp
; AVX-X86-NEXT: popl %ebp ; AVX-X86-NEXT: popl %ebp
Show All 31 Lines
; X87-NEXT: andl $-8, %esp ; X87-NEXT: andl $-8, %esp
; X87-NEXT: subl $16, %esp ; X87-NEXT: subl $16, %esp
; X87-NEXT: movl 8(%ebp), %eax ; X87-NEXT: movl 8(%ebp), %eax
; X87-NEXT: movl 12(%ebp), %ecx ; X87-NEXT: movl 12(%ebp), %ecx
; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp) ; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X87-NEXT: movl %eax, {{[0-9]+}}(%esp) ; X87-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X87-NEXT: shrl $31, %ecx ; X87-NEXT: shrl $31, %ecx
; X87-NEXT: fildll {{[0-9]+}}(%esp) ; X87-NEXT: fildll {{[0-9]+}}(%esp)
; X87-NEXT: fadds {{\.LCPI.*}}(,%ecx,4) ; X87-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; X87-NEXT: fstps {{[0-9]+}}(%esp) ; X87-NEXT: fstps {{[0-9]+}}(%esp)
; X87-NEXT: flds {{[0-9]+}}(%esp) ; X87-NEXT: flds {{[0-9]+}}(%esp)
; X87-NEXT: wait ; X87-NEXT: wait
; X87-NEXT: movl %ebp, %esp ; X87-NEXT: movl %ebp, %esp
; X87-NEXT: popl %ebp ; X87-NEXT: popl %ebp
; X87-NEXT: .cfi_def_cfa %esp, 4 ; X87-NEXT: .cfi_def_cfa %esp, 4
; X87-NEXT: retl ; X87-NEXT: retl
%result = call float @llvm.experimental.constrained.uitofp.f32.i64(i64 %x, %result = call float @llvm.experimental.constrained.uitofp.f32.i64(i64 %x,
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; SSE-X86-NEXT: pushl %ebp ; SSE-X86-NEXT: pushl %ebp
; SSE-X86-NEXT: .cfi_def_cfa_offset 8 ; SSE-X86-NEXT: .cfi_def_cfa_offset 8
; SSE-X86-NEXT: .cfi_offset %ebp, -8 ; SSE-X86-NEXT: .cfi_offset %ebp, -8
; SSE-X86-NEXT: movl %esp, %ebp ; SSE-X86-NEXT: movl %esp, %ebp
; SSE-X86-NEXT: .cfi_def_cfa_register %ebp ; SSE-X86-NEXT: .cfi_def_cfa_register %ebp
; SSE-X86-NEXT: andl $-8, %esp ; SSE-X86-NEXT: andl $-8, %esp
; SSE-X86-NEXT: subl $8, %esp ; SSE-X86-NEXT: subl $8, %esp
; SSE-X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE-X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE-X86-NEXT: orpd {{\.LCPI.*}}, %xmm0 ; SSE-X86-NEXT: orpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE-X86-NEXT: subsd {{\.LCPI.*}}, %xmm0 ; SSE-X86-NEXT: subsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE-X86-NEXT: movsd %xmm0, (%esp) ; SSE-X86-NEXT: movsd %xmm0, (%esp)
; SSE-X86-NEXT: fldl (%esp) ; SSE-X86-NEXT: fldl (%esp)
; SSE-X86-NEXT: wait ; SSE-X86-NEXT: wait
; SSE-X86-NEXT: movl %ebp, %esp ; SSE-X86-NEXT: movl %ebp, %esp
; SSE-X86-NEXT: popl %ebp ; SSE-X86-NEXT: popl %ebp
; SSE-X86-NEXT: .cfi_def_cfa %esp, 4 ; SSE-X86-NEXT: .cfi_def_cfa %esp, 4
; SSE-X86-NEXT: retl ; SSE-X86-NEXT: retl
; ;
; SSE-X64-LABEL: uitofp_i32tof64: ; SSE-X64-LABEL: uitofp_i32tof64:
; SSE-X64: # %bb.0: ; SSE-X64: # %bb.0:
; SSE-X64-NEXT: movl %edi, %eax ; SSE-X64-NEXT: movl %edi, %eax
; SSE-X64-NEXT: cvtsi2sd %rax, %xmm0 ; SSE-X64-NEXT: cvtsi2sd %rax, %xmm0
; SSE-X64-NEXT: retq ; SSE-X64-NEXT: retq
; ;
; AVX1-X86-LABEL: uitofp_i32tof64: ; AVX1-X86-LABEL: uitofp_i32tof64:
; AVX1-X86: # %bb.0: ; AVX1-X86: # %bb.0:
; AVX1-X86-NEXT: pushl %ebp ; AVX1-X86-NEXT: pushl %ebp
; AVX1-X86-NEXT: .cfi_def_cfa_offset 8 ; AVX1-X86-NEXT: .cfi_def_cfa_offset 8
; AVX1-X86-NEXT: .cfi_offset %ebp, -8 ; AVX1-X86-NEXT: .cfi_offset %ebp, -8
; AVX1-X86-NEXT: movl %esp, %ebp ; AVX1-X86-NEXT: movl %esp, %ebp
; AVX1-X86-NEXT: .cfi_def_cfa_register %ebp ; AVX1-X86-NEXT: .cfi_def_cfa_register %ebp
; AVX1-X86-NEXT: andl $-8, %esp ; AVX1-X86-NEXT: andl $-8, %esp
; AVX1-X86-NEXT: subl $8, %esp ; AVX1-X86-NEXT: subl $8, %esp
; AVX1-X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; AVX1-X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX1-X86-NEXT: vorpd {{\.LCPI.*}}, %xmm0, %xmm0 ; AVX1-X86-NEXT: vorpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX1-X86-NEXT: vsubsd {{\.LCPI.*}}, %xmm0, %xmm0 ; AVX1-X86-NEXT: vsubsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX1-X86-NEXT: vmovsd %xmm0, (%esp) ; AVX1-X86-NEXT: vmovsd %xmm0, (%esp)
; AVX1-X86-NEXT: fldl (%esp) ; AVX1-X86-NEXT: fldl (%esp)
; AVX1-X86-NEXT: wait ; AVX1-X86-NEXT: wait
; AVX1-X86-NEXT: movl %ebp, %esp ; AVX1-X86-NEXT: movl %ebp, %esp
; AVX1-X86-NEXT: popl %ebp ; AVX1-X86-NEXT: popl %ebp
; AVX1-X86-NEXT: .cfi_def_cfa %esp, 4 ; AVX1-X86-NEXT: .cfi_def_cfa %esp, 4
; AVX1-X86-NEXT: retl ; AVX1-X86-NEXT: retl
; ;
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; SSE-X86-NEXT: .cfi_def_cfa_register %ebp ; SSE-X86-NEXT: .cfi_def_cfa_register %ebp
; SSE-X86-NEXT: andl $-8, %esp ; SSE-X86-NEXT: andl $-8, %esp
; SSE-X86-NEXT: subl $24, %esp ; SSE-X86-NEXT: subl $24, %esp
; SSE-X86-NEXT: movl 12(%ebp), %eax ; SSE-X86-NEXT: movl 12(%ebp), %eax
; SSE-X86-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE-X86-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; SSE-X86-NEXT: movlps %xmm0, {{[0-9]+}}(%esp) ; SSE-X86-NEXT: movlps %xmm0, {{[0-9]+}}(%esp)
; SSE-X86-NEXT: shrl $31, %eax ; SSE-X86-NEXT: shrl $31, %eax
; SSE-X86-NEXT: fildll {{[0-9]+}}(%esp) ; SSE-X86-NEXT: fildll {{[0-9]+}}(%esp)
; SSE-X86-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; SSE-X86-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; SSE-X86-NEXT: fstpl {{[0-9]+}}(%esp) ; SSE-X86-NEXT: fstpl {{[0-9]+}}(%esp)
; SSE-X86-NEXT: wait ; SSE-X86-NEXT: wait
; SSE-X86-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE-X86-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; SSE-X86-NEXT: movsd %xmm0, (%esp) ; SSE-X86-NEXT: movsd %xmm0, (%esp)
; SSE-X86-NEXT: fldl (%esp) ; SSE-X86-NEXT: fldl (%esp)
; SSE-X86-NEXT: wait ; SSE-X86-NEXT: wait
; SSE-X86-NEXT: movl %ebp, %esp ; SSE-X86-NEXT: movl %ebp, %esp
; SSE-X86-NEXT: popl %ebp ; SSE-X86-NEXT: popl %ebp
Show All 25 Lines
; AVX-X86-NEXT: .cfi_def_cfa_register %ebp ; AVX-X86-NEXT: .cfi_def_cfa_register %ebp
; AVX-X86-NEXT: andl $-8, %esp ; AVX-X86-NEXT: andl $-8, %esp
; AVX-X86-NEXT: subl $24, %esp ; AVX-X86-NEXT: subl $24, %esp
; AVX-X86-NEXT: movl 12(%ebp), %eax ; AVX-X86-NEXT: movl 12(%ebp), %eax
; AVX-X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; AVX-X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX-X86-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp) ; AVX-X86-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)
; AVX-X86-NEXT: shrl $31, %eax ; AVX-X86-NEXT: shrl $31, %eax
; AVX-X86-NEXT: fildll {{[0-9]+}}(%esp) ; AVX-X86-NEXT: fildll {{[0-9]+}}(%esp)
; AVX-X86-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; AVX-X86-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX-X86-NEXT: fstpl {{[0-9]+}}(%esp) ; AVX-X86-NEXT: fstpl {{[0-9]+}}(%esp)
; AVX-X86-NEXT: wait ; AVX-X86-NEXT: wait
; AVX-X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; AVX-X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX-X86-NEXT: vmovsd %xmm0, (%esp) ; AVX-X86-NEXT: vmovsd %xmm0, (%esp)
; AVX-X86-NEXT: fldl (%esp) ; AVX-X86-NEXT: fldl (%esp)
; AVX-X86-NEXT: wait ; AVX-X86-NEXT: wait
; AVX-X86-NEXT: movl %ebp, %esp ; AVX-X86-NEXT: movl %ebp, %esp
; AVX-X86-NEXT: popl %ebp ; AVX-X86-NEXT: popl %ebp
Show All 31 Lines
; X87-NEXT: andl $-8, %esp ; X87-NEXT: andl $-8, %esp
; X87-NEXT: subl $16, %esp ; X87-NEXT: subl $16, %esp
; X87-NEXT: movl 8(%ebp), %eax ; X87-NEXT: movl 8(%ebp), %eax
; X87-NEXT: movl 12(%ebp), %ecx ; X87-NEXT: movl 12(%ebp), %ecx
; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp) ; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X87-NEXT: movl %eax, (%esp) ; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: shrl $31, %ecx ; X87-NEXT: shrl $31, %ecx
; X87-NEXT: fildll (%esp) ; X87-NEXT: fildll (%esp)
; X87-NEXT: fadds {{\.LCPI.*}}(,%ecx,4) ; X87-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; X87-NEXT: fstpl {{[0-9]+}}(%esp) ; X87-NEXT: fstpl {{[0-9]+}}(%esp)
; X87-NEXT: fldl {{[0-9]+}}(%esp) ; X87-NEXT: fldl {{[0-9]+}}(%esp)
; X87-NEXT: wait ; X87-NEXT: wait
; X87-NEXT: movl %ebp, %esp ; X87-NEXT: movl %ebp, %esp
; X87-NEXT: popl %ebp ; X87-NEXT: popl %ebp
; X87-NEXT: .cfi_def_cfa %esp, 4 ; X87-NEXT: .cfi_def_cfa %esp, 4
; X87-NEXT: retl ; X87-NEXT: retl
%result = call double @llvm.experimental.constrained.uitofp.f64.i64(i64 %x, %result = call double @llvm.experimental.constrained.uitofp.f64.i64(i64 %x,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret double %result ret double %result
} }
attributes #0 = { strictfp } attributes #0 = { strictfp }

llvm/test/CodeGen/X86/fp128-cast.ll

Show First 20 Lines • Show All 1,281 Lines • ▼ Show 20 Lines
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: pushl %ecx ; X32-NEXT: pushl %ecx
; X32-NEXT: pushl %edi ; X32-NEXT: pushl %edi
; X32-NEXT: pushl %edx ; X32-NEXT: pushl %edx
; X32-NEXT: calll __trunctfdf2 ; X32-NEXT: calll __trunctfdf2
; X32-NEXT: addl $16, %esp ; X32-NEXT: addl $16, %esp
; X32-NEXT: fstpl {{[0-9]+}}(%esp) ; X32-NEXT: fstpl {{[0-9]+}}(%esp)
; X32-NEXT: testb $-128, {{[0-9]+}}(%esp) ; X32-NEXT: testb $-128, {{[0-9]+}}(%esp)
; X32-NEXT: flds {{\.LCPI.*}} ; X32-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X32-NEXT: flds {{\.LCPI.*}} ; X32-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X32-NEXT: jne .LBB26_3 ; X32-NEXT: jne .LBB26_3
; X32-NEXT: # %bb.2: # %if.then ; X32-NEXT: # %bb.2: # %if.then
; X32-NEXT: fstp %st(1) ; X32-NEXT: fstp %st(1)
; X32-NEXT: fldz ; X32-NEXT: fldz
; X32-NEXT: .LBB26_3: # %if.then ; X32-NEXT: .LBB26_3: # %if.then
; X32-NEXT: fstp %st(0) ; X32-NEXT: fstp %st(0)
; X32-NEXT: subl $16, %esp ; X32-NEXT: subl $16, %esp
; X32-NEXT: leal {{[0-9]+}}(%esp), %eax ; X32-NEXT: leal {{[0-9]+}}(%esp), %eax
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llvm/test/CodeGen/X86/fp128-i128.ll

Show First 20 Lines • Show All 138 Lines • ▼ Show 20 Lines
; SSE-NEXT: movq %rcx, (%rsp) ; SSE-NEXT: movq %rcx, (%rsp)
; SSE-NEXT: movaps (%rsp), %xmm0 ; SSE-NEXT: movaps (%rsp), %xmm0
; SSE-NEXT: movaps {{.*}}(%rip), %xmm1 ; SSE-NEXT: movaps {{.*}}(%rip), %xmm1
; SSE-NEXT: callq __lttf2@PLT ; SSE-NEXT: callq __lttf2@PLT
; SSE-NEXT: xorl %ecx, %ecx ; SSE-NEXT: xorl %ecx, %ecx
; SSE-NEXT: testl %eax, %eax ; SSE-NEXT: testl %eax, %eax
; SSE-NEXT: sets %cl ; SSE-NEXT: sets %cl
; SSE-NEXT: shlq $4, %rcx ; SSE-NEXT: shlq $4, %rcx
; SSE-NEXT: movaps {{\.LCPI.*}}(%rcx), %xmm0 ; SSE-NEXT: movaps {{\.LCPI[0-9]+_[0-9]+}}(%rcx), %xmm0
; SSE-NEXT: addq $40, %rsp ; SSE-NEXT: addq $40, %rsp
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: TestI128_1: ; AVX-LABEL: TestI128_1:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: subq $40, %rsp ; AVX-NEXT: subq $40, %rsp
; AVX-NEXT: vmovaps %xmm0, {{[0-9]+}}(%rsp) ; AVX-NEXT: vmovaps %xmm0, {{[0-9]+}}(%rsp)
; AVX-NEXT: movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF ; AVX-NEXT: movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF
; AVX-NEXT: andq {{[0-9]+}}(%rsp), %rax ; AVX-NEXT: andq {{[0-9]+}}(%rsp), %rax
; AVX-NEXT: movq {{[0-9]+}}(%rsp), %rcx ; AVX-NEXT: movq {{[0-9]+}}(%rsp), %rcx
; AVX-NEXT: movq %rax, {{[0-9]+}}(%rsp) ; AVX-NEXT: movq %rax, {{[0-9]+}}(%rsp)
; AVX-NEXT: movq %rcx, (%rsp) ; AVX-NEXT: movq %rcx, (%rsp)
; AVX-NEXT: vmovaps (%rsp), %xmm0 ; AVX-NEXT: vmovaps (%rsp), %xmm0
; AVX-NEXT: vmovaps {{.*}}(%rip), %xmm1 ; AVX-NEXT: vmovaps {{.*}}(%rip), %xmm1
; AVX-NEXT: callq __lttf2@PLT ; AVX-NEXT: callq __lttf2@PLT
; AVX-NEXT: xorl %ecx, %ecx ; AVX-NEXT: xorl %ecx, %ecx
; AVX-NEXT: testl %eax, %eax ; AVX-NEXT: testl %eax, %eax
; AVX-NEXT: sets %cl ; AVX-NEXT: sets %cl
; AVX-NEXT: shlq $4, %rcx ; AVX-NEXT: shlq $4, %rcx
; AVX-NEXT: vmovaps {{\.LCPI.*}}(%rcx), %xmm0 ; AVX-NEXT: vmovaps {{\.LCPI[0-9]+_[0-9]+}}(%rcx), %xmm0
; AVX-NEXT: addq $40, %rsp ; AVX-NEXT: addq $40, %rsp
; AVX-NEXT: retq ; AVX-NEXT: retq
entry: entry:
%0 = bitcast fp128 %x to i128 %0 = bitcast fp128 %x to i128
%bf.clear = and i128 %0, 170141183460469231731687303715884105727 %bf.clear = and i128 %0, 170141183460469231731687303715884105727
%1 = bitcast i128 %bf.clear to fp128 %1 = bitcast i128 %bf.clear to fp128
%cmp = fcmp olt fp128 %1, 0xL999999999999999A3FFB999999999999 %cmp = fcmp olt fp128 %1, 0xL999999999999999A3FFB999999999999
%cond = select i1 %cmp, fp128 0xL00000000000000003FFF000000000000, fp128 0xL00000000000000004000000000000000 %cond = select i1 %cmp, fp128 0xL00000000000000003FFF000000000000, fp128 0xL00000000000000004000000000000000
▲ Show 20 Lines • Show All 368 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/fp80-strict-scalar.ll

Show First 20 Lines • Show All 582 Lines • ▼ Show 20 Lines
; X86-NEXT: pushl %ebp ; X86-NEXT: pushl %ebp
; X86-NEXT: .cfi_def_cfa_offset 8 ; X86-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: .cfi_offset %ebp, -8 ; X86-NEXT: .cfi_offset %ebp, -8
; X86-NEXT: movl %esp, %ebp ; X86-NEXT: movl %esp, %ebp
; X86-NEXT: .cfi_def_cfa_register %ebp ; X86-NEXT: .cfi_def_cfa_register %ebp
; X86-NEXT: andl $-8, %esp ; X86-NEXT: andl $-8, %esp
; X86-NEXT: subl $16, %esp ; X86-NEXT: subl $16, %esp
; X86-NEXT: fldt 8(%ebp) ; X86-NEXT: fldt 8(%ebp)
; X86-NEXT: flds {{\.LCPI.*}} ; X86-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-NEXT: fcom %st(1) ; X86-NEXT: fcom %st(1)
; X86-NEXT: wait ; X86-NEXT: wait
; X86-NEXT: fnstsw %ax ; X86-NEXT: fnstsw %ax
; X86-NEXT: xorl %edx, %edx ; X86-NEXT: xorl %edx, %edx
; X86-NEXT: # kill: def $ah killed $ah killed $ax ; X86-NEXT: # kill: def $ah killed $ah killed $ax
; X86-NEXT: sahf ; X86-NEXT: sahf
; X86-NEXT: setbe %al ; X86-NEXT: setbe %al
; X86-NEXT: fldz ; X86-NEXT: fldz
▲ Show 20 Lines • Show All 300 Lines • ▼ Show 20 Lines
; X86-NEXT: andl $-8, %esp ; X86-NEXT: andl $-8, %esp
; X86-NEXT: subl $8, %esp ; X86-NEXT: subl $8, %esp
; X86-NEXT: movl 8(%ebp), %eax ; X86-NEXT: movl 8(%ebp), %eax
; X86-NEXT: movl 12(%ebp), %ecx ; X86-NEXT: movl 12(%ebp), %ecx
; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp) ; X86-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X86-NEXT: movl %eax, (%esp) ; X86-NEXT: movl %eax, (%esp)
; X86-NEXT: shrl $31, %ecx ; X86-NEXT: shrl $31, %ecx
; X86-NEXT: fildll (%esp) ; X86-NEXT: fildll (%esp)
; X86-NEXT: fadds {{\.LCPI.*}}(,%ecx,4) ; X86-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; X86-NEXT: wait ; X86-NEXT: wait
; X86-NEXT: movl %ebp, %esp ; X86-NEXT: movl %ebp, %esp
; X86-NEXT: popl %ebp ; X86-NEXT: popl %ebp
; X86-NEXT: .cfi_def_cfa %esp, 4 ; X86-NEXT: .cfi_def_cfa %esp, 4
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: uint64_to_fp80: ; X64-LABEL: uint64_to_fp80:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movq %rdi, -{{[0-9]+}}(%rsp) ; X64-NEXT: movq %rdi, -{{[0-9]+}}(%rsp)
; X64-NEXT: xorl %eax, %eax ; X64-NEXT: xorl %eax, %eax
; X64-NEXT: testq %rdi, %rdi ; X64-NEXT: testq %rdi, %rdi
; X64-NEXT: sets %al ; X64-NEXT: sets %al
; X64-NEXT: fildll -{{[0-9]+}}(%rsp) ; X64-NEXT: fildll -{{[0-9]+}}(%rsp)
; X64-NEXT: fadds {{\.LCPI.*}}(,%rax,4) ; X64-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%rax,4)
; X64-NEXT: wait ; X64-NEXT: wait
; X64-NEXT: retq ; X64-NEXT: retq
%result = call x86_fp80 @llvm.experimental.constrained.uitofp.f80.i64(i64 %x, %result = call x86_fp80 @llvm.experimental.constrained.uitofp.f80.i64(i64 %x,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret x86_fp80 %result ret x86_fp80 %result
} }
attributes #0 = { strictfp } attributes #0 = { strictfp }

llvm/test/CodeGen/X86/fptosi-sat-scalar.ll

Show First 20 Lines • Show All 99 Lines • ▼ Show 20 Lines
; X86-X87-NEXT: flds {{[0-9]+}}(%esp) ; X86-X87-NEXT: flds {{[0-9]+}}(%esp)
; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00
; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fists {{[0-9]+}}(%esp) ; X86-X87-NEXT: fists {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movb $-128, %dl ; X86-X87-NEXT: movb $-128, %dl
; X86-X87-NEXT: jb .LBB1_2 ; X86-X87-NEXT: jb .LBB1_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movb {{[0-9]+}}(%esp), %dl ; X86-X87-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-X87-NEXT: .LBB1_2: ; X86-X87-NEXT: .LBB1_2:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movb $127, %cl ; X86-X87-NEXT: movb $127, %cl
; X86-X87-NEXT: ja .LBB1_4 ; X86-X87-NEXT: ja .LBB1_4
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; X86-X87-NEXT: flds {{[0-9]+}}(%esp) ; X86-X87-NEXT: flds {{[0-9]+}}(%esp)
; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00
; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fists {{[0-9]+}}(%esp) ; X86-X87-NEXT: fists {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movw $-4096, %cx # imm = 0xF000 ; X86-X87-NEXT: movw $-4096, %cx # imm = 0xF000
; X86-X87-NEXT: jb .LBB2_2 ; X86-X87-NEXT: jb .LBB2_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB2_2: ; X86-X87-NEXT: .LBB2_2:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $4095, %edx # imm = 0xFFF ; X86-X87-NEXT: movl $4095, %edx # imm = 0xFFF
; X86-X87-NEXT: ja .LBB2_4 ; X86-X87-NEXT: ja .LBB2_4
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; X86-X87-NEXT: flds {{[0-9]+}}(%esp) ; X86-X87-NEXT: flds {{[0-9]+}}(%esp)
; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00
; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fists {{[0-9]+}}(%esp) ; X86-X87-NEXT: fists {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movw $-32768, %cx # imm = 0x8000 ; X86-X87-NEXT: movw $-32768, %cx # imm = 0x8000
; X86-X87-NEXT: jb .LBB3_2 ; X86-X87-NEXT: jb .LBB3_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB3_2: ; X86-X87-NEXT: .LBB3_2:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $32767, %edx # imm = 0x7FFF ; X86-X87-NEXT: movl $32767, %edx # imm = 0x7FFF
; X86-X87-NEXT: ja .LBB3_4 ; X86-X87-NEXT: ja .LBB3_4
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; X86-X87-NEXT: flds {{[0-9]+}}(%esp) ; X86-X87-NEXT: flds {{[0-9]+}}(%esp)
; X86-X87-NEXT: fnstcw (%esp) ; X86-X87-NEXT: fnstcw (%esp)
; X86-X87-NEXT: movzwl (%esp), %eax ; X86-X87-NEXT: movzwl (%esp), %eax
; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00
; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fistl {{[0-9]+}}(%esp) ; X86-X87-NEXT: fistl {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw (%esp) ; X86-X87-NEXT: fldcw (%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $-262144, %ecx # imm = 0xFFFC0000 ; X86-X87-NEXT: movl $-262144, %ecx # imm = 0xFFFC0000
; X86-X87-NEXT: jb .LBB4_2 ; X86-X87-NEXT: jb .LBB4_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB4_2: ; X86-X87-NEXT: .LBB4_2:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $262143, %edx # imm = 0x3FFFF ; X86-X87-NEXT: movl $262143, %edx # imm = 0x3FFFF
; X86-X87-NEXT: ja .LBB4_4 ; X86-X87-NEXT: ja .LBB4_4
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; X86-X87-NEXT: addl $8, %esp ; X86-X87-NEXT: addl $8, %esp
; X86-X87-NEXT: retl ; X86-X87-NEXT: retl
; ;
; X86-SSE-LABEL: test_signed_i19_f32: ; X86-SSE-LABEL: test_signed_i19_f32:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: xorl %eax, %eax ; X86-SSE-NEXT: xorl %eax, %eax
; X86-SSE-NEXT: ucomiss %xmm0, %xmm0 ; X86-SSE-NEXT: ucomiss %xmm0, %xmm0
; X86-SSE-NEXT: maxss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: maxss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: minss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: minss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: cvttss2si %xmm0, %ecx ; X86-SSE-NEXT: cvttss2si %xmm0, %ecx
; X86-SSE-NEXT: cmovnpl %ecx, %eax ; X86-SSE-NEXT: cmovnpl %ecx, %eax
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-LABEL: test_signed_i19_f32: ; X64-LABEL: test_signed_i19_f32:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: xorl %eax, %eax ; X64-NEXT: xorl %eax, %eax
; X64-NEXT: ucomiss %xmm0, %xmm0 ; X64-NEXT: ucomiss %xmm0, %xmm0
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; X86-X87-NEXT: flds {{[0-9]+}}(%esp) ; X86-X87-NEXT: flds {{[0-9]+}}(%esp)
; X86-X87-NEXT: fnstcw (%esp) ; X86-X87-NEXT: fnstcw (%esp)
; X86-X87-NEXT: movzwl (%esp), %eax ; X86-X87-NEXT: movzwl (%esp), %eax
; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00
; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fistl {{[0-9]+}}(%esp) ; X86-X87-NEXT: fistl {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw (%esp) ; X86-X87-NEXT: fldcw (%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $-2147483648, %ecx # imm = 0x80000000 ; X86-X87-NEXT: movl $-2147483648, %ecx # imm = 0x80000000
; X86-X87-NEXT: jb .LBB5_2 ; X86-X87-NEXT: jb .LBB5_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB5_2: ; X86-X87-NEXT: .LBB5_2:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $2147483647, %edx # imm = 0x7FFFFFFF ; X86-X87-NEXT: movl $2147483647, %edx # imm = 0x7FFFFFFF
; X86-X87-NEXT: ja .LBB5_4 ; X86-X87-NEXT: ja .LBB5_4
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; X86-X87-NEXT: movl %ecx, %eax ; X86-X87-NEXT: movl %ecx, %eax
; X86-X87-NEXT: addl $8, %esp ; X86-X87-NEXT: addl $8, %esp
; X86-X87-NEXT: retl ; X86-X87-NEXT: retl
; ;
; X86-SSE-LABEL: test_signed_i32_f32: ; X86-SSE-LABEL: test_signed_i32_f32:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: cvttss2si %xmm0, %eax ; X86-SSE-NEXT: cvttss2si %xmm0, %eax
; X86-SSE-NEXT: ucomiss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $2147483647, %ecx # imm = 0x7FFFFFFF ; X86-SSE-NEXT: movl $2147483647, %ecx # imm = 0x7FFFFFFF
; X86-SSE-NEXT: cmovbel %eax, %ecx ; X86-SSE-NEXT: cmovbel %eax, %ecx
; X86-SSE-NEXT: xorl %eax, %eax ; X86-SSE-NEXT: xorl %eax, %eax
; X86-SSE-NEXT: ucomiss %xmm0, %xmm0 ; X86-SSE-NEXT: ucomiss %xmm0, %xmm0
; X86-SSE-NEXT: cmovnpl %ecx, %eax ; X86-SSE-NEXT: cmovnpl %ecx, %eax
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-LABEL: test_signed_i32_f32: ; X64-LABEL: test_signed_i32_f32:
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; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00
; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fld %st(0) ; X86-X87-NEXT: fld %st(0)
; X86-X87-NEXT: fistpll {{[0-9]+}}(%esp) ; X86-X87-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $0, %edx ; X86-X87-NEXT: movl $0, %edx
; X86-X87-NEXT: jb .LBB6_2 ; X86-X87-NEXT: jb .LBB6_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-X87-NEXT: .LBB6_2: ; X86-X87-NEXT: .LBB6_2:
; X86-X87-NEXT: movl $-131072, %edi # imm = 0xFFFE0000 ; X86-X87-NEXT: movl $-131072, %edi # imm = 0xFFFE0000
; X86-X87-NEXT: jb .LBB6_4 ; X86-X87-NEXT: jb .LBB6_4
; X86-X87-NEXT: # %bb.3: ; X86-X87-NEXT: # %bb.3:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-X87-NEXT: .LBB6_4: ; X86-X87-NEXT: .LBB6_4:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $131071, %esi # imm = 0x1FFFF ; X86-X87-NEXT: movl $131071, %esi # imm = 0x1FFFF
; X86-X87-NEXT: ja .LBB6_6 ; X86-X87-NEXT: ja .LBB6_6
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; X86-SSE-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-SSE-NEXT: orl $3072, %eax # imm = 0xC00
; X86-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fistpll {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: xorl %ecx, %ecx ; X86-SSE-NEXT: xorl %ecx, %ecx
; X86-SSE-NEXT: ucomiss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-SSE-NEXT: cmovbl %ecx, %esi ; X86-SSE-NEXT: cmovbl %ecx, %esi
; X86-SSE-NEXT: movl $-131072, %eax # imm = 0xFFFE0000 ; X86-SSE-NEXT: movl $-131072, %eax # imm = 0xFFFE0000
; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: ucomiss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $131071, %edx # imm = 0x1FFFF ; X86-SSE-NEXT: movl $131071, %edx # imm = 0x1FFFF
; X86-SSE-NEXT: cmovbel %eax, %edx ; X86-SSE-NEXT: cmovbel %eax, %edx
; X86-SSE-NEXT: movl $-1, %eax ; X86-SSE-NEXT: movl $-1, %eax
; X86-SSE-NEXT: cmovbel %esi, %eax ; X86-SSE-NEXT: cmovbel %esi, %eax
; X86-SSE-NEXT: ucomiss %xmm0, %xmm0 ; X86-SSE-NEXT: ucomiss %xmm0, %xmm0
; X86-SSE-NEXT: cmovpl %ecx, %eax ; X86-SSE-NEXT: cmovpl %ecx, %eax
; X86-SSE-NEXT: cmovpl %ecx, %edx ; X86-SSE-NEXT: cmovpl %ecx, %edx
; X86-SSE-NEXT: addl $16, %esp ; X86-SSE-NEXT: addl $16, %esp
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; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00
; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fld %st(0) ; X86-X87-NEXT: fld %st(0)
; X86-X87-NEXT: fistpll {{[0-9]+}}(%esp) ; X86-X87-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $0, %edx ; X86-X87-NEXT: movl $0, %edx
; X86-X87-NEXT: jb .LBB7_2 ; X86-X87-NEXT: jb .LBB7_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-X87-NEXT: .LBB7_2: ; X86-X87-NEXT: .LBB7_2:
; X86-X87-NEXT: movl $-2147483648, %edi # imm = 0x80000000 ; X86-X87-NEXT: movl $-2147483648, %edi # imm = 0x80000000
; X86-X87-NEXT: jb .LBB7_4 ; X86-X87-NEXT: jb .LBB7_4
; X86-X87-NEXT: # %bb.3: ; X86-X87-NEXT: # %bb.3:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-X87-NEXT: .LBB7_4: ; X86-X87-NEXT: .LBB7_4:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $2147483647, %esi # imm = 0x7FFFFFFF ; X86-X87-NEXT: movl $2147483647, %esi # imm = 0x7FFFFFFF
; X86-X87-NEXT: ja .LBB7_6 ; X86-X87-NEXT: ja .LBB7_6
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; X86-SSE-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-SSE-NEXT: orl $3072, %eax # imm = 0xC00
; X86-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fistpll {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: xorl %ecx, %ecx ; X86-SSE-NEXT: xorl %ecx, %ecx
; X86-SSE-NEXT: ucomiss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-SSE-NEXT: cmovbl %ecx, %esi ; X86-SSE-NEXT: cmovbl %ecx, %esi
; X86-SSE-NEXT: movl $-2147483648, %eax # imm = 0x80000000 ; X86-SSE-NEXT: movl $-2147483648, %eax # imm = 0x80000000
; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: ucomiss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $2147483647, %edx # imm = 0x7FFFFFFF ; X86-SSE-NEXT: movl $2147483647, %edx # imm = 0x7FFFFFFF
; X86-SSE-NEXT: cmovbel %eax, %edx ; X86-SSE-NEXT: cmovbel %eax, %edx
; X86-SSE-NEXT: movl $-1, %eax ; X86-SSE-NEXT: movl $-1, %eax
; X86-SSE-NEXT: cmovbel %esi, %eax ; X86-SSE-NEXT: cmovbel %esi, %eax
; X86-SSE-NEXT: ucomiss %xmm0, %xmm0 ; X86-SSE-NEXT: ucomiss %xmm0, %xmm0
; X86-SSE-NEXT: cmovpl %ecx, %eax ; X86-SSE-NEXT: cmovpl %ecx, %eax
; X86-SSE-NEXT: cmovpl %ecx, %edx ; X86-SSE-NEXT: cmovpl %ecx, %edx
; X86-SSE-NEXT: addl $16, %esp ; X86-SSE-NEXT: addl $16, %esp
Show All 21 Lines
; X86-X87-NEXT: pushl %ebx ; X86-X87-NEXT: pushl %ebx
; X86-X87-NEXT: pushl %edi ; X86-X87-NEXT: pushl %edi
; X86-X87-NEXT: pushl %esi ; X86-X87-NEXT: pushl %esi
; X86-X87-NEXT: subl $44, %esp ; X86-X87-NEXT: subl $44, %esp
; X86-X87-NEXT: flds {{[0-9]+}}(%esp) ; X86-X87-NEXT: flds {{[0-9]+}}(%esp)
; X86-X87-NEXT: fsts {{[0-9]+}}(%esp) ; X86-X87-NEXT: fsts {{[0-9]+}}(%esp)
; X86-X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: movl %eax, (%esp) ; X86-X87-NEXT: movl %eax, (%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fsts {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; X86-X87-NEXT: fsts {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: movl %eax, %ebx ; X86-X87-NEXT: movl %eax, %ebx
; X86-X87-NEXT: calll __fixsfti ; X86-X87-NEXT: calll __fixsfti
; X86-X87-NEXT: subl $4, %esp ; X86-X87-NEXT: subl $4, %esp
; X86-X87-NEXT: xorl %edx, %edx ; X86-X87-NEXT: xorl %edx, %edx
Show All 11 Lines
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ebp ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X86-X87-NEXT: .LBB8_4: ; X86-X87-NEXT: .LBB8_4:
; X86-X87-NEXT: movl $0, %edi ; X86-X87-NEXT: movl $0, %edi
; X86-X87-NEXT: jb .LBB8_6 ; X86-X87-NEXT: jb .LBB8_6
; X86-X87-NEXT: # %bb.5: ; X86-X87-NEXT: # %bb.5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-X87-NEXT: .LBB8_6: ; X86-X87-NEXT: .LBB8_6:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload ; X86-X87-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $-1, %eax ; X86-X87-NEXT: movl $-1, %eax
; X86-X87-NEXT: movl $-1, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; X86-X87-NEXT: movl $-1, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: movss %xmm0, {{[0-9]+}}(%esp) ; X86-SSE-NEXT: movss %xmm0, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl %eax, (%esp) ; X86-SSE-NEXT: movl %eax, (%esp)
; X86-SSE-NEXT: calll __fixsfti ; X86-SSE-NEXT: calll __fixsfti
; X86-SSE-NEXT: subl $4, %esp ; X86-SSE-NEXT: subl $4, %esp
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: xorl %ebp, %ebp ; X86-SSE-NEXT: xorl %ebp, %ebp
; X86-SSE-NEXT: ucomiss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $-8, %ebx ; X86-SSE-NEXT: movl $-8, %ebx
; X86-SSE-NEXT: movl $0, %ecx ; X86-SSE-NEXT: movl $0, %ecx
; X86-SSE-NEXT: movl $0, %edx ; X86-SSE-NEXT: movl $0, %edx
; X86-SSE-NEXT: movl $0, %edi ; X86-SSE-NEXT: movl $0, %edi
; X86-SSE-NEXT: jb .LBB8_2 ; X86-SSE-NEXT: jb .LBB8_2
; X86-SSE-NEXT: # %bb.1: ; X86-SSE-NEXT: # %bb.1:
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ebx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-SSE-NEXT: .LBB8_2: ; X86-SSE-NEXT: .LBB8_2:
; X86-SSE-NEXT: ucomiss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $-1, %eax ; X86-SSE-NEXT: movl $-1, %eax
; X86-SSE-NEXT: cmoval %eax, %edi ; X86-SSE-NEXT: cmoval %eax, %edi
; X86-SSE-NEXT: cmoval %eax, %edx ; X86-SSE-NEXT: cmoval %eax, %edx
; X86-SSE-NEXT: cmoval %eax, %ecx ; X86-SSE-NEXT: cmoval %eax, %ecx
; X86-SSE-NEXT: movl $7, %eax ; X86-SSE-NEXT: movl $7, %eax
; X86-SSE-NEXT: cmovbel %ebx, %eax ; X86-SSE-NEXT: cmovbel %ebx, %eax
; X86-SSE-NEXT: ucomiss %xmm0, %xmm0 ; X86-SSE-NEXT: ucomiss %xmm0, %xmm0
; X86-SSE-NEXT: cmovpl %ebp, %eax ; X86-SSE-NEXT: cmovpl %ebp, %eax
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; X86-X87-NEXT: pushl %ebx ; X86-X87-NEXT: pushl %ebx
; X86-X87-NEXT: pushl %edi ; X86-X87-NEXT: pushl %edi
; X86-X87-NEXT: pushl %esi ; X86-X87-NEXT: pushl %esi
; X86-X87-NEXT: subl $44, %esp ; X86-X87-NEXT: subl $44, %esp
; X86-X87-NEXT: flds {{[0-9]+}}(%esp) ; X86-X87-NEXT: flds {{[0-9]+}}(%esp)
; X86-X87-NEXT: fsts {{[0-9]+}}(%esp) ; X86-X87-NEXT: fsts {{[0-9]+}}(%esp)
; X86-X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: movl %eax, (%esp) ; X86-X87-NEXT: movl %eax, (%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fsts {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; X86-X87-NEXT: fsts {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: movl %eax, %ebx ; X86-X87-NEXT: movl %eax, %ebx
; X86-X87-NEXT: calll __fixsfti ; X86-X87-NEXT: calll __fixsfti
; X86-X87-NEXT: subl $4, %esp ; X86-X87-NEXT: subl $4, %esp
; X86-X87-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; X86-X87-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-X87-NEXT: movb %bh, %ah ; X86-X87-NEXT: movb %bh, %ah
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $0, %eax ; X86-X87-NEXT: movl $0, %eax
; X86-X87-NEXT: movl $0, %ebx ; X86-X87-NEXT: movl $0, %ebx
; X86-X87-NEXT: jae .LBB9_1 ; X86-X87-NEXT: jae .LBB9_1
; X86-X87-NEXT: # %bb.2: ; X86-X87-NEXT: # %bb.2:
; X86-X87-NEXT: movl $0, %edx ; X86-X87-NEXT: movl $0, %edx
; X86-X87-NEXT: jae .LBB9_3 ; X86-X87-NEXT: jae .LBB9_3
; X86-X87-NEXT: .LBB9_4: ; X86-X87-NEXT: .LBB9_4:
; X86-X87-NEXT: movl $-2147483648, %ecx # imm = 0x80000000 ; X86-X87-NEXT: movl $-2147483648, %ecx # imm = 0x80000000
; X86-X87-NEXT: jb .LBB9_6 ; X86-X87-NEXT: jb .LBB9_6
; X86-X87-NEXT: .LBB9_5: ; X86-X87-NEXT: .LBB9_5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB9_6: ; X86-X87-NEXT: .LBB9_6:
; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload ; X86-X87-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF ; X86-X87-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
; X86-X87-NEXT: ja .LBB9_8 ; X86-X87-NEXT: ja .LBB9_8
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: movss %xmm0, {{[0-9]+}}(%esp) ; X86-SSE-NEXT: movss %xmm0, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl %eax, (%esp) ; X86-SSE-NEXT: movl %eax, (%esp)
; X86-SSE-NEXT: calll __fixsfti ; X86-SSE-NEXT: calll __fixsfti
; X86-SSE-NEXT: subl $4, %esp ; X86-SSE-NEXT: subl $4, %esp
; X86-SSE-NEXT: xorl %ecx, %ecx ; X86-SSE-NEXT: xorl %ecx, %ecx
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: ucomiss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: cmovbl %ecx, %eax ; X86-SSE-NEXT: cmovbl %ecx, %eax
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: cmovbl %ecx, %edx ; X86-SSE-NEXT: cmovbl %ecx, %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-SSE-NEXT: cmovbl %ecx, %edi ; X86-SSE-NEXT: cmovbl %ecx, %edi
; X86-SSE-NEXT: movl $-2147483648, %ebx # imm = 0x80000000 ; X86-SSE-NEXT: movl $-2147483648, %ebx # imm = 0x80000000
; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %ebx ; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %ebx
; X86-SSE-NEXT: ucomiss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $2147483647, %ebp # imm = 0x7FFFFFFF ; X86-SSE-NEXT: movl $2147483647, %ebp # imm = 0x7FFFFFFF
; X86-SSE-NEXT: cmovbel %ebx, %ebp ; X86-SSE-NEXT: cmovbel %ebx, %ebp
; X86-SSE-NEXT: movl $-1, %ebx ; X86-SSE-NEXT: movl $-1, %ebx
; X86-SSE-NEXT: cmoval %ebx, %edi ; X86-SSE-NEXT: cmoval %ebx, %edi
; X86-SSE-NEXT: cmoval %ebx, %edx ; X86-SSE-NEXT: cmoval %ebx, %edx
; X86-SSE-NEXT: cmoval %ebx, %eax ; X86-SSE-NEXT: cmoval %ebx, %eax
; X86-SSE-NEXT: ucomiss %xmm0, %xmm0 ; X86-SSE-NEXT: ucomiss %xmm0, %xmm0
; X86-SSE-NEXT: cmovpl %ecx, %eax ; X86-SSE-NEXT: cmovpl %ecx, %eax
▲ Show 20 Lines • Show All 135 Lines • ▼ Show 20 Lines
; X86-X87-NEXT: fldl {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldl {{[0-9]+}}(%esp)
; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00
; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fists {{[0-9]+}}(%esp) ; X86-X87-NEXT: fists {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movb $-128, %dl ; X86-X87-NEXT: movb $-128, %dl
; X86-X87-NEXT: jb .LBB11_2 ; X86-X87-NEXT: jb .LBB11_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movb {{[0-9]+}}(%esp), %dl ; X86-X87-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-X87-NEXT: .LBB11_2: ; X86-X87-NEXT: .LBB11_2:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movb $127, %cl ; X86-X87-NEXT: movb $127, %cl
; X86-X87-NEXT: ja .LBB11_4 ; X86-X87-NEXT: ja .LBB11_4
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; X86-X87-NEXT: fldl {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldl {{[0-9]+}}(%esp)
; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00
; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fists {{[0-9]+}}(%esp) ; X86-X87-NEXT: fists {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movw $-4096, %cx # imm = 0xF000 ; X86-X87-NEXT: movw $-4096, %cx # imm = 0xF000
; X86-X87-NEXT: jb .LBB12_2 ; X86-X87-NEXT: jb .LBB12_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB12_2: ; X86-X87-NEXT: .LBB12_2:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $4095, %edx # imm = 0xFFF ; X86-X87-NEXT: movl $4095, %edx # imm = 0xFFF
; X86-X87-NEXT: ja .LBB12_4 ; X86-X87-NEXT: ja .LBB12_4
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; X86-X87-NEXT: fldl {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldl {{[0-9]+}}(%esp)
; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00
; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fists {{[0-9]+}}(%esp) ; X86-X87-NEXT: fists {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movw $-32768, %cx # imm = 0x8000 ; X86-X87-NEXT: movw $-32768, %cx # imm = 0x8000
; X86-X87-NEXT: jb .LBB13_2 ; X86-X87-NEXT: jb .LBB13_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB13_2: ; X86-X87-NEXT: .LBB13_2:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $32767, %edx # imm = 0x7FFF ; X86-X87-NEXT: movl $32767, %edx # imm = 0x7FFF
; X86-X87-NEXT: ja .LBB13_4 ; X86-X87-NEXT: ja .LBB13_4
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; X86-X87-NEXT: fldl {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldl {{[0-9]+}}(%esp)
; X86-X87-NEXT: fnstcw (%esp) ; X86-X87-NEXT: fnstcw (%esp)
; X86-X87-NEXT: movzwl (%esp), %eax ; X86-X87-NEXT: movzwl (%esp), %eax
; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00
; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fistl {{[0-9]+}}(%esp) ; X86-X87-NEXT: fistl {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw (%esp) ; X86-X87-NEXT: fldcw (%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $-262144, %ecx # imm = 0xFFFC0000 ; X86-X87-NEXT: movl $-262144, %ecx # imm = 0xFFFC0000
; X86-X87-NEXT: jb .LBB14_2 ; X86-X87-NEXT: jb .LBB14_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB14_2: ; X86-X87-NEXT: .LBB14_2:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $262143, %edx # imm = 0x3FFFF ; X86-X87-NEXT: movl $262143, %edx # imm = 0x3FFFF
; X86-X87-NEXT: ja .LBB14_4 ; X86-X87-NEXT: ja .LBB14_4
Show All 13 Lines
; X86-X87-NEXT: addl $8, %esp ; X86-X87-NEXT: addl $8, %esp
; X86-X87-NEXT: retl ; X86-X87-NEXT: retl
; ;
; X86-SSE-LABEL: test_signed_i19_f64: ; X86-SSE-LABEL: test_signed_i19_f64:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE-NEXT: xorl %eax, %eax ; X86-SSE-NEXT: xorl %eax, %eax
; X86-SSE-NEXT: ucomisd %xmm0, %xmm0 ; X86-SSE-NEXT: ucomisd %xmm0, %xmm0
; X86-SSE-NEXT: maxsd {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: maxsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: minsd {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: minsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: cvttsd2si %xmm0, %ecx ; X86-SSE-NEXT: cvttsd2si %xmm0, %ecx
; X86-SSE-NEXT: cmovnpl %ecx, %eax ; X86-SSE-NEXT: cmovnpl %ecx, %eax
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-LABEL: test_signed_i19_f64: ; X64-LABEL: test_signed_i19_f64:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: xorl %eax, %eax ; X64-NEXT: xorl %eax, %eax
; X64-NEXT: ucomisd %xmm0, %xmm0 ; X64-NEXT: ucomisd %xmm0, %xmm0
Show All 13 Lines
; X86-X87-NEXT: fldl {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldl {{[0-9]+}}(%esp)
; X86-X87-NEXT: fnstcw (%esp) ; X86-X87-NEXT: fnstcw (%esp)
; X86-X87-NEXT: movzwl (%esp), %eax ; X86-X87-NEXT: movzwl (%esp), %eax
; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00
; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fistl {{[0-9]+}}(%esp) ; X86-X87-NEXT: fistl {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw (%esp) ; X86-X87-NEXT: fldcw (%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $-2147483648, %ecx # imm = 0x80000000 ; X86-X87-NEXT: movl $-2147483648, %ecx # imm = 0x80000000
; X86-X87-NEXT: jb .LBB15_2 ; X86-X87-NEXT: jb .LBB15_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB15_2: ; X86-X87-NEXT: .LBB15_2:
; X86-X87-NEXT: fldl {{\.LCPI.*}} ; X86-X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $2147483647, %edx # imm = 0x7FFFFFFF ; X86-X87-NEXT: movl $2147483647, %edx # imm = 0x7FFFFFFF
; X86-X87-NEXT: ja .LBB15_4 ; X86-X87-NEXT: ja .LBB15_4
Show All 13 Lines
; X86-X87-NEXT: addl $8, %esp ; X86-X87-NEXT: addl $8, %esp
; X86-X87-NEXT: retl ; X86-X87-NEXT: retl
; ;
; X86-SSE-LABEL: test_signed_i32_f64: ; X86-SSE-LABEL: test_signed_i32_f64:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE-NEXT: xorl %eax, %eax ; X86-SSE-NEXT: xorl %eax, %eax
; X86-SSE-NEXT: ucomisd %xmm0, %xmm0 ; X86-SSE-NEXT: ucomisd %xmm0, %xmm0
; X86-SSE-NEXT: maxsd {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: maxsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: minsd {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: minsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: cvttsd2si %xmm0, %ecx ; X86-SSE-NEXT: cvttsd2si %xmm0, %ecx
; X86-SSE-NEXT: cmovnpl %ecx, %eax ; X86-SSE-NEXT: cmovnpl %ecx, %eax
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-LABEL: test_signed_i32_f64: ; X64-LABEL: test_signed_i32_f64:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: xorl %eax, %eax ; X64-NEXT: xorl %eax, %eax
; X64-NEXT: ucomisd %xmm0, %xmm0 ; X64-NEXT: ucomisd %xmm0, %xmm0
Show All 16 Lines
; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00
; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fld %st(0) ; X86-X87-NEXT: fld %st(0)
; X86-X87-NEXT: fistpll {{[0-9]+}}(%esp) ; X86-X87-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $0, %edx ; X86-X87-NEXT: movl $0, %edx
; X86-X87-NEXT: jb .LBB16_2 ; X86-X87-NEXT: jb .LBB16_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-X87-NEXT: .LBB16_2: ; X86-X87-NEXT: .LBB16_2:
; X86-X87-NEXT: movl $-131072, %edi # imm = 0xFFFE0000 ; X86-X87-NEXT: movl $-131072, %edi # imm = 0xFFFE0000
; X86-X87-NEXT: jb .LBB16_4 ; X86-X87-NEXT: jb .LBB16_4
; X86-X87-NEXT: # %bb.3: ; X86-X87-NEXT: # %bb.3:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-X87-NEXT: .LBB16_4: ; X86-X87-NEXT: .LBB16_4:
; X86-X87-NEXT: fldl {{\.LCPI.*}} ; X86-X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $131071, %esi # imm = 0x1FFFF ; X86-X87-NEXT: movl $131071, %esi # imm = 0x1FFFF
; X86-X87-NEXT: ja .LBB16_6 ; X86-X87-NEXT: ja .LBB16_6
Show All 31 Lines
; X86-SSE-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-SSE-NEXT: orl $3072, %eax # imm = 0xC00
; X86-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fistpll {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: xorl %ecx, %ecx ; X86-SSE-NEXT: xorl %ecx, %ecx
; X86-SSE-NEXT: ucomisd {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomisd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-SSE-NEXT: cmovbl %ecx, %esi ; X86-SSE-NEXT: cmovbl %ecx, %esi
; X86-SSE-NEXT: movl $-131072, %eax # imm = 0xFFFE0000 ; X86-SSE-NEXT: movl $-131072, %eax # imm = 0xFFFE0000
; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: ucomisd {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomisd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $131071, %edx # imm = 0x1FFFF ; X86-SSE-NEXT: movl $131071, %edx # imm = 0x1FFFF
; X86-SSE-NEXT: cmovbel %eax, %edx ; X86-SSE-NEXT: cmovbel %eax, %edx
; X86-SSE-NEXT: movl $-1, %eax ; X86-SSE-NEXT: movl $-1, %eax
; X86-SSE-NEXT: cmovbel %esi, %eax ; X86-SSE-NEXT: cmovbel %esi, %eax
; X86-SSE-NEXT: ucomisd %xmm0, %xmm0 ; X86-SSE-NEXT: ucomisd %xmm0, %xmm0
; X86-SSE-NEXT: cmovpl %ecx, %eax ; X86-SSE-NEXT: cmovpl %ecx, %eax
; X86-SSE-NEXT: cmovpl %ecx, %edx ; X86-SSE-NEXT: cmovpl %ecx, %edx
; X86-SSE-NEXT: addl $16, %esp ; X86-SSE-NEXT: addl $16, %esp
Show All 23 Lines
; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00
; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fld %st(0) ; X86-X87-NEXT: fld %st(0)
; X86-X87-NEXT: fistpll {{[0-9]+}}(%esp) ; X86-X87-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $0, %edx ; X86-X87-NEXT: movl $0, %edx
; X86-X87-NEXT: jb .LBB17_2 ; X86-X87-NEXT: jb .LBB17_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-X87-NEXT: .LBB17_2: ; X86-X87-NEXT: .LBB17_2:
; X86-X87-NEXT: movl $-2147483648, %edi # imm = 0x80000000 ; X86-X87-NEXT: movl $-2147483648, %edi # imm = 0x80000000
; X86-X87-NEXT: jb .LBB17_4 ; X86-X87-NEXT: jb .LBB17_4
; X86-X87-NEXT: # %bb.3: ; X86-X87-NEXT: # %bb.3:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-X87-NEXT: .LBB17_4: ; X86-X87-NEXT: .LBB17_4:
; X86-X87-NEXT: fldl {{\.LCPI.*}} ; X86-X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $2147483647, %esi # imm = 0x7FFFFFFF ; X86-X87-NEXT: movl $2147483647, %esi # imm = 0x7FFFFFFF
; X86-X87-NEXT: ja .LBB17_6 ; X86-X87-NEXT: ja .LBB17_6
Show All 31 Lines
; X86-SSE-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-SSE-NEXT: orl $3072, %eax # imm = 0xC00
; X86-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fistpll {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: xorl %ecx, %ecx ; X86-SSE-NEXT: xorl %ecx, %ecx
; X86-SSE-NEXT: ucomisd {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomisd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-SSE-NEXT: cmovbl %ecx, %esi ; X86-SSE-NEXT: cmovbl %ecx, %esi
; X86-SSE-NEXT: movl $-2147483648, %eax # imm = 0x80000000 ; X86-SSE-NEXT: movl $-2147483648, %eax # imm = 0x80000000
; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: ucomisd {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomisd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $2147483647, %edx # imm = 0x7FFFFFFF ; X86-SSE-NEXT: movl $2147483647, %edx # imm = 0x7FFFFFFF
; X86-SSE-NEXT: cmovbel %eax, %edx ; X86-SSE-NEXT: cmovbel %eax, %edx
; X86-SSE-NEXT: movl $-1, %eax ; X86-SSE-NEXT: movl $-1, %eax
; X86-SSE-NEXT: cmovbel %esi, %eax ; X86-SSE-NEXT: cmovbel %esi, %eax
; X86-SSE-NEXT: ucomisd %xmm0, %xmm0 ; X86-SSE-NEXT: ucomisd %xmm0, %xmm0
; X86-SSE-NEXT: cmovpl %ecx, %eax ; X86-SSE-NEXT: cmovpl %ecx, %eax
; X86-SSE-NEXT: cmovpl %ecx, %edx ; X86-SSE-NEXT: cmovpl %ecx, %edx
; X86-SSE-NEXT: addl $16, %esp ; X86-SSE-NEXT: addl $16, %esp
Show All 21 Lines
; X86-X87-NEXT: pushl %ebx ; X86-X87-NEXT: pushl %ebx
; X86-X87-NEXT: pushl %edi ; X86-X87-NEXT: pushl %edi
; X86-X87-NEXT: pushl %esi ; X86-X87-NEXT: pushl %esi
; X86-X87-NEXT: subl $60, %esp ; X86-X87-NEXT: subl $60, %esp
; X86-X87-NEXT: fldl {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldl {{[0-9]+}}(%esp)
; X86-X87-NEXT: fstl {{[0-9]+}}(%esp) ; X86-X87-NEXT: fstl {{[0-9]+}}(%esp)
; X86-X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: movl %eax, (%esp) ; X86-X87-NEXT: movl %eax, (%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fstl {{[-0-9]+}}(%e{{[sb]}}p) # 8-byte Folded Spill ; X86-X87-NEXT: fstl {{[-0-9]+}}(%e{{[sb]}}p) # 8-byte Folded Spill
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: movl %eax, %ebx ; X86-X87-NEXT: movl %eax, %ebx
; X86-X87-NEXT: calll __fixdfti ; X86-X87-NEXT: calll __fixdfti
; X86-X87-NEXT: subl $4, %esp ; X86-X87-NEXT: subl $4, %esp
; X86-X87-NEXT: xorl %edx, %edx ; X86-X87-NEXT: xorl %edx, %edx
Show All 11 Lines
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ebp ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X86-X87-NEXT: .LBB18_4: ; X86-X87-NEXT: .LBB18_4:
; X86-X87-NEXT: movl $0, %edi ; X86-X87-NEXT: movl $0, %edi
; X86-X87-NEXT: jb .LBB18_6 ; X86-X87-NEXT: jb .LBB18_6
; X86-X87-NEXT: # %bb.5: ; X86-X87-NEXT: # %bb.5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-X87-NEXT: .LBB18_6: ; X86-X87-NEXT: .LBB18_6:
; X86-X87-NEXT: fldl {{\.LCPI.*}} ; X86-X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fldl {{[-0-9]+}}(%e{{[sb]}}p) # 8-byte Folded Reload ; X86-X87-NEXT: fldl {{[-0-9]+}}(%e{{[sb]}}p) # 8-byte Folded Reload
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $-1, %eax ; X86-X87-NEXT: movl $-1, %eax
; X86-X87-NEXT: movl $-1, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; X86-X87-NEXT: movl $-1, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE-NEXT: movsd %xmm0, {{[0-9]+}}(%esp) ; X86-SSE-NEXT: movsd %xmm0, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl %eax, (%esp) ; X86-SSE-NEXT: movl %eax, (%esp)
; X86-SSE-NEXT: calll __fixdfti ; X86-SSE-NEXT: calll __fixdfti
; X86-SSE-NEXT: subl $4, %esp ; X86-SSE-NEXT: subl $4, %esp
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE-NEXT: xorl %ebp, %ebp ; X86-SSE-NEXT: xorl %ebp, %ebp
; X86-SSE-NEXT: ucomisd {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomisd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $-8, %ebx ; X86-SSE-NEXT: movl $-8, %ebx
; X86-SSE-NEXT: movl $0, %ecx ; X86-SSE-NEXT: movl $0, %ecx
; X86-SSE-NEXT: movl $0, %edx ; X86-SSE-NEXT: movl $0, %edx
; X86-SSE-NEXT: movl $0, %edi ; X86-SSE-NEXT: movl $0, %edi
; X86-SSE-NEXT: jb .LBB18_2 ; X86-SSE-NEXT: jb .LBB18_2
; X86-SSE-NEXT: # %bb.1: ; X86-SSE-NEXT: # %bb.1:
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ebx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-SSE-NEXT: .LBB18_2: ; X86-SSE-NEXT: .LBB18_2:
; X86-SSE-NEXT: ucomisd {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomisd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $-1, %eax ; X86-SSE-NEXT: movl $-1, %eax
; X86-SSE-NEXT: cmoval %eax, %edi ; X86-SSE-NEXT: cmoval %eax, %edi
; X86-SSE-NEXT: cmoval %eax, %edx ; X86-SSE-NEXT: cmoval %eax, %edx
; X86-SSE-NEXT: cmoval %eax, %ecx ; X86-SSE-NEXT: cmoval %eax, %ecx
; X86-SSE-NEXT: movl $7, %eax ; X86-SSE-NEXT: movl $7, %eax
; X86-SSE-NEXT: cmovbel %ebx, %eax ; X86-SSE-NEXT: cmovbel %ebx, %eax
; X86-SSE-NEXT: ucomisd %xmm0, %xmm0 ; X86-SSE-NEXT: ucomisd %xmm0, %xmm0
; X86-SSE-NEXT: cmovpl %ebp, %eax ; X86-SSE-NEXT: cmovpl %ebp, %eax
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; X86-X87-NEXT: pushl %ebx ; X86-X87-NEXT: pushl %ebx
; X86-X87-NEXT: pushl %edi ; X86-X87-NEXT: pushl %edi
; X86-X87-NEXT: pushl %esi ; X86-X87-NEXT: pushl %esi
; X86-X87-NEXT: subl $60, %esp ; X86-X87-NEXT: subl $60, %esp
; X86-X87-NEXT: fldl {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldl {{[0-9]+}}(%esp)
; X86-X87-NEXT: fstl {{[0-9]+}}(%esp) ; X86-X87-NEXT: fstl {{[0-9]+}}(%esp)
; X86-X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: movl %eax, (%esp) ; X86-X87-NEXT: movl %eax, (%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fstl {{[-0-9]+}}(%e{{[sb]}}p) # 8-byte Folded Spill ; X86-X87-NEXT: fstl {{[-0-9]+}}(%e{{[sb]}}p) # 8-byte Folded Spill
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: movl %eax, %ebx ; X86-X87-NEXT: movl %eax, %ebx
; X86-X87-NEXT: calll __fixdfti ; X86-X87-NEXT: calll __fixdfti
; X86-X87-NEXT: subl $4, %esp ; X86-X87-NEXT: subl $4, %esp
; X86-X87-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; X86-X87-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-X87-NEXT: movb %bh, %ah ; X86-X87-NEXT: movb %bh, %ah
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $0, %eax ; X86-X87-NEXT: movl $0, %eax
; X86-X87-NEXT: movl $0, %ebx ; X86-X87-NEXT: movl $0, %ebx
; X86-X87-NEXT: jae .LBB19_1 ; X86-X87-NEXT: jae .LBB19_1
; X86-X87-NEXT: # %bb.2: ; X86-X87-NEXT: # %bb.2:
; X86-X87-NEXT: movl $0, %edx ; X86-X87-NEXT: movl $0, %edx
; X86-X87-NEXT: jae .LBB19_3 ; X86-X87-NEXT: jae .LBB19_3
; X86-X87-NEXT: .LBB19_4: ; X86-X87-NEXT: .LBB19_4:
; X86-X87-NEXT: movl $-2147483648, %ecx # imm = 0x80000000 ; X86-X87-NEXT: movl $-2147483648, %ecx # imm = 0x80000000
; X86-X87-NEXT: jb .LBB19_6 ; X86-X87-NEXT: jb .LBB19_6
; X86-X87-NEXT: .LBB19_5: ; X86-X87-NEXT: .LBB19_5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB19_6: ; X86-X87-NEXT: .LBB19_6:
; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-X87-NEXT: fldl {{\.LCPI.*}} ; X86-X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fldl {{[-0-9]+}}(%e{{[sb]}}p) # 8-byte Folded Reload ; X86-X87-NEXT: fldl {{[-0-9]+}}(%e{{[sb]}}p) # 8-byte Folded Reload
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF ; X86-X87-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
; X86-X87-NEXT: ja .LBB19_8 ; X86-X87-NEXT: ja .LBB19_8
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE-NEXT: movsd %xmm0, {{[0-9]+}}(%esp) ; X86-SSE-NEXT: movsd %xmm0, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl %eax, (%esp) ; X86-SSE-NEXT: movl %eax, (%esp)
; X86-SSE-NEXT: calll __fixdfti ; X86-SSE-NEXT: calll __fixdfti
; X86-SSE-NEXT: subl $4, %esp ; X86-SSE-NEXT: subl $4, %esp
; X86-SSE-NEXT: xorl %ecx, %ecx ; X86-SSE-NEXT: xorl %ecx, %ecx
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE-NEXT: ucomisd {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomisd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: cmovbl %ecx, %eax ; X86-SSE-NEXT: cmovbl %ecx, %eax
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: cmovbl %ecx, %edx ; X86-SSE-NEXT: cmovbl %ecx, %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-SSE-NEXT: cmovbl %ecx, %edi ; X86-SSE-NEXT: cmovbl %ecx, %edi
; X86-SSE-NEXT: movl $-2147483648, %ebx # imm = 0x80000000 ; X86-SSE-NEXT: movl $-2147483648, %ebx # imm = 0x80000000
; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %ebx ; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %ebx
; X86-SSE-NEXT: ucomisd {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomisd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $2147483647, %ebp # imm = 0x7FFFFFFF ; X86-SSE-NEXT: movl $2147483647, %ebp # imm = 0x7FFFFFFF
; X86-SSE-NEXT: cmovbel %ebx, %ebp ; X86-SSE-NEXT: cmovbel %ebx, %ebp
; X86-SSE-NEXT: movl $-1, %ebx ; X86-SSE-NEXT: movl $-1, %ebx
; X86-SSE-NEXT: cmoval %ebx, %edi ; X86-SSE-NEXT: cmoval %ebx, %edi
; X86-SSE-NEXT: cmoval %ebx, %edx ; X86-SSE-NEXT: cmoval %ebx, %edx
; X86-SSE-NEXT: cmoval %ebx, %eax ; X86-SSE-NEXT: cmoval %ebx, %eax
; X86-SSE-NEXT: ucomisd %xmm0, %xmm0 ; X86-SSE-NEXT: ucomisd %xmm0, %xmm0
; X86-SSE-NEXT: cmovpl %ecx, %eax ; X86-SSE-NEXT: cmovpl %ecx, %eax
▲ Show 20 Lines • Show All 149 Lines • ▼ Show 20 Lines
; X86-X87-NEXT: calll __gnu_h2f_ieee ; X86-X87-NEXT: calll __gnu_h2f_ieee
; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00
; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fists {{[0-9]+}}(%esp) ; X86-X87-NEXT: fists {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movb $-128, %dl ; X86-X87-NEXT: movb $-128, %dl
; X86-X87-NEXT: jb .LBB21_2 ; X86-X87-NEXT: jb .LBB21_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movb {{[0-9]+}}(%esp), %dl ; X86-X87-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-X87-NEXT: .LBB21_2: ; X86-X87-NEXT: .LBB21_2:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movb $127, %cl ; X86-X87-NEXT: movb $127, %cl
; X86-X87-NEXT: ja .LBB21_4 ; X86-X87-NEXT: ja .LBB21_4
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; X86-X87-NEXT: calll __gnu_h2f_ieee ; X86-X87-NEXT: calll __gnu_h2f_ieee
; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00
; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fists {{[0-9]+}}(%esp) ; X86-X87-NEXT: fists {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movw $-4096, %cx # imm = 0xF000 ; X86-X87-NEXT: movw $-4096, %cx # imm = 0xF000
; X86-X87-NEXT: jb .LBB22_2 ; X86-X87-NEXT: jb .LBB22_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB22_2: ; X86-X87-NEXT: .LBB22_2:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $4095, %edx # imm = 0xFFF ; X86-X87-NEXT: movl $4095, %edx # imm = 0xFFF
; X86-X87-NEXT: ja .LBB22_4 ; X86-X87-NEXT: ja .LBB22_4
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; X86-X87-NEXT: calll __gnu_h2f_ieee ; X86-X87-NEXT: calll __gnu_h2f_ieee
; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00
; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fists {{[0-9]+}}(%esp) ; X86-X87-NEXT: fists {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movw $-32768, %cx # imm = 0x8000 ; X86-X87-NEXT: movw $-32768, %cx # imm = 0x8000
; X86-X87-NEXT: jb .LBB23_2 ; X86-X87-NEXT: jb .LBB23_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB23_2: ; X86-X87-NEXT: .LBB23_2:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $32767, %edx # imm = 0x7FFF ; X86-X87-NEXT: movl $32767, %edx # imm = 0x7FFF
; X86-X87-NEXT: ja .LBB23_4 ; X86-X87-NEXT: ja .LBB23_4
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; X86-X87-NEXT: calll __gnu_h2f_ieee ; X86-X87-NEXT: calll __gnu_h2f_ieee
; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00
; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fistl {{[0-9]+}}(%esp) ; X86-X87-NEXT: fistl {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $-262144, %ecx # imm = 0xFFFC0000 ; X86-X87-NEXT: movl $-262144, %ecx # imm = 0xFFFC0000
; X86-X87-NEXT: jb .LBB24_2 ; X86-X87-NEXT: jb .LBB24_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB24_2: ; X86-X87-NEXT: .LBB24_2:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $262143, %edx # imm = 0x3FFFF ; X86-X87-NEXT: movl $262143, %edx # imm = 0x3FFFF
; X86-X87-NEXT: ja .LBB24_4 ; X86-X87-NEXT: ja .LBB24_4
Show All 18 Lines
; X86-SSE-NEXT: subl $12, %esp ; X86-SSE-NEXT: subl $12, %esp
; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl %eax, (%esp) ; X86-SSE-NEXT: movl %eax, (%esp)
; X86-SSE-NEXT: calll __gnu_h2f_ieee ; X86-SSE-NEXT: calll __gnu_h2f_ieee
; X86-SSE-NEXT: fstps {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fstps {{[0-9]+}}(%esp)
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: xorl %eax, %eax ; X86-SSE-NEXT: xorl %eax, %eax
; X86-SSE-NEXT: ucomiss %xmm0, %xmm0 ; X86-SSE-NEXT: ucomiss %xmm0, %xmm0
; X86-SSE-NEXT: maxss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: maxss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: minss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: minss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: cvttss2si %xmm0, %ecx ; X86-SSE-NEXT: cvttss2si %xmm0, %ecx
; X86-SSE-NEXT: cmovnpl %ecx, %eax ; X86-SSE-NEXT: cmovnpl %ecx, %eax
; X86-SSE-NEXT: addl $12, %esp ; X86-SSE-NEXT: addl $12, %esp
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-LABEL: test_signed_i19_f16: ; X64-LABEL: test_signed_i19_f16:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: pushq %rax ; X64-NEXT: pushq %rax
Show All 20 Lines
; X86-X87-NEXT: calll __gnu_h2f_ieee ; X86-X87-NEXT: calll __gnu_h2f_ieee
; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00
; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fistl {{[0-9]+}}(%esp) ; X86-X87-NEXT: fistl {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $-2147483648, %ecx # imm = 0x80000000 ; X86-X87-NEXT: movl $-2147483648, %ecx # imm = 0x80000000
; X86-X87-NEXT: jb .LBB25_2 ; X86-X87-NEXT: jb .LBB25_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB25_2: ; X86-X87-NEXT: .LBB25_2:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $2147483647, %edx # imm = 0x7FFFFFFF ; X86-X87-NEXT: movl $2147483647, %edx # imm = 0x7FFFFFFF
; X86-X87-NEXT: ja .LBB25_4 ; X86-X87-NEXT: ja .LBB25_4
Show All 17 Lines
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: subl $12, %esp ; X86-SSE-NEXT: subl $12, %esp
; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl %eax, (%esp) ; X86-SSE-NEXT: movl %eax, (%esp)
; X86-SSE-NEXT: calll __gnu_h2f_ieee ; X86-SSE-NEXT: calll __gnu_h2f_ieee
; X86-SSE-NEXT: fstps {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fstps {{[0-9]+}}(%esp)
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: cvttss2si %xmm0, %eax ; X86-SSE-NEXT: cvttss2si %xmm0, %eax
; X86-SSE-NEXT: ucomiss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $2147483647, %ecx # imm = 0x7FFFFFFF ; X86-SSE-NEXT: movl $2147483647, %ecx # imm = 0x7FFFFFFF
; X86-SSE-NEXT: cmovbel %eax, %ecx ; X86-SSE-NEXT: cmovbel %eax, %ecx
; X86-SSE-NEXT: xorl %eax, %eax ; X86-SSE-NEXT: xorl %eax, %eax
; X86-SSE-NEXT: ucomiss %xmm0, %xmm0 ; X86-SSE-NEXT: ucomiss %xmm0, %xmm0
; X86-SSE-NEXT: cmovnpl %ecx, %eax ; X86-SSE-NEXT: cmovnpl %ecx, %eax
; X86-SSE-NEXT: addl $12, %esp ; X86-SSE-NEXT: addl $12, %esp
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
Show All 27 Lines
; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00
; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fld %st(0) ; X86-X87-NEXT: fld %st(0)
; X86-X87-NEXT: fistpll {{[0-9]+}}(%esp) ; X86-X87-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $0, %edx ; X86-X87-NEXT: movl $0, %edx
; X86-X87-NEXT: jb .LBB26_2 ; X86-X87-NEXT: jb .LBB26_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-X87-NEXT: .LBB26_2: ; X86-X87-NEXT: .LBB26_2:
; X86-X87-NEXT: movl $-131072, %edi # imm = 0xFFFE0000 ; X86-X87-NEXT: movl $-131072, %edi # imm = 0xFFFE0000
; X86-X87-NEXT: jb .LBB26_4 ; X86-X87-NEXT: jb .LBB26_4
; X86-X87-NEXT: # %bb.3: ; X86-X87-NEXT: # %bb.3:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-X87-NEXT: .LBB26_4: ; X86-X87-NEXT: .LBB26_4:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $131071, %esi # imm = 0x1FFFF ; X86-X87-NEXT: movl $131071, %esi # imm = 0x1FFFF
; X86-X87-NEXT: ja .LBB26_6 ; X86-X87-NEXT: ja .LBB26_6
Show All 35 Lines
; X86-SSE-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-SSE-NEXT: orl $3072, %eax # imm = 0xC00
; X86-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fistpll {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: xorl %ecx, %ecx ; X86-SSE-NEXT: xorl %ecx, %ecx
; X86-SSE-NEXT: ucomiss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-SSE-NEXT: cmovbl %ecx, %esi ; X86-SSE-NEXT: cmovbl %ecx, %esi
; X86-SSE-NEXT: movl $-131072, %eax # imm = 0xFFFE0000 ; X86-SSE-NEXT: movl $-131072, %eax # imm = 0xFFFE0000
; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: ucomiss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $131071, %edx # imm = 0x1FFFF ; X86-SSE-NEXT: movl $131071, %edx # imm = 0x1FFFF
; X86-SSE-NEXT: cmovbel %eax, %edx ; X86-SSE-NEXT: cmovbel %eax, %edx
; X86-SSE-NEXT: movl $-1, %eax ; X86-SSE-NEXT: movl $-1, %eax
; X86-SSE-NEXT: cmovbel %esi, %eax ; X86-SSE-NEXT: cmovbel %esi, %eax
; X86-SSE-NEXT: ucomiss %xmm0, %xmm0 ; X86-SSE-NEXT: ucomiss %xmm0, %xmm0
; X86-SSE-NEXT: cmovpl %ecx, %eax ; X86-SSE-NEXT: cmovpl %ecx, %eax
; X86-SSE-NEXT: cmovpl %ecx, %edx ; X86-SSE-NEXT: cmovpl %ecx, %edx
; X86-SSE-NEXT: addl $24, %esp ; X86-SSE-NEXT: addl $24, %esp
Show All 33 Lines
; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00
; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fld %st(0) ; X86-X87-NEXT: fld %st(0)
; X86-X87-NEXT: fistpll {{[0-9]+}}(%esp) ; X86-X87-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $0, %edx ; X86-X87-NEXT: movl $0, %edx
; X86-X87-NEXT: jb .LBB27_2 ; X86-X87-NEXT: jb .LBB27_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-X87-NEXT: .LBB27_2: ; X86-X87-NEXT: .LBB27_2:
; X86-X87-NEXT: movl $-2147483648, %edi # imm = 0x80000000 ; X86-X87-NEXT: movl $-2147483648, %edi # imm = 0x80000000
; X86-X87-NEXT: jb .LBB27_4 ; X86-X87-NEXT: jb .LBB27_4
; X86-X87-NEXT: # %bb.3: ; X86-X87-NEXT: # %bb.3:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-X87-NEXT: .LBB27_4: ; X86-X87-NEXT: .LBB27_4:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $2147483647, %esi # imm = 0x7FFFFFFF ; X86-X87-NEXT: movl $2147483647, %esi # imm = 0x7FFFFFFF
; X86-X87-NEXT: ja .LBB27_6 ; X86-X87-NEXT: ja .LBB27_6
Show All 35 Lines
; X86-SSE-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-SSE-NEXT: orl $3072, %eax # imm = 0xC00
; X86-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fistpll {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: xorl %ecx, %ecx ; X86-SSE-NEXT: xorl %ecx, %ecx
; X86-SSE-NEXT: ucomiss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-SSE-NEXT: cmovbl %ecx, %esi ; X86-SSE-NEXT: cmovbl %ecx, %esi
; X86-SSE-NEXT: movl $-2147483648, %eax # imm = 0x80000000 ; X86-SSE-NEXT: movl $-2147483648, %eax # imm = 0x80000000
; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: ucomiss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $2147483647, %edx # imm = 0x7FFFFFFF ; X86-SSE-NEXT: movl $2147483647, %edx # imm = 0x7FFFFFFF
; X86-SSE-NEXT: cmovbel %eax, %edx ; X86-SSE-NEXT: cmovbel %eax, %edx
; X86-SSE-NEXT: movl $-1, %eax ; X86-SSE-NEXT: movl $-1, %eax
; X86-SSE-NEXT: cmovbel %esi, %eax ; X86-SSE-NEXT: cmovbel %esi, %eax
; X86-SSE-NEXT: ucomiss %xmm0, %xmm0 ; X86-SSE-NEXT: ucomiss %xmm0, %xmm0
; X86-SSE-NEXT: cmovpl %ecx, %eax ; X86-SSE-NEXT: cmovpl %ecx, %eax
; X86-SSE-NEXT: cmovpl %ecx, %edx ; X86-SSE-NEXT: cmovpl %ecx, %edx
; X86-SSE-NEXT: addl $24, %esp ; X86-SSE-NEXT: addl $24, %esp
Show All 27 Lines
; X86-X87-NEXT: pushl %esi ; X86-X87-NEXT: pushl %esi
; X86-X87-NEXT: subl $44, %esp ; X86-X87-NEXT: subl $44, %esp
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: movl %eax, (%esp) ; X86-X87-NEXT: movl %eax, (%esp)
; X86-X87-NEXT: calll __gnu_h2f_ieee ; X86-X87-NEXT: calll __gnu_h2f_ieee
; X86-X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: movl %eax, (%esp) ; X86-X87-NEXT: movl %eax, (%esp)
; X86-X87-NEXT: fsts {{[0-9]+}}(%esp) ; X86-X87-NEXT: fsts {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fsts {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; X86-X87-NEXT: fsts {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: movl %eax, %ebx ; X86-X87-NEXT: movl %eax, %ebx
; X86-X87-NEXT: calll __fixsfti ; X86-X87-NEXT: calll __fixsfti
; X86-X87-NEXT: subl $4, %esp ; X86-X87-NEXT: subl $4, %esp
; X86-X87-NEXT: xorl %edx, %edx ; X86-X87-NEXT: xorl %edx, %edx
Show All 11 Lines
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ebp ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X86-X87-NEXT: .LBB28_4: ; X86-X87-NEXT: .LBB28_4:
; X86-X87-NEXT: movl $0, %edi ; X86-X87-NEXT: movl $0, %edi
; X86-X87-NEXT: jb .LBB28_6 ; X86-X87-NEXT: jb .LBB28_6
; X86-X87-NEXT: # %bb.5: ; X86-X87-NEXT: # %bb.5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-X87-NEXT: .LBB28_6: ; X86-X87-NEXT: .LBB28_6:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload ; X86-X87-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $-1, %eax ; X86-X87-NEXT: movl $-1, %eax
; X86-X87-NEXT: movl $-1, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; X86-X87-NEXT: movl $-1, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: movss %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-SSE-NEXT: movss %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-SSE-NEXT: movss %xmm0, {{[0-9]+}}(%esp) ; X86-SSE-NEXT: movss %xmm0, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: calll __fixsfti ; X86-SSE-NEXT: calll __fixsfti
; X86-SSE-NEXT: subl $4, %esp ; X86-SSE-NEXT: subl $4, %esp
; X86-SSE-NEXT: movss {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 4-byte Reload ; X86-SSE-NEXT: movss {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 4-byte Reload
; X86-SSE-NEXT: # xmm0 = mem[0],zero,zero,zero ; X86-SSE-NEXT: # xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: xorl %ebp, %ebp ; X86-SSE-NEXT: xorl %ebp, %ebp
; X86-SSE-NEXT: ucomiss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $-8, %ebx ; X86-SSE-NEXT: movl $-8, %ebx
; X86-SSE-NEXT: movl $0, %ecx ; X86-SSE-NEXT: movl $0, %ecx
; X86-SSE-NEXT: movl $0, %edx ; X86-SSE-NEXT: movl $0, %edx
; X86-SSE-NEXT: movl $0, %edi ; X86-SSE-NEXT: movl $0, %edi
; X86-SSE-NEXT: jb .LBB28_2 ; X86-SSE-NEXT: jb .LBB28_2
; X86-SSE-NEXT: # %bb.1: ; X86-SSE-NEXT: # %bb.1:
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ebx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-SSE-NEXT: .LBB28_2: ; X86-SSE-NEXT: .LBB28_2:
; X86-SSE-NEXT: ucomiss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $-1, %eax ; X86-SSE-NEXT: movl $-1, %eax
; X86-SSE-NEXT: cmoval %eax, %edi ; X86-SSE-NEXT: cmoval %eax, %edi
; X86-SSE-NEXT: cmoval %eax, %edx ; X86-SSE-NEXT: cmoval %eax, %edx
; X86-SSE-NEXT: cmoval %eax, %ecx ; X86-SSE-NEXT: cmoval %eax, %ecx
; X86-SSE-NEXT: movl $7, %eax ; X86-SSE-NEXT: movl $7, %eax
; X86-SSE-NEXT: cmovbel %ebx, %eax ; X86-SSE-NEXT: cmovbel %ebx, %eax
; X86-SSE-NEXT: ucomiss %xmm0, %xmm0 ; X86-SSE-NEXT: ucomiss %xmm0, %xmm0
; X86-SSE-NEXT: cmovpl %ebp, %eax ; X86-SSE-NEXT: cmovpl %ebp, %eax
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; X86-X87-NEXT: pushl %esi ; X86-X87-NEXT: pushl %esi
; X86-X87-NEXT: subl $44, %esp ; X86-X87-NEXT: subl $44, %esp
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: movl %eax, (%esp) ; X86-X87-NEXT: movl %eax, (%esp)
; X86-X87-NEXT: calll __gnu_h2f_ieee ; X86-X87-NEXT: calll __gnu_h2f_ieee
; X86-X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: movl %eax, (%esp) ; X86-X87-NEXT: movl %eax, (%esp)
; X86-X87-NEXT: fsts {{[0-9]+}}(%esp) ; X86-X87-NEXT: fsts {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fsts {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; X86-X87-NEXT: fsts {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: movl %eax, %ebx ; X86-X87-NEXT: movl %eax, %ebx
; X86-X87-NEXT: calll __fixsfti ; X86-X87-NEXT: calll __fixsfti
; X86-X87-NEXT: subl $4, %esp ; X86-X87-NEXT: subl $4, %esp
; X86-X87-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; X86-X87-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-X87-NEXT: movb %bh, %ah ; X86-X87-NEXT: movb %bh, %ah
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $0, %eax ; X86-X87-NEXT: movl $0, %eax
; X86-X87-NEXT: movl $0, %ebx ; X86-X87-NEXT: movl $0, %ebx
; X86-X87-NEXT: jae .LBB29_1 ; X86-X87-NEXT: jae .LBB29_1
; X86-X87-NEXT: # %bb.2: ; X86-X87-NEXT: # %bb.2:
; X86-X87-NEXT: movl $0, %edx ; X86-X87-NEXT: movl $0, %edx
; X86-X87-NEXT: jae .LBB29_3 ; X86-X87-NEXT: jae .LBB29_3
; X86-X87-NEXT: .LBB29_4: ; X86-X87-NEXT: .LBB29_4:
; X86-X87-NEXT: movl $-2147483648, %ecx # imm = 0x80000000 ; X86-X87-NEXT: movl $-2147483648, %ecx # imm = 0x80000000
; X86-X87-NEXT: jb .LBB29_6 ; X86-X87-NEXT: jb .LBB29_6
; X86-X87-NEXT: .LBB29_5: ; X86-X87-NEXT: .LBB29_5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB29_6: ; X86-X87-NEXT: .LBB29_6:
; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload ; X86-X87-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF ; X86-X87-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
; X86-X87-NEXT: ja .LBB29_8 ; X86-X87-NEXT: ja .LBB29_8
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: movss %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-SSE-NEXT: movss %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-SSE-NEXT: movss %xmm0, {{[0-9]+}}(%esp) ; X86-SSE-NEXT: movss %xmm0, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: calll __fixsfti ; X86-SSE-NEXT: calll __fixsfti
; X86-SSE-NEXT: subl $4, %esp ; X86-SSE-NEXT: subl $4, %esp
; X86-SSE-NEXT: xorl %ecx, %ecx ; X86-SSE-NEXT: xorl %ecx, %ecx
; X86-SSE-NEXT: movss {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 4-byte Reload ; X86-SSE-NEXT: movss {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 4-byte Reload
; X86-SSE-NEXT: # xmm0 = mem[0],zero,zero,zero ; X86-SSE-NEXT: # xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: ucomiss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: cmovbl %ecx, %eax ; X86-SSE-NEXT: cmovbl %ecx, %eax
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: cmovbl %ecx, %edx ; X86-SSE-NEXT: cmovbl %ecx, %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-SSE-NEXT: cmovbl %ecx, %edi ; X86-SSE-NEXT: cmovbl %ecx, %edi
; X86-SSE-NEXT: movl $-2147483648, %ebx # imm = 0x80000000 ; X86-SSE-NEXT: movl $-2147483648, %ebx # imm = 0x80000000
; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %ebx ; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %ebx
; X86-SSE-NEXT: ucomiss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $2147483647, %ebp # imm = 0x7FFFFFFF ; X86-SSE-NEXT: movl $2147483647, %ebp # imm = 0x7FFFFFFF
; X86-SSE-NEXT: cmovbel %ebx, %ebp ; X86-SSE-NEXT: cmovbel %ebx, %ebp
; X86-SSE-NEXT: movl $-1, %ebx ; X86-SSE-NEXT: movl $-1, %ebx
; X86-SSE-NEXT: cmoval %ebx, %edi ; X86-SSE-NEXT: cmoval %ebx, %edi
; X86-SSE-NEXT: cmoval %ebx, %edx ; X86-SSE-NEXT: cmoval %ebx, %edx
; X86-SSE-NEXT: cmoval %ebx, %eax ; X86-SSE-NEXT: cmoval %ebx, %eax
; X86-SSE-NEXT: ucomiss %xmm0, %xmm0 ; X86-SSE-NEXT: ucomiss %xmm0, %xmm0
; X86-SSE-NEXT: cmovpl %ecx, %eax ; X86-SSE-NEXT: cmovpl %ecx, %eax
▲ Show 20 Lines • Show All 177 Lines • ▼ Show 20 Lines
; X86-X87-NEXT: fldt {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldt {{[0-9]+}}(%esp)
; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00
; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fists {{[0-9]+}}(%esp) ; X86-X87-NEXT: fists {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movb $-128, %dl ; X86-X87-NEXT: movb $-128, %dl
; X86-X87-NEXT: jb .LBB31_2 ; X86-X87-NEXT: jb .LBB31_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movb {{[0-9]+}}(%esp), %dl ; X86-X87-NEXT: movb {{[0-9]+}}(%esp), %dl
; X86-X87-NEXT: .LBB31_2: ; X86-X87-NEXT: .LBB31_2:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movb $127, %cl ; X86-X87-NEXT: movb $127, %cl
; X86-X87-NEXT: ja .LBB31_4 ; X86-X87-NEXT: ja .LBB31_4
Show All 19 Lines
; X86-SSE-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-SSE-NEXT: orl $3072, %eax # imm = 0xC00
; X86-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fists {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fists {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: flds {{\.LCPI.*}} ; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st ; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1) ; X86-SSE-NEXT: fstp %st(1)
; X86-SSE-NEXT: movl $128, %ecx ; X86-SSE-NEXT: movl $128, %ecx
; X86-SSE-NEXT: cmovael %eax, %ecx ; X86-SSE-NEXT: cmovael %eax, %ecx
; X86-SSE-NEXT: flds {{\.LCPI.*}} ; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st ; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1) ; X86-SSE-NEXT: fstp %st(1)
; X86-SSE-NEXT: movl $127, %edx ; X86-SSE-NEXT: movl $127, %edx
; X86-SSE-NEXT: cmovbel %ecx, %edx ; X86-SSE-NEXT: cmovbel %ecx, %edx
; X86-SSE-NEXT: xorl %eax, %eax ; X86-SSE-NEXT: xorl %eax, %eax
; X86-SSE-NEXT: fucompi %st(0), %st ; X86-SSE-NEXT: fucompi %st(0), %st
; X86-SSE-NEXT: cmovnpl %edx, %eax ; X86-SSE-NEXT: cmovnpl %edx, %eax
Show All 40 Lines
; X86-X87-NEXT: fldt {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldt {{[0-9]+}}(%esp)
; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00
; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fists {{[0-9]+}}(%esp) ; X86-X87-NEXT: fists {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movw $-4096, %cx # imm = 0xF000 ; X86-X87-NEXT: movw $-4096, %cx # imm = 0xF000
; X86-X87-NEXT: jb .LBB32_2 ; X86-X87-NEXT: jb .LBB32_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB32_2: ; X86-X87-NEXT: .LBB32_2:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $4095, %edx # imm = 0xFFF ; X86-X87-NEXT: movl $4095, %edx # imm = 0xFFF
; X86-X87-NEXT: ja .LBB32_4 ; X86-X87-NEXT: ja .LBB32_4
Show All 19 Lines
; X86-SSE-NEXT: fldt {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldt {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-SSE-NEXT: orl $3072, %eax # imm = 0xC00
; X86-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fists {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fists {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: flds {{\.LCPI.*}} ; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st ; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1) ; X86-SSE-NEXT: fstp %st(1)
; X86-SSE-NEXT: movw $-4096, %ax # imm = 0xF000 ; X86-SSE-NEXT: movw $-4096, %ax # imm = 0xF000
; X86-SSE-NEXT: jb .LBB32_2 ; X86-SSE-NEXT: jb .LBB32_2
; X86-SSE-NEXT: # %bb.1: ; X86-SSE-NEXT: # %bb.1:
; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: .LBB32_2: ; X86-SSE-NEXT: .LBB32_2:
; X86-SSE-NEXT: flds {{\.LCPI.*}} ; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st ; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1) ; X86-SSE-NEXT: fstp %st(1)
; X86-SSE-NEXT: movl $4095, %ecx # imm = 0xFFF ; X86-SSE-NEXT: movl $4095, %ecx # imm = 0xFFF
; X86-SSE-NEXT: cmovbel %eax, %ecx ; X86-SSE-NEXT: cmovbel %eax, %ecx
; X86-SSE-NEXT: xorl %eax, %eax ; X86-SSE-NEXT: xorl %eax, %eax
; X86-SSE-NEXT: fucompi %st(0), %st ; X86-SSE-NEXT: fucompi %st(0), %st
; X86-SSE-NEXT: cmovnpl %ecx, %eax ; X86-SSE-NEXT: cmovnpl %ecx, %eax
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; X86-X87-NEXT: fldt {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldt {{[0-9]+}}(%esp)
; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00
; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fists {{[0-9]+}}(%esp) ; X86-X87-NEXT: fists {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movw $-32768, %cx # imm = 0x8000 ; X86-X87-NEXT: movw $-32768, %cx # imm = 0x8000
; X86-X87-NEXT: jb .LBB33_2 ; X86-X87-NEXT: jb .LBB33_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB33_2: ; X86-X87-NEXT: .LBB33_2:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $32767, %edx # imm = 0x7FFF ; X86-X87-NEXT: movl $32767, %edx # imm = 0x7FFF
; X86-X87-NEXT: ja .LBB33_4 ; X86-X87-NEXT: ja .LBB33_4
Show All 19 Lines
; X86-SSE-NEXT: fldt {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldt {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-SSE-NEXT: orl $3072, %eax # imm = 0xC00
; X86-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fists {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fists {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: flds {{\.LCPI.*}} ; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st ; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1) ; X86-SSE-NEXT: fstp %st(1)
; X86-SSE-NEXT: movw $-32768, %ax # imm = 0x8000 ; X86-SSE-NEXT: movw $-32768, %ax # imm = 0x8000
; X86-SSE-NEXT: jb .LBB33_2 ; X86-SSE-NEXT: jb .LBB33_2
; X86-SSE-NEXT: # %bb.1: ; X86-SSE-NEXT: # %bb.1:
; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: .LBB33_2: ; X86-SSE-NEXT: .LBB33_2:
; X86-SSE-NEXT: flds {{\.LCPI.*}} ; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st ; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1) ; X86-SSE-NEXT: fstp %st(1)
; X86-SSE-NEXT: movl $32767, %ecx # imm = 0x7FFF ; X86-SSE-NEXT: movl $32767, %ecx # imm = 0x7FFF
; X86-SSE-NEXT: cmovbel %eax, %ecx ; X86-SSE-NEXT: cmovbel %eax, %ecx
; X86-SSE-NEXT: xorl %eax, %eax ; X86-SSE-NEXT: xorl %eax, %eax
; X86-SSE-NEXT: fucompi %st(0), %st ; X86-SSE-NEXT: fucompi %st(0), %st
; X86-SSE-NEXT: cmovnpl %ecx, %eax ; X86-SSE-NEXT: cmovnpl %ecx, %eax
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; X86-X87-NEXT: fldt {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldt {{[0-9]+}}(%esp)
; X86-X87-NEXT: fnstcw (%esp) ; X86-X87-NEXT: fnstcw (%esp)
; X86-X87-NEXT: movzwl (%esp), %eax ; X86-X87-NEXT: movzwl (%esp), %eax
; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00
; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fistl {{[0-9]+}}(%esp) ; X86-X87-NEXT: fistl {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw (%esp) ; X86-X87-NEXT: fldcw (%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $-262144, %ecx # imm = 0xFFFC0000 ; X86-X87-NEXT: movl $-262144, %ecx # imm = 0xFFFC0000
; X86-X87-NEXT: jb .LBB34_2 ; X86-X87-NEXT: jb .LBB34_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB34_2: ; X86-X87-NEXT: .LBB34_2:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $262143, %edx # imm = 0x3FFFF ; X86-X87-NEXT: movl $262143, %edx # imm = 0x3FFFF
; X86-X87-NEXT: ja .LBB34_4 ; X86-X87-NEXT: ja .LBB34_4
Show All 19 Lines
; X86-SSE-NEXT: fldt {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldt {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fnstcw (%esp) ; X86-SSE-NEXT: fnstcw (%esp)
; X86-SSE-NEXT: movzwl (%esp), %eax ; X86-SSE-NEXT: movzwl (%esp), %eax
; X86-SSE-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-SSE-NEXT: orl $3072, %eax # imm = 0xC00
; X86-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fistl {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fistl {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw (%esp) ; X86-SSE-NEXT: fldcw (%esp)
; X86-SSE-NEXT: flds {{\.LCPI.*}} ; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st ; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1) ; X86-SSE-NEXT: fstp %st(1)
; X86-SSE-NEXT: movl $-262144, %eax # imm = 0xFFFC0000 ; X86-SSE-NEXT: movl $-262144, %eax # imm = 0xFFFC0000
; X86-SSE-NEXT: jb .LBB34_2 ; X86-SSE-NEXT: jb .LBB34_2
; X86-SSE-NEXT: # %bb.1: ; X86-SSE-NEXT: # %bb.1:
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: .LBB34_2: ; X86-SSE-NEXT: .LBB34_2:
; X86-SSE-NEXT: flds {{\.LCPI.*}} ; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st ; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1) ; X86-SSE-NEXT: fstp %st(1)
; X86-SSE-NEXT: movl $262143, %ecx # imm = 0x3FFFF ; X86-SSE-NEXT: movl $262143, %ecx # imm = 0x3FFFF
; X86-SSE-NEXT: cmovbel %eax, %ecx ; X86-SSE-NEXT: cmovbel %eax, %ecx
; X86-SSE-NEXT: xorl %eax, %eax ; X86-SSE-NEXT: xorl %eax, %eax
; X86-SSE-NEXT: fucompi %st(0), %st ; X86-SSE-NEXT: fucompi %st(0), %st
; X86-SSE-NEXT: cmovnpl %ecx, %eax ; X86-SSE-NEXT: cmovnpl %ecx, %eax
Show All 40 Lines
; X86-X87-NEXT: fldt {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldt {{[0-9]+}}(%esp)
; X86-X87-NEXT: fnstcw (%esp) ; X86-X87-NEXT: fnstcw (%esp)
; X86-X87-NEXT: movzwl (%esp), %eax ; X86-X87-NEXT: movzwl (%esp), %eax
; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00
; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fistl {{[0-9]+}}(%esp) ; X86-X87-NEXT: fistl {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw (%esp) ; X86-X87-NEXT: fldcw (%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $-2147483648, %ecx # imm = 0x80000000 ; X86-X87-NEXT: movl $-2147483648, %ecx # imm = 0x80000000
; X86-X87-NEXT: jb .LBB35_2 ; X86-X87-NEXT: jb .LBB35_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB35_2: ; X86-X87-NEXT: .LBB35_2:
; X86-X87-NEXT: fldl {{\.LCPI.*}} ; X86-X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $2147483647, %edx # imm = 0x7FFFFFFF ; X86-X87-NEXT: movl $2147483647, %edx # imm = 0x7FFFFFFF
; X86-X87-NEXT: ja .LBB35_4 ; X86-X87-NEXT: ja .LBB35_4
Show All 19 Lines
; X86-SSE-NEXT: fldt {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldt {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fnstcw (%esp) ; X86-SSE-NEXT: fnstcw (%esp)
; X86-SSE-NEXT: movzwl (%esp), %eax ; X86-SSE-NEXT: movzwl (%esp), %eax
; X86-SSE-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-SSE-NEXT: orl $3072, %eax # imm = 0xC00
; X86-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fistl {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fistl {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw (%esp) ; X86-SSE-NEXT: fldcw (%esp)
; X86-SSE-NEXT: flds {{\.LCPI.*}} ; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st ; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1) ; X86-SSE-NEXT: fstp %st(1)
; X86-SSE-NEXT: movl $-2147483648, %eax # imm = 0x80000000 ; X86-SSE-NEXT: movl $-2147483648, %eax # imm = 0x80000000
; X86-SSE-NEXT: jb .LBB35_2 ; X86-SSE-NEXT: jb .LBB35_2
; X86-SSE-NEXT: # %bb.1: ; X86-SSE-NEXT: # %bb.1:
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: .LBB35_2: ; X86-SSE-NEXT: .LBB35_2:
; X86-SSE-NEXT: fldl {{\.LCPI.*}} ; X86-SSE-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st ; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1) ; X86-SSE-NEXT: fstp %st(1)
; X86-SSE-NEXT: movl $2147483647, %ecx # imm = 0x7FFFFFFF ; X86-SSE-NEXT: movl $2147483647, %ecx # imm = 0x7FFFFFFF
; X86-SSE-NEXT: cmovbel %eax, %ecx ; X86-SSE-NEXT: cmovbel %eax, %ecx
; X86-SSE-NEXT: xorl %eax, %eax ; X86-SSE-NEXT: xorl %eax, %eax
; X86-SSE-NEXT: fucompi %st(0), %st ; X86-SSE-NEXT: fucompi %st(0), %st
; X86-SSE-NEXT: cmovnpl %ecx, %eax ; X86-SSE-NEXT: cmovnpl %ecx, %eax
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00
; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fld %st(0) ; X86-X87-NEXT: fld %st(0)
; X86-X87-NEXT: fistpll {{[0-9]+}}(%esp) ; X86-X87-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $0, %edx ; X86-X87-NEXT: movl $0, %edx
; X86-X87-NEXT: jb .LBB36_2 ; X86-X87-NEXT: jb .LBB36_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-X87-NEXT: .LBB36_2: ; X86-X87-NEXT: .LBB36_2:
; X86-X87-NEXT: movl $-131072, %edi # imm = 0xFFFE0000 ; X86-X87-NEXT: movl $-131072, %edi # imm = 0xFFFE0000
; X86-X87-NEXT: jb .LBB36_4 ; X86-X87-NEXT: jb .LBB36_4
; X86-X87-NEXT: # %bb.3: ; X86-X87-NEXT: # %bb.3:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-X87-NEXT: .LBB36_4: ; X86-X87-NEXT: .LBB36_4:
; X86-X87-NEXT: fldl {{\.LCPI.*}} ; X86-X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $131071, %esi # imm = 0x1FFFF ; X86-X87-NEXT: movl $131071, %esi # imm = 0x1FFFF
; X86-X87-NEXT: ja .LBB36_6 ; X86-X87-NEXT: ja .LBB36_6
Show All 30 Lines
; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-SSE-NEXT: orl $3072, %eax # imm = 0xC00
; X86-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fld %st(0) ; X86-SSE-NEXT: fld %st(0)
; X86-SSE-NEXT: fistpll {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: xorl %ecx, %ecx ; X86-SSE-NEXT: xorl %ecx, %ecx
; X86-SSE-NEXT: flds {{\.LCPI.*}} ; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st ; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1) ; X86-SSE-NEXT: fstp %st(1)
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-SSE-NEXT: cmovbl %ecx, %esi ; X86-SSE-NEXT: cmovbl %ecx, %esi
; X86-SSE-NEXT: movl $-131072, %eax # imm = 0xFFFE0000 ; X86-SSE-NEXT: movl $-131072, %eax # imm = 0xFFFE0000
; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: fldl {{\.LCPI.*}} ; X86-SSE-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st ; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1) ; X86-SSE-NEXT: fstp %st(1)
; X86-SSE-NEXT: movl $131071, %edx # imm = 0x1FFFF ; X86-SSE-NEXT: movl $131071, %edx # imm = 0x1FFFF
; X86-SSE-NEXT: cmovbel %eax, %edx ; X86-SSE-NEXT: cmovbel %eax, %edx
; X86-SSE-NEXT: movl $-1, %eax ; X86-SSE-NEXT: movl $-1, %eax
; X86-SSE-NEXT: cmovbel %esi, %eax ; X86-SSE-NEXT: cmovbel %esi, %eax
; X86-SSE-NEXT: fucompi %st(0), %st ; X86-SSE-NEXT: fucompi %st(0), %st
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fnstcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-X87-NEXT: orl $3072, %eax # imm = 0xC00
; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-X87-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: fld %st(0) ; X86-X87-NEXT: fld %st(0)
; X86-X87-NEXT: fistpll {{[0-9]+}}(%esp) ; X86-X87-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $0, %edx ; X86-X87-NEXT: movl $0, %edx
; X86-X87-NEXT: jb .LBB37_2 ; X86-X87-NEXT: jb .LBB37_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-X87-NEXT: .LBB37_2: ; X86-X87-NEXT: .LBB37_2:
; X86-X87-NEXT: movl $-2147483648, %edi # imm = 0x80000000 ; X86-X87-NEXT: movl $-2147483648, %edi # imm = 0x80000000
; X86-X87-NEXT: jb .LBB37_4 ; X86-X87-NEXT: jb .LBB37_4
; X86-X87-NEXT: # %bb.3: ; X86-X87-NEXT: # %bb.3:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-X87-NEXT: .LBB37_4: ; X86-X87-NEXT: .LBB37_4:
; X86-X87-NEXT: fldt {{\.LCPI.*}} ; X86-X87-NEXT: fldt {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $2147483647, %esi # imm = 0x7FFFFFFF ; X86-X87-NEXT: movl $2147483647, %esi # imm = 0x7FFFFFFF
; X86-X87-NEXT: ja .LBB37_6 ; X86-X87-NEXT: ja .LBB37_6
Show All 30 Lines
; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: orl $3072, %eax # imm = 0xC00 ; X86-SSE-NEXT: orl $3072, %eax # imm = 0xC00
; X86-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp) ; X86-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fld %st(0) ; X86-SSE-NEXT: fld %st(0)
; X86-SSE-NEXT: fistpll {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fistpll {{[0-9]+}}(%esp)
; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: xorl %ecx, %ecx ; X86-SSE-NEXT: xorl %ecx, %ecx
; X86-SSE-NEXT: flds {{\.LCPI.*}} ; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st ; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1) ; X86-SSE-NEXT: fstp %st(1)
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-SSE-NEXT: cmovbl %ecx, %esi ; X86-SSE-NEXT: cmovbl %ecx, %esi
; X86-SSE-NEXT: movl $-2147483648, %eax # imm = 0x80000000 ; X86-SSE-NEXT: movl $-2147483648, %eax # imm = 0x80000000
; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: fldt {{\.LCPI.*}} ; X86-SSE-NEXT: fldt {{\.LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st ; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1) ; X86-SSE-NEXT: fstp %st(1)
; X86-SSE-NEXT: movl $2147483647, %edx # imm = 0x7FFFFFFF ; X86-SSE-NEXT: movl $2147483647, %edx # imm = 0x7FFFFFFF
; X86-SSE-NEXT: cmovbel %eax, %edx ; X86-SSE-NEXT: cmovbel %eax, %edx
; X86-SSE-NEXT: movl $-1, %eax ; X86-SSE-NEXT: movl $-1, %eax
; X86-SSE-NEXT: cmovbel %esi, %eax ; X86-SSE-NEXT: cmovbel %esi, %eax
; X86-SSE-NEXT: fucompi %st(0), %st ; X86-SSE-NEXT: fucompi %st(0), %st
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; X86-X87-NEXT: pushl %edi ; X86-X87-NEXT: pushl %edi
; X86-X87-NEXT: pushl %esi ; X86-X87-NEXT: pushl %esi
; X86-X87-NEXT: subl $60, %esp ; X86-X87-NEXT: subl $60, %esp
; X86-X87-NEXT: fldt {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldt {{[0-9]+}}(%esp)
; X86-X87-NEXT: fld %st(0) ; X86-X87-NEXT: fld %st(0)
; X86-X87-NEXT: fstpt {{[0-9]+}}(%esp) ; X86-X87-NEXT: fstpt {{[0-9]+}}(%esp)
; X86-X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: movl %eax, (%esp) ; X86-X87-NEXT: movl %eax, (%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fld %st(1) ; X86-X87-NEXT: fld %st(1)
; X86-X87-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Spill ; X86-X87-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Spill
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: movl %eax, %ebx ; X86-X87-NEXT: movl %eax, %ebx
; X86-X87-NEXT: calll __fixxfti ; X86-X87-NEXT: calll __fixxfti
; X86-X87-NEXT: subl $4, %esp ; X86-X87-NEXT: subl $4, %esp
Show All 12 Lines
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ebp ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ebp
; X86-X87-NEXT: .LBB38_4: ; X86-X87-NEXT: .LBB38_4:
; X86-X87-NEXT: movl $0, %edi ; X86-X87-NEXT: movl $0, %edi
; X86-X87-NEXT: jb .LBB38_6 ; X86-X87-NEXT: jb .LBB38_6
; X86-X87-NEXT: # %bb.5: ; X86-X87-NEXT: # %bb.5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-X87-NEXT: .LBB38_6: ; X86-X87-NEXT: .LBB38_6:
; X86-X87-NEXT: fldt {{\.LCPI.*}} ; X86-X87-NEXT: fldt {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Reload ; X86-X87-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Reload
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $-1, %eax ; X86-X87-NEXT: movl $-1, %eax
; X86-X87-NEXT: movl $-1, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; X86-X87-NEXT: movl $-1, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
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; X86-SSE-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Spill ; X86-SSE-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Spill
; X86-SSE-NEXT: fstpt {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fstpt {{[0-9]+}}(%esp)
; X86-SSE-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl %eax, (%esp) ; X86-SSE-NEXT: movl %eax, (%esp)
; X86-SSE-NEXT: calll __fixxfti ; X86-SSE-NEXT: calll __fixxfti
; X86-SSE-NEXT: subl $4, %esp ; X86-SSE-NEXT: subl $4, %esp
; X86-SSE-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Reload ; X86-SSE-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Reload
; X86-SSE-NEXT: xorl %ebp, %ebp ; X86-SSE-NEXT: xorl %ebp, %ebp
; X86-SSE-NEXT: flds {{\.LCPI.*}} ; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st ; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1) ; X86-SSE-NEXT: fstp %st(1)
; X86-SSE-NEXT: movl $-8, %ebx ; X86-SSE-NEXT: movl $-8, %ebx
; X86-SSE-NEXT: movl $0, %ecx ; X86-SSE-NEXT: movl $0, %ecx
; X86-SSE-NEXT: movl $0, %edx ; X86-SSE-NEXT: movl $0, %edx
; X86-SSE-NEXT: movl $0, %edi ; X86-SSE-NEXT: movl $0, %edi
; X86-SSE-NEXT: jb .LBB38_2 ; X86-SSE-NEXT: jb .LBB38_2
; X86-SSE-NEXT: # %bb.1: ; X86-SSE-NEXT: # %bb.1:
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ebx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-SSE-NEXT: .LBB38_2: ; X86-SSE-NEXT: .LBB38_2:
; X86-SSE-NEXT: fldt {{\.LCPI.*}} ; X86-SSE-NEXT: fldt {{\.LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st ; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1) ; X86-SSE-NEXT: fstp %st(1)
; X86-SSE-NEXT: movl $-1, %eax ; X86-SSE-NEXT: movl $-1, %eax
; X86-SSE-NEXT: cmoval %eax, %edi ; X86-SSE-NEXT: cmoval %eax, %edi
; X86-SSE-NEXT: cmoval %eax, %edx ; X86-SSE-NEXT: cmoval %eax, %edx
; X86-SSE-NEXT: cmoval %eax, %ecx ; X86-SSE-NEXT: cmoval %eax, %ecx
; X86-SSE-NEXT: movl $7, %eax ; X86-SSE-NEXT: movl $7, %eax
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; X86-X87-NEXT: pushl %edi ; X86-X87-NEXT: pushl %edi
; X86-X87-NEXT: pushl %esi ; X86-X87-NEXT: pushl %esi
; X86-X87-NEXT: subl $60, %esp ; X86-X87-NEXT: subl $60, %esp
; X86-X87-NEXT: fldt {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldt {{[0-9]+}}(%esp)
; X86-X87-NEXT: fld %st(0) ; X86-X87-NEXT: fld %st(0)
; X86-X87-NEXT: fstpt {{[0-9]+}}(%esp) ; X86-X87-NEXT: fstpt {{[0-9]+}}(%esp)
; X86-X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: movl %eax, (%esp) ; X86-X87-NEXT: movl %eax, (%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fld %st(1) ; X86-X87-NEXT: fld %st(1)
; X86-X87-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Spill ; X86-X87-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Spill
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: movl %eax, %ebx ; X86-X87-NEXT: movl %eax, %ebx
; X86-X87-NEXT: calll __fixxfti ; X86-X87-NEXT: calll __fixxfti
; X86-X87-NEXT: subl $4, %esp ; X86-X87-NEXT: subl $4, %esp
; X86-X87-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; X86-X87-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill
; X86-X87-NEXT: movb %bh, %ah ; X86-X87-NEXT: movb %bh, %ah
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $0, %eax ; X86-X87-NEXT: movl $0, %eax
; X86-X87-NEXT: movl $0, %ebx ; X86-X87-NEXT: movl $0, %ebx
; X86-X87-NEXT: jae .LBB39_1 ; X86-X87-NEXT: jae .LBB39_1
; X86-X87-NEXT: # %bb.2: ; X86-X87-NEXT: # %bb.2:
; X86-X87-NEXT: movl $0, %edx ; X86-X87-NEXT: movl $0, %edx
; X86-X87-NEXT: jae .LBB39_3 ; X86-X87-NEXT: jae .LBB39_3
; X86-X87-NEXT: .LBB39_4: ; X86-X87-NEXT: .LBB39_4:
; X86-X87-NEXT: movl $-2147483648, %ecx # imm = 0x80000000 ; X86-X87-NEXT: movl $-2147483648, %ecx # imm = 0x80000000
; X86-X87-NEXT: jb .LBB39_6 ; X86-X87-NEXT: jb .LBB39_6
; X86-X87-NEXT: .LBB39_5: ; X86-X87-NEXT: .LBB39_5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB39_6: ; X86-X87-NEXT: .LBB39_6:
; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-X87-NEXT: fldt {{\.LCPI.*}} ; X86-X87-NEXT: fldt {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Reload ; X86-X87-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Reload
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fstp %st(1) ; X86-X87-NEXT: fstp %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF ; X86-X87-NEXT: movl $2147483647, %eax # imm = 0x7FFFFFFF
; X86-X87-NEXT: ja .LBB39_8 ; X86-X87-NEXT: ja .LBB39_8
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; X86-SSE-NEXT: fld %st(0) ; X86-SSE-NEXT: fld %st(0)
; X86-SSE-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Spill ; X86-SSE-NEXT: fstpt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Spill
; X86-SSE-NEXT: fstpt {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fstpt {{[0-9]+}}(%esp)
; X86-SSE-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl %eax, (%esp) ; X86-SSE-NEXT: movl %eax, (%esp)
; X86-SSE-NEXT: calll __fixxfti ; X86-SSE-NEXT: calll __fixxfti
; X86-SSE-NEXT: subl $4, %esp ; X86-SSE-NEXT: subl $4, %esp
; X86-SSE-NEXT: xorl %ecx, %ecx ; X86-SSE-NEXT: xorl %ecx, %ecx
; X86-SSE-NEXT: flds {{\.LCPI.*}} ; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Reload ; X86-SSE-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Reload
; X86-SSE-NEXT: fucomi %st(1), %st ; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1) ; X86-SSE-NEXT: fstp %st(1)
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: cmovbl %ecx, %eax ; X86-SSE-NEXT: cmovbl %ecx, %eax
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: cmovbl %ecx, %edx ; X86-SSE-NEXT: cmovbl %ecx, %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-SSE-NEXT: cmovbl %ecx, %edi ; X86-SSE-NEXT: cmovbl %ecx, %edi
; X86-SSE-NEXT: movl $-2147483648, %ebx # imm = 0x80000000 ; X86-SSE-NEXT: movl $-2147483648, %ebx # imm = 0x80000000
; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %ebx ; X86-SSE-NEXT: cmovael {{[0-9]+}}(%esp), %ebx
; X86-SSE-NEXT: fldt {{\.LCPI.*}} ; X86-SSE-NEXT: fldt {{\.LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st ; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1) ; X86-SSE-NEXT: fstp %st(1)
; X86-SSE-NEXT: movl $2147483647, %ebp # imm = 0x7FFFFFFF ; X86-SSE-NEXT: movl $2147483647, %ebp # imm = 0x7FFFFFFF
; X86-SSE-NEXT: cmovbel %ebx, %ebp ; X86-SSE-NEXT: cmovbel %ebx, %ebp
; X86-SSE-NEXT: movl $-1, %ebx ; X86-SSE-NEXT: movl $-1, %ebx
; X86-SSE-NEXT: cmoval %ebx, %edi ; X86-SSE-NEXT: cmoval %ebx, %edi
; X86-SSE-NEXT: cmoval %ebx, %edx ; X86-SSE-NEXT: cmoval %ebx, %edx
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llvm/test/CodeGen/X86/fptoui-sat-scalar.ll

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; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: jb .LBB1_1 ; X86-X87-NEXT: jb .LBB1_1
; X86-X87-NEXT: # %bb.2: ; X86-X87-NEXT: # %bb.2:
; X86-X87-NEXT: movb {{[0-9]+}}(%esp), %cl ; X86-X87-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-X87-NEXT: jmp .LBB1_3 ; X86-X87-NEXT: jmp .LBB1_3
; X86-X87-NEXT: .LBB1_1: ; X86-X87-NEXT: .LBB1_1:
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: .LBB1_3: ; X86-X87-NEXT: .LBB1_3:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movb $-1, %al ; X86-X87-NEXT: movb $-1, %al
; X86-X87-NEXT: ja .LBB1_5 ; X86-X87-NEXT: ja .LBB1_5
; X86-X87-NEXT: # %bb.4: ; X86-X87-NEXT: # %bb.4:
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; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: jb .LBB2_2 ; X86-X87-NEXT: jb .LBB2_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB2_2: ; X86-X87-NEXT: .LBB2_2:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $8191, %eax # imm = 0x1FFF ; X86-X87-NEXT: movl $8191, %eax # imm = 0x1FFF
; X86-X87-NEXT: ja .LBB2_4 ; X86-X87-NEXT: ja .LBB2_4
; X86-X87-NEXT: # %bb.3: ; X86-X87-NEXT: # %bb.3:
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; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: jb .LBB3_2 ; X86-X87-NEXT: jb .LBB3_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB3_2: ; X86-X87-NEXT: .LBB3_2:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $65535, %eax # imm = 0xFFFF ; X86-X87-NEXT: movl $65535, %eax # imm = 0xFFFF
; X86-X87-NEXT: ja .LBB3_4 ; X86-X87-NEXT: ja .LBB3_4
; X86-X87-NEXT: # %bb.3: ; X86-X87-NEXT: # %bb.3:
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; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: jb .LBB4_2 ; X86-X87-NEXT: jb .LBB4_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB4_2: ; X86-X87-NEXT: .LBB4_2:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $524287, %eax # imm = 0x7FFFF ; X86-X87-NEXT: movl $524287, %eax # imm = 0x7FFFF
; X86-X87-NEXT: ja .LBB4_4 ; X86-X87-NEXT: ja .LBB4_4
; X86-X87-NEXT: # %bb.3: ; X86-X87-NEXT: # %bb.3:
; X86-X87-NEXT: movl %ecx, %eax ; X86-X87-NEXT: movl %ecx, %eax
; X86-X87-NEXT: .LBB4_4: ; X86-X87-NEXT: .LBB4_4:
; X86-X87-NEXT: addl $20, %esp ; X86-X87-NEXT: addl $20, %esp
; X86-X87-NEXT: retl ; X86-X87-NEXT: retl
; ;
; X86-SSE-LABEL: test_unsigned_i19_f32: ; X86-SSE-LABEL: test_unsigned_i19_f32:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: xorps %xmm1, %xmm1 ; X86-SSE-NEXT: xorps %xmm1, %xmm1
; X86-SSE-NEXT: maxss %xmm1, %xmm0 ; X86-SSE-NEXT: maxss %xmm1, %xmm0
; X86-SSE-NEXT: minss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: minss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: cvttss2si %xmm0, %eax ; X86-SSE-NEXT: cvttss2si %xmm0, %eax
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-LABEL: test_unsigned_i19_f32: ; X64-LABEL: test_unsigned_i19_f32:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: xorps %xmm1, %xmm1 ; X64-NEXT: xorps %xmm1, %xmm1
; X64-NEXT: maxss %xmm1, %xmm0 ; X64-NEXT: maxss %xmm1, %xmm0
; X64-NEXT: minss {{.*}}(%rip), %xmm0 ; X64-NEXT: minss {{.*}}(%rip), %xmm0
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; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: jb .LBB5_2 ; X86-X87-NEXT: jb .LBB5_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB5_2: ; X86-X87-NEXT: .LBB5_2:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $-1, %eax ; X86-X87-NEXT: movl $-1, %eax
; X86-X87-NEXT: ja .LBB5_4 ; X86-X87-NEXT: ja .LBB5_4
; X86-X87-NEXT: # %bb.3: ; X86-X87-NEXT: # %bb.3:
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; X86-SSE-NEXT: xorl $-2147483648, %eax # imm = 0x80000000 ; X86-SSE-NEXT: xorl $-2147483648, %eax # imm = 0x80000000
; X86-SSE-NEXT: cvttss2si %xmm0, %ecx ; X86-SSE-NEXT: cvttss2si %xmm0, %ecx
; X86-SSE-NEXT: ucomiss %xmm0, %xmm1 ; X86-SSE-NEXT: ucomiss %xmm0, %xmm1
; X86-SSE-NEXT: cmovbel %eax, %ecx ; X86-SSE-NEXT: cmovbel %eax, %ecx
; X86-SSE-NEXT: xorl %edx, %edx ; X86-SSE-NEXT: xorl %edx, %edx
; X86-SSE-NEXT: xorps %xmm1, %xmm1 ; X86-SSE-NEXT: xorps %xmm1, %xmm1
; X86-SSE-NEXT: ucomiss %xmm1, %xmm0 ; X86-SSE-NEXT: ucomiss %xmm1, %xmm0
; X86-SSE-NEXT: cmovael %ecx, %edx ; X86-SSE-NEXT: cmovael %ecx, %edx
; X86-SSE-NEXT: ucomiss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $-1, %eax ; X86-SSE-NEXT: movl $-1, %eax
; X86-SSE-NEXT: cmovbel %edx, %eax ; X86-SSE-NEXT: cmovbel %edx, %eax
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-LABEL: test_unsigned_i32_f32: ; X64-LABEL: test_unsigned_i32_f32:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: cvttss2si %xmm0, %rax ; X64-NEXT: cvttss2si %xmm0, %rax
; X64-NEXT: xorl %ecx, %ecx ; X64-NEXT: xorl %ecx, %ecx
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} }
define i50 @test_unsigned_i50_f32(float %f) nounwind { define i50 @test_unsigned_i50_f32(float %f) nounwind {
; X86-X87-LABEL: test_unsigned_i50_f32: ; X86-X87-LABEL: test_unsigned_i50_f32:
; X86-X87: # %bb.0: ; X86-X87: # %bb.0:
; X86-X87-NEXT: pushl %esi ; X86-X87-NEXT: pushl %esi
; X86-X87-NEXT: subl $16, %esp ; X86-X87-NEXT: subl $16, %esp
; X86-X87-NEXT: flds {{[0-9]+}}(%esp) ; X86-X87-NEXT: flds {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: setbe %al ; X86-X87-NEXT: setbe %al
; X86-X87-NEXT: fldz ; X86-X87-NEXT: fldz
; X86-X87-NEXT: jbe .LBB6_2 ; X86-X87-NEXT: jbe .LBB6_2
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; X86-X87-NEXT: jb .LBB6_4 ; X86-X87-NEXT: jb .LBB6_4
; X86-X87-NEXT: # %bb.3: ; X86-X87-NEXT: # %bb.3:
; X86-X87-NEXT: movl %ecx, %esi ; X86-X87-NEXT: movl %ecx, %esi
; X86-X87-NEXT: .LBB6_4: ; X86-X87-NEXT: .LBB6_4:
; X86-X87-NEXT: jb .LBB6_6 ; X86-X87-NEXT: jb .LBB6_6
; X86-X87-NEXT: # %bb.5: ; X86-X87-NEXT: # %bb.5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-X87-NEXT: .LBB6_6: ; X86-X87-NEXT: .LBB6_6:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $-1, %eax ; X86-X87-NEXT: movl $-1, %eax
; X86-X87-NEXT: ja .LBB6_8 ; X86-X87-NEXT: ja .LBB6_8
; X86-X87-NEXT: # %bb.7: ; X86-X87-NEXT: # %bb.7:
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; X86-SSE-NEXT: movl $0, %esi ; X86-SSE-NEXT: movl $0, %esi
; X86-SSE-NEXT: jb .LBB6_4 ; X86-SSE-NEXT: jb .LBB6_4
; X86-SSE-NEXT: # %bb.3: ; X86-SSE-NEXT: # %bb.3:
; X86-SSE-NEXT: movzbl %cl, %eax ; X86-SSE-NEXT: movzbl %cl, %eax
; X86-SSE-NEXT: shll $31, %eax ; X86-SSE-NEXT: shll $31, %eax
; X86-SSE-NEXT: xorl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: xorl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-SSE-NEXT: .LBB6_4: ; X86-SSE-NEXT: .LBB6_4:
; X86-SSE-NEXT: ucomiss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $262143, %edx # imm = 0x3FFFF ; X86-SSE-NEXT: movl $262143, %edx # imm = 0x3FFFF
; X86-SSE-NEXT: cmovbel %eax, %edx ; X86-SSE-NEXT: cmovbel %eax, %edx
; X86-SSE-NEXT: movl $-1, %eax ; X86-SSE-NEXT: movl $-1, %eax
; X86-SSE-NEXT: cmovbel %esi, %eax ; X86-SSE-NEXT: cmovbel %esi, %eax
; X86-SSE-NEXT: addl $16, %esp ; X86-SSE-NEXT: addl $16, %esp
; X86-SSE-NEXT: popl %esi ; X86-SSE-NEXT: popl %esi
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
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define i64 @test_unsigned_i64_f32(float %f) nounwind { define i64 @test_unsigned_i64_f32(float %f) nounwind {
; X86-X87-LABEL: test_unsigned_i64_f32: ; X86-X87-LABEL: test_unsigned_i64_f32:
; X86-X87: # %bb.0: ; X86-X87: # %bb.0:
; X86-X87-NEXT: pushl %edi ; X86-X87-NEXT: pushl %edi
; X86-X87-NEXT: pushl %esi ; X86-X87-NEXT: pushl %esi
; X86-X87-NEXT: subl $20, %esp ; X86-X87-NEXT: subl $20, %esp
; X86-X87-NEXT: flds {{[0-9]+}}(%esp) ; X86-X87-NEXT: flds {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: setbe %al ; X86-X87-NEXT: setbe %al
; X86-X87-NEXT: fldz ; X86-X87-NEXT: fldz
; X86-X87-NEXT: jbe .LBB7_2 ; X86-X87-NEXT: jbe .LBB7_2
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; X86-X87-NEXT: jb .LBB7_4 ; X86-X87-NEXT: jb .LBB7_4
; X86-X87-NEXT: # %bb.3: ; X86-X87-NEXT: # %bb.3:
; X86-X87-NEXT: movl %ecx, %edi ; X86-X87-NEXT: movl %ecx, %edi
; X86-X87-NEXT: .LBB7_4: ; X86-X87-NEXT: .LBB7_4:
; X86-X87-NEXT: jb .LBB7_6 ; X86-X87-NEXT: jb .LBB7_6
; X86-X87-NEXT: # %bb.5: ; X86-X87-NEXT: # %bb.5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-X87-NEXT: .LBB7_6: ; X86-X87-NEXT: .LBB7_6:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $-1, %eax ; X86-X87-NEXT: movl $-1, %eax
; X86-X87-NEXT: movl $-1, %edx ; X86-X87-NEXT: movl $-1, %edx
; X86-X87-NEXT: ja .LBB7_8 ; X86-X87-NEXT: ja .LBB7_8
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; X86-SSE-NEXT: movl $0, %eax ; X86-SSE-NEXT: movl $0, %eax
; X86-SSE-NEXT: jb .LBB7_4 ; X86-SSE-NEXT: jb .LBB7_4
; X86-SSE-NEXT: # %bb.3: ; X86-SSE-NEXT: # %bb.3:
; X86-SSE-NEXT: movzbl %cl, %edx ; X86-SSE-NEXT: movzbl %cl, %edx
; X86-SSE-NEXT: shll $31, %edx ; X86-SSE-NEXT: shll $31, %edx
; X86-SSE-NEXT: xorl {{[0-9]+}}(%esp), %edx ; X86-SSE-NEXT: xorl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: .LBB7_4: ; X86-SSE-NEXT: .LBB7_4:
; X86-SSE-NEXT: ucomiss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $-1, %ecx ; X86-SSE-NEXT: movl $-1, %ecx
; X86-SSE-NEXT: cmoval %ecx, %edx ; X86-SSE-NEXT: cmoval %ecx, %edx
; X86-SSE-NEXT: cmoval %ecx, %eax ; X86-SSE-NEXT: cmoval %ecx, %eax
; X86-SSE-NEXT: addl $20, %esp ; X86-SSE-NEXT: addl $20, %esp
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-LABEL: test_unsigned_i64_f32: ; X64-LABEL: test_unsigned_i64_f32:
; X64: # %bb.0: ; X64: # %bb.0:
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; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-X87-NEXT: .LBB8_4: ; X86-X87-NEXT: .LBB8_4:
; X86-X87-NEXT: jb .LBB8_6 ; X86-X87-NEXT: jb .LBB8_6
; X86-X87-NEXT: # %bb.5: ; X86-X87-NEXT: # %bb.5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-X87-NEXT: .LBB8_6: ; X86-X87-NEXT: .LBB8_6:
; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload ; X86-X87-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $15, %eax ; X86-X87-NEXT: movl $15, %eax
; X86-X87-NEXT: ja .LBB8_8 ; X86-X87-NEXT: ja .LBB8_8
; X86-X87-NEXT: # %bb.7: ; X86-X87-NEXT: # %bb.7:
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; X86-SSE-NEXT: movl $0, %edi ; X86-SSE-NEXT: movl $0, %edi
; X86-SSE-NEXT: jb .LBB8_2 ; X86-SSE-NEXT: jb .LBB8_2
; X86-SSE-NEXT: # %bb.1: ; X86-SSE-NEXT: # %bb.1:
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-SSE-NEXT: .LBB8_2: ; X86-SSE-NEXT: .LBB8_2:
; X86-SSE-NEXT: ucomiss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $15, %ebx ; X86-SSE-NEXT: movl $15, %ebx
; X86-SSE-NEXT: cmovbel %edi, %ebx ; X86-SSE-NEXT: cmovbel %edi, %ebx
; X86-SSE-NEXT: movl $-1, %edi ; X86-SSE-NEXT: movl $-1, %edi
; X86-SSE-NEXT: cmoval %edi, %edx ; X86-SSE-NEXT: cmoval %edi, %edx
; X86-SSE-NEXT: cmoval %edi, %ecx ; X86-SSE-NEXT: cmoval %edi, %ecx
; X86-SSE-NEXT: cmoval %edi, %eax ; X86-SSE-NEXT: cmoval %edi, %eax
; X86-SSE-NEXT: movl %eax, 8(%esi) ; X86-SSE-NEXT: movl %eax, 8(%esi)
; X86-SSE-NEXT: movl %ecx, 4(%esi) ; X86-SSE-NEXT: movl %ecx, 4(%esi)
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; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: movl $0, %ebx ; X86-X87-NEXT: movl $0, %ebx
; X86-X87-NEXT: jb .LBB9_6 ; X86-X87-NEXT: jb .LBB9_6
; X86-X87-NEXT: # %bb.5: ; X86-X87-NEXT: # %bb.5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ebx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-X87-NEXT: .LBB9_6: ; X86-X87-NEXT: .LBB9_6:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload ; X86-X87-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $-1, %eax ; X86-X87-NEXT: movl $-1, %eax
; X86-X87-NEXT: movl $-1, %ebp ; X86-X87-NEXT: movl $-1, %ebp
; X86-X87-NEXT: movl $-1, %edi ; X86-X87-NEXT: movl $-1, %edi
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; X86-SSE-NEXT: movl $0, %edi ; X86-SSE-NEXT: movl $0, %edi
; X86-SSE-NEXT: jb .LBB9_2 ; X86-SSE-NEXT: jb .LBB9_2
; X86-SSE-NEXT: # %bb.1: ; X86-SSE-NEXT: # %bb.1:
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-SSE-NEXT: .LBB9_2: ; X86-SSE-NEXT: .LBB9_2:
; X86-SSE-NEXT: ucomiss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $-1, %ebx ; X86-SSE-NEXT: movl $-1, %ebx
; X86-SSE-NEXT: cmoval %ebx, %edi ; X86-SSE-NEXT: cmoval %ebx, %edi
; X86-SSE-NEXT: cmoval %ebx, %edx ; X86-SSE-NEXT: cmoval %ebx, %edx
; X86-SSE-NEXT: cmoval %ebx, %ecx ; X86-SSE-NEXT: cmoval %ebx, %ecx
; X86-SSE-NEXT: cmoval %ebx, %eax ; X86-SSE-NEXT: cmoval %ebx, %eax
; X86-SSE-NEXT: movl %eax, 12(%esi) ; X86-SSE-NEXT: movl %eax, 12(%esi)
; X86-SSE-NEXT: movl %ecx, 8(%esi) ; X86-SSE-NEXT: movl %ecx, 8(%esi)
; X86-SSE-NEXT: movl %edx, 4(%esi) ; X86-SSE-NEXT: movl %edx, 4(%esi)
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; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: jb .LBB11_1 ; X86-X87-NEXT: jb .LBB11_1
; X86-X87-NEXT: # %bb.2: ; X86-X87-NEXT: # %bb.2:
; X86-X87-NEXT: movb {{[0-9]+}}(%esp), %cl ; X86-X87-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-X87-NEXT: jmp .LBB11_3 ; X86-X87-NEXT: jmp .LBB11_3
; X86-X87-NEXT: .LBB11_1: ; X86-X87-NEXT: .LBB11_1:
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: .LBB11_3: ; X86-X87-NEXT: .LBB11_3:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movb $-1, %al ; X86-X87-NEXT: movb $-1, %al
; X86-X87-NEXT: ja .LBB11_5 ; X86-X87-NEXT: ja .LBB11_5
; X86-X87-NEXT: # %bb.4: ; X86-X87-NEXT: # %bb.4:
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; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: jb .LBB12_2 ; X86-X87-NEXT: jb .LBB12_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB12_2: ; X86-X87-NEXT: .LBB12_2:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $8191, %eax # imm = 0x1FFF ; X86-X87-NEXT: movl $8191, %eax # imm = 0x1FFF
; X86-X87-NEXT: ja .LBB12_4 ; X86-X87-NEXT: ja .LBB12_4
; X86-X87-NEXT: # %bb.3: ; X86-X87-NEXT: # %bb.3:
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; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: jb .LBB13_2 ; X86-X87-NEXT: jb .LBB13_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB13_2: ; X86-X87-NEXT: .LBB13_2:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $65535, %eax # imm = 0xFFFF ; X86-X87-NEXT: movl $65535, %eax # imm = 0xFFFF
; X86-X87-NEXT: ja .LBB13_4 ; X86-X87-NEXT: ja .LBB13_4
; X86-X87-NEXT: # %bb.3: ; X86-X87-NEXT: # %bb.3:
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; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: jb .LBB14_2 ; X86-X87-NEXT: jb .LBB14_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB14_2: ; X86-X87-NEXT: .LBB14_2:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $524287, %eax # imm = 0x7FFFF ; X86-X87-NEXT: movl $524287, %eax # imm = 0x7FFFF
; X86-X87-NEXT: ja .LBB14_4 ; X86-X87-NEXT: ja .LBB14_4
; X86-X87-NEXT: # %bb.3: ; X86-X87-NEXT: # %bb.3:
; X86-X87-NEXT: movl %ecx, %eax ; X86-X87-NEXT: movl %ecx, %eax
; X86-X87-NEXT: .LBB14_4: ; X86-X87-NEXT: .LBB14_4:
; X86-X87-NEXT: addl $20, %esp ; X86-X87-NEXT: addl $20, %esp
; X86-X87-NEXT: retl ; X86-X87-NEXT: retl
; ;
; X86-SSE-LABEL: test_unsigned_i19_f64: ; X86-SSE-LABEL: test_unsigned_i19_f64:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE-NEXT: xorpd %xmm1, %xmm1 ; X86-SSE-NEXT: xorpd %xmm1, %xmm1
; X86-SSE-NEXT: maxsd %xmm1, %xmm0 ; X86-SSE-NEXT: maxsd %xmm1, %xmm0
; X86-SSE-NEXT: minsd {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: minsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: cvttsd2si %xmm0, %eax ; X86-SSE-NEXT: cvttsd2si %xmm0, %eax
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-LABEL: test_unsigned_i19_f64: ; X64-LABEL: test_unsigned_i19_f64:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: xorpd %xmm1, %xmm1 ; X64-NEXT: xorpd %xmm1, %xmm1
; X64-NEXT: maxsd %xmm1, %xmm0 ; X64-NEXT: maxsd %xmm1, %xmm0
; X64-NEXT: minsd {{.*}}(%rip), %xmm0 ; X64-NEXT: minsd {{.*}}(%rip), %xmm0
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; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: jb .LBB15_2 ; X86-X87-NEXT: jb .LBB15_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB15_2: ; X86-X87-NEXT: .LBB15_2:
; X86-X87-NEXT: fldl {{\.LCPI.*}} ; X86-X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $-1, %eax ; X86-X87-NEXT: movl $-1, %eax
; X86-X87-NEXT: ja .LBB15_4 ; X86-X87-NEXT: ja .LBB15_4
; X86-X87-NEXT: # %bb.3: ; X86-X87-NEXT: # %bb.3:
; X86-X87-NEXT: movl %ecx, %eax ; X86-X87-NEXT: movl %ecx, %eax
; X86-X87-NEXT: .LBB15_4: ; X86-X87-NEXT: .LBB15_4:
; X86-X87-NEXT: addl $20, %esp ; X86-X87-NEXT: addl $20, %esp
; X86-X87-NEXT: retl ; X86-X87-NEXT: retl
; ;
; X86-SSE-LABEL: test_unsigned_i32_f64: ; X86-SSE-LABEL: test_unsigned_i32_f64:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE-NEXT: xorpd %xmm1, %xmm1 ; X86-SSE-NEXT: xorpd %xmm1, %xmm1
; X86-SSE-NEXT: maxsd %xmm1, %xmm0 ; X86-SSE-NEXT: maxsd %xmm1, %xmm0
; X86-SSE-NEXT: minsd {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: minsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: cvttsd2si %xmm0, %ecx ; X86-SSE-NEXT: cvttsd2si %xmm0, %ecx
; X86-SSE-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero ; X86-SSE-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; X86-SSE-NEXT: movapd %xmm0, %xmm2 ; X86-SSE-NEXT: movapd %xmm0, %xmm2
; X86-SSE-NEXT: subsd %xmm1, %xmm2 ; X86-SSE-NEXT: subsd %xmm1, %xmm2
; X86-SSE-NEXT: cvttsd2si %xmm2, %eax ; X86-SSE-NEXT: cvttsd2si %xmm2, %eax
; X86-SSE-NEXT: xorl $-2147483648, %eax # imm = 0x80000000 ; X86-SSE-NEXT: xorl $-2147483648, %eax # imm = 0x80000000
; X86-SSE-NEXT: ucomisd %xmm1, %xmm0 ; X86-SSE-NEXT: ucomisd %xmm1, %xmm0
; X86-SSE-NEXT: cmovbl %ecx, %eax ; X86-SSE-NEXT: cmovbl %ecx, %eax
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} }
define i50 @test_unsigned_i50_f64(double %f) nounwind { define i50 @test_unsigned_i50_f64(double %f) nounwind {
; X86-X87-LABEL: test_unsigned_i50_f64: ; X86-X87-LABEL: test_unsigned_i50_f64:
; X86-X87: # %bb.0: ; X86-X87: # %bb.0:
; X86-X87-NEXT: pushl %esi ; X86-X87-NEXT: pushl %esi
; X86-X87-NEXT: subl $16, %esp ; X86-X87-NEXT: subl $16, %esp
; X86-X87-NEXT: fldl {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldl {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: setbe %al ; X86-X87-NEXT: setbe %al
; X86-X87-NEXT: fldz ; X86-X87-NEXT: fldz
; X86-X87-NEXT: jbe .LBB16_2 ; X86-X87-NEXT: jbe .LBB16_2
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; X86-X87-NEXT: jb .LBB16_4 ; X86-X87-NEXT: jb .LBB16_4
; X86-X87-NEXT: # %bb.3: ; X86-X87-NEXT: # %bb.3:
; X86-X87-NEXT: movl %ecx, %esi ; X86-X87-NEXT: movl %ecx, %esi
; X86-X87-NEXT: .LBB16_4: ; X86-X87-NEXT: .LBB16_4:
; X86-X87-NEXT: jb .LBB16_6 ; X86-X87-NEXT: jb .LBB16_6
; X86-X87-NEXT: # %bb.5: ; X86-X87-NEXT: # %bb.5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-X87-NEXT: .LBB16_6: ; X86-X87-NEXT: .LBB16_6:
; X86-X87-NEXT: fldl {{\.LCPI.*}} ; X86-X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $-1, %eax ; X86-X87-NEXT: movl $-1, %eax
; X86-X87-NEXT: ja .LBB16_8 ; X86-X87-NEXT: ja .LBB16_8
; X86-X87-NEXT: # %bb.7: ; X86-X87-NEXT: # %bb.7:
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; X86-SSE-NEXT: movl $0, %esi ; X86-SSE-NEXT: movl $0, %esi
; X86-SSE-NEXT: jb .LBB16_4 ; X86-SSE-NEXT: jb .LBB16_4
; X86-SSE-NEXT: # %bb.3: ; X86-SSE-NEXT: # %bb.3:
; X86-SSE-NEXT: movzbl %cl, %eax ; X86-SSE-NEXT: movzbl %cl, %eax
; X86-SSE-NEXT: shll $31, %eax ; X86-SSE-NEXT: shll $31, %eax
; X86-SSE-NEXT: xorl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: xorl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-SSE-NEXT: .LBB16_4: ; X86-SSE-NEXT: .LBB16_4:
; X86-SSE-NEXT: ucomisd {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomisd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $262143, %edx # imm = 0x3FFFF ; X86-SSE-NEXT: movl $262143, %edx # imm = 0x3FFFF
; X86-SSE-NEXT: cmovbel %eax, %edx ; X86-SSE-NEXT: cmovbel %eax, %edx
; X86-SSE-NEXT: movl $-1, %eax ; X86-SSE-NEXT: movl $-1, %eax
; X86-SSE-NEXT: cmovbel %esi, %eax ; X86-SSE-NEXT: cmovbel %esi, %eax
; X86-SSE-NEXT: addl $16, %esp ; X86-SSE-NEXT: addl $16, %esp
; X86-SSE-NEXT: popl %esi ; X86-SSE-NEXT: popl %esi
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
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define i64 @test_unsigned_i64_f64(double %f) nounwind { define i64 @test_unsigned_i64_f64(double %f) nounwind {
; X86-X87-LABEL: test_unsigned_i64_f64: ; X86-X87-LABEL: test_unsigned_i64_f64:
; X86-X87: # %bb.0: ; X86-X87: # %bb.0:
; X86-X87-NEXT: pushl %edi ; X86-X87-NEXT: pushl %edi
; X86-X87-NEXT: pushl %esi ; X86-X87-NEXT: pushl %esi
; X86-X87-NEXT: subl $20, %esp ; X86-X87-NEXT: subl $20, %esp
; X86-X87-NEXT: fldl {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldl {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: setbe %al ; X86-X87-NEXT: setbe %al
; X86-X87-NEXT: fldz ; X86-X87-NEXT: fldz
; X86-X87-NEXT: jbe .LBB17_2 ; X86-X87-NEXT: jbe .LBB17_2
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; X86-X87-NEXT: jb .LBB17_4 ; X86-X87-NEXT: jb .LBB17_4
; X86-X87-NEXT: # %bb.3: ; X86-X87-NEXT: # %bb.3:
; X86-X87-NEXT: movl %ecx, %edi ; X86-X87-NEXT: movl %ecx, %edi
; X86-X87-NEXT: .LBB17_4: ; X86-X87-NEXT: .LBB17_4:
; X86-X87-NEXT: jb .LBB17_6 ; X86-X87-NEXT: jb .LBB17_6
; X86-X87-NEXT: # %bb.5: ; X86-X87-NEXT: # %bb.5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-X87-NEXT: .LBB17_6: ; X86-X87-NEXT: .LBB17_6:
; X86-X87-NEXT: fldl {{\.LCPI.*}} ; X86-X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $-1, %eax ; X86-X87-NEXT: movl $-1, %eax
; X86-X87-NEXT: movl $-1, %edx ; X86-X87-NEXT: movl $-1, %edx
; X86-X87-NEXT: ja .LBB17_8 ; X86-X87-NEXT: ja .LBB17_8
Show All 34 Lines
; X86-SSE-NEXT: movl $0, %eax ; X86-SSE-NEXT: movl $0, %eax
; X86-SSE-NEXT: jb .LBB17_4 ; X86-SSE-NEXT: jb .LBB17_4
; X86-SSE-NEXT: # %bb.3: ; X86-SSE-NEXT: # %bb.3:
; X86-SSE-NEXT: movzbl %cl, %edx ; X86-SSE-NEXT: movzbl %cl, %edx
; X86-SSE-NEXT: shll $31, %edx ; X86-SSE-NEXT: shll $31, %edx
; X86-SSE-NEXT: xorl {{[0-9]+}}(%esp), %edx ; X86-SSE-NEXT: xorl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: .LBB17_4: ; X86-SSE-NEXT: .LBB17_4:
; X86-SSE-NEXT: ucomisd {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomisd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $-1, %ecx ; X86-SSE-NEXT: movl $-1, %ecx
; X86-SSE-NEXT: cmoval %ecx, %edx ; X86-SSE-NEXT: cmoval %ecx, %edx
; X86-SSE-NEXT: cmoval %ecx, %eax ; X86-SSE-NEXT: cmoval %ecx, %eax
; X86-SSE-NEXT: addl $20, %esp ; X86-SSE-NEXT: addl $20, %esp
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-LABEL: test_unsigned_i64_f64: ; X64-LABEL: test_unsigned_i64_f64:
; X64: # %bb.0: ; X64: # %bb.0:
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-X87-NEXT: .LBB18_4: ; X86-X87-NEXT: .LBB18_4:
; X86-X87-NEXT: jb .LBB18_6 ; X86-X87-NEXT: jb .LBB18_6
; X86-X87-NEXT: # %bb.5: ; X86-X87-NEXT: # %bb.5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-X87-NEXT: .LBB18_6: ; X86-X87-NEXT: .LBB18_6:
; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: fldl {{\.LCPI.*}} ; X86-X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fldl {{[-0-9]+}}(%e{{[sb]}}p) # 8-byte Folded Reload ; X86-X87-NEXT: fldl {{[-0-9]+}}(%e{{[sb]}}p) # 8-byte Folded Reload
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $15, %eax ; X86-X87-NEXT: movl $15, %eax
; X86-X87-NEXT: ja .LBB18_8 ; X86-X87-NEXT: ja .LBB18_8
; X86-X87-NEXT: # %bb.7: ; X86-X87-NEXT: # %bb.7:
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; X86-SSE-NEXT: movl $0, %edi ; X86-SSE-NEXT: movl $0, %edi
; X86-SSE-NEXT: jb .LBB18_2 ; X86-SSE-NEXT: jb .LBB18_2
; X86-SSE-NEXT: # %bb.1: ; X86-SSE-NEXT: # %bb.1:
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-SSE-NEXT: .LBB18_2: ; X86-SSE-NEXT: .LBB18_2:
; X86-SSE-NEXT: ucomisd {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomisd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $15, %ebx ; X86-SSE-NEXT: movl $15, %ebx
; X86-SSE-NEXT: cmovbel %edi, %ebx ; X86-SSE-NEXT: cmovbel %edi, %ebx
; X86-SSE-NEXT: movl $-1, %edi ; X86-SSE-NEXT: movl $-1, %edi
; X86-SSE-NEXT: cmoval %edi, %edx ; X86-SSE-NEXT: cmoval %edi, %edx
; X86-SSE-NEXT: cmoval %edi, %ecx ; X86-SSE-NEXT: cmoval %edi, %ecx
; X86-SSE-NEXT: cmoval %edi, %eax ; X86-SSE-NEXT: cmoval %edi, %eax
; X86-SSE-NEXT: movl %eax, 8(%esi) ; X86-SSE-NEXT: movl %eax, 8(%esi)
; X86-SSE-NEXT: movl %ecx, 4(%esi) ; X86-SSE-NEXT: movl %ecx, 4(%esi)
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: movl $0, %ebx ; X86-X87-NEXT: movl $0, %ebx
; X86-X87-NEXT: jb .LBB19_6 ; X86-X87-NEXT: jb .LBB19_6
; X86-X87-NEXT: # %bb.5: ; X86-X87-NEXT: # %bb.5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ebx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-X87-NEXT: .LBB19_6: ; X86-X87-NEXT: .LBB19_6:
; X86-X87-NEXT: fldl {{\.LCPI.*}} ; X86-X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fldl {{[-0-9]+}}(%e{{[sb]}}p) # 8-byte Folded Reload ; X86-X87-NEXT: fldl {{[-0-9]+}}(%e{{[sb]}}p) # 8-byte Folded Reload
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $-1, %eax ; X86-X87-NEXT: movl $-1, %eax
; X86-X87-NEXT: movl $-1, %ebp ; X86-X87-NEXT: movl $-1, %ebp
; X86-X87-NEXT: movl $-1, %edi ; X86-X87-NEXT: movl $-1, %edi
Show All 40 Lines
; X86-SSE-NEXT: movl $0, %edi ; X86-SSE-NEXT: movl $0, %edi
; X86-SSE-NEXT: jb .LBB19_2 ; X86-SSE-NEXT: jb .LBB19_2
; X86-SSE-NEXT: # %bb.1: ; X86-SSE-NEXT: # %bb.1:
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-SSE-NEXT: .LBB19_2: ; X86-SSE-NEXT: .LBB19_2:
; X86-SSE-NEXT: ucomisd {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomisd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $-1, %ebx ; X86-SSE-NEXT: movl $-1, %ebx
; X86-SSE-NEXT: cmoval %ebx, %edi ; X86-SSE-NEXT: cmoval %ebx, %edi
; X86-SSE-NEXT: cmoval %ebx, %edx ; X86-SSE-NEXT: cmoval %ebx, %edx
; X86-SSE-NEXT: cmoval %ebx, %ecx ; X86-SSE-NEXT: cmoval %ebx, %ecx
; X86-SSE-NEXT: cmoval %ebx, %eax ; X86-SSE-NEXT: cmoval %ebx, %eax
; X86-SSE-NEXT: movl %eax, 12(%esi) ; X86-SSE-NEXT: movl %eax, 12(%esi)
; X86-SSE-NEXT: movl %ecx, 8(%esi) ; X86-SSE-NEXT: movl %ecx, 8(%esi)
; X86-SSE-NEXT: movl %edx, 4(%esi) ; X86-SSE-NEXT: movl %edx, 4(%esi)
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; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: jb .LBB21_1 ; X86-X87-NEXT: jb .LBB21_1
; X86-X87-NEXT: # %bb.2: ; X86-X87-NEXT: # %bb.2:
; X86-X87-NEXT: movb {{[0-9]+}}(%esp), %cl ; X86-X87-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-X87-NEXT: jmp .LBB21_3 ; X86-X87-NEXT: jmp .LBB21_3
; X86-X87-NEXT: .LBB21_1: ; X86-X87-NEXT: .LBB21_1:
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: .LBB21_3: ; X86-X87-NEXT: .LBB21_3:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movb $-1, %al ; X86-X87-NEXT: movb $-1, %al
; X86-X87-NEXT: ja .LBB21_5 ; X86-X87-NEXT: ja .LBB21_5
; X86-X87-NEXT: # %bb.4: ; X86-X87-NEXT: # %bb.4:
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; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: jb .LBB22_2 ; X86-X87-NEXT: jb .LBB22_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB22_2: ; X86-X87-NEXT: .LBB22_2:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $8191, %eax # imm = 0x1FFF ; X86-X87-NEXT: movl $8191, %eax # imm = 0x1FFF
; X86-X87-NEXT: ja .LBB22_4 ; X86-X87-NEXT: ja .LBB22_4
; X86-X87-NEXT: # %bb.3: ; X86-X87-NEXT: # %bb.3:
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; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: jb .LBB23_2 ; X86-X87-NEXT: jb .LBB23_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB23_2: ; X86-X87-NEXT: .LBB23_2:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $65535, %eax # imm = 0xFFFF ; X86-X87-NEXT: movl $65535, %eax # imm = 0xFFFF
; X86-X87-NEXT: ja .LBB23_4 ; X86-X87-NEXT: ja .LBB23_4
; X86-X87-NEXT: # %bb.3: ; X86-X87-NEXT: # %bb.3:
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; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: jb .LBB24_2 ; X86-X87-NEXT: jb .LBB24_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB24_2: ; X86-X87-NEXT: .LBB24_2:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $524287, %eax # imm = 0x7FFFF ; X86-X87-NEXT: movl $524287, %eax # imm = 0x7FFFF
; X86-X87-NEXT: ja .LBB24_4 ; X86-X87-NEXT: ja .LBB24_4
; X86-X87-NEXT: # %bb.3: ; X86-X87-NEXT: # %bb.3:
; X86-X87-NEXT: movl %ecx, %eax ; X86-X87-NEXT: movl %ecx, %eax
; X86-X87-NEXT: .LBB24_4: ; X86-X87-NEXT: .LBB24_4:
; X86-X87-NEXT: addl $28, %esp ; X86-X87-NEXT: addl $28, %esp
; X86-X87-NEXT: retl ; X86-X87-NEXT: retl
; ;
; X86-SSE-LABEL: test_unsigned_i19_f16: ; X86-SSE-LABEL: test_unsigned_i19_f16:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: subl $12, %esp ; X86-SSE-NEXT: subl $12, %esp
; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl %eax, (%esp) ; X86-SSE-NEXT: movl %eax, (%esp)
; X86-SSE-NEXT: calll __gnu_h2f_ieee ; X86-SSE-NEXT: calll __gnu_h2f_ieee
; X86-SSE-NEXT: fstps {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fstps {{[0-9]+}}(%esp)
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: xorps %xmm1, %xmm1 ; X86-SSE-NEXT: xorps %xmm1, %xmm1
; X86-SSE-NEXT: maxss %xmm1, %xmm0 ; X86-SSE-NEXT: maxss %xmm1, %xmm0
; X86-SSE-NEXT: minss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: minss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: cvttss2si %xmm0, %eax ; X86-SSE-NEXT: cvttss2si %xmm0, %eax
; X86-SSE-NEXT: addl $12, %esp ; X86-SSE-NEXT: addl $12, %esp
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-LABEL: test_unsigned_i19_f16: ; X64-LABEL: test_unsigned_i19_f16:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: pushq %rax ; X64-NEXT: pushq %rax
; X64-NEXT: movzwl %di, %edi ; X64-NEXT: movzwl %di, %edi
Show All 30 Lines
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: jb .LBB25_2 ; X86-X87-NEXT: jb .LBB25_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB25_2: ; X86-X87-NEXT: .LBB25_2:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $-1, %eax ; X86-X87-NEXT: movl $-1, %eax
; X86-X87-NEXT: ja .LBB25_4 ; X86-X87-NEXT: ja .LBB25_4
; X86-X87-NEXT: # %bb.3: ; X86-X87-NEXT: # %bb.3:
Show All 17 Lines
; X86-SSE-NEXT: xorl $-2147483648, %eax # imm = 0x80000000 ; X86-SSE-NEXT: xorl $-2147483648, %eax # imm = 0x80000000
; X86-SSE-NEXT: cvttss2si %xmm0, %ecx ; X86-SSE-NEXT: cvttss2si %xmm0, %ecx
; X86-SSE-NEXT: ucomiss %xmm1, %xmm0 ; X86-SSE-NEXT: ucomiss %xmm1, %xmm0
; X86-SSE-NEXT: cmovael %eax, %ecx ; X86-SSE-NEXT: cmovael %eax, %ecx
; X86-SSE-NEXT: xorl %edx, %edx ; X86-SSE-NEXT: xorl %edx, %edx
; X86-SSE-NEXT: xorps %xmm1, %xmm1 ; X86-SSE-NEXT: xorps %xmm1, %xmm1
; X86-SSE-NEXT: ucomiss %xmm1, %xmm0 ; X86-SSE-NEXT: ucomiss %xmm1, %xmm0
; X86-SSE-NEXT: cmovael %ecx, %edx ; X86-SSE-NEXT: cmovael %ecx, %edx
; X86-SSE-NEXT: ucomiss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $-1, %eax ; X86-SSE-NEXT: movl $-1, %eax
; X86-SSE-NEXT: cmovbel %edx, %eax ; X86-SSE-NEXT: cmovbel %edx, %eax
; X86-SSE-NEXT: addl $12, %esp ; X86-SSE-NEXT: addl $12, %esp
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-LABEL: test_unsigned_i32_f16: ; X64-LABEL: test_unsigned_i32_f16:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: pushq %rax ; X64-NEXT: pushq %rax
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define i50 @test_unsigned_i50_f16(half %f) nounwind { define i50 @test_unsigned_i50_f16(half %f) nounwind {
; X86-X87-LABEL: test_unsigned_i50_f16: ; X86-X87-LABEL: test_unsigned_i50_f16:
; X86-X87: # %bb.0: ; X86-X87: # %bb.0:
; X86-X87-NEXT: pushl %esi ; X86-X87-NEXT: pushl %esi
; X86-X87-NEXT: subl $24, %esp ; X86-X87-NEXT: subl $24, %esp
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: movl %eax, (%esp) ; X86-X87-NEXT: movl %eax, (%esp)
; X86-X87-NEXT: calll __gnu_h2f_ieee ; X86-X87-NEXT: calll __gnu_h2f_ieee
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: setae %al ; X86-X87-NEXT: setae %al
; X86-X87-NEXT: fldz ; X86-X87-NEXT: fldz
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; X86-X87-NEXT: jb .LBB26_4 ; X86-X87-NEXT: jb .LBB26_4
; X86-X87-NEXT: # %bb.3: ; X86-X87-NEXT: # %bb.3:
; X86-X87-NEXT: movl %ecx, %esi ; X86-X87-NEXT: movl %ecx, %esi
; X86-X87-NEXT: .LBB26_4: ; X86-X87-NEXT: .LBB26_4:
; X86-X87-NEXT: jb .LBB26_6 ; X86-X87-NEXT: jb .LBB26_6
; X86-X87-NEXT: # %bb.5: ; X86-X87-NEXT: # %bb.5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-X87-NEXT: .LBB26_6: ; X86-X87-NEXT: .LBB26_6:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $-1, %eax ; X86-X87-NEXT: movl $-1, %eax
; X86-X87-NEXT: ja .LBB26_8 ; X86-X87-NEXT: ja .LBB26_8
; X86-X87-NEXT: # %bb.7: ; X86-X87-NEXT: # %bb.7:
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; X86-SSE-NEXT: movl $0, %esi ; X86-SSE-NEXT: movl $0, %esi
; X86-SSE-NEXT: jb .LBB26_4 ; X86-SSE-NEXT: jb .LBB26_4
; X86-SSE-NEXT: # %bb.3: ; X86-SSE-NEXT: # %bb.3:
; X86-SSE-NEXT: movzbl %cl, %eax ; X86-SSE-NEXT: movzbl %cl, %eax
; X86-SSE-NEXT: shll $31, %eax ; X86-SSE-NEXT: shll $31, %eax
; X86-SSE-NEXT: xorl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: xorl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-SSE-NEXT: .LBB26_4: ; X86-SSE-NEXT: .LBB26_4:
; X86-SSE-NEXT: ucomiss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $262143, %edx # imm = 0x3FFFF ; X86-SSE-NEXT: movl $262143, %edx # imm = 0x3FFFF
; X86-SSE-NEXT: cmovbel %eax, %edx ; X86-SSE-NEXT: cmovbel %eax, %edx
; X86-SSE-NEXT: movl $-1, %eax ; X86-SSE-NEXT: movl $-1, %eax
; X86-SSE-NEXT: cmovbel %esi, %eax ; X86-SSE-NEXT: cmovbel %esi, %eax
; X86-SSE-NEXT: addl $24, %esp ; X86-SSE-NEXT: addl $24, %esp
; X86-SSE-NEXT: popl %esi ; X86-SSE-NEXT: popl %esi
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
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; X86-X87-LABEL: test_unsigned_i64_f16: ; X86-X87-LABEL: test_unsigned_i64_f16:
; X86-X87: # %bb.0: ; X86-X87: # %bb.0:
; X86-X87-NEXT: pushl %edi ; X86-X87-NEXT: pushl %edi
; X86-X87-NEXT: pushl %esi ; X86-X87-NEXT: pushl %esi
; X86-X87-NEXT: subl $20, %esp ; X86-X87-NEXT: subl $20, %esp
; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; X86-X87-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X86-X87-NEXT: movl %eax, (%esp) ; X86-X87-NEXT: movl %eax, (%esp)
; X86-X87-NEXT: calll __gnu_h2f_ieee ; X86-X87-NEXT: calll __gnu_h2f_ieee
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: setae %al ; X86-X87-NEXT: setae %al
; X86-X87-NEXT: fldz ; X86-X87-NEXT: fldz
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; X86-X87-NEXT: jb .LBB27_4 ; X86-X87-NEXT: jb .LBB27_4
; X86-X87-NEXT: # %bb.3: ; X86-X87-NEXT: # %bb.3:
; X86-X87-NEXT: movl %ecx, %edi ; X86-X87-NEXT: movl %ecx, %edi
; X86-X87-NEXT: .LBB27_4: ; X86-X87-NEXT: .LBB27_4:
; X86-X87-NEXT: jb .LBB27_6 ; X86-X87-NEXT: jb .LBB27_6
; X86-X87-NEXT: # %bb.5: ; X86-X87-NEXT: # %bb.5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-X87-NEXT: .LBB27_6: ; X86-X87-NEXT: .LBB27_6:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $-1, %eax ; X86-X87-NEXT: movl $-1, %eax
; X86-X87-NEXT: movl $-1, %edx ; X86-X87-NEXT: movl $-1, %edx
; X86-X87-NEXT: ja .LBB27_8 ; X86-X87-NEXT: ja .LBB27_8
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; X86-SSE-NEXT: movl $0, %eax ; X86-SSE-NEXT: movl $0, %eax
; X86-SSE-NEXT: jb .LBB27_4 ; X86-SSE-NEXT: jb .LBB27_4
; X86-SSE-NEXT: # %bb.3: ; X86-SSE-NEXT: # %bb.3:
; X86-SSE-NEXT: movzbl %cl, %edx ; X86-SSE-NEXT: movzbl %cl, %edx
; X86-SSE-NEXT: shll $31, %edx ; X86-SSE-NEXT: shll $31, %edx
; X86-SSE-NEXT: xorl {{[0-9]+}}(%esp), %edx ; X86-SSE-NEXT: xorl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: .LBB27_4: ; X86-SSE-NEXT: .LBB27_4:
; X86-SSE-NEXT: ucomiss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $-1, %ecx ; X86-SSE-NEXT: movl $-1, %ecx
; X86-SSE-NEXT: cmoval %ecx, %edx ; X86-SSE-NEXT: cmoval %ecx, %edx
; X86-SSE-NEXT: cmoval %ecx, %eax ; X86-SSE-NEXT: cmoval %ecx, %eax
; X86-SSE-NEXT: addl $28, %esp ; X86-SSE-NEXT: addl $28, %esp
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-LABEL: test_unsigned_i64_f16: ; X64-LABEL: test_unsigned_i64_f16:
; X64: # %bb.0: ; X64: # %bb.0:
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; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-X87-NEXT: .LBB28_4: ; X86-X87-NEXT: .LBB28_4:
; X86-X87-NEXT: jb .LBB28_6 ; X86-X87-NEXT: jb .LBB28_6
; X86-X87-NEXT: # %bb.5: ; X86-X87-NEXT: # %bb.5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-X87-NEXT: .LBB28_6: ; X86-X87-NEXT: .LBB28_6:
; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload ; X86-X87-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $15, %eax ; X86-X87-NEXT: movl $15, %eax
; X86-X87-NEXT: ja .LBB28_8 ; X86-X87-NEXT: ja .LBB28_8
; X86-X87-NEXT: # %bb.7: ; X86-X87-NEXT: # %bb.7:
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; X86-SSE-NEXT: movl $0, %edi ; X86-SSE-NEXT: movl $0, %edi
; X86-SSE-NEXT: jb .LBB28_2 ; X86-SSE-NEXT: jb .LBB28_2
; X86-SSE-NEXT: # %bb.1: ; X86-SSE-NEXT: # %bb.1:
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-SSE-NEXT: .LBB28_2: ; X86-SSE-NEXT: .LBB28_2:
; X86-SSE-NEXT: ucomiss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $15, %ebx ; X86-SSE-NEXT: movl $15, %ebx
; X86-SSE-NEXT: cmovbel %edi, %ebx ; X86-SSE-NEXT: cmovbel %edi, %ebx
; X86-SSE-NEXT: movl $-1, %edi ; X86-SSE-NEXT: movl $-1, %edi
; X86-SSE-NEXT: cmoval %edi, %edx ; X86-SSE-NEXT: cmoval %edi, %edx
; X86-SSE-NEXT: cmoval %edi, %ecx ; X86-SSE-NEXT: cmoval %edi, %ecx
; X86-SSE-NEXT: cmoval %edi, %eax ; X86-SSE-NEXT: cmoval %edi, %eax
; X86-SSE-NEXT: movl %eax, 8(%esi) ; X86-SSE-NEXT: movl %eax, 8(%esi)
; X86-SSE-NEXT: movl %ecx, 4(%esi) ; X86-SSE-NEXT: movl %ecx, 4(%esi)
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Lines
; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: movl $0, %ebx ; X86-X87-NEXT: movl $0, %ebx
; X86-X87-NEXT: jb .LBB29_6 ; X86-X87-NEXT: jb .LBB29_6
; X86-X87-NEXT: # %bb.5: ; X86-X87-NEXT: # %bb.5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ebx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-X87-NEXT: .LBB29_6: ; X86-X87-NEXT: .LBB29_6:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload ; X86-X87-NEXT: flds {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $-1, %eax ; X86-X87-NEXT: movl $-1, %eax
; X86-X87-NEXT: movl $-1, %ebp ; X86-X87-NEXT: movl $-1, %ebp
; X86-X87-NEXT: movl $-1, %edi ; X86-X87-NEXT: movl $-1, %edi
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; X86-SSE-NEXT: movl $0, %edi ; X86-SSE-NEXT: movl $0, %edi
; X86-SSE-NEXT: jb .LBB29_2 ; X86-SSE-NEXT: jb .LBB29_2
; X86-SSE-NEXT: # %bb.1: ; X86-SSE-NEXT: # %bb.1:
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-SSE-NEXT: .LBB29_2: ; X86-SSE-NEXT: .LBB29_2:
; X86-SSE-NEXT: ucomiss {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movl $-1, %ebx ; X86-SSE-NEXT: movl $-1, %ebx
; X86-SSE-NEXT: cmoval %ebx, %edi ; X86-SSE-NEXT: cmoval %ebx, %edi
; X86-SSE-NEXT: cmoval %ebx, %edx ; X86-SSE-NEXT: cmoval %ebx, %edx
; X86-SSE-NEXT: cmoval %ebx, %ecx ; X86-SSE-NEXT: cmoval %ebx, %ecx
; X86-SSE-NEXT: cmoval %ebx, %eax ; X86-SSE-NEXT: cmoval %ebx, %eax
; X86-SSE-NEXT: movl %eax, 12(%esi) ; X86-SSE-NEXT: movl %eax, 12(%esi)
; X86-SSE-NEXT: movl %ecx, 8(%esi) ; X86-SSE-NEXT: movl %ecx, 8(%esi)
; X86-SSE-NEXT: movl %edx, 4(%esi) ; X86-SSE-NEXT: movl %edx, 4(%esi)
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; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: jb .LBB31_1 ; X86-X87-NEXT: jb .LBB31_1
; X86-X87-NEXT: # %bb.2: ; X86-X87-NEXT: # %bb.2:
; X86-X87-NEXT: movb {{[0-9]+}}(%esp), %cl ; X86-X87-NEXT: movb {{[0-9]+}}(%esp), %cl
; X86-X87-NEXT: jmp .LBB31_3 ; X86-X87-NEXT: jmp .LBB31_3
; X86-X87-NEXT: .LBB31_1: ; X86-X87-NEXT: .LBB31_1:
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: .LBB31_3: ; X86-X87-NEXT: .LBB31_3:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movb $-1, %al ; X86-X87-NEXT: movb $-1, %al
; X86-X87-NEXT: ja .LBB31_5 ; X86-X87-NEXT: ja .LBB31_5
; X86-X87-NEXT: # %bb.4: ; X86-X87-NEXT: # %bb.4:
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; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldcw {{[0-9]+}}(%esp)
; X86-SSE-NEXT: movzbl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: xorl %ecx, %ecx ; X86-SSE-NEXT: xorl %ecx, %ecx
; X86-SSE-NEXT: fldz ; X86-SSE-NEXT: fldz
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st ; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1) ; X86-SSE-NEXT: fstp %st(1)
; X86-SSE-NEXT: cmovael %eax, %ecx ; X86-SSE-NEXT: cmovael %eax, %ecx
; X86-SSE-NEXT: flds {{\.LCPI.*}} ; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucompi %st(1), %st ; X86-SSE-NEXT: fucompi %st(1), %st
; X86-SSE-NEXT: fstp %st(0) ; X86-SSE-NEXT: fstp %st(0)
; X86-SSE-NEXT: movl $255, %eax ; X86-SSE-NEXT: movl $255, %eax
; X86-SSE-NEXT: cmovbel %ecx, %eax ; X86-SSE-NEXT: cmovbel %ecx, %eax
; X86-SSE-NEXT: # kill: def $al killed $al killed $eax ; X86-SSE-NEXT: # kill: def $al killed $al killed $eax
; X86-SSE-NEXT: addl $8, %esp ; X86-SSE-NEXT: addl $8, %esp
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: jb .LBB32_2 ; X86-X87-NEXT: jb .LBB32_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB32_2: ; X86-X87-NEXT: .LBB32_2:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $8191, %eax # imm = 0x1FFF ; X86-X87-NEXT: movl $8191, %eax # imm = 0x1FFF
; X86-X87-NEXT: ja .LBB32_4 ; X86-X87-NEXT: ja .LBB32_4
; X86-X87-NEXT: # %bb.3: ; X86-X87-NEXT: # %bb.3:
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; X86-SSE-NEXT: fldz ; X86-SSE-NEXT: fldz
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st ; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1) ; X86-SSE-NEXT: fstp %st(1)
; X86-SSE-NEXT: jb .LBB32_2 ; X86-SSE-NEXT: jb .LBB32_2
; X86-SSE-NEXT: # %bb.1: ; X86-SSE-NEXT: # %bb.1:
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-SSE-NEXT: .LBB32_2: ; X86-SSE-NEXT: .LBB32_2:
; X86-SSE-NEXT: flds {{\.LCPI.*}} ; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucompi %st(1), %st ; X86-SSE-NEXT: fucompi %st(1), %st
; X86-SSE-NEXT: fstp %st(0) ; X86-SSE-NEXT: fstp %st(0)
; X86-SSE-NEXT: movl $8191, %eax # imm = 0x1FFF ; X86-SSE-NEXT: movl $8191, %eax # imm = 0x1FFF
; X86-SSE-NEXT: cmovbel %ecx, %eax ; X86-SSE-NEXT: cmovbel %ecx, %eax
; X86-SSE-NEXT: # kill: def $ax killed $ax killed $eax ; X86-SSE-NEXT: # kill: def $ax killed $ax killed $eax
; X86-SSE-NEXT: addl $8, %esp ; X86-SSE-NEXT: addl $8, %esp
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
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; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: jb .LBB33_2 ; X86-X87-NEXT: jb .LBB33_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB33_2: ; X86-X87-NEXT: .LBB33_2:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $65535, %eax # imm = 0xFFFF ; X86-X87-NEXT: movl $65535, %eax # imm = 0xFFFF
; X86-X87-NEXT: ja .LBB33_4 ; X86-X87-NEXT: ja .LBB33_4
; X86-X87-NEXT: # %bb.3: ; X86-X87-NEXT: # %bb.3:
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; X86-SSE-NEXT: fldz ; X86-SSE-NEXT: fldz
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st ; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1) ; X86-SSE-NEXT: fstp %st(1)
; X86-SSE-NEXT: jb .LBB33_2 ; X86-SSE-NEXT: jb .LBB33_2
; X86-SSE-NEXT: # %bb.1: ; X86-SSE-NEXT: # %bb.1:
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-SSE-NEXT: .LBB33_2: ; X86-SSE-NEXT: .LBB33_2:
; X86-SSE-NEXT: flds {{\.LCPI.*}} ; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucompi %st(1), %st ; X86-SSE-NEXT: fucompi %st(1), %st
; X86-SSE-NEXT: fstp %st(0) ; X86-SSE-NEXT: fstp %st(0)
; X86-SSE-NEXT: movl $65535, %eax # imm = 0xFFFF ; X86-SSE-NEXT: movl $65535, %eax # imm = 0xFFFF
; X86-SSE-NEXT: cmovbel %ecx, %eax ; X86-SSE-NEXT: cmovbel %ecx, %eax
; X86-SSE-NEXT: # kill: def $ax killed $ax killed $eax ; X86-SSE-NEXT: # kill: def $ax killed $ax killed $eax
; X86-SSE-NEXT: addl $8, %esp ; X86-SSE-NEXT: addl $8, %esp
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
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; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: jb .LBB34_2 ; X86-X87-NEXT: jb .LBB34_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB34_2: ; X86-X87-NEXT: .LBB34_2:
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $524287, %eax # imm = 0x7FFFF ; X86-X87-NEXT: movl $524287, %eax # imm = 0x7FFFF
; X86-X87-NEXT: ja .LBB34_4 ; X86-X87-NEXT: ja .LBB34_4
; X86-X87-NEXT: # %bb.3: ; X86-X87-NEXT: # %bb.3:
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; X86-SSE-NEXT: fldz ; X86-SSE-NEXT: fldz
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st ; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1) ; X86-SSE-NEXT: fstp %st(1)
; X86-SSE-NEXT: jb .LBB34_2 ; X86-SSE-NEXT: jb .LBB34_2
; X86-SSE-NEXT: # %bb.1: ; X86-SSE-NEXT: # %bb.1:
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-SSE-NEXT: .LBB34_2: ; X86-SSE-NEXT: .LBB34_2:
; X86-SSE-NEXT: flds {{\.LCPI.*}} ; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucompi %st(1), %st ; X86-SSE-NEXT: fucompi %st(1), %st
; X86-SSE-NEXT: fstp %st(0) ; X86-SSE-NEXT: fstp %st(0)
; X86-SSE-NEXT: movl $524287, %eax # imm = 0x7FFFF ; X86-SSE-NEXT: movl $524287, %eax # imm = 0x7FFFF
; X86-SSE-NEXT: cmovbel %ecx, %eax ; X86-SSE-NEXT: cmovbel %ecx, %eax
; X86-SSE-NEXT: addl $20, %esp ; X86-SSE-NEXT: addl $20, %esp
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
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; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: jb .LBB35_2 ; X86-X87-NEXT: jb .LBB35_2
; X86-X87-NEXT: # %bb.1: ; X86-X87-NEXT: # %bb.1:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: .LBB35_2: ; X86-X87-NEXT: .LBB35_2:
; X86-X87-NEXT: fldl {{\.LCPI.*}} ; X86-X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $-1, %eax ; X86-X87-NEXT: movl $-1, %eax
; X86-X87-NEXT: ja .LBB35_4 ; X86-X87-NEXT: ja .LBB35_4
; X86-X87-NEXT: # %bb.3: ; X86-X87-NEXT: # %bb.3:
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; X86-SSE-NEXT: fldz ; X86-SSE-NEXT: fldz
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucomi %st(1), %st ; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: fstp %st(1) ; X86-SSE-NEXT: fstp %st(1)
; X86-SSE-NEXT: jb .LBB35_2 ; X86-SSE-NEXT: jb .LBB35_2
; X86-SSE-NEXT: # %bb.1: ; X86-SSE-NEXT: # %bb.1:
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-SSE-NEXT: .LBB35_2: ; X86-SSE-NEXT: .LBB35_2:
; X86-SSE-NEXT: fldl {{\.LCPI.*}} ; X86-SSE-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucompi %st(1), %st ; X86-SSE-NEXT: fucompi %st(1), %st
; X86-SSE-NEXT: fstp %st(0) ; X86-SSE-NEXT: fstp %st(0)
; X86-SSE-NEXT: movl $-1, %eax ; X86-SSE-NEXT: movl $-1, %eax
; X86-SSE-NEXT: cmovbel %ecx, %eax ; X86-SSE-NEXT: cmovbel %ecx, %eax
; X86-SSE-NEXT: addl $20, %esp ; X86-SSE-NEXT: addl $20, %esp
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
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} }
define i50 @test_unsigned_i50_f80(x86_fp80 %f) nounwind { define i50 @test_unsigned_i50_f80(x86_fp80 %f) nounwind {
; X86-X87-LABEL: test_unsigned_i50_f80: ; X86-X87-LABEL: test_unsigned_i50_f80:
; X86-X87: # %bb.0: ; X86-X87: # %bb.0:
; X86-X87-NEXT: pushl %esi ; X86-X87-NEXT: pushl %esi
; X86-X87-NEXT: subl $16, %esp ; X86-X87-NEXT: subl $16, %esp
; X86-X87-NEXT: fldt {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldt {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: setbe %al ; X86-X87-NEXT: setbe %al
; X86-X87-NEXT: fldz ; X86-X87-NEXT: fldz
; X86-X87-NEXT: jbe .LBB36_2 ; X86-X87-NEXT: jbe .LBB36_2
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; X86-X87-NEXT: jb .LBB36_4 ; X86-X87-NEXT: jb .LBB36_4
; X86-X87-NEXT: # %bb.3: ; X86-X87-NEXT: # %bb.3:
; X86-X87-NEXT: movl %ecx, %esi ; X86-X87-NEXT: movl %ecx, %esi
; X86-X87-NEXT: .LBB36_4: ; X86-X87-NEXT: .LBB36_4:
; X86-X87-NEXT: jb .LBB36_6 ; X86-X87-NEXT: jb .LBB36_6
; X86-X87-NEXT: # %bb.5: ; X86-X87-NEXT: # %bb.5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-X87-NEXT: .LBB36_6: ; X86-X87-NEXT: .LBB36_6:
; X86-X87-NEXT: fldl {{\.LCPI.*}} ; X86-X87-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $-1, %eax ; X86-X87-NEXT: movl $-1, %eax
; X86-X87-NEXT: ja .LBB36_8 ; X86-X87-NEXT: ja .LBB36_8
; X86-X87-NEXT: # %bb.7: ; X86-X87-NEXT: # %bb.7:
; X86-X87-NEXT: movl %edx, %eax ; X86-X87-NEXT: movl %edx, %eax
; X86-X87-NEXT: .LBB36_8: ; X86-X87-NEXT: .LBB36_8:
; X86-X87-NEXT: movl $262143, %edx # imm = 0x3FFFF ; X86-X87-NEXT: movl $262143, %edx # imm = 0x3FFFF
; X86-X87-NEXT: ja .LBB36_10 ; X86-X87-NEXT: ja .LBB36_10
; X86-X87-NEXT: # %bb.9: ; X86-X87-NEXT: # %bb.9:
; X86-X87-NEXT: movl %esi, %edx ; X86-X87-NEXT: movl %esi, %edx
; X86-X87-NEXT: .LBB36_10: ; X86-X87-NEXT: .LBB36_10:
; X86-X87-NEXT: addl $16, %esp ; X86-X87-NEXT: addl $16, %esp
; X86-X87-NEXT: popl %esi ; X86-X87-NEXT: popl %esi
; X86-X87-NEXT: retl ; X86-X87-NEXT: retl
; ;
; X86-SSE-LABEL: test_unsigned_i50_f80: ; X86-SSE-LABEL: test_unsigned_i50_f80:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pushl %esi ; X86-SSE-NEXT: pushl %esi
; X86-SSE-NEXT: subl $16, %esp ; X86-SSE-NEXT: subl $16, %esp
; X86-SSE-NEXT: fldt {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldt {{[0-9]+}}(%esp)
; X86-SSE-NEXT: flds {{\.LCPI.*}} ; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: xorl %eax, %eax ; X86-SSE-NEXT: xorl %eax, %eax
; X86-SSE-NEXT: fucomi %st(1), %st ; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: setbe %cl ; X86-SSE-NEXT: setbe %cl
; X86-SSE-NEXT: fldz ; X86-SSE-NEXT: fldz
; X86-SSE-NEXT: fld %st(0) ; X86-SSE-NEXT: fld %st(0)
; X86-SSE-NEXT: fcmovbe %st(2), %st ; X86-SSE-NEXT: fcmovbe %st(2), %st
; X86-SSE-NEXT: fstp %st(2) ; X86-SSE-NEXT: fstp %st(2)
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
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; X86-SSE-NEXT: jb .LBB36_2 ; X86-SSE-NEXT: jb .LBB36_2
; X86-SSE-NEXT: # %bb.1: ; X86-SSE-NEXT: # %bb.1:
; X86-SSE-NEXT: movb %cl, %al ; X86-SSE-NEXT: movb %cl, %al
; X86-SSE-NEXT: shll $31, %eax ; X86-SSE-NEXT: shll $31, %eax
; X86-SSE-NEXT: xorl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: xorl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl %eax, %esi ; X86-SSE-NEXT: movl %eax, %esi
; X86-SSE-NEXT: .LBB36_2: ; X86-SSE-NEXT: .LBB36_2:
; X86-SSE-NEXT: fldl {{\.LCPI.*}} ; X86-SSE-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucompi %st(1), %st ; X86-SSE-NEXT: fucompi %st(1), %st
; X86-SSE-NEXT: fstp %st(0) ; X86-SSE-NEXT: fstp %st(0)
; X86-SSE-NEXT: movl $-1, %eax ; X86-SSE-NEXT: movl $-1, %eax
; X86-SSE-NEXT: cmovbel %edx, %eax ; X86-SSE-NEXT: cmovbel %edx, %eax
; X86-SSE-NEXT: movl $262143, %edx # imm = 0x3FFFF ; X86-SSE-NEXT: movl $262143, %edx # imm = 0x3FFFF
; X86-SSE-NEXT: cmovbel %esi, %edx ; X86-SSE-NEXT: cmovbel %esi, %edx
; X86-SSE-NEXT: addl $16, %esp ; X86-SSE-NEXT: addl $16, %esp
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define i64 @test_unsigned_i64_f80(x86_fp80 %f) nounwind { define i64 @test_unsigned_i64_f80(x86_fp80 %f) nounwind {
; X86-X87-LABEL: test_unsigned_i64_f80: ; X86-X87-LABEL: test_unsigned_i64_f80:
; X86-X87: # %bb.0: ; X86-X87: # %bb.0:
; X86-X87-NEXT: pushl %edi ; X86-X87-NEXT: pushl %edi
; X86-X87-NEXT: pushl %esi ; X86-X87-NEXT: pushl %esi
; X86-X87-NEXT: subl $20, %esp ; X86-X87-NEXT: subl $20, %esp
; X86-X87-NEXT: fldt {{[0-9]+}}(%esp) ; X86-X87-NEXT: fldt {{[0-9]+}}(%esp)
; X86-X87-NEXT: flds {{\.LCPI.*}} ; X86-X87-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fucom %st(1) ; X86-X87-NEXT: fucom %st(1)
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: xorl %ecx, %ecx ; X86-X87-NEXT: xorl %ecx, %ecx
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: setbe %al ; X86-X87-NEXT: setbe %al
; X86-X87-NEXT: fldz ; X86-X87-NEXT: fldz
; X86-X87-NEXT: jbe .LBB37_2 ; X86-X87-NEXT: jbe .LBB37_2
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; X86-X87-NEXT: jb .LBB37_4 ; X86-X87-NEXT: jb .LBB37_4
; X86-X87-NEXT: # %bb.3: ; X86-X87-NEXT: # %bb.3:
; X86-X87-NEXT: movl %ecx, %edi ; X86-X87-NEXT: movl %ecx, %edi
; X86-X87-NEXT: .LBB37_4: ; X86-X87-NEXT: .LBB37_4:
; X86-X87-NEXT: jb .LBB37_6 ; X86-X87-NEXT: jb .LBB37_6
; X86-X87-NEXT: # %bb.5: ; X86-X87-NEXT: # %bb.5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-X87-NEXT: .LBB37_6: ; X86-X87-NEXT: .LBB37_6:
; X86-X87-NEXT: fldt {{\.LCPI.*}} ; X86-X87-NEXT: fldt {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fxch %st(1) ; X86-X87-NEXT: fxch %st(1)
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $-1, %eax ; X86-X87-NEXT: movl $-1, %eax
; X86-X87-NEXT: movl $-1, %edx ; X86-X87-NEXT: movl $-1, %edx
; X86-X87-NEXT: ja .LBB37_8 ; X86-X87-NEXT: ja .LBB37_8
; X86-X87-NEXT: # %bb.7: ; X86-X87-NEXT: # %bb.7:
; X86-X87-NEXT: movl %esi, %eax ; X86-X87-NEXT: movl %esi, %eax
; X86-X87-NEXT: movl %edi, %edx ; X86-X87-NEXT: movl %edi, %edx
; X86-X87-NEXT: .LBB37_8: ; X86-X87-NEXT: .LBB37_8:
; X86-X87-NEXT: addl $20, %esp ; X86-X87-NEXT: addl $20, %esp
; X86-X87-NEXT: popl %esi ; X86-X87-NEXT: popl %esi
; X86-X87-NEXT: popl %edi ; X86-X87-NEXT: popl %edi
; X86-X87-NEXT: retl ; X86-X87-NEXT: retl
; ;
; X86-SSE-LABEL: test_unsigned_i64_f80: ; X86-SSE-LABEL: test_unsigned_i64_f80:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pushl %ebx ; X86-SSE-NEXT: pushl %ebx
; X86-SSE-NEXT: subl $16, %esp ; X86-SSE-NEXT: subl $16, %esp
; X86-SSE-NEXT: fldt {{[0-9]+}}(%esp) ; X86-SSE-NEXT: fldt {{[0-9]+}}(%esp)
; X86-SSE-NEXT: flds {{\.LCPI.*}} ; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: xorl %ecx, %ecx ; X86-SSE-NEXT: xorl %ecx, %ecx
; X86-SSE-NEXT: fucomi %st(1), %st ; X86-SSE-NEXT: fucomi %st(1), %st
; X86-SSE-NEXT: setbe %bl ; X86-SSE-NEXT: setbe %bl
; X86-SSE-NEXT: fldz ; X86-SSE-NEXT: fldz
; X86-SSE-NEXT: fld %st(0) ; X86-SSE-NEXT: fld %st(0)
; X86-SSE-NEXT: fcmovbe %st(2), %st ; X86-SSE-NEXT: fcmovbe %st(2), %st
; X86-SSE-NEXT: fstp %st(2) ; X86-SSE-NEXT: fstp %st(2)
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
Show All 13 Lines
; X86-SSE-NEXT: jb .LBB37_2 ; X86-SSE-NEXT: jb .LBB37_2
; X86-SSE-NEXT: # %bb.1: ; X86-SSE-NEXT: # %bb.1:
; X86-SSE-NEXT: movb %bl, %cl ; X86-SSE-NEXT: movb %bl, %cl
; X86-SSE-NEXT: shll $31, %ecx ; X86-SSE-NEXT: shll $31, %ecx
; X86-SSE-NEXT: xorl {{[0-9]+}}(%esp), %ecx ; X86-SSE-NEXT: xorl {{[0-9]+}}(%esp), %ecx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl %ecx, %edx ; X86-SSE-NEXT: movl %ecx, %edx
; X86-SSE-NEXT: .LBB37_2: ; X86-SSE-NEXT: .LBB37_2:
; X86-SSE-NEXT: fldt {{\.LCPI.*}} ; X86-SSE-NEXT: fldt {{\.LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucompi %st(1), %st ; X86-SSE-NEXT: fucompi %st(1), %st
; X86-SSE-NEXT: fstp %st(0) ; X86-SSE-NEXT: fstp %st(0)
; X86-SSE-NEXT: movl $-1, %ecx ; X86-SSE-NEXT: movl $-1, %ecx
; X86-SSE-NEXT: cmoval %ecx, %eax ; X86-SSE-NEXT: cmoval %ecx, %eax
; X86-SSE-NEXT: cmoval %ecx, %edx ; X86-SSE-NEXT: cmoval %ecx, %edx
; X86-SSE-NEXT: addl $16, %esp ; X86-SSE-NEXT: addl $16, %esp
; X86-SSE-NEXT: popl %ebx ; X86-SSE-NEXT: popl %ebx
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; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-X87-NEXT: .LBB38_4: ; X86-X87-NEXT: .LBB38_4:
; X86-X87-NEXT: jb .LBB38_6 ; X86-X87-NEXT: jb .LBB38_6
; X86-X87-NEXT: # %bb.5: ; X86-X87-NEXT: # %bb.5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-X87-NEXT: .LBB38_6: ; X86-X87-NEXT: .LBB38_6:
; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: fldt {{\.LCPI.*}} ; X86-X87-NEXT: fldt {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Reload ; X86-X87-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Reload
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $15, %eax ; X86-X87-NEXT: movl $15, %eax
; X86-X87-NEXT: ja .LBB38_8 ; X86-X87-NEXT: ja .LBB38_8
; X86-X87-NEXT: # %bb.7: ; X86-X87-NEXT: # %bb.7:
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; X86-SSE-NEXT: movl $0, %edi ; X86-SSE-NEXT: movl $0, %edi
; X86-SSE-NEXT: jb .LBB38_2 ; X86-SSE-NEXT: jb .LBB38_2
; X86-SSE-NEXT: # %bb.1: ; X86-SSE-NEXT: # %bb.1:
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-SSE-NEXT: .LBB38_2: ; X86-SSE-NEXT: .LBB38_2:
; X86-SSE-NEXT: fldt {{\.LCPI.*}} ; X86-SSE-NEXT: fldt {{\.LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucompi %st(1), %st ; X86-SSE-NEXT: fucompi %st(1), %st
; X86-SSE-NEXT: fstp %st(0) ; X86-SSE-NEXT: fstp %st(0)
; X86-SSE-NEXT: movl $15, %ebx ; X86-SSE-NEXT: movl $15, %ebx
; X86-SSE-NEXT: cmovbel %edi, %ebx ; X86-SSE-NEXT: cmovbel %edi, %ebx
; X86-SSE-NEXT: movl $-1, %edi ; X86-SSE-NEXT: movl $-1, %edi
; X86-SSE-NEXT: cmoval %edi, %edx ; X86-SSE-NEXT: cmoval %edi, %edx
; X86-SSE-NEXT: cmoval %edi, %ecx ; X86-SSE-NEXT: cmoval %edi, %ecx
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; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-X87-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-X87-NEXT: movl $0, %ebx ; X86-X87-NEXT: movl $0, %ebx
; X86-X87-NEXT: jb .LBB39_6 ; X86-X87-NEXT: jb .LBB39_6
; X86-X87-NEXT: # %bb.5: ; X86-X87-NEXT: # %bb.5:
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ebx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-X87-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-X87-NEXT: .LBB39_6: ; X86-X87-NEXT: .LBB39_6:
; X86-X87-NEXT: fldt {{\.LCPI.*}} ; X86-X87-NEXT: fldt {{\.LCPI[0-9]+_[0-9]+}}
; X86-X87-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Reload ; X86-X87-NEXT: fldt {{[-0-9]+}}(%e{{[sb]}}p) # 10-byte Folded Reload
; X86-X87-NEXT: fucompp ; X86-X87-NEXT: fucompp
; X86-X87-NEXT: fnstsw %ax ; X86-X87-NEXT: fnstsw %ax
; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax ; X86-X87-NEXT: # kill: def $ah killed $ah killed $ax
; X86-X87-NEXT: sahf ; X86-X87-NEXT: sahf
; X86-X87-NEXT: movl $-1, %eax ; X86-X87-NEXT: movl $-1, %eax
; X86-X87-NEXT: movl $-1, %ebp ; X86-X87-NEXT: movl $-1, %ebp
; X86-X87-NEXT: movl $-1, %edi ; X86-X87-NEXT: movl $-1, %edi
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; X86-SSE-NEXT: movl $0, %edi ; X86-SSE-NEXT: movl $0, %edi
; X86-SSE-NEXT: jb .LBB39_2 ; X86-SSE-NEXT: jb .LBB39_2
; X86-SSE-NEXT: # %bb.1: ; X86-SSE-NEXT: # %bb.1:
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-SSE-NEXT: .LBB39_2: ; X86-SSE-NEXT: .LBB39_2:
; X86-SSE-NEXT: fldt {{\.LCPI.*}} ; X86-SSE-NEXT: fldt {{\.LCPI[0-9]+_[0-9]+}}
; X86-SSE-NEXT: fxch %st(1) ; X86-SSE-NEXT: fxch %st(1)
; X86-SSE-NEXT: fucompi %st(1), %st ; X86-SSE-NEXT: fucompi %st(1), %st
; X86-SSE-NEXT: fstp %st(0) ; X86-SSE-NEXT: fstp %st(0)
; X86-SSE-NEXT: movl $-1, %ebx ; X86-SSE-NEXT: movl $-1, %ebx
; X86-SSE-NEXT: cmoval %ebx, %edi ; X86-SSE-NEXT: cmoval %ebx, %edi
; X86-SSE-NEXT: cmoval %ebx, %edx ; X86-SSE-NEXT: cmoval %ebx, %edx
; X86-SSE-NEXT: cmoval %ebx, %ecx ; X86-SSE-NEXT: cmoval %ebx, %ecx
; X86-SSE-NEXT: cmoval %ebx, %eax ; X86-SSE-NEXT: cmoval %ebx, %eax
Show All 38 Lines

llvm/test/CodeGen/X86/funnel-shift-rot.ll

Show First 20 Lines • Show All 124 Lines • ▼ Show 20 Lines; X64-AVX2-NEXT: retq
ret i32 %f ret i32 %f
} }
; Vector rotate. ; Vector rotate.
define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %z) nounwind { define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %z) nounwind {
; X32-SSE2-LABEL: rotl_v4i32: ; X32-SSE2-LABEL: rotl_v4i32:
; X32-SSE2: # %bb.0: ; X32-SSE2: # %bb.0:
; X32-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X32-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X32-SSE2-NEXT: pslld $23, %xmm1 ; X32-SSE2-NEXT: pslld $23, %xmm1
; X32-SSE2-NEXT: paddd {{\.LCPI.*}}, %xmm1 ; X32-SSE2-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X32-SSE2-NEXT: cvttps2dq %xmm1, %xmm1 ; X32-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; X32-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; X32-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; X32-SSE2-NEXT: pmuludq %xmm1, %xmm0 ; X32-SSE2-NEXT: pmuludq %xmm1, %xmm0
; X32-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3] ; X32-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3]
; X32-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; X32-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; X32-SSE2-NEXT: pmuludq %xmm2, %xmm1 ; X32-SSE2-NEXT: pmuludq %xmm2, %xmm1
; X32-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3] ; X32-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3]
; X32-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1] ; X32-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
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; Vector rotate. ; Vector rotate.
define <4 x i32> @rotr_v4i32(<4 x i32> %x, <4 x i32> %z) nounwind { define <4 x i32> @rotr_v4i32(<4 x i32> %x, <4 x i32> %z) nounwind {
; X32-SSE2-LABEL: rotr_v4i32: ; X32-SSE2-LABEL: rotr_v4i32:
; X32-SSE2: # %bb.0: ; X32-SSE2: # %bb.0:
; X32-SSE2-NEXT: pxor %xmm2, %xmm2 ; X32-SSE2-NEXT: pxor %xmm2, %xmm2
; X32-SSE2-NEXT: psubd %xmm1, %xmm2 ; X32-SSE2-NEXT: psubd %xmm1, %xmm2
; X32-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm2 ; X32-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
; X32-SSE2-NEXT: pslld $23, %xmm2 ; X32-SSE2-NEXT: pslld $23, %xmm2
; X32-SSE2-NEXT: paddd {{\.LCPI.*}}, %xmm2 ; X32-SSE2-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
; X32-SSE2-NEXT: cvttps2dq %xmm2, %xmm1 ; X32-SSE2-NEXT: cvttps2dq %xmm2, %xmm1
; X32-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; X32-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; X32-SSE2-NEXT: pmuludq %xmm1, %xmm0 ; X32-SSE2-NEXT: pmuludq %xmm1, %xmm0
; X32-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3] ; X32-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3]
; X32-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; X32-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; X32-SSE2-NEXT: pmuludq %xmm2, %xmm1 ; X32-SSE2-NEXT: pmuludq %xmm2, %xmm1
; X32-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3] ; X32-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3]
; X32-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1] ; X32-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
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llvm/test/CodeGen/X86/haddsub-broadcast.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -mattr=avx2 | FileCheck %s ; RUN: llc < %s -mtriple=i686-- -mattr=avx2 | FileCheck %s
; The broadcast node takes a vector operand as input and changes its length. ; The broadcast node takes a vector operand as input and changes its length.
define <4 x double> @PR43402(i64 %x) { define <4 x double> @PR43402(i64 %x) {
; CHECK-LABEL: PR43402: ; CHECK-LABEL: PR43402:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] ; CHECK-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; CHECK-NEXT: vsubpd {{\.LCPI.*}}, %xmm0, %xmm0 ; CHECK-NEXT: vsubpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; CHECK-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; CHECK-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; CHECK-NEXT: vaddsd %xmm0, %xmm1, %xmm0 ; CHECK-NEXT: vaddsd %xmm0, %xmm1, %xmm0
; CHECK-NEXT: vbroadcastsd %xmm0, %ymm0 ; CHECK-NEXT: vbroadcastsd %xmm0, %ymm0
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%conv = uitofp i64 %x to double %conv = uitofp i64 %x to double
%t2 = insertelement <4 x double> undef, double %conv, i32 0 %t2 = insertelement <4 x double> undef, double %conv, i32 0
%t3 = shufflevector <4 x double> %t2, <4 x double> undef, <4 x i32> zeroinitializer %t3 = shufflevector <4 x double> %t2, <4 x double> undef, <4 x i32> zeroinitializer
ret <4 x double> %t3 ret <4 x double> %t3
} }

llvm/test/CodeGen/X86/half.ll

Show First 20 Lines • Show All 358 Lines • ▼ Show 20 Lines
; CHECK-I686-NEXT: pushl %esi ; CHECK-I686-NEXT: pushl %esi
; CHECK-I686-NEXT: subl $24, %esp ; CHECK-I686-NEXT: subl $24, %esp
; CHECK-I686-NEXT: movl {{[0-9]+}}(%esp), %esi ; CHECK-I686-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK-I686-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-I686-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-I686-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-I686-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-I686-NEXT: movlps %xmm0, {{[0-9]+}}(%esp) ; CHECK-I686-NEXT: movlps %xmm0, {{[0-9]+}}(%esp)
; CHECK-I686-NEXT: shrl $31, %eax ; CHECK-I686-NEXT: shrl $31, %eax
; CHECK-I686-NEXT: fildll {{[0-9]+}}(%esp) ; CHECK-I686-NEXT: fildll {{[0-9]+}}(%esp)
; CHECK-I686-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; CHECK-I686-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; CHECK-I686-NEXT: fstps (%esp) ; CHECK-I686-NEXT: fstps (%esp)
; CHECK-I686-NEXT: calll __gnu_f2h_ieee ; CHECK-I686-NEXT: calll __gnu_f2h_ieee
; CHECK-I686-NEXT: movw %ax, (%esi) ; CHECK-I686-NEXT: movw %ax, (%esi)
; CHECK-I686-NEXT: addl $24, %esp ; CHECK-I686-NEXT: addl $24, %esp
; CHECK-I686-NEXT: popl %esi ; CHECK-I686-NEXT: popl %esi
; CHECK-I686-NEXT: retl ; CHECK-I686-NEXT: retl
%r = uitofp i64 %a to half %r = uitofp i64 %a to half
store half %r, half* %p store half %r, half* %p
▲ Show 20 Lines • Show All 595 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll

Show First 20 Lines • Show All 493 Lines • ▼ Show 20 Lines
; A few trivial vector tests ; A few trivial vector tests
;------------------------------------------------------------------------------; ;------------------------------------------------------------------------------;
define <4 x i1> @vec_4xi32_splat_eq(<4 x i32> %x, <4 x i32> %y) nounwind { define <4 x i1> @vec_4xi32_splat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
; X86-SSE2-LABEL: vec_4xi32_splat_eq: ; X86-SSE2-LABEL: vec_4xi32_splat_eq:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pxor %xmm2, %xmm2 ; X86-SSE2-NEXT: pxor %xmm2, %xmm2
; X86-SSE2-NEXT: pslld $23, %xmm1 ; X86-SSE2-NEXT: pslld $23, %xmm1
; X86-SSE2-NEXT: paddd {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1 ; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; X86-SSE2-NEXT: pmuludq %xmm1, %xmm0 ; X86-SSE2-NEXT: pmuludq %xmm1, %xmm0
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; X86-SSE2-NEXT: pmuludq %xmm3, %xmm1 ; X86-SSE2-NEXT: pmuludq %xmm3, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pcmpeqd %xmm2, %xmm0 ; X86-SSE2-NEXT: pcmpeqd %xmm2, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; AVX2-LABEL: vec_4xi32_splat_eq: ; AVX2-LABEL: vec_4xi32_splat_eq:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [1,1,1,1] ; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [1,1,1,1]
; AVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3 ; AVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX2-NEXT: vpsllvd %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines; AVX2-NEXT: ret{{[l|q]}}
ret <4 x i1> %res ret <4 x i1> %res
} }
define <4 x i1> @vec_4xi32_nonsplat_undef0_eq(<4 x i32> %x, <4 x i32> %y) nounwind { define <4 x i1> @vec_4xi32_nonsplat_undef0_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
; X86-SSE2-LABEL: vec_4xi32_nonsplat_undef0_eq: ; X86-SSE2-LABEL: vec_4xi32_nonsplat_undef0_eq:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pxor %xmm2, %xmm2 ; X86-SSE2-NEXT: pxor %xmm2, %xmm2
; X86-SSE2-NEXT: pslld $23, %xmm1 ; X86-SSE2-NEXT: pslld $23, %xmm1
; X86-SSE2-NEXT: paddd {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1 ; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
; X86-SSE2-NEXT: pmuludq %xmm1, %xmm0 ; X86-SSE2-NEXT: pmuludq %xmm1, %xmm0
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; X86-SSE2-NEXT: pmuludq %xmm3, %xmm1 ; X86-SSE2-NEXT: pmuludq %xmm3, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pcmpeqd %xmm2, %xmm0 ; X86-SSE2-NEXT: pcmpeqd %xmm2, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; AVX2-LABEL: vec_4xi32_nonsplat_undef0_eq: ; AVX2-LABEL: vec_4xi32_nonsplat_undef0_eq:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [1,1,1,1] ; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [1,1,1,1]
; AVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3 ; AVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3
; AVX2-NEXT: vpsllvd %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
▲ Show 20 Lines • Show All 235 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll

Show First 20 Lines • Show All 455 Lines • ▼ Show 20 Lines
;------------------------------------------------------------------------------; ;------------------------------------------------------------------------------;
; A few trivial vector tests ; A few trivial vector tests
;------------------------------------------------------------------------------; ;------------------------------------------------------------------------------;
define <4 x i1> @vec_4xi32_splat_eq(<4 x i32> %x, <4 x i32> %y) nounwind { define <4 x i1> @vec_4xi32_splat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
; X86-SSE2-LABEL: vec_4xi32_splat_eq: ; X86-SSE2-LABEL: vec_4xi32_splat_eq:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pslld $23, %xmm1 ; X86-SSE2-NEXT: pslld $23, %xmm1
; X86-SSE2-NEXT: paddd {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1 ; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [1,1,1,1] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [1,1,1,1]
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
; X86-SSE2-NEXT: pmuludq %xmm2, %xmm3 ; X86-SSE2-NEXT: pmuludq %xmm2, %xmm3
; X86-SSE2-NEXT: pmuludq %xmm1, %xmm2 ; X86-SSE2-NEXT: pmuludq %xmm1, %xmm2
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[0,2,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[0,2,2,3]
; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] ; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
Show All 32 Lines; X64-SSE2-NEXT: retq
%res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0> %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>
ret <4 x i1> %res ret <4 x i1> %res
} }
define <4 x i1> @vec_4xi32_nonsplat_eq(<4 x i32> %x, <4 x i32> %y) nounwind { define <4 x i1> @vec_4xi32_nonsplat_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
; X86-SSE2-LABEL: vec_4xi32_nonsplat_eq: ; X86-SSE2-LABEL: vec_4xi32_nonsplat_eq:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pslld $23, %xmm1 ; X86-SSE2-NEXT: pslld $23, %xmm1
; X86-SSE2-NEXT: paddd {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1 ; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [0,1,16776960,2147483648] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [0,1,16776960,2147483648]
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[1,1,3,3]
; X86-SSE2-NEXT: pmuludq %xmm1, %xmm2 ; X86-SSE2-NEXT: pmuludq %xmm1, %xmm2
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; X86-SSE2-NEXT: pmuludq %xmm3, %xmm1 ; X86-SSE2-NEXT: pmuludq %xmm3, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
Show All 36 Lines
} }
define <4 x i1> @vec_4xi32_nonsplat_undef0_eq(<4 x i32> %x, <4 x i32> %y) nounwind { define <4 x i1> @vec_4xi32_nonsplat_undef0_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
; X86-SSE2-LABEL: vec_4xi32_nonsplat_undef0_eq: ; X86-SSE2-LABEL: vec_4xi32_nonsplat_undef0_eq:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movl $1, %eax ; X86-SSE2-NEXT: movl $1, %eax
; X86-SSE2-NEXT: movd %eax, %xmm2 ; X86-SSE2-NEXT: movd %eax, %xmm2
; X86-SSE2-NEXT: pslld $23, %xmm1 ; X86-SSE2-NEXT: pslld $23, %xmm1
; X86-SSE2-NEXT: paddd {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1 ; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; X86-SSE2-NEXT: pmuludq %xmm1, %xmm2 ; X86-SSE2-NEXT: pmuludq %xmm1, %xmm2
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; X86-SSE2-NEXT: pmuludq {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pmuludq {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] ; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; X86-SSE2-NEXT: pand %xmm2, %xmm0 ; X86-SSE2-NEXT: pand %xmm2, %xmm0
; X86-SSE2-NEXT: pxor %xmm1, %xmm1 ; X86-SSE2-NEXT: pxor %xmm1, %xmm1
; X86-SSE2-NEXT: pcmpeqd %xmm1, %xmm0 ; X86-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; AVX2-LABEL: vec_4xi32_nonsplat_undef0_eq: ; AVX2-LABEL: vec_4xi32_nonsplat_undef0_eq:
Show All 26 Lines; X64-SSE2-NEXT: retq
%t1 = and <4 x i32> %t0, %x %t1 = and <4 x i32> %t0, %x
%res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0> %res = icmp eq <4 x i32> %t1, <i32 0, i32 0, i32 0, i32 0>
ret <4 x i1> %res ret <4 x i1> %res
} }
define <4 x i1> @vec_4xi32_nonsplat_undef1_eq(<4 x i32> %x, <4 x i32> %y) nounwind { define <4 x i1> @vec_4xi32_nonsplat_undef1_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
; X86-SSE2-LABEL: vec_4xi32_nonsplat_undef1_eq: ; X86-SSE2-LABEL: vec_4xi32_nonsplat_undef1_eq:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pslld $23, %xmm1 ; X86-SSE2-NEXT: pslld $23, %xmm1
; X86-SSE2-NEXT: paddd {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1 ; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [1,1,1,1] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [1,1,1,1]
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm1[1,1,3,3]
; X86-SSE2-NEXT: pmuludq %xmm2, %xmm3 ; X86-SSE2-NEXT: pmuludq %xmm2, %xmm3
; X86-SSE2-NEXT: pmuludq %xmm1, %xmm2 ; X86-SSE2-NEXT: pmuludq %xmm1, %xmm2
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[0,2,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm3[0,2,2,3]
; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] ; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
Show All 33 Lines; X64-SSE2-NEXT: retq
ret <4 x i1> %res ret <4 x i1> %res
} }
define <4 x i1> @vec_4xi32_nonsplat_undef2_eq(<4 x i32> %x, <4 x i32> %y) nounwind { define <4 x i1> @vec_4xi32_nonsplat_undef2_eq(<4 x i32> %x, <4 x i32> %y) nounwind {
; X86-SSE2-LABEL: vec_4xi32_nonsplat_undef2_eq: ; X86-SSE2-LABEL: vec_4xi32_nonsplat_undef2_eq:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movl $1, %eax ; X86-SSE2-NEXT: movl $1, %eax
; X86-SSE2-NEXT: movd %eax, %xmm2 ; X86-SSE2-NEXT: movd %eax, %xmm2
; X86-SSE2-NEXT: pslld $23, %xmm1 ; X86-SSE2-NEXT: pslld $23, %xmm1
; X86-SSE2-NEXT: paddd {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1 ; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; X86-SSE2-NEXT: pmuludq %xmm1, %xmm2 ; X86-SSE2-NEXT: pmuludq %xmm1, %xmm2
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; X86-SSE2-NEXT: pmuludq {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pmuludq {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] ; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
; X86-SSE2-NEXT: pand %xmm2, %xmm0 ; X86-SSE2-NEXT: pand %xmm2, %xmm0
; X86-SSE2-NEXT: pxor %xmm1, %xmm1 ; X86-SSE2-NEXT: pxor %xmm1, %xmm1
; X86-SSE2-NEXT: pcmpeqd %xmm1, %xmm0 ; X86-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; AVX2-LABEL: vec_4xi32_nonsplat_undef2_eq: ; AVX2-LABEL: vec_4xi32_nonsplat_undef2_eq:
▲ Show 20 Lines • Show All 180 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/i64-to-float.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86-SSE ; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86-SSE
; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx | FileCheck %s --check-prefix=X86-AVX ; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx | FileCheck %s --check-prefix=X86-AVX
; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx512f,+avx512vl | FileCheck %s --check-prefix=X86-AVX512F ; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx512f,+avx512vl | FileCheck %s --check-prefix=X86-AVX512F
; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx512f,+avx512dq,+avx512vl | FileCheck %s --check-prefix=X86-AVX512DQ ; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx512f,+avx512dq,+avx512vl | FileCheck %s --check-prefix=X86-AVX512DQ
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64-SSE ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64-SSE
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=X64-AVX ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=X64-AVX
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f,+avx512vl | FileCheck %s --check-prefix=X64-AVX512F ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f,+avx512vl | FileCheck %s --check-prefix=X64-AVX512F
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f,+avx512dq,+avx512vl | FileCheck %s --check-prefix=X64-AVX512DQ ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx512f,+avx512dq,+avx512vl | FileCheck %s --check-prefix=X64-AVX512DQ
;PR29078 ;PR29078
define <2 x double> @mask_sitofp_2i64_2f64(<2 x i64> %a) nounwind { define <2 x double> @mask_sitofp_2i64_2f64(<2 x i64> %a) nounwind {
; X86-SSE-LABEL: mask_sitofp_2i64_2f64: ; X86-SSE-LABEL: mask_sitofp_2i64_2f64:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: cvtdq2pd %xmm0, %xmm0 ; X86-SSE-NEXT: cvtdq2pd %xmm0, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X86-AVX-LABEL: mask_sitofp_2i64_2f64: ; X86-AVX-LABEL: mask_sitofp_2i64_2f64:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[8,9],zero,zero,xmm0[u,u,u,u,u,u,u,u] ; X86-AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[8,9],zero,zero,xmm0[u,u,u,u,u,u,u,u]
; X86-AVX-NEXT: vcvtdq2pd %xmm0, %xmm0 ; X86-AVX-NEXT: vcvtdq2pd %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X86-AVX512F-LABEL: mask_sitofp_2i64_2f64: ; X86-AVX512F-LABEL: mask_sitofp_2i64_2f64:
; X86-AVX512F: # %bb.0: ; X86-AVX512F: # %bb.0:
; X86-AVX512F-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[8,9],zero,zero,xmm0[u,u,u,u,u,u,u,u] ; X86-AVX512F-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[8,9],zero,zero,xmm0[u,u,u,u,u,u,u,u]
; X86-AVX512F-NEXT: vcvtdq2pd %xmm0, %xmm0 ; X86-AVX512F-NEXT: vcvtdq2pd %xmm0, %xmm0
; X86-AVX512F-NEXT: retl ; X86-AVX512F-NEXT: retl
; ;
; X86-AVX512DQ-LABEL: mask_sitofp_2i64_2f64: ; X86-AVX512DQ-LABEL: mask_sitofp_2i64_2f64:
; X86-AVX512DQ: # %bb.0: ; X86-AVX512DQ: # %bb.0:
; X86-AVX512DQ-NEXT: vandps {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX512DQ-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX512DQ-NEXT: vcvtqq2pd %xmm0, %xmm0 ; X86-AVX512DQ-NEXT: vcvtqq2pd %xmm0, %xmm0
; X86-AVX512DQ-NEXT: retl ; X86-AVX512DQ-NEXT: retl
; ;
; X64-SSE-LABEL: mask_sitofp_2i64_2f64: ; X64-SSE-LABEL: mask_sitofp_2i64_2f64:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; X64-SSE-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE-NEXT: cvtdq2pd %xmm0, %xmm0 ; X64-SSE-NEXT: cvtdq2pd %xmm0, %xmm0
Show All 20 Lines; X64-AVX512DQ-NEXT: retq
%cvt = sitofp <2 x i64> %and to <2 x double> %cvt = sitofp <2 x i64> %and to <2 x double>
ret <2 x double> %cvt ret <2 x double> %cvt
} }
define <2 x double> @mask_uitofp_2i64_2f64(<2 x i64> %a) nounwind { define <2 x double> @mask_uitofp_2i64_2f64(<2 x i64> %a) nounwind {
; X86-SSE-LABEL: mask_uitofp_2i64_2f64: ; X86-SSE-LABEL: mask_uitofp_2i64_2f64:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: cvtdq2pd %xmm0, %xmm0 ; X86-SSE-NEXT: cvtdq2pd %xmm0, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X86-AVX-LABEL: mask_uitofp_2i64_2f64: ; X86-AVX-LABEL: mask_uitofp_2i64_2f64:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[8,9],zero,zero,xmm0[u,u,u,u,u,u,u,u] ; X86-AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[8,9],zero,zero,xmm0[u,u,u,u,u,u,u,u]
; X86-AVX-NEXT: vcvtdq2pd %xmm0, %xmm0 ; X86-AVX-NEXT: vcvtdq2pd %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X86-AVX512F-LABEL: mask_uitofp_2i64_2f64: ; X86-AVX512F-LABEL: mask_uitofp_2i64_2f64:
; X86-AVX512F: # %bb.0: ; X86-AVX512F: # %bb.0:
; X86-AVX512F-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[8,9],zero,zero,xmm0[u,u,u,u,u,u,u,u] ; X86-AVX512F-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[8,9],zero,zero,xmm0[u,u,u,u,u,u,u,u]
; X86-AVX512F-NEXT: vcvtdq2pd %xmm0, %xmm0 ; X86-AVX512F-NEXT: vcvtdq2pd %xmm0, %xmm0
; X86-AVX512F-NEXT: retl ; X86-AVX512F-NEXT: retl
; ;
; X86-AVX512DQ-LABEL: mask_uitofp_2i64_2f64: ; X86-AVX512DQ-LABEL: mask_uitofp_2i64_2f64:
; X86-AVX512DQ: # %bb.0: ; X86-AVX512DQ: # %bb.0:
; X86-AVX512DQ-NEXT: vandps {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX512DQ-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX512DQ-NEXT: vcvtqq2pd %xmm0, %xmm0 ; X86-AVX512DQ-NEXT: vcvtqq2pd %xmm0, %xmm0
; X86-AVX512DQ-NEXT: retl ; X86-AVX512DQ-NEXT: retl
; ;
; X64-SSE-LABEL: mask_uitofp_2i64_2f64: ; X64-SSE-LABEL: mask_uitofp_2i64_2f64:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; X64-SSE-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE-NEXT: cvtdq2pd %xmm0, %xmm0 ; X64-SSE-NEXT: cvtdq2pd %xmm0, %xmm0
Show All 20 Lines; X64-AVX512DQ-NEXT: retq
%cvt = uitofp <2 x i64> %and to <2 x double> %cvt = uitofp <2 x i64> %and to <2 x double>
ret <2 x double> %cvt ret <2 x double> %cvt
} }
define <4 x float> @mask_sitofp_4i64_4f32(<4 x i64> %a) nounwind { define <4 x float> @mask_sitofp_4i64_4f32(<4 x i64> %a) nounwind {
; X86-SSE-LABEL: mask_sitofp_4i64_4f32: ; X86-SSE-LABEL: mask_sitofp_4i64_4f32:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; X86-SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; X86-SSE-NEXT: andps {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: cvtdq2ps %xmm0, %xmm0 ; X86-SSE-NEXT: cvtdq2ps %xmm0, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X86-AVX-LABEL: mask_sitofp_4i64_4f32: ; X86-AVX-LABEL: mask_sitofp_4i64_4f32:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 ; X86-AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; X86-AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; X86-AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; X86-AVX-NEXT: vandps {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vcvtdq2ps %xmm0, %xmm0 ; X86-AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
; X86-AVX-NEXT: vzeroupper ; X86-AVX-NEXT: vzeroupper
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X86-AVX512F-LABEL: mask_sitofp_4i64_4f32: ; X86-AVX512F-LABEL: mask_sitofp_4i64_4f32:
; X86-AVX512F: # %bb.0: ; X86-AVX512F: # %bb.0:
; X86-AVX512F-NEXT: vpmovqd %ymm0, %xmm0 ; X86-AVX512F-NEXT: vpmovqd %ymm0, %xmm0
; X86-AVX512F-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX512F-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX512F-NEXT: vcvtdq2ps %xmm0, %xmm0 ; X86-AVX512F-NEXT: vcvtdq2ps %xmm0, %xmm0
; X86-AVX512F-NEXT: vzeroupper ; X86-AVX512F-NEXT: vzeroupper
; X86-AVX512F-NEXT: retl ; X86-AVX512F-NEXT: retl
; ;
; X86-AVX512DQ-LABEL: mask_sitofp_4i64_4f32: ; X86-AVX512DQ-LABEL: mask_sitofp_4i64_4f32:
; X86-AVX512DQ: # %bb.0: ; X86-AVX512DQ: # %bb.0:
; X86-AVX512DQ-NEXT: vandps {{\.LCPI.*}}, %ymm0, %ymm0 ; X86-AVX512DQ-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-AVX512DQ-NEXT: vcvtqq2ps %ymm0, %xmm0 ; X86-AVX512DQ-NEXT: vcvtqq2ps %ymm0, %xmm0
; X86-AVX512DQ-NEXT: vzeroupper ; X86-AVX512DQ-NEXT: vzeroupper
; X86-AVX512DQ-NEXT: retl ; X86-AVX512DQ-NEXT: retl
; ;
; X64-SSE-LABEL: mask_sitofp_4i64_4f32: ; X64-SSE-LABEL: mask_sitofp_4i64_4f32:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; X64-SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; X64-SSE-NEXT: andps {{.*}}(%rip), %xmm0 ; X64-SSE-NEXT: andps {{.*}}(%rip), %xmm0
Show All 27 Lines; X64-AVX512DQ-NEXT: retq
%cvt = sitofp <4 x i64> %and to <4 x float> %cvt = sitofp <4 x i64> %and to <4 x float>
ret <4 x float> %cvt ret <4 x float> %cvt
} }
define <4 x float> @mask_uitofp_4i64_4f32(<4 x i64> %a) nounwind { define <4 x float> @mask_uitofp_4i64_4f32(<4 x i64> %a) nounwind {
; X86-SSE-LABEL: mask_uitofp_4i64_4f32: ; X86-SSE-LABEL: mask_uitofp_4i64_4f32:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; X86-SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; X86-SSE-NEXT: andps {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: cvtdq2ps %xmm0, %xmm0 ; X86-SSE-NEXT: cvtdq2ps %xmm0, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X86-AVX-LABEL: mask_uitofp_4i64_4f32: ; X86-AVX-LABEL: mask_uitofp_4i64_4f32:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vextractf128 $1, %ymm0, %xmm1 ; X86-AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; X86-AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; X86-AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; X86-AVX-NEXT: vandps {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vcvtdq2ps %xmm0, %xmm0 ; X86-AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
; X86-AVX-NEXT: vzeroupper ; X86-AVX-NEXT: vzeroupper
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X86-AVX512F-LABEL: mask_uitofp_4i64_4f32: ; X86-AVX512F-LABEL: mask_uitofp_4i64_4f32:
; X86-AVX512F: # %bb.0: ; X86-AVX512F: # %bb.0:
; X86-AVX512F-NEXT: vpmovqd %ymm0, %xmm0 ; X86-AVX512F-NEXT: vpmovqd %ymm0, %xmm0
; X86-AVX512F-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX512F-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX512F-NEXT: vcvtdq2ps %xmm0, %xmm0 ; X86-AVX512F-NEXT: vcvtdq2ps %xmm0, %xmm0
; X86-AVX512F-NEXT: vzeroupper ; X86-AVX512F-NEXT: vzeroupper
; X86-AVX512F-NEXT: retl ; X86-AVX512F-NEXT: retl
; ;
; X86-AVX512DQ-LABEL: mask_uitofp_4i64_4f32: ; X86-AVX512DQ-LABEL: mask_uitofp_4i64_4f32:
; X86-AVX512DQ: # %bb.0: ; X86-AVX512DQ: # %bb.0:
; X86-AVX512DQ-NEXT: vandps {{\.LCPI.*}}, %ymm0, %ymm0 ; X86-AVX512DQ-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-AVX512DQ-NEXT: vcvtqq2ps %ymm0, %xmm0 ; X86-AVX512DQ-NEXT: vcvtqq2ps %ymm0, %xmm0
; X86-AVX512DQ-NEXT: vzeroupper ; X86-AVX512DQ-NEXT: vzeroupper
; X86-AVX512DQ-NEXT: retl ; X86-AVX512DQ-NEXT: retl
; ;
; X64-SSE-LABEL: mask_uitofp_4i64_4f32: ; X64-SSE-LABEL: mask_uitofp_4i64_4f32:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; X64-SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; X64-SSE-NEXT: andps {{.*}}(%rip), %xmm0 ; X64-SSE-NEXT: andps {{.*}}(%rip), %xmm0
Show All 39 Lines
; X86-SSE-NEXT: pcmpgtd %xmm3, %xmm4 ; X86-SSE-NEXT: pcmpgtd %xmm3, %xmm4
; X86-SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2] ; X86-SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
; X86-SSE-NEXT: pcmpeqd %xmm3, %xmm2 ; X86-SSE-NEXT: pcmpeqd %xmm3, %xmm2
; X86-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3] ; X86-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
; X86-SSE-NEXT: pand %xmm5, %xmm2 ; X86-SSE-NEXT: pand %xmm5, %xmm2
; X86-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3] ; X86-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
; X86-SSE-NEXT: por %xmm2, %xmm3 ; X86-SSE-NEXT: por %xmm2, %xmm3
; X86-SSE-NEXT: pand %xmm3, %xmm0 ; X86-SSE-NEXT: pand %xmm3, %xmm0
; X86-SSE-NEXT: pandn {{\.LCPI.*}}, %xmm3 ; X86-SSE-NEXT: pandn {{\.LCPI[0-9]+_[0-9]+}}, %xmm3
; X86-SSE-NEXT: por %xmm0, %xmm3 ; X86-SSE-NEXT: por %xmm0, %xmm3
; X86-SSE-NEXT: pxor %xmm3, %xmm1 ; X86-SSE-NEXT: pxor %xmm3, %xmm1
; X86-SSE-NEXT: movdqa {{.*#+}} xmm0 = [2147483903,0,2147483903,0] ; X86-SSE-NEXT: movdqa {{.*#+}} xmm0 = [2147483903,0,2147483903,0]
; X86-SSE-NEXT: movdqa %xmm0, %xmm2 ; X86-SSE-NEXT: movdqa %xmm0, %xmm2
; X86-SSE-NEXT: pcmpgtd %xmm1, %xmm2 ; X86-SSE-NEXT: pcmpgtd %xmm1, %xmm2
; X86-SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm2[0,0,2,2] ; X86-SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm2[0,0,2,2]
; X86-SSE-NEXT: pcmpeqd %xmm0, %xmm1 ; X86-SSE-NEXT: pcmpeqd %xmm0, %xmm1
; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,3,3] ; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,1,3,3]
; X86-SSE-NEXT: pand %xmm4, %xmm0 ; X86-SSE-NEXT: pand %xmm4, %xmm0
; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3] ; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
; X86-SSE-NEXT: por %xmm0, %xmm1 ; X86-SSE-NEXT: por %xmm0, %xmm1
; X86-SSE-NEXT: pand %xmm1, %xmm3 ; X86-SSE-NEXT: pand %xmm1, %xmm3
; X86-SSE-NEXT: pandn {{\.LCPI.*}}, %xmm1 ; X86-SSE-NEXT: pandn {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE-NEXT: por %xmm3, %xmm1 ; X86-SSE-NEXT: por %xmm3, %xmm1
; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3] ; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,2,2,3]
; X86-SSE-NEXT: cvtdq2pd %xmm0, %xmm0 ; X86-SSE-NEXT: cvtdq2pd %xmm0, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X86-AVX-LABEL: clamp_sitofp_2i64_2f64: ; X86-AVX-LABEL: clamp_sitofp_2i64_2f64:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vmovddup {{.*#+}} xmm1 = [18446744073709551361,18446744073709551361] ; X86-AVX-NEXT: vmovddup {{.*#+}} xmm1 = [18446744073709551361,18446744073709551361]
; X86-AVX-NEXT: # xmm1 = mem[0,0] ; X86-AVX-NEXT: # xmm1 = mem[0,0]
; X86-AVX-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm2 ; X86-AVX-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm2
; X86-AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0 ; X86-AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
; X86-AVX-NEXT: vmovddup {{.*#+}} xmm1 = [255,255] ; X86-AVX-NEXT: vmovddup {{.*#+}} xmm1 = [255,255]
; X86-AVX-NEXT: # xmm1 = mem[0,0] ; X86-AVX-NEXT: # xmm1 = mem[0,0]
; X86-AVX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm2 ; X86-AVX-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm2
; X86-AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0 ; X86-AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
; X86-AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,2,3] ; X86-AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,2,3]
; X86-AVX-NEXT: vcvtdq2pd %xmm0, %xmm0 ; X86-AVX-NEXT: vcvtdq2pd %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X86-AVX512F-LABEL: clamp_sitofp_2i64_2f64: ; X86-AVX512F-LABEL: clamp_sitofp_2i64_2f64:
; X86-AVX512F: # %bb.0: ; X86-AVX512F: # %bb.0:
; X86-AVX512F-NEXT: vpmaxsq {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX512F-NEXT: vpmaxsq {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX512F-NEXT: vpminsq {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX512F-NEXT: vpminsq {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX512F-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; X86-AVX512F-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; X86-AVX512F-NEXT: vcvtdq2pd %xmm0, %xmm0 ; X86-AVX512F-NEXT: vcvtdq2pd %xmm0, %xmm0
; X86-AVX512F-NEXT: retl ; X86-AVX512F-NEXT: retl
; ;
; X86-AVX512DQ-LABEL: clamp_sitofp_2i64_2f64: ; X86-AVX512DQ-LABEL: clamp_sitofp_2i64_2f64:
; X86-AVX512DQ: # %bb.0: ; X86-AVX512DQ: # %bb.0:
; X86-AVX512DQ-NEXT: vpmaxsq {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX512DQ-NEXT: vpmaxsq {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX512DQ-NEXT: vpminsq {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX512DQ-NEXT: vpminsq {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX512DQ-NEXT: vcvtqq2pd %xmm0, %xmm0 ; X86-AVX512DQ-NEXT: vcvtqq2pd %xmm0, %xmm0
; X86-AVX512DQ-NEXT: retl ; X86-AVX512DQ-NEXT: retl
; ;
; X64-SSE-LABEL: clamp_sitofp_2i64_2f64: ; X64-SSE-LABEL: clamp_sitofp_2i64_2f64:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648] ; X64-SSE-NEXT: movdqa {{.*#+}} xmm1 = [2147483648,2147483648]
; X64-SSE-NEXT: movdqa %xmm0, %xmm2 ; X64-SSE-NEXT: movdqa %xmm0, %xmm2
; X64-SSE-NEXT: pxor %xmm1, %xmm2 ; X64-SSE-NEXT: pxor %xmm1, %xmm2
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llvm/test/CodeGen/X86/insert-into-constant-vector.ll

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; RUN: llc < %s -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=X64-AVX,X64-AVX512F ; RUN: llc < %s -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=X64-AVX,X64-AVX512F
define <16 x i8> @elt0_v16i8(i8 %x) { define <16 x i8> @elt0_v16i8(i8 %x) {
; X86-SSE2-LABEL: elt0_v16i8: ; X86-SSE2-LABEL: elt0_v16i8:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X86-SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X86-SSE2-NEXT: movaps {{.*#+}} xmm0 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; X86-SSE2-NEXT: movaps {{.*#+}} xmm0 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; X86-SSE2-NEXT: andnps %xmm1, %xmm0 ; X86-SSE2-NEXT: andnps %xmm1, %xmm0
; X86-SSE2-NEXT: orps {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: orps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X64-SSE2-LABEL: elt0_v16i8: ; X64-SSE2-LABEL: elt0_v16i8:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: movd %edi, %xmm1 ; X64-SSE2-NEXT: movd %edi, %xmm1
; X64-SSE2-NEXT: movdqa {{.*#+}} xmm0 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255] ; X64-SSE2-NEXT: movdqa {{.*#+}} xmm0 = [0,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
; X64-SSE2-NEXT: pandn %xmm1, %xmm0 ; X64-SSE2-NEXT: pandn %xmm1, %xmm0
; X64-SSE2-NEXT: por {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: por {{.*}}(%rip), %xmm0
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; X64-SSE4-NEXT: movaps {{.*#+}} xmm3 = [6,7] ; X64-SSE4-NEXT: movaps {{.*#+}} xmm3 = [6,7]
; X64-SSE4-NEXT: retq ; X64-SSE4-NEXT: retq
; ;
; X86-AVX1-LABEL: elt5_v8i64: ; X86-AVX1-LABEL: elt5_v8i64:
; X86-AVX1: # %bb.0: ; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; X86-AVX1-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; X86-AVX1-NEXT: vmovaps {{.*#+}} xmm1 = [4,0,0,0] ; X86-AVX1-NEXT: vmovaps {{.*#+}} xmm1 = [4,0,0,0]
; X86-AVX1-NEXT: vmovlhps {{.*#+}} xmm0 = xmm1[0],xmm0[0] ; X86-AVX1-NEXT: vmovlhps {{.*#+}} xmm0 = xmm1[0],xmm0[0]
; X86-AVX1-NEXT: vinsertf128 $1, {{\.LCPI.*}}, %ymm0, %ymm1 ; X86-AVX1-NEXT: vinsertf128 $1, {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm1
; X86-AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [42,0,1,0,2,0,3,0] ; X86-AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [42,0,1,0,2,0,3,0]
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X64-AVX1-LABEL: elt5_v8i64: ; X64-AVX1-LABEL: elt5_v8i64:
; X64-AVX1: # %bb.0: ; X64-AVX1: # %bb.0:
; X64-AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = <4,u,6,7> ; X64-AVX1-NEXT: vmovdqa {{.*#+}} xmm0 = <4,u,6,7>
; X64-AVX1-NEXT: vpinsrq $1, %rdi, %xmm0, %xmm0 ; X64-AVX1-NEXT: vpinsrq $1, %rdi, %xmm0, %xmm0
; X64-AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm0[0,1,2,3],mem[4,5,6,7] ; X64-AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm0[0,1,2,3],mem[4,5,6,7]
; X64-AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [42,1,2,3] ; X64-AVX1-NEXT: vmovaps {{.*#+}} ymm0 = [42,1,2,3]
; X64-AVX1-NEXT: retq ; X64-AVX1-NEXT: retq
; ;
; X86-AVX2-LABEL: elt5_v8i64: ; X86-AVX2-LABEL: elt5_v8i64:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; X86-AVX2-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; X86-AVX2-NEXT: vmovaps {{.*#+}} xmm1 = [4,0,0,0] ; X86-AVX2-NEXT: vmovaps {{.*#+}} xmm1 = [4,0,0,0]
; X86-AVX2-NEXT: vmovlhps {{.*#+}} xmm0 = xmm1[0],xmm0[0] ; X86-AVX2-NEXT: vmovlhps {{.*#+}} xmm0 = xmm1[0],xmm0[0]
; X86-AVX2-NEXT: vinsertf128 $1, {{\.LCPI.*}}, %ymm0, %ymm1 ; X86-AVX2-NEXT: vinsertf128 $1, {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm1
; X86-AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [42,0,1,0,2,0,3,0] ; X86-AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [42,0,1,0,2,0,3,0]
; X86-AVX2-NEXT: retl ; X86-AVX2-NEXT: retl
; ;
; X64-AVX2-LABEL: elt5_v8i64: ; X64-AVX2-LABEL: elt5_v8i64:
; X64-AVX2: # %bb.0: ; X64-AVX2: # %bb.0:
; X64-AVX2-NEXT: vmovdqa {{.*#+}} xmm0 = <4,u,6,7> ; X64-AVX2-NEXT: vmovdqa {{.*#+}} xmm0 = <4,u,6,7>
; X64-AVX2-NEXT: vpinsrq $1, %rdi, %xmm0, %xmm0 ; X64-AVX2-NEXT: vpinsrq $1, %rdi, %xmm0, %xmm0
; X64-AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],mem[4,5,6,7] ; X64-AVX2-NEXT: vpblendd {{.*#+}} ymm1 = ymm0[0,1,2,3],mem[4,5,6,7]
; X64-AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [42,1,2,3] ; X64-AVX2-NEXT: vmovaps {{.*#+}} ymm0 = [42,1,2,3]
; X64-AVX2-NEXT: retq ; X64-AVX2-NEXT: retq
; ;
; X86-AVX512F-LABEL: elt5_v8i64: ; X86-AVX512F-LABEL: elt5_v8i64:
; X86-AVX512F: # %bb.0: ; X86-AVX512F: # %bb.0:
; X86-AVX512F-NEXT: vmovaps {{.*#+}} ymm0 = [42,0,1,0,2,0,3,0] ; X86-AVX512F-NEXT: vmovaps {{.*#+}} ymm0 = [42,0,1,0,2,0,3,0]
; X86-AVX512F-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero ; X86-AVX512F-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; X86-AVX512F-NEXT: vmovaps {{.*#+}} xmm2 = [4,0,0,0] ; X86-AVX512F-NEXT: vmovaps {{.*#+}} xmm2 = [4,0,0,0]
; X86-AVX512F-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0] ; X86-AVX512F-NEXT: vmovlhps {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; X86-AVX512F-NEXT: vinsertf128 $1, {{\.LCPI.*}}, %ymm1, %ymm1 ; X86-AVX512F-NEXT: vinsertf128 $1, {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm1
; X86-AVX512F-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0 ; X86-AVX512F-NEXT: vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
; X86-AVX512F-NEXT: retl ; X86-AVX512F-NEXT: retl
; ;
; X64-AVX512F-LABEL: elt5_v8i64: ; X64-AVX512F-LABEL: elt5_v8i64:
; X64-AVX512F: # %bb.0: ; X64-AVX512F: # %bb.0:
; X64-AVX512F-NEXT: vmovq %rdi, %xmm1 ; X64-AVX512F-NEXT: vmovq %rdi, %xmm1
; X64-AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm2 = [0,1,2,3,4,8,6,7] ; X64-AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm2 = [0,1,2,3,4,8,6,7]
; X64-AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm0 = <42,1,2,3,4,u,6,7> ; X64-AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm0 = <42,1,2,3,4,u,6,7>
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llvm/test/CodeGen/X86/insertelement-var-index.ll

Show First 20 Lines • Show All 1,374 Lines • ▼ Show 20 Lines
; ;
; AVX1-LABEL: arg_f32_v8f32: ; AVX1-LABEL: arg_f32_v8f32:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[0,0,0,0] ; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[0,0,0,0]
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1
; AVX1-NEXT: vmovd %edi, %xmm2 ; AVX1-NEXT: vmovd %edi, %xmm2
; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,0,0,0] ; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,0,0,0]
; AVX1-NEXT: vpcmpeqd {{.*}}(%rip), %xmm2, %xmm3 ; AVX1-NEXT: vpcmpeqd {{.*}}(%rip), %xmm2, %xmm3
; AVX1-NEXT: vpcmpeqd {{\.LCPI.*}}+{{.*}}(%rip), %xmm2, %xmm2 ; AVX1-NEXT: vpcmpeqd {{\.LCPI[0-9]+_[0-9]+}}+{{.*}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2
; AVX1-NEXT: vblendvps %ymm2, %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vblendvps %ymm2, %ymm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: arg_f32_v8f32: ; AVX2-LABEL: arg_f32_v8f32:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vbroadcastss %xmm1, %ymm1 ; AVX2-NEXT: vbroadcastss %xmm1, %ymm1
; AVX2-NEXT: vmovd %edi, %xmm2 ; AVX2-NEXT: vmovd %edi, %xmm2
Show All 27 Lines
; AVX1-LABEL: arg_f64_v4f64: ; AVX1-LABEL: arg_f64_v4f64:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vmovddup {{.*#+}} xmm1 = xmm1[0,0] ; AVX1-NEXT: vmovddup {{.*#+}} xmm1 = xmm1[0,0]
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm1, %ymm1
; AVX1-NEXT: movslq %edi, %rax ; AVX1-NEXT: movslq %edi, %rax
; AVX1-NEXT: vmovq %rax, %xmm2 ; AVX1-NEXT: vmovq %rax, %xmm2
; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,1,0,1] ; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,1,0,1]
; AVX1-NEXT: vpcmpeqq {{.*}}(%rip), %xmm2, %xmm3 ; AVX1-NEXT: vpcmpeqq {{.*}}(%rip), %xmm2, %xmm3
; AVX1-NEXT: vpcmpeqq {{\.LCPI.*}}+{{.*}}(%rip), %xmm2, %xmm2 ; AVX1-NEXT: vpcmpeqq {{\.LCPI[0-9]+_[0-9]+}}+{{.*}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2 ; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2
; AVX1-NEXT: vblendvpd %ymm2, %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vblendvpd %ymm2, %ymm1, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: arg_f64_v4f64: ; AVX2-LABEL: arg_f64_v4f64:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vbroadcastsd %xmm1, %ymm1 ; AVX2-NEXT: vbroadcastsd %xmm1, %ymm1
; AVX2-NEXT: movslq %edi, %rax ; AVX2-NEXT: movslq %edi, %rax
▲ Show 20 Lines • Show All 220 Lines • ▼ Show 20 Lines
; SSE-NEXT: movaps -{{[0-9]+}}(%rsp), %xmm1 ; SSE-NEXT: movaps -{{[0-9]+}}(%rsp), %xmm1
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: load_f32_v8f32: ; AVX1-LABEL: load_f32_v8f32:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vmovd %esi, %xmm1 ; AVX1-NEXT: vmovd %esi, %xmm1
; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,0,0] ; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
; AVX1-NEXT: vpcmpeqd {{.*}}(%rip), %xmm1, %xmm2 ; AVX1-NEXT: vpcmpeqd {{.*}}(%rip), %xmm1, %xmm2
; AVX1-NEXT: vpcmpeqd {{\.LCPI.*}}+{{.*}}(%rip), %xmm1, %xmm1 ; AVX1-NEXT: vpcmpeqd {{\.LCPI[0-9]+_[0-9]+}}+{{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
; AVX1-NEXT: vbroadcastss (%rdi), %ymm2 ; AVX1-NEXT: vbroadcastss (%rdi), %ymm2
; AVX1-NEXT: vblendvps %ymm1, %ymm2, %ymm0, %ymm0 ; AVX1-NEXT: vblendvps %ymm1, %ymm2, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: load_f32_v8f32: ; AVX2-LABEL: load_f32_v8f32:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vbroadcastss (%rdi), %ymm1 ; AVX2-NEXT: vbroadcastss (%rdi), %ymm1
Show All 28 Lines
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: load_f64_v4f64: ; AVX1-LABEL: load_f64_v4f64:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: movslq %esi, %rax ; AVX1-NEXT: movslq %esi, %rax
; AVX1-NEXT: vmovq %rax, %xmm1 ; AVX1-NEXT: vmovq %rax, %xmm1
; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,1] ; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
; AVX1-NEXT: vpcmpeqq {{.*}}(%rip), %xmm1, %xmm2 ; AVX1-NEXT: vpcmpeqq {{.*}}(%rip), %xmm1, %xmm2
; AVX1-NEXT: vpcmpeqq {{\.LCPI.*}}+{{.*}}(%rip), %xmm1, %xmm1 ; AVX1-NEXT: vpcmpeqq {{\.LCPI[0-9]+_[0-9]+}}+{{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
; AVX1-NEXT: vbroadcastsd (%rdi), %ymm2 ; AVX1-NEXT: vbroadcastsd (%rdi), %ymm2
; AVX1-NEXT: vblendvpd %ymm1, %ymm2, %ymm0, %ymm0 ; AVX1-NEXT: vblendvpd %ymm1, %ymm2, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: load_f64_v4f64: ; AVX2-LABEL: load_f64_v4f64:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vbroadcastsd (%rdi), %ymm1 ; AVX2-NEXT: vbroadcastsd (%rdi), %ymm1
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llvm/test/CodeGen/X86/known-bits-vector.ll

Show First 20 Lines • Show All 68 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%5 = shufflevector <4 x i32> %4, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2> %5 = shufflevector <4 x i32> %4, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
%6 = uitofp <4 x i32> %5 to <4 x float> %6 = uitofp <4 x i32> %5 to <4 x float>
ret <4 x float> %6 ret <4 x float> %6
} }
define <4 x i32> @knownbits_mask_shuffle_sext(<8 x i16> %a0) nounwind { define <4 x i32> @knownbits_mask_shuffle_sext(<8 x i16> %a0) nounwind {
; X32-LABEL: knownbits_mask_shuffle_sext: ; X32-LABEL: knownbits_mask_shuffle_sext:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X32-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] ; X32-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: knownbits_mask_shuffle_sext: ; X64-LABEL: knownbits_mask_shuffle_sext:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] ; X64-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; X64-NEXT: retq ; X64-NEXT: retq
%1 = and <8 x i16> %a0, <i16 -1, i16 -1, i16 -1, i16 -1, i16 15, i16 15, i16 15, i16 15> %1 = and <8 x i16> %a0, <i16 -1, i16 -1, i16 -1, i16 -1, i16 15, i16 15, i16 15, i16 15>
%2 = shufflevector <8 x i16> %1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%3 = sext <4 x i16> %2 to <4 x i32> %3 = sext <4 x i16> %2 to <4 x i32>
ret <4 x i32> %3 ret <4 x i32> %3
} }
define <4 x i32> @knownbits_mask_shuffle_shuffle_sext(<8 x i16> %a0) nounwind { define <4 x i32> @knownbits_mask_shuffle_shuffle_sext(<8 x i16> %a0) nounwind {
; X32-LABEL: knownbits_mask_shuffle_shuffle_sext: ; X32-LABEL: knownbits_mask_shuffle_shuffle_sext:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; X32-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X32-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] ; X32-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: knownbits_mask_shuffle_shuffle_sext: ; X64-LABEL: knownbits_mask_shuffle_shuffle_sext:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] ; X64-NEXT: vpunpckhwd {{.*#+}} xmm0 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; X64-NEXT: retq ; X64-NEXT: retq
%1 = and <8 x i16> %a0, <i16 -1, i16 -1, i16 -1, i16 -1, i16 15, i16 15, i16 15, i16 15> %1 = and <8 x i16> %a0, <i16 -1, i16 -1, i16 -1, i16 -1, i16 15, i16 15, i16 15, i16 15>
%2 = shufflevector <8 x i16> %1, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef> %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
%3 = shufflevector <8 x i16> %2, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %3 = shufflevector <8 x i16> %2, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%4 = sext <4 x i16> %3 to <4 x i32> %4 = sext <4 x i16> %3 to <4 x i32>
ret <4 x i32> %4 ret <4 x i32> %4
} }
define <4 x i32> @knownbits_mask_shuffle_shuffle_undef_sext(<8 x i16> %a0) nounwind { define <4 x i32> @knownbits_mask_shuffle_shuffle_undef_sext(<8 x i16> %a0) nounwind {
; X32-LABEL: knownbits_mask_shuffle_shuffle_undef_sext: ; X32-LABEL: knownbits_mask_shuffle_shuffle_undef_sext:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3] ; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
; X32-NEXT: vpmovsxwd %xmm0, %xmm0 ; X32-NEXT: vpmovsxwd %xmm0, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: knownbits_mask_shuffle_shuffle_undef_sext: ; X64-LABEL: knownbits_mask_shuffle_shuffle_undef_sext:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3] ; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
; X64-NEXT: vpmovsxwd %xmm0, %xmm0 ; X64-NEXT: vpmovsxwd %xmm0, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = and <8 x i16> %a0, <i16 -1, i16 -1, i16 -1, i16 -1, i16 15, i16 15, i16 15, i16 15> %1 = and <8 x i16> %a0, <i16 -1, i16 -1, i16 -1, i16 -1, i16 15, i16 15, i16 15, i16 15>
%2 = shufflevector <8 x i16> %1, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%3 = shufflevector <8 x i16> %2, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %3 = shufflevector <8 x i16> %2, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%4 = sext <4 x i16> %3 to <4 x i32> %4 = sext <4 x i16> %3 to <4 x i32>
ret <4 x i32> %4 ret <4 x i32> %4
} }
define <4 x float> @knownbits_mask_shuffle_uitofp(<4 x i32> %a0) nounwind { define <4 x float> @knownbits_mask_shuffle_uitofp(<4 x i32> %a0) nounwind {
; X32-LABEL: knownbits_mask_shuffle_uitofp: ; X32-LABEL: knownbits_mask_shuffle_uitofp:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: vandps {{\.LCPI.*}}, %xmm0, %xmm0 ; X32-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3] ; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3]
; X32-NEXT: vcvtdq2ps %xmm0, %xmm0 ; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: knownbits_mask_shuffle_uitofp: ; X64-LABEL: knownbits_mask_shuffle_uitofp:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 ; X64-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
; X64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3] ; X64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3]
Show All 20 Lines; X64-NEXT: retq
%3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 2, i32 2, i32 3, i32 3> %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 2, i32 2, i32 3, i32 3>
%4 = uitofp <4 x i32> %3 to <4 x float> %4 = uitofp <4 x i32> %3 to <4 x float>
ret <4 x float> %4 ret <4 x float> %4
} }
define <4 x float> @knownbits_mask_xor_shuffle_uitofp(<4 x i32> %a0) nounwind { define <4 x float> @knownbits_mask_xor_shuffle_uitofp(<4 x i32> %a0) nounwind {
; X32-LABEL: knownbits_mask_xor_shuffle_uitofp: ; X32-LABEL: knownbits_mask_xor_shuffle_uitofp:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: vandps {{\.LCPI.*}}, %xmm0, %xmm0 ; X32-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32-NEXT: vxorps {{\.LCPI.*}}, %xmm0, %xmm0 ; X32-NEXT: vxorps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3] ; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[2,2,3,3]
; X32-NEXT: vcvtdq2ps %xmm0, %xmm0 ; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: knownbits_mask_xor_shuffle_uitofp: ; X64-LABEL: knownbits_mask_xor_shuffle_uitofp:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 ; X64-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
; X64-NEXT: vxorps {{.*}}(%rip), %xmm0, %xmm0 ; X64-NEXT: vxorps {{.*}}(%rip), %xmm0, %xmm0
▲ Show 20 Lines • Show All 193 Lines • ▼ Show 20 Lines; X64-NEXT: retq
%4 = shl <4 x i32> %3, <i32 22, i32 22, i32 22, i32 22> %4 = shl <4 x i32> %3, <i32 22, i32 22, i32 22, i32 22>
ret <4 x i32> %4 ret <4 x i32> %4
} }
declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>) declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>)
define <8 x float> @knownbits_mask_concat_uitofp(<4 x i32> %a0, <4 x i32> %a1) nounwind { define <8 x float> @knownbits_mask_concat_uitofp(<4 x i32> %a0, <4 x i32> %a1) nounwind {
; X32-LABEL: knownbits_mask_concat_uitofp: ; X32-LABEL: knownbits_mask_concat_uitofp:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: vandps {{\.LCPI.*}}, %xmm0, %xmm0 ; X32-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32-NEXT: vandps {{\.LCPI.*}}, %xmm1, %xmm1 ; X32-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1
; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,0,2] ; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,0,2]
; X32-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[1,3,1,3] ; X32-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[1,3,1,3]
; X32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; X32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X32-NEXT: vcvtdq2ps %ymm0, %ymm0 ; X32-NEXT: vcvtdq2ps %ymm0, %ymm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: knownbits_mask_concat_uitofp: ; X64-LABEL: knownbits_mask_concat_uitofp:
; X64: # %bb.0: ; X64: # %bb.0:
Show All 30 Lines; X64-NEXT: retq
%3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 3, i32 3> %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
%4 = uitofp <4 x i32> %3 to <4 x float> %4 = uitofp <4 x i32> %3 to <4 x float>
ret <4 x float> %4 ret <4 x float> %4
} }
define <4 x float> @knownbits_smax_smin_shuffle_uitofp(<4 x i32> %a0) { define <4 x float> @knownbits_smax_smin_shuffle_uitofp(<4 x i32> %a0) {
; X32-LABEL: knownbits_smax_smin_shuffle_uitofp: ; X32-LABEL: knownbits_smax_smin_shuffle_uitofp:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: vpminsd {{\.LCPI.*}}, %xmm0, %xmm0 ; X32-NEXT: vpminsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32-NEXT: vpmaxsd {{\.LCPI.*}}, %xmm0, %xmm0 ; X32-NEXT: vpmaxsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3] ; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3]
; X32-NEXT: vcvtdq2ps %xmm0, %xmm0 ; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: knownbits_smax_smin_shuffle_uitofp: ; X64-LABEL: knownbits_smax_smin_shuffle_uitofp:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpminsd {{.*}}(%rip), %xmm0, %xmm0 ; X64-NEXT: vpminsd {{.*}}(%rip), %xmm0, %xmm0
; X64-NEXT: vpmaxsd {{.*}}(%rip), %xmm0, %xmm0 ; X64-NEXT: vpmaxsd {{.*}}(%rip), %xmm0, %xmm0
; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3] ; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3]
; X64-NEXT: vcvtdq2ps %xmm0, %xmm0 ; X64-NEXT: vcvtdq2ps %xmm0, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %a0, <4 x i32> <i32 0, i32 -65535, i32 -65535, i32 0>) %1 = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %a0, <4 x i32> <i32 0, i32 -65535, i32 -65535, i32 0>)
%2 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %1, <4 x i32> <i32 65535, i32 -1, i32 -1, i32 131071>) %2 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %1, <4 x i32> <i32 65535, i32 -1, i32 -1, i32 131071>)
%3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3> %3 = shufflevector <4 x i32> %2, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3>
%4 = uitofp <4 x i32> %3 to <4 x float> %4 = uitofp <4 x i32> %3 to <4 x float>
ret <4 x float> %4 ret <4 x float> %4
} }
declare <4 x i32> @llvm.smin.v4i32(<4 x i32>, <4 x i32>) nounwind readnone declare <4 x i32> @llvm.smin.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
declare <4 x i32> @llvm.smax.v4i32(<4 x i32>, <4 x i32>) nounwind readnone declare <4 x i32> @llvm.smax.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
define <4 x float> @knownbits_umin_shuffle_uitofp(<4 x i32> %a0) { define <4 x float> @knownbits_umin_shuffle_uitofp(<4 x i32> %a0) {
; X32-LABEL: knownbits_umin_shuffle_uitofp: ; X32-LABEL: knownbits_umin_shuffle_uitofp:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: vpminud {{\.LCPI.*}}, %xmm0, %xmm0 ; X32-NEXT: vpminud {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3] ; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3]
; X32-NEXT: vcvtdq2ps %xmm0, %xmm0 ; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: knownbits_umin_shuffle_uitofp: ; X64-LABEL: knownbits_umin_shuffle_uitofp:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm0 ; X64-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm0
; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3] ; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3]
Show All 21 Lines; X64-NEXT: retq
%3 = ashr <4 x i32> %2, <i32 31, i32 31, i32 31, i32 31> %3 = ashr <4 x i32> %2, <i32 31, i32 31, i32 31, i32 31>
ret <4 x i32> %3 ret <4 x i32> %3
} }
declare <4 x i32> @llvm.umax.v4i32(<4 x i32>, <4 x i32>) nounwind readnone declare <4 x i32> @llvm.umax.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
define <4 x float> @knownbits_mask_umax_shuffle_uitofp(<4 x i32> %a0) { define <4 x float> @knownbits_mask_umax_shuffle_uitofp(<4 x i32> %a0) {
; X32-LABEL: knownbits_mask_umax_shuffle_uitofp: ; X32-LABEL: knownbits_mask_umax_shuffle_uitofp:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32-NEXT: vpmaxud {{\.LCPI.*}}, %xmm0, %xmm0 ; X32-NEXT: vpmaxud {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3] ; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,3,3]
; X32-NEXT: vcvtdq2ps %xmm0, %xmm0 ; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: knownbits_mask_umax_shuffle_uitofp: ; X64-LABEL: knownbits_mask_umax_shuffle_uitofp:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm0 ; X64-NEXT: vpmaxud {{.*}}(%rip), %xmm0, %xmm0
Show All 27 Lines
; If we don't know that the input isn't INT_MIN we can't combine to sitofp ; If we don't know that the input isn't INT_MIN we can't combine to sitofp
define <4 x float> @knownbits_abs_uitofp(<4 x i32> %a0) { define <4 x float> @knownbits_abs_uitofp(<4 x i32> %a0) {
; X32-LABEL: knownbits_abs_uitofp: ; X32-LABEL: knownbits_abs_uitofp:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: vpabsd %xmm0, %xmm0 ; X32-NEXT: vpabsd %xmm0, %xmm0
; X32-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7] ; X32-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
; X32-NEXT: vpsrld $16, %xmm0, %xmm0 ; X32-NEXT: vpsrld $16, %xmm0, %xmm0
; X32-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7] ; X32-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
; X32-NEXT: vsubps {{\.LCPI.*}}, %xmm0, %xmm0 ; X32-NEXT: vsubps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32-NEXT: vaddps %xmm0, %xmm1, %xmm0 ; X32-NEXT: vaddps %xmm0, %xmm1, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: knownbits_abs_uitofp: ; X64-LABEL: knownbits_abs_uitofp:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpabsd %xmm0, %xmm0 ; X64-NEXT: vpabsd %xmm0, %xmm0
; X64-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7] ; X64-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
; X64-NEXT: vpsrld $16, %xmm0, %xmm0 ; X64-NEXT: vpsrld $16, %xmm0, %xmm0
; X64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7] ; X64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
; X64-NEXT: vsubps {{.*}}(%rip), %xmm0, %xmm0 ; X64-NEXT: vsubps {{.*}}(%rip), %xmm0, %xmm0
; X64-NEXT: vaddps %xmm0, %xmm1, %xmm0 ; X64-NEXT: vaddps %xmm0, %xmm1, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = sub <4 x i32> zeroinitializer, %a0 %1 = sub <4 x i32> zeroinitializer, %a0
%2 = icmp slt <4 x i32> %a0, zeroinitializer %2 = icmp slt <4 x i32> %a0, zeroinitializer
%3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> %a0 %3 = select <4 x i1> %2, <4 x i32> %1, <4 x i32> %a0
%4 = uitofp <4 x i32> %3 to <4 x float> %4 = uitofp <4 x i32> %3 to <4 x float>
ret <4 x float> %4 ret <4 x float> %4
} }
define <4 x float> @knownbits_or_abs_uitofp(<4 x i32> %a0) { define <4 x float> @knownbits_or_abs_uitofp(<4 x i32> %a0) {
; X32-LABEL: knownbits_or_abs_uitofp: ; X32-LABEL: knownbits_or_abs_uitofp:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: vpor {{\.LCPI.*}}, %xmm0, %xmm0 ; X32-NEXT: vpor {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,0,2] ; X32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,0,2]
; X32-NEXT: vpabsd %xmm0, %xmm0 ; X32-NEXT: vpabsd %xmm0, %xmm0
; X32-NEXT: vcvtdq2ps %xmm0, %xmm0 ; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: knownbits_or_abs_uitofp: ; X64-LABEL: knownbits_or_abs_uitofp:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0 ; X64-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
Show All 13 Lines
define <4 x float> @knownbits_and_select_shuffle_uitofp(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2, <4 x i32> %a3) nounwind { define <4 x float> @knownbits_and_select_shuffle_uitofp(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2, <4 x i32> %a3) nounwind {
; X32-LABEL: knownbits_and_select_shuffle_uitofp: ; X32-LABEL: knownbits_and_select_shuffle_uitofp:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: pushl %ebp ; X32-NEXT: pushl %ebp
; X32-NEXT: movl %esp, %ebp ; X32-NEXT: movl %esp, %ebp
; X32-NEXT: andl $-16, %esp ; X32-NEXT: andl $-16, %esp
; X32-NEXT: subl $16, %esp ; X32-NEXT: subl $16, %esp
; X32-NEXT: vmovaps 8(%ebp), %xmm3 ; X32-NEXT: vmovaps 8(%ebp), %xmm3
; X32-NEXT: vandps {{\.LCPI.*}}, %xmm2, %xmm2 ; X32-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm2, %xmm2
; X32-NEXT: vandps {{\.LCPI.*}}, %xmm3, %xmm3 ; X32-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm3, %xmm3
; X32-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 ; X32-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; X32-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0 ; X32-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,2,2] ; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,2,2]
; X32-NEXT: vcvtdq2ps %xmm0, %xmm0 ; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
; X32-NEXT: movl %ebp, %esp ; X32-NEXT: movl %ebp, %esp
; X32-NEXT: popl %ebp ; X32-NEXT: popl %ebp
; X32-NEXT: retl ; X32-NEXT: retl
; ;
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; X32-LABEL: knownbits_lshr_and_select_shuffle_uitofp: ; X32-LABEL: knownbits_lshr_and_select_shuffle_uitofp:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: pushl %ebp ; X32-NEXT: pushl %ebp
; X32-NEXT: movl %esp, %ebp ; X32-NEXT: movl %esp, %ebp
; X32-NEXT: andl $-16, %esp ; X32-NEXT: andl $-16, %esp
; X32-NEXT: subl $16, %esp ; X32-NEXT: subl $16, %esp
; X32-NEXT: vmovaps 8(%ebp), %xmm3 ; X32-NEXT: vmovaps 8(%ebp), %xmm3
; X32-NEXT: vpsrld $5, %xmm2, %xmm2 ; X32-NEXT: vpsrld $5, %xmm2, %xmm2
; X32-NEXT: vandps {{\.LCPI.*}}, %xmm3, %xmm3 ; X32-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm3, %xmm3
; X32-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0 ; X32-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
; X32-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0 ; X32-NEXT: vblendvps %xmm0, %xmm2, %xmm3, %xmm0
; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,2,2] ; X32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,0,2,2]
; X32-NEXT: vcvtdq2ps %xmm0, %xmm0 ; X32-NEXT: vcvtdq2ps %xmm0, %xmm0
; X32-NEXT: movl %ebp, %esp ; X32-NEXT: movl %ebp, %esp
; X32-NEXT: popl %ebp ; X32-NEXT: popl %ebp
; X32-NEXT: retl ; X32-NEXT: retl
; ;
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llvm/test/CodeGen/X86/known-signbits-vector.ll

Show First 20 Lines • Show All 509 Lines • ▼ Show 20 Lines
define <4 x i32> @signbits_mask_ashr_smax(<4 x i32> %a0, <4 x i32> %a1) { define <4 x i32> @signbits_mask_ashr_smax(<4 x i32> %a0, <4 x i32> %a1) {
; X86-LABEL: signbits_mask_ashr_smax: ; X86-LABEL: signbits_mask_ashr_smax:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vpsrad $25, %xmm0, %xmm0 ; X86-NEXT: vpsrad $25, %xmm0, %xmm0
; X86-NEXT: vpsrad $25, %xmm1, %xmm1 ; X86-NEXT: vpsrad $25, %xmm1, %xmm1
; X86-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0 ; X86-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0] ; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; X86-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-AVX1-LABEL: signbits_mask_ashr_smax: ; X64-AVX1-LABEL: signbits_mask_ashr_smax:
; X64-AVX1: # %bb.0: ; X64-AVX1: # %bb.0:
; X64-AVX1-NEXT: vpsrad $25, %xmm0, %xmm0 ; X64-AVX1-NEXT: vpsrad $25, %xmm0, %xmm0
; X64-AVX1-NEXT: vpsrad $25, %xmm1, %xmm1 ; X64-AVX1-NEXT: vpsrad $25, %xmm1, %xmm1
; X64-AVX1-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0 ; X64-AVX1-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0] ; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
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define <4 x i32> @signbits_mask_ashr_smin(<4 x i32> %a0, <4 x i32> %a1) { define <4 x i32> @signbits_mask_ashr_smin(<4 x i32> %a0, <4 x i32> %a1) {
; X86-LABEL: signbits_mask_ashr_smin: ; X86-LABEL: signbits_mask_ashr_smin:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vpsrad $25, %xmm0, %xmm0 ; X86-NEXT: vpsrad $25, %xmm0, %xmm0
; X86-NEXT: vpsrad $25, %xmm1, %xmm1 ; X86-NEXT: vpsrad $25, %xmm1, %xmm1
; X86-NEXT: vpminsd %xmm1, %xmm0, %xmm0 ; X86-NEXT: vpminsd %xmm1, %xmm0, %xmm0
; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0] ; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; X86-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-AVX1-LABEL: signbits_mask_ashr_smin: ; X64-AVX1-LABEL: signbits_mask_ashr_smin:
; X64-AVX1: # %bb.0: ; X64-AVX1: # %bb.0:
; X64-AVX1-NEXT: vpsrad $25, %xmm0, %xmm0 ; X64-AVX1-NEXT: vpsrad $25, %xmm0, %xmm0
; X64-AVX1-NEXT: vpsrad $25, %xmm1, %xmm1 ; X64-AVX1-NEXT: vpsrad $25, %xmm1, %xmm1
; X64-AVX1-NEXT: vpminsd %xmm1, %xmm0, %xmm0 ; X64-AVX1-NEXT: vpminsd %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0] ; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
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define <4 x i32> @signbits_mask_ashr_umax(<4 x i32> %a0, <4 x i32> %a1) { define <4 x i32> @signbits_mask_ashr_umax(<4 x i32> %a0, <4 x i32> %a1) {
; X86-LABEL: signbits_mask_ashr_umax: ; X86-LABEL: signbits_mask_ashr_umax:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vpsrad $25, %xmm0, %xmm0 ; X86-NEXT: vpsrad $25, %xmm0, %xmm0
; X86-NEXT: vpsrad $25, %xmm1, %xmm1 ; X86-NEXT: vpsrad $25, %xmm1, %xmm1
; X86-NEXT: vpmaxud %xmm1, %xmm0, %xmm0 ; X86-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0] ; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; X86-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-AVX1-LABEL: signbits_mask_ashr_umax: ; X64-AVX1-LABEL: signbits_mask_ashr_umax:
; X64-AVX1: # %bb.0: ; X64-AVX1: # %bb.0:
; X64-AVX1-NEXT: vpsrad $25, %xmm0, %xmm0 ; X64-AVX1-NEXT: vpsrad $25, %xmm0, %xmm0
; X64-AVX1-NEXT: vpsrad $25, %xmm1, %xmm1 ; X64-AVX1-NEXT: vpsrad $25, %xmm1, %xmm1
; X64-AVX1-NEXT: vpmaxud %xmm1, %xmm0, %xmm0 ; X64-AVX1-NEXT: vpmaxud %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0] ; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
Show All 21 Lines
define <4 x i32> @signbits_mask_ashr_umin(<4 x i32> %a0, <4 x i32> %a1) { define <4 x i32> @signbits_mask_ashr_umin(<4 x i32> %a0, <4 x i32> %a1) {
; X86-LABEL: signbits_mask_ashr_umin: ; X86-LABEL: signbits_mask_ashr_umin:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vpsrad $25, %xmm0, %xmm0 ; X86-NEXT: vpsrad $25, %xmm0, %xmm0
; X86-NEXT: vpsrad $25, %xmm1, %xmm1 ; X86-NEXT: vpsrad $25, %xmm1, %xmm1
; X86-NEXT: vpminud %xmm1, %xmm0, %xmm0 ; X86-NEXT: vpminud %xmm1, %xmm0, %xmm0
; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0] ; X86-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; X86-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-AVX1-LABEL: signbits_mask_ashr_umin: ; X64-AVX1-LABEL: signbits_mask_ashr_umin:
; X64-AVX1: # %bb.0: ; X64-AVX1: # %bb.0:
; X64-AVX1-NEXT: vpsrad $25, %xmm0, %xmm0 ; X64-AVX1-NEXT: vpsrad $25, %xmm0, %xmm0
; X64-AVX1-NEXT: vpsrad $25, %xmm1, %xmm1 ; X64-AVX1-NEXT: vpsrad $25, %xmm1, %xmm1
; X64-AVX1-NEXT: vpminud %xmm1, %xmm0, %xmm0 ; X64-AVX1-NEXT: vpminud %xmm1, %xmm0, %xmm0
; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0] ; X64-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
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; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: vextractf128 $1, %ymm0, %xmm2 ; X86-NEXT: vextractf128 $1, %ymm0, %xmm2
; X86-NEXT: vpxor %xmm3, %xmm3, %xmm3 ; X86-NEXT: vpxor %xmm3, %xmm3, %xmm3
; X86-NEXT: vpcmpeqb %xmm3, %xmm2, %xmm2 ; X86-NEXT: vpcmpeqb %xmm3, %xmm2, %xmm2
; X86-NEXT: vpcmpeqb %xmm3, %xmm0, %xmm0 ; X86-NEXT: vpcmpeqb %xmm3, %xmm0, %xmm0
; X86-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; X86-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; X86-NEXT: vandnps %ymm1, %ymm0, %ymm1 ; X86-NEXT: vandnps %ymm1, %ymm0, %ymm1
; X86-NEXT: vandps {{\.LCPI.*}}, %ymm0, %ymm0 ; X86-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-NEXT: vorps %ymm1, %ymm0, %ymm0 ; X86-NEXT: vorps %ymm1, %ymm0, %ymm0
; X86-NEXT: vmovaps %ymm0, (%eax) ; X86-NEXT: vmovaps %ymm0, (%eax)
; X86-NEXT: vzeroupper ; X86-NEXT: vzeroupper
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-AVX1-LABEL: cross_bb_signbits_insert_subvec: ; X64-AVX1-LABEL: cross_bb_signbits_insert_subvec:
; X64-AVX1: # %bb.0: ; X64-AVX1: # %bb.0:
; X64-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; X64-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
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llvm/test/CodeGen/X86/limited-prec.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -limit-float-precision=6 -mtriple=i686-- | FileCheck %s --check-prefix=precision6 ; RUN: llc < %s -limit-float-precision=6 -mtriple=i686-- | FileCheck %s --check-prefix=precision6
; RUN: llc < %s -limit-float-precision=12 -mtriple=i686-- | FileCheck %s --check-prefix=precision12 ; RUN: llc < %s -limit-float-precision=12 -mtriple=i686-- | FileCheck %s --check-prefix=precision12
; RUN: llc < %s -limit-float-precision=18 -mtriple=i686-- | FileCheck %s --check-prefix=precision18 ; RUN: llc < %s -limit-float-precision=18 -mtriple=i686-- | FileCheck %s --check-prefix=precision18
define float @f1(float %x) nounwind noinline { define float @f1(float %x) nounwind noinline {
; precision6-LABEL: f1: ; precision6-LABEL: f1:
; precision6: # %bb.0: # %entry ; precision6: # %bb.0: # %entry
; precision6-NEXT: subl $20, %esp ; precision6-NEXT: subl $20, %esp
; precision6-NEXT: flds {{[0-9]+}}(%esp) ; precision6-NEXT: flds {{[0-9]+}}(%esp)
; precision6-NEXT: fmuls {{\.LCPI.*}} ; precision6-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fnstcw (%esp) ; precision6-NEXT: fnstcw (%esp)
; precision6-NEXT: movzwl (%esp), %eax ; precision6-NEXT: movzwl (%esp), %eax
; precision6-NEXT: orl $3072, %eax # imm = 0xC00 ; precision6-NEXT: orl $3072, %eax # imm = 0xC00
; precision6-NEXT: movw %ax, {{[0-9]+}}(%esp) ; precision6-NEXT: movw %ax, {{[0-9]+}}(%esp)
; precision6-NEXT: fldcw {{[0-9]+}}(%esp) ; precision6-NEXT: fldcw {{[0-9]+}}(%esp)
; precision6-NEXT: fistl {{[0-9]+}}(%esp) ; precision6-NEXT: fistl {{[0-9]+}}(%esp)
; precision6-NEXT: fldcw (%esp) ; precision6-NEXT: fldcw (%esp)
; precision6-NEXT: movl {{[0-9]+}}(%esp), %eax ; precision6-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp) ; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision6-NEXT: fisubl {{[0-9]+}}(%esp) ; precision6-NEXT: fisubl {{[0-9]+}}(%esp)
; precision6-NEXT: fld %st(0) ; precision6-NEXT: fld %st(0)
; precision6-NEXT: fmuls {{\.LCPI.*}} ; precision6-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fadds {{\.LCPI.*}} ; precision6-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fmulp %st, %st(1) ; precision6-NEXT: fmulp %st, %st(1)
; precision6-NEXT: fadds {{\.LCPI.*}} ; precision6-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fstps {{[0-9]+}}(%esp) ; precision6-NEXT: fstps {{[0-9]+}}(%esp)
; precision6-NEXT: shll $23, %eax ; precision6-NEXT: shll $23, %eax
; precision6-NEXT: addl {{[0-9]+}}(%esp), %eax ; precision6-NEXT: addl {{[0-9]+}}(%esp), %eax
; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp) ; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision6-NEXT: flds {{[0-9]+}}(%esp) ; precision6-NEXT: flds {{[0-9]+}}(%esp)
; precision6-NEXT: addl $20, %esp ; precision6-NEXT: addl $20, %esp
; precision6-NEXT: retl ; precision6-NEXT: retl
; ;
; precision12-LABEL: f1: ; precision12-LABEL: f1:
; precision12: # %bb.0: # %entry ; precision12: # %bb.0: # %entry
; precision12-NEXT: subl $20, %esp ; precision12-NEXT: subl $20, %esp
; precision12-NEXT: flds {{[0-9]+}}(%esp) ; precision12-NEXT: flds {{[0-9]+}}(%esp)
; precision12-NEXT: fmuls {{\.LCPI.*}} ; precision12-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fnstcw (%esp) ; precision12-NEXT: fnstcw (%esp)
; precision12-NEXT: movzwl (%esp), %eax ; precision12-NEXT: movzwl (%esp), %eax
; precision12-NEXT: orl $3072, %eax # imm = 0xC00 ; precision12-NEXT: orl $3072, %eax # imm = 0xC00
; precision12-NEXT: movw %ax, {{[0-9]+}}(%esp) ; precision12-NEXT: movw %ax, {{[0-9]+}}(%esp)
; precision12-NEXT: fldcw {{[0-9]+}}(%esp) ; precision12-NEXT: fldcw {{[0-9]+}}(%esp)
; precision12-NEXT: fistl {{[0-9]+}}(%esp) ; precision12-NEXT: fistl {{[0-9]+}}(%esp)
; precision12-NEXT: fldcw (%esp) ; precision12-NEXT: fldcw (%esp)
; precision12-NEXT: movl {{[0-9]+}}(%esp), %eax ; precision12-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp) ; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision12-NEXT: fisubl {{[0-9]+}}(%esp) ; precision12-NEXT: fisubl {{[0-9]+}}(%esp)
; precision12-NEXT: fld %st(0) ; precision12-NEXT: fld %st(0)
; precision12-NEXT: fmuls {{\.LCPI.*}} ; precision12-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fadds {{\.LCPI.*}} ; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fmul %st(1), %st ; precision12-NEXT: fmul %st(1), %st
; precision12-NEXT: fadds {{\.LCPI.*}} ; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fmulp %st, %st(1) ; precision12-NEXT: fmulp %st, %st(1)
; precision12-NEXT: fadds {{\.LCPI.*}} ; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fstps {{[0-9]+}}(%esp) ; precision12-NEXT: fstps {{[0-9]+}}(%esp)
; precision12-NEXT: shll $23, %eax ; precision12-NEXT: shll $23, %eax
; precision12-NEXT: addl {{[0-9]+}}(%esp), %eax ; precision12-NEXT: addl {{[0-9]+}}(%esp), %eax
; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp) ; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision12-NEXT: flds {{[0-9]+}}(%esp) ; precision12-NEXT: flds {{[0-9]+}}(%esp)
; precision12-NEXT: addl $20, %esp ; precision12-NEXT: addl $20, %esp
; precision12-NEXT: retl ; precision12-NEXT: retl
; ;
; precision18-LABEL: f1: ; precision18-LABEL: f1:
; precision18: # %bb.0: # %entry ; precision18: # %bb.0: # %entry
; precision18-NEXT: subl $20, %esp ; precision18-NEXT: subl $20, %esp
; precision18-NEXT: flds {{[0-9]+}}(%esp) ; precision18-NEXT: flds {{[0-9]+}}(%esp)
; precision18-NEXT: fmuls {{\.LCPI.*}} ; precision18-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fnstcw (%esp) ; precision18-NEXT: fnstcw (%esp)
; precision18-NEXT: movzwl (%esp), %eax ; precision18-NEXT: movzwl (%esp), %eax
; precision18-NEXT: orl $3072, %eax # imm = 0xC00 ; precision18-NEXT: orl $3072, %eax # imm = 0xC00
; precision18-NEXT: movw %ax, {{[0-9]+}}(%esp) ; precision18-NEXT: movw %ax, {{[0-9]+}}(%esp)
; precision18-NEXT: fldcw {{[0-9]+}}(%esp) ; precision18-NEXT: fldcw {{[0-9]+}}(%esp)
; precision18-NEXT: fistl {{[0-9]+}}(%esp) ; precision18-NEXT: fistl {{[0-9]+}}(%esp)
; precision18-NEXT: fldcw (%esp) ; precision18-NEXT: fldcw (%esp)
; precision18-NEXT: movl {{[0-9]+}}(%esp), %eax ; precision18-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp) ; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision18-NEXT: fisubl {{[0-9]+}}(%esp) ; precision18-NEXT: fisubl {{[0-9]+}}(%esp)
; precision18-NEXT: fld %st(0) ; precision18-NEXT: fld %st(0)
; precision18-NEXT: fmuls {{\.LCPI.*}} ; precision18-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fadds {{\.LCPI.*}} ; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st ; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}} ; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st ; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}} ; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st ; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}} ; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st ; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}} ; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmulp %st, %st(1) ; precision18-NEXT: fmulp %st, %st(1)
; precision18-NEXT: fld1 ; precision18-NEXT: fld1
; precision18-NEXT: faddp %st, %st(1) ; precision18-NEXT: faddp %st, %st(1)
; precision18-NEXT: fstps {{[0-9]+}}(%esp) ; precision18-NEXT: fstps {{[0-9]+}}(%esp)
; precision18-NEXT: shll $23, %eax ; precision18-NEXT: shll $23, %eax
; precision18-NEXT: addl {{[0-9]+}}(%esp), %eax ; precision18-NEXT: addl {{[0-9]+}}(%esp), %eax
; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp) ; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision18-NEXT: flds {{[0-9]+}}(%esp) ; precision18-NEXT: flds {{[0-9]+}}(%esp)
Show All 18 Lines
; precision6-NEXT: movw %ax, {{[0-9]+}}(%esp) ; precision6-NEXT: movw %ax, {{[0-9]+}}(%esp)
; precision6-NEXT: fldcw {{[0-9]+}}(%esp) ; precision6-NEXT: fldcw {{[0-9]+}}(%esp)
; precision6-NEXT: fistl {{[0-9]+}}(%esp) ; precision6-NEXT: fistl {{[0-9]+}}(%esp)
; precision6-NEXT: fldcw (%esp) ; precision6-NEXT: fldcw (%esp)
; precision6-NEXT: movl {{[0-9]+}}(%esp), %eax ; precision6-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp) ; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision6-NEXT: fisubl {{[0-9]+}}(%esp) ; precision6-NEXT: fisubl {{[0-9]+}}(%esp)
; precision6-NEXT: fld %st(0) ; precision6-NEXT: fld %st(0)
; precision6-NEXT: fmuls {{\.LCPI.*}} ; precision6-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fadds {{\.LCPI.*}} ; precision6-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fmulp %st, %st(1) ; precision6-NEXT: fmulp %st, %st(1)
; precision6-NEXT: fadds {{\.LCPI.*}} ; precision6-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fstps {{[0-9]+}}(%esp) ; precision6-NEXT: fstps {{[0-9]+}}(%esp)
; precision6-NEXT: shll $23, %eax ; precision6-NEXT: shll $23, %eax
; precision6-NEXT: addl {{[0-9]+}}(%esp), %eax ; precision6-NEXT: addl {{[0-9]+}}(%esp), %eax
; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp) ; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision6-NEXT: flds {{[0-9]+}}(%esp) ; precision6-NEXT: flds {{[0-9]+}}(%esp)
; precision6-NEXT: addl $20, %esp ; precision6-NEXT: addl $20, %esp
; precision6-NEXT: retl ; precision6-NEXT: retl
; ;
; precision12-LABEL: f2: ; precision12-LABEL: f2:
; precision12: # %bb.0: # %entry ; precision12: # %bb.0: # %entry
; precision12-NEXT: subl $20, %esp ; precision12-NEXT: subl $20, %esp
; precision12-NEXT: flds {{[0-9]+}}(%esp) ; precision12-NEXT: flds {{[0-9]+}}(%esp)
; precision12-NEXT: fnstcw (%esp) ; precision12-NEXT: fnstcw (%esp)
; precision12-NEXT: movzwl (%esp), %eax ; precision12-NEXT: movzwl (%esp), %eax
; precision12-NEXT: orl $3072, %eax # imm = 0xC00 ; precision12-NEXT: orl $3072, %eax # imm = 0xC00
; precision12-NEXT: movw %ax, {{[0-9]+}}(%esp) ; precision12-NEXT: movw %ax, {{[0-9]+}}(%esp)
; precision12-NEXT: fldcw {{[0-9]+}}(%esp) ; precision12-NEXT: fldcw {{[0-9]+}}(%esp)
; precision12-NEXT: fistl {{[0-9]+}}(%esp) ; precision12-NEXT: fistl {{[0-9]+}}(%esp)
; precision12-NEXT: fldcw (%esp) ; precision12-NEXT: fldcw (%esp)
; precision12-NEXT: movl {{[0-9]+}}(%esp), %eax ; precision12-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp) ; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision12-NEXT: fisubl {{[0-9]+}}(%esp) ; precision12-NEXT: fisubl {{[0-9]+}}(%esp)
; precision12-NEXT: fld %st(0) ; precision12-NEXT: fld %st(0)
; precision12-NEXT: fmuls {{\.LCPI.*}} ; precision12-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fadds {{\.LCPI.*}} ; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fmul %st(1), %st ; precision12-NEXT: fmul %st(1), %st
; precision12-NEXT: fadds {{\.LCPI.*}} ; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fmulp %st, %st(1) ; precision12-NEXT: fmulp %st, %st(1)
; precision12-NEXT: fadds {{\.LCPI.*}} ; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fstps {{[0-9]+}}(%esp) ; precision12-NEXT: fstps {{[0-9]+}}(%esp)
; precision12-NEXT: shll $23, %eax ; precision12-NEXT: shll $23, %eax
; precision12-NEXT: addl {{[0-9]+}}(%esp), %eax ; precision12-NEXT: addl {{[0-9]+}}(%esp), %eax
; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp) ; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision12-NEXT: flds {{[0-9]+}}(%esp) ; precision12-NEXT: flds {{[0-9]+}}(%esp)
; precision12-NEXT: addl $20, %esp ; precision12-NEXT: addl $20, %esp
; precision12-NEXT: retl ; precision12-NEXT: retl
; ;
; precision18-LABEL: f2: ; precision18-LABEL: f2:
; precision18: # %bb.0: # %entry ; precision18: # %bb.0: # %entry
; precision18-NEXT: subl $20, %esp ; precision18-NEXT: subl $20, %esp
; precision18-NEXT: flds {{[0-9]+}}(%esp) ; precision18-NEXT: flds {{[0-9]+}}(%esp)
; precision18-NEXT: fnstcw (%esp) ; precision18-NEXT: fnstcw (%esp)
; precision18-NEXT: movzwl (%esp), %eax ; precision18-NEXT: movzwl (%esp), %eax
; precision18-NEXT: orl $3072, %eax # imm = 0xC00 ; precision18-NEXT: orl $3072, %eax # imm = 0xC00
; precision18-NEXT: movw %ax, {{[0-9]+}}(%esp) ; precision18-NEXT: movw %ax, {{[0-9]+}}(%esp)
; precision18-NEXT: fldcw {{[0-9]+}}(%esp) ; precision18-NEXT: fldcw {{[0-9]+}}(%esp)
; precision18-NEXT: fistl {{[0-9]+}}(%esp) ; precision18-NEXT: fistl {{[0-9]+}}(%esp)
; precision18-NEXT: fldcw (%esp) ; precision18-NEXT: fldcw (%esp)
; precision18-NEXT: movl {{[0-9]+}}(%esp), %eax ; precision18-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp) ; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision18-NEXT: fisubl {{[0-9]+}}(%esp) ; precision18-NEXT: fisubl {{[0-9]+}}(%esp)
; precision18-NEXT: fld %st(0) ; precision18-NEXT: fld %st(0)
; precision18-NEXT: fmuls {{\.LCPI.*}} ; precision18-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fadds {{\.LCPI.*}} ; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st ; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}} ; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st ; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}} ; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st ; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}} ; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st ; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}} ; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmulp %st, %st(1) ; precision18-NEXT: fmulp %st, %st(1)
; precision18-NEXT: fld1 ; precision18-NEXT: fld1
; precision18-NEXT: faddp %st, %st(1) ; precision18-NEXT: faddp %st, %st(1)
; precision18-NEXT: fstps {{[0-9]+}}(%esp) ; precision18-NEXT: fstps {{[0-9]+}}(%esp)
; precision18-NEXT: shll $23, %eax ; precision18-NEXT: shll $23, %eax
; precision18-NEXT: addl {{[0-9]+}}(%esp), %eax ; precision18-NEXT: addl {{[0-9]+}}(%esp), %eax
; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp) ; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision18-NEXT: flds {{[0-9]+}}(%esp) ; precision18-NEXT: flds {{[0-9]+}}(%esp)
; precision18-NEXT: addl $20, %esp ; precision18-NEXT: addl $20, %esp
; precision18-NEXT: retl ; precision18-NEXT: retl
entry: entry:
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
%0 = call float @llvm.exp2.f32(float %x) ; <float> [#uses=1] %0 = call float @llvm.exp2.f32(float %x) ; <float> [#uses=1]
ret float %0 ret float %0
} }
declare float @llvm.exp2.f32(float) nounwind readonly declare float @llvm.exp2.f32(float) nounwind readonly
define float @f3(float %x) nounwind noinline { define float @f3(float %x) nounwind noinline {
; precision6-LABEL: f3: ; precision6-LABEL: f3:
; precision6: # %bb.0: # %entry ; precision6: # %bb.0: # %entry
; precision6-NEXT: subl $20, %esp ; precision6-NEXT: subl $20, %esp
; precision6-NEXT: flds {{[0-9]+}}(%esp) ; precision6-NEXT: flds {{[0-9]+}}(%esp)
; precision6-NEXT: fmuls {{\.LCPI.*}} ; precision6-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fnstcw (%esp) ; precision6-NEXT: fnstcw (%esp)
; precision6-NEXT: movzwl (%esp), %eax ; precision6-NEXT: movzwl (%esp), %eax
; precision6-NEXT: orl $3072, %eax # imm = 0xC00 ; precision6-NEXT: orl $3072, %eax # imm = 0xC00
; precision6-NEXT: movw %ax, {{[0-9]+}}(%esp) ; precision6-NEXT: movw %ax, {{[0-9]+}}(%esp)
; precision6-NEXT: fldcw {{[0-9]+}}(%esp) ; precision6-NEXT: fldcw {{[0-9]+}}(%esp)
; precision6-NEXT: fistl {{[0-9]+}}(%esp) ; precision6-NEXT: fistl {{[0-9]+}}(%esp)
; precision6-NEXT: fldcw (%esp) ; precision6-NEXT: fldcw (%esp)
; precision6-NEXT: movl {{[0-9]+}}(%esp), %eax ; precision6-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp) ; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision6-NEXT: fisubl {{[0-9]+}}(%esp) ; precision6-NEXT: fisubl {{[0-9]+}}(%esp)
; precision6-NEXT: fld %st(0) ; precision6-NEXT: fld %st(0)
; precision6-NEXT: fmuls {{\.LCPI.*}} ; precision6-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fadds {{\.LCPI.*}} ; precision6-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fmulp %st, %st(1) ; precision6-NEXT: fmulp %st, %st(1)
; precision6-NEXT: fadds {{\.LCPI.*}} ; precision6-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fstps {{[0-9]+}}(%esp) ; precision6-NEXT: fstps {{[0-9]+}}(%esp)
; precision6-NEXT: shll $23, %eax ; precision6-NEXT: shll $23, %eax
; precision6-NEXT: addl {{[0-9]+}}(%esp), %eax ; precision6-NEXT: addl {{[0-9]+}}(%esp), %eax
; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp) ; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision6-NEXT: flds {{[0-9]+}}(%esp) ; precision6-NEXT: flds {{[0-9]+}}(%esp)
; precision6-NEXT: addl $20, %esp ; precision6-NEXT: addl $20, %esp
; precision6-NEXT: retl ; precision6-NEXT: retl
; ;
; precision12-LABEL: f3: ; precision12-LABEL: f3:
; precision12: # %bb.0: # %entry ; precision12: # %bb.0: # %entry
; precision12-NEXT: subl $20, %esp ; precision12-NEXT: subl $20, %esp
; precision12-NEXT: flds {{[0-9]+}}(%esp) ; precision12-NEXT: flds {{[0-9]+}}(%esp)
; precision12-NEXT: fmuls {{\.LCPI.*}} ; precision12-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fnstcw (%esp) ; precision12-NEXT: fnstcw (%esp)
; precision12-NEXT: movzwl (%esp), %eax ; precision12-NEXT: movzwl (%esp), %eax
; precision12-NEXT: orl $3072, %eax # imm = 0xC00 ; precision12-NEXT: orl $3072, %eax # imm = 0xC00
; precision12-NEXT: movw %ax, {{[0-9]+}}(%esp) ; precision12-NEXT: movw %ax, {{[0-9]+}}(%esp)
; precision12-NEXT: fldcw {{[0-9]+}}(%esp) ; precision12-NEXT: fldcw {{[0-9]+}}(%esp)
; precision12-NEXT: fistl {{[0-9]+}}(%esp) ; precision12-NEXT: fistl {{[0-9]+}}(%esp)
; precision12-NEXT: fldcw (%esp) ; precision12-NEXT: fldcw (%esp)
; precision12-NEXT: movl {{[0-9]+}}(%esp), %eax ; precision12-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp) ; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision12-NEXT: fisubl {{[0-9]+}}(%esp) ; precision12-NEXT: fisubl {{[0-9]+}}(%esp)
; precision12-NEXT: fld %st(0) ; precision12-NEXT: fld %st(0)
; precision12-NEXT: fmuls {{\.LCPI.*}} ; precision12-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fadds {{\.LCPI.*}} ; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fmul %st(1), %st ; precision12-NEXT: fmul %st(1), %st
; precision12-NEXT: fadds {{\.LCPI.*}} ; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fmulp %st, %st(1) ; precision12-NEXT: fmulp %st, %st(1)
; precision12-NEXT: fadds {{\.LCPI.*}} ; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fstps {{[0-9]+}}(%esp) ; precision12-NEXT: fstps {{[0-9]+}}(%esp)
; precision12-NEXT: shll $23, %eax ; precision12-NEXT: shll $23, %eax
; precision12-NEXT: addl {{[0-9]+}}(%esp), %eax ; precision12-NEXT: addl {{[0-9]+}}(%esp), %eax
; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp) ; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision12-NEXT: flds {{[0-9]+}}(%esp) ; precision12-NEXT: flds {{[0-9]+}}(%esp)
; precision12-NEXT: addl $20, %esp ; precision12-NEXT: addl $20, %esp
; precision12-NEXT: retl ; precision12-NEXT: retl
; ;
; precision18-LABEL: f3: ; precision18-LABEL: f3:
; precision18: # %bb.0: # %entry ; precision18: # %bb.0: # %entry
; precision18-NEXT: subl $20, %esp ; precision18-NEXT: subl $20, %esp
; precision18-NEXT: flds {{[0-9]+}}(%esp) ; precision18-NEXT: flds {{[0-9]+}}(%esp)
; precision18-NEXT: fmuls {{\.LCPI.*}} ; precision18-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fnstcw (%esp) ; precision18-NEXT: fnstcw (%esp)
; precision18-NEXT: movzwl (%esp), %eax ; precision18-NEXT: movzwl (%esp), %eax
; precision18-NEXT: orl $3072, %eax # imm = 0xC00 ; precision18-NEXT: orl $3072, %eax # imm = 0xC00
; precision18-NEXT: movw %ax, {{[0-9]+}}(%esp) ; precision18-NEXT: movw %ax, {{[0-9]+}}(%esp)
; precision18-NEXT: fldcw {{[0-9]+}}(%esp) ; precision18-NEXT: fldcw {{[0-9]+}}(%esp)
; precision18-NEXT: fistl {{[0-9]+}}(%esp) ; precision18-NEXT: fistl {{[0-9]+}}(%esp)
; precision18-NEXT: fldcw (%esp) ; precision18-NEXT: fldcw (%esp)
; precision18-NEXT: movl {{[0-9]+}}(%esp), %eax ; precision18-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp) ; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision18-NEXT: fisubl {{[0-9]+}}(%esp) ; precision18-NEXT: fisubl {{[0-9]+}}(%esp)
; precision18-NEXT: fld %st(0) ; precision18-NEXT: fld %st(0)
; precision18-NEXT: fmuls {{\.LCPI.*}} ; precision18-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fadds {{\.LCPI.*}} ; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st ; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}} ; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st ; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}} ; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st ; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}} ; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st ; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}} ; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmulp %st, %st(1) ; precision18-NEXT: fmulp %st, %st(1)
; precision18-NEXT: fld1 ; precision18-NEXT: fld1
; precision18-NEXT: faddp %st, %st(1) ; precision18-NEXT: faddp %st, %st(1)
; precision18-NEXT: fstps {{[0-9]+}}(%esp) ; precision18-NEXT: fstps {{[0-9]+}}(%esp)
; precision18-NEXT: shll $23, %eax ; precision18-NEXT: shll $23, %eax
; precision18-NEXT: addl {{[0-9]+}}(%esp), %eax ; precision18-NEXT: addl {{[0-9]+}}(%esp), %eax
; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp) ; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision18-NEXT: flds {{[0-9]+}}(%esp) ; precision18-NEXT: flds {{[0-9]+}}(%esp)
Show All 17 Lines
; precision6-NEXT: orl $1065353216, %ecx # imm = 0x3F800000 ; precision6-NEXT: orl $1065353216, %ecx # imm = 0x3F800000
; precision6-NEXT: movl %ecx, (%esp) ; precision6-NEXT: movl %ecx, (%esp)
; precision6-NEXT: andl $2139095040, %eax # imm = 0x7F800000 ; precision6-NEXT: andl $2139095040, %eax # imm = 0x7F800000
; precision6-NEXT: shrl $23, %eax ; precision6-NEXT: shrl $23, %eax
; precision6-NEXT: addl $-127, %eax ; precision6-NEXT: addl $-127, %eax
; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp) ; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision6-NEXT: flds (%esp) ; precision6-NEXT: flds (%esp)
; precision6-NEXT: fld %st(0) ; precision6-NEXT: fld %st(0)
; precision6-NEXT: fmuls {{\.LCPI.*}} ; precision6-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fadds {{\.LCPI.*}} ; precision6-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fmulp %st, %st(1) ; precision6-NEXT: fmulp %st, %st(1)
; precision6-NEXT: fadds {{\.LCPI.*}} ; precision6-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fildl {{[0-9]+}}(%esp) ; precision6-NEXT: fildl {{[0-9]+}}(%esp)
; precision6-NEXT: fmuls {{\.LCPI.*}} ; precision6-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: faddp %st, %st(1) ; precision6-NEXT: faddp %st, %st(1)
; precision6-NEXT: addl $8, %esp ; precision6-NEXT: addl $8, %esp
; precision6-NEXT: retl ; precision6-NEXT: retl
; ;
; precision12-LABEL: f4: ; precision12-LABEL: f4:
; precision12: # %bb.0: # %entry ; precision12: # %bb.0: # %entry
; precision12-NEXT: subl $8, %esp ; precision12-NEXT: subl $8, %esp
; precision12-NEXT: movl {{[0-9]+}}(%esp), %eax ; precision12-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision12-NEXT: movl %eax, %ecx ; precision12-NEXT: movl %eax, %ecx
; precision12-NEXT: andl $8388607, %ecx # imm = 0x7FFFFF ; precision12-NEXT: andl $8388607, %ecx # imm = 0x7FFFFF
; precision12-NEXT: orl $1065353216, %ecx # imm = 0x3F800000 ; precision12-NEXT: orl $1065353216, %ecx # imm = 0x3F800000
; precision12-NEXT: movl %ecx, (%esp) ; precision12-NEXT: movl %ecx, (%esp)
; precision12-NEXT: andl $2139095040, %eax # imm = 0x7F800000 ; precision12-NEXT: andl $2139095040, %eax # imm = 0x7F800000
; precision12-NEXT: shrl $23, %eax ; precision12-NEXT: shrl $23, %eax
; precision12-NEXT: addl $-127, %eax ; precision12-NEXT: addl $-127, %eax
; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp) ; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision12-NEXT: flds (%esp) ; precision12-NEXT: flds (%esp)
; precision12-NEXT: fld %st(0) ; precision12-NEXT: fld %st(0)
; precision12-NEXT: fmuls {{\.LCPI.*}} ; precision12-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fadds {{\.LCPI.*}} ; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fmul %st(1), %st ; precision12-NEXT: fmul %st(1), %st
; precision12-NEXT: fadds {{\.LCPI.*}} ; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fmul %st(1), %st ; precision12-NEXT: fmul %st(1), %st
; precision12-NEXT: fadds {{\.LCPI.*}} ; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fmulp %st, %st(1) ; precision12-NEXT: fmulp %st, %st(1)
; precision12-NEXT: fadds {{\.LCPI.*}} ; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fildl {{[0-9]+}}(%esp) ; precision12-NEXT: fildl {{[0-9]+}}(%esp)
; precision12-NEXT: fmuls {{\.LCPI.*}} ; precision12-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: faddp %st, %st(1) ; precision12-NEXT: faddp %st, %st(1)
; precision12-NEXT: addl $8, %esp ; precision12-NEXT: addl $8, %esp
; precision12-NEXT: retl ; precision12-NEXT: retl
; ;
; precision18-LABEL: f4: ; precision18-LABEL: f4:
; precision18: # %bb.0: # %entry ; precision18: # %bb.0: # %entry
; precision18-NEXT: subl $8, %esp ; precision18-NEXT: subl $8, %esp
; precision18-NEXT: movl {{[0-9]+}}(%esp), %eax ; precision18-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision18-NEXT: movl %eax, %ecx ; precision18-NEXT: movl %eax, %ecx
; precision18-NEXT: andl $8388607, %ecx # imm = 0x7FFFFF ; precision18-NEXT: andl $8388607, %ecx # imm = 0x7FFFFF
; precision18-NEXT: orl $1065353216, %ecx # imm = 0x3F800000 ; precision18-NEXT: orl $1065353216, %ecx # imm = 0x3F800000
; precision18-NEXT: movl %ecx, (%esp) ; precision18-NEXT: movl %ecx, (%esp)
; precision18-NEXT: andl $2139095040, %eax # imm = 0x7F800000 ; precision18-NEXT: andl $2139095040, %eax # imm = 0x7F800000
; precision18-NEXT: shrl $23, %eax ; precision18-NEXT: shrl $23, %eax
; precision18-NEXT: addl $-127, %eax ; precision18-NEXT: addl $-127, %eax
; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp) ; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision18-NEXT: flds (%esp) ; precision18-NEXT: flds (%esp)
; precision18-NEXT: fld %st(0) ; precision18-NEXT: fld %st(0)
; precision18-NEXT: fmuls {{\.LCPI.*}} ; precision18-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fadds {{\.LCPI.*}} ; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st ; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}} ; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st ; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}} ; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st ; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}} ; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st ; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}} ; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmulp %st, %st(1) ; precision18-NEXT: fmulp %st, %st(1)
; precision18-NEXT: fadds {{\.LCPI.*}} ; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fildl {{[0-9]+}}(%esp) ; precision18-NEXT: fildl {{[0-9]+}}(%esp)
; precision18-NEXT: fmuls {{\.LCPI.*}} ; precision18-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: faddp %st, %st(1) ; precision18-NEXT: faddp %st, %st(1)
; precision18-NEXT: addl $8, %esp ; precision18-NEXT: addl $8, %esp
; precision18-NEXT: retl ; precision18-NEXT: retl
entry: entry:
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
%0 = call float @llvm.log.f32(float %x) ; <float> [#uses=1] %0 = call float @llvm.log.f32(float %x) ; <float> [#uses=1]
ret float %0 ret float %0
} }
Show All 10 Lines
; precision6-NEXT: orl $1065353216, %ecx # imm = 0x3F800000 ; precision6-NEXT: orl $1065353216, %ecx # imm = 0x3F800000
; precision6-NEXT: movl %ecx, (%esp) ; precision6-NEXT: movl %ecx, (%esp)
; precision6-NEXT: andl $2139095040, %eax # imm = 0x7F800000 ; precision6-NEXT: andl $2139095040, %eax # imm = 0x7F800000
; precision6-NEXT: shrl $23, %eax ; precision6-NEXT: shrl $23, %eax
; precision6-NEXT: addl $-127, %eax ; precision6-NEXT: addl $-127, %eax
; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp) ; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision6-NEXT: flds (%esp) ; precision6-NEXT: flds (%esp)
; precision6-NEXT: fld %st(0) ; precision6-NEXT: fld %st(0)
; precision6-NEXT: fmuls {{\.LCPI.*}} ; precision6-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fadds {{\.LCPI.*}} ; precision6-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fmulp %st, %st(1) ; precision6-NEXT: fmulp %st, %st(1)
; precision6-NEXT: fadds {{\.LCPI.*}} ; precision6-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fiaddl {{[0-9]+}}(%esp) ; precision6-NEXT: fiaddl {{[0-9]+}}(%esp)
; precision6-NEXT: addl $8, %esp ; precision6-NEXT: addl $8, %esp
; precision6-NEXT: retl ; precision6-NEXT: retl
; ;
; precision12-LABEL: f5: ; precision12-LABEL: f5:
; precision12: # %bb.0: # %entry ; precision12: # %bb.0: # %entry
; precision12-NEXT: subl $8, %esp ; precision12-NEXT: subl $8, %esp
; precision12-NEXT: movl {{[0-9]+}}(%esp), %eax ; precision12-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision12-NEXT: movl %eax, %ecx ; precision12-NEXT: movl %eax, %ecx
; precision12-NEXT: andl $8388607, %ecx # imm = 0x7FFFFF ; precision12-NEXT: andl $8388607, %ecx # imm = 0x7FFFFF
; precision12-NEXT: orl $1065353216, %ecx # imm = 0x3F800000 ; precision12-NEXT: orl $1065353216, %ecx # imm = 0x3F800000
; precision12-NEXT: movl %ecx, (%esp) ; precision12-NEXT: movl %ecx, (%esp)
; precision12-NEXT: andl $2139095040, %eax # imm = 0x7F800000 ; precision12-NEXT: andl $2139095040, %eax # imm = 0x7F800000
; precision12-NEXT: shrl $23, %eax ; precision12-NEXT: shrl $23, %eax
; precision12-NEXT: addl $-127, %eax ; precision12-NEXT: addl $-127, %eax
; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp) ; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision12-NEXT: flds (%esp) ; precision12-NEXT: flds (%esp)
; precision12-NEXT: fld %st(0) ; precision12-NEXT: fld %st(0)
; precision12-NEXT: fmuls {{\.LCPI.*}} ; precision12-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fadds {{\.LCPI.*}} ; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fmul %st(1), %st ; precision12-NEXT: fmul %st(1), %st
; precision12-NEXT: fadds {{\.LCPI.*}} ; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fmul %st(1), %st ; precision12-NEXT: fmul %st(1), %st
; precision12-NEXT: fadds {{\.LCPI.*}} ; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fmulp %st, %st(1) ; precision12-NEXT: fmulp %st, %st(1)
; precision12-NEXT: fadds {{\.LCPI.*}} ; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fiaddl {{[0-9]+}}(%esp) ; precision12-NEXT: fiaddl {{[0-9]+}}(%esp)
; precision12-NEXT: addl $8, %esp ; precision12-NEXT: addl $8, %esp
; precision12-NEXT: retl ; precision12-NEXT: retl
; ;
; precision18-LABEL: f5: ; precision18-LABEL: f5:
; precision18: # %bb.0: # %entry ; precision18: # %bb.0: # %entry
; precision18-NEXT: subl $8, %esp ; precision18-NEXT: subl $8, %esp
; precision18-NEXT: movl {{[0-9]+}}(%esp), %eax ; precision18-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision18-NEXT: movl %eax, %ecx ; precision18-NEXT: movl %eax, %ecx
; precision18-NEXT: andl $8388607, %ecx # imm = 0x7FFFFF ; precision18-NEXT: andl $8388607, %ecx # imm = 0x7FFFFF
; precision18-NEXT: orl $1065353216, %ecx # imm = 0x3F800000 ; precision18-NEXT: orl $1065353216, %ecx # imm = 0x3F800000
; precision18-NEXT: movl %ecx, (%esp) ; precision18-NEXT: movl %ecx, (%esp)
; precision18-NEXT: andl $2139095040, %eax # imm = 0x7F800000 ; precision18-NEXT: andl $2139095040, %eax # imm = 0x7F800000
; precision18-NEXT: shrl $23, %eax ; precision18-NEXT: shrl $23, %eax
; precision18-NEXT: addl $-127, %eax ; precision18-NEXT: addl $-127, %eax
; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp) ; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision18-NEXT: flds (%esp) ; precision18-NEXT: flds (%esp)
; precision18-NEXT: fld %st(0) ; precision18-NEXT: fld %st(0)
; precision18-NEXT: fmuls {{\.LCPI.*}} ; precision18-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fadds {{\.LCPI.*}} ; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st ; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}} ; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st ; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}} ; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st ; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}} ; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st ; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}} ; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmulp %st, %st(1) ; precision18-NEXT: fmulp %st, %st(1)
; precision18-NEXT: fadds {{\.LCPI.*}} ; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fiaddl {{[0-9]+}}(%esp) ; precision18-NEXT: fiaddl {{[0-9]+}}(%esp)
; precision18-NEXT: addl $8, %esp ; precision18-NEXT: addl $8, %esp
; precision18-NEXT: retl ; precision18-NEXT: retl
entry: entry:
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
%0 = call float @llvm.log2.f32(float %x) ; <float> [#uses=1] %0 = call float @llvm.log2.f32(float %x) ; <float> [#uses=1]
ret float %0 ret float %0
} }
Show All 10 Lines
; precision6-NEXT: orl $1065353216, %ecx # imm = 0x3F800000 ; precision6-NEXT: orl $1065353216, %ecx # imm = 0x3F800000
; precision6-NEXT: movl %ecx, (%esp) ; precision6-NEXT: movl %ecx, (%esp)
; precision6-NEXT: andl $2139095040, %eax # imm = 0x7F800000 ; precision6-NEXT: andl $2139095040, %eax # imm = 0x7F800000
; precision6-NEXT: shrl $23, %eax ; precision6-NEXT: shrl $23, %eax
; precision6-NEXT: addl $-127, %eax ; precision6-NEXT: addl $-127, %eax
; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp) ; precision6-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision6-NEXT: flds (%esp) ; precision6-NEXT: flds (%esp)
; precision6-NEXT: fld %st(0) ; precision6-NEXT: fld %st(0)
; precision6-NEXT: fmuls {{\.LCPI.*}} ; precision6-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fadds {{\.LCPI.*}} ; precision6-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fmulp %st, %st(1) ; precision6-NEXT: fmulp %st, %st(1)
; precision6-NEXT: fadds {{\.LCPI.*}} ; precision6-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: fildl {{[0-9]+}}(%esp) ; precision6-NEXT: fildl {{[0-9]+}}(%esp)
; precision6-NEXT: fmuls {{\.LCPI.*}} ; precision6-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; precision6-NEXT: faddp %st, %st(1) ; precision6-NEXT: faddp %st, %st(1)
; precision6-NEXT: addl $8, %esp ; precision6-NEXT: addl $8, %esp
; precision6-NEXT: retl ; precision6-NEXT: retl
; ;
; precision12-LABEL: f6: ; precision12-LABEL: f6:
; precision12: # %bb.0: # %entry ; precision12: # %bb.0: # %entry
; precision12-NEXT: subl $8, %esp ; precision12-NEXT: subl $8, %esp
; precision12-NEXT: movl {{[0-9]+}}(%esp), %eax ; precision12-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision12-NEXT: movl %eax, %ecx ; precision12-NEXT: movl %eax, %ecx
; precision12-NEXT: andl $8388607, %ecx # imm = 0x7FFFFF ; precision12-NEXT: andl $8388607, %ecx # imm = 0x7FFFFF
; precision12-NEXT: orl $1065353216, %ecx # imm = 0x3F800000 ; precision12-NEXT: orl $1065353216, %ecx # imm = 0x3F800000
; precision12-NEXT: movl %ecx, (%esp) ; precision12-NEXT: movl %ecx, (%esp)
; precision12-NEXT: andl $2139095040, %eax # imm = 0x7F800000 ; precision12-NEXT: andl $2139095040, %eax # imm = 0x7F800000
; precision12-NEXT: shrl $23, %eax ; precision12-NEXT: shrl $23, %eax
; precision12-NEXT: addl $-127, %eax ; precision12-NEXT: addl $-127, %eax
; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp) ; precision12-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision12-NEXT: flds (%esp) ; precision12-NEXT: flds (%esp)
; precision12-NEXT: fld %st(0) ; precision12-NEXT: fld %st(0)
; precision12-NEXT: fmuls {{\.LCPI.*}} ; precision12-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fadds {{\.LCPI.*}} ; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fmul %st(1), %st ; precision12-NEXT: fmul %st(1), %st
; precision12-NEXT: fadds {{\.LCPI.*}} ; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fmulp %st, %st(1) ; precision12-NEXT: fmulp %st, %st(1)
; precision12-NEXT: fadds {{\.LCPI.*}} ; precision12-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: fildl {{[0-9]+}}(%esp) ; precision12-NEXT: fildl {{[0-9]+}}(%esp)
; precision12-NEXT: fmuls {{\.LCPI.*}} ; precision12-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; precision12-NEXT: faddp %st, %st(1) ; precision12-NEXT: faddp %st, %st(1)
; precision12-NEXT: addl $8, %esp ; precision12-NEXT: addl $8, %esp
; precision12-NEXT: retl ; precision12-NEXT: retl
; ;
; precision18-LABEL: f6: ; precision18-LABEL: f6:
; precision18: # %bb.0: # %entry ; precision18: # %bb.0: # %entry
; precision18-NEXT: subl $8, %esp ; precision18-NEXT: subl $8, %esp
; precision18-NEXT: movl {{[0-9]+}}(%esp), %eax ; precision18-NEXT: movl {{[0-9]+}}(%esp), %eax
; precision18-NEXT: movl %eax, %ecx ; precision18-NEXT: movl %eax, %ecx
; precision18-NEXT: andl $8388607, %ecx # imm = 0x7FFFFF ; precision18-NEXT: andl $8388607, %ecx # imm = 0x7FFFFF
; precision18-NEXT: orl $1065353216, %ecx # imm = 0x3F800000 ; precision18-NEXT: orl $1065353216, %ecx # imm = 0x3F800000
; precision18-NEXT: movl %ecx, (%esp) ; precision18-NEXT: movl %ecx, (%esp)
; precision18-NEXT: andl $2139095040, %eax # imm = 0x7F800000 ; precision18-NEXT: andl $2139095040, %eax # imm = 0x7F800000
; precision18-NEXT: shrl $23, %eax ; precision18-NEXT: shrl $23, %eax
; precision18-NEXT: addl $-127, %eax ; precision18-NEXT: addl $-127, %eax
; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp) ; precision18-NEXT: movl %eax, {{[0-9]+}}(%esp)
; precision18-NEXT: flds (%esp) ; precision18-NEXT: flds (%esp)
; precision18-NEXT: fld %st(0) ; precision18-NEXT: fld %st(0)
; precision18-NEXT: fmuls {{\.LCPI.*}} ; precision18-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fadds {{\.LCPI.*}} ; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st ; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}} ; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st ; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}} ; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmul %st(1), %st ; precision18-NEXT: fmul %st(1), %st
; precision18-NEXT: fadds {{\.LCPI.*}} ; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fmulp %st, %st(1) ; precision18-NEXT: fmulp %st, %st(1)
; precision18-NEXT: fadds {{\.LCPI.*}} ; precision18-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: fildl {{[0-9]+}}(%esp) ; precision18-NEXT: fildl {{[0-9]+}}(%esp)
; precision18-NEXT: fmuls {{\.LCPI.*}} ; precision18-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; precision18-NEXT: faddp %st, %st(1) ; precision18-NEXT: faddp %st, %st(1)
; precision18-NEXT: addl $8, %esp ; precision18-NEXT: addl $8, %esp
; precision18-NEXT: retl ; precision18-NEXT: retl
entry: entry:
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
%0 = call float @llvm.log10.f32(float %x) ; <float> [#uses=1] %0 = call float @llvm.log10.f32(float %x) ; <float> [#uses=1]
ret float %0 ret float %0
} }
declare float @llvm.log10.f32(float) nounwind readonly declare float @llvm.log10.f32(float) nounwind readonly

llvm/test/CodeGen/X86/masked_gather_scatter.ll

Show First 20 Lines • Show All 511 Lines • ▼ Show 20 Lines
; SKX_SMALL-NEXT: kxnorw %k0, %k0, %k1 ; SKX_SMALL-NEXT: kxnorw %k0, %k0, %k1
; SKX_SMALL-NEXT: vpgatherqd (,%zmm1), %ymm0 {%k1} ; SKX_SMALL-NEXT: vpgatherqd (,%zmm1), %ymm0 {%k1}
; SKX_SMALL-NEXT: retq ; SKX_SMALL-NEXT: retq
; ;
; SKX_LARGE-LABEL: test9: ; SKX_LARGE-LABEL: test9:
; SKX_LARGE: # %bb.0: # %entry ; SKX_LARGE: # %bb.0: # %entry
; SKX_LARGE-NEXT: vpbroadcastq %rdi, %zmm2 ; SKX_LARGE-NEXT: vpbroadcastq %rdi, %zmm2
; SKX_LARGE-NEXT: vpmovzxdq {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero ; SKX_LARGE-NEXT: vpmovzxdq {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero
; SKX_LARGE-NEXT: movabsq ${{\.LCPI.*}}, %rax ; SKX_LARGE-NEXT: movabsq ${{\.LCPI[0-9]+_[0-9]+}}, %rax
; SKX_LARGE-NEXT: vpmuldq (%rax){1to8}, %zmm1, %zmm1 ; SKX_LARGE-NEXT: vpmuldq (%rax){1to8}, %zmm1, %zmm1
; SKX_LARGE-NEXT: movabsq ${{\.LCPI.*}}, %rax ; SKX_LARGE-NEXT: movabsq ${{\.LCPI[0-9]+_[0-9]+}}, %rax
; SKX_LARGE-NEXT: vpmullq (%rax){1to8}, %zmm0, %zmm0 ; SKX_LARGE-NEXT: vpmullq (%rax){1to8}, %zmm0, %zmm0
; SKX_LARGE-NEXT: vpaddq %zmm1, %zmm0, %zmm0 ; SKX_LARGE-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; SKX_LARGE-NEXT: vpaddq %zmm0, %zmm2, %zmm0 ; SKX_LARGE-NEXT: vpaddq %zmm0, %zmm2, %zmm0
; SKX_LARGE-NEXT: movabsq ${{\.LCPI.*}}, %rax ; SKX_LARGE-NEXT: movabsq ${{\.LCPI[0-9]+_[0-9]+}}, %rax
; SKX_LARGE-NEXT: vpaddq (%rax){1to8}, %zmm0, %zmm1 ; SKX_LARGE-NEXT: vpaddq (%rax){1to8}, %zmm0, %zmm1
; SKX_LARGE-NEXT: kxnorw %k0, %k0, %k1 ; SKX_LARGE-NEXT: kxnorw %k0, %k0, %k1
; SKX_LARGE-NEXT: vpgatherqd (,%zmm1), %ymm0 {%k1} ; SKX_LARGE-NEXT: vpgatherqd (,%zmm1), %ymm0 {%k1}
; SKX_LARGE-NEXT: retq ; SKX_LARGE-NEXT: retq
; ;
; SKX_32-LABEL: test9: ; SKX_32-LABEL: test9:
; SKX_32: # %bb.0: # %entry ; SKX_32: # %bb.0: # %entry
; SKX_32-NEXT: vpmulld {{\.LCPI.*}}{1to8}, %ymm1, %ymm1 ; SKX_32-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}{1to8}, %ymm1, %ymm1
; SKX_32-NEXT: vpmovqd %zmm0, %ymm0 ; SKX_32-NEXT: vpmovqd %zmm0, %ymm0
; SKX_32-NEXT: vpmulld {{\.LCPI.*}}{1to8}, %ymm0, %ymm0 ; SKX_32-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}{1to8}, %ymm0, %ymm0
; SKX_32-NEXT: vpaddd {{[0-9]+}}(%esp){1to8}, %ymm0, %ymm0 ; SKX_32-NEXT: vpaddd {{[0-9]+}}(%esp){1to8}, %ymm0, %ymm0
; SKX_32-NEXT: vpaddd %ymm1, %ymm0, %ymm0 ; SKX_32-NEXT: vpaddd %ymm1, %ymm0, %ymm0
; SKX_32-NEXT: vpaddd {{\.LCPI.*}}{1to8}, %ymm0, %ymm1 ; SKX_32-NEXT: vpaddd {{\.LCPI[0-9]+_[0-9]+}}{1to8}, %ymm0, %ymm1
; SKX_32-NEXT: kxnorw %k0, %k0, %k1 ; SKX_32-NEXT: kxnorw %k0, %k0, %k1
; SKX_32-NEXT: vpgatherdd (,%ymm1), %ymm0 {%k1} ; SKX_32-NEXT: vpgatherdd (,%ymm1), %ymm0 {%k1}
; SKX_32-NEXT: retl ; SKX_32-NEXT: retl
entry: entry:
%broadcast.splatinsert = insertelement <8 x %struct.ST*> undef, %struct.ST* %base, i32 0 %broadcast.splatinsert = insertelement <8 x %struct.ST*> undef, %struct.ST* %base, i32 0
%broadcast.splat = shufflevector <8 x %struct.ST*> %broadcast.splatinsert, <8 x %struct.ST*> undef, <8 x i32> zeroinitializer %broadcast.splat = shufflevector <8 x %struct.ST*> %broadcast.splatinsert, <8 x %struct.ST*> undef, <8 x i32> zeroinitializer
%arrayidx = getelementptr %struct.ST, <8 x %struct.ST*> %broadcast.splat, <8 x i64> %ind1, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>, <8 x i32><i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, <8 x i32> %ind5, <8 x i64> <i64 13, i64 13, i64 13, i64 13, i64 13, i64 13, i64 13, i64 13> %arrayidx = getelementptr %struct.ST, <8 x %struct.ST*> %broadcast.splat, <8 x i64> %ind1, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>, <8 x i32><i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, <8 x i32> %ind5, <8 x i64> <i64 13, i64 13, i64 13, i64 13, i64 13, i64 13, i64 13, i64 13>
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; SKX_SMALL-NEXT: kxnorw %k0, %k0, %k1 ; SKX_SMALL-NEXT: kxnorw %k0, %k0, %k1
; SKX_SMALL-NEXT: vpgatherqd (,%zmm1), %ymm0 {%k1} ; SKX_SMALL-NEXT: vpgatherqd (,%zmm1), %ymm0 {%k1}
; SKX_SMALL-NEXT: retq ; SKX_SMALL-NEXT: retq
; ;
; SKX_LARGE-LABEL: test10: ; SKX_LARGE-LABEL: test10:
; SKX_LARGE: # %bb.0: # %entry ; SKX_LARGE: # %bb.0: # %entry
; SKX_LARGE-NEXT: vpbroadcastq %rdi, %zmm2 ; SKX_LARGE-NEXT: vpbroadcastq %rdi, %zmm2
; SKX_LARGE-NEXT: vpmovzxdq {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero ; SKX_LARGE-NEXT: vpmovzxdq {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero
; SKX_LARGE-NEXT: movabsq ${{\.LCPI.*}}, %rax ; SKX_LARGE-NEXT: movabsq ${{\.LCPI[0-9]+_[0-9]+}}, %rax
; SKX_LARGE-NEXT: vpmuldq (%rax){1to8}, %zmm1, %zmm1 ; SKX_LARGE-NEXT: vpmuldq (%rax){1to8}, %zmm1, %zmm1
; SKX_LARGE-NEXT: movabsq ${{\.LCPI.*}}, %rax ; SKX_LARGE-NEXT: movabsq ${{\.LCPI[0-9]+_[0-9]+}}, %rax
; SKX_LARGE-NEXT: vpmullq (%rax){1to8}, %zmm0, %zmm0 ; SKX_LARGE-NEXT: vpmullq (%rax){1to8}, %zmm0, %zmm0
; SKX_LARGE-NEXT: vpaddq %zmm1, %zmm0, %zmm0 ; SKX_LARGE-NEXT: vpaddq %zmm1, %zmm0, %zmm0
; SKX_LARGE-NEXT: vpaddq %zmm0, %zmm2, %zmm0 ; SKX_LARGE-NEXT: vpaddq %zmm0, %zmm2, %zmm0
; SKX_LARGE-NEXT: movabsq ${{\.LCPI.*}}, %rax ; SKX_LARGE-NEXT: movabsq ${{\.LCPI[0-9]+_[0-9]+}}, %rax
; SKX_LARGE-NEXT: vpaddq (%rax){1to8}, %zmm0, %zmm1 ; SKX_LARGE-NEXT: vpaddq (%rax){1to8}, %zmm0, %zmm1
; SKX_LARGE-NEXT: kxnorw %k0, %k0, %k1 ; SKX_LARGE-NEXT: kxnorw %k0, %k0, %k1
; SKX_LARGE-NEXT: vpgatherqd (,%zmm1), %ymm0 {%k1} ; SKX_LARGE-NEXT: vpgatherqd (,%zmm1), %ymm0 {%k1}
; SKX_LARGE-NEXT: retq ; SKX_LARGE-NEXT: retq
; ;
; SKX_32-LABEL: test10: ; SKX_32-LABEL: test10:
; SKX_32: # %bb.0: # %entry ; SKX_32: # %bb.0: # %entry
; SKX_32-NEXT: vpmulld {{\.LCPI.*}}{1to8}, %ymm1, %ymm1 ; SKX_32-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}{1to8}, %ymm1, %ymm1
; SKX_32-NEXT: vpmovqd %zmm0, %ymm0 ; SKX_32-NEXT: vpmovqd %zmm0, %ymm0
; SKX_32-NEXT: vpmulld {{\.LCPI.*}}{1to8}, %ymm0, %ymm0 ; SKX_32-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}{1to8}, %ymm0, %ymm0
; SKX_32-NEXT: vpaddd {{[0-9]+}}(%esp){1to8}, %ymm0, %ymm0 ; SKX_32-NEXT: vpaddd {{[0-9]+}}(%esp){1to8}, %ymm0, %ymm0
; SKX_32-NEXT: vpaddd %ymm1, %ymm0, %ymm0 ; SKX_32-NEXT: vpaddd %ymm1, %ymm0, %ymm0
; SKX_32-NEXT: vpaddd {{\.LCPI.*}}{1to8}, %ymm0, %ymm1 ; SKX_32-NEXT: vpaddd {{\.LCPI[0-9]+_[0-9]+}}{1to8}, %ymm0, %ymm1
; SKX_32-NEXT: kxnorw %k0, %k0, %k1 ; SKX_32-NEXT: kxnorw %k0, %k0, %k1
; SKX_32-NEXT: vpgatherdd (,%ymm1), %ymm0 {%k1} ; SKX_32-NEXT: vpgatherdd (,%ymm1), %ymm0 {%k1}
; SKX_32-NEXT: retl ; SKX_32-NEXT: retl
entry: entry:
%broadcast.splatinsert = insertelement <8 x %struct.ST*> undef, %struct.ST* %base, i32 0 %broadcast.splatinsert = insertelement <8 x %struct.ST*> undef, %struct.ST* %base, i32 0
%broadcast.splat = shufflevector <8 x %struct.ST*> %broadcast.splatinsert, <8 x %struct.ST*> undef, <8 x i32> zeroinitializer %broadcast.splat = shufflevector <8 x %struct.ST*> %broadcast.splatinsert, <8 x %struct.ST*> undef, <8 x i32> zeroinitializer
%arrayidx = getelementptr %struct.ST, <8 x %struct.ST*> %broadcast.splat, <8 x i64> %i1, i32 2, i32 1, <8 x i32> %ind5, i64 13 %arrayidx = getelementptr %struct.ST, <8 x %struct.ST*> %broadcast.splat, <8 x i64> %i1, i32 2, i32 1, <8 x i32> %ind5, i64 13
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; KNL_64-NEXT: vpandd {{.*}}(%rip){1to16}, %zmm0, %zmm1 ; KNL_64-NEXT: vpandd {{.*}}(%rip){1to16}, %zmm0, %zmm1
; KNL_64-NEXT: kxnorw %k0, %k0, %k1 ; KNL_64-NEXT: kxnorw %k0, %k0, %k1
; KNL_64-NEXT: vgatherdps (%rdi,%zmm1,4), %zmm0 {%k1} ; KNL_64-NEXT: vgatherdps (%rdi,%zmm1,4), %zmm0 {%k1}
; KNL_64-NEXT: retq ; KNL_64-NEXT: retq
; ;
; KNL_32-LABEL: zext_index: ; KNL_32-LABEL: zext_index:
; KNL_32: # %bb.0: ; KNL_32: # %bb.0:
; KNL_32-NEXT: movl {{[0-9]+}}(%esp), %eax ; KNL_32-NEXT: movl {{[0-9]+}}(%esp), %eax
; KNL_32-NEXT: vpandd {{\.LCPI.*}}{1to16}, %zmm0, %zmm1 ; KNL_32-NEXT: vpandd {{\.LCPI[0-9]+_[0-9]+}}{1to16}, %zmm0, %zmm1
; KNL_32-NEXT: kxnorw %k0, %k0, %k1 ; KNL_32-NEXT: kxnorw %k0, %k0, %k1
; KNL_32-NEXT: vgatherdps (%eax,%zmm1,4), %zmm0 {%k1} ; KNL_32-NEXT: vgatherdps (%eax,%zmm1,4), %zmm0 {%k1}
; KNL_32-NEXT: retl ; KNL_32-NEXT: retl
; ;
; SKX_SMALL-LABEL: zext_index: ; SKX_SMALL-LABEL: zext_index:
; SKX_SMALL: # %bb.0: ; SKX_SMALL: # %bb.0:
; SKX_SMALL-NEXT: vandps {{.*}}(%rip){1to16}, %zmm0, %zmm1 ; SKX_SMALL-NEXT: vandps {{.*}}(%rip){1to16}, %zmm0, %zmm1
; SKX_SMALL-NEXT: kxnorw %k0, %k0, %k1 ; SKX_SMALL-NEXT: kxnorw %k0, %k0, %k1
; SKX_SMALL-NEXT: vgatherdps (%rdi,%zmm1,4), %zmm0 {%k1} ; SKX_SMALL-NEXT: vgatherdps (%rdi,%zmm1,4), %zmm0 {%k1}
; SKX_SMALL-NEXT: retq ; SKX_SMALL-NEXT: retq
; ;
; SKX_LARGE-LABEL: zext_index: ; SKX_LARGE-LABEL: zext_index:
; SKX_LARGE: # %bb.0: ; SKX_LARGE: # %bb.0:
; SKX_LARGE-NEXT: movabsq ${{\.LCPI.*}}, %rax ; SKX_LARGE-NEXT: movabsq ${{\.LCPI[0-9]+_[0-9]+}}, %rax
; SKX_LARGE-NEXT: vandps (%rax){1to16}, %zmm0, %zmm1 ; SKX_LARGE-NEXT: vandps (%rax){1to16}, %zmm0, %zmm1
; SKX_LARGE-NEXT: kxnorw %k0, %k0, %k1 ; SKX_LARGE-NEXT: kxnorw %k0, %k0, %k1
; SKX_LARGE-NEXT: vgatherdps (%rdi,%zmm1,4), %zmm0 {%k1} ; SKX_LARGE-NEXT: vgatherdps (%rdi,%zmm1,4), %zmm0 {%k1}
; SKX_LARGE-NEXT: retq ; SKX_LARGE-NEXT: retq
; ;
; SKX_32-LABEL: zext_index: ; SKX_32-LABEL: zext_index:
; SKX_32: # %bb.0: ; SKX_32: # %bb.0:
; SKX_32-NEXT: movl {{[0-9]+}}(%esp), %eax ; SKX_32-NEXT: movl {{[0-9]+}}(%esp), %eax
; SKX_32-NEXT: vandps {{\.LCPI.*}}{1to16}, %zmm0, %zmm1 ; SKX_32-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}{1to16}, %zmm0, %zmm1
; SKX_32-NEXT: kxnorw %k0, %k0, %k1 ; SKX_32-NEXT: kxnorw %k0, %k0, %k1
; SKX_32-NEXT: vgatherdps (%eax,%zmm1,4), %zmm0 {%k1} ; SKX_32-NEXT: vgatherdps (%eax,%zmm1,4), %zmm0 {%k1}
; SKX_32-NEXT: retl ; SKX_32-NEXT: retl
%ind_masked = and <16 x i32> %ind, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15> %ind_masked = and <16 x i32> %ind, <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
%sext_ind = zext <16 x i32> %ind_masked to <16 x i64> %sext_ind = zext <16 x i32> %ind_masked to <16 x i64>
%gep.random = getelementptr float, float *%base, <16 x i64> %sext_ind %gep.random = getelementptr float, float *%base, <16 x i64> %sext_ind
%res = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> %gep.random, i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <16 x float> undef) %res = call <16 x float> @llvm.masked.gather.v16f32.v16p0f32(<16 x float*> %gep.random, i32 4, <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <16 x float> undef)
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; SKX_SMALL-NEXT: vpxor %xmm0, %xmm0, %xmm0 ; SKX_SMALL-NEXT: vpxor %xmm0, %xmm0, %xmm0
; SKX_SMALL-NEXT: vpgatherdq (%rdi,%xmm1,8), %xmm0 {%k1} ; SKX_SMALL-NEXT: vpgatherdq (%rdi,%xmm1,8), %xmm0 {%k1}
; SKX_SMALL-NEXT: retq ; SKX_SMALL-NEXT: retq
; ;
; SKX_LARGE-LABEL: gather_2i64_constant_indices: ; SKX_LARGE-LABEL: gather_2i64_constant_indices:
; SKX_LARGE: # %bb.0: ; SKX_LARGE: # %bb.0:
; SKX_LARGE-NEXT: vpsllq $63, %xmm0, %xmm0 ; SKX_LARGE-NEXT: vpsllq $63, %xmm0, %xmm0
; SKX_LARGE-NEXT: vpmovq2m %xmm0, %k1 ; SKX_LARGE-NEXT: vpmovq2m %xmm0, %k1
; SKX_LARGE-NEXT: movabsq ${{\.LCPI.*}}, %rax ; SKX_LARGE-NEXT: movabsq ${{\.LCPI[0-9]+_[0-9]+}}, %rax
; SKX_LARGE-NEXT: vmovdqa (%rax), %xmm1 ; SKX_LARGE-NEXT: vmovdqa (%rax), %xmm1
; SKX_LARGE-NEXT: vpxor %xmm0, %xmm0, %xmm0 ; SKX_LARGE-NEXT: vpxor %xmm0, %xmm0, %xmm0
; SKX_LARGE-NEXT: vpgatherdq (%rdi,%xmm1,8), %xmm0 {%k1} ; SKX_LARGE-NEXT: vpgatherdq (%rdi,%xmm1,8), %xmm0 {%k1}
; SKX_LARGE-NEXT: retq ; SKX_LARGE-NEXT: retq
; ;
; SKX_32-LABEL: gather_2i64_constant_indices: ; SKX_32-LABEL: gather_2i64_constant_indices:
; SKX_32: # %bb.0: ; SKX_32: # %bb.0:
; SKX_32-NEXT: vpsllq $63, %xmm0, %xmm0 ; SKX_32-NEXT: vpsllq $63, %xmm0, %xmm0
Show All 40 Lines
; SKX_SMALL-NEXT: vpgatherdd (%rdi,%zmm1,4), %zmm0 {%k1} ; SKX_SMALL-NEXT: vpgatherdd (%rdi,%zmm1,4), %zmm0 {%k1}
; SKX_SMALL-NEXT: retq ; SKX_SMALL-NEXT: retq
; ;
; SKX_LARGE-LABEL: gather_16i64_constant_indices: ; SKX_LARGE-LABEL: gather_16i64_constant_indices:
; SKX_LARGE: # %bb.0: ; SKX_LARGE: # %bb.0:
; SKX_LARGE-NEXT: vpmovsxbd %xmm0, %zmm0 ; SKX_LARGE-NEXT: vpmovsxbd %xmm0, %zmm0
; SKX_LARGE-NEXT: vpslld $31, %zmm0, %zmm0 ; SKX_LARGE-NEXT: vpslld $31, %zmm0, %zmm0
; SKX_LARGE-NEXT: vpmovd2m %zmm0, %k1 ; SKX_LARGE-NEXT: vpmovd2m %zmm0, %k1
; SKX_LARGE-NEXT: movabsq ${{\.LCPI.*}}, %rax ; SKX_LARGE-NEXT: movabsq ${{\.LCPI[0-9]+_[0-9]+}}, %rax
; SKX_LARGE-NEXT: vmovdqa64 (%rax), %zmm1 ; SKX_LARGE-NEXT: vmovdqa64 (%rax), %zmm1
; SKX_LARGE-NEXT: vpxor %xmm0, %xmm0, %xmm0 ; SKX_LARGE-NEXT: vpxor %xmm0, %xmm0, %xmm0
; SKX_LARGE-NEXT: vpgatherdd (%rdi,%zmm1,4), %zmm0 {%k1} ; SKX_LARGE-NEXT: vpgatherdd (%rdi,%zmm1,4), %zmm0 {%k1}
; SKX_LARGE-NEXT: retq ; SKX_LARGE-NEXT: retq
; ;
; SKX_32-LABEL: gather_16i64_constant_indices: ; SKX_32-LABEL: gather_16i64_constant_indices:
; SKX_32: # %bb.0: ; SKX_32: # %bb.0:
; SKX_32-NEXT: vpmovsxbd %xmm0, %zmm0 ; SKX_32-NEXT: vpmovsxbd %xmm0, %zmm0
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; SKX_SMALL-NEXT: vmovdqa {{.*#+}} xmm0 = <0,4294967294,u,u> ; SKX_SMALL-NEXT: vmovdqa {{.*#+}} xmm0 = <0,4294967294,u,u>
; SKX_SMALL-NEXT: vpscatterdd %xmm1, (%rdi,%xmm0,4) {%k1} ; SKX_SMALL-NEXT: vpscatterdd %xmm1, (%rdi,%xmm0,4) {%k1}
; SKX_SMALL-NEXT: retq ; SKX_SMALL-NEXT: retq
; ;
; SKX_LARGE-LABEL: scatter_2i64_constant_indices: ; SKX_LARGE-LABEL: scatter_2i64_constant_indices:
; SKX_LARGE: # %bb.0: ; SKX_LARGE: # %bb.0:
; SKX_LARGE-NEXT: vpsllq $63, %xmm0, %xmm0 ; SKX_LARGE-NEXT: vpsllq $63, %xmm0, %xmm0
; SKX_LARGE-NEXT: vpmovq2m %xmm0, %k1 ; SKX_LARGE-NEXT: vpmovq2m %xmm0, %k1
; SKX_LARGE-NEXT: movabsq ${{\.LCPI.*}}, %rax ; SKX_LARGE-NEXT: movabsq ${{\.LCPI[0-9]+_[0-9]+}}, %rax
; SKX_LARGE-NEXT: vmovdqa (%rax), %xmm0 ; SKX_LARGE-NEXT: vmovdqa (%rax), %xmm0
; SKX_LARGE-NEXT: vpscatterdd %xmm1, (%rdi,%xmm0,4) {%k1} ; SKX_LARGE-NEXT: vpscatterdd %xmm1, (%rdi,%xmm0,4) {%k1}
; SKX_LARGE-NEXT: retq ; SKX_LARGE-NEXT: retq
; ;
; SKX_32-LABEL: scatter_2i64_constant_indices: ; SKX_32-LABEL: scatter_2i64_constant_indices:
; SKX_32: # %bb.0: ; SKX_32: # %bb.0:
; SKX_32-NEXT: vpsllq $63, %xmm0, %xmm0 ; SKX_32-NEXT: vpsllq $63, %xmm0, %xmm0
; SKX_32-NEXT: vpmovq2m %xmm0, %k1 ; SKX_32-NEXT: vpmovq2m %xmm0, %k1
Show All 38 Lines
; SKX_SMALL-NEXT: vzeroupper ; SKX_SMALL-NEXT: vzeroupper
; SKX_SMALL-NEXT: retq ; SKX_SMALL-NEXT: retq
; ;
; SKX_LARGE-LABEL: scatter_16i64_constant_indices: ; SKX_LARGE-LABEL: scatter_16i64_constant_indices:
; SKX_LARGE: # %bb.0: ; SKX_LARGE: # %bb.0:
; SKX_LARGE-NEXT: vpmovsxbd %xmm0, %zmm0 ; SKX_LARGE-NEXT: vpmovsxbd %xmm0, %zmm0
; SKX_LARGE-NEXT: vpslld $31, %zmm0, %zmm0 ; SKX_LARGE-NEXT: vpslld $31, %zmm0, %zmm0
; SKX_LARGE-NEXT: vpmovd2m %zmm0, %k1 ; SKX_LARGE-NEXT: vpmovd2m %zmm0, %k1
; SKX_LARGE-NEXT: movabsq ${{\.LCPI.*}}, %rax ; SKX_LARGE-NEXT: movabsq ${{\.LCPI[0-9]+_[0-9]+}}, %rax
; SKX_LARGE-NEXT: vmovdqa64 (%rax), %zmm0 ; SKX_LARGE-NEXT: vmovdqa64 (%rax), %zmm0
; SKX_LARGE-NEXT: vpscatterdd %zmm1, (%rdi,%zmm0,4) {%k1} ; SKX_LARGE-NEXT: vpscatterdd %zmm1, (%rdi,%zmm0,4) {%k1}
; SKX_LARGE-NEXT: vzeroupper ; SKX_LARGE-NEXT: vzeroupper
; SKX_LARGE-NEXT: retq ; SKX_LARGE-NEXT: retq
; ;
; SKX_32-LABEL: scatter_16i64_constant_indices: ; SKX_32-LABEL: scatter_16i64_constant_indices:
; SKX_32: # %bb.0: ; SKX_32: # %bb.0:
; SKX_32-NEXT: vpmovsxbd %xmm0, %zmm0 ; SKX_32-NEXT: vpmovsxbd %xmm0, %zmm0
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; SKX_SMALL: # %bb.0: # %bb ; SKX_SMALL: # %bb.0: # %bb
; SKX_SMALL-NEXT: vpaddq {{.*}}(%rip){1to8}, %zmm0, %zmm1 ; SKX_SMALL-NEXT: vpaddq {{.*}}(%rip){1to8}, %zmm0, %zmm1
; SKX_SMALL-NEXT: kxnorw %k0, %k0, %k1 ; SKX_SMALL-NEXT: kxnorw %k0, %k0, %k1
; SKX_SMALL-NEXT: vpgatherqq (,%zmm1), %zmm0 {%k1} ; SKX_SMALL-NEXT: vpgatherqq (,%zmm1), %zmm0 {%k1}
; SKX_SMALL-NEXT: retq ; SKX_SMALL-NEXT: retq
; ;
; SKX_LARGE-LABEL: pr45906: ; SKX_LARGE-LABEL: pr45906:
; SKX_LARGE: # %bb.0: # %bb ; SKX_LARGE: # %bb.0: # %bb
; SKX_LARGE-NEXT: movabsq ${{\.LCPI.*}}, %rax ; SKX_LARGE-NEXT: movabsq ${{\.LCPI[0-9]+_[0-9]+}}, %rax
; SKX_LARGE-NEXT: vpaddq (%rax){1to8}, %zmm0, %zmm1 ; SKX_LARGE-NEXT: vpaddq (%rax){1to8}, %zmm0, %zmm1
; SKX_LARGE-NEXT: kxnorw %k0, %k0, %k1 ; SKX_LARGE-NEXT: kxnorw %k0, %k0, %k1
; SKX_LARGE-NEXT: vpgatherqq (,%zmm1), %zmm0 {%k1} ; SKX_LARGE-NEXT: vpgatherqq (,%zmm1), %zmm0 {%k1}
; SKX_LARGE-NEXT: retq ; SKX_LARGE-NEXT: retq
; ;
; SKX_32-LABEL: pr45906: ; SKX_32-LABEL: pr45906:
; SKX_32: # %bb.0: # %bb ; SKX_32: # %bb.0: # %bb
; SKX_32-NEXT: vpaddd {{\.LCPI.*}}{1to8}, %ymm0, %ymm1 ; SKX_32-NEXT: vpaddd {{\.LCPI[0-9]+_[0-9]+}}{1to8}, %ymm0, %ymm1
; SKX_32-NEXT: kxnorw %k0, %k0, %k1 ; SKX_32-NEXT: kxnorw %k0, %k0, %k1
; SKX_32-NEXT: vpgatherdq (,%ymm1), %zmm0 {%k1} ; SKX_32-NEXT: vpgatherdq (,%ymm1), %zmm0 {%k1}
; SKX_32-NEXT: retl ; SKX_32-NEXT: retl
bb: bb:
%tmp = getelementptr inbounds %struct.foo, <8 x %struct.foo*> %ptr, i64 0, i32 1 %tmp = getelementptr inbounds %struct.foo, <8 x %struct.foo*> %ptr, i64 0, i32 1
%tmp1 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0i64(<8 x i64*> %tmp, i32 8, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i64> undef) %tmp1 = call <8 x i64> @llvm.masked.gather.v8i64.v8p0i64(<8 x i64*> %tmp, i32 8, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i64> undef)
ret <8 x i64> %tmp1 ret <8 x i64> %tmp1
} }
declare <8 x i64> @llvm.masked.gather.v8i64.v8p0i64(<8 x i64*>, i32, <8 x i1>, <8 x i64>) declare <8 x i64> @llvm.masked.gather.v8i64.v8p0i64(<8 x i64*>, i32, <8 x i1>, <8 x i64>)

llvm/test/CodeGen/X86/memcmp-minsize.ll

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; X86-NOSSE-NEXT: testl %eax, %eax ; X86-NOSSE-NEXT: testl %eax, %eax
; X86-NOSSE-NEXT: sete %al ; X86-NOSSE-NEXT: sete %al
; X86-NOSSE-NEXT: retl ; X86-NOSSE-NEXT: retl
; ;
; X86-SSE2-LABEL: length16_eq_const: ; X86-SSE2-LABEL: length16_eq_const:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0 ; X86-SSE2-NEXT: movdqu (%eax), %xmm0
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax ; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF ; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
; X86-SSE2-NEXT: sete %al ; X86-SSE2-NEXT: sete %al
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X64-SSE2-LABEL: length16_eq_const: ; X64-SSE2-LABEL: length16_eq_const:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: movdqu (%rdi), %xmm0 ; X64-SSE2-NEXT: movdqu (%rdi), %xmm0
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llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll

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; X86-SSE1-NEXT: sete %al ; X86-SSE1-NEXT: sete %al
; X86-SSE1-NEXT: popl %esi ; X86-SSE1-NEXT: popl %esi
; X86-SSE1-NEXT: retl ; X86-SSE1-NEXT: retl
; ;
; X86-SSE2-LABEL: length16_eq_const: ; X86-SSE2-LABEL: length16_eq_const:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0 ; X86-SSE2-NEXT: movdqu (%eax), %xmm0
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax ; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF ; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
; X86-SSE2-NEXT: sete %al ; X86-SSE2-NEXT: sete %al
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-SSE41-LABEL: length16_eq_const: ; X86-SSE41-LABEL: length16_eq_const:
; X86-SSE41: # %bb.0: ; X86-SSE41: # %bb.0:
; X86-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE41-NEXT: movdqu (%eax), %xmm0 ; X86-SSE41-NEXT: movdqu (%eax), %xmm0
; X86-SSE41-NEXT: pxor {{\.LCPI.*}}, %xmm0 ; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE41-NEXT: ptest %xmm0, %xmm0 ; X86-SSE41-NEXT: ptest %xmm0, %xmm0
; X86-SSE41-NEXT: sete %al ; X86-SSE41-NEXT: sete %al
; X86-SSE41-NEXT: retl ; X86-SSE41-NEXT: retl
; ;
; X64-SSE2-LABEL: length16_eq_const: ; X64-SSE2-LABEL: length16_eq_const:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: movdqu (%rdi), %xmm0 ; X64-SSE2-NEXT: movdqu (%rdi), %xmm0
; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm0
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; X86-SSE1-NEXT: setne %al ; X86-SSE1-NEXT: setne %al
; X86-SSE1-NEXT: retl ; X86-SSE1-NEXT: retl
; ;
; X86-SSE2-LABEL: length24_eq_const: ; X86-SSE2-LABEL: length24_eq_const:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0 ; X86-SSE2-NEXT: movdqu (%eax), %xmm0
; X86-SSE2-NEXT: movdqu 8(%eax), %xmm1 ; X86-SSE2-NEXT: movdqu 8(%eax), %xmm1
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0 ; X86-SSE2-NEXT: pand %xmm1, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax ; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF ; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
; X86-SSE2-NEXT: setne %al ; X86-SSE2-NEXT: setne %al
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-SSE41-LABEL: length24_eq_const: ; X86-SSE41-LABEL: length24_eq_const:
; X86-SSE41: # %bb.0: ; X86-SSE41: # %bb.0:
; X86-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE41-NEXT: movdqu (%eax), %xmm0 ; X86-SSE41-NEXT: movdqu (%eax), %xmm0
; X86-SSE41-NEXT: movdqu 8(%eax), %xmm1 ; X86-SSE41-NEXT: movdqu 8(%eax), %xmm1
; X86-SSE41-NEXT: pxor {{\.LCPI.*}}, %xmm1 ; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE41-NEXT: pxor {{\.LCPI.*}}, %xmm0 ; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE41-NEXT: por %xmm1, %xmm0 ; X86-SSE41-NEXT: por %xmm1, %xmm0
; X86-SSE41-NEXT: ptest %xmm0, %xmm0 ; X86-SSE41-NEXT: ptest %xmm0, %xmm0
; X86-SSE41-NEXT: setne %al ; X86-SSE41-NEXT: setne %al
; X86-SSE41-NEXT: retl ; X86-SSE41-NEXT: retl
; ;
; X64-SSE2-LABEL: length24_eq_const: ; X64-SSE2-LABEL: length24_eq_const:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: movdqu (%rdi), %xmm0 ; X64-SSE2-NEXT: movdqu (%rdi), %xmm0
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; X86-SSE1-NEXT: setne %al ; X86-SSE1-NEXT: setne %al
; X86-SSE1-NEXT: retl ; X86-SSE1-NEXT: retl
; ;
; X86-SSE2-LABEL: length31_eq_const: ; X86-SSE2-LABEL: length31_eq_const:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0 ; X86-SSE2-NEXT: movdqu (%eax), %xmm0
; X86-SSE2-NEXT: movdqu 15(%eax), %xmm1 ; X86-SSE2-NEXT: movdqu 15(%eax), %xmm1
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0 ; X86-SSE2-NEXT: pand %xmm1, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax ; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF ; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
; X86-SSE2-NEXT: setne %al ; X86-SSE2-NEXT: setne %al
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-SSE41-LABEL: length31_eq_const: ; X86-SSE41-LABEL: length31_eq_const:
; X86-SSE41: # %bb.0: ; X86-SSE41: # %bb.0:
; X86-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE41-NEXT: movdqu (%eax), %xmm0 ; X86-SSE41-NEXT: movdqu (%eax), %xmm0
; X86-SSE41-NEXT: movdqu 15(%eax), %xmm1 ; X86-SSE41-NEXT: movdqu 15(%eax), %xmm1
; X86-SSE41-NEXT: pxor {{\.LCPI.*}}, %xmm1 ; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE41-NEXT: pxor {{\.LCPI.*}}, %xmm0 ; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE41-NEXT: por %xmm1, %xmm0 ; X86-SSE41-NEXT: por %xmm1, %xmm0
; X86-SSE41-NEXT: ptest %xmm0, %xmm0 ; X86-SSE41-NEXT: ptest %xmm0, %xmm0
; X86-SSE41-NEXT: setne %al ; X86-SSE41-NEXT: setne %al
; X86-SSE41-NEXT: retl ; X86-SSE41-NEXT: retl
; ;
; X64-SSE2-LABEL: length31_eq_const: ; X64-SSE2-LABEL: length31_eq_const:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: movdqu (%rdi), %xmm0 ; X64-SSE2-NEXT: movdqu (%rdi), %xmm0
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; X86-SSE1-NEXT: setne %al ; X86-SSE1-NEXT: setne %al
; X86-SSE1-NEXT: retl ; X86-SSE1-NEXT: retl
; ;
; X86-SSE2-LABEL: length32_eq_const: ; X86-SSE2-LABEL: length32_eq_const:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0 ; X86-SSE2-NEXT: movdqu (%eax), %xmm0
; X86-SSE2-NEXT: movdqu 16(%eax), %xmm1 ; X86-SSE2-NEXT: movdqu 16(%eax), %xmm1
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0 ; X86-SSE2-NEXT: pand %xmm1, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax ; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF ; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
; X86-SSE2-NEXT: setne %al ; X86-SSE2-NEXT: setne %al
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-SSE41-LABEL: length32_eq_const: ; X86-SSE41-LABEL: length32_eq_const:
; X86-SSE41: # %bb.0: ; X86-SSE41: # %bb.0:
; X86-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE41-NEXT: movdqu (%eax), %xmm0 ; X86-SSE41-NEXT: movdqu (%eax), %xmm0
; X86-SSE41-NEXT: movdqu 16(%eax), %xmm1 ; X86-SSE41-NEXT: movdqu 16(%eax), %xmm1
; X86-SSE41-NEXT: pxor {{\.LCPI.*}}, %xmm1 ; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE41-NEXT: pxor {{\.LCPI.*}}, %xmm0 ; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE41-NEXT: por %xmm1, %xmm0 ; X86-SSE41-NEXT: por %xmm1, %xmm0
; X86-SSE41-NEXT: ptest %xmm0, %xmm0 ; X86-SSE41-NEXT: ptest %xmm0, %xmm0
; X86-SSE41-NEXT: setne %al ; X86-SSE41-NEXT: setne %al
; X86-SSE41-NEXT: retl ; X86-SSE41-NEXT: retl
; ;
; X64-SSE2-LABEL: length32_eq_const: ; X64-SSE2-LABEL: length32_eq_const:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: movdqu (%rdi), %xmm0 ; X64-SSE2-NEXT: movdqu (%rdi), %xmm0
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; X86-SSE1-NEXT: retl ; X86-SSE1-NEXT: retl
; ;
; X86-SSE2-LABEL: length48_eq_const: ; X86-SSE2-LABEL: length48_eq_const:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0 ; X86-SSE2-NEXT: movdqu (%eax), %xmm0
; X86-SSE2-NEXT: movdqu 16(%eax), %xmm1 ; X86-SSE2-NEXT: movdqu 16(%eax), %xmm1
; X86-SSE2-NEXT: movdqu 32(%eax), %xmm2 ; X86-SSE2-NEXT: movdqu 32(%eax), %xmm2
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm2 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: pand %xmm1, %xmm2 ; X86-SSE2-NEXT: pand %xmm1, %xmm2
; X86-SSE2-NEXT: pand %xmm0, %xmm2 ; X86-SSE2-NEXT: pand %xmm0, %xmm2
; X86-SSE2-NEXT: pmovmskb %xmm2, %eax ; X86-SSE2-NEXT: pmovmskb %xmm2, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF ; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
; X86-SSE2-NEXT: setne %al ; X86-SSE2-NEXT: setne %al
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-SSE41-LABEL: length48_eq_const: ; X86-SSE41-LABEL: length48_eq_const:
; X86-SSE41: # %bb.0: ; X86-SSE41: # %bb.0:
; X86-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE41-NEXT: movdqu (%eax), %xmm0 ; X86-SSE41-NEXT: movdqu (%eax), %xmm0
; X86-SSE41-NEXT: movdqu 16(%eax), %xmm1 ; X86-SSE41-NEXT: movdqu 16(%eax), %xmm1
; X86-SSE41-NEXT: movdqu 32(%eax), %xmm2 ; X86-SSE41-NEXT: movdqu 32(%eax), %xmm2
; X86-SSE41-NEXT: pxor {{\.LCPI.*}}, %xmm1 ; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE41-NEXT: pxor {{\.LCPI.*}}, %xmm0 ; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE41-NEXT: pxor {{\.LCPI.*}}, %xmm2 ; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE41-NEXT: por %xmm1, %xmm2 ; X86-SSE41-NEXT: por %xmm1, %xmm2
; X86-SSE41-NEXT: por %xmm0, %xmm2 ; X86-SSE41-NEXT: por %xmm0, %xmm2
; X86-SSE41-NEXT: ptest %xmm2, %xmm2 ; X86-SSE41-NEXT: ptest %xmm2, %xmm2
; X86-SSE41-NEXT: setne %al ; X86-SSE41-NEXT: setne %al
; X86-SSE41-NEXT: retl ; X86-SSE41-NEXT: retl
; ;
; X64-SSE2-LABEL: length48_eq_const: ; X64-SSE2-LABEL: length48_eq_const:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
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; ;
; X86-SSE2-LABEL: length63_eq_const: ; X86-SSE2-LABEL: length63_eq_const:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0 ; X86-SSE2-NEXT: movdqu (%eax), %xmm0
; X86-SSE2-NEXT: movdqu 16(%eax), %xmm1 ; X86-SSE2-NEXT: movdqu 16(%eax), %xmm1
; X86-SSE2-NEXT: movdqu 32(%eax), %xmm2 ; X86-SSE2-NEXT: movdqu 32(%eax), %xmm2
; X86-SSE2-NEXT: movdqu 47(%eax), %xmm3 ; X86-SSE2-NEXT: movdqu 47(%eax), %xmm3
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm3 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm3
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm2 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: pand %xmm3, %xmm2 ; X86-SSE2-NEXT: pand %xmm3, %xmm2
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pand %xmm2, %xmm1 ; X86-SSE2-NEXT: pand %xmm2, %xmm1
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0 ; X86-SSE2-NEXT: pand %xmm1, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax ; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF ; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
; X86-SSE2-NEXT: sete %al ; X86-SSE2-NEXT: sete %al
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-SSE41-LABEL: length63_eq_const: ; X86-SSE41-LABEL: length63_eq_const:
; X86-SSE41: # %bb.0: ; X86-SSE41: # %bb.0:
; X86-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE41-NEXT: movdqu (%eax), %xmm0 ; X86-SSE41-NEXT: movdqu (%eax), %xmm0
; X86-SSE41-NEXT: movdqu 16(%eax), %xmm1 ; X86-SSE41-NEXT: movdqu 16(%eax), %xmm1
; X86-SSE41-NEXT: movdqu 32(%eax), %xmm2 ; X86-SSE41-NEXT: movdqu 32(%eax), %xmm2
; X86-SSE41-NEXT: movdqu 47(%eax), %xmm3 ; X86-SSE41-NEXT: movdqu 47(%eax), %xmm3
; X86-SSE41-NEXT: pxor {{\.LCPI.*}}, %xmm3 ; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm3
; X86-SSE41-NEXT: pxor {{\.LCPI.*}}, %xmm2 ; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE41-NEXT: por %xmm3, %xmm2 ; X86-SSE41-NEXT: por %xmm3, %xmm2
; X86-SSE41-NEXT: pxor {{\.LCPI.*}}, %xmm1 ; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE41-NEXT: por %xmm2, %xmm1 ; X86-SSE41-NEXT: por %xmm2, %xmm1
; X86-SSE41-NEXT: pxor {{\.LCPI.*}}, %xmm0 ; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE41-NEXT: por %xmm1, %xmm0 ; X86-SSE41-NEXT: por %xmm1, %xmm0
; X86-SSE41-NEXT: ptest %xmm0, %xmm0 ; X86-SSE41-NEXT: ptest %xmm0, %xmm0
; X86-SSE41-NEXT: sete %al ; X86-SSE41-NEXT: sete %al
; X86-SSE41-NEXT: retl ; X86-SSE41-NEXT: retl
; ;
; X64-SSE2-LABEL: length63_eq_const: ; X64-SSE2-LABEL: length63_eq_const:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: movdqu (%rdi), %xmm0 ; X64-SSE2-NEXT: movdqu (%rdi), %xmm0
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; ;
; X86-SSE2-LABEL: length64_eq_const: ; X86-SSE2-LABEL: length64_eq_const:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0 ; X86-SSE2-NEXT: movdqu (%eax), %xmm0
; X86-SSE2-NEXT: movdqu 16(%eax), %xmm1 ; X86-SSE2-NEXT: movdqu 16(%eax), %xmm1
; X86-SSE2-NEXT: movdqu 32(%eax), %xmm2 ; X86-SSE2-NEXT: movdqu 32(%eax), %xmm2
; X86-SSE2-NEXT: movdqu 48(%eax), %xmm3 ; X86-SSE2-NEXT: movdqu 48(%eax), %xmm3
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm3 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm3
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm2 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: pand %xmm3, %xmm2 ; X86-SSE2-NEXT: pand %xmm3, %xmm2
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pand %xmm2, %xmm1 ; X86-SSE2-NEXT: pand %xmm2, %xmm1
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0 ; X86-SSE2-NEXT: pand %xmm1, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax ; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF ; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
; X86-SSE2-NEXT: sete %al ; X86-SSE2-NEXT: sete %al
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-SSE41-LABEL: length64_eq_const: ; X86-SSE41-LABEL: length64_eq_const:
; X86-SSE41: # %bb.0: ; X86-SSE41: # %bb.0:
; X86-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE41-NEXT: movdqu (%eax), %xmm0 ; X86-SSE41-NEXT: movdqu (%eax), %xmm0
; X86-SSE41-NEXT: movdqu 16(%eax), %xmm1 ; X86-SSE41-NEXT: movdqu 16(%eax), %xmm1
; X86-SSE41-NEXT: movdqu 32(%eax), %xmm2 ; X86-SSE41-NEXT: movdqu 32(%eax), %xmm2
; X86-SSE41-NEXT: movdqu 48(%eax), %xmm3 ; X86-SSE41-NEXT: movdqu 48(%eax), %xmm3
; X86-SSE41-NEXT: pxor {{\.LCPI.*}}, %xmm3 ; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm3
; X86-SSE41-NEXT: pxor {{\.LCPI.*}}, %xmm2 ; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE41-NEXT: por %xmm3, %xmm2 ; X86-SSE41-NEXT: por %xmm3, %xmm2
; X86-SSE41-NEXT: pxor {{\.LCPI.*}}, %xmm1 ; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE41-NEXT: por %xmm2, %xmm1 ; X86-SSE41-NEXT: por %xmm2, %xmm1
; X86-SSE41-NEXT: pxor {{\.LCPI.*}}, %xmm0 ; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE41-NEXT: por %xmm1, %xmm0 ; X86-SSE41-NEXT: por %xmm1, %xmm0
; X86-SSE41-NEXT: ptest %xmm0, %xmm0 ; X86-SSE41-NEXT: ptest %xmm0, %xmm0
; X86-SSE41-NEXT: sete %al ; X86-SSE41-NEXT: sete %al
; X86-SSE41-NEXT: retl ; X86-SSE41-NEXT: retl
; ;
; X64-SSE2-LABEL: length64_eq_const: ; X64-SSE2-LABEL: length64_eq_const:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: movdqu (%rdi), %xmm0 ; X64-SSE2-NEXT: movdqu (%rdi), %xmm0
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llvm/test/CodeGen/X86/memcmp-optsize.ll

Show First 20 Lines • Show All 584 Lines • ▼ Show 20 Lines
; X86-NOSSE-NEXT: testl %eax, %eax ; X86-NOSSE-NEXT: testl %eax, %eax
; X86-NOSSE-NEXT: sete %al ; X86-NOSSE-NEXT: sete %al
; X86-NOSSE-NEXT: retl ; X86-NOSSE-NEXT: retl
; ;
; X86-SSE2-LABEL: length16_eq_const: ; X86-SSE2-LABEL: length16_eq_const:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0 ; X86-SSE2-NEXT: movdqu (%eax), %xmm0
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax ; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF ; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
; X86-SSE2-NEXT: sete %al ; X86-SSE2-NEXT: sete %al
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X64-SSE2-LABEL: length16_eq_const: ; X64-SSE2-LABEL: length16_eq_const:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: movdqu (%rdi), %xmm0 ; X64-SSE2-NEXT: movdqu (%rdi), %xmm0
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; X86-NOSSE-NEXT: setne %al ; X86-NOSSE-NEXT: setne %al
; X86-NOSSE-NEXT: retl ; X86-NOSSE-NEXT: retl
; ;
; X86-SSE2-LABEL: length24_eq_const: ; X86-SSE2-LABEL: length24_eq_const:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0 ; X86-SSE2-NEXT: movdqu (%eax), %xmm0
; X86-SSE2-NEXT: movdqu 8(%eax), %xmm1 ; X86-SSE2-NEXT: movdqu 8(%eax), %xmm1
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0 ; X86-SSE2-NEXT: pand %xmm1, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax ; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF ; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
; X86-SSE2-NEXT: setne %al ; X86-SSE2-NEXT: setne %al
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X64-SSE2-LABEL: length24_eq_const: ; X64-SSE2-LABEL: length24_eq_const:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
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; X86-NOSSE-NEXT: setne %al ; X86-NOSSE-NEXT: setne %al
; X86-NOSSE-NEXT: retl ; X86-NOSSE-NEXT: retl
; ;
; X86-SSE2-LABEL: length32_eq_const: ; X86-SSE2-LABEL: length32_eq_const:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0 ; X86-SSE2-NEXT: movdqu (%eax), %xmm0
; X86-SSE2-NEXT: movdqu 16(%eax), %xmm1 ; X86-SSE2-NEXT: movdqu 16(%eax), %xmm1
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0 ; X86-SSE2-NEXT: pand %xmm1, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax ; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF ; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
; X86-SSE2-NEXT: setne %al ; X86-SSE2-NEXT: setne %al
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X64-SSE2-LABEL: length32_eq_const: ; X64-SSE2-LABEL: length32_eq_const:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
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llvm/test/CodeGen/X86/memcmp-pgso.ll

Show First 20 Lines • Show All 584 Lines • ▼ Show 20 Lines
; X86-NOSSE-NEXT: testl %eax, %eax ; X86-NOSSE-NEXT: testl %eax, %eax
; X86-NOSSE-NEXT: sete %al ; X86-NOSSE-NEXT: sete %al
; X86-NOSSE-NEXT: retl ; X86-NOSSE-NEXT: retl
; ;
; X86-SSE2-LABEL: length16_eq_const: ; X86-SSE2-LABEL: length16_eq_const:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0 ; X86-SSE2-NEXT: movdqu (%eax), %xmm0
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax ; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF ; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
; X86-SSE2-NEXT: sete %al ; X86-SSE2-NEXT: sete %al
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X64-SSE2-LABEL: length16_eq_const: ; X64-SSE2-LABEL: length16_eq_const:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: movdqu (%rdi), %xmm0 ; X64-SSE2-NEXT: movdqu (%rdi), %xmm0
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; X86-NOSSE-NEXT: setne %al ; X86-NOSSE-NEXT: setne %al
; X86-NOSSE-NEXT: retl ; X86-NOSSE-NEXT: retl
; ;
; X86-SSE2-LABEL: length24_eq_const: ; X86-SSE2-LABEL: length24_eq_const:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0 ; X86-SSE2-NEXT: movdqu (%eax), %xmm0
; X86-SSE2-NEXT: movdqu 8(%eax), %xmm1 ; X86-SSE2-NEXT: movdqu 8(%eax), %xmm1
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0 ; X86-SSE2-NEXT: pand %xmm1, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax ; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF ; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
; X86-SSE2-NEXT: setne %al ; X86-SSE2-NEXT: setne %al
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X64-SSE2-LABEL: length24_eq_const: ; X64-SSE2-LABEL: length24_eq_const:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
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; X86-NOSSE-NEXT: setne %al ; X86-NOSSE-NEXT: setne %al
; X86-NOSSE-NEXT: retl ; X86-NOSSE-NEXT: retl
; ;
; X86-SSE2-LABEL: length32_eq_const: ; X86-SSE2-LABEL: length32_eq_const:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0 ; X86-SSE2-NEXT: movdqu (%eax), %xmm0
; X86-SSE2-NEXT: movdqu 16(%eax), %xmm1 ; X86-SSE2-NEXT: movdqu 16(%eax), %xmm1
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0 ; X86-SSE2-NEXT: pand %xmm1, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax ; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF ; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
; X86-SSE2-NEXT: setne %al ; X86-SSE2-NEXT: setne %al
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X64-SSE2-LABEL: length32_eq_const: ; X64-SSE2-LABEL: length32_eq_const:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
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llvm/test/CodeGen/X86/memcmp.ll

Show First 20 Lines • Show All 1,479 Lines • ▼ Show 20 Lines
; X86-SSE1-NEXT: testl %eax, %eax ; X86-SSE1-NEXT: testl %eax, %eax
; X86-SSE1-NEXT: sete %al ; X86-SSE1-NEXT: sete %al
; X86-SSE1-NEXT: retl ; X86-SSE1-NEXT: retl
; ;
; X86-SSE2-LABEL: length16_eq_const: ; X86-SSE2-LABEL: length16_eq_const:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0 ; X86-SSE2-NEXT: movdqu (%eax), %xmm0
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax ; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF ; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
; X86-SSE2-NEXT: sete %al ; X86-SSE2-NEXT: sete %al
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-SSE41-LABEL: length16_eq_const: ; X86-SSE41-LABEL: length16_eq_const:
; X86-SSE41: # %bb.0: ; X86-SSE41: # %bb.0:
; X86-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE41-NEXT: movdqu (%eax), %xmm0 ; X86-SSE41-NEXT: movdqu (%eax), %xmm0
; X86-SSE41-NEXT: pxor {{\.LCPI.*}}, %xmm0 ; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE41-NEXT: ptest %xmm0, %xmm0 ; X86-SSE41-NEXT: ptest %xmm0, %xmm0
; X86-SSE41-NEXT: sete %al ; X86-SSE41-NEXT: sete %al
; X86-SSE41-NEXT: retl ; X86-SSE41-NEXT: retl
; ;
; X64-SSE2-LABEL: length16_eq_const: ; X64-SSE2-LABEL: length16_eq_const:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: movdqu (%rdi), %xmm0 ; X64-SSE2-NEXT: movdqu (%rdi), %xmm0
; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pcmpeqb {{.*}}(%rip), %xmm0
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; X86-SSE1-NEXT: setne %al ; X86-SSE1-NEXT: setne %al
; X86-SSE1-NEXT: retl ; X86-SSE1-NEXT: retl
; ;
; X86-SSE2-LABEL: length24_eq_const: ; X86-SSE2-LABEL: length24_eq_const:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0 ; X86-SSE2-NEXT: movdqu (%eax), %xmm0
; X86-SSE2-NEXT: movdqu 8(%eax), %xmm1 ; X86-SSE2-NEXT: movdqu 8(%eax), %xmm1
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0 ; X86-SSE2-NEXT: pand %xmm1, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax ; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF ; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
; X86-SSE2-NEXT: setne %al ; X86-SSE2-NEXT: setne %al
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-SSE41-LABEL: length24_eq_const: ; X86-SSE41-LABEL: length24_eq_const:
; X86-SSE41: # %bb.0: ; X86-SSE41: # %bb.0:
; X86-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE41-NEXT: movdqu (%eax), %xmm0 ; X86-SSE41-NEXT: movdqu (%eax), %xmm0
; X86-SSE41-NEXT: movdqu 8(%eax), %xmm1 ; X86-SSE41-NEXT: movdqu 8(%eax), %xmm1
; X86-SSE41-NEXT: pxor {{\.LCPI.*}}, %xmm1 ; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE41-NEXT: pxor {{\.LCPI.*}}, %xmm0 ; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE41-NEXT: por %xmm1, %xmm0 ; X86-SSE41-NEXT: por %xmm1, %xmm0
; X86-SSE41-NEXT: ptest %xmm0, %xmm0 ; X86-SSE41-NEXT: ptest %xmm0, %xmm0
; X86-SSE41-NEXT: setne %al ; X86-SSE41-NEXT: setne %al
; X86-SSE41-NEXT: retl ; X86-SSE41-NEXT: retl
; ;
; X64-SSE2-LABEL: length24_eq_const: ; X64-SSE2-LABEL: length24_eq_const:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: movdqu (%rdi), %xmm0 ; X64-SSE2-NEXT: movdqu (%rdi), %xmm0
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; X86-SSE1-NEXT: setne %al ; X86-SSE1-NEXT: setne %al
; X86-SSE1-NEXT: retl ; X86-SSE1-NEXT: retl
; ;
; X86-SSE2-LABEL: length31_eq_const: ; X86-SSE2-LABEL: length31_eq_const:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0 ; X86-SSE2-NEXT: movdqu (%eax), %xmm0
; X86-SSE2-NEXT: movdqu 15(%eax), %xmm1 ; X86-SSE2-NEXT: movdqu 15(%eax), %xmm1
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0 ; X86-SSE2-NEXT: pand %xmm1, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax ; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF ; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
; X86-SSE2-NEXT: setne %al ; X86-SSE2-NEXT: setne %al
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-SSE41-LABEL: length31_eq_const: ; X86-SSE41-LABEL: length31_eq_const:
; X86-SSE41: # %bb.0: ; X86-SSE41: # %bb.0:
; X86-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE41-NEXT: movdqu (%eax), %xmm0 ; X86-SSE41-NEXT: movdqu (%eax), %xmm0
; X86-SSE41-NEXT: movdqu 15(%eax), %xmm1 ; X86-SSE41-NEXT: movdqu 15(%eax), %xmm1
; X86-SSE41-NEXT: pxor {{\.LCPI.*}}, %xmm1 ; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE41-NEXT: pxor {{\.LCPI.*}}, %xmm0 ; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE41-NEXT: por %xmm1, %xmm0 ; X86-SSE41-NEXT: por %xmm1, %xmm0
; X86-SSE41-NEXT: ptest %xmm0, %xmm0 ; X86-SSE41-NEXT: ptest %xmm0, %xmm0
; X86-SSE41-NEXT: setne %al ; X86-SSE41-NEXT: setne %al
; X86-SSE41-NEXT: retl ; X86-SSE41-NEXT: retl
; ;
; X64-SSE2-LABEL: length31_eq_const: ; X64-SSE2-LABEL: length31_eq_const:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: movdqu (%rdi), %xmm0 ; X64-SSE2-NEXT: movdqu (%rdi), %xmm0
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; X86-SSE1-NEXT: setne %al ; X86-SSE1-NEXT: setne %al
; X86-SSE1-NEXT: retl ; X86-SSE1-NEXT: retl
; ;
; X86-SSE2-LABEL: length32_eq_const: ; X86-SSE2-LABEL: length32_eq_const:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE2-NEXT: movdqu (%eax), %xmm0 ; X86-SSE2-NEXT: movdqu (%eax), %xmm0
; X86-SSE2-NEXT: movdqu 16(%eax), %xmm1 ; X86-SSE2-NEXT: movdqu 16(%eax), %xmm1
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pcmpeqb {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pcmpeqb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0 ; X86-SSE2-NEXT: pand %xmm1, %xmm0
; X86-SSE2-NEXT: pmovmskb %xmm0, %eax ; X86-SSE2-NEXT: pmovmskb %xmm0, %eax
; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF ; X86-SSE2-NEXT: cmpl $65535, %eax # imm = 0xFFFF
; X86-SSE2-NEXT: setne %al ; X86-SSE2-NEXT: setne %al
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-SSE41-LABEL: length32_eq_const: ; X86-SSE41-LABEL: length32_eq_const:
; X86-SSE41: # %bb.0: ; X86-SSE41: # %bb.0:
; X86-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE41-NEXT: movdqu (%eax), %xmm0 ; X86-SSE41-NEXT: movdqu (%eax), %xmm0
; X86-SSE41-NEXT: movdqu 16(%eax), %xmm1 ; X86-SSE41-NEXT: movdqu 16(%eax), %xmm1
; X86-SSE41-NEXT: pxor {{\.LCPI.*}}, %xmm1 ; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE41-NEXT: pxor {{\.LCPI.*}}, %xmm0 ; X86-SSE41-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE41-NEXT: por %xmm1, %xmm0 ; X86-SSE41-NEXT: por %xmm1, %xmm0
; X86-SSE41-NEXT: ptest %xmm0, %xmm0 ; X86-SSE41-NEXT: ptest %xmm0, %xmm0
; X86-SSE41-NEXT: setne %al ; X86-SSE41-NEXT: setne %al
; X86-SSE41-NEXT: retl ; X86-SSE41-NEXT: retl
; ;
; X64-SSE2-LABEL: length32_eq_const: ; X64-SSE2-LABEL: length32_eq_const:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: movdqu (%rdi), %xmm0 ; X64-SSE2-NEXT: movdqu (%rdi), %xmm0
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llvm/test/CodeGen/X86/merge-consecutive-loads-256.ll

Show First 20 Lines • Show All 495 Lines • ▼ Show 20 Lines
; AVX-NEXT: vmovups (%rdi), %ymm0 ; AVX-NEXT: vmovups (%rdi), %ymm0
; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 ; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; X86-AVX-LABEL: merge_16i16_i16_0uu3zzuuuuuzCuEF: ; X86-AVX-LABEL: merge_16i16_i16_0uu3zzuuuuuzCuEF:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX-NEXT: vmovups (%eax), %ymm0 ; X86-AVX-NEXT: vmovups (%eax), %ymm0
; X86-AVX-NEXT: vandps {{\.LCPI.*}}, %ymm0, %ymm0 ; X86-AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
%ptr0 = getelementptr inbounds i16, i16* %ptr, i64 0 %ptr0 = getelementptr inbounds i16, i16* %ptr, i64 0
%ptr3 = getelementptr inbounds i16, i16* %ptr, i64 3 %ptr3 = getelementptr inbounds i16, i16* %ptr, i64 3
%ptrC = getelementptr inbounds i16, i16* %ptr, i64 12 %ptrC = getelementptr inbounds i16, i16* %ptr, i64 12
%ptrE = getelementptr inbounds i16, i16* %ptr, i64 14 %ptrE = getelementptr inbounds i16, i16* %ptr, i64 14
%ptrF = getelementptr inbounds i16, i16* %ptr, i64 15 %ptrF = getelementptr inbounds i16, i16* %ptr, i64 15
%val0 = load i16, i16* %ptr0 %val0 = load i16, i16* %ptr0
%val3 = load i16, i16* %ptr3 %val3 = load i16, i16* %ptr3
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llvm/test/CodeGen/X86/merge-consecutive-loads-512.ll

Show First 20 Lines • Show All 132 Lines • ▼ Show 20 Lines
; ALL-NEXT: vmovdqu64 8(%rdi), %zmm0 ; ALL-NEXT: vmovdqu64 8(%rdi), %zmm0
; ALL-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0 ; ALL-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
; ALL-NEXT: retq ; ALL-NEXT: retq
; ;
; X86-AVX512F-LABEL: merge_8f64_f64_1u3u5zu8: ; X86-AVX512F-LABEL: merge_8f64_f64_1u3u5zu8:
; X86-AVX512F: # %bb.0: ; X86-AVX512F: # %bb.0:
; X86-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX512F-NEXT: vmovdqu64 8(%eax), %zmm0 ; X86-AVX512F-NEXT: vmovdqu64 8(%eax), %zmm0
; X86-AVX512F-NEXT: vpandq {{\.LCPI.*}}, %zmm0, %zmm0 ; X86-AVX512F-NEXT: vpandq {{\.LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0
; X86-AVX512F-NEXT: retl ; X86-AVX512F-NEXT: retl
%ptr0 = getelementptr inbounds double, double* %ptr, i64 1 %ptr0 = getelementptr inbounds double, double* %ptr, i64 1
%ptr2 = getelementptr inbounds double, double* %ptr, i64 3 %ptr2 = getelementptr inbounds double, double* %ptr, i64 3
%ptr4 = getelementptr inbounds double, double* %ptr, i64 5 %ptr4 = getelementptr inbounds double, double* %ptr, i64 5
%ptr7 = getelementptr inbounds double, double* %ptr, i64 8 %ptr7 = getelementptr inbounds double, double* %ptr, i64 8
%val0 = load double, double* %ptr0 %val0 = load double, double* %ptr0
%val2 = load double, double* %ptr2 %val2 = load double, double* %ptr2
%val4 = load double, double* %ptr4 %val4 = load double, double* %ptr4
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; ALL-NEXT: vmovdqu64 8(%rdi), %zmm0 ; ALL-NEXT: vmovdqu64 8(%rdi), %zmm0
; ALL-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0 ; ALL-NEXT: vpandq {{.*}}(%rip), %zmm0, %zmm0
; ALL-NEXT: retq ; ALL-NEXT: retq
; ;
; X86-AVX512F-LABEL: merge_8i64_i64_1u3u5zu8: ; X86-AVX512F-LABEL: merge_8i64_i64_1u3u5zu8:
; X86-AVX512F: # %bb.0: ; X86-AVX512F: # %bb.0:
; X86-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX512F-NEXT: vmovdqu64 8(%eax), %zmm0 ; X86-AVX512F-NEXT: vmovdqu64 8(%eax), %zmm0
; X86-AVX512F-NEXT: vpandd {{\.LCPI.*}}, %zmm0, %zmm0 ; X86-AVX512F-NEXT: vpandd {{\.LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0
; X86-AVX512F-NEXT: retl ; X86-AVX512F-NEXT: retl
%ptr0 = getelementptr inbounds i64, i64* %ptr, i64 1 %ptr0 = getelementptr inbounds i64, i64* %ptr, i64 1
%ptr2 = getelementptr inbounds i64, i64* %ptr, i64 3 %ptr2 = getelementptr inbounds i64, i64* %ptr, i64 3
%ptr4 = getelementptr inbounds i64, i64* %ptr, i64 5 %ptr4 = getelementptr inbounds i64, i64* %ptr, i64 5
%ptr7 = getelementptr inbounds i64, i64* %ptr, i64 8 %ptr7 = getelementptr inbounds i64, i64* %ptr, i64 8
%val0 = load i64, i64* %ptr0 %val0 = load i64, i64* %ptr0
%val2 = load i64, i64* %ptr2 %val2 = load i64, i64* %ptr2
%val4 = load i64, i64* %ptr4 %val4 = load i64, i64* %ptr4
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; ALL-NEXT: vmovdqu64 (%rdi), %zmm0 ; ALL-NEXT: vmovdqu64 (%rdi), %zmm0
; ALL-NEXT: vpandd {{.*}}(%rip), %zmm0, %zmm0 ; ALL-NEXT: vpandd {{.*}}(%rip), %zmm0, %zmm0
; ALL-NEXT: retq ; ALL-NEXT: retq
; ;
; X86-AVX512F-LABEL: merge_16i32_i32_0uu3zzuuuuuzCuEF: ; X86-AVX512F-LABEL: merge_16i32_i32_0uu3zzuuuuuzCuEF:
; X86-AVX512F: # %bb.0: ; X86-AVX512F: # %bb.0:
; X86-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX512F-NEXT: vmovdqu64 (%eax), %zmm0 ; X86-AVX512F-NEXT: vmovdqu64 (%eax), %zmm0
; X86-AVX512F-NEXT: vpandd {{\.LCPI.*}}, %zmm0, %zmm0 ; X86-AVX512F-NEXT: vpandd {{\.LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0
; X86-AVX512F-NEXT: retl ; X86-AVX512F-NEXT: retl
%ptr0 = getelementptr inbounds i32, i32* %ptr, i64 0 %ptr0 = getelementptr inbounds i32, i32* %ptr, i64 0
%ptr3 = getelementptr inbounds i32, i32* %ptr, i64 3 %ptr3 = getelementptr inbounds i32, i32* %ptr, i64 3
%ptrC = getelementptr inbounds i32, i32* %ptr, i64 12 %ptrC = getelementptr inbounds i32, i32* %ptr, i64 12
%ptrE = getelementptr inbounds i32, i32* %ptr, i64 14 %ptrE = getelementptr inbounds i32, i32* %ptr, i64 14
%ptrF = getelementptr inbounds i32, i32* %ptr, i64 15 %ptrF = getelementptr inbounds i32, i32* %ptr, i64 15
%val0 = load i32, i32* %ptr0 %val0 = load i32, i32* %ptr0
%val3 = load i32, i32* %ptr3 %val3 = load i32, i32* %ptr3
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llvm/test/CodeGen/X86/mmx-arith.ll

Show All 27 Lines
; X32-NEXT: movq %mm0, (%eax) ; X32-NEXT: movq %mm0, (%eax)
; X32-NEXT: psubusb (%ecx), %mm0 ; X32-NEXT: psubusb (%ecx), %mm0
; X32-NEXT: movq %mm0, (%eax) ; X32-NEXT: movq %mm0, (%eax)
; X32-NEXT: movq2dq %mm0, %xmm0 ; X32-NEXT: movq2dq %mm0, %xmm0
; X32-NEXT: movq {{.*#+}} xmm1 = mem[0],zero ; X32-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
; X32-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; X32-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X32-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; X32-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X32-NEXT: pmullw %xmm0, %xmm1 ; X32-NEXT: pmullw %xmm0, %xmm1
; X32-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X32-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X32-NEXT: packuswb %xmm1, %xmm1 ; X32-NEXT: packuswb %xmm1, %xmm1
; X32-NEXT: movq %xmm1, (%eax) ; X32-NEXT: movq %xmm1, (%eax)
; X32-NEXT: movq {{.*#+}} xmm0 = mem[0],zero ; X32-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; X32-NEXT: pand %xmm1, %xmm0 ; X32-NEXT: pand %xmm1, %xmm0
; X32-NEXT: movq %xmm0, (%eax) ; X32-NEXT: movq %xmm0, (%eax)
; X32-NEXT: movq {{.*#+}} xmm1 = mem[0],zero ; X32-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
; X32-NEXT: por %xmm0, %xmm1 ; X32-NEXT: por %xmm0, %xmm1
; X32-NEXT: movq %xmm1, (%eax) ; X32-NEXT: movq %xmm1, (%eax)
▲ Show 20 Lines • Show All 608 Lines • ▼ Show 20 Lines
; X32: # %bb.0: # %entry ; X32: # %bb.0: # %entry
; X32-NEXT: pushl %ebp ; X32-NEXT: pushl %ebp
; X32-NEXT: .cfi_def_cfa_offset 8 ; X32-NEXT: .cfi_def_cfa_offset 8
; X32-NEXT: .cfi_offset %ebp, -8 ; X32-NEXT: .cfi_offset %ebp, -8
; X32-NEXT: movl %esp, %ebp ; X32-NEXT: movl %esp, %ebp
; X32-NEXT: .cfi_def_cfa_register %ebp ; X32-NEXT: .cfi_def_cfa_register %ebp
; X32-NEXT: andl $-8, %esp ; X32-NEXT: andl $-8, %esp
; X32-NEXT: subl $8, %esp ; X32-NEXT: subl $8, %esp
; X32-NEXT: movq {{\.LCPI.*}}, %mm0 # mm0 = 0x7AAAAAAA7AAAAAAA ; X32-NEXT: movq {{\.LCPI[0-9]+_[0-9]+}}, %mm0 # mm0 = 0x7AAAAAAA7AAAAAAA
; X32-NEXT: psrad $255, %mm0 ; X32-NEXT: psrad $255, %mm0
; X32-NEXT: movq %mm0, (%esp) ; X32-NEXT: movq %mm0, (%esp)
; X32-NEXT: movl (%esp), %eax ; X32-NEXT: movl (%esp), %eax
; X32-NEXT: movl {{[0-9]+}}(%esp), %edx ; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
; X32-NEXT: movl %ebp, %esp ; X32-NEXT: movl %ebp, %esp
; X32-NEXT: popl %ebp ; X32-NEXT: popl %ebp
; X32-NEXT: .cfi_def_cfa %esp, 4 ; X32-NEXT: .cfi_def_cfa %esp, 4
; X32-NEXT: retl ; X32-NEXT: retl
Show All 33 Lines

llvm/test/CodeGen/X86/mmx-fold-zero.ll

Show All 26 Lines
; X86-NEXT: movq %mm1, %mm7 ; X86-NEXT: movq %mm1, %mm7
; X86-NEXT: pmuludq %mm5, %mm7 ; X86-NEXT: pmuludq %mm5, %mm7
; X86-NEXT: paddw %mm4, %mm7 ; X86-NEXT: paddw %mm4, %mm7
; X86-NEXT: paddw %mm7, %mm5 ; X86-NEXT: paddw %mm7, %mm5
; X86-NEXT: paddw %mm5, %mm2 ; X86-NEXT: paddw %mm5, %mm2
; X86-NEXT: paddw %mm2, %mm0 ; X86-NEXT: paddw %mm2, %mm0
; X86-NEXT: paddw %mm6, %mm0 ; X86-NEXT: paddw %mm6, %mm0
; X86-NEXT: pmuludq %mm3, %mm0 ; X86-NEXT: pmuludq %mm3, %mm0
; X86-NEXT: paddw {{\.LCPI.*}}, %mm0 ; X86-NEXT: paddw {{\.LCPI[0-9]+_[0-9]+}}, %mm0
; X86-NEXT: paddw %mm1, %mm0 ; X86-NEXT: paddw %mm1, %mm0
; X86-NEXT: pmuludq %mm7, %mm0 ; X86-NEXT: pmuludq %mm7, %mm0
; X86-NEXT: pmuludq (%esp), %mm0 # 8-byte Folded Reload ; X86-NEXT: pmuludq (%esp), %mm0 # 8-byte Folded Reload
; X86-NEXT: paddw %mm5, %mm0 ; X86-NEXT: paddw %mm5, %mm0
; X86-NEXT: paddw %mm2, %mm0 ; X86-NEXT: paddw %mm2, %mm0
; X86-NEXT: movq2dq %mm0, %xmm0 ; X86-NEXT: movq2dq %mm0, %xmm0
; X86-NEXT: movsd %xmm0, {{[0-9]+}}(%esp) ; X86-NEXT: movsd %xmm0, {{[0-9]+}}(%esp)
; X86-NEXT: fldl {{[0-9]+}}(%esp) ; X86-NEXT: fldl {{[0-9]+}}(%esp)
Show All 21 Lines
; X64-NEXT: movq %mm1, %mm7 ; X64-NEXT: movq %mm1, %mm7
; X64-NEXT: pmuludq %mm5, %mm7 ; X64-NEXT: pmuludq %mm5, %mm7
; X64-NEXT: paddw %mm4, %mm7 ; X64-NEXT: paddw %mm4, %mm7
; X64-NEXT: paddw %mm7, %mm5 ; X64-NEXT: paddw %mm7, %mm5
; X64-NEXT: paddw %mm5, %mm2 ; X64-NEXT: paddw %mm5, %mm2
; X64-NEXT: paddw %mm2, %mm0 ; X64-NEXT: paddw %mm2, %mm0
; X64-NEXT: paddw %mm6, %mm0 ; X64-NEXT: paddw %mm6, %mm0
; X64-NEXT: pmuludq %mm3, %mm0 ; X64-NEXT: pmuludq %mm3, %mm0
; X64-NEXT: paddw {{\.LCPI.*}}, %mm0 ; X64-NEXT: paddw {{\.LCPI[0-9]+_[0-9]+}}, %mm0
; X64-NEXT: paddw %mm1, %mm0 ; X64-NEXT: paddw %mm1, %mm0
; X64-NEXT: pmuludq %mm7, %mm0 ; X64-NEXT: pmuludq %mm7, %mm0
; X64-NEXT: pmuludq {{[-0-9]+}}(%r{{[sb]}}p), %mm0 # 8-byte Folded Reload ; X64-NEXT: pmuludq {{[-0-9]+}}(%r{{[sb]}}p), %mm0 # 8-byte Folded Reload
; X64-NEXT: paddw %mm5, %mm0 ; X64-NEXT: paddw %mm5, %mm0
; X64-NEXT: paddw %mm2, %mm0 ; X64-NEXT: paddw %mm2, %mm0
; X64-NEXT: movq2dq %mm0, %xmm0 ; X64-NEXT: movq2dq %mm0, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%5 = bitcast double %0 to x86_mmx %5 = bitcast double %0 to x86_mmx
Show All 28 Lines

llvm/test/CodeGen/X86/neg_fp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -mattr=+sse4.1 | FileCheck %s ; RUN: llc < %s -mtriple=i686-- -mattr=+sse4.1 | FileCheck %s
; Test that when we don't -enable-unsafe-fp-math, we don't do the optimization ; Test that when we don't -enable-unsafe-fp-math, we don't do the optimization
; -0 - (A - B) to (B - A) because A==B, -0 != 0 ; -0 - (A - B) to (B - A) because A==B, -0 != 0
define float @negfp(float %a, float %b) nounwind { define float @negfp(float %a, float %b) nounwind {
; CHECK-LABEL: negfp: ; CHECK-LABEL: negfp:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %eax ; CHECK-NEXT: pushl %eax
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: subss {{[0-9]+}}(%esp), %xmm0 ; CHECK-NEXT: subss {{[0-9]+}}(%esp), %xmm0
; CHECK-NEXT: xorps {{\.LCPI.*}}, %xmm0 ; CHECK-NEXT: xorps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; CHECK-NEXT: movss %xmm0, (%esp) ; CHECK-NEXT: movss %xmm0, (%esp)
; CHECK-NEXT: flds (%esp) ; CHECK-NEXT: flds (%esp)
; CHECK-NEXT: popl %eax ; CHECK-NEXT: popl %eax
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
%sub = fsub float %a, %b ; <float> [#uses=1] %sub = fsub float %a, %b ; <float> [#uses=1]
%neg = fsub float -0.000000e+00, %sub ; <float> [#uses=1] %neg = fsub float -0.000000e+00, %sub ; <float> [#uses=1]
ret float %neg ret float %neg
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llvm/test/CodeGen/X86/nontemporal.ll

Show All 14 Lines
; X86-SSE-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero ; X86-SSE-NEXT: movsd {{.*#+}} xmm3 = mem[0],zero
; X86-SSE-NEXT: movl 12(%ebp), %ecx ; X86-SSE-NEXT: movl 12(%ebp), %ecx
; X86-SSE-NEXT: movdqa 56(%ebp), %xmm4 ; X86-SSE-NEXT: movdqa 56(%ebp), %xmm4
; X86-SSE-NEXT: movdqa 40(%ebp), %xmm5 ; X86-SSE-NEXT: movdqa 40(%ebp), %xmm5
; X86-SSE-NEXT: movdqa 24(%ebp), %xmm6 ; X86-SSE-NEXT: movdqa 24(%ebp), %xmm6
; X86-SSE-NEXT: movl 8(%ebp), %esi ; X86-SSE-NEXT: movl 8(%ebp), %esi
; X86-SSE-NEXT: movl 80(%ebp), %edx ; X86-SSE-NEXT: movl 80(%ebp), %edx
; X86-SSE-NEXT: movl (%edx), %eax ; X86-SSE-NEXT: movl (%edx), %eax
; X86-SSE-NEXT: addps {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: addps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movntps %xmm0, (%esi) ; X86-SSE-NEXT: movntps %xmm0, (%esi)
; X86-SSE-NEXT: paddq {{\.LCPI.*}}, %xmm2 ; X86-SSE-NEXT: paddq {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE-NEXT: addl (%edx), %eax ; X86-SSE-NEXT: addl (%edx), %eax
; X86-SSE-NEXT: movntdq %xmm2, (%esi) ; X86-SSE-NEXT: movntdq %xmm2, (%esi)
; X86-SSE-NEXT: addpd {{\.LCPI.*}}, %xmm1 ; X86-SSE-NEXT: addpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE-NEXT: addl (%edx), %eax ; X86-SSE-NEXT: addl (%edx), %eax
; X86-SSE-NEXT: movntpd %xmm1, (%esi) ; X86-SSE-NEXT: movntpd %xmm1, (%esi)
; X86-SSE-NEXT: paddd {{\.LCPI.*}}, %xmm6 ; X86-SSE-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm6
; X86-SSE-NEXT: addl (%edx), %eax ; X86-SSE-NEXT: addl (%edx), %eax
; X86-SSE-NEXT: movntdq %xmm6, (%esi) ; X86-SSE-NEXT: movntdq %xmm6, (%esi)
; X86-SSE-NEXT: paddw {{\.LCPI.*}}, %xmm5 ; X86-SSE-NEXT: paddw {{\.LCPI[0-9]+_[0-9]+}}, %xmm5
; X86-SSE-NEXT: addl (%edx), %eax ; X86-SSE-NEXT: addl (%edx), %eax
; X86-SSE-NEXT: movntdq %xmm5, (%esi) ; X86-SSE-NEXT: movntdq %xmm5, (%esi)
; X86-SSE-NEXT: paddb {{\.LCPI.*}}, %xmm4 ; X86-SSE-NEXT: paddb {{\.LCPI[0-9]+_[0-9]+}}, %xmm4
; X86-SSE-NEXT: addl (%edx), %eax ; X86-SSE-NEXT: addl (%edx), %eax
; X86-SSE-NEXT: movntdq %xmm4, (%esi) ; X86-SSE-NEXT: movntdq %xmm4, (%esi)
; X86-SSE-NEXT: addl (%edx), %eax ; X86-SSE-NEXT: addl (%edx), %eax
; X86-SSE-NEXT: movntil %ecx, (%esi) ; X86-SSE-NEXT: movntil %ecx, (%esi)
; X86-SSE-NEXT: addl (%edx), %eax ; X86-SSE-NEXT: addl (%edx), %eax
; X86-SSE-NEXT: movsd %xmm3, (%esi) ; X86-SSE-NEXT: movsd %xmm3, (%esi)
; X86-SSE-NEXT: addl (%edx), %eax ; X86-SSE-NEXT: addl (%edx), %eax
; X86-SSE-NEXT: leal -4(%ebp), %esp ; X86-SSE-NEXT: leal -4(%ebp), %esp
Show All 11 Lines
; X86-AVX-NEXT: vmovsd {{.*#+}} xmm3 = mem[0],zero ; X86-AVX-NEXT: vmovsd {{.*#+}} xmm3 = mem[0],zero
; X86-AVX-NEXT: movl 12(%ebp), %ecx ; X86-AVX-NEXT: movl 12(%ebp), %ecx
; X86-AVX-NEXT: vmovdqa 56(%ebp), %xmm4 ; X86-AVX-NEXT: vmovdqa 56(%ebp), %xmm4
; X86-AVX-NEXT: vmovdqa 40(%ebp), %xmm5 ; X86-AVX-NEXT: vmovdqa 40(%ebp), %xmm5
; X86-AVX-NEXT: vmovdqa 24(%ebp), %xmm6 ; X86-AVX-NEXT: vmovdqa 24(%ebp), %xmm6
; X86-AVX-NEXT: movl 8(%ebp), %edx ; X86-AVX-NEXT: movl 8(%ebp), %edx
; X86-AVX-NEXT: movl 80(%ebp), %esi ; X86-AVX-NEXT: movl 80(%ebp), %esi
; X86-AVX-NEXT: movl (%esi), %eax ; X86-AVX-NEXT: movl (%esi), %eax
; X86-AVX-NEXT: vaddps {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vaddps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vmovntps %xmm0, (%edx) ; X86-AVX-NEXT: vmovntps %xmm0, (%edx)
; X86-AVX-NEXT: vpaddq {{\.LCPI.*}}, %xmm2, %xmm0 ; X86-AVX-NEXT: vpaddq {{\.LCPI[0-9]+_[0-9]+}}, %xmm2, %xmm0
; X86-AVX-NEXT: addl (%esi), %eax ; X86-AVX-NEXT: addl (%esi), %eax
; X86-AVX-NEXT: vmovntdq %xmm0, (%edx) ; X86-AVX-NEXT: vmovntdq %xmm0, (%edx)
; X86-AVX-NEXT: vaddpd {{\.LCPI.*}}, %xmm1, %xmm0 ; X86-AVX-NEXT: vaddpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm0
; X86-AVX-NEXT: addl (%esi), %eax ; X86-AVX-NEXT: addl (%esi), %eax
; X86-AVX-NEXT: vmovntpd %xmm0, (%edx) ; X86-AVX-NEXT: vmovntpd %xmm0, (%edx)
; X86-AVX-NEXT: vpaddd {{\.LCPI.*}}, %xmm6, %xmm0 ; X86-AVX-NEXT: vpaddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm6, %xmm0
; X86-AVX-NEXT: addl (%esi), %eax ; X86-AVX-NEXT: addl (%esi), %eax
; X86-AVX-NEXT: vmovntdq %xmm0, (%edx) ; X86-AVX-NEXT: vmovntdq %xmm0, (%edx)
; X86-AVX-NEXT: vpaddw {{\.LCPI.*}}, %xmm5, %xmm0 ; X86-AVX-NEXT: vpaddw {{\.LCPI[0-9]+_[0-9]+}}, %xmm5, %xmm0
; X86-AVX-NEXT: addl (%esi), %eax ; X86-AVX-NEXT: addl (%esi), %eax
; X86-AVX-NEXT: vmovntdq %xmm0, (%edx) ; X86-AVX-NEXT: vmovntdq %xmm0, (%edx)
; X86-AVX-NEXT: vpaddb {{\.LCPI.*}}, %xmm4, %xmm0 ; X86-AVX-NEXT: vpaddb {{\.LCPI[0-9]+_[0-9]+}}, %xmm4, %xmm0
; X86-AVX-NEXT: addl (%esi), %eax ; X86-AVX-NEXT: addl (%esi), %eax
; X86-AVX-NEXT: vmovntdq %xmm0, (%edx) ; X86-AVX-NEXT: vmovntdq %xmm0, (%edx)
; X86-AVX-NEXT: addl (%esi), %eax ; X86-AVX-NEXT: addl (%esi), %eax
; X86-AVX-NEXT: movntil %ecx, (%edx) ; X86-AVX-NEXT: movntil %ecx, (%edx)
; X86-AVX-NEXT: addl (%esi), %eax ; X86-AVX-NEXT: addl (%esi), %eax
; X86-AVX-NEXT: vmovsd %xmm3, (%edx) ; X86-AVX-NEXT: vmovsd %xmm3, (%edx)
; X86-AVX-NEXT: addl (%esi), %eax ; X86-AVX-NEXT: addl (%esi), %eax
; X86-AVX-NEXT: leal -4(%ebp), %esp ; X86-AVX-NEXT: leal -4(%ebp), %esp
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llvm/test/CodeGen/X86/packss.ll

Show First 20 Lines • Show All 115 Lines • ▼ Show 20 Lines; AVX2-NEXT: ret{{[l|q]}}
%2 = trunc <8 x i32> %1 to <8 x i16> %2 = trunc <8 x i32> %1 to <8 x i16>
ret <8 x i16> %2 ret <8 x i16> %2
} }
define <8 x i16> @trunc_ashr_v4i32_icmp_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind { define <8 x i16> @trunc_ashr_v4i32_icmp_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
; X86-SSE-LABEL: trunc_ashr_v4i32_icmp_v4i32: ; X86-SSE-LABEL: trunc_ashr_v4i32_icmp_v4i32:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: psrad $31, %xmm0 ; X86-SSE-NEXT: psrad $31, %xmm0
; X86-SSE-NEXT: pcmpgtd {{\.LCPI.*}}, %xmm1 ; X86-SSE-NEXT: pcmpgtd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE-NEXT: packssdw %xmm1, %xmm0 ; X86-SSE-NEXT: packssdw %xmm1, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X86-AVX-LABEL: trunc_ashr_v4i32_icmp_v4i32: ; X86-AVX-LABEL: trunc_ashr_v4i32_icmp_v4i32:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpsrad $31, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrad $31, %xmm0, %xmm0
; X86-AVX-NEXT: vpcmpgtd {{\.LCPI.*}}, %xmm1, %xmm1 ; X86-AVX-NEXT: vpcmpgtd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1, %xmm1
; X86-AVX-NEXT: vpackssdw %xmm1, %xmm0, %xmm0 ; X86-AVX-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE-LABEL: trunc_ashr_v4i32_icmp_v4i32: ; X64-SSE-LABEL: trunc_ashr_v4i32_icmp_v4i32:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: psrad $31, %xmm0 ; X64-SSE-NEXT: psrad $31, %xmm0
; X64-SSE-NEXT: pcmpgtd {{.*}}(%rip), %xmm1 ; X64-SSE-NEXT: pcmpgtd {{.*}}(%rip), %xmm1
; X64-SSE-NEXT: packssdw %xmm1, %xmm0 ; X64-SSE-NEXT: packssdw %xmm1, %xmm0
▲ Show 20 Lines • Show All 241 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/peep-test-1.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s ; RUN: llc < %s -mtriple=i686-- | FileCheck %s
define void @foo(i32 %n, double* nocapture %p) nounwind { define void @foo(i32 %n, double* nocapture %p) nounwind {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .p2align 4, 0x90
; CHECK-NEXT: .LBB0_1: # %bb ; CHECK-NEXT: .LBB0_1: # %bb
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: fldl (%eax,%ecx,8) ; CHECK-NEXT: fldl (%eax,%ecx,8)
; CHECK-NEXT: fmull {{\.LCPI.*}} ; CHECK-NEXT: fmull {{\.LCPI[0-9]+_[0-9]+}}
; CHECK-NEXT: fstpl (%eax,%ecx,8) ; CHECK-NEXT: fstpl (%eax,%ecx,8)
; CHECK-NEXT: decl %ecx ; CHECK-NEXT: decl %ecx
; CHECK-NEXT: js .LBB0_1 ; CHECK-NEXT: js .LBB0_1
; CHECK-NEXT: # %bb.2: # %return ; CHECK-NEXT: # %bb.2: # %return
; CHECK-NEXT: retl ; CHECK-NEXT: retl
br label %bb br label %bb
bb: bb:
Show All 14 Lines

llvm/test/CodeGen/X86/pointer-vector.ll

Show First 20 Lines • Show All 127 Lines • ▼ Show 20 Lines
define <4 x i32> @ICMP0(<4 x i8*>* %p0, <4 x i8*>* %p1) nounwind { define <4 x i32> @ICMP0(<4 x i8*>* %p0, <4 x i8*>* %p1) nounwind {
; CHECK-LABEL: ICMP0: ; CHECK-LABEL: ICMP0:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movdqa (%ecx), %xmm0 ; CHECK-NEXT: movdqa (%ecx), %xmm0
; CHECK-NEXT: pcmpgtd (%eax), %xmm0 ; CHECK-NEXT: pcmpgtd (%eax), %xmm0
; CHECK-NEXT: movaps {{.*#+}} xmm1 = [9,8,7,6] ; CHECK-NEXT: movaps {{.*#+}} xmm1 = [9,8,7,6]
; CHECK-NEXT: blendvps %xmm0, {{\.LCPI.*}}, %xmm1 ; CHECK-NEXT: blendvps %xmm0, {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; CHECK-NEXT: movaps %xmm1, %xmm0 ; CHECK-NEXT: movaps %xmm1, %xmm0
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
%g0 = load <4 x i8*>, <4 x i8*>* %p0 %g0 = load <4 x i8*>, <4 x i8*>* %p0
%g1 = load <4 x i8*>, <4 x i8*>* %p1 %g1 = load <4 x i8*>, <4 x i8*>* %p1
%k = icmp sgt <4 x i8*> %g0, %g1 %k = icmp sgt <4 x i8*> %g0, %g1
%j = select <4 x i1> %k, <4 x i32> <i32 0, i32 1, i32 2, i32 4>, <4 x i32> <i32 9, i32 8, i32 7, i32 6> %j = select <4 x i1> %k, <4 x i32> <i32 0, i32 1, i32 2, i32 4>, <4 x i32> <i32 9, i32 8, i32 7, i32 6>
ret <4 x i32> %j ret <4 x i32> %j
} }
define <4 x i32> @ICMP1(<4 x i8*>* %p0, <4 x i8*>* %p1) nounwind { define <4 x i32> @ICMP1(<4 x i8*>* %p0, <4 x i8*>* %p1) nounwind {
; CHECK-LABEL: ICMP1: ; CHECK-LABEL: ICMP1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK-NEXT: movdqa (%ecx), %xmm0 ; CHECK-NEXT: movdqa (%ecx), %xmm0
; CHECK-NEXT: pcmpeqd (%eax), %xmm0 ; CHECK-NEXT: pcmpeqd (%eax), %xmm0
; CHECK-NEXT: movaps {{.*#+}} xmm1 = [9,8,7,6] ; CHECK-NEXT: movaps {{.*#+}} xmm1 = [9,8,7,6]
; CHECK-NEXT: blendvps %xmm0, {{\.LCPI.*}}, %xmm1 ; CHECK-NEXT: blendvps %xmm0, {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; CHECK-NEXT: movaps %xmm1, %xmm0 ; CHECK-NEXT: movaps %xmm1, %xmm0
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
%g0 = load <4 x i8*>, <4 x i8*>* %p0 %g0 = load <4 x i8*>, <4 x i8*>* %p0
%g1 = load <4 x i8*>, <4 x i8*>* %p1 %g1 = load <4 x i8*>, <4 x i8*>* %p1
%k = icmp eq <4 x i8*> %g0, %g1 %k = icmp eq <4 x i8*> %g0, %g1
%j = select <4 x i1> %k, <4 x i32> <i32 0, i32 1, i32 2, i32 4>, <4 x i32> <i32 9, i32 8, i32 7, i32 6> %j = select <4 x i1> %k, <4 x i32> <i32 0, i32 1, i32 2, i32 4>, <4 x i32> <i32 9, i32 8, i32 7, i32 6>
ret <4 x i32> %j ret <4 x i32> %j
} }

llvm/test/CodeGen/X86/popcnt.ll

Show First 20 Lines • Show All 247 Lines • ▼ Show 20 Lines
; X64-POPCNT-NEXT: popcntq %rdi, %rax ; X64-POPCNT-NEXT: popcntq %rdi, %rax
; X64-POPCNT-NEXT: retq ; X64-POPCNT-NEXT: retq
; ;
; X86-SSE2-LABEL: cnt64: ; X86-SSE2-LABEL: cnt64:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero ; X86-SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; X86-SSE2-NEXT: movdqa %xmm0, %xmm1 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm1
; X86-SSE2-NEXT: psrlw $1, %xmm1 ; X86-SSE2-NEXT: psrlw $1, %xmm1
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: psubb %xmm1, %xmm0 ; X86-SSE2-NEXT: psubb %xmm1, %xmm0
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; X86-SSE2-NEXT: movdqa %xmm0, %xmm2 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm2
; X86-SSE2-NEXT: pand %xmm1, %xmm2 ; X86-SSE2-NEXT: pand %xmm1, %xmm2
; X86-SSE2-NEXT: psrlw $2, %xmm0 ; X86-SSE2-NEXT: psrlw $2, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0 ; X86-SSE2-NEXT: pand %xmm1, %xmm0
; X86-SSE2-NEXT: paddb %xmm2, %xmm0 ; X86-SSE2-NEXT: paddb %xmm2, %xmm0
; X86-SSE2-NEXT: movdqa %xmm0, %xmm1 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm1
; X86-SSE2-NEXT: psrlw $4, %xmm1 ; X86-SSE2-NEXT: psrlw $4, %xmm1
; X86-SSE2-NEXT: paddb %xmm0, %xmm1 ; X86-SSE2-NEXT: paddb %xmm0, %xmm1
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pxor %xmm0, %xmm0 ; X86-SSE2-NEXT: pxor %xmm0, %xmm0
; X86-SSE2-NEXT: psadbw %xmm1, %xmm0 ; X86-SSE2-NEXT: psadbw %xmm1, %xmm0
; X86-SSE2-NEXT: movd %xmm0, %eax ; X86-SSE2-NEXT: movd %xmm0, %eax
; X86-SSE2-NEXT: xorl %edx, %edx ; X86-SSE2-NEXT: xorl %edx, %edx
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-SSSE3-LABEL: cnt64: ; X86-SSSE3-LABEL: cnt64:
; X86-SSSE3: # %bb.0: ; X86-SSSE3: # %bb.0:
▲ Show 20 Lines • Show All 468 Lines • ▼ Show 20 Lines
; X64-POPCNT-NEXT: popcntq %rdi, %rax ; X64-POPCNT-NEXT: popcntq %rdi, %rax
; X64-POPCNT-NEXT: retq ; X64-POPCNT-NEXT: retq
; ;
; X86-SSE2-LABEL: cnt64_optsize: ; X86-SSE2-LABEL: cnt64_optsize:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero ; X86-SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; X86-SSE2-NEXT: movdqa %xmm0, %xmm1 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm1
; X86-SSE2-NEXT: psrlw $1, %xmm1 ; X86-SSE2-NEXT: psrlw $1, %xmm1
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: psubb %xmm1, %xmm0 ; X86-SSE2-NEXT: psubb %xmm1, %xmm0
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; X86-SSE2-NEXT: movdqa %xmm0, %xmm2 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm2
; X86-SSE2-NEXT: pand %xmm1, %xmm2 ; X86-SSE2-NEXT: pand %xmm1, %xmm2
; X86-SSE2-NEXT: psrlw $2, %xmm0 ; X86-SSE2-NEXT: psrlw $2, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0 ; X86-SSE2-NEXT: pand %xmm1, %xmm0
; X86-SSE2-NEXT: paddb %xmm2, %xmm0 ; X86-SSE2-NEXT: paddb %xmm2, %xmm0
; X86-SSE2-NEXT: movdqa %xmm0, %xmm1 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm1
; X86-SSE2-NEXT: psrlw $4, %xmm1 ; X86-SSE2-NEXT: psrlw $4, %xmm1
; X86-SSE2-NEXT: paddb %xmm0, %xmm1 ; X86-SSE2-NEXT: paddb %xmm0, %xmm1
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pxor %xmm0, %xmm0 ; X86-SSE2-NEXT: pxor %xmm0, %xmm0
; X86-SSE2-NEXT: psadbw %xmm1, %xmm0 ; X86-SSE2-NEXT: psadbw %xmm1, %xmm0
; X86-SSE2-NEXT: movd %xmm0, %eax ; X86-SSE2-NEXT: movd %xmm0, %eax
; X86-SSE2-NEXT: xorl %edx, %edx ; X86-SSE2-NEXT: xorl %edx, %edx
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-SSSE3-LABEL: cnt64_optsize: ; X86-SSSE3-LABEL: cnt64_optsize:
; X86-SSSE3: # %bb.0: ; X86-SSSE3: # %bb.0:
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; X64-POPCNT-NEXT: popcntq %rdi, %rax ; X64-POPCNT-NEXT: popcntq %rdi, %rax
; X64-POPCNT-NEXT: retq ; X64-POPCNT-NEXT: retq
; ;
; X86-SSE2-LABEL: cnt64_pgso: ; X86-SSE2-LABEL: cnt64_pgso:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero ; X86-SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; X86-SSE2-NEXT: movdqa %xmm0, %xmm1 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm1
; X86-SSE2-NEXT: psrlw $1, %xmm1 ; X86-SSE2-NEXT: psrlw $1, %xmm1
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: psubb %xmm1, %xmm0 ; X86-SSE2-NEXT: psubb %xmm1, %xmm0
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [51,51,51,51,51,51,51,51,51,51,51,51,51,51,51,51]
; X86-SSE2-NEXT: movdqa %xmm0, %xmm2 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm2
; X86-SSE2-NEXT: pand %xmm1, %xmm2 ; X86-SSE2-NEXT: pand %xmm1, %xmm2
; X86-SSE2-NEXT: psrlw $2, %xmm0 ; X86-SSE2-NEXT: psrlw $2, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0 ; X86-SSE2-NEXT: pand %xmm1, %xmm0
; X86-SSE2-NEXT: paddb %xmm2, %xmm0 ; X86-SSE2-NEXT: paddb %xmm2, %xmm0
; X86-SSE2-NEXT: movdqa %xmm0, %xmm1 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm1
; X86-SSE2-NEXT: psrlw $4, %xmm1 ; X86-SSE2-NEXT: psrlw $4, %xmm1
; X86-SSE2-NEXT: paddb %xmm0, %xmm1 ; X86-SSE2-NEXT: paddb %xmm0, %xmm1
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pxor %xmm0, %xmm0 ; X86-SSE2-NEXT: pxor %xmm0, %xmm0
; X86-SSE2-NEXT: psadbw %xmm1, %xmm0 ; X86-SSE2-NEXT: psadbw %xmm1, %xmm0
; X86-SSE2-NEXT: movd %xmm0, %eax ; X86-SSE2-NEXT: movd %xmm0, %eax
; X86-SSE2-NEXT: xorl %edx, %edx ; X86-SSE2-NEXT: xorl %edx, %edx
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-SSSE3-LABEL: cnt64_pgso: ; X86-SSSE3-LABEL: cnt64_pgso:
; X86-SSSE3: # %bb.0: ; X86-SSSE3: # %bb.0:
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llvm/test/CodeGen/X86/pr15309.ll

Show All 13 Lines
; CHECK-NEXT: movl 160(%ecx), %edi ; CHECK-NEXT: movl 160(%ecx), %edi
; CHECK-NEXT: movl 164(%ecx), %ecx ; CHECK-NEXT: movl 164(%ecx), %ecx
; CHECK-NEXT: movl %ecx, {{[0-9]+}}(%esp) ; CHECK-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl %edi, (%esp) ; CHECK-NEXT: movl %edi, (%esp)
; CHECK-NEXT: movl %esi, {{[0-9]+}}(%esp) ; CHECK-NEXT: movl %esi, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl %edx, {{[0-9]+}}(%esp) ; CHECK-NEXT: movl %edx, {{[0-9]+}}(%esp)
; CHECK-NEXT: shrl $31, %ecx ; CHECK-NEXT: shrl $31, %ecx
; CHECK-NEXT: fildll (%esp) ; CHECK-NEXT: fildll (%esp)
; CHECK-NEXT: fadds {{\.LCPI.*}}(,%ecx,4) ; CHECK-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; CHECK-NEXT: shrl $31, %esi ; CHECK-NEXT: shrl $31, %esi
; CHECK-NEXT: fildll {{[0-9]+}}(%esp) ; CHECK-NEXT: fildll {{[0-9]+}}(%esp)
; CHECK-NEXT: fadds {{\.LCPI.*}}(,%esi,4) ; CHECK-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%esi,4)
; CHECK-NEXT: fstps 84(%eax) ; CHECK-NEXT: fstps 84(%eax)
; CHECK-NEXT: fstps 80(%eax) ; CHECK-NEXT: fstps 80(%eax)
; CHECK-NEXT: addl $20, %esp ; CHECK-NEXT: addl $20, %esp
; CHECK-NEXT: popl %esi ; CHECK-NEXT: popl %esi
; CHECK-NEXT: popl %edi ; CHECK-NEXT: popl %edi
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%t0 = getelementptr <2 x i64>, <2 x i64>* %src, i32 10 %t0 = getelementptr <2 x i64>, <2 x i64>* %src, i32 10
%t1 = load <2 x i64>, <2 x i64>* %t0, align 16 %t1 = load <2 x i64>, <2 x i64>* %t0, align 16
%t2 = uitofp <2 x i64> %t1 to <2 x float> %t2 = uitofp <2 x i64> %t1 to <2 x float>
%t3 = getelementptr <2 x float>, <2 x float>* %dest, i32 10 %t3 = getelementptr <2 x float>, <2 x float>* %dest, i32 10
store <2 x float> %t2, <2 x float>* %t3, align 8 store <2 x float> %t2, <2 x float>* %t3, align 8
ret void ret void
} }

llvm/test/CodeGen/X86/pr34080-2.ll

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; CHECK-NEXT: shrl $31, %eax ; CHECK-NEXT: shrl $31, %eax
; CHECK-NEXT: sarl $5, %edx ; CHECK-NEXT: sarl $5, %edx
; CHECK-NEXT: addl %eax, %edx ; CHECK-NEXT: addl %eax, %edx
; CHECK-NEXT: addl 16(%ebx), %ecx ; CHECK-NEXT: addl 16(%ebx), %ecx
; CHECK-NEXT: addl %edi, %ecx ; CHECK-NEXT: addl %edi, %ecx
; CHECK-NEXT: leal 257(%ecx,%edx), %eax ; CHECK-NEXT: leal 257(%ecx,%edx), %eax
; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp) ; CHECK-NEXT: movl %eax, {{[0-9]+}}(%esp)
; CHECK-NEXT: fildl {{[0-9]+}}(%esp) ; CHECK-NEXT: fildl {{[0-9]+}}(%esp)
; CHECK-NEXT: fadds {{\.LCPI.*}} ; CHECK-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}
; CHECK-NEXT: fmuls {{\.LCPI.*}} ; CHECK-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; CHECK-NEXT: fnstcw {{[0-9]+}}(%esp) ; CHECK-NEXT: fnstcw {{[0-9]+}}(%esp)
; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: orl $3072, %eax # imm = 0xC00 ; CHECK-NEXT: orl $3072, %eax # imm = 0xC00
; CHECK-NEXT: movw %ax, {{[0-9]+}}(%esp) ; CHECK-NEXT: movw %ax, {{[0-9]+}}(%esp)
; CHECK-NEXT: fldcw {{[0-9]+}}(%esp) ; CHECK-NEXT: fldcw {{[0-9]+}}(%esp)
; CHECK-NEXT: fistpll {{[0-9]+}}(%esp) ; CHECK-NEXT: fistpll {{[0-9]+}}(%esp)
; CHECK-NEXT: fldcw {{[0-9]+}}(%esp) ; CHECK-NEXT: fldcw {{[0-9]+}}(%esp)
; CHECK-NEXT: movb $1, 36(%ebx) ; CHECK-NEXT: movb $1, 36(%ebx)
; CHECK-NEXT: imull $3600000, 20(%ebx), %eax # imm = 0x36EE80 ; CHECK-NEXT: imull $3600000, 20(%ebx), %eax # imm = 0x36EE80
; CHECK-NEXT: imull $60000, 24(%ebx), %ecx # imm = 0xEA60 ; CHECK-NEXT: imull $60000, 24(%ebx), %ecx # imm = 0xEA60
; CHECK-NEXT: addl %eax, %ecx ; CHECK-NEXT: addl %eax, %ecx
; CHECK-NEXT: fldl 28(%ebx) ; CHECK-NEXT: fldl 28(%ebx)
; CHECK-NEXT: fmuls {{\.LCPI.*}} ; CHECK-NEXT: fmuls {{\.LCPI[0-9]+_[0-9]+}}
; CHECK-NEXT: fnstcw {{[0-9]+}}(%esp) ; CHECK-NEXT: fnstcw {{[0-9]+}}(%esp)
; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: orl $3072, %eax # imm = 0xC00 ; CHECK-NEXT: orl $3072, %eax # imm = 0xC00
; CHECK-NEXT: movw %ax, {{[0-9]+}}(%esp) ; CHECK-NEXT: movw %ax, {{[0-9]+}}(%esp)
; CHECK-NEXT: movl %ecx, %eax ; CHECK-NEXT: movl %ecx, %eax
; CHECK-NEXT: sarl $31, %eax ; CHECK-NEXT: sarl $31, %eax
; CHECK-NEXT: fldcw {{[0-9]+}}(%esp) ; CHECK-NEXT: fldcw {{[0-9]+}}(%esp)
; CHECK-NEXT: fistpll {{[0-9]+}}(%esp) ; CHECK-NEXT: fistpll {{[0-9]+}}(%esp)
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llvm/test/CodeGen/X86/pr34605.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -mattr=avx512bw,avx512vl,avx512dq | FileCheck %s ; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -mattr=avx512bw,avx512vl,avx512dq | FileCheck %s
define void @pr34605(i8* nocapture %s, i32 %p) { define void @pr34605(i8* nocapture %s, i32 %p) {
; CHECK-LABEL: pr34605: ; CHECK-LABEL: pr34605:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: vpbroadcastd {{[0-9]+}}(%esp), %zmm0 ; CHECK-NEXT: vpbroadcastd {{[0-9]+}}(%esp), %zmm0
; CHECK-NEXT: vpcmpeqd {{\.LCPI.*}}, %zmm0, %k0 ; CHECK-NEXT: vpcmpeqd {{\.LCPI[0-9]+_[0-9]+}}, %zmm0, %k0
; CHECK-NEXT: vpcmpeqd {{\.LCPI.*}}, %zmm0, %k1 ; CHECK-NEXT: vpcmpeqd {{\.LCPI[0-9]+_[0-9]+}}, %zmm0, %k1
; CHECK-NEXT: kunpckwd %k0, %k1, %k0 ; CHECK-NEXT: kunpckwd %k0, %k1, %k0
; CHECK-NEXT: vpcmpeqd {{\.LCPI.*}}, %zmm0, %k1 ; CHECK-NEXT: vpcmpeqd {{\.LCPI[0-9]+_[0-9]+}}, %zmm0, %k1
; CHECK-NEXT: vpcmpeqd {{\.LCPI.*}}, %zmm0, %k2 ; CHECK-NEXT: vpcmpeqd {{\.LCPI[0-9]+_[0-9]+}}, %zmm0, %k2
; CHECK-NEXT: kunpckwd %k1, %k2, %k1 ; CHECK-NEXT: kunpckwd %k1, %k2, %k1
; CHECK-NEXT: kunpckdq %k0, %k1, %k0 ; CHECK-NEXT: kunpckdq %k0, %k1, %k0
; CHECK-NEXT: movl $1, %ecx ; CHECK-NEXT: movl $1, %ecx
; CHECK-NEXT: kmovd %ecx, %k1 ; CHECK-NEXT: kmovd %ecx, %k1
; CHECK-NEXT: kmovd %k1, %k1 ; CHECK-NEXT: kmovd %k1, %k1
; CHECK-NEXT: kandq %k1, %k0, %k1 ; CHECK-NEXT: kandq %k1, %k0, %k1
; CHECK-NEXT: vmovdqu8 {{\.LCPI.*}}, %zmm0 {%k1} {z} ; CHECK-NEXT: vmovdqu8 {{\.LCPI[0-9]+_[0-9]+}}, %zmm0 {%k1} {z}
; CHECK-NEXT: vmovdqu64 %zmm0, (%eax) ; CHECK-NEXT: vmovdqu64 %zmm0, (%eax)
; CHECK-NEXT: vpxor %xmm0, %xmm0, %xmm0 ; CHECK-NEXT: vpxor %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vmovdqu64 %zmm0, 64(%eax) ; CHECK-NEXT: vmovdqu64 %zmm0, 64(%eax)
; CHECK-NEXT: vmovdqu64 %zmm0, 128(%eax) ; CHECK-NEXT: vmovdqu64 %zmm0, 128(%eax)
; CHECK-NEXT: vmovdqu64 %zmm0, 192(%eax) ; CHECK-NEXT: vmovdqu64 %zmm0, 192(%eax)
; CHECK-NEXT: vmovdqu64 %zmm0, 256(%eax) ; CHECK-NEXT: vmovdqu64 %zmm0, 256(%eax)
; CHECK-NEXT: vmovdqu64 %zmm0, 320(%eax) ; CHECK-NEXT: vmovdqu64 %zmm0, 320(%eax)
; CHECK-NEXT: vmovdqu64 %zmm0, 384(%eax) ; CHECK-NEXT: vmovdqu64 %zmm0, 384(%eax)
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llvm/test/CodeGen/X86/pr40539.ll

Show All 35 Lines
define zeroext i1 @_Z8test_cosv() { define zeroext i1 @_Z8test_cosv() {
; CHECK-LABEL: _Z8test_cosv: ; CHECK-LABEL: _Z8test_cosv:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subl $8, %esp ; CHECK-NEXT: subl $8, %esp
; CHECK-NEXT: .cfi_def_cfa_offset 12 ; CHECK-NEXT: .cfi_def_cfa_offset 12
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: divss {{\.LCPI.*}}, %xmm0 ; CHECK-NEXT: divss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; CHECK-NEXT: movss %xmm0, {{[0-9]+}}(%esp) ; CHECK-NEXT: movss %xmm0, {{[0-9]+}}(%esp)
; CHECK-NEXT: flds {{[0-9]+}}(%esp) ; CHECK-NEXT: flds {{[0-9]+}}(%esp)
; CHECK-NEXT: #APP ; CHECK-NEXT: #APP
; CHECK-NEXT: fcos ; CHECK-NEXT: fcos
; CHECK-NEXT: #NO_APP ; CHECK-NEXT: #NO_APP
; CHECK-NEXT: fstps (%esp) ; CHECK-NEXT: fstps (%esp)
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: ucomiss %xmm0, %xmm1 ; CHECK-NEXT: ucomiss %xmm0, %xmm1
; CHECK-NEXT: setae %cl ; CHECK-NEXT: setae %cl
; CHECK-NEXT: ucomiss {{\.LCPI.*}}, %xmm0 ; CHECK-NEXT: ucomiss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; CHECK-NEXT: setae %al ; CHECK-NEXT: setae %al
; CHECK-NEXT: andb %cl, %al ; CHECK-NEXT: andb %cl, %al
; CHECK-NEXT: addl $8, %esp ; CHECK-NEXT: addl $8, %esp
; CHECK-NEXT: .cfi_def_cfa_offset 4 ; CHECK-NEXT: .cfi_def_cfa_offset 4
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
%0 = load float, float* @fpi, align 4 %0 = load float, float* @fpi, align 4
%div = fdiv float %0, 6.000000e+00 %div = fdiv float %0, 6.000000e+00
%1 = fpext float %div to x86_fp80 %1 = fpext float %div to x86_fp80
%2 = tail call x86_fp80 asm "fcos", "={st},0,~{dirflag},~{fpsr},~{flags}"(x86_fp80 %1) %2 = tail call x86_fp80 asm "fcos", "={st},0,~{dirflag},~{fpsr},~{flags}"(x86_fp80 %1)
%conv = fptrunc x86_fp80 %2 to float %conv = fptrunc x86_fp80 %2 to float
%cmp = fcmp ole float %conv, 0x3FEBD70A40000000 %cmp = fcmp ole float %conv, 0x3FEBD70A40000000
%cmp1 = fcmp oge float %conv, 0x3FEB851EC0000000 %cmp1 = fcmp oge float %conv, 0x3FEB851EC0000000
%or.cond = and i1 %cmp, %cmp1 %or.cond = and i1 %cmp, %cmp1
ret i1 %or.cond ret i1 %or.cond
} }

llvm/test/CodeGen/X86/pr40891.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=avx2 | FileCheck %s ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=avx2 | FileCheck %s
; Make sure this sequence doesn't hang in DAG combine. ; Make sure this sequence doesn't hang in DAG combine.
define <8 x i32> @foo(<8 x i64> %x, <4 x i64> %y) { define <8 x i32> @foo(<8 x i64> %x, <4 x i64> %y) {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vandps %ymm2, %ymm0, %ymm0 ; CHECK-NEXT: vandps %ymm2, %ymm0, %ymm0
; CHECK-NEXT: vandps {{\.LCPI.*}}, %ymm1, %ymm1 ; CHECK-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm1
; CHECK-NEXT: vperm2f128 {{.*#+}} ymm2 = ymm0[2,3],ymm1[2,3] ; CHECK-NEXT: vperm2f128 {{.*#+}} ymm2 = ymm0[2,3],ymm1[2,3]
; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; CHECK-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; CHECK-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,2],ymm2[0,2],ymm0[4,6],ymm2[4,6] ; CHECK-NEXT: vshufps {{.*#+}} ymm0 = ymm0[0,2],ymm2[0,2],ymm0[4,6],ymm2[4,6]
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%a = shufflevector <4 x i64> %y, <4 x i64> <i64 12345, i64 67890, i64 13579, i64 24680>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %a = shufflevector <4 x i64> %y, <4 x i64> <i64 12345, i64 67890, i64 13579, i64 24680>, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%b = and <8 x i64> %x, %a %b = and <8 x i64> %x, %a
%c = trunc <8 x i64> %b to <8 x i32> %c = trunc <8 x i64> %b to <8 x i32>
ret <8 x i32> %c ret <8 x i32> %c
} }

llvm/test/CodeGen/X86/pr46527.ll

Show All 16 Lines
; CHECK-NEXT: andb $1, %dl ; CHECK-NEXT: andb $1, %dl
; CHECK-NEXT: movzbl %dl, %edx ; CHECK-NEXT: movzbl %dl, %edx
; CHECK-NEXT: movd %edx, %xmm1 ; CHECK-NEXT: movd %edx, %xmm1
; CHECK-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; CHECK-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; CHECK-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7] ; CHECK-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,0,0,0,4,5,6,7]
; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,0,0] ; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
; CHECK-NEXT: paddb %xmm1, %xmm1 ; CHECK-NEXT: paddb %xmm1, %xmm1
; CHECK-NEXT: pxor %xmm0, %xmm1 ; CHECK-NEXT: pxor %xmm0, %xmm1
; CHECK-NEXT: pxor {{\.LCPI.*}}@GOTOFF(%eax), %xmm1 ; CHECK-NEXT: pxor {{\.LCPI[0-9]+_[0-9]+}}@GOTOFF(%eax), %xmm1
; CHECK-NEXT: movdqa %xmm1, (%ecx) ; CHECK-NEXT: movdqa %xmm1, (%ecx)
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
%0 = select i1 %flag, i8 0, i8 2 %0 = select i1 %flag, i8 0, i8 2
%1 = insertelement <16 x i8> undef, i8 %0, i32 0 %1 = insertelement <16 x i8> undef, i8 %0, i32 0
%2 = shufflevector <16 x i8> %1, <16 x i8> undef, <16 x i32> zeroinitializer %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <16 x i32> zeroinitializer
%3 = xor <16 x i8> %2, %in %3 = xor <16 x i8> %2, %in
%4 = xor <16 x i8> %3, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> %4 = xor <16 x i8> %3, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
store <16 x i8> %4, <16 x i8>* %out, align 16 store <16 x i8> %4, <16 x i8>* %out, align 16
ret void ret void
} }

llvm/test/CodeGen/X86/pr47299.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -O3 -x86-asm-syntax=intel -mtriple=x86_64-linux-generic-march=x86-64 -mcpu=skylake-avx512 < %s | FileCheck %s ; RUN: llc -O3 -x86-asm-syntax=intel -mtriple=x86_64-linux-generic-march=x86-64 -mcpu=skylake-avx512 < %s | FileCheck %s
declare <7 x i1> @llvm.get.active.lane.mask.v7i1.i64(i64, i64) declare <7 x i1> @llvm.get.active.lane.mask.v7i1.i64(i64, i64)
declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64, i64) declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64, i64)
declare <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64, i64) declare <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64, i64)
declare <64 x i1> @llvm.get.active.lane.mask.v64i1.i64(i64, i64) declare <64 x i1> @llvm.get.active.lane.mask.v64i1.i64(i64, i64)
declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32, i32) declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32, i32)
declare <64 x i1> @llvm.get.active.lane.mask.v64i1.i32(i32, i32) declare <64 x i1> @llvm.get.active.lane.mask.v64i1.i32(i32, i32)
define <7 x i1> @create_mask7(i64 %0) { define <7 x i1> @create_mask7(i64 %0) {
; CHECK-LABEL: create_mask7: ; CHECK-LABEL: create_mask7:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mov rax, rdi ; CHECK-NEXT: mov rax, rdi
; CHECK-NEXT: vpbroadcastq zmm0, rsi ; CHECK-NEXT: vpbroadcastq zmm0, rsi
; CHECK-NEXT: vpcmpnleuq k0, zmm0, zmmword ptr [rip + {{\.LCPI.*}}] ; CHECK-NEXT: vpcmpnleuq k0, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
; CHECK-NEXT: kshiftrb k1, k0, 6 ; CHECK-NEXT: kshiftrb k1, k0, 6
; CHECK-NEXT: kmovd r8d, k1 ; CHECK-NEXT: kmovd r8d, k1
; CHECK-NEXT: kshiftrb k1, k0, 5 ; CHECK-NEXT: kshiftrb k1, k0, 5
; CHECK-NEXT: kmovd r9d, k1 ; CHECK-NEXT: kmovd r9d, k1
; CHECK-NEXT: kshiftrb k1, k0, 4 ; CHECK-NEXT: kshiftrb k1, k0, 4
; CHECK-NEXT: kmovd r10d, k1 ; CHECK-NEXT: kmovd r10d, k1
; CHECK-NEXT: kshiftrb k1, k0, 3 ; CHECK-NEXT: kshiftrb k1, k0, 3
; CHECK-NEXT: kmovd edi, k1 ; CHECK-NEXT: kmovd edi, k1
Show All 27 Lines; CHECK-NEXT: ret
%2 = call <7 x i1> @llvm.get.active.lane.mask.v7i1.i64(i64 0, i64 %0) %2 = call <7 x i1> @llvm.get.active.lane.mask.v7i1.i64(i64 0, i64 %0)
ret <7 x i1> %2 ret <7 x i1> %2
} }
define <16 x i1> @create_mask16(i64 %0) { define <16 x i1> @create_mask16(i64 %0) {
; CHECK-LABEL: create_mask16: ; CHECK-LABEL: create_mask16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vpbroadcastq zmm0, rdi ; CHECK-NEXT: vpbroadcastq zmm0, rdi
; CHECK-NEXT: vpcmpnleuq k0, zmm0, zmmword ptr [rip + {{\.LCPI.*}}] ; CHECK-NEXT: vpcmpnleuq k0, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
; CHECK-NEXT: vpcmpnleuq k1, zmm0, zmmword ptr [rip + {{\.LCPI.*}}] ; CHECK-NEXT: vpcmpnleuq k1, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
; CHECK-NEXT: kunpckbw k0, k1, k0 ; CHECK-NEXT: kunpckbw k0, k1, k0
; CHECK-NEXT: vpmovm2b xmm0, k0 ; CHECK-NEXT: vpmovm2b xmm0, k0
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64 0, i64 %0) %2 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64 0, i64 %0)
ret <16 x i1> %2 ret <16 x i1> %2
} }
define <32 x i1> @create_mask32(i64 %0) { define <32 x i1> @create_mask32(i64 %0) {
; CHECK-LABEL: create_mask32: ; CHECK-LABEL: create_mask32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vpbroadcastq zmm0, rdi ; CHECK-NEXT: vpbroadcastq zmm0, rdi
; CHECK-NEXT: vpcmpnleuq k0, zmm0, zmmword ptr [rip + {{\.LCPI.*}}] ; CHECK-NEXT: vpcmpnleuq k0, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
; CHECK-NEXT: vpcmpnleuq k1, zmm0, zmmword ptr [rip + {{\.LCPI.*}}] ; CHECK-NEXT: vpcmpnleuq k1, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
; CHECK-NEXT: vpcmpnleuq k2, zmm0, zmmword ptr [rip + {{\.LCPI.*}}] ; CHECK-NEXT: vpcmpnleuq k2, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
; CHECK-NEXT: kunpckbw k0, k1, k0 ; CHECK-NEXT: kunpckbw k0, k1, k0
; CHECK-NEXT: vpcmpnleuq k1, zmm0, zmmword ptr [rip + {{\.LCPI.*}}] ; CHECK-NEXT: vpcmpnleuq k1, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
; CHECK-NEXT: kunpckbw k1, k1, k2 ; CHECK-NEXT: kunpckbw k1, k1, k2
; CHECK-NEXT: kunpckwd k0, k1, k0 ; CHECK-NEXT: kunpckwd k0, k1, k0
; CHECK-NEXT: vpmovm2b ymm0, k0 ; CHECK-NEXT: vpmovm2b ymm0, k0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = call <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64 0, i64 %0) %2 = call <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64 0, i64 %0)
ret <32 x i1> %2 ret <32 x i1> %2
} }
define <64 x i1> @create_mask64(i64 %0) { define <64 x i1> @create_mask64(i64 %0) {
; CHECK-LABEL: create_mask64: ; CHECK-LABEL: create_mask64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vpbroadcastq zmm0, rdi ; CHECK-NEXT: vpbroadcastq zmm0, rdi
; CHECK-NEXT: vpcmpnleuq k0, zmm0, zmmword ptr [rip + {{\.LCPI.*}}] ; CHECK-NEXT: vpcmpnleuq k0, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
; CHECK-NEXT: vpcmpnleuq k1, zmm0, zmmword ptr [rip + {{\.LCPI.*}}] ; CHECK-NEXT: vpcmpnleuq k1, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
; CHECK-NEXT: vpcmpnleuq k2, zmm0, zmmword ptr [rip + {{\.LCPI.*}}] ; CHECK-NEXT: vpcmpnleuq k2, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
; CHECK-NEXT: kunpckbw k0, k1, k0 ; CHECK-NEXT: kunpckbw k0, k1, k0
; CHECK-NEXT: vpcmpnleuq k1, zmm0, zmmword ptr [rip + {{\.LCPI.*}}] ; CHECK-NEXT: vpcmpnleuq k1, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
; CHECK-NEXT: kunpckbw k1, k1, k2 ; CHECK-NEXT: kunpckbw k1, k1, k2
; CHECK-NEXT: vpcmpnleuq k2, zmm0, zmmword ptr [rip + {{\.LCPI.*}}] ; CHECK-NEXT: vpcmpnleuq k2, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
; CHECK-NEXT: kunpckwd k0, k1, k0 ; CHECK-NEXT: kunpckwd k0, k1, k0
; CHECK-NEXT: vpcmpnleuq k1, zmm0, zmmword ptr [rip + {{\.LCPI.*}}] ; CHECK-NEXT: vpcmpnleuq k1, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
; CHECK-NEXT: kunpckbw k1, k1, k2 ; CHECK-NEXT: kunpckbw k1, k1, k2
; CHECK-NEXT: vpcmpnleuq k2, zmm0, zmmword ptr [rip + {{\.LCPI.*}}] ; CHECK-NEXT: vpcmpnleuq k2, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
; CHECK-NEXT: vpcmpnleuq k3, zmm0, zmmword ptr [rip + {{\.LCPI.*}}] ; CHECK-NEXT: vpcmpnleuq k3, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
; CHECK-NEXT: kunpckbw k2, k3, k2 ; CHECK-NEXT: kunpckbw k2, k3, k2
; CHECK-NEXT: kunpckwd k1, k2, k1 ; CHECK-NEXT: kunpckwd k1, k2, k1
; CHECK-NEXT: kunpckdq k0, k1, k0 ; CHECK-NEXT: kunpckdq k0, k1, k0
; CHECK-NEXT: vpmovm2b zmm0, k0 ; CHECK-NEXT: vpmovm2b zmm0, k0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = call <64 x i1> @llvm.get.active.lane.mask.v64i1.i64(i64 0, i64 %0) %2 = call <64 x i1> @llvm.get.active.lane.mask.v64i1.i64(i64 0, i64 %0)
ret <64 x i1> %2 ret <64 x i1> %2
} }
define <16 x i1> @create_mask16_i32(i32 %0) { define <16 x i1> @create_mask16_i32(i32 %0) {
; CHECK-LABEL: create_mask16_i32: ; CHECK-LABEL: create_mask16_i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vpbroadcastd zmm0, edi ; CHECK-NEXT: vpbroadcastd zmm0, edi
; CHECK-NEXT: vpcmpnleud k0, zmm0, zmmword ptr [rip + {{\.LCPI.*}}] ; CHECK-NEXT: vpcmpnleud k0, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
; CHECK-NEXT: vpmovm2b xmm0, k0 ; CHECK-NEXT: vpmovm2b xmm0, k0
; CHECK-NEXT: vzeroupper ; CHECK-NEXT: vzeroupper
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 %0) %2 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 0, i32 %0)
ret <16 x i1> %2 ret <16 x i1> %2
} }
define <64 x i1> @create_mask64_i32(i32 %0) { define <64 x i1> @create_mask64_i32(i32 %0) {
; CHECK-LABEL: create_mask64_i32: ; CHECK-LABEL: create_mask64_i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vpbroadcastd zmm0, edi ; CHECK-NEXT: vpbroadcastd zmm0, edi
; CHECK-NEXT: vpcmpnleud k0, zmm0, zmmword ptr [rip + {{\.LCPI.*}}] ; CHECK-NEXT: vpcmpnleud k0, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
; CHECK-NEXT: vpcmpnleud k1, zmm0, zmmword ptr [rip + {{\.LCPI.*}}] ; CHECK-NEXT: vpcmpnleud k1, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
; CHECK-NEXT: vpcmpnleud k2, zmm0, zmmword ptr [rip + {{\.LCPI.*}}] ; CHECK-NEXT: vpcmpnleud k2, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
; CHECK-NEXT: kunpckwd k0, k1, k0 ; CHECK-NEXT: kunpckwd k0, k1, k0
; CHECK-NEXT: vpcmpnleud k1, zmm0, zmmword ptr [rip + {{\.LCPI.*}}] ; CHECK-NEXT: vpcmpnleud k1, zmm0, zmmword ptr [rip + {{\.LCPI[0-9]+_[0-9]+}}]
; CHECK-NEXT: kunpckwd k1, k1, k2 ; CHECK-NEXT: kunpckwd k1, k1, k2
; CHECK-NEXT: kunpckdq k0, k1, k0 ; CHECK-NEXT: kunpckdq k0, k1, k0
; CHECK-NEXT: vpmovm2b zmm0, k0 ; CHECK-NEXT: vpmovm2b zmm0, k0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%2 = call <64 x i1> @llvm.get.active.lane.mask.v64i1.i32(i32 0, i32 %0) %2 = call <64 x i1> @llvm.get.active.lane.mask.v64i1.i32(i32 0, i32 %0)
ret <64 x i1> %2 ret <64 x i1> %2
} }

llvm/test/CodeGen/X86/rotate-extract-vector.ll

Show First 20 Lines • Show All 103 Lines • ▼ Show 20 Lines
} }
define <4 x i32> @vrolw_extract_mul_with_mask(<4 x i32> %i) nounwind { define <4 x i32> @vrolw_extract_mul_with_mask(<4 x i32> %i) nounwind {
; X86-LABEL: vrolw_extract_mul_with_mask: ; X86-LABEL: vrolw_extract_mul_with_mask:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vpbroadcastd {{.*#+}} xmm1 = [9,9,9,9] ; X86-NEXT: vpbroadcastd {{.*#+}} xmm1 = [9,9,9,9]
; X86-NEXT: vpmulld %xmm1, %xmm0, %xmm0 ; X86-NEXT: vpmulld %xmm1, %xmm0, %xmm0
; X86-NEXT: vprold $7, %zmm0, %zmm0 ; X86-NEXT: vprold $7, %zmm0, %zmm0
; X86-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-NEXT: vzeroupper ; X86-NEXT: vzeroupper
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: vrolw_extract_mul_with_mask: ; X64-LABEL: vrolw_extract_mul_with_mask:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpbroadcastd {{.*#+}} xmm1 = [9,9,9,9] ; X64-NEXT: vpbroadcastd {{.*#+}} xmm1 = [9,9,9,9]
; X64-NEXT: vpmulld %xmm1, %xmm0, %xmm0 ; X64-NEXT: vpmulld %xmm1, %xmm0, %xmm0
; X64-NEXT: vprold $7, %zmm0, %zmm0 ; X64-NEXT: vprold $7, %zmm0, %zmm0
; X64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-NEXT: vzeroupper ; X64-NEXT: vzeroupper
; X64-NEXT: retq ; X64-NEXT: retq
%lhs_mul = mul <4 x i32> %i, <i32 1152, i32 1152, i32 1152, i32 1152> %lhs_mul = mul <4 x i32> %i, <i32 1152, i32 1152, i32 1152, i32 1152>
%rhs_mul = mul <4 x i32> %i, <i32 9, i32 9, i32 9, i32 9> %rhs_mul = mul <4 x i32> %i, <i32 9, i32 9, i32 9, i32 9>
%lhs_and = and <4 x i32> %lhs_mul, <i32 160, i32 160, i32 160, i32 160> %lhs_and = and <4 x i32> %lhs_mul, <i32 160, i32 160, i32 160, i32 160>
%rhs_shift = lshr <4 x i32> %rhs_mul, <i32 25, i32 25, i32 25, i32 25> %rhs_shift = lshr <4 x i32> %rhs_mul, <i32 25, i32 25, i32 25, i32 25>
%out = or <4 x i32> %lhs_and, %rhs_shift %out = or <4 x i32> %lhs_and, %rhs_shift
ret <4 x i32> %out ret <4 x i32> %out
} }
define <32 x i16> @illegal_no_extract_mul(<32 x i16> %i) nounwind { define <32 x i16> @illegal_no_extract_mul(<32 x i16> %i) nounwind {
; X86-LABEL: illegal_no_extract_mul: ; X86-LABEL: illegal_no_extract_mul:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vpmullw {{\.LCPI.*}}, %zmm0, %zmm1 ; X86-NEXT: vpmullw {{\.LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm1
; X86-NEXT: vpmullw {{\.LCPI.*}}, %zmm0, %zmm0 ; X86-NEXT: vpmullw {{\.LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0
; X86-NEXT: vpsrlw $10, %zmm0, %zmm0 ; X86-NEXT: vpsrlw $10, %zmm0, %zmm0
; X86-NEXT: vporq %zmm0, %zmm1, %zmm0 ; X86-NEXT: vporq %zmm0, %zmm1, %zmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: illegal_no_extract_mul: ; X64-LABEL: illegal_no_extract_mul:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpmullw {{.*}}(%rip), %zmm0, %zmm1 ; X64-NEXT: vpmullw {{.*}}(%rip), %zmm0, %zmm1
; X64-NEXT: vpmullw {{.*}}(%rip), %zmm0, %zmm0 ; X64-NEXT: vpmullw {{.*}}(%rip), %zmm0, %zmm0
▲ Show 20 Lines • Show All 180 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/scalar-fp-to-i64.ll

Show First 20 Lines • Show All 261 Lines • ▼ Show 20 Lines
; X87-WIN-NEXT: movl %ebp, %esp ; X87-WIN-NEXT: movl %ebp, %esp
; X87-WIN-NEXT: popl %ebp ; X87-WIN-NEXT: popl %ebp
; X87-WIN-NEXT: retl ; X87-WIN-NEXT: retl
; ;
; X87-LIN-LABEL: f_to_u64: ; X87-LIN-LABEL: f_to_u64:
; X87-LIN: # %bb.0: ; X87-LIN: # %bb.0:
; X87-LIN-NEXT: subl $20, %esp ; X87-LIN-NEXT: subl $20, %esp
; X87-LIN-NEXT: flds {{[0-9]+}}(%esp) ; X87-LIN-NEXT: flds {{[0-9]+}}(%esp)
; X87-LIN-NEXT: flds {{\.LCPI.*}} ; X87-LIN-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X87-LIN-NEXT: fucom %st(1) ; X87-LIN-NEXT: fucom %st(1)
; X87-LIN-NEXT: fnstsw %ax ; X87-LIN-NEXT: fnstsw %ax
; X87-LIN-NEXT: xorl %edx, %edx ; X87-LIN-NEXT: xorl %edx, %edx
; X87-LIN-NEXT: # kill: def $ah killed $ah killed $ax ; X87-LIN-NEXT: # kill: def $ah killed $ah killed $ax
; X87-LIN-NEXT: sahf ; X87-LIN-NEXT: sahf
; X87-LIN-NEXT: setbe %al ; X87-LIN-NEXT: setbe %al
; X87-LIN-NEXT: fldz ; X87-LIN-NEXT: fldz
; X87-LIN-NEXT: jbe .LBB0_2 ; X87-LIN-NEXT: jbe .LBB0_2
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; X87-WIN-NEXT: movl %ebp, %esp ; X87-WIN-NEXT: movl %ebp, %esp
; X87-WIN-NEXT: popl %ebp ; X87-WIN-NEXT: popl %ebp
; X87-WIN-NEXT: retl ; X87-WIN-NEXT: retl
; ;
; X87-LIN-LABEL: d_to_u64: ; X87-LIN-LABEL: d_to_u64:
; X87-LIN: # %bb.0: ; X87-LIN: # %bb.0:
; X87-LIN-NEXT: subl $20, %esp ; X87-LIN-NEXT: subl $20, %esp
; X87-LIN-NEXT: fldl {{[0-9]+}}(%esp) ; X87-LIN-NEXT: fldl {{[0-9]+}}(%esp)
; X87-LIN-NEXT: flds {{\.LCPI.*}} ; X87-LIN-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X87-LIN-NEXT: fucom %st(1) ; X87-LIN-NEXT: fucom %st(1)
; X87-LIN-NEXT: fnstsw %ax ; X87-LIN-NEXT: fnstsw %ax
; X87-LIN-NEXT: xorl %edx, %edx ; X87-LIN-NEXT: xorl %edx, %edx
; X87-LIN-NEXT: # kill: def $ah killed $ah killed $ax ; X87-LIN-NEXT: # kill: def $ah killed $ah killed $ax
; X87-LIN-NEXT: sahf ; X87-LIN-NEXT: sahf
; X87-LIN-NEXT: setbe %al ; X87-LIN-NEXT: setbe %al
; X87-LIN-NEXT: fldz ; X87-LIN-NEXT: fldz
; X87-LIN-NEXT: jbe .LBB2_2 ; X87-LIN-NEXT: jbe .LBB2_2
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; X86-AVX512-WIN-NEXT: movl %ebp, %esp ; X86-AVX512-WIN-NEXT: movl %ebp, %esp
; X86-AVX512-WIN-NEXT: popl %ebp ; X86-AVX512-WIN-NEXT: popl %ebp
; X86-AVX512-WIN-NEXT: retl ; X86-AVX512-WIN-NEXT: retl
; ;
; X86-AVX512-LIN-LABEL: x_to_u64: ; X86-AVX512-LIN-LABEL: x_to_u64:
; X86-AVX512-LIN: # %bb.0: ; X86-AVX512-LIN: # %bb.0:
; X86-AVX512-LIN-NEXT: subl $12, %esp ; X86-AVX512-LIN-NEXT: subl $12, %esp
; X86-AVX512-LIN-NEXT: fldt {{[0-9]+}}(%esp) ; X86-AVX512-LIN-NEXT: fldt {{[0-9]+}}(%esp)
; X86-AVX512-LIN-NEXT: flds {{\.LCPI.*}} ; X86-AVX512-LIN-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-AVX512-LIN-NEXT: xorl %edx, %edx ; X86-AVX512-LIN-NEXT: xorl %edx, %edx
; X86-AVX512-LIN-NEXT: fucomi %st(1), %st ; X86-AVX512-LIN-NEXT: fucomi %st(1), %st
; X86-AVX512-LIN-NEXT: fldz ; X86-AVX512-LIN-NEXT: fldz
; X86-AVX512-LIN-NEXT: fcmovbe %st(1), %st ; X86-AVX512-LIN-NEXT: fcmovbe %st(1), %st
; X86-AVX512-LIN-NEXT: fstp %st(1) ; X86-AVX512-LIN-NEXT: fstp %st(1)
; X86-AVX512-LIN-NEXT: fsubrp %st, %st(1) ; X86-AVX512-LIN-NEXT: fsubrp %st, %st(1)
; X86-AVX512-LIN-NEXT: fisttpll (%esp) ; X86-AVX512-LIN-NEXT: fisttpll (%esp)
; X86-AVX512-LIN-NEXT: setbe %dl ; X86-AVX512-LIN-NEXT: setbe %dl
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; X86-SSE3-WIN-NEXT: movl %ebp, %esp ; X86-SSE3-WIN-NEXT: movl %ebp, %esp
; X86-SSE3-WIN-NEXT: popl %ebp ; X86-SSE3-WIN-NEXT: popl %ebp
; X86-SSE3-WIN-NEXT: retl ; X86-SSE3-WIN-NEXT: retl
; ;
; X86-SSE3-LIN-LABEL: x_to_u64: ; X86-SSE3-LIN-LABEL: x_to_u64:
; X86-SSE3-LIN: # %bb.0: ; X86-SSE3-LIN: # %bb.0:
; X86-SSE3-LIN-NEXT: subl $12, %esp ; X86-SSE3-LIN-NEXT: subl $12, %esp
; X86-SSE3-LIN-NEXT: fldt {{[0-9]+}}(%esp) ; X86-SSE3-LIN-NEXT: fldt {{[0-9]+}}(%esp)
; X86-SSE3-LIN-NEXT: flds {{\.LCPI.*}} ; X86-SSE3-LIN-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-SSE3-LIN-NEXT: xorl %edx, %edx ; X86-SSE3-LIN-NEXT: xorl %edx, %edx
; X86-SSE3-LIN-NEXT: fucomi %st(1), %st ; X86-SSE3-LIN-NEXT: fucomi %st(1), %st
; X86-SSE3-LIN-NEXT: fldz ; X86-SSE3-LIN-NEXT: fldz
; X86-SSE3-LIN-NEXT: fcmovbe %st(1), %st ; X86-SSE3-LIN-NEXT: fcmovbe %st(1), %st
; X86-SSE3-LIN-NEXT: fstp %st(1) ; X86-SSE3-LIN-NEXT: fstp %st(1)
; X86-SSE3-LIN-NEXT: fsubrp %st, %st(1) ; X86-SSE3-LIN-NEXT: fsubrp %st, %st(1)
; X86-SSE3-LIN-NEXT: fisttpll (%esp) ; X86-SSE3-LIN-NEXT: fisttpll (%esp)
; X86-SSE3-LIN-NEXT: setbe %dl ; X86-SSE3-LIN-NEXT: setbe %dl
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; X86-SSE2-WIN-NEXT: movl %ebp, %esp ; X86-SSE2-WIN-NEXT: movl %ebp, %esp
; X86-SSE2-WIN-NEXT: popl %ebp ; X86-SSE2-WIN-NEXT: popl %ebp
; X86-SSE2-WIN-NEXT: retl ; X86-SSE2-WIN-NEXT: retl
; ;
; X86-SSE2-LIN-LABEL: x_to_u64: ; X86-SSE2-LIN-LABEL: x_to_u64:
; X86-SSE2-LIN: # %bb.0: ; X86-SSE2-LIN: # %bb.0:
; X86-SSE2-LIN-NEXT: subl $20, %esp ; X86-SSE2-LIN-NEXT: subl $20, %esp
; X86-SSE2-LIN-NEXT: fldt {{[0-9]+}}(%esp) ; X86-SSE2-LIN-NEXT: fldt {{[0-9]+}}(%esp)
; X86-SSE2-LIN-NEXT: flds {{\.LCPI.*}} ; X86-SSE2-LIN-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X86-SSE2-LIN-NEXT: xorl %edx, %edx ; X86-SSE2-LIN-NEXT: xorl %edx, %edx
; X86-SSE2-LIN-NEXT: fucomi %st(1), %st ; X86-SSE2-LIN-NEXT: fucomi %st(1), %st
; X86-SSE2-LIN-NEXT: setbe %dl ; X86-SSE2-LIN-NEXT: setbe %dl
; X86-SSE2-LIN-NEXT: fldz ; X86-SSE2-LIN-NEXT: fldz
; X86-SSE2-LIN-NEXT: fcmovbe %st(1), %st ; X86-SSE2-LIN-NEXT: fcmovbe %st(1), %st
; X86-SSE2-LIN-NEXT: fstp %st(1) ; X86-SSE2-LIN-NEXT: fstp %st(1)
; X86-SSE2-LIN-NEXT: fsubrp %st, %st(1) ; X86-SSE2-LIN-NEXT: fsubrp %st, %st(1)
; X86-SSE2-LIN-NEXT: fnstcw {{[0-9]+}}(%esp) ; X86-SSE2-LIN-NEXT: fnstcw {{[0-9]+}}(%esp)
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; X87-WIN-NEXT: movl %ebp, %esp ; X87-WIN-NEXT: movl %ebp, %esp
; X87-WIN-NEXT: popl %ebp ; X87-WIN-NEXT: popl %ebp
; X87-WIN-NEXT: retl ; X87-WIN-NEXT: retl
; ;
; X87-LIN-LABEL: x_to_u64: ; X87-LIN-LABEL: x_to_u64:
; X87-LIN: # %bb.0: ; X87-LIN: # %bb.0:
; X87-LIN-NEXT: subl $20, %esp ; X87-LIN-NEXT: subl $20, %esp
; X87-LIN-NEXT: fldt {{[0-9]+}}(%esp) ; X87-LIN-NEXT: fldt {{[0-9]+}}(%esp)
; X87-LIN-NEXT: flds {{\.LCPI.*}} ; X87-LIN-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; X87-LIN-NEXT: fucom %st(1) ; X87-LIN-NEXT: fucom %st(1)
; X87-LIN-NEXT: fnstsw %ax ; X87-LIN-NEXT: fnstsw %ax
; X87-LIN-NEXT: xorl %edx, %edx ; X87-LIN-NEXT: xorl %edx, %edx
; X87-LIN-NEXT: # kill: def $ah killed $ah killed $ax ; X87-LIN-NEXT: # kill: def $ah killed $ah killed $ax
; X87-LIN-NEXT: sahf ; X87-LIN-NEXT: sahf
; X87-LIN-NEXT: setbe %al ; X87-LIN-NEXT: setbe %al
; X87-LIN-NEXT: fldz ; X87-LIN-NEXT: fldz
; X87-LIN-NEXT: jbe .LBB4_2 ; X87-LIN-NEXT: jbe .LBB4_2
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llvm/test/CodeGen/X86/scalar-int-to-fp.ll

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; AVX512_64: # %bb.0: ; AVX512_64: # %bb.0:
; AVX512_64-NEXT: vcvtusi2ss %edi, %xmm0, %xmm0 ; AVX512_64-NEXT: vcvtusi2ss %edi, %xmm0, %xmm0
; AVX512_64-NEXT: retq ; AVX512_64-NEXT: retq
; ;
; SSE2_32-LABEL: u32_to_f: ; SSE2_32-LABEL: u32_to_f:
; SSE2_32: # %bb.0: ; SSE2_32: # %bb.0:
; SSE2_32-NEXT: pushl %eax ; SSE2_32-NEXT: pushl %eax
; SSE2_32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2_32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2_32-NEXT: orpd {{\.LCPI.*}}, %xmm0 ; SSE2_32-NEXT: orpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE2_32-NEXT: subsd {{\.LCPI.*}}, %xmm0 ; SSE2_32-NEXT: subsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE2_32-NEXT: cvtsd2ss %xmm0, %xmm0 ; SSE2_32-NEXT: cvtsd2ss %xmm0, %xmm0
; SSE2_32-NEXT: movss %xmm0, (%esp) ; SSE2_32-NEXT: movss %xmm0, (%esp)
; SSE2_32-NEXT: flds (%esp) ; SSE2_32-NEXT: flds (%esp)
; SSE2_32-NEXT: popl %eax ; SSE2_32-NEXT: popl %eax
; SSE2_32-NEXT: retl ; SSE2_32-NEXT: retl
; ;
; SSE2_64-LABEL: u32_to_f: ; SSE2_64-LABEL: u32_to_f:
; SSE2_64: # %bb.0: ; SSE2_64: # %bb.0:
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; ;
; SSE2_32-LABEL: u32_to_d: ; SSE2_32-LABEL: u32_to_d:
; SSE2_32: # %bb.0: ; SSE2_32: # %bb.0:
; SSE2_32-NEXT: pushl %ebp ; SSE2_32-NEXT: pushl %ebp
; SSE2_32-NEXT: movl %esp, %ebp ; SSE2_32-NEXT: movl %esp, %ebp
; SSE2_32-NEXT: andl $-8, %esp ; SSE2_32-NEXT: andl $-8, %esp
; SSE2_32-NEXT: subl $8, %esp ; SSE2_32-NEXT: subl $8, %esp
; SSE2_32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2_32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2_32-NEXT: orpd {{\.LCPI.*}}, %xmm0 ; SSE2_32-NEXT: orpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE2_32-NEXT: subsd {{\.LCPI.*}}, %xmm0 ; SSE2_32-NEXT: subsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE2_32-NEXT: movsd %xmm0, (%esp) ; SSE2_32-NEXT: movsd %xmm0, (%esp)
; SSE2_32-NEXT: fldl (%esp) ; SSE2_32-NEXT: fldl (%esp)
; SSE2_32-NEXT: movl %ebp, %esp ; SSE2_32-NEXT: movl %ebp, %esp
; SSE2_32-NEXT: popl %ebp ; SSE2_32-NEXT: popl %ebp
; SSE2_32-NEXT: retl ; SSE2_32-NEXT: retl
; ;
; SSE2_64-LABEL: u32_to_d: ; SSE2_64-LABEL: u32_to_d:
; SSE2_64: # %bb.0: ; SSE2_64: # %bb.0:
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; AVX512F_32-NEXT: movl %esp, %ebp ; AVX512F_32-NEXT: movl %esp, %ebp
; AVX512F_32-NEXT: andl $-8, %esp ; AVX512F_32-NEXT: andl $-8, %esp
; AVX512F_32-NEXT: subl $16, %esp ; AVX512F_32-NEXT: subl $16, %esp
; AVX512F_32-NEXT: movl 12(%ebp), %eax ; AVX512F_32-NEXT: movl 12(%ebp), %eax
; AVX512F_32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; AVX512F_32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX512F_32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp) ; AVX512F_32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)
; AVX512F_32-NEXT: shrl $31, %eax ; AVX512F_32-NEXT: shrl $31, %eax
; AVX512F_32-NEXT: fildll {{[0-9]+}}(%esp) ; AVX512F_32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX512F_32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; AVX512F_32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX512F_32-NEXT: fstps {{[0-9]+}}(%esp) ; AVX512F_32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX512F_32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; AVX512F_32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX512F_32-NEXT: vmovss %xmm0, (%esp) ; AVX512F_32-NEXT: vmovss %xmm0, (%esp)
; AVX512F_32-NEXT: flds (%esp) ; AVX512F_32-NEXT: flds (%esp)
; AVX512F_32-NEXT: movl %ebp, %esp ; AVX512F_32-NEXT: movl %ebp, %esp
; AVX512F_32-NEXT: popl %ebp ; AVX512F_32-NEXT: popl %ebp
; AVX512F_32-NEXT: retl ; AVX512F_32-NEXT: retl
; ;
; SSE2_32-LABEL: u64_to_f: ; SSE2_32-LABEL: u64_to_f:
; SSE2_32: # %bb.0: ; SSE2_32: # %bb.0:
; SSE2_32-NEXT: pushl %ebp ; SSE2_32-NEXT: pushl %ebp
; SSE2_32-NEXT: movl %esp, %ebp ; SSE2_32-NEXT: movl %esp, %ebp
; SSE2_32-NEXT: andl $-8, %esp ; SSE2_32-NEXT: andl $-8, %esp
; SSE2_32-NEXT: subl $16, %esp ; SSE2_32-NEXT: subl $16, %esp
; SSE2_32-NEXT: movl 12(%ebp), %eax ; SSE2_32-NEXT: movl 12(%ebp), %eax
; SSE2_32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE2_32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; SSE2_32-NEXT: movlps %xmm0, {{[0-9]+}}(%esp) ; SSE2_32-NEXT: movlps %xmm0, {{[0-9]+}}(%esp)
; SSE2_32-NEXT: shrl $31, %eax ; SSE2_32-NEXT: shrl $31, %eax
; SSE2_32-NEXT: fildll {{[0-9]+}}(%esp) ; SSE2_32-NEXT: fildll {{[0-9]+}}(%esp)
; SSE2_32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; SSE2_32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; SSE2_32-NEXT: fstps {{[0-9]+}}(%esp) ; SSE2_32-NEXT: fstps {{[0-9]+}}(%esp)
; SSE2_32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE2_32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2_32-NEXT: movss %xmm0, (%esp) ; SSE2_32-NEXT: movss %xmm0, (%esp)
; SSE2_32-NEXT: flds (%esp) ; SSE2_32-NEXT: flds (%esp)
; SSE2_32-NEXT: movl %ebp, %esp ; SSE2_32-NEXT: movl %ebp, %esp
; SSE2_32-NEXT: popl %ebp ; SSE2_32-NEXT: popl %ebp
; SSE2_32-NEXT: retl ; SSE2_32-NEXT: retl
; ;
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; SSE1_32-NEXT: movl 8(%ebp), %eax ; SSE1_32-NEXT: movl 8(%ebp), %eax
; SSE1_32-NEXT: movl 12(%ebp), %ecx ; SSE1_32-NEXT: movl 12(%ebp), %ecx
; SSE1_32-NEXT: movl %ecx, {{[0-9]+}}(%esp) ; SSE1_32-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; SSE1_32-NEXT: movl %eax, {{[0-9]+}}(%esp) ; SSE1_32-NEXT: movl %eax, {{[0-9]+}}(%esp)
; SSE1_32-NEXT: fldl {{[0-9]+}}(%esp) ; SSE1_32-NEXT: fldl {{[0-9]+}}(%esp)
; SSE1_32-NEXT: fstpl {{[0-9]+}}(%esp) ; SSE1_32-NEXT: fstpl {{[0-9]+}}(%esp)
; SSE1_32-NEXT: shrl $31, %ecx ; SSE1_32-NEXT: shrl $31, %ecx
; SSE1_32-NEXT: fildll {{[0-9]+}}(%esp) ; SSE1_32-NEXT: fildll {{[0-9]+}}(%esp)
; SSE1_32-NEXT: fadds {{\.LCPI.*}}(,%ecx,4) ; SSE1_32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; SSE1_32-NEXT: fstps {{[0-9]+}}(%esp) ; SSE1_32-NEXT: fstps {{[0-9]+}}(%esp)
; SSE1_32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE1_32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE1_32-NEXT: movss %xmm0, (%esp) ; SSE1_32-NEXT: movss %xmm0, (%esp)
; SSE1_32-NEXT: flds (%esp) ; SSE1_32-NEXT: flds (%esp)
; SSE1_32-NEXT: movl %ebp, %esp ; SSE1_32-NEXT: movl %ebp, %esp
; SSE1_32-NEXT: popl %ebp ; SSE1_32-NEXT: popl %ebp
; SSE1_32-NEXT: retl ; SSE1_32-NEXT: retl
; ;
; X87-LABEL: u64_to_f: ; X87-LABEL: u64_to_f:
; X87: # %bb.0: ; X87: # %bb.0:
; X87-NEXT: pushl %ebp ; X87-NEXT: pushl %ebp
; X87-NEXT: movl %esp, %ebp ; X87-NEXT: movl %esp, %ebp
; X87-NEXT: andl $-8, %esp ; X87-NEXT: andl $-8, %esp
; X87-NEXT: subl $16, %esp ; X87-NEXT: subl $16, %esp
; X87-NEXT: movl 8(%ebp), %eax ; X87-NEXT: movl 8(%ebp), %eax
; X87-NEXT: movl 12(%ebp), %ecx ; X87-NEXT: movl 12(%ebp), %ecx
; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp) ; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X87-NEXT: movl %eax, {{[0-9]+}}(%esp) ; X87-NEXT: movl %eax, {{[0-9]+}}(%esp)
; X87-NEXT: shrl $31, %ecx ; X87-NEXT: shrl $31, %ecx
; X87-NEXT: fildll {{[0-9]+}}(%esp) ; X87-NEXT: fildll {{[0-9]+}}(%esp)
; X87-NEXT: fadds {{\.LCPI.*}}(,%ecx,4) ; X87-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; X87-NEXT: fstps {{[0-9]+}}(%esp) ; X87-NEXT: fstps {{[0-9]+}}(%esp)
; X87-NEXT: flds {{[0-9]+}}(%esp) ; X87-NEXT: flds {{[0-9]+}}(%esp)
; X87-NEXT: movl %ebp, %esp ; X87-NEXT: movl %ebp, %esp
; X87-NEXT: popl %ebp ; X87-NEXT: popl %ebp
; X87-NEXT: retl ; X87-NEXT: retl
%r = uitofp i64 %a to float %r = uitofp i64 %a to float
ret float %r ret float %r
} }
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; AVX512F_32-LABEL: u64_to_d: ; AVX512F_32-LABEL: u64_to_d:
; AVX512F_32: # %bb.0: ; AVX512F_32: # %bb.0:
; AVX512F_32-NEXT: pushl %ebp ; AVX512F_32-NEXT: pushl %ebp
; AVX512F_32-NEXT: movl %esp, %ebp ; AVX512F_32-NEXT: movl %esp, %ebp
; AVX512F_32-NEXT: andl $-8, %esp ; AVX512F_32-NEXT: andl $-8, %esp
; AVX512F_32-NEXT: subl $8, %esp ; AVX512F_32-NEXT: subl $8, %esp
; AVX512F_32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; AVX512F_32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX512F_32-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] ; AVX512F_32-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; AVX512F_32-NEXT: vsubpd {{\.LCPI.*}}, %xmm0, %xmm0 ; AVX512F_32-NEXT: vsubpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX512F_32-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0] ; AVX512F_32-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX512F_32-NEXT: vaddsd %xmm0, %xmm1, %xmm0 ; AVX512F_32-NEXT: vaddsd %xmm0, %xmm1, %xmm0
; AVX512F_32-NEXT: vmovsd %xmm0, (%esp) ; AVX512F_32-NEXT: vmovsd %xmm0, (%esp)
; AVX512F_32-NEXT: fldl (%esp) ; AVX512F_32-NEXT: fldl (%esp)
; AVX512F_32-NEXT: movl %ebp, %esp ; AVX512F_32-NEXT: movl %ebp, %esp
; AVX512F_32-NEXT: popl %ebp ; AVX512F_32-NEXT: popl %ebp
; AVX512F_32-NEXT: retl ; AVX512F_32-NEXT: retl
; ;
; SSE2_32-LABEL: u64_to_d: ; SSE2_32-LABEL: u64_to_d:
; SSE2_32: # %bb.0: ; SSE2_32: # %bb.0:
; SSE2_32-NEXT: pushl %ebp ; SSE2_32-NEXT: pushl %ebp
; SSE2_32-NEXT: movl %esp, %ebp ; SSE2_32-NEXT: movl %esp, %ebp
; SSE2_32-NEXT: andl $-8, %esp ; SSE2_32-NEXT: andl $-8, %esp
; SSE2_32-NEXT: subl $8, %esp ; SSE2_32-NEXT: subl $8, %esp
; SSE2_32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE2_32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; SSE2_32-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] ; SSE2_32-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; SSE2_32-NEXT: subpd {{\.LCPI.*}}, %xmm0 ; SSE2_32-NEXT: subpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE2_32-NEXT: movapd %xmm0, %xmm1 ; SSE2_32-NEXT: movapd %xmm0, %xmm1
; SSE2_32-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2_32-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2_32-NEXT: addsd %xmm0, %xmm1 ; SSE2_32-NEXT: addsd %xmm0, %xmm1
; SSE2_32-NEXT: movsd %xmm1, (%esp) ; SSE2_32-NEXT: movsd %xmm1, (%esp)
; SSE2_32-NEXT: fldl (%esp) ; SSE2_32-NEXT: fldl (%esp)
; SSE2_32-NEXT: movl %ebp, %esp ; SSE2_32-NEXT: movl %ebp, %esp
; SSE2_32-NEXT: popl %ebp ; SSE2_32-NEXT: popl %ebp
; SSE2_32-NEXT: retl ; SSE2_32-NEXT: retl
Show All 15 Lines
; SSE1_32-NEXT: andl $-8, %esp ; SSE1_32-NEXT: andl $-8, %esp
; SSE1_32-NEXT: subl $16, %esp ; SSE1_32-NEXT: subl $16, %esp
; SSE1_32-NEXT: movl 8(%ebp), %eax ; SSE1_32-NEXT: movl 8(%ebp), %eax
; SSE1_32-NEXT: movl 12(%ebp), %ecx ; SSE1_32-NEXT: movl 12(%ebp), %ecx
; SSE1_32-NEXT: movl %ecx, {{[0-9]+}}(%esp) ; SSE1_32-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; SSE1_32-NEXT: movl %eax, (%esp) ; SSE1_32-NEXT: movl %eax, (%esp)
; SSE1_32-NEXT: shrl $31, %ecx ; SSE1_32-NEXT: shrl $31, %ecx
; SSE1_32-NEXT: fildll (%esp) ; SSE1_32-NEXT: fildll (%esp)
; SSE1_32-NEXT: fadds {{\.LCPI.*}}(,%ecx,4) ; SSE1_32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; SSE1_32-NEXT: fstpl {{[0-9]+}}(%esp) ; SSE1_32-NEXT: fstpl {{[0-9]+}}(%esp)
; SSE1_32-NEXT: fldl {{[0-9]+}}(%esp) ; SSE1_32-NEXT: fldl {{[0-9]+}}(%esp)
; SSE1_32-NEXT: movl %ebp, %esp ; SSE1_32-NEXT: movl %ebp, %esp
; SSE1_32-NEXT: popl %ebp ; SSE1_32-NEXT: popl %ebp
; SSE1_32-NEXT: retl ; SSE1_32-NEXT: retl
; ;
; X87-LABEL: u64_to_d: ; X87-LABEL: u64_to_d:
; X87: # %bb.0: ; X87: # %bb.0:
; X87-NEXT: pushl %ebp ; X87-NEXT: pushl %ebp
; X87-NEXT: movl %esp, %ebp ; X87-NEXT: movl %esp, %ebp
; X87-NEXT: andl $-8, %esp ; X87-NEXT: andl $-8, %esp
; X87-NEXT: subl $16, %esp ; X87-NEXT: subl $16, %esp
; X87-NEXT: movl 8(%ebp), %eax ; X87-NEXT: movl 8(%ebp), %eax
; X87-NEXT: movl 12(%ebp), %ecx ; X87-NEXT: movl 12(%ebp), %ecx
; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp) ; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X87-NEXT: movl %eax, (%esp) ; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: shrl $31, %ecx ; X87-NEXT: shrl $31, %ecx
; X87-NEXT: fildll (%esp) ; X87-NEXT: fildll (%esp)
; X87-NEXT: fadds {{\.LCPI.*}}(,%ecx,4) ; X87-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; X87-NEXT: fstpl {{[0-9]+}}(%esp) ; X87-NEXT: fstpl {{[0-9]+}}(%esp)
; X87-NEXT: fldl {{[0-9]+}}(%esp) ; X87-NEXT: fldl {{[0-9]+}}(%esp)
; X87-NEXT: movl %ebp, %esp ; X87-NEXT: movl %ebp, %esp
; X87-NEXT: popl %ebp ; X87-NEXT: popl %ebp
; X87-NEXT: retl ; X87-NEXT: retl
%r = uitofp i64 %a to double %r = uitofp i64 %a to double
ret double %r ret double %r
} }
Show All 37 Lines
; AVX512F_32-LABEL: u64_to_d_optsize: ; AVX512F_32-LABEL: u64_to_d_optsize:
; AVX512F_32: # %bb.0: ; AVX512F_32: # %bb.0:
; AVX512F_32-NEXT: pushl %ebp ; AVX512F_32-NEXT: pushl %ebp
; AVX512F_32-NEXT: movl %esp, %ebp ; AVX512F_32-NEXT: movl %esp, %ebp
; AVX512F_32-NEXT: andl $-8, %esp ; AVX512F_32-NEXT: andl $-8, %esp
; AVX512F_32-NEXT: subl $8, %esp ; AVX512F_32-NEXT: subl $8, %esp
; AVX512F_32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; AVX512F_32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX512F_32-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] ; AVX512F_32-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; AVX512F_32-NEXT: vsubpd {{\.LCPI.*}}, %xmm0, %xmm0 ; AVX512F_32-NEXT: vsubpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX512F_32-NEXT: vhaddpd %xmm0, %xmm0, %xmm0 ; AVX512F_32-NEXT: vhaddpd %xmm0, %xmm0, %xmm0
; AVX512F_32-NEXT: vmovlpd %xmm0, (%esp) ; AVX512F_32-NEXT: vmovlpd %xmm0, (%esp)
; AVX512F_32-NEXT: fldl (%esp) ; AVX512F_32-NEXT: fldl (%esp)
; AVX512F_32-NEXT: movl %ebp, %esp ; AVX512F_32-NEXT: movl %ebp, %esp
; AVX512F_32-NEXT: popl %ebp ; AVX512F_32-NEXT: popl %ebp
; AVX512F_32-NEXT: retl ; AVX512F_32-NEXT: retl
; ;
; SSE2_32-LABEL: u64_to_d_optsize: ; SSE2_32-LABEL: u64_to_d_optsize:
; SSE2_32: # %bb.0: ; SSE2_32: # %bb.0:
; SSE2_32-NEXT: pushl %ebp ; SSE2_32-NEXT: pushl %ebp
; SSE2_32-NEXT: movl %esp, %ebp ; SSE2_32-NEXT: movl %esp, %ebp
; SSE2_32-NEXT: andl $-8, %esp ; SSE2_32-NEXT: andl $-8, %esp
; SSE2_32-NEXT: subl $8, %esp ; SSE2_32-NEXT: subl $8, %esp
; SSE2_32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE2_32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; SSE2_32-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] ; SSE2_32-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; SSE2_32-NEXT: subpd {{\.LCPI.*}}, %xmm0 ; SSE2_32-NEXT: subpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE2_32-NEXT: movapd %xmm0, %xmm1 ; SSE2_32-NEXT: movapd %xmm0, %xmm1
; SSE2_32-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1] ; SSE2_32-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]
; SSE2_32-NEXT: addsd %xmm0, %xmm1 ; SSE2_32-NEXT: addsd %xmm0, %xmm1
; SSE2_32-NEXT: movsd %xmm1, (%esp) ; SSE2_32-NEXT: movsd %xmm1, (%esp)
; SSE2_32-NEXT: fldl (%esp) ; SSE2_32-NEXT: fldl (%esp)
; SSE2_32-NEXT: movl %ebp, %esp ; SSE2_32-NEXT: movl %ebp, %esp
; SSE2_32-NEXT: popl %ebp ; SSE2_32-NEXT: popl %ebp
; SSE2_32-NEXT: retl ; SSE2_32-NEXT: retl
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; SSE1_32-NEXT: andl $-8, %esp ; SSE1_32-NEXT: andl $-8, %esp
; SSE1_32-NEXT: subl $16, %esp ; SSE1_32-NEXT: subl $16, %esp
; SSE1_32-NEXT: movl 8(%ebp), %eax ; SSE1_32-NEXT: movl 8(%ebp), %eax
; SSE1_32-NEXT: movl 12(%ebp), %ecx ; SSE1_32-NEXT: movl 12(%ebp), %ecx
; SSE1_32-NEXT: movl %ecx, {{[0-9]+}}(%esp) ; SSE1_32-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; SSE1_32-NEXT: movl %eax, (%esp) ; SSE1_32-NEXT: movl %eax, (%esp)
; SSE1_32-NEXT: shrl $31, %ecx ; SSE1_32-NEXT: shrl $31, %ecx
; SSE1_32-NEXT: fildll (%esp) ; SSE1_32-NEXT: fildll (%esp)
; SSE1_32-NEXT: fadds {{\.LCPI.*}}(,%ecx,4) ; SSE1_32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; SSE1_32-NEXT: fstpl {{[0-9]+}}(%esp) ; SSE1_32-NEXT: fstpl {{[0-9]+}}(%esp)
; SSE1_32-NEXT: fldl {{[0-9]+}}(%esp) ; SSE1_32-NEXT: fldl {{[0-9]+}}(%esp)
; SSE1_32-NEXT: movl %ebp, %esp ; SSE1_32-NEXT: movl %ebp, %esp
; SSE1_32-NEXT: popl %ebp ; SSE1_32-NEXT: popl %ebp
; SSE1_32-NEXT: retl ; SSE1_32-NEXT: retl
; ;
; X87-LABEL: u64_to_d_optsize: ; X87-LABEL: u64_to_d_optsize:
; X87: # %bb.0: ; X87: # %bb.0:
; X87-NEXT: pushl %ebp ; X87-NEXT: pushl %ebp
; X87-NEXT: movl %esp, %ebp ; X87-NEXT: movl %esp, %ebp
; X87-NEXT: andl $-8, %esp ; X87-NEXT: andl $-8, %esp
; X87-NEXT: subl $16, %esp ; X87-NEXT: subl $16, %esp
; X87-NEXT: movl 8(%ebp), %eax ; X87-NEXT: movl 8(%ebp), %eax
; X87-NEXT: movl 12(%ebp), %ecx ; X87-NEXT: movl 12(%ebp), %ecx
; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp) ; X87-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; X87-NEXT: movl %eax, (%esp) ; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: shrl $31, %ecx ; X87-NEXT: shrl $31, %ecx
; X87-NEXT: fildll (%esp) ; X87-NEXT: fildll (%esp)
; X87-NEXT: fadds {{\.LCPI.*}}(,%ecx,4) ; X87-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; X87-NEXT: fstpl {{[0-9]+}}(%esp) ; X87-NEXT: fstpl {{[0-9]+}}(%esp)
; X87-NEXT: fldl {{[0-9]+}}(%esp) ; X87-NEXT: fldl {{[0-9]+}}(%esp)
; X87-NEXT: movl %ebp, %esp ; X87-NEXT: movl %ebp, %esp
; X87-NEXT: popl %ebp ; X87-NEXT: popl %ebp
; X87-NEXT: retl ; X87-NEXT: retl
%r = uitofp i64 %a to double %r = uitofp i64 %a to double
ret double %r ret double %r
} }
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; CHECK32-NEXT: andl $-8, %esp ; CHECK32-NEXT: andl $-8, %esp
; CHECK32-NEXT: subl $8, %esp ; CHECK32-NEXT: subl $8, %esp
; CHECK32-NEXT: movl 8(%ebp), %eax ; CHECK32-NEXT: movl 8(%ebp), %eax
; CHECK32-NEXT: movl 12(%ebp), %ecx ; CHECK32-NEXT: movl 12(%ebp), %ecx
; CHECK32-NEXT: movl %ecx, {{[0-9]+}}(%esp) ; CHECK32-NEXT: movl %ecx, {{[0-9]+}}(%esp)
; CHECK32-NEXT: movl %eax, (%esp) ; CHECK32-NEXT: movl %eax, (%esp)
; CHECK32-NEXT: shrl $31, %ecx ; CHECK32-NEXT: shrl $31, %ecx
; CHECK32-NEXT: fildll (%esp) ; CHECK32-NEXT: fildll (%esp)
; CHECK32-NEXT: fadds {{\.LCPI.*}}(,%ecx,4) ; CHECK32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; CHECK32-NEXT: movl %ebp, %esp ; CHECK32-NEXT: movl %ebp, %esp
; CHECK32-NEXT: popl %ebp ; CHECK32-NEXT: popl %ebp
; CHECK32-NEXT: retl ; CHECK32-NEXT: retl
; ;
; CHECK64-LABEL: u64_to_x: ; CHECK64-LABEL: u64_to_x:
; CHECK64: # %bb.0: ; CHECK64: # %bb.0:
; CHECK64-NEXT: movq %rdi, -{{[0-9]+}}(%rsp) ; CHECK64-NEXT: movq %rdi, -{{[0-9]+}}(%rsp)
; CHECK64-NEXT: xorl %eax, %eax ; CHECK64-NEXT: xorl %eax, %eax
; CHECK64-NEXT: testq %rdi, %rdi ; CHECK64-NEXT: testq %rdi, %rdi
; CHECK64-NEXT: sets %al ; CHECK64-NEXT: sets %al
; CHECK64-NEXT: fildll -{{[0-9]+}}(%rsp) ; CHECK64-NEXT: fildll -{{[0-9]+}}(%rsp)
; CHECK64-NEXT: fadds {{\.LCPI.*}}(,%rax,4) ; CHECK64-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%rax,4)
; CHECK64-NEXT: retq ; CHECK64-NEXT: retq
%r = uitofp i64 %a to x86_fp80 %r = uitofp i64 %a to x86_fp80
ret x86_fp80 %r ret x86_fp80 %r
} }
define x86_fp80 @s64_to_x(i64 %a) nounwind { define x86_fp80 @s64_to_x(i64 %a) nounwind {
; CHECK32-LABEL: s64_to_x: ; CHECK32-LABEL: s64_to_x:
; CHECK32: # %bb.0: ; CHECK32: # %bb.0:
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llvm/test/CodeGen/X86/select-of-fp-constants.ll

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; This should do a single load into the fp stack for the return, not diddle with xmm registers. ; This should do a single load into the fp stack for the return, not diddle with xmm registers.
define float @icmp_select_fp_constants(i32 %x) nounwind readnone { define float @icmp_select_fp_constants(i32 %x) nounwind readnone {
; X86-LABEL: icmp_select_fp_constants: ; X86-LABEL: icmp_select_fp_constants:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: xorl %eax, %eax ; X86-NEXT: xorl %eax, %eax
; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp) ; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp)
; X86-NEXT: sete %al ; X86-NEXT: sete %al
; X86-NEXT: flds {{\.LCPI.*}}(,%eax,4) ; X86-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-SSE-LABEL: icmp_select_fp_constants: ; X64-SSE-LABEL: icmp_select_fp_constants:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: xorl %eax, %eax ; X64-SSE-NEXT: xorl %eax, %eax
; X64-SSE-NEXT: testl %edi, %edi ; X64-SSE-NEXT: testl %edi, %edi
; X64-SSE-NEXT: sete %al ; X64-SSE-NEXT: sete %al
; X64-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X64-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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define float @fcmp_select_fp_constants(float %x) nounwind readnone { define float @fcmp_select_fp_constants(float %x) nounwind readnone {
; X86-SSE-LABEL: fcmp_select_fp_constants: ; X86-SSE-LABEL: fcmp_select_fp_constants:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: cmpneqss {{[0-9]+}}(%esp), %xmm0 ; X86-SSE-NEXT: cmpneqss {{[0-9]+}}(%esp), %xmm0
; X86-SSE-NEXT: movd %xmm0, %eax ; X86-SSE-NEXT: movd %xmm0, %eax
; X86-SSE-NEXT: andl $1, %eax ; X86-SSE-NEXT: andl $1, %eax
; X86-SSE-NEXT: flds {{\.LCPI.*}}(,%eax,4) ; X86-SSE-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X86-AVX2-LABEL: fcmp_select_fp_constants: ; X86-AVX2-LABEL: fcmp_select_fp_constants:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-AVX2-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-AVX2-NEXT: vcmpneqss {{[0-9]+}}(%esp), %xmm0, %xmm0 ; X86-AVX2-NEXT: vcmpneqss {{[0-9]+}}(%esp), %xmm0, %xmm0
; X86-AVX2-NEXT: vmovd %xmm0, %eax ; X86-AVX2-NEXT: vmovd %xmm0, %eax
; X86-AVX2-NEXT: andl $1, %eax ; X86-AVX2-NEXT: andl $1, %eax
; X86-AVX2-NEXT: flds {{\.LCPI.*}}(,%eax,4) ; X86-AVX2-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; X86-AVX2-NEXT: retl ; X86-AVX2-NEXT: retl
; ;
; X86-AVX512F-LABEL: fcmp_select_fp_constants: ; X86-AVX512F-LABEL: fcmp_select_fp_constants:
; X86-AVX512F: # %bb.0: ; X86-AVX512F: # %bb.0:
; X86-AVX512F-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-AVX512F-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-AVX512F-NEXT: vcmpneqss {{\.LCPI.*}}, %xmm0, %k0 ; X86-AVX512F-NEXT: vcmpneqss {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %k0
; X86-AVX512F-NEXT: kmovw %k0, %eax ; X86-AVX512F-NEXT: kmovw %k0, %eax
; X86-AVX512F-NEXT: flds {{\.LCPI.*}}(,%eax,4) ; X86-AVX512F-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; X86-AVX512F-NEXT: retl ; X86-AVX512F-NEXT: retl
; ;
; X64-SSE-LABEL: fcmp_select_fp_constants: ; X64-SSE-LABEL: fcmp_select_fp_constants:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: cmpneqss {{.*}}(%rip), %xmm0 ; X64-SSE-NEXT: cmpneqss {{.*}}(%rip), %xmm0
; X64-SSE-NEXT: movd %xmm0, %eax ; X64-SSE-NEXT: movd %xmm0, %eax
; X64-SSE-NEXT: andl $1, %eax ; X64-SSE-NEXT: andl $1, %eax
; X64-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X64-SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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llvm/test/CodeGen/X86/select.ll

Show First 20 Lines • Show All 157 Lines • ▼ Show 20 Lines
; ATHLON-NEXT: flds LCPI2_0(,%eax,4) ; ATHLON-NEXT: flds LCPI2_0(,%eax,4)
; ATHLON-NEXT: retl ; ATHLON-NEXT: retl
; ;
; MCU-LABEL: test3: ; MCU-LABEL: test3:
; MCU: # %bb.0: # %entry ; MCU: # %bb.0: # %entry
; MCU-NEXT: xorl %ecx, %ecx ; MCU-NEXT: xorl %ecx, %ecx
; MCU-NEXT: testl %eax, %eax ; MCU-NEXT: testl %eax, %eax
; MCU-NEXT: sete %cl ; MCU-NEXT: sete %cl
; MCU-NEXT: flds {{\.LCPI.*}}(,%ecx,4) ; MCU-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}(,%ecx,4)
; MCU-NEXT: retl ; MCU-NEXT: retl
entry: entry:
%0 = icmp eq i32 %x, 0 %0 = icmp eq i32 %x, 0
%iftmp.0.0 = select i1 %0, float 4.200000e+01, float 2.300000e+01 %iftmp.0.0 = select i1 %0, float 4.200000e+01, float 2.300000e+01
ret float %iftmp.0.0 ret float %iftmp.0.0
} }
define signext i8 @test4(i8* nocapture %P, double %F) nounwind readonly { define signext i8 @test4(i8* nocapture %P, double %F) nounwind readonly {
Show All 17 Lines
; ATHLON-NEXT: seta %cl ; ATHLON-NEXT: seta %cl
; ATHLON-NEXT: movsbl (%eax,%ecx,4), %eax ; ATHLON-NEXT: movsbl (%eax,%ecx,4), %eax
; ATHLON-NEXT: retl ; ATHLON-NEXT: retl
; ;
; MCU-LABEL: test4: ; MCU-LABEL: test4:
; MCU: # %bb.0: # %entry ; MCU: # %bb.0: # %entry
; MCU-NEXT: movl %eax, %ecx ; MCU-NEXT: movl %eax, %ecx
; MCU-NEXT: fldl {{[0-9]+}}(%esp) ; MCU-NEXT: fldl {{[0-9]+}}(%esp)
; MCU-NEXT: flds {{\.LCPI.*}} ; MCU-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; MCU-NEXT: fucompp ; MCU-NEXT: fucompp
; MCU-NEXT: fnstsw %ax ; MCU-NEXT: fnstsw %ax
; MCU-NEXT: xorl %edx, %edx ; MCU-NEXT: xorl %edx, %edx
; MCU-NEXT: # kill: def $ah killed $ah killed $ax ; MCU-NEXT: # kill: def $ah killed $ah killed $ax
; MCU-NEXT: sahf ; MCU-NEXT: sahf
; MCU-NEXT: seta %dl ; MCU-NEXT: seta %dl
; MCU-NEXT: movb (%ecx,%edx,4), %al ; MCU-NEXT: movb (%ecx,%edx,4), %al
; MCU-NEXT: retl ; MCU-NEXT: retl
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; ATHLON-NEXT: fldt LCPI6_0(%eax) ; ATHLON-NEXT: fldt LCPI6_0(%eax)
; ATHLON-NEXT: retl ; ATHLON-NEXT: retl
; ;
; MCU-LABEL: test7: ; MCU-LABEL: test7:
; MCU: # %bb.0: ; MCU: # %bb.0:
; MCU-NEXT: notl %eax ; MCU-NEXT: notl %eax
; MCU-NEXT: shrl $27, %eax ; MCU-NEXT: shrl $27, %eax
; MCU-NEXT: andl $-16, %eax ; MCU-NEXT: andl $-16, %eax
; MCU-NEXT: fldt {{\.LCPI.*}}(%eax) ; MCU-NEXT: fldt {{\.LCPI[0-9]+_[0-9]+}}(%eax)
; MCU-NEXT: retl ; MCU-NEXT: retl
%tmp9 = icmp sgt i32 %tmp8, -1 %tmp9 = icmp sgt i32 %tmp8, -1
%retval = select i1 %tmp9, x86_fp80 0xK4005B400000000000000, x86_fp80 0xK40078700000000000000 %retval = select i1 %tmp9, x86_fp80 0xK4005B400000000000000, x86_fp80 0xK40078700000000000000
ret x86_fp80 %retval ret x86_fp80 %retval
} }
; widening select v6i32 and then a sub ; widening select v6i32 and then a sub
define void @test8(i1 %c, <6 x i32>* %dst.addr, <6 x i32> %src1,<6 x i32> %src2) nounwind { define void @test8(i1 %c, <6 x i32>* %dst.addr, <6 x i32> %src1,<6 x i32> %src2) nounwind {
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llvm/test/CodeGen/X86/setcc-lowering.ll

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; AVX-NEXT: vpackssdw %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vpackssdw %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vzeroupper ; AVX-NEXT: vzeroupper
; AVX-NEXT: retq ; AVX-NEXT: retq
; ;
; KNL-32-LABEL: pr25080: ; KNL-32-LABEL: pr25080:
; KNL-32: # %bb.0: # %entry ; KNL-32: # %bb.0: # %entry
; KNL-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 ; KNL-32-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
; KNL-32-NEXT: vptestnmd {{\.LCPI.*}}{1to16}, %zmm0, %k0 ; KNL-32-NEXT: vptestnmd {{\.LCPI[0-9]+_[0-9]+}}{1to16}, %zmm0, %k0
; KNL-32-NEXT: movb $15, %al ; KNL-32-NEXT: movb $15, %al
; KNL-32-NEXT: kmovw %eax, %k1 ; KNL-32-NEXT: kmovw %eax, %k1
; KNL-32-NEXT: korw %k1, %k0, %k1 ; KNL-32-NEXT: korw %k1, %k0, %k1
; KNL-32-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z} ; KNL-32-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; KNL-32-NEXT: vpmovdw %zmm0, %ymm0 ; KNL-32-NEXT: vpmovdw %zmm0, %ymm0
; KNL-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0 ; KNL-32-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
; KNL-32-NEXT: retl ; KNL-32-NEXT: retl
entry: entry:
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llvm/test/CodeGen/X86/shrink-fp-const2.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s ; RUN: llc < %s -mtriple=i686-- | FileCheck %s
; This should be a flds, not fldt. ; This should be a flds, not fldt.
define x86_fp80 @test2() nounwind { define x86_fp80 @test2() nounwind {
; CHECK-LABEL: test2: ; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: flds {{\.LCPI.*}} ; CHECK-NEXT: flds {{\.LCPI[0-9]+_[0-9]+}}
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
ret x86_fp80 0xK3FFFC000000000000000 ret x86_fp80 0xK3FFFC000000000000000
} }

llvm/test/CodeGen/X86/shrink_vmul.ll

Show First 20 Lines • Show All 1,400 Lines • ▼ Show 20 Lines
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-SSE-NEXT: movl c, %edx ; X86-SSE-NEXT: movl c, %edx
; X86-SSE-NEXT: movzwl (%ecx,%eax), %ecx ; X86-SSE-NEXT: movzwl (%ecx,%eax), %ecx
; X86-SSE-NEXT: movd %ecx, %xmm0 ; X86-SSE-NEXT: movd %ecx, %xmm0
; X86-SSE-NEXT: pxor %xmm1, %xmm1 ; X86-SSE-NEXT: pxor %xmm1, %xmm1
; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] ; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; X86-SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; X86-SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; X86-SSE-NEXT: pmaddwd {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmaddwd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movq %xmm0, (%edx,%eax,4) ; X86-SSE-NEXT: movq %xmm0, (%edx,%eax,4)
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X86-AVX-LABEL: mul_2xi8_varconst1: ; X86-AVX-LABEL: mul_2xi8_varconst1:
; X86-AVX: # %bb.0: # %entry ; X86-AVX: # %bb.0: # %entry
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-AVX-NEXT: movl c, %edx ; X86-AVX-NEXT: movl c, %edx
; X86-AVX-NEXT: movzwl (%ecx,%eax), %ecx ; X86-AVX-NEXT: movzwl (%ecx,%eax), %ecx
; X86-AVX-NEXT: vmovd %ecx, %xmm0 ; X86-AVX-NEXT: vmovd %ecx, %xmm0
; X86-AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; X86-AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; X86-AVX-NEXT: vpmaddwd {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpmaddwd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4) ; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4)
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE-LABEL: mul_2xi8_varconst1: ; X64-SSE-LABEL: mul_2xi8_varconst1:
; X64-SSE: # %bb.0: # %entry ; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: movq {{.*}}(%rip), %rax ; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
; X64-SSE-NEXT: movzwl (%rdi,%rsi), %ecx ; X64-SSE-NEXT: movzwl (%rdi,%rsi), %ecx
; X64-SSE-NEXT: movd %ecx, %xmm0 ; X64-SSE-NEXT: movd %ecx, %xmm0
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; X86-SSE: # %bb.0: # %entry ; X86-SSE: # %bb.0: # %entry
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-SSE-NEXT: movl c, %edx ; X86-SSE-NEXT: movl c, %edx
; X86-SSE-NEXT: movzwl (%ecx,%eax), %ecx ; X86-SSE-NEXT: movzwl (%ecx,%eax), %ecx
; X86-SSE-NEXT: movd %ecx, %xmm0 ; X86-SSE-NEXT: movd %ecx, %xmm0
; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X86-SSE-NEXT: psraw $8, %xmm0 ; X86-SSE-NEXT: psraw $8, %xmm0
; X86-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,1,4,5,6,7] ; X86-SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,2,1,4,5,6,7]
; X86-SSE-NEXT: psrad $16, %xmm0 ; X86-SSE-NEXT: psrad $16, %xmm0
; X86-SSE-NEXT: movq %xmm0, (%edx,%eax,4) ; X86-SSE-NEXT: movq %xmm0, (%edx,%eax,4)
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X86-AVX-LABEL: mul_2xi8_varconst2: ; X86-AVX-LABEL: mul_2xi8_varconst2:
; X86-AVX: # %bb.0: # %entry ; X86-AVX: # %bb.0: # %entry
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-AVX-NEXT: movl c, %edx ; X86-AVX-NEXT: movl c, %edx
; X86-AVX-NEXT: movzwl (%ecx,%eax), %ecx ; X86-AVX-NEXT: movzwl (%ecx,%eax), %ecx
; X86-AVX-NEXT: vmovd %ecx, %xmm0 ; X86-AVX-NEXT: vmovd %ecx, %xmm0
; X86-AVX-NEXT: vpmovsxbd %xmm0, %xmm0 ; X86-AVX-NEXT: vpmovsxbd %xmm0, %xmm0
; X86-AVX-NEXT: vpmulld {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4) ; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4)
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE-LABEL: mul_2xi8_varconst2: ; X64-SSE-LABEL: mul_2xi8_varconst2:
; X64-SSE: # %bb.0: # %entry ; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: movq {{.*}}(%rip), %rax ; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
; X64-SSE-NEXT: movzwl (%rdi,%rsi), %ecx ; X64-SSE-NEXT: movzwl (%rdi,%rsi), %ecx
; X64-SSE-NEXT: movd %ecx, %xmm0 ; X64-SSE-NEXT: movd %ecx, %xmm0
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; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-SSE-NEXT: movl c, %edx ; X86-SSE-NEXT: movl c, %edx
; X86-SSE-NEXT: movzwl (%ecx,%eax), %ecx ; X86-SSE-NEXT: movzwl (%ecx,%eax), %ecx
; X86-SSE-NEXT: movd %ecx, %xmm0 ; X86-SSE-NEXT: movd %ecx, %xmm0
; X86-SSE-NEXT: pxor %xmm1, %xmm1 ; X86-SSE-NEXT: pxor %xmm1, %xmm1
; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] ; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; X86-SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; X86-SSE-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; X86-SSE-NEXT: pmaddwd {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmaddwd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movq %xmm0, (%edx,%eax,4) ; X86-SSE-NEXT: movq %xmm0, (%edx,%eax,4)
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X86-AVX-LABEL: mul_2xi8_varconst3: ; X86-AVX-LABEL: mul_2xi8_varconst3:
; X86-AVX: # %bb.0: # %entry ; X86-AVX: # %bb.0: # %entry
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-AVX-NEXT: movl c, %edx ; X86-AVX-NEXT: movl c, %edx
; X86-AVX-NEXT: movzwl (%ecx,%eax), %ecx ; X86-AVX-NEXT: movzwl (%ecx,%eax), %ecx
; X86-AVX-NEXT: vmovd %ecx, %xmm0 ; X86-AVX-NEXT: vmovd %ecx, %xmm0
; X86-AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; X86-AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; X86-AVX-NEXT: vpmaddwd {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpmaddwd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4) ; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4)
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE-LABEL: mul_2xi8_varconst3: ; X64-SSE-LABEL: mul_2xi8_varconst3:
; X64-SSE: # %bb.0: # %entry ; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: movq {{.*}}(%rip), %rax ; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
; X64-SSE-NEXT: movzwl (%rdi,%rsi), %ecx ; X64-SSE-NEXT: movzwl (%rdi,%rsi), %ecx
; X64-SSE-NEXT: movd %ecx, %xmm0 ; X64-SSE-NEXT: movd %ecx, %xmm0
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; X86-AVX-LABEL: mul_2xi8_varconst4: ; X86-AVX-LABEL: mul_2xi8_varconst4:
; X86-AVX: # %bb.0: # %entry ; X86-AVX: # %bb.0: # %entry
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-AVX-NEXT: movl c, %edx ; X86-AVX-NEXT: movl c, %edx
; X86-AVX-NEXT: movzwl (%ecx,%eax), %ecx ; X86-AVX-NEXT: movzwl (%ecx,%eax), %ecx
; X86-AVX-NEXT: vmovd %ecx, %xmm0 ; X86-AVX-NEXT: vmovd %ecx, %xmm0
; X86-AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; X86-AVX-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; X86-AVX-NEXT: vpmulld {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4) ; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4)
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE-LABEL: mul_2xi8_varconst4: ; X64-SSE-LABEL: mul_2xi8_varconst4:
; X64-SSE: # %bb.0: # %entry ; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: movq {{.*}}(%rip), %rax ; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
; X64-SSE-NEXT: movzwl (%rdi,%rsi), %ecx ; X64-SSE-NEXT: movzwl (%rdi,%rsi), %ecx
; X64-SSE-NEXT: movd %ecx, %xmm0 ; X64-SSE-NEXT: movd %ecx, %xmm0
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; X86-AVX-LABEL: mul_2xi8_varconst5: ; X86-AVX-LABEL: mul_2xi8_varconst5:
; X86-AVX: # %bb.0: # %entry ; X86-AVX: # %bb.0: # %entry
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-AVX-NEXT: movl c, %edx ; X86-AVX-NEXT: movl c, %edx
; X86-AVX-NEXT: movzwl (%ecx,%eax), %ecx ; X86-AVX-NEXT: movzwl (%ecx,%eax), %ecx
; X86-AVX-NEXT: vmovd %ecx, %xmm0 ; X86-AVX-NEXT: vmovd %ecx, %xmm0
; X86-AVX-NEXT: vpmovsxbd %xmm0, %xmm0 ; X86-AVX-NEXT: vpmovsxbd %xmm0, %xmm0
; X86-AVX-NEXT: vpmulld {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4) ; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4)
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE-LABEL: mul_2xi8_varconst5: ; X64-SSE-LABEL: mul_2xi8_varconst5:
; X64-SSE: # %bb.0: # %entry ; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: movq {{.*}}(%rip), %rax ; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
; X64-SSE-NEXT: movzwl (%rdi,%rsi), %ecx ; X64-SSE-NEXT: movzwl (%rdi,%rsi), %ecx
; X64-SSE-NEXT: movd %ecx, %xmm0 ; X64-SSE-NEXT: movd %ecx, %xmm0
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; X86-AVX-LABEL: mul_2xi8_varconst6: ; X86-AVX-LABEL: mul_2xi8_varconst6:
; X86-AVX: # %bb.0: # %entry ; X86-AVX: # %bb.0: # %entry
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-AVX-NEXT: movl c, %edx ; X86-AVX-NEXT: movl c, %edx
; X86-AVX-NEXT: movzwl (%ecx,%eax), %ecx ; X86-AVX-NEXT: movzwl (%ecx,%eax), %ecx
; X86-AVX-NEXT: vmovd %ecx, %xmm0 ; X86-AVX-NEXT: vmovd %ecx, %xmm0
; X86-AVX-NEXT: vpmovsxbd %xmm0, %xmm0 ; X86-AVX-NEXT: vpmovsxbd %xmm0, %xmm0
; X86-AVX-NEXT: vpmulld {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4) ; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4)
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE-LABEL: mul_2xi8_varconst6: ; X64-SSE-LABEL: mul_2xi8_varconst6:
; X64-SSE: # %bb.0: # %entry ; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: movq {{.*}}(%rip), %rax ; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
; X64-SSE-NEXT: movzwl (%rdi,%rsi), %ecx ; X64-SSE-NEXT: movzwl (%rdi,%rsi), %ecx
; X64-SSE-NEXT: movd %ecx, %xmm0 ; X64-SSE-NEXT: movd %ecx, %xmm0
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; ;
; X86-AVX-LABEL: mul_2xi16_varconst1: ; X86-AVX-LABEL: mul_2xi16_varconst1:
; X86-AVX: # %bb.0: # %entry ; X86-AVX: # %bb.0: # %entry
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-AVX-NEXT: movl c, %edx ; X86-AVX-NEXT: movl c, %edx
; X86-AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero ; X86-AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; X86-AVX-NEXT: vpmulld {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4) ; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4)
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE-LABEL: mul_2xi16_varconst1: ; X64-SSE-LABEL: mul_2xi16_varconst1:
; X64-SSE: # %bb.0: # %entry ; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: movq {{.*}}(%rip), %rax ; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
; X64-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X64-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-SSE-NEXT: movdqa {{.*#+}} xmm1 = <0,65535,u,u,u,u,u,u> ; X64-SSE-NEXT: movdqa {{.*#+}} xmm1 = <0,65535,u,u,u,u,u,u>
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; ;
; X86-AVX-LABEL: mul_2xi16_varconst2: ; X86-AVX-LABEL: mul_2xi16_varconst2:
; X86-AVX: # %bb.0: # %entry ; X86-AVX: # %bb.0: # %entry
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-AVX-NEXT: movl c, %edx ; X86-AVX-NEXT: movl c, %edx
; X86-AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-AVX-NEXT: vpmovsxwd %xmm0, %xmm0 ; X86-AVX-NEXT: vpmovsxwd %xmm0, %xmm0
; X86-AVX-NEXT: vpmulld {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4) ; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4)
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE-LABEL: mul_2xi16_varconst2: ; X64-SSE-LABEL: mul_2xi16_varconst2:
; X64-SSE: # %bb.0: # %entry ; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: movq {{.*}}(%rip), %rax ; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
; X64-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X64-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-SSE-NEXT: movdqa {{.*#+}} xmm1 = <32768,32767,u,u,u,u,u,u> ; X64-SSE-NEXT: movdqa {{.*#+}} xmm1 = <32768,32767,u,u,u,u,u,u>
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define void @mul_2xi16_varconst3(i8* nocapture readonly %a, i64 %index) { define void @mul_2xi16_varconst3(i8* nocapture readonly %a, i64 %index) {
; X86-SSE-LABEL: mul_2xi16_varconst3: ; X86-SSE-LABEL: mul_2xi16_varconst3:
; X86-SSE: # %bb.0: # %entry ; X86-SSE: # %bb.0: # %entry
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-SSE-NEXT: movl c, %edx ; X86-SSE-NEXT: movl c, %edx
; X86-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: psrld $16, %xmm0 ; X86-SSE-NEXT: psrld $16, %xmm0
; X86-SSE-NEXT: pmuludq {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmuludq {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: psllq $32, %xmm0 ; X86-SSE-NEXT: psllq $32, %xmm0
; X86-SSE-NEXT: movq %xmm0, (%edx,%eax,4) ; X86-SSE-NEXT: movq %xmm0, (%edx,%eax,4)
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X86-AVX-LABEL: mul_2xi16_varconst3: ; X86-AVX-LABEL: mul_2xi16_varconst3:
; X86-AVX: # %bb.0: # %entry ; X86-AVX: # %bb.0: # %entry
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-AVX-NEXT: movl c, %edx ; X86-AVX-NEXT: movl c, %edx
; X86-AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero ; X86-AVX-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; X86-AVX-NEXT: vpmulld {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4) ; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4)
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE-LABEL: mul_2xi16_varconst3: ; X64-SSE-LABEL: mul_2xi16_varconst3:
; X64-SSE: # %bb.0: # %entry ; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: movq {{.*}}(%rip), %rax ; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
; X64-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X64-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-SSE-NEXT: psrld $16, %xmm0 ; X64-SSE-NEXT: psrld $16, %xmm0
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; X86-SSE: # %bb.0: # %entry ; X86-SSE: # %bb.0: # %entry
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-SSE-NEXT: movl c, %edx ; X86-SSE-NEXT: movl c, %edx
; X86-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0] ; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
; X86-SSE-NEXT: psrad $16, %xmm0 ; X86-SSE-NEXT: psrad $16, %xmm0
; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
; X86-SSE-NEXT: pmuludq {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmuludq {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: psllq $32, %xmm0 ; X86-SSE-NEXT: psllq $32, %xmm0
; X86-SSE-NEXT: movq %xmm0, (%edx,%eax,4) ; X86-SSE-NEXT: movq %xmm0, (%edx,%eax,4)
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X86-AVX-LABEL: mul_2xi16_varconst4: ; X86-AVX-LABEL: mul_2xi16_varconst4:
; X86-AVX: # %bb.0: # %entry ; X86-AVX: # %bb.0: # %entry
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-AVX-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-AVX-NEXT: movl c, %edx ; X86-AVX-NEXT: movl c, %edx
; X86-AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-AVX-NEXT: vpmovsxwd %xmm0, %xmm0 ; X86-AVX-NEXT: vpmovsxwd %xmm0, %xmm0
; X86-AVX-NEXT: vpmulld {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4) ; X86-AVX-NEXT: vmovq %xmm0, (%edx,%eax,4)
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE-LABEL: mul_2xi16_varconst4: ; X64-SSE-LABEL: mul_2xi16_varconst4:
; X64-SSE: # %bb.0: # %entry ; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: movq {{.*}}(%rip), %rax ; X64-SSE-NEXT: movq {{.*}}(%rip), %rax
; X64-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X64-SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0] ; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,0,0]
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llvm/test/CodeGen/X86/sink-addsub-of-const.ll

Show First 20 Lines • Show All 255 Lines • ▼ Show 20 Lines
; add (add %x, C), %y ; add (add %x, C), %y
; Outer 'add' is commutative - 2 variants. ; Outer 'add' is commutative - 2 variants.
define <4 x i32> @vec_sink_add_of_const_to_add0(<4 x i32> %a, <4 x i32> %b) { define <4 x i32> @vec_sink_add_of_const_to_add0(<4 x i32> %a, <4 x i32> %b) {
; X32-LABEL: vec_sink_add_of_const_to_add0: ; X32-LABEL: vec_sink_add_of_const_to_add0:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: paddd %xmm1, %xmm0 ; X32-NEXT: paddd %xmm1, %xmm0
; X32-NEXT: paddd {{\.LCPI.*}}, %xmm0 ; X32-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: vec_sink_add_of_const_to_add0: ; X64-LABEL: vec_sink_add_of_const_to_add0:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: paddd %xmm1, %xmm0 ; X64-NEXT: paddd %xmm1, %xmm0
; X64-NEXT: paddd {{.*}}(%rip), %xmm0 ; X64-NEXT: paddd {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%t0 = add <4 x i32> %a, <i32 42, i32 24, i32 undef, i32 46> ; constant always on RHS %t0 = add <4 x i32> %a, <i32 42, i32 24, i32 undef, i32 46> ; constant always on RHS
%r = add <4 x i32> %t0, %b %r = add <4 x i32> %t0, %b
ret <4 x i32> %r ret <4 x i32> %r
} }
define <4 x i32> @vec_sink_add_of_const_to_add1(<4 x i32> %a, <4 x i32> %b) { define <4 x i32> @vec_sink_add_of_const_to_add1(<4 x i32> %a, <4 x i32> %b) {
; X32-LABEL: vec_sink_add_of_const_to_add1: ; X32-LABEL: vec_sink_add_of_const_to_add1:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: paddd %xmm1, %xmm0 ; X32-NEXT: paddd %xmm1, %xmm0
; X32-NEXT: paddd {{\.LCPI.*}}, %xmm0 ; X32-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: vec_sink_add_of_const_to_add1: ; X64-LABEL: vec_sink_add_of_const_to_add1:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: paddd %xmm1, %xmm0 ; X64-NEXT: paddd %xmm1, %xmm0
; X64-NEXT: paddd {{.*}}(%rip), %xmm0 ; X64-NEXT: paddd {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%t0 = add <4 x i32> %a, <i32 42, i32 24, i32 undef, i32 46> ; constant always on RHS %t0 = add <4 x i32> %a, <i32 42, i32 24, i32 undef, i32 46> ; constant always on RHS
%r = add <4 x i32> %b, %t0 %r = add <4 x i32> %b, %t0
ret <4 x i32> %r ret <4 x i32> %r
} }
; add (sub %x, C), %y ; add (sub %x, C), %y
; Outer 'add' is commutative - 2 variants. ; Outer 'add' is commutative - 2 variants.
define <4 x i32> @vec_sink_sub_of_const_to_add0(<4 x i32> %a, <4 x i32> %b) { define <4 x i32> @vec_sink_sub_of_const_to_add0(<4 x i32> %a, <4 x i32> %b) {
; X32-LABEL: vec_sink_sub_of_const_to_add0: ; X32-LABEL: vec_sink_sub_of_const_to_add0:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: paddd %xmm1, %xmm0 ; X32-NEXT: paddd %xmm1, %xmm0
; X32-NEXT: psubd {{\.LCPI.*}}, %xmm0 ; X32-NEXT: psubd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: vec_sink_sub_of_const_to_add0: ; X64-LABEL: vec_sink_sub_of_const_to_add0:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: paddd %xmm1, %xmm0 ; X64-NEXT: paddd %xmm1, %xmm0
; X64-NEXT: psubd {{.*}}(%rip), %xmm0 ; X64-NEXT: psubd {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%t0 = sub <4 x i32> %a, <i32 42, i32 24, i32 undef, i32 46> %t0 = sub <4 x i32> %a, <i32 42, i32 24, i32 undef, i32 46>
%r = add <4 x i32> %t0, %b %r = add <4 x i32> %t0, %b
ret <4 x i32> %r ret <4 x i32> %r
} }
define <4 x i32> @vec_sink_sub_of_const_to_add1(<4 x i32> %a, <4 x i32> %b) { define <4 x i32> @vec_sink_sub_of_const_to_add1(<4 x i32> %a, <4 x i32> %b) {
; X32-LABEL: vec_sink_sub_of_const_to_add1: ; X32-LABEL: vec_sink_sub_of_const_to_add1:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: paddd %xmm1, %xmm0 ; X32-NEXT: paddd %xmm1, %xmm0
; X32-NEXT: psubd {{\.LCPI.*}}, %xmm0 ; X32-NEXT: psubd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: vec_sink_sub_of_const_to_add1: ; X64-LABEL: vec_sink_sub_of_const_to_add1:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: paddd %xmm1, %xmm0 ; X64-NEXT: paddd %xmm1, %xmm0
; X64-NEXT: psubd {{.*}}(%rip), %xmm0 ; X64-NEXT: psubd {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%t0 = sub <4 x i32> %a, <i32 42, i32 24, i32 undef, i32 46> %t0 = sub <4 x i32> %a, <i32 42, i32 24, i32 undef, i32 46>
%r = add <4 x i32> %b, %t0 %r = add <4 x i32> %b, %t0
ret <4 x i32> %r ret <4 x i32> %r
} }
; add (sub C, %x), %y ; add (sub C, %x), %y
; Outer 'add' is commutative - 2 variants. ; Outer 'add' is commutative - 2 variants.
define <4 x i32> @vec_sink_sub_from_const_to_add0(<4 x i32> %a, <4 x i32> %b) { define <4 x i32> @vec_sink_sub_from_const_to_add0(<4 x i32> %a, <4 x i32> %b) {
; X32-LABEL: vec_sink_sub_from_const_to_add0: ; X32-LABEL: vec_sink_sub_from_const_to_add0:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: psubd %xmm0, %xmm1 ; X32-NEXT: psubd %xmm0, %xmm1
; X32-NEXT: paddd {{\.LCPI.*}}, %xmm1 ; X32-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X32-NEXT: movdqa %xmm1, %xmm0 ; X32-NEXT: movdqa %xmm1, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: vec_sink_sub_from_const_to_add0: ; X64-LABEL: vec_sink_sub_from_const_to_add0:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: psubd %xmm0, %xmm1 ; X64-NEXT: psubd %xmm0, %xmm1
; X64-NEXT: paddd {{.*}}(%rip), %xmm1 ; X64-NEXT: paddd {{.*}}(%rip), %xmm1
; X64-NEXT: movdqa %xmm1, %xmm0 ; X64-NEXT: movdqa %xmm1, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%t0 = sub <4 x i32> <i32 42, i32 24, i32 undef, i32 46>, %a %t0 = sub <4 x i32> <i32 42, i32 24, i32 undef, i32 46>, %a
%r = add <4 x i32> %t0, %b %r = add <4 x i32> %t0, %b
ret <4 x i32> %r ret <4 x i32> %r
} }
define <4 x i32> @vec_sink_sub_from_const_to_add1(<4 x i32> %a, <4 x i32> %b) { define <4 x i32> @vec_sink_sub_from_const_to_add1(<4 x i32> %a, <4 x i32> %b) {
; X32-LABEL: vec_sink_sub_from_const_to_add1: ; X32-LABEL: vec_sink_sub_from_const_to_add1:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: psubd %xmm0, %xmm1 ; X32-NEXT: psubd %xmm0, %xmm1
; X32-NEXT: paddd {{\.LCPI.*}}, %xmm1 ; X32-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X32-NEXT: movdqa %xmm1, %xmm0 ; X32-NEXT: movdqa %xmm1, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: vec_sink_sub_from_const_to_add1: ; X64-LABEL: vec_sink_sub_from_const_to_add1:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: psubd %xmm0, %xmm1 ; X64-NEXT: psubd %xmm0, %xmm1
; X64-NEXT: paddd {{.*}}(%rip), %xmm1 ; X64-NEXT: paddd {{.*}}(%rip), %xmm1
; X64-NEXT: movdqa %xmm1, %xmm0 ; X64-NEXT: movdqa %xmm1, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%t0 = sub <4 x i32> <i32 42, i32 24, i32 undef, i32 46>, %a %t0 = sub <4 x i32> <i32 42, i32 24, i32 undef, i32 46>, %a
%r = add <4 x i32> %b, %t0 %r = add <4 x i32> %b, %t0
ret <4 x i32> %r ret <4 x i32> %r
} }
; sub (add %x, C), %y ; sub (add %x, C), %y
; sub %y, (add %x, C) ; sub %y, (add %x, C)
define <4 x i32> @vec_sink_add_of_const_to_sub(<4 x i32> %a, <4 x i32> %b) { define <4 x i32> @vec_sink_add_of_const_to_sub(<4 x i32> %a, <4 x i32> %b) {
; X32-LABEL: vec_sink_add_of_const_to_sub: ; X32-LABEL: vec_sink_add_of_const_to_sub:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: psubd %xmm1, %xmm0 ; X32-NEXT: psubd %xmm1, %xmm0
; X32-NEXT: paddd {{\.LCPI.*}}, %xmm0 ; X32-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: vec_sink_add_of_const_to_sub: ; X64-LABEL: vec_sink_add_of_const_to_sub:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: psubd %xmm1, %xmm0 ; X64-NEXT: psubd %xmm1, %xmm0
; X64-NEXT: paddd {{.*}}(%rip), %xmm0 ; X64-NEXT: paddd {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%t0 = add <4 x i32> %a, <i32 42, i32 24, i32 undef, i32 46> ; constant always on RHS %t0 = add <4 x i32> %a, <i32 42, i32 24, i32 undef, i32 46> ; constant always on RHS
%r = sub <4 x i32> %t0, %b %r = sub <4 x i32> %t0, %b
ret <4 x i32> %r ret <4 x i32> %r
} }
define <4 x i32> @vec_sink_add_of_const_to_sub2(<4 x i32> %a, <4 x i32> %b) { define <4 x i32> @vec_sink_add_of_const_to_sub2(<4 x i32> %a, <4 x i32> %b) {
; X32-LABEL: vec_sink_add_of_const_to_sub2: ; X32-LABEL: vec_sink_add_of_const_to_sub2:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: psubd %xmm0, %xmm1 ; X32-NEXT: psubd %xmm0, %xmm1
; X32-NEXT: psubd {{\.LCPI.*}}, %xmm1 ; X32-NEXT: psubd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X32-NEXT: movdqa %xmm1, %xmm0 ; X32-NEXT: movdqa %xmm1, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: vec_sink_add_of_const_to_sub2: ; X64-LABEL: vec_sink_add_of_const_to_sub2:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: psubd %xmm0, %xmm1 ; X64-NEXT: psubd %xmm0, %xmm1
; X64-NEXT: psubd {{.*}}(%rip), %xmm1 ; X64-NEXT: psubd {{.*}}(%rip), %xmm1
; X64-NEXT: movdqa %xmm1, %xmm0 ; X64-NEXT: movdqa %xmm1, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%t0 = add <4 x i32> %a, <i32 42, i32 24, i32 undef, i32 46> ; constant always on RHS %t0 = add <4 x i32> %a, <i32 42, i32 24, i32 undef, i32 46> ; constant always on RHS
%r = sub <4 x i32> %b, %t0 %r = sub <4 x i32> %b, %t0
ret <4 x i32> %r ret <4 x i32> %r
} }
; sub (sub %x, C), %y ; sub (sub %x, C), %y
; sub %y, (sub %x, C) ; sub %y, (sub %x, C)
define <4 x i32> @vec_sink_sub_of_const_to_sub(<4 x i32> %a, <4 x i32> %b) { define <4 x i32> @vec_sink_sub_of_const_to_sub(<4 x i32> %a, <4 x i32> %b) {
; X32-LABEL: vec_sink_sub_of_const_to_sub: ; X32-LABEL: vec_sink_sub_of_const_to_sub:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: psubd %xmm1, %xmm0 ; X32-NEXT: psubd %xmm1, %xmm0
; X32-NEXT: psubd {{\.LCPI.*}}, %xmm0 ; X32-NEXT: psubd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: vec_sink_sub_of_const_to_sub: ; X64-LABEL: vec_sink_sub_of_const_to_sub:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: psubd %xmm1, %xmm0 ; X64-NEXT: psubd %xmm1, %xmm0
; X64-NEXT: psubd {{.*}}(%rip), %xmm0 ; X64-NEXT: psubd {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%t0 = sub <4 x i32> %a, <i32 42, i32 24, i32 undef, i32 46> %t0 = sub <4 x i32> %a, <i32 42, i32 24, i32 undef, i32 46>
%r = sub <4 x i32> %t0, %b %r = sub <4 x i32> %t0, %b
ret <4 x i32> %r ret <4 x i32> %r
} }
define <4 x i32> @vec_sink_sub_of_const_to_sub2(<4 x i32> %a, <4 x i32> %b) { define <4 x i32> @vec_sink_sub_of_const_to_sub2(<4 x i32> %a, <4 x i32> %b) {
; X32-LABEL: vec_sink_sub_of_const_to_sub2: ; X32-LABEL: vec_sink_sub_of_const_to_sub2:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: psubd %xmm0, %xmm1 ; X32-NEXT: psubd %xmm0, %xmm1
; X32-NEXT: paddd {{\.LCPI.*}}, %xmm1 ; X32-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X32-NEXT: movdqa %xmm1, %xmm0 ; X32-NEXT: movdqa %xmm1, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: vec_sink_sub_of_const_to_sub2: ; X64-LABEL: vec_sink_sub_of_const_to_sub2:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: psubd %xmm0, %xmm1 ; X64-NEXT: psubd %xmm0, %xmm1
; X64-NEXT: paddd {{.*}}(%rip), %xmm1 ; X64-NEXT: paddd {{.*}}(%rip), %xmm1
; X64-NEXT: movdqa %xmm1, %xmm0 ; X64-NEXT: movdqa %xmm1, %xmm0
Show All 17 Lines; ALL-NEXT: ret{{[l|q]}}
%t0 = sub <4 x i32> <i32 42, i32 24, i32 undef, i32 46>, %a %t0 = sub <4 x i32> <i32 42, i32 24, i32 undef, i32 46>, %a
%r = sub <4 x i32> %t0, %b %r = sub <4 x i32> %t0, %b
ret <4 x i32> %r ret <4 x i32> %r
} }
define <4 x i32> @vec_sink_sub_from_const_to_sub2(<4 x i32> %a, <4 x i32> %b) { define <4 x i32> @vec_sink_sub_from_const_to_sub2(<4 x i32> %a, <4 x i32> %b) {
; X32-LABEL: vec_sink_sub_from_const_to_sub2: ; X32-LABEL: vec_sink_sub_from_const_to_sub2:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: paddd %xmm1, %xmm0 ; X32-NEXT: paddd %xmm1, %xmm0
; X32-NEXT: psubd {{\.LCPI.*}}, %xmm0 ; X32-NEXT: psubd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: vec_sink_sub_from_const_to_sub2: ; X64-LABEL: vec_sink_sub_from_const_to_sub2:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: paddd %xmm1, %xmm0 ; X64-NEXT: paddd %xmm1, %xmm0
; X64-NEXT: psubd {{.*}}(%rip), %xmm0 ; X64-NEXT: psubd {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%t0 = sub <4 x i32> <i32 42, i32 24, i32 undef, i32 46>, %a %t0 = sub <4 x i32> <i32 42, i32 24, i32 undef, i32 46>, %a
%r = sub <4 x i32> %b, %t0 %r = sub <4 x i32> %b, %t0
ret <4 x i32> %r ret <4 x i32> %r
} }

llvm/test/CodeGen/X86/slow-pmulld.ll

Show All 15 Lines
; Make sure that the slow-pmulld feature can be used without SSE4.1. ; Make sure that the slow-pmulld feature can be used without SSE4.1.
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=silvermont -mattr=-sse4.1 ; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=silvermont -mattr=-sse4.1
define <4 x i32> @test_mul_v4i32_v4i8(<4 x i8> %A) { define <4 x i32> @test_mul_v4i32_v4i8(<4 x i8> %A) {
; CHECK32-LABEL: test_mul_v4i32_v4i8: ; CHECK32-LABEL: test_mul_v4i32_v4i8:
; CHECK32: # %bb.0: ; CHECK32: # %bb.0:
; CHECK32-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; CHECK32-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; CHECK32-NEXT: pmaddwd {{\.LCPI.*}}, %xmm0 ; CHECK32-NEXT: pmaddwd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; CHECK32-NEXT: retl ; CHECK32-NEXT: retl
; ;
; CHECK64-LABEL: test_mul_v4i32_v4i8: ; CHECK64-LABEL: test_mul_v4i32_v4i8:
; CHECK64: # %bb.0: ; CHECK64: # %bb.0:
; CHECK64-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; CHECK64-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; CHECK64-NEXT: pmaddwd {{.*}}(%rip), %xmm0 ; CHECK64-NEXT: pmaddwd {{.*}}(%rip), %xmm0
; CHECK64-NEXT: retq ; CHECK64-NEXT: retq
; ;
; SSE4-32-LABEL: test_mul_v4i32_v4i8: ; SSE4-32-LABEL: test_mul_v4i32_v4i8:
; SSE4-32: # %bb.0: ; SSE4-32: # %bb.0:
; SSE4-32-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; SSE4-32-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; SSE4-32-NEXT: pmaddwd {{\.LCPI.*}}, %xmm0 ; SSE4-32-NEXT: pmaddwd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE4-32-NEXT: retl ; SSE4-32-NEXT: retl
; ;
; SSE4-64-LABEL: test_mul_v4i32_v4i8: ; SSE4-64-LABEL: test_mul_v4i32_v4i8:
; SSE4-64: # %bb.0: ; SSE4-64: # %bb.0:
; SSE4-64-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; SSE4-64-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; SSE4-64-NEXT: pmaddwd {{.*}}(%rip), %xmm0 ; SSE4-64-NEXT: pmaddwd {{.*}}(%rip), %xmm0
; SSE4-64-NEXT: retq ; SSE4-64-NEXT: retq
; ;
; AVX2-32-LABEL: test_mul_v4i32_v4i8: ; AVX2-32-LABEL: test_mul_v4i32_v4i8:
; AVX2-32: # %bb.0: ; AVX2-32: # %bb.0:
; AVX2-32-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; AVX2-32-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; AVX2-32-NEXT: vpmaddwd {{\.LCPI.*}}, %xmm0, %xmm0 ; AVX2-32-NEXT: vpmaddwd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX2-32-NEXT: retl ; AVX2-32-NEXT: retl
; ;
; AVX2-64-LABEL: test_mul_v4i32_v4i8: ; AVX2-64-LABEL: test_mul_v4i32_v4i8:
; AVX2-64: # %bb.0: ; AVX2-64: # %bb.0:
; AVX2-64-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; AVX2-64-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; AVX2-64-NEXT: vpmaddwd {{.*}}(%rip), %xmm0, %xmm0 ; AVX2-64-NEXT: vpmaddwd {{.*}}(%rip), %xmm0, %xmm0
; AVX2-64-NEXT: retq ; AVX2-64-NEXT: retq
; ;
; AVX512DQ-32-LABEL: test_mul_v4i32_v4i8: ; AVX512DQ-32-LABEL: test_mul_v4i32_v4i8:
; AVX512DQ-32: # %bb.0: ; AVX512DQ-32: # %bb.0:
; AVX512DQ-32-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; AVX512DQ-32-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; AVX512DQ-32-NEXT: vpmaddwd {{\.LCPI.*}}, %xmm0, %xmm0 ; AVX512DQ-32-NEXT: vpmaddwd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX512DQ-32-NEXT: retl ; AVX512DQ-32-NEXT: retl
; ;
; AVX512DQ-64-LABEL: test_mul_v4i32_v4i8: ; AVX512DQ-64-LABEL: test_mul_v4i32_v4i8:
; AVX512DQ-64: # %bb.0: ; AVX512DQ-64: # %bb.0:
; AVX512DQ-64-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; AVX512DQ-64-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; AVX512DQ-64-NEXT: vpmaddwd {{.*}}(%rip), %xmm0, %xmm0 ; AVX512DQ-64-NEXT: vpmaddwd {{.*}}(%rip), %xmm0, %xmm0
; AVX512DQ-64-NEXT: retq ; AVX512DQ-64-NEXT: retq
; ;
; AVX512BW-32-LABEL: test_mul_v4i32_v4i8: ; AVX512BW-32-LABEL: test_mul_v4i32_v4i8:
; AVX512BW-32: # %bb.0: ; AVX512BW-32: # %bb.0:
; AVX512BW-32-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; AVX512BW-32-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; AVX512BW-32-NEXT: vpmaddwd {{\.LCPI.*}}, %xmm0, %xmm0 ; AVX512BW-32-NEXT: vpmaddwd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX512BW-32-NEXT: retl ; AVX512BW-32-NEXT: retl
; ;
; AVX512BW-64-LABEL: test_mul_v4i32_v4i8: ; AVX512BW-64-LABEL: test_mul_v4i32_v4i8:
; AVX512BW-64: # %bb.0: ; AVX512BW-64: # %bb.0:
; AVX512BW-64-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; AVX512BW-64-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; AVX512BW-64-NEXT: vpmaddwd {{.*}}(%rip), %xmm0, %xmm0 ; AVX512BW-64-NEXT: vpmaddwd {{.*}}(%rip), %xmm0, %xmm0
; AVX512BW-64-NEXT: retq ; AVX512BW-64-NEXT: retq
; ;
▲ Show 20 Lines • Show All 82 Lines • ▼ Show 20 Lines
; SSE4-64-NEXT: movdqa {{.*#+}} xmm2 = [18778,18778,18778,18778] ; SSE4-64-NEXT: movdqa {{.*#+}} xmm2 = [18778,18778,18778,18778]
; SSE4-64-NEXT: pmaddwd %xmm2, %xmm0 ; SSE4-64-NEXT: pmaddwd %xmm2, %xmm0
; SSE4-64-NEXT: pmaddwd %xmm2, %xmm1 ; SSE4-64-NEXT: pmaddwd %xmm2, %xmm1
; SSE4-64-NEXT: retq ; SSE4-64-NEXT: retq
; ;
; AVX2-32-LABEL: test_mul_v8i32_v8i8: ; AVX2-32-LABEL: test_mul_v8i32_v8i8:
; AVX2-32: # %bb.0: ; AVX2-32: # %bb.0:
; AVX2-32-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero ; AVX2-32-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
; AVX2-32-NEXT: vpmaddwd {{\.LCPI.*}}, %ymm0, %ymm0 ; AVX2-32-NEXT: vpmaddwd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; AVX2-32-NEXT: retl ; AVX2-32-NEXT: retl
; ;
; AVX2-64-LABEL: test_mul_v8i32_v8i8: ; AVX2-64-LABEL: test_mul_v8i32_v8i8:
; AVX2-64: # %bb.0: ; AVX2-64: # %bb.0:
; AVX2-64-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero ; AVX2-64-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
; AVX2-64-NEXT: vpmaddwd {{.*}}(%rip), %ymm0, %ymm0 ; AVX2-64-NEXT: vpmaddwd {{.*}}(%rip), %ymm0, %ymm0
; AVX2-64-NEXT: retq ; AVX2-64-NEXT: retq
; ;
; AVX512DQ-32-LABEL: test_mul_v8i32_v8i8: ; AVX512DQ-32-LABEL: test_mul_v8i32_v8i8:
; AVX512DQ-32: # %bb.0: ; AVX512DQ-32: # %bb.0:
; AVX512DQ-32-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero ; AVX512DQ-32-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
; AVX512DQ-32-NEXT: vpmaddwd {{\.LCPI.*}}, %ymm0, %ymm0 ; AVX512DQ-32-NEXT: vpmaddwd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; AVX512DQ-32-NEXT: retl ; AVX512DQ-32-NEXT: retl
; ;
; AVX512DQ-64-LABEL: test_mul_v8i32_v8i8: ; AVX512DQ-64-LABEL: test_mul_v8i32_v8i8:
; AVX512DQ-64: # %bb.0: ; AVX512DQ-64: # %bb.0:
; AVX512DQ-64-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero ; AVX512DQ-64-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
; AVX512DQ-64-NEXT: vpmaddwd {{.*}}(%rip), %ymm0, %ymm0 ; AVX512DQ-64-NEXT: vpmaddwd {{.*}}(%rip), %ymm0, %ymm0
; AVX512DQ-64-NEXT: retq ; AVX512DQ-64-NEXT: retq
; ;
; AVX512BW-32-LABEL: test_mul_v8i32_v8i8: ; AVX512BW-32-LABEL: test_mul_v8i32_v8i8:
; AVX512BW-32: # %bb.0: ; AVX512BW-32: # %bb.0:
; AVX512BW-32-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero ; AVX512BW-32-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
; AVX512BW-32-NEXT: vpmaddwd {{\.LCPI.*}}, %ymm0, %ymm0 ; AVX512BW-32-NEXT: vpmaddwd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; AVX512BW-32-NEXT: retl ; AVX512BW-32-NEXT: retl
; ;
; AVX512BW-64-LABEL: test_mul_v8i32_v8i8: ; AVX512BW-64-LABEL: test_mul_v8i32_v8i8:
; AVX512BW-64: # %bb.0: ; AVX512BW-64: # %bb.0:
; AVX512BW-64-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero ; AVX512BW-64-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
; AVX512BW-64-NEXT: vpmaddwd {{.*}}(%rip), %ymm0, %ymm0 ; AVX512BW-64-NEXT: vpmaddwd {{.*}}(%rip), %ymm0, %ymm0
; AVX512BW-64-NEXT: retq ; AVX512BW-64-NEXT: retq
; ;
▲ Show 20 Lines • Show All 150 Lines • ▼ Show 20 Lines
; AVX2-64-NEXT: vpbroadcastd {{.*#+}} ymm2 = [18778,18778,18778,18778,18778,18778,18778,18778] ; AVX2-64-NEXT: vpbroadcastd {{.*#+}} ymm2 = [18778,18778,18778,18778,18778,18778,18778,18778]
; AVX2-64-NEXT: vpmaddwd %ymm2, %ymm0, %ymm0 ; AVX2-64-NEXT: vpmaddwd %ymm2, %ymm0, %ymm0
; AVX2-64-NEXT: vpmaddwd %ymm2, %ymm1, %ymm1 ; AVX2-64-NEXT: vpmaddwd %ymm2, %ymm1, %ymm1
; AVX2-64-NEXT: retq ; AVX2-64-NEXT: retq
; ;
; AVX512DQ-32-LABEL: test_mul_v16i32_v16i8: ; AVX512DQ-32-LABEL: test_mul_v16i32_v16i8:
; AVX512DQ-32: # %bb.0: ; AVX512DQ-32: # %bb.0:
; AVX512DQ-32-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero ; AVX512DQ-32-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; AVX512DQ-32-NEXT: vpmulld {{\.LCPI.*}}{1to16}, %zmm0, %zmm0 ; AVX512DQ-32-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}{1to16}, %zmm0, %zmm0
; AVX512DQ-32-NEXT: retl ; AVX512DQ-32-NEXT: retl
; ;
; AVX512DQ-64-LABEL: test_mul_v16i32_v16i8: ; AVX512DQ-64-LABEL: test_mul_v16i32_v16i8:
; AVX512DQ-64: # %bb.0: ; AVX512DQ-64: # %bb.0:
; AVX512DQ-64-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero ; AVX512DQ-64-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; AVX512DQ-64-NEXT: vpmulld {{.*}}(%rip){1to16}, %zmm0, %zmm0 ; AVX512DQ-64-NEXT: vpmulld {{.*}}(%rip){1to16}, %zmm0, %zmm0
; AVX512DQ-64-NEXT: retq ; AVX512DQ-64-NEXT: retq
; ;
; AVX512BW-32-LABEL: test_mul_v16i32_v16i8: ; AVX512BW-32-LABEL: test_mul_v16i32_v16i8:
; AVX512BW-32: # %bb.0: ; AVX512BW-32: # %bb.0:
; AVX512BW-32-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero ; AVX512BW-32-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; AVX512BW-32-NEXT: vpmaddwd {{\.LCPI.*}}, %zmm0, %zmm0 ; AVX512BW-32-NEXT: vpmaddwd {{\.LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0
; AVX512BW-32-NEXT: retl ; AVX512BW-32-NEXT: retl
; ;
; AVX512BW-64-LABEL: test_mul_v16i32_v16i8: ; AVX512BW-64-LABEL: test_mul_v16i32_v16i8:
; AVX512BW-64: # %bb.0: ; AVX512BW-64: # %bb.0:
; AVX512BW-64-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero ; AVX512BW-64-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; AVX512BW-64-NEXT: vpmaddwd {{.*}}(%rip), %zmm0, %zmm0 ; AVX512BW-64-NEXT: vpmaddwd {{.*}}(%rip), %zmm0, %zmm0
; AVX512BW-64-NEXT: retq ; AVX512BW-64-NEXT: retq
; ;
; KNL-32-LABEL: test_mul_v16i32_v16i8: ; KNL-32-LABEL: test_mul_v16i32_v16i8:
; KNL-32: # %bb.0: ; KNL-32: # %bb.0:
; KNL-32-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero ; KNL-32-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; KNL-32-NEXT: vpmulld {{\.LCPI.*}}{1to16}, %zmm0, %zmm0 ; KNL-32-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}{1to16}, %zmm0, %zmm0
; KNL-32-NEXT: retl ; KNL-32-NEXT: retl
; ;
; KNL-64-LABEL: test_mul_v16i32_v16i8: ; KNL-64-LABEL: test_mul_v16i32_v16i8:
; KNL-64: # %bb.0: ; KNL-64: # %bb.0:
; KNL-64-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero ; KNL-64-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; KNL-64-NEXT: vpmulld {{.*}}(%rip){1to16}, %zmm0, %zmm0 ; KNL-64-NEXT: vpmulld {{.*}}(%rip){1to16}, %zmm0, %zmm0
; KNL-64-NEXT: retq ; KNL-64-NEXT: retq
%z = zext <16 x i8> %A to <16 x i32> %z = zext <16 x i8> %A to <16 x i32>
Show All 18 Lines
; CHECK64-NEXT: pmulhuw %xmm1, %xmm2 ; CHECK64-NEXT: pmulhuw %xmm1, %xmm2
; CHECK64-NEXT: pmullw %xmm1, %xmm0 ; CHECK64-NEXT: pmullw %xmm1, %xmm0
; CHECK64-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3] ; CHECK64-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
; CHECK64-NEXT: retq ; CHECK64-NEXT: retq
; ;
; SSE4-32-LABEL: test_mul_v4i32_v4i16: ; SSE4-32-LABEL: test_mul_v4i32_v4i16:
; SSE4-32: # %bb.0: ; SSE4-32: # %bb.0:
; SSE4-32-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero ; SSE4-32-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; SSE4-32-NEXT: pmulld {{\.LCPI.*}}, %xmm0 ; SSE4-32-NEXT: pmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE4-32-NEXT: retl ; SSE4-32-NEXT: retl
; ;
; SSE4-64-LABEL: test_mul_v4i32_v4i16: ; SSE4-64-LABEL: test_mul_v4i32_v4i16:
; SSE4-64: # %bb.0: ; SSE4-64: # %bb.0:
; SSE4-64-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero ; SSE4-64-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; SSE4-64-NEXT: pmulld {{.*}}(%rip), %xmm0 ; SSE4-64-NEXT: pmulld {{.*}}(%rip), %xmm0
; SSE4-64-NEXT: retq ; SSE4-64-NEXT: retq
; ;
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; AVX2-64-NEXT: vpbroadcastd {{.*#+}} ymm2 = [18778,18778,18778,18778,18778,18778,18778,18778] ; AVX2-64-NEXT: vpbroadcastd {{.*#+}} ymm2 = [18778,18778,18778,18778,18778,18778,18778,18778]
; AVX2-64-NEXT: vpmulld %ymm2, %ymm0, %ymm0 ; AVX2-64-NEXT: vpmulld %ymm2, %ymm0, %ymm0
; AVX2-64-NEXT: vpmulld %ymm2, %ymm1, %ymm1 ; AVX2-64-NEXT: vpmulld %ymm2, %ymm1, %ymm1
; AVX2-64-NEXT: retq ; AVX2-64-NEXT: retq
; ;
; AVX512-32-LABEL: test_mul_v16i32_v16i16: ; AVX512-32-LABEL: test_mul_v16i32_v16i16:
; AVX512-32: # %bb.0: ; AVX512-32: # %bb.0:
; AVX512-32-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero ; AVX512-32-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512-32-NEXT: vpmulld {{\.LCPI.*}}{1to16}, %zmm0, %zmm0 ; AVX512-32-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}{1to16}, %zmm0, %zmm0
; AVX512-32-NEXT: retl ; AVX512-32-NEXT: retl
; ;
; AVX512-64-LABEL: test_mul_v16i32_v16i16: ; AVX512-64-LABEL: test_mul_v16i32_v16i16:
; AVX512-64: # %bb.0: ; AVX512-64: # %bb.0:
; AVX512-64-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero ; AVX512-64-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512-64-NEXT: vpmulld {{.*}}(%rip){1to16}, %zmm0, %zmm0 ; AVX512-64-NEXT: vpmulld {{.*}}(%rip){1to16}, %zmm0, %zmm0
; AVX512-64-NEXT: retq ; AVX512-64-NEXT: retq
%z = zext <16 x i16> %A to <16 x i32> %z = zext <16 x i16> %A to <16 x i32>
%m = mul nuw nsw <16 x i32> %z, <i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778> %m = mul nuw nsw <16 x i32> %z, <i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778>
ret <16 x i32> %m ret <16 x i32> %m
} }
; ;
; MinSize Tests ; MinSize Tests
; ;
define <4 x i32> @test_mul_v4i32_v4i8_minsize(<4 x i8> %A) minsize { define <4 x i32> @test_mul_v4i32_v4i8_minsize(<4 x i8> %A) minsize {
; CHECK32-LABEL: test_mul_v4i32_v4i8_minsize: ; CHECK32-LABEL: test_mul_v4i32_v4i8_minsize:
; CHECK32: # %bb.0: ; CHECK32: # %bb.0:
; CHECK32-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; CHECK32-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; CHECK32-NEXT: pmaddwd {{\.LCPI.*}}, %xmm0 ; CHECK32-NEXT: pmaddwd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; CHECK32-NEXT: retl ; CHECK32-NEXT: retl
; ;
; CHECK64-LABEL: test_mul_v4i32_v4i8_minsize: ; CHECK64-LABEL: test_mul_v4i32_v4i8_minsize:
; CHECK64: # %bb.0: ; CHECK64: # %bb.0:
; CHECK64-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; CHECK64-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; CHECK64-NEXT: pmaddwd {{.*}}(%rip), %xmm0 ; CHECK64-NEXT: pmaddwd {{.*}}(%rip), %xmm0
; CHECK64-NEXT: retq ; CHECK64-NEXT: retq
; ;
; SSE4-32-LABEL: test_mul_v4i32_v4i8_minsize: ; SSE4-32-LABEL: test_mul_v4i32_v4i8_minsize:
; SSE4-32: # %bb.0: ; SSE4-32: # %bb.0:
; SSE4-32-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; SSE4-32-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; SSE4-32-NEXT: pmaddwd {{\.LCPI.*}}, %xmm0 ; SSE4-32-NEXT: pmaddwd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE4-32-NEXT: retl ; SSE4-32-NEXT: retl
; ;
; SSE4-64-LABEL: test_mul_v4i32_v4i8_minsize: ; SSE4-64-LABEL: test_mul_v4i32_v4i8_minsize:
; SSE4-64: # %bb.0: ; SSE4-64: # %bb.0:
; SSE4-64-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; SSE4-64-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; SSE4-64-NEXT: pmaddwd {{.*}}(%rip), %xmm0 ; SSE4-64-NEXT: pmaddwd {{.*}}(%rip), %xmm0
; SSE4-64-NEXT: retq ; SSE4-64-NEXT: retq
; ;
; AVX2-32-LABEL: test_mul_v4i32_v4i8_minsize: ; AVX2-32-LABEL: test_mul_v4i32_v4i8_minsize:
; AVX2-32: # %bb.0: ; AVX2-32: # %bb.0:
; AVX2-32-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; AVX2-32-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; AVX2-32-NEXT: vpmaddwd {{\.LCPI.*}}, %xmm0, %xmm0 ; AVX2-32-NEXT: vpmaddwd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX2-32-NEXT: retl ; AVX2-32-NEXT: retl
; ;
; AVX2-64-LABEL: test_mul_v4i32_v4i8_minsize: ; AVX2-64-LABEL: test_mul_v4i32_v4i8_minsize:
; AVX2-64: # %bb.0: ; AVX2-64: # %bb.0:
; AVX2-64-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; AVX2-64-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; AVX2-64-NEXT: vpmaddwd {{.*}}(%rip), %xmm0, %xmm0 ; AVX2-64-NEXT: vpmaddwd {{.*}}(%rip), %xmm0, %xmm0
; AVX2-64-NEXT: retq ; AVX2-64-NEXT: retq
; ;
; AVX512DQ-32-LABEL: test_mul_v4i32_v4i8_minsize: ; AVX512DQ-32-LABEL: test_mul_v4i32_v4i8_minsize:
; AVX512DQ-32: # %bb.0: ; AVX512DQ-32: # %bb.0:
; AVX512DQ-32-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; AVX512DQ-32-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; AVX512DQ-32-NEXT: vpmaddwd {{\.LCPI.*}}, %xmm0, %xmm0 ; AVX512DQ-32-NEXT: vpmaddwd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX512DQ-32-NEXT: retl ; AVX512DQ-32-NEXT: retl
; ;
; AVX512DQ-64-LABEL: test_mul_v4i32_v4i8_minsize: ; AVX512DQ-64-LABEL: test_mul_v4i32_v4i8_minsize:
; AVX512DQ-64: # %bb.0: ; AVX512DQ-64: # %bb.0:
; AVX512DQ-64-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; AVX512DQ-64-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; AVX512DQ-64-NEXT: vpmaddwd {{.*}}(%rip), %xmm0, %xmm0 ; AVX512DQ-64-NEXT: vpmaddwd {{.*}}(%rip), %xmm0, %xmm0
; AVX512DQ-64-NEXT: retq ; AVX512DQ-64-NEXT: retq
; ;
; AVX512BW-32-LABEL: test_mul_v4i32_v4i8_minsize: ; AVX512BW-32-LABEL: test_mul_v4i32_v4i8_minsize:
; AVX512BW-32: # %bb.0: ; AVX512BW-32: # %bb.0:
; AVX512BW-32-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; AVX512BW-32-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; AVX512BW-32-NEXT: vpmaddwd {{\.LCPI.*}}, %xmm0, %xmm0 ; AVX512BW-32-NEXT: vpmaddwd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX512BW-32-NEXT: retl ; AVX512BW-32-NEXT: retl
; ;
; AVX512BW-64-LABEL: test_mul_v4i32_v4i8_minsize: ; AVX512BW-64-LABEL: test_mul_v4i32_v4i8_minsize:
; AVX512BW-64: # %bb.0: ; AVX512BW-64: # %bb.0:
; AVX512BW-64-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; AVX512BW-64-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; AVX512BW-64-NEXT: vpmaddwd {{.*}}(%rip), %xmm0, %xmm0 ; AVX512BW-64-NEXT: vpmaddwd {{.*}}(%rip), %xmm0, %xmm0
; AVX512BW-64-NEXT: retq ; AVX512BW-64-NEXT: retq
; ;
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; SSE4-64-NEXT: movdqa {{.*#+}} xmm2 = [18778,18778,18778,18778] ; SSE4-64-NEXT: movdqa {{.*#+}} xmm2 = [18778,18778,18778,18778]
; SSE4-64-NEXT: pmaddwd %xmm2, %xmm0 ; SSE4-64-NEXT: pmaddwd %xmm2, %xmm0
; SSE4-64-NEXT: pmaddwd %xmm2, %xmm1 ; SSE4-64-NEXT: pmaddwd %xmm2, %xmm1
; SSE4-64-NEXT: retq ; SSE4-64-NEXT: retq
; ;
; AVX2-32-LABEL: test_mul_v8i32_v8i8_minsize: ; AVX2-32-LABEL: test_mul_v8i32_v8i8_minsize:
; AVX2-32: # %bb.0: ; AVX2-32: # %bb.0:
; AVX2-32-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero ; AVX2-32-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
; AVX2-32-NEXT: vpmaddwd {{\.LCPI.*}}, %ymm0, %ymm0 ; AVX2-32-NEXT: vpmaddwd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; AVX2-32-NEXT: retl ; AVX2-32-NEXT: retl
; ;
; AVX2-64-LABEL: test_mul_v8i32_v8i8_minsize: ; AVX2-64-LABEL: test_mul_v8i32_v8i8_minsize:
; AVX2-64: # %bb.0: ; AVX2-64: # %bb.0:
; AVX2-64-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero ; AVX2-64-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
; AVX2-64-NEXT: vpmaddwd {{.*}}(%rip), %ymm0, %ymm0 ; AVX2-64-NEXT: vpmaddwd {{.*}}(%rip), %ymm0, %ymm0
; AVX2-64-NEXT: retq ; AVX2-64-NEXT: retq
; ;
; AVX512DQ-32-LABEL: test_mul_v8i32_v8i8_minsize: ; AVX512DQ-32-LABEL: test_mul_v8i32_v8i8_minsize:
; AVX512DQ-32: # %bb.0: ; AVX512DQ-32: # %bb.0:
; AVX512DQ-32-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero ; AVX512DQ-32-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
; AVX512DQ-32-NEXT: vpmaddwd {{\.LCPI.*}}, %ymm0, %ymm0 ; AVX512DQ-32-NEXT: vpmaddwd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; AVX512DQ-32-NEXT: retl ; AVX512DQ-32-NEXT: retl
; ;
; AVX512DQ-64-LABEL: test_mul_v8i32_v8i8_minsize: ; AVX512DQ-64-LABEL: test_mul_v8i32_v8i8_minsize:
; AVX512DQ-64: # %bb.0: ; AVX512DQ-64: # %bb.0:
; AVX512DQ-64-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero ; AVX512DQ-64-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
; AVX512DQ-64-NEXT: vpmaddwd {{.*}}(%rip), %ymm0, %ymm0 ; AVX512DQ-64-NEXT: vpmaddwd {{.*}}(%rip), %ymm0, %ymm0
; AVX512DQ-64-NEXT: retq ; AVX512DQ-64-NEXT: retq
; ;
; AVX512BW-32-LABEL: test_mul_v8i32_v8i8_minsize: ; AVX512BW-32-LABEL: test_mul_v8i32_v8i8_minsize:
; AVX512BW-32: # %bb.0: ; AVX512BW-32: # %bb.0:
; AVX512BW-32-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero ; AVX512BW-32-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
; AVX512BW-32-NEXT: vpmaddwd {{\.LCPI.*}}, %ymm0, %ymm0 ; AVX512BW-32-NEXT: vpmaddwd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; AVX512BW-32-NEXT: retl ; AVX512BW-32-NEXT: retl
; ;
; AVX512BW-64-LABEL: test_mul_v8i32_v8i8_minsize: ; AVX512BW-64-LABEL: test_mul_v8i32_v8i8_minsize:
; AVX512BW-64: # %bb.0: ; AVX512BW-64: # %bb.0:
; AVX512BW-64-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero ; AVX512BW-64-NEXT: vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
; AVX512BW-64-NEXT: vpmaddwd {{.*}}(%rip), %ymm0, %ymm0 ; AVX512BW-64-NEXT: vpmaddwd {{.*}}(%rip), %ymm0, %ymm0
; AVX512BW-64-NEXT: retq ; AVX512BW-64-NEXT: retq
; ;
▲ Show 20 Lines • Show All 130 Lines • ▼ Show 20 Lines
; AVX2-64-NEXT: vpbroadcastd {{.*#+}} ymm2 = [18778,18778,18778,18778,18778,18778,18778,18778] ; AVX2-64-NEXT: vpbroadcastd {{.*#+}} ymm2 = [18778,18778,18778,18778,18778,18778,18778,18778]
; AVX2-64-NEXT: vpmaddwd %ymm2, %ymm0, %ymm0 ; AVX2-64-NEXT: vpmaddwd %ymm2, %ymm0, %ymm0
; AVX2-64-NEXT: vpmaddwd %ymm2, %ymm1, %ymm1 ; AVX2-64-NEXT: vpmaddwd %ymm2, %ymm1, %ymm1
; AVX2-64-NEXT: retq ; AVX2-64-NEXT: retq
; ;
; AVX512DQ-32-LABEL: test_mul_v16i32_v16i8_minsize: ; AVX512DQ-32-LABEL: test_mul_v16i32_v16i8_minsize:
; AVX512DQ-32: # %bb.0: ; AVX512DQ-32: # %bb.0:
; AVX512DQ-32-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero ; AVX512DQ-32-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; AVX512DQ-32-NEXT: vpmulld {{\.LCPI.*}}{1to16}, %zmm0, %zmm0 ; AVX512DQ-32-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}{1to16}, %zmm0, %zmm0
; AVX512DQ-32-NEXT: retl ; AVX512DQ-32-NEXT: retl
; ;
; AVX512DQ-64-LABEL: test_mul_v16i32_v16i8_minsize: ; AVX512DQ-64-LABEL: test_mul_v16i32_v16i8_minsize:
; AVX512DQ-64: # %bb.0: ; AVX512DQ-64: # %bb.0:
; AVX512DQ-64-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero ; AVX512DQ-64-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; AVX512DQ-64-NEXT: vpmulld {{.*}}(%rip){1to16}, %zmm0, %zmm0 ; AVX512DQ-64-NEXT: vpmulld {{.*}}(%rip){1to16}, %zmm0, %zmm0
; AVX512DQ-64-NEXT: retq ; AVX512DQ-64-NEXT: retq
; ;
; AVX512BW-32-LABEL: test_mul_v16i32_v16i8_minsize: ; AVX512BW-32-LABEL: test_mul_v16i32_v16i8_minsize:
; AVX512BW-32: # %bb.0: ; AVX512BW-32: # %bb.0:
; AVX512BW-32-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero ; AVX512BW-32-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; AVX512BW-32-NEXT: vpmaddwd {{\.LCPI.*}}, %zmm0, %zmm0 ; AVX512BW-32-NEXT: vpmaddwd {{\.LCPI[0-9]+_[0-9]+}}, %zmm0, %zmm0
; AVX512BW-32-NEXT: retl ; AVX512BW-32-NEXT: retl
; ;
; AVX512BW-64-LABEL: test_mul_v16i32_v16i8_minsize: ; AVX512BW-64-LABEL: test_mul_v16i32_v16i8_minsize:
; AVX512BW-64: # %bb.0: ; AVX512BW-64: # %bb.0:
; AVX512BW-64-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero ; AVX512BW-64-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; AVX512BW-64-NEXT: vpmaddwd {{.*}}(%rip), %zmm0, %zmm0 ; AVX512BW-64-NEXT: vpmaddwd {{.*}}(%rip), %zmm0, %zmm0
; AVX512BW-64-NEXT: retq ; AVX512BW-64-NEXT: retq
; ;
; KNL-32-LABEL: test_mul_v16i32_v16i8_minsize: ; KNL-32-LABEL: test_mul_v16i32_v16i8_minsize:
; KNL-32: # %bb.0: ; KNL-32: # %bb.0:
; KNL-32-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero ; KNL-32-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; KNL-32-NEXT: vpmulld {{\.LCPI.*}}{1to16}, %zmm0, %zmm0 ; KNL-32-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}{1to16}, %zmm0, %zmm0
; KNL-32-NEXT: retl ; KNL-32-NEXT: retl
; ;
; KNL-64-LABEL: test_mul_v16i32_v16i8_minsize: ; KNL-64-LABEL: test_mul_v16i32_v16i8_minsize:
; KNL-64: # %bb.0: ; KNL-64: # %bb.0:
; KNL-64-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero ; KNL-64-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; KNL-64-NEXT: vpmulld {{.*}}(%rip){1to16}, %zmm0, %zmm0 ; KNL-64-NEXT: vpmulld {{.*}}(%rip){1to16}, %zmm0, %zmm0
; KNL-64-NEXT: retq ; KNL-64-NEXT: retq
%z = zext <16 x i8> %A to <16 x i32> %z = zext <16 x i8> %A to <16 x i32>
%m = mul nuw nsw <16 x i32> %z, <i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778> %m = mul nuw nsw <16 x i32> %z, <i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778>
ret <16 x i32> %m ret <16 x i32> %m
} }
define <4 x i32> @test_mul_v4i32_v4i16_minsize(<4 x i16> %A) minsize { define <4 x i32> @test_mul_v4i32_v4i16_minsize(<4 x i16> %A) minsize {
; CHECK32-LABEL: test_mul_v4i32_v4i16_minsize: ; CHECK32-LABEL: test_mul_v4i32_v4i16_minsize:
; CHECK32: # %bb.0: ; CHECK32: # %bb.0:
; CHECK32-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero ; CHECK32-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; CHECK32-NEXT: pmulld {{\.LCPI.*}}, %xmm0 ; CHECK32-NEXT: pmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; CHECK32-NEXT: retl ; CHECK32-NEXT: retl
; ;
; CHECK64-LABEL: test_mul_v4i32_v4i16_minsize: ; CHECK64-LABEL: test_mul_v4i32_v4i16_minsize:
; CHECK64: # %bb.0: ; CHECK64: # %bb.0:
; CHECK64-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero ; CHECK64-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; CHECK64-NEXT: pmulld {{.*}}(%rip), %xmm0 ; CHECK64-NEXT: pmulld {{.*}}(%rip), %xmm0
; CHECK64-NEXT: retq ; CHECK64-NEXT: retq
; ;
; SSE4-32-LABEL: test_mul_v4i32_v4i16_minsize: ; SSE4-32-LABEL: test_mul_v4i32_v4i16_minsize:
; SSE4-32: # %bb.0: ; SSE4-32: # %bb.0:
; SSE4-32-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero ; SSE4-32-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; SSE4-32-NEXT: pmulld {{\.LCPI.*}}, %xmm0 ; SSE4-32-NEXT: pmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE4-32-NEXT: retl ; SSE4-32-NEXT: retl
; ;
; SSE4-64-LABEL: test_mul_v4i32_v4i16_minsize: ; SSE4-64-LABEL: test_mul_v4i32_v4i16_minsize:
; SSE4-64: # %bb.0: ; SSE4-64: # %bb.0:
; SSE4-64-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero ; SSE4-64-NEXT: pmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; SSE4-64-NEXT: pmulld {{.*}}(%rip), %xmm0 ; SSE4-64-NEXT: pmulld {{.*}}(%rip), %xmm0
; SSE4-64-NEXT: retq ; SSE4-64-NEXT: retq
; ;
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; AVX2-64-NEXT: vpbroadcastd {{.*#+}} ymm2 = [18778,18778,18778,18778,18778,18778,18778,18778] ; AVX2-64-NEXT: vpbroadcastd {{.*#+}} ymm2 = [18778,18778,18778,18778,18778,18778,18778,18778]
; AVX2-64-NEXT: vpmulld %ymm2, %ymm0, %ymm0 ; AVX2-64-NEXT: vpmulld %ymm2, %ymm0, %ymm0
; AVX2-64-NEXT: vpmulld %ymm2, %ymm1, %ymm1 ; AVX2-64-NEXT: vpmulld %ymm2, %ymm1, %ymm1
; AVX2-64-NEXT: retq ; AVX2-64-NEXT: retq
; ;
; AVX512-32-LABEL: test_mul_v16i32_v16i16_minsize: ; AVX512-32-LABEL: test_mul_v16i32_v16i16_minsize:
; AVX512-32: # %bb.0: ; AVX512-32: # %bb.0:
; AVX512-32-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero ; AVX512-32-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512-32-NEXT: vpmulld {{\.LCPI.*}}{1to16}, %zmm0, %zmm0 ; AVX512-32-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}{1to16}, %zmm0, %zmm0
; AVX512-32-NEXT: retl ; AVX512-32-NEXT: retl
; ;
; AVX512-64-LABEL: test_mul_v16i32_v16i16_minsize: ; AVX512-64-LABEL: test_mul_v16i32_v16i16_minsize:
; AVX512-64: # %bb.0: ; AVX512-64: # %bb.0:
; AVX512-64-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero ; AVX512-64-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
; AVX512-64-NEXT: vpmulld {{.*}}(%rip){1to16}, %zmm0, %zmm0 ; AVX512-64-NEXT: vpmulld {{.*}}(%rip){1to16}, %zmm0, %zmm0
; AVX512-64-NEXT: retq ; AVX512-64-NEXT: retq
%z = zext <16 x i16> %A to <16 x i32> %z = zext <16 x i16> %A to <16 x i32>
%m = mul nuw nsw <16 x i32> %z, <i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778> %m = mul nuw nsw <16 x i32> %z, <i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778, i32 18778>
ret <16 x i32> %m ret <16 x i32> %m
} }

llvm/test/CodeGen/X86/sse-fcopysign.ll

Show First 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; LLVM Intrinsic ; LLVM Intrinsic
; ;
define float @int1(float %a, float %b) nounwind { define float @int1(float %a, float %b) nounwind {
; X32-LABEL: int1: ; X32-LABEL: int1:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: pushl %eax ; X32-NEXT: pushl %eax
; X32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X32-NEXT: andps {{\.LCPI.*}}, %xmm0 ; X32-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X32-NEXT: andps {{\.LCPI.*}}, %xmm1 ; X32-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X32-NEXT: orps %xmm0, %xmm1 ; X32-NEXT: orps %xmm0, %xmm1
; X32-NEXT: movss %xmm1, (%esp) ; X32-NEXT: movss %xmm1, (%esp)
; X32-NEXT: flds (%esp) ; X32-NEXT: flds (%esp)
; X32-NEXT: popl %eax ; X32-NEXT: popl %eax
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: int1: ; X64-LABEL: int1:
; X64: # %bb.0: ; X64: # %bb.0:
Show All 10 Lines
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: pushl %ebp ; X32-NEXT: pushl %ebp
; X32-NEXT: movl %esp, %ebp ; X32-NEXT: movl %esp, %ebp
; X32-NEXT: andl $-8, %esp ; X32-NEXT: andl $-8, %esp
; X32-NEXT: subl $8, %esp ; X32-NEXT: subl $8, %esp
; X32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X32-NEXT: addss 20(%ebp), %xmm0 ; X32-NEXT: addss 20(%ebp), %xmm0
; X32-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero ; X32-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; X32-NEXT: andps {{\.LCPI.*}}, %xmm1 ; X32-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X32-NEXT: cvtss2sd %xmm0, %xmm0 ; X32-NEXT: cvtss2sd %xmm0, %xmm0
; X32-NEXT: andps {{\.LCPI.*}}, %xmm0 ; X32-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-NEXT: orps %xmm1, %xmm0 ; X32-NEXT: orps %xmm1, %xmm0
; X32-NEXT: movlps %xmm0, (%esp) ; X32-NEXT: movlps %xmm0, (%esp)
; X32-NEXT: fldl (%esp) ; X32-NEXT: fldl (%esp)
; X32-NEXT: movl %ebp, %esp ; X32-NEXT: movl %ebp, %esp
; X32-NEXT: popl %ebp ; X32-NEXT: popl %ebp
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: int2: ; X64-LABEL: int2:
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llvm/test/CodeGen/X86/sse-load-ret.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -mcpu=yonah | FileCheck %s ; RUN: llc < %s -mtriple=i686-- -mcpu=yonah | FileCheck %s
define double @test1(double* %P) { define double @test1(double* %P) {
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax ; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK-NEXT: fldl (%eax) ; CHECK-NEXT: fldl (%eax)
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%X = load double, double* %P ; <double> [#uses=1] %X = load double, double* %P ; <double> [#uses=1]
ret double %X ret double %X
} }
define double @test2() { define double @test2() {
; CHECK-LABEL: test2: ; CHECK-LABEL: test2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: fldl {{\.LCPI.*}} ; CHECK-NEXT: fldl {{\.LCPI[0-9]+_[0-9]+}}
; CHECK-NEXT: retl ; CHECK-NEXT: retl
ret double 1.234560e+03 ret double 1.234560e+03
} }
define double @test3(i1 %B) { define double @test3(i1 %B) {
; CHECK-LABEL: test3: ; CHECK-LABEL: test3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
Show All 25 Lines

llvm/test/CodeGen/X86/sse1-fcopysign.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown -mattr=-sse2,+sse | FileCheck %s --check-prefix=X86 ; RUN: llc < %s -mtriple=i686-unknown -mattr=-sse2,+sse | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=-sse2,+sse | FileCheck %s --check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=-sse2,+sse | FileCheck %s --check-prefix=X64
define float @f32_pos(float %a, float %b) nounwind { define float @f32_pos(float %a, float %b) nounwind {
; X86-LABEL: f32_pos: ; X86-LABEL: f32_pos:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: pushl %eax ; X86-NEXT: pushl %eax
; X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-NEXT: andps {{\.LCPI.*}}, %xmm0 ; X86-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: movss %xmm0, (%esp) ; X86-NEXT: movss %xmm0, (%esp)
; X86-NEXT: flds (%esp) ; X86-NEXT: flds (%esp)
; X86-NEXT: popl %eax ; X86-NEXT: popl %eax
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: f32_pos: ; X64-LABEL: f32_pos:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: andps {{.*}}(%rip), %xmm0 ; X64-NEXT: andps {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%tmp = tail call float @llvm.copysign.f32(float %a, float 1.0) %tmp = tail call float @llvm.copysign.f32(float %a, float 1.0)
ret float %tmp ret float %tmp
} }
define float @f32_neg(float %a, float %b) nounwind { define float @f32_neg(float %a, float %b) nounwind {
; X86-LABEL: f32_neg: ; X86-LABEL: f32_neg:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: pushl %eax ; X86-NEXT: pushl %eax
; X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-NEXT: orps {{\.LCPI.*}}, %xmm0 ; X86-NEXT: orps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: movss %xmm0, (%esp) ; X86-NEXT: movss %xmm0, (%esp)
; X86-NEXT: flds (%esp) ; X86-NEXT: flds (%esp)
; X86-NEXT: popl %eax ; X86-NEXT: popl %eax
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: f32_neg: ; X64-LABEL: f32_neg:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: orps {{.*}}(%rip), %xmm0 ; X64-NEXT: orps {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%tmp = tail call float @llvm.copysign.f32(float %a, float -1.0) %tmp = tail call float @llvm.copysign.f32(float %a, float -1.0)
ret float %tmp ret float %tmp
} }
define <4 x float> @v4f32_pos(<4 x float> %a, <4 x float> %b) nounwind { define <4 x float> @v4f32_pos(<4 x float> %a, <4 x float> %b) nounwind {
; X86-LABEL: v4f32_pos: ; X86-LABEL: v4f32_pos:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: andps {{\.LCPI.*}}, %xmm0 ; X86-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: v4f32_pos: ; X64-LABEL: v4f32_pos:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: andps {{.*}}(%rip), %xmm0 ; X64-NEXT: andps {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%tmp = tail call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>) %tmp = tail call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>)
ret <4 x float> %tmp ret <4 x float> %tmp
} }
define <4 x float> @v4f32_neg(<4 x float> %a, <4 x float> %b) nounwind { define <4 x float> @v4f32_neg(<4 x float> %a, <4 x float> %b) nounwind {
; X86-LABEL: v4f32_neg: ; X86-LABEL: v4f32_neg:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: orps {{\.LCPI.*}}, %xmm0 ; X86-NEXT: orps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: v4f32_neg: ; X64-LABEL: v4f32_neg:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: orps {{.*}}(%rip), %xmm0 ; X64-NEXT: orps {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%tmp = tail call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> <float -1.0, float -1.0, float -1.0, float -1.0>) %tmp = tail call <4 x float> @llvm.copysign.v4f32(<4 x float> %a, <4 x float> <float -1.0, float -1.0, float -1.0, float -1.0>)
ret <4 x float> %tmp ret <4 x float> %tmp
} }
define <4 x float> @v4f32_const_mag(<4 x float> %a, <4 x float> %b) nounwind { define <4 x float> @v4f32_const_mag(<4 x float> %a, <4 x float> %b) nounwind {
; X86-LABEL: v4f32_const_mag: ; X86-LABEL: v4f32_const_mag:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: movaps %xmm1, %xmm0 ; X86-NEXT: movaps %xmm1, %xmm0
; X86-NEXT: andps {{\.LCPI.*}}, %xmm0 ; X86-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: orps {{\.LCPI.*}}, %xmm0 ; X86-NEXT: orps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: v4f32_const_mag: ; X64-LABEL: v4f32_const_mag:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: movaps %xmm1, %xmm0 ; X64-NEXT: movaps %xmm1, %xmm0
; X64-NEXT: andps {{.*}}(%rip), %xmm0 ; X64-NEXT: andps {{.*}}(%rip), %xmm0
; X64-NEXT: orps {{.*}}(%rip), %xmm0 ; X64-NEXT: orps {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%tmp = tail call <4 x float> @llvm.copysign.v4f32(<4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float> %b ) %tmp = tail call <4 x float> @llvm.copysign.v4f32(<4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>, <4 x float> %b )
ret <4 x float> %tmp ret <4 x float> %tmp
} }
declare float @llvm.copysign.f32(float, float) declare float @llvm.copysign.f32(float, float)
declare <4 x float> @llvm.copysign.v4f32(<4 x float>, <4 x float>) declare <4 x float> @llvm.copysign.v4f32(<4 x float>, <4 x float>)

llvm/test/CodeGen/X86/sse1.ll

Show First 20 Lines • Show All 174 Lines • ▼ Show 20 Lines
; X86-NEXT: movl %edx, (%esp) ; X86-NEXT: movl %edx, (%esp)
; X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; X86-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; X86-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; X86-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; X86-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; X86-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1] ; X86-NEXT: unpcklps {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
; X86-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm1[0] ; X86-NEXT: movlhps {{.*#+}} xmm2 = xmm2[0],xmm1[0]
; X86-NEXT: andps {{\.LCPI.*}}, %xmm2 ; X86-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-NEXT: movaps %xmm2, (%eax) ; X86-NEXT: movaps %xmm2, (%eax)
; X86-NEXT: addl $16, %esp ; X86-NEXT: addl $16, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: popl %ebx ; X86-NEXT: popl %ebx
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
; ;
; X64-LABEL: PR30512: ; X64-LABEL: PR30512:
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; ;
; We now no longer try to lower sqrt using rsqrt with SSE1 only as the ; We now no longer try to lower sqrt using rsqrt with SSE1 only as the
; v4i32 vselect mentioned above should never have been created. We ended up ; v4i32 vselect mentioned above should never have been created. We ended up
; scalarizing it anyway. ; scalarizing it anyway.
define <2 x float> @PR31672() #0 { define <2 x float> @PR31672() #0 {
; X86-LABEL: PR31672: ; X86-LABEL: PR31672:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: sqrtps {{\.LCPI.*}}, %xmm0 ; X86-NEXT: sqrtps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: PR31672: ; X64-LABEL: PR31672:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: sqrtps {{.*}}(%rip), %xmm0 ; X64-NEXT: sqrtps {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%t0 = call fast <2 x float> @llvm.sqrt.v2f32(<2 x float> <float 42.0, float 3.0>) %t0 = call fast <2 x float> @llvm.sqrt.v2f32(<2 x float> <float 42.0, float 3.0>)
ret <2 x float> %t0 ret <2 x float> %t0
} }
declare <2 x float> @llvm.sqrt.v2f32(<2 x float>) #1 declare <2 x float> @llvm.sqrt.v2f32(<2 x float>) #1
attributes #0 = { nounwind "unsafe-fp-math"="true" } attributes #0 = { nounwind "unsafe-fp-math"="true" }

llvm/test/CodeGen/X86/sse2.ll

Show First 20 Lines • Show All 669 Lines • ▼ Show 20 Lines
; AVX-NEXT: ret{{[l|q]}} ; AVX-NEXT: ret{{[l|q]}}
%1 = shufflevector <2 x i64> %i, <2 x i64> <i64 0, i64 undef>, <2 x i32> <i32 0, i32 2> %1 = shufflevector <2 x i64> %i, <2 x i64> <i64 0, i64 undef>, <2 x i32> <i32 0, i32 2>
ret <2 x i64> %1 ret <2 x i64> %1
} }
define <4 x i32> @PR19721(<4 x i32> %i) { define <4 x i32> @PR19721(<4 x i32> %i) {
; X86-SSE-LABEL: PR19721: ; X86-SSE-LABEL: PR19721:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: andps {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; AVX-LABEL: PR19721: ; AVX-LABEL: PR19721:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
; AVX-NEXT: ret{{[l|q]}} ; AVX-NEXT: ret{{[l|q]}}
; ;
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llvm/test/CodeGen/X86/sse3.ll

Show First 20 Lines • Show All 391 Lines • ▼ Show 20 Linesentry:
ret <16 x i8> %tmp9 ret <16 x i8> %tmp9
} }
; rdar://8520311 ; rdar://8520311
define <4 x i32> @t17() nounwind { define <4 x i32> @t17() nounwind {
; X86-LABEL: t17: ; X86-LABEL: t17:
; X86: # %bb.0: # %entry ; X86: # %bb.0: # %entry
; X86-NEXT: pshufd {{.*#+}} xmm0 = mem[0,1,0,1] ; X86-NEXT: pshufd {{.*#+}} xmm0 = mem[0,1,0,1]
; X86-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: t17: ; X64-LABEL: t17:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: pshufd {{.*#+}} xmm0 = mem[0,1,0,1] ; X64-NEXT: pshufd {{.*#+}} xmm0 = mem[0,1,0,1]
; X64-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-NEXT: pand {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
entry: entry:
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llvm/test/CodeGen/X86/uint64-to-float.ll

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; X86-NEXT: movl %esp, %ebp ; X86-NEXT: movl %esp, %ebp
; X86-NEXT: andl $-8, %esp ; X86-NEXT: andl $-8, %esp
; X86-NEXT: subl $16, %esp ; X86-NEXT: subl $16, %esp
; X86-NEXT: movl 12(%ebp), %eax ; X86-NEXT: movl 12(%ebp), %eax
; X86-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; X86-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-NEXT: movlps %xmm0, {{[0-9]+}}(%esp) ; X86-NEXT: movlps %xmm0, {{[0-9]+}}(%esp)
; X86-NEXT: shrl $31, %eax ; X86-NEXT: shrl $31, %eax
; X86-NEXT: fildll {{[0-9]+}}(%esp) ; X86-NEXT: fildll {{[0-9]+}}(%esp)
; X86-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; X86-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; X86-NEXT: fstps {{[0-9]+}}(%esp) ; X86-NEXT: fstps {{[0-9]+}}(%esp)
; X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-NEXT: movss %xmm0, (%esp) ; X86-NEXT: movss %xmm0, (%esp)
; X86-NEXT: flds (%esp) ; X86-NEXT: flds (%esp)
; X86-NEXT: movl %ebp, %esp ; X86-NEXT: movl %ebp, %esp
; X86-NEXT: popl %ebp ; X86-NEXT: popl %ebp
; X86-NEXT: retl ; X86-NEXT: retl
; ;
Show All 19 Lines

llvm/test/CodeGen/X86/uint_to_fp-2.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+sse2 | FileCheck %s ; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+sse2 | FileCheck %s
; rdar://6504833 ; rdar://6504833
define float @test1(i32 %x) nounwind readnone { define float @test1(i32 %x) nounwind readnone {
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %eax ; CHECK-NEXT: pushl %eax
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: orpd {{\.LCPI.*}}, %xmm0 ; CHECK-NEXT: orpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; CHECK-NEXT: subsd {{\.LCPI.*}}, %xmm0 ; CHECK-NEXT: subsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; CHECK-NEXT: cvtsd2ss %xmm0, %xmm0 ; CHECK-NEXT: cvtsd2ss %xmm0, %xmm0
; CHECK-NEXT: movss %xmm0, (%esp) ; CHECK-NEXT: movss %xmm0, (%esp)
; CHECK-NEXT: flds (%esp) ; CHECK-NEXT: flds (%esp)
; CHECK-NEXT: popl %eax ; CHECK-NEXT: popl %eax
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
%0 = uitofp i32 %x to float %0 = uitofp i32 %x to float
ret float %0 ret float %0
} }
; PR10802 ; PR10802
define float @test2(<4 x i32> %x) nounwind readnone ssp { define float @test2(<4 x i32> %x) nounwind readnone ssp {
; CHECK-LABEL: test2: ; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %eax ; CHECK-NEXT: pushl %eax
; CHECK-NEXT: xorps %xmm1, %xmm1 ; CHECK-NEXT: xorps %xmm1, %xmm1
; CHECK-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3] ; CHECK-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
; CHECK-NEXT: orps {{\.LCPI.*}}, %xmm1 ; CHECK-NEXT: orps {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; CHECK-NEXT: subsd {{\.LCPI.*}}, %xmm1 ; CHECK-NEXT: subsd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; CHECK-NEXT: xorps %xmm0, %xmm0 ; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: cvtsd2ss %xmm1, %xmm0 ; CHECK-NEXT: cvtsd2ss %xmm1, %xmm0
; CHECK-NEXT: movss %xmm0, (%esp) ; CHECK-NEXT: movss %xmm0, (%esp)
; CHECK-NEXT: flds (%esp) ; CHECK-NEXT: flds (%esp)
; CHECK-NEXT: popl %eax ; CHECK-NEXT: popl %eax
; CHECK-NEXT: retl ; CHECK-NEXT: retl
entry: entry:
%vecext = extractelement <4 x i32> %x, i32 0 %vecext = extractelement <4 x i32> %x, i32 0
%conv = uitofp i32 %vecext to float %conv = uitofp i32 %vecext to float
ret float %conv ret float %conv
} }

llvm/test/CodeGen/X86/uint_to_fp-3.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32-SSE ; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32-SSE
; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx | FileCheck %s --check-prefix=X32-AVX ; RUN: llc < %s -mtriple=i686-unknown -mattr=+avx | FileCheck %s --check-prefix=X32-AVX
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64-SSE ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64-SSE
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=X64-AVX ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=X64-AVX
;PR29079 ;PR29079
define <4 x float> @mask_ucvt_4i32_4f32(<4 x i32> %a) { define <4 x float> @mask_ucvt_4i32_4f32(<4 x i32> %a) {
; X32-SSE-LABEL: mask_ucvt_4i32_4f32: ; X32-SSE-LABEL: mask_ucvt_4i32_4f32:
; X32-SSE: # %bb.0: ; X32-SSE: # %bb.0:
; X32-SSE-NEXT: andps {{\.LCPI.*}}, %xmm0 ; X32-SSE-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-SSE-NEXT: cvtdq2ps %xmm0, %xmm0 ; X32-SSE-NEXT: cvtdq2ps %xmm0, %xmm0
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X32-AVX-LABEL: mask_ucvt_4i32_4f32: ; X32-AVX-LABEL: mask_ucvt_4i32_4f32:
; X32-AVX: # %bb.0: ; X32-AVX: # %bb.0:
; X32-AVX-NEXT: vandps {{\.LCPI.*}}, %xmm0, %xmm0 ; X32-AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32-AVX-NEXT: vcvtdq2ps %xmm0, %xmm0 ; X32-AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
; X32-AVX-NEXT: retl ; X32-AVX-NEXT: retl
; ;
; X64-SSE-LABEL: mask_ucvt_4i32_4f32: ; X64-SSE-LABEL: mask_ucvt_4i32_4f32:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: andps {{.*}}(%rip), %xmm0 ; X64-SSE-NEXT: andps {{.*}}(%rip), %xmm0
; X64-SSE-NEXT: cvtdq2ps %xmm0, %xmm0 ; X64-SSE-NEXT: cvtdq2ps %xmm0, %xmm0
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX-LABEL: mask_ucvt_4i32_4f32: ; X64-AVX-LABEL: mask_ucvt_4i32_4f32:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vcvtdq2ps %xmm0, %xmm0 ; X64-AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%and = and <4 x i32> %a, <i32 127, i32 255, i32 4095, i32 65595> %and = and <4 x i32> %a, <i32 127, i32 255, i32 4095, i32 65595>
%cvt = uitofp <4 x i32> %and to <4 x float> %cvt = uitofp <4 x i32> %and to <4 x float>
ret <4 x float> %cvt ret <4 x float> %cvt
} }
define <4 x double> @mask_ucvt_4i32_4f64(<4 x i32> %a) { define <4 x double> @mask_ucvt_4i32_4f64(<4 x i32> %a) {
; X32-SSE-LABEL: mask_ucvt_4i32_4f64: ; X32-SSE-LABEL: mask_ucvt_4i32_4f64:
; X32-SSE: # %bb.0: ; X32-SSE: # %bb.0:
; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X32-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-SSE-NEXT: cvtdq2pd %xmm0, %xmm2 ; X32-SSE-NEXT: cvtdq2pd %xmm0, %xmm2
; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3] ; X32-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
; X32-SSE-NEXT: cvtdq2pd %xmm0, %xmm1 ; X32-SSE-NEXT: cvtdq2pd %xmm0, %xmm1
; X32-SSE-NEXT: movaps %xmm2, %xmm0 ; X32-SSE-NEXT: movaps %xmm2, %xmm0
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X32-AVX-LABEL: mask_ucvt_4i32_4f64: ; X32-AVX-LABEL: mask_ucvt_4i32_4f64:
; X32-AVX: # %bb.0: ; X32-AVX: # %bb.0:
; X32-AVX-NEXT: vandps {{\.LCPI.*}}, %xmm0, %xmm0 ; X32-AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32-AVX-NEXT: vcvtdq2pd %xmm0, %ymm0 ; X32-AVX-NEXT: vcvtdq2pd %xmm0, %ymm0
; X32-AVX-NEXT: retl ; X32-AVX-NEXT: retl
; ;
; X64-SSE-LABEL: mask_ucvt_4i32_4f64: ; X64-SSE-LABEL: mask_ucvt_4i32_4f64:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE-NEXT: cvtdq2pd %xmm0, %xmm2 ; X64-SSE-NEXT: cvtdq2pd %xmm0, %xmm2
; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3] ; X64-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
Show All 16 Lines
; X32-SSE-LABEL: lshr_truncate_mask_ucvt_4i64_4f32: ; X32-SSE-LABEL: lshr_truncate_mask_ucvt_4i64_4f32:
; X32-SSE: # %bb.0: ; X32-SSE: # %bb.0:
; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: movups (%eax), %xmm0 ; X32-SSE-NEXT: movups (%eax), %xmm0
; X32-SSE-NEXT: movups 16(%eax), %xmm1 ; X32-SSE-NEXT: movups 16(%eax), %xmm1
; X32-SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; X32-SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; X32-SSE-NEXT: psrld $16, %xmm0 ; X32-SSE-NEXT: psrld $16, %xmm0
; X32-SSE-NEXT: cvtdq2ps %xmm0, %xmm0 ; X32-SSE-NEXT: cvtdq2ps %xmm0, %xmm0
; X32-SSE-NEXT: mulps {{\.LCPI.*}}, %xmm0 ; X32-SSE-NEXT: mulps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X32-AVX-LABEL: lshr_truncate_mask_ucvt_4i64_4f32: ; X32-AVX-LABEL: lshr_truncate_mask_ucvt_4i64_4f32:
; X32-AVX: # %bb.0: ; X32-AVX: # %bb.0:
; X32-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax ; X32-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-AVX-NEXT: vmovups (%eax), %xmm0 ; X32-AVX-NEXT: vmovups (%eax), %xmm0
; X32-AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],mem[0,2] ; X32-AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],mem[0,2]
; X32-AVX-NEXT: vpsrld $16, %xmm0, %xmm0 ; X32-AVX-NEXT: vpsrld $16, %xmm0, %xmm0
; X32-AVX-NEXT: vcvtdq2ps %xmm0, %xmm0 ; X32-AVX-NEXT: vcvtdq2ps %xmm0, %xmm0
; X32-AVX-NEXT: vmulps {{\.LCPI.*}}, %xmm0, %xmm0 ; X32-AVX-NEXT: vmulps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X32-AVX-NEXT: retl ; X32-AVX-NEXT: retl
; ;
; X64-SSE-LABEL: lshr_truncate_mask_ucvt_4i64_4f32: ; X64-SSE-LABEL: lshr_truncate_mask_ucvt_4i64_4f32:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: movups (%rdi), %xmm0 ; X64-SSE-NEXT: movups (%rdi), %xmm0
; X64-SSE-NEXT: movups 16(%rdi), %xmm1 ; X64-SSE-NEXT: movups 16(%rdi), %xmm1
; X64-SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; X64-SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; X64-SSE-NEXT: psrld $16, %xmm0 ; X64-SSE-NEXT: psrld $16, %xmm0
Show All 19 Lines

llvm/test/CodeGen/X86/urem-power-of-two.ll

Show First 20 Lines • Show All 100 Lines • ▼ Show 20 Lines; X64-NEXT: retq
ret i8 %urem ret i8 %urem
} }
; A vector constant divisor should get the same treatment as a scalar. ; A vector constant divisor should get the same treatment as a scalar.
define <4 x i32> @vec_const_uniform_pow_2(<4 x i32> %x) { define <4 x i32> @vec_const_uniform_pow_2(<4 x i32> %x) {
; X86-LABEL: vec_const_uniform_pow_2: ; X86-LABEL: vec_const_uniform_pow_2:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: andps {{\.LCPI.*}}, %xmm0 ; X86-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: vec_const_uniform_pow_2: ; X64-LABEL: vec_const_uniform_pow_2:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: andps {{.*}}(%rip), %xmm0 ; X64-NEXT: andps {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%urem = urem <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16> %urem = urem <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16>
ret <4 x i32> %urem ret <4 x i32> %urem
} }
define <4 x i32> @vec_const_nonuniform_pow_2(<4 x i32> %x) { define <4 x i32> @vec_const_nonuniform_pow_2(<4 x i32> %x) {
; X86-LABEL: vec_const_nonuniform_pow_2: ; X86-LABEL: vec_const_nonuniform_pow_2:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: andps {{\.LCPI.*}}, %xmm0 ; X86-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: vec_const_nonuniform_pow_2: ; X64-LABEL: vec_const_nonuniform_pow_2:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: andps {{.*}}(%rip), %xmm0 ; X64-NEXT: andps {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%urem = urem <4 x i32> %x, <i32 2, i32 4, i32 8, i32 16> %urem = urem <4 x i32> %x, <i32 2, i32 4, i32 8, i32 16>
ret <4 x i32> %urem ret <4 x i32> %urem
} }

llvm/test/CodeGen/X86/var-permute-256.ll

Show All 28 Lines
; AVX1-NEXT: vpaddq %xmm1, %xmm1, %xmm3 ; AVX1-NEXT: vpaddq %xmm1, %xmm1, %xmm3
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
; AVX1-NEXT: vpaddq %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vpaddq %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm4 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm4
; AVX1-NEXT: vpermilpd %ymm4, %ymm2, %ymm2 ; AVX1-NEXT: vpermilpd %ymm4, %ymm2, %ymm2
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; AVX1-NEXT: vpermilpd %ymm4, %ymm0, %ymm0 ; AVX1-NEXT: vpermilpd %ymm4, %ymm0, %ymm0
; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm3, %xmm3 ; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm3, %xmm3
; AVX1-NEXT: vpcmpgtq {{\.LCPI.*}}+{{.*}}(%rip), %xmm1, %xmm1 ; AVX1-NEXT: vpcmpgtq {{\.LCPI[0-9]+_[0-9]+}}+{{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm1 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm1
; AVX1-NEXT: vblendvpd %ymm1, %ymm2, %ymm0, %ymm0 ; AVX1-NEXT: vblendvpd %ymm1, %ymm2, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: var_shuffle_v4i64: ; AVX2-LABEL: var_shuffle_v4i64:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddq %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpaddq %ymm1, %ymm1, %ymm1
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [2,2,2,2] ; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [2,2,2,2]
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; AVX1-LABEL: var_shuffle_v8i32: ; AVX1-LABEL: var_shuffle_v8i32:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vperm2f128 {{.*#+}} ymm2 = ymm0[2,3,2,3] ; AVX1-NEXT: vperm2f128 {{.*#+}} ymm2 = ymm0[2,3,2,3]
; AVX1-NEXT: vpermilps %ymm1, %ymm2, %ymm2 ; AVX1-NEXT: vpermilps %ymm1, %ymm2, %ymm2
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; AVX1-NEXT: vpermilps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vpermilps %ymm1, %ymm0, %ymm0
; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm1, %xmm3 ; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm1, %xmm3
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
; AVX1-NEXT: vpcmpgtd {{\.LCPI.*}}+{{.*}}(%rip), %xmm1, %xmm1 ; AVX1-NEXT: vpcmpgtd {{\.LCPI[0-9]+_[0-9]+}}+{{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm1 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm1
; AVX1-NEXT: vblendvps %ymm1, %ymm2, %ymm0, %ymm0 ; AVX1-NEXT: vblendvps %ymm1, %ymm2, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; INT256-LABEL: var_shuffle_v8i32: ; INT256-LABEL: var_shuffle_v8i32:
; INT256: # %bb.0: ; INT256: # %bb.0:
; INT256-NEXT: vpermps %ymm0, %ymm1, %ymm0 ; INT256-NEXT: vpermps %ymm0, %ymm1, %ymm0
; INT256-NEXT: retq ; INT256-NEXT: retq
▲ Show 20 Lines • Show All 343 Lines • ▼ Show 20 Lines
; AVX1-NEXT: vpaddq %xmm1, %xmm1, %xmm3 ; AVX1-NEXT: vpaddq %xmm1, %xmm1, %xmm3
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
; AVX1-NEXT: vpaddq %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vpaddq %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm4 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm4
; AVX1-NEXT: vpermilpd %ymm4, %ymm2, %ymm2 ; AVX1-NEXT: vpermilpd %ymm4, %ymm2, %ymm2
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; AVX1-NEXT: vpermilpd %ymm4, %ymm0, %ymm0 ; AVX1-NEXT: vpermilpd %ymm4, %ymm0, %ymm0
; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm3, %xmm3 ; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm3, %xmm3
; AVX1-NEXT: vpcmpgtq {{\.LCPI.*}}+{{.*}}(%rip), %xmm1, %xmm1 ; AVX1-NEXT: vpcmpgtq {{\.LCPI[0-9]+_[0-9]+}}+{{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm1 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm1
; AVX1-NEXT: vblendvpd %ymm1, %ymm2, %ymm0, %ymm0 ; AVX1-NEXT: vblendvpd %ymm1, %ymm2, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: var_shuffle_v4f64: ; AVX2-LABEL: var_shuffle_v4f64:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: vpaddq %ymm1, %ymm1, %ymm1 ; AVX2-NEXT: vpaddq %ymm1, %ymm1, %ymm1
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [2,2,2,2] ; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [2,2,2,2]
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; AVX1-LABEL: var_shuffle_v8f32: ; AVX1-LABEL: var_shuffle_v8f32:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
; AVX1-NEXT: vperm2f128 {{.*#+}} ymm2 = ymm0[2,3,2,3] ; AVX1-NEXT: vperm2f128 {{.*#+}} ymm2 = ymm0[2,3,2,3]
; AVX1-NEXT: vpermilps %ymm1, %ymm2, %ymm2 ; AVX1-NEXT: vpermilps %ymm1, %ymm2, %ymm2
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; AVX1-NEXT: vpermilps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vpermilps %ymm1, %ymm0, %ymm0
; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm1, %xmm3 ; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm1, %xmm3
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
; AVX1-NEXT: vpcmpgtd {{\.LCPI.*}}+{{.*}}(%rip), %xmm1, %xmm1 ; AVX1-NEXT: vpcmpgtd {{\.LCPI[0-9]+_[0-9]+}}+{{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm1 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm1
; AVX1-NEXT: vblendvps %ymm1, %ymm2, %ymm0, %ymm0 ; AVX1-NEXT: vblendvps %ymm1, %ymm2, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; INT256-LABEL: var_shuffle_v8f32: ; INT256-LABEL: var_shuffle_v8f32:
; INT256: # %bb.0: ; INT256: # %bb.0:
; INT256-NEXT: vpermps %ymm0, %ymm1, %ymm0 ; INT256-NEXT: vpermps %ymm0, %ymm1, %ymm0
; INT256-NEXT: retq ; INT256-NEXT: retq
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; AVX1-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0 ; AVX1-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; AVX1-NEXT: vpaddq %xmm1, %xmm1, %xmm2 ; AVX1-NEXT: vpaddq %xmm1, %xmm1, %xmm2
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
; AVX1-NEXT: vpaddq %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vpaddq %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm3 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm3
; AVX1-NEXT: vpermilpd %ymm3, %ymm0, %ymm0 ; AVX1-NEXT: vpermilpd %ymm3, %ymm0, %ymm0
; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm2, %xmm2 ; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vpcmpgtq {{\.LCPI.*}}+{{.*}}(%rip), %xmm1, %xmm1 ; AVX1-NEXT: vpcmpgtq {{\.LCPI[0-9]+_[0-9]+}}+{{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
; AVX1-NEXT: vpermilpd %ymm3, %ymm0, %ymm2 ; AVX1-NEXT: vpermilpd %ymm3, %ymm0, %ymm2
; AVX1-NEXT: vblendvpd %ymm1, %ymm2, %ymm0, %ymm0 ; AVX1-NEXT: vblendvpd %ymm1, %ymm2, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: var_shuffle_v4i64_from_v2i64: ; AVX2-LABEL: var_shuffle_v4i64_from_v2i64:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0 ; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; AVX1-LABEL: var_shuffle_v8i32_from_v4i32: ; AVX1-LABEL: var_shuffle_v8i32_from_v4i32:
; AVX1: # %bb.0: # %entry ; AVX1: # %bb.0: # %entry
; AVX1-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0 ; AVX1-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX1-NEXT: vpermilps %ymm1, %ymm0, %ymm2 ; AVX1-NEXT: vpermilps %ymm1, %ymm0, %ymm2
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; AVX1-NEXT: vpermilps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vpermilps %ymm1, %ymm0, %ymm0
; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm1, %xmm3 ; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm1, %xmm3
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
; AVX1-NEXT: vpcmpgtd {{\.LCPI.*}}+{{.*}}(%rip), %xmm1, %xmm1 ; AVX1-NEXT: vpcmpgtd {{\.LCPI[0-9]+_[0-9]+}}+{{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm1 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm1
; AVX1-NEXT: vblendvps %ymm1, %ymm2, %ymm0, %ymm0 ; AVX1-NEXT: vblendvps %ymm1, %ymm2, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; INT256-LABEL: var_shuffle_v8i32_from_v4i32: ; INT256-LABEL: var_shuffle_v8i32_from_v4i32:
; INT256: # %bb.0: # %entry ; INT256: # %bb.0: # %entry
; INT256-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0 ; INT256-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
; INT256-NEXT: vpermps %ymm0, %ymm1, %ymm0 ; INT256-NEXT: vpermps %ymm0, %ymm1, %ymm0
▲ Show 20 Lines • Show All 342 Lines • ▼ Show 20 Lines
; AVX1-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0 ; AVX1-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; AVX1-NEXT: vpaddq %xmm1, %xmm1, %xmm2 ; AVX1-NEXT: vpaddq %xmm1, %xmm1, %xmm2
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
; AVX1-NEXT: vpaddq %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vpaddq %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm3 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm3
; AVX1-NEXT: vpermilpd %ymm3, %ymm0, %ymm0 ; AVX1-NEXT: vpermilpd %ymm3, %ymm0, %ymm0
; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm2, %xmm2 ; AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm2, %xmm2
; AVX1-NEXT: vpcmpgtq {{\.LCPI.*}}+{{.*}}(%rip), %xmm1, %xmm1 ; AVX1-NEXT: vpcmpgtq {{\.LCPI[0-9]+_[0-9]+}}+{{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1
; AVX1-NEXT: vpermilpd %ymm3, %ymm0, %ymm2 ; AVX1-NEXT: vpermilpd %ymm3, %ymm0, %ymm2
; AVX1-NEXT: vblendvpd %ymm1, %ymm2, %ymm0, %ymm0 ; AVX1-NEXT: vblendvpd %ymm1, %ymm2, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: var_shuffle_v4f64_from_v2f64: ; AVX2-LABEL: var_shuffle_v4f64_from_v2f64:
; AVX2: # %bb.0: ; AVX2: # %bb.0:
; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0 ; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; AVX1-LABEL: var_shuffle_v8f32_from_v4f32: ; AVX1-LABEL: var_shuffle_v8f32_from_v4f32:
; AVX1: # %bb.0: # %entry ; AVX1: # %bb.0: # %entry
; AVX1-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0 ; AVX1-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX1-NEXT: vpermilps %ymm1, %ymm0, %ymm2 ; AVX1-NEXT: vpermilps %ymm1, %ymm0, %ymm2
; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
; AVX1-NEXT: vpermilps %ymm1, %ymm0, %ymm0 ; AVX1-NEXT: vpermilps %ymm1, %ymm0, %ymm0
; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm1, %xmm3 ; AVX1-NEXT: vpcmpgtd {{.*}}(%rip), %xmm1, %xmm3
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
; AVX1-NEXT: vpcmpgtd {{\.LCPI.*}}+{{.*}}(%rip), %xmm1, %xmm1 ; AVX1-NEXT: vpcmpgtd {{\.LCPI[0-9]+_[0-9]+}}+{{.*}}(%rip), %xmm1, %xmm1
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm1 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm3, %ymm1
; AVX1-NEXT: vblendvps %ymm1, %ymm2, %ymm0, %ymm0 ; AVX1-NEXT: vblendvps %ymm1, %ymm2, %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; INT256-LABEL: var_shuffle_v8f32_from_v4f32: ; INT256-LABEL: var_shuffle_v8f32_from_v4f32:
; INT256: # %bb.0: # %entry ; INT256: # %bb.0: # %entry
; INT256-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0 ; INT256-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0
; INT256-NEXT: vpermps %ymm0, %ymm1, %ymm0 ; INT256-NEXT: vpermps %ymm0, %ymm1, %ymm0
▲ Show 20 Lines • Show All 69 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vec-strict-fptoint-128.ll

Show First 20 Lines • Show All 2,025 Lines • ▼ Show 20 Lines %ret = call <2 x i16> @llvm.experimental.constrained.fptoui.v2i16.v2f32(<2 x float> %a,
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <2 x i16> %ret ret <2 x i16> %ret
} }
define <2 x i8> @strict_vector_fptosi_v2f64_to_v2i8(<2 x double> %a) #0 { define <2 x i8> @strict_vector_fptosi_v2f64_to_v2i8(<2 x double> %a) #0 {
; SSE-32-LABEL: strict_vector_fptosi_v2f64_to_v2i8: ; SSE-32-LABEL: strict_vector_fptosi_v2f64_to_v2i8:
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: cvttpd2dq %xmm0, %xmm0 ; SSE-32-NEXT: cvttpd2dq %xmm0, %xmm0
; SSE-32-NEXT: andpd {{\.LCPI.*}}, %xmm0 ; SSE-32-NEXT: andpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE-32-NEXT: packuswb %xmm0, %xmm0 ; SSE-32-NEXT: packuswb %xmm0, %xmm0
; SSE-32-NEXT: packuswb %xmm0, %xmm0 ; SSE-32-NEXT: packuswb %xmm0, %xmm0
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: strict_vector_fptosi_v2f64_to_v2i8: ; SSE-64-LABEL: strict_vector_fptosi_v2f64_to_v2i8:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: cvttpd2dq %xmm0, %xmm0 ; SSE-64-NEXT: cvttpd2dq %xmm0, %xmm0
; SSE-64-NEXT: andpd {{.*}}(%rip), %xmm0 ; SSE-64-NEXT: andpd {{.*}}(%rip), %xmm0
Show All 34 Lines %ret = call <2 x i8> @llvm.experimental.constrained.fptosi.v2i8.v2f64(<2 x double> %a,
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <2 x i8> %ret ret <2 x i8> %ret
} }
define <2 x i8> @strict_vector_fptoui_v2f64_to_v2i8(<2 x double> %a) #0 { define <2 x i8> @strict_vector_fptoui_v2f64_to_v2i8(<2 x double> %a) #0 {
; SSE-32-LABEL: strict_vector_fptoui_v2f64_to_v2i8: ; SSE-32-LABEL: strict_vector_fptoui_v2f64_to_v2i8:
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: cvttpd2dq %xmm0, %xmm0 ; SSE-32-NEXT: cvttpd2dq %xmm0, %xmm0
; SSE-32-NEXT: andpd {{\.LCPI.*}}, %xmm0 ; SSE-32-NEXT: andpd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE-32-NEXT: packuswb %xmm0, %xmm0 ; SSE-32-NEXT: packuswb %xmm0, %xmm0
; SSE-32-NEXT: packuswb %xmm0, %xmm0 ; SSE-32-NEXT: packuswb %xmm0, %xmm0
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: strict_vector_fptoui_v2f64_to_v2i8: ; SSE-64-LABEL: strict_vector_fptoui_v2f64_to_v2i8:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: cvttpd2dq %xmm0, %xmm0 ; SSE-64-NEXT: cvttpd2dq %xmm0, %xmm0
; SSE-64-NEXT: andpd {{.*}}(%rip), %xmm0 ; SSE-64-NEXT: andpd {{.*}}(%rip), %xmm0
Show All 35 Lines; AVX512VLDQ-NEXT: ret{{[l|q]}}
ret <2 x i8> %ret ret <2 x i8> %ret
} }
define <2 x i8> @strict_vector_fptosi_v2f32_to_v2i8(<2 x float> %a) #0 { define <2 x i8> @strict_vector_fptosi_v2f32_to_v2i8(<2 x float> %a) #0 {
; SSE-32-LABEL: strict_vector_fptosi_v2f32_to_v2i8: ; SSE-32-LABEL: strict_vector_fptosi_v2f32_to_v2i8:
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero ; SSE-32-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
; SSE-32-NEXT: cvttps2dq %xmm0, %xmm0 ; SSE-32-NEXT: cvttps2dq %xmm0, %xmm0
; SSE-32-NEXT: pand {{\.LCPI.*}}, %xmm0 ; SSE-32-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE-32-NEXT: packuswb %xmm0, %xmm0 ; SSE-32-NEXT: packuswb %xmm0, %xmm0
; SSE-32-NEXT: packuswb %xmm0, %xmm0 ; SSE-32-NEXT: packuswb %xmm0, %xmm0
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: strict_vector_fptosi_v2f32_to_v2i8: ; SSE-64-LABEL: strict_vector_fptosi_v2f32_to_v2i8:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero ; SSE-64-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
; SSE-64-NEXT: cvttps2dq %xmm0, %xmm0 ; SSE-64-NEXT: cvttps2dq %xmm0, %xmm0
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines; AVX512VLDQ-NEXT: ret{{[l|q]}}
ret <2 x i8> %ret ret <2 x i8> %ret
} }
define <2 x i8> @strict_vector_fptoui_v2f32_to_v2i8(<2 x float> %a) #0 { define <2 x i8> @strict_vector_fptoui_v2f32_to_v2i8(<2 x float> %a) #0 {
; SSE-32-LABEL: strict_vector_fptoui_v2f32_to_v2i8: ; SSE-32-LABEL: strict_vector_fptoui_v2f32_to_v2i8:
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero ; SSE-32-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
; SSE-32-NEXT: cvttps2dq %xmm0, %xmm0 ; SSE-32-NEXT: cvttps2dq %xmm0, %xmm0
; SSE-32-NEXT: pand {{\.LCPI.*}}, %xmm0 ; SSE-32-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE-32-NEXT: packuswb %xmm0, %xmm0 ; SSE-32-NEXT: packuswb %xmm0, %xmm0
; SSE-32-NEXT: packuswb %xmm0, %xmm0 ; SSE-32-NEXT: packuswb %xmm0, %xmm0
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: strict_vector_fptoui_v2f32_to_v2i8: ; SSE-64-LABEL: strict_vector_fptoui_v2f32_to_v2i8:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero ; SSE-64-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
; SSE-64-NEXT: cvttps2dq %xmm0, %xmm0 ; SSE-64-NEXT: cvttps2dq %xmm0, %xmm0
▲ Show 20 Lines • Show All 828 Lines • ▼ Show 20 Lines
define <4 x i32> @strict_vector_fptoui_v4f32_to_v4i32(<4 x float> %a) #0 { define <4 x i32> @strict_vector_fptoui_v4f32_to_v4i32(<4 x float> %a) #0 {
; SSE-32-LABEL: strict_vector_fptoui_v4f32_to_v4i32: ; SSE-32-LABEL: strict_vector_fptoui_v4f32_to_v4i32:
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: movaps {{.*#+}} xmm2 = [2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9] ; SSE-32-NEXT: movaps {{.*#+}} xmm2 = [2.14748365E+9,2.14748365E+9,2.14748365E+9,2.14748365E+9]
; SSE-32-NEXT: movaps %xmm0, %xmm3 ; SSE-32-NEXT: movaps %xmm0, %xmm3
; SSE-32-NEXT: cmpltps %xmm2, %xmm3 ; SSE-32-NEXT: cmpltps %xmm2, %xmm3
; SSE-32-NEXT: movaps %xmm3, %xmm1 ; SSE-32-NEXT: movaps %xmm3, %xmm1
; SSE-32-NEXT: andnps {{\.LCPI.*}}, %xmm1 ; SSE-32-NEXT: andnps {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; SSE-32-NEXT: andnps %xmm2, %xmm3 ; SSE-32-NEXT: andnps %xmm2, %xmm3
; SSE-32-NEXT: subps %xmm3, %xmm0 ; SSE-32-NEXT: subps %xmm3, %xmm0
; SSE-32-NEXT: cvttps2dq %xmm0, %xmm0 ; SSE-32-NEXT: cvttps2dq %xmm0, %xmm0
; SSE-32-NEXT: xorps %xmm0, %xmm1 ; SSE-32-NEXT: xorps %xmm0, %xmm1
; SSE-32-NEXT: movaps %xmm1, %xmm0 ; SSE-32-NEXT: movaps %xmm1, %xmm0
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: strict_vector_fptoui_v4f32_to_v4i32: ; SSE-64-LABEL: strict_vector_fptoui_v4f32_to_v4i32:
▲ Show 20 Lines • Show All 271 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vec-strict-inttofp-128.ll

Show First 20 Lines • Show All 272 Lines • ▼ Show 20 Lines
; SSE-32-NEXT: subl $24, %esp ; SSE-32-NEXT: subl $24, %esp
; SSE-32-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3] ; SSE-32-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; SSE-32-NEXT: movq %xmm1, {{[0-9]+}}(%esp) ; SSE-32-NEXT: movq %xmm1, {{[0-9]+}}(%esp)
; SSE-32-NEXT: movq %xmm0, {{[0-9]+}}(%esp) ; SSE-32-NEXT: movq %xmm0, {{[0-9]+}}(%esp)
; SSE-32-NEXT: pshufd {{.*#+}} xmm1 = xmm0[3,3,3,3] ; SSE-32-NEXT: pshufd {{.*#+}} xmm1 = xmm0[3,3,3,3]
; SSE-32-NEXT: movd %xmm1, %eax ; SSE-32-NEXT: movd %xmm1, %eax
; SSE-32-NEXT: shrl $31, %eax ; SSE-32-NEXT: shrl $31, %eax
; SSE-32-NEXT: fildll {{[0-9]+}}(%esp) ; SSE-32-NEXT: fildll {{[0-9]+}}(%esp)
; SSE-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; SSE-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; SSE-32-NEXT: fstps (%esp) ; SSE-32-NEXT: fstps (%esp)
; SSE-32-NEXT: wait ; SSE-32-NEXT: wait
; SSE-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1] ; SSE-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
; SSE-32-NEXT: movd %xmm0, %eax ; SSE-32-NEXT: movd %xmm0, %eax
; SSE-32-NEXT: shrl $31, %eax ; SSE-32-NEXT: shrl $31, %eax
; SSE-32-NEXT: fildll {{[0-9]+}}(%esp) ; SSE-32-NEXT: fildll {{[0-9]+}}(%esp)
; SSE-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; SSE-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; SSE-32-NEXT: fstps {{[0-9]+}}(%esp) ; SSE-32-NEXT: fstps {{[0-9]+}}(%esp)
; SSE-32-NEXT: wait ; SSE-32-NEXT: wait
; SSE-32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; SSE-32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE-32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE-32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE-32-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSE-32-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: .cfi_def_cfa %esp, 4 ; SSE-32-NEXT: .cfi_def_cfa %esp, 4
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; SSE41-32-NEXT: subl $24, %esp ; SSE41-32-NEXT: subl $24, %esp
; SSE41-32-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3] ; SSE41-32-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; SSE41-32-NEXT: movq %xmm1, {{[0-9]+}}(%esp) ; SSE41-32-NEXT: movq %xmm1, {{[0-9]+}}(%esp)
; SSE41-32-NEXT: movq %xmm0, {{[0-9]+}}(%esp) ; SSE41-32-NEXT: movq %xmm0, {{[0-9]+}}(%esp)
; SSE41-32-NEXT: pshufd {{.*#+}} xmm1 = xmm0[3,3,3,3] ; SSE41-32-NEXT: pshufd {{.*#+}} xmm1 = xmm0[3,3,3,3]
; SSE41-32-NEXT: movd %xmm1, %eax ; SSE41-32-NEXT: movd %xmm1, %eax
; SSE41-32-NEXT: shrl $31, %eax ; SSE41-32-NEXT: shrl $31, %eax
; SSE41-32-NEXT: fildll {{[0-9]+}}(%esp) ; SSE41-32-NEXT: fildll {{[0-9]+}}(%esp)
; SSE41-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; SSE41-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; SSE41-32-NEXT: fstps (%esp) ; SSE41-32-NEXT: fstps (%esp)
; SSE41-32-NEXT: wait ; SSE41-32-NEXT: wait
; SSE41-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1] ; SSE41-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
; SSE41-32-NEXT: movd %xmm0, %eax ; SSE41-32-NEXT: movd %xmm0, %eax
; SSE41-32-NEXT: shrl $31, %eax ; SSE41-32-NEXT: shrl $31, %eax
; SSE41-32-NEXT: fildll {{[0-9]+}}(%esp) ; SSE41-32-NEXT: fildll {{[0-9]+}}(%esp)
; SSE41-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; SSE41-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; SSE41-32-NEXT: fstps {{[0-9]+}}(%esp) ; SSE41-32-NEXT: fstps {{[0-9]+}}(%esp)
; SSE41-32-NEXT: wait ; SSE41-32-NEXT: wait
; SSE41-32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; SSE41-32-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE41-32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; SSE41-32-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE41-32-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; SSE41-32-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
; SSE41-32-NEXT: movl %ebp, %esp ; SSE41-32-NEXT: movl %ebp, %esp
; SSE41-32-NEXT: popl %ebp ; SSE41-32-NEXT: popl %ebp
; SSE41-32-NEXT: .cfi_def_cfa %esp, 4 ; SSE41-32-NEXT: .cfi_def_cfa %esp, 4
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; AVX-32-NEXT: andl $-8, %esp ; AVX-32-NEXT: andl $-8, %esp
; AVX-32-NEXT: subl $24, %esp ; AVX-32-NEXT: subl $24, %esp
; AVX-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp) ; AVX-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)
; AVX-32-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,2,3] ; AVX-32-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,2,3]
; AVX-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp) ; AVX-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp)
; AVX-32-NEXT: vextractps $1, %xmm0, %eax ; AVX-32-NEXT: vextractps $1, %xmm0, %eax
; AVX-32-NEXT: shrl $31, %eax ; AVX-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp) ; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; AVX-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX-32-NEXT: fstps {{[0-9]+}}(%esp) ; AVX-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX-32-NEXT: wait ; AVX-32-NEXT: wait
; AVX-32-NEXT: vextractps $3, %xmm0, %eax ; AVX-32-NEXT: vextractps $3, %xmm0, %eax
; AVX-32-NEXT: shrl $31, %eax ; AVX-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp) ; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; AVX-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX-32-NEXT: fstps (%esp) ; AVX-32-NEXT: fstps (%esp)
; AVX-32-NEXT: wait ; AVX-32-NEXT: wait
; AVX-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; AVX-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] ; AVX-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]
; AVX-32-NEXT: movl %ebp, %esp ; AVX-32-NEXT: movl %ebp, %esp
; AVX-32-NEXT: popl %ebp ; AVX-32-NEXT: popl %ebp
; AVX-32-NEXT: .cfi_def_cfa %esp, 4 ; AVX-32-NEXT: .cfi_def_cfa %esp, 4
; AVX-32-NEXT: retl ; AVX-32-NEXT: retl
▲ Show 20 Lines • Show All 88 Lines • ▼ Show 20 Lines %result = call <4 x float> @llvm.experimental.constrained.sitofp.v4f32.v4i1(<4 x i1> %x,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <4 x float> %result ret <4 x float> %result
} }
define <4 x float> @uitofp_v4i1_v4f32(<4 x i1> %x) #0 { define <4 x float> @uitofp_v4i1_v4f32(<4 x i1> %x) #0 {
; SSE-32-LABEL: uitofp_v4i1_v4f32: ; SSE-32-LABEL: uitofp_v4i1_v4f32:
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: andps {{\.LCPI.*}}, %xmm0 ; SSE-32-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE-32-NEXT: cvtdq2ps %xmm0, %xmm0 ; SSE-32-NEXT: cvtdq2ps %xmm0, %xmm0
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: uitofp_v4i1_v4f32: ; SSE-64-LABEL: uitofp_v4i1_v4f32:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: andps {{.*}}(%rip), %xmm0 ; SSE-64-NEXT: andps {{.*}}(%rip), %xmm0
; SSE-64-NEXT: cvtdq2ps %xmm0, %xmm0 ; SSE-64-NEXT: cvtdq2ps %xmm0, %xmm0
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; SSE41-32-LABEL: uitofp_v4i1_v4f32: ; SSE41-32-LABEL: uitofp_v4i1_v4f32:
; SSE41-32: # %bb.0: ; SSE41-32: # %bb.0:
; SSE41-32-NEXT: andps {{\.LCPI.*}}, %xmm0 ; SSE41-32-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE41-32-NEXT: cvtdq2ps %xmm0, %xmm0 ; SSE41-32-NEXT: cvtdq2ps %xmm0, %xmm0
; SSE41-32-NEXT: retl ; SSE41-32-NEXT: retl
; ;
; SSE41-64-LABEL: uitofp_v4i1_v4f32: ; SSE41-64-LABEL: uitofp_v4i1_v4f32:
; SSE41-64: # %bb.0: ; SSE41-64: # %bb.0:
; SSE41-64-NEXT: andps {{.*}}(%rip), %xmm0 ; SSE41-64-NEXT: andps {{.*}}(%rip), %xmm0
; SSE41-64-NEXT: cvtdq2ps %xmm0, %xmm0 ; SSE41-64-NEXT: cvtdq2ps %xmm0, %xmm0
; SSE41-64-NEXT: retq ; SSE41-64-NEXT: retq
; ;
; AVX1-32-LABEL: uitofp_v4i1_v4f32: ; AVX1-32-LABEL: uitofp_v4i1_v4f32:
; AVX1-32: # %bb.0: ; AVX1-32: # %bb.0:
; AVX1-32-NEXT: vandps {{\.LCPI.*}}, %xmm0, %xmm0 ; AVX1-32-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX1-32-NEXT: vcvtdq2ps %xmm0, %xmm0 ; AVX1-32-NEXT: vcvtdq2ps %xmm0, %xmm0
; AVX1-32-NEXT: retl ; AVX1-32-NEXT: retl
; ;
; AVX1-64-LABEL: uitofp_v4i1_v4f32: ; AVX1-64-LABEL: uitofp_v4i1_v4f32:
; AVX1-64: # %bb.0: ; AVX1-64: # %bb.0:
; AVX1-64-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 ; AVX1-64-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
; AVX1-64-NEXT: vcvtdq2ps %xmm0, %xmm0 ; AVX1-64-NEXT: vcvtdq2ps %xmm0, %xmm0
; AVX1-64-NEXT: retq ; AVX1-64-NEXT: retq
; ;
; AVX512F-LABEL: uitofp_v4i1_v4f32: ; AVX512F-LABEL: uitofp_v4i1_v4f32:
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: vbroadcastss {{.*#+}} xmm1 = [1,1,1,1] ; AVX512F-NEXT: vbroadcastss {{.*#+}} xmm1 = [1,1,1,1]
; AVX512F-NEXT: vandps %xmm1, %xmm0, %xmm0 ; AVX512F-NEXT: vandps %xmm1, %xmm0, %xmm0
; AVX512F-NEXT: vcvtdq2ps %xmm0, %xmm0 ; AVX512F-NEXT: vcvtdq2ps %xmm0, %xmm0
; AVX512F-NEXT: ret{{[l|q]}} ; AVX512F-NEXT: ret{{[l|q]}}
; ;
; AVX512VL-32-LABEL: uitofp_v4i1_v4f32: ; AVX512VL-32-LABEL: uitofp_v4i1_v4f32:
; AVX512VL-32: # %bb.0: ; AVX512VL-32: # %bb.0:
; AVX512VL-32-NEXT: vpandd {{\.LCPI.*}}{1to4}, %xmm0, %xmm0 ; AVX512VL-32-NEXT: vpandd {{\.LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0
; AVX512VL-32-NEXT: vcvtdq2ps %xmm0, %xmm0 ; AVX512VL-32-NEXT: vcvtdq2ps %xmm0, %xmm0
; AVX512VL-32-NEXT: retl ; AVX512VL-32-NEXT: retl
; ;
; AVX512VL-64-LABEL: uitofp_v4i1_v4f32: ; AVX512VL-64-LABEL: uitofp_v4i1_v4f32:
; AVX512VL-64: # %bb.0: ; AVX512VL-64: # %bb.0:
; AVX512VL-64-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm0, %xmm0 ; AVX512VL-64-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm0, %xmm0
; AVX512VL-64-NEXT: vcvtdq2ps %xmm0, %xmm0 ; AVX512VL-64-NEXT: vcvtdq2ps %xmm0, %xmm0
; AVX512VL-64-NEXT: retq ; AVX512VL-64-NEXT: retq
; ;
; AVX512DQ-LABEL: uitofp_v4i1_v4f32: ; AVX512DQ-LABEL: uitofp_v4i1_v4f32:
; AVX512DQ: # %bb.0: ; AVX512DQ: # %bb.0:
; AVX512DQ-NEXT: vbroadcastss {{.*#+}} xmm1 = [1,1,1,1] ; AVX512DQ-NEXT: vbroadcastss {{.*#+}} xmm1 = [1,1,1,1]
; AVX512DQ-NEXT: vandps %xmm1, %xmm0, %xmm0 ; AVX512DQ-NEXT: vandps %xmm1, %xmm0, %xmm0
; AVX512DQ-NEXT: vcvtdq2ps %xmm0, %xmm0 ; AVX512DQ-NEXT: vcvtdq2ps %xmm0, %xmm0
; AVX512DQ-NEXT: ret{{[l|q]}} ; AVX512DQ-NEXT: ret{{[l|q]}}
; ;
; AVX512DQVL-32-LABEL: uitofp_v4i1_v4f32: ; AVX512DQVL-32-LABEL: uitofp_v4i1_v4f32:
; AVX512DQVL-32: # %bb.0: ; AVX512DQVL-32: # %bb.0:
; AVX512DQVL-32-NEXT: vandps {{\.LCPI.*}}{1to4}, %xmm0, %xmm0 ; AVX512DQVL-32-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0
; AVX512DQVL-32-NEXT: vcvtdq2ps %xmm0, %xmm0 ; AVX512DQVL-32-NEXT: vcvtdq2ps %xmm0, %xmm0
; AVX512DQVL-32-NEXT: retl ; AVX512DQVL-32-NEXT: retl
; ;
; AVX512DQVL-64-LABEL: uitofp_v4i1_v4f32: ; AVX512DQVL-64-LABEL: uitofp_v4i1_v4f32:
; AVX512DQVL-64: # %bb.0: ; AVX512DQVL-64: # %bb.0:
; AVX512DQVL-64-NEXT: vandps {{.*}}(%rip){1to4}, %xmm0, %xmm0 ; AVX512DQVL-64-NEXT: vandps {{.*}}(%rip){1to4}, %xmm0, %xmm0
; AVX512DQVL-64-NEXT: vcvtdq2ps %xmm0, %xmm0 ; AVX512DQVL-64-NEXT: vcvtdq2ps %xmm0, %xmm0
; AVX512DQVL-64-NEXT: retq ; AVX512DQVL-64-NEXT: retq
▲ Show 20 Lines • Show All 132 Lines • ▼ Show 20 Lines %result = call <4 x float> @llvm.experimental.constrained.sitofp.v4f32.v4i32(<4 x i32> %x,
ret <4 x float> %result ret <4 x float> %result
} }
define <4 x float> @uitofp_v4i32_v4f32(<4 x i32> %x) #0 { define <4 x float> @uitofp_v4i32_v4f32(<4 x i32> %x) #0 {
; SSE-32-LABEL: uitofp_v4i32_v4f32: ; SSE-32-LABEL: uitofp_v4i32_v4f32:
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535] ; SSE-32-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
; SSE-32-NEXT: pand %xmm0, %xmm1 ; SSE-32-NEXT: pand %xmm0, %xmm1
; SSE-32-NEXT: por {{\.LCPI.*}}, %xmm1 ; SSE-32-NEXT: por {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; SSE-32-NEXT: psrld $16, %xmm0 ; SSE-32-NEXT: psrld $16, %xmm0
; SSE-32-NEXT: por {{\.LCPI.*}}, %xmm0 ; SSE-32-NEXT: por {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE-32-NEXT: subps {{\.LCPI.*}}, %xmm0 ; SSE-32-NEXT: subps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE-32-NEXT: addps %xmm1, %xmm0 ; SSE-32-NEXT: addps %xmm1, %xmm0
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: uitofp_v4i32_v4f32: ; SSE-64-LABEL: uitofp_v4i32_v4f32:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535] ; SSE-64-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
; SSE-64-NEXT: pand %xmm0, %xmm1 ; SSE-64-NEXT: pand %xmm0, %xmm1
; SSE-64-NEXT: por {{.*}}(%rip), %xmm1 ; SSE-64-NEXT: por {{.*}}(%rip), %xmm1
; SSE-64-NEXT: psrld $16, %xmm0 ; SSE-64-NEXT: psrld $16, %xmm0
; SSE-64-NEXT: por {{.*}}(%rip), %xmm0 ; SSE-64-NEXT: por {{.*}}(%rip), %xmm0
; SSE-64-NEXT: subps {{.*}}(%rip), %xmm0 ; SSE-64-NEXT: subps {{.*}}(%rip), %xmm0
; SSE-64-NEXT: addps %xmm1, %xmm0 ; SSE-64-NEXT: addps %xmm1, %xmm0
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; SSE41-32-LABEL: uitofp_v4i32_v4f32: ; SSE41-32-LABEL: uitofp_v4i32_v4f32:
; SSE41-32: # %bb.0: ; SSE41-32: # %bb.0:
; SSE41-32-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535] ; SSE41-32-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
; SSE41-32-NEXT: pand %xmm0, %xmm1 ; SSE41-32-NEXT: pand %xmm0, %xmm1
; SSE41-32-NEXT: por {{\.LCPI.*}}, %xmm1 ; SSE41-32-NEXT: por {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; SSE41-32-NEXT: psrld $16, %xmm0 ; SSE41-32-NEXT: psrld $16, %xmm0
; SSE41-32-NEXT: por {{\.LCPI.*}}, %xmm0 ; SSE41-32-NEXT: por {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE41-32-NEXT: subps {{\.LCPI.*}}, %xmm0 ; SSE41-32-NEXT: subps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE41-32-NEXT: addps %xmm1, %xmm0 ; SSE41-32-NEXT: addps %xmm1, %xmm0
; SSE41-32-NEXT: retl ; SSE41-32-NEXT: retl
; ;
; SSE41-64-LABEL: uitofp_v4i32_v4f32: ; SSE41-64-LABEL: uitofp_v4i32_v4f32:
; SSE41-64: # %bb.0: ; SSE41-64: # %bb.0:
; SSE41-64-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535] ; SSE41-64-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535]
; SSE41-64-NEXT: pand %xmm0, %xmm1 ; SSE41-64-NEXT: pand %xmm0, %xmm1
; SSE41-64-NEXT: por {{.*}}(%rip), %xmm1 ; SSE41-64-NEXT: por {{.*}}(%rip), %xmm1
; SSE41-64-NEXT: psrld $16, %xmm0 ; SSE41-64-NEXT: psrld $16, %xmm0
; SSE41-64-NEXT: por {{.*}}(%rip), %xmm0 ; SSE41-64-NEXT: por {{.*}}(%rip), %xmm0
; SSE41-64-NEXT: subps {{.*}}(%rip), %xmm0 ; SSE41-64-NEXT: subps {{.*}}(%rip), %xmm0
; SSE41-64-NEXT: addps %xmm1, %xmm0 ; SSE41-64-NEXT: addps %xmm1, %xmm0
; SSE41-64-NEXT: retq ; SSE41-64-NEXT: retq
; ;
; AVX1-32-LABEL: uitofp_v4i32_v4f32: ; AVX1-32-LABEL: uitofp_v4i32_v4f32:
; AVX1-32: # %bb.0: ; AVX1-32: # %bb.0:
; AVX1-32-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7] ; AVX1-32-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
; AVX1-32-NEXT: vpsrld $16, %xmm0, %xmm0 ; AVX1-32-NEXT: vpsrld $16, %xmm0, %xmm0
; AVX1-32-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7] ; AVX1-32-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
; AVX1-32-NEXT: vsubps {{\.LCPI.*}}, %xmm0, %xmm0 ; AVX1-32-NEXT: vsubps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX1-32-NEXT: vaddps %xmm0, %xmm1, %xmm0 ; AVX1-32-NEXT: vaddps %xmm0, %xmm1, %xmm0
; AVX1-32-NEXT: retl ; AVX1-32-NEXT: retl
; ;
; AVX1-64-LABEL: uitofp_v4i32_v4f32: ; AVX1-64-LABEL: uitofp_v4i32_v4f32:
; AVX1-64: # %bb.0: ; AVX1-64: # %bb.0:
; AVX1-64-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7] ; AVX1-64-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
; AVX1-64-NEXT: vpsrld $16, %xmm0, %xmm0 ; AVX1-64-NEXT: vpsrld $16, %xmm0, %xmm0
; AVX1-64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7] ; AVX1-64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1],xmm0[2],mem[3],xmm0[4],mem[5],xmm0[6],mem[7]
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines %result = call <2 x double> @llvm.experimental.constrained.sitofp.v2f64.v2i1(<2 x i1> %x,
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <2 x double> %result ret <2 x double> %result
} }
define <2 x double> @uitofp_v2i1_v2f64(<2 x i1> %x) #0 { define <2 x double> @uitofp_v2i1_v2f64(<2 x i1> %x) #0 {
; SSE-32-LABEL: uitofp_v2i1_v2f64: ; SSE-32-LABEL: uitofp_v2i1_v2f64:
; SSE-32: # %bb.0: ; SSE-32: # %bb.0:
; SSE-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; SSE-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; SSE-32-NEXT: pand {{\.LCPI.*}}, %xmm0 ; SSE-32-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE-32-NEXT: cvtdq2pd %xmm0, %xmm0 ; SSE-32-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
; ;
; SSE-64-LABEL: uitofp_v2i1_v2f64: ; SSE-64-LABEL: uitofp_v2i1_v2f64:
; SSE-64: # %bb.0: ; SSE-64: # %bb.0:
; SSE-64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; SSE-64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; SSE-64-NEXT: pand {{.*}}(%rip), %xmm0 ; SSE-64-NEXT: pand {{.*}}(%rip), %xmm0
; SSE-64-NEXT: cvtdq2pd %xmm0, %xmm0 ; SSE-64-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE-64-NEXT: retq ; SSE-64-NEXT: retq
; ;
; SSE41-32-LABEL: uitofp_v2i1_v2f64: ; SSE41-32-LABEL: uitofp_v2i1_v2f64:
; SSE41-32: # %bb.0: ; SSE41-32: # %bb.0:
; SSE41-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; SSE41-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; SSE41-32-NEXT: pand {{\.LCPI.*}}, %xmm0 ; SSE41-32-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE41-32-NEXT: cvtdq2pd %xmm0, %xmm0 ; SSE41-32-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE41-32-NEXT: retl ; SSE41-32-NEXT: retl
; ;
; SSE41-64-LABEL: uitofp_v2i1_v2f64: ; SSE41-64-LABEL: uitofp_v2i1_v2f64:
; SSE41-64: # %bb.0: ; SSE41-64: # %bb.0:
; SSE41-64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; SSE41-64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; SSE41-64-NEXT: pand {{.*}}(%rip), %xmm0 ; SSE41-64-NEXT: pand {{.*}}(%rip), %xmm0
; SSE41-64-NEXT: cvtdq2pd %xmm0, %xmm0 ; SSE41-64-NEXT: cvtdq2pd %xmm0, %xmm0
; SSE41-64-NEXT: retq ; SSE41-64-NEXT: retq
; ;
; AVX1-32-LABEL: uitofp_v2i1_v2f64: ; AVX1-32-LABEL: uitofp_v2i1_v2f64:
; AVX1-32: # %bb.0: ; AVX1-32: # %bb.0:
; AVX1-32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,2,3] ; AVX1-32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,2,3]
; AVX1-32-NEXT: vandps {{\.LCPI.*}}, %xmm0, %xmm0 ; AVX1-32-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX1-32-NEXT: vcvtdq2pd %xmm0, %xmm0 ; AVX1-32-NEXT: vcvtdq2pd %xmm0, %xmm0
; AVX1-32-NEXT: retl ; AVX1-32-NEXT: retl
; ;
; AVX1-64-LABEL: uitofp_v2i1_v2f64: ; AVX1-64-LABEL: uitofp_v2i1_v2f64:
; AVX1-64: # %bb.0: ; AVX1-64: # %bb.0:
; AVX1-64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,2,3] ; AVX1-64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,2,3]
; AVX1-64-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 ; AVX1-64-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
; AVX1-64-NEXT: vcvtdq2pd %xmm0, %xmm0 ; AVX1-64-NEXT: vcvtdq2pd %xmm0, %xmm0
; AVX1-64-NEXT: retq ; AVX1-64-NEXT: retq
; ;
; AVX512F-LABEL: uitofp_v2i1_v2f64: ; AVX512F-LABEL: uitofp_v2i1_v2f64:
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,2,3] ; AVX512F-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,2,3]
; AVX512F-NEXT: vbroadcastss {{.*#+}} xmm1 = [1,1,1,1] ; AVX512F-NEXT: vbroadcastss {{.*#+}} xmm1 = [1,1,1,1]
; AVX512F-NEXT: vandps %xmm1, %xmm0, %xmm0 ; AVX512F-NEXT: vandps %xmm1, %xmm0, %xmm0
; AVX512F-NEXT: vcvtdq2pd %xmm0, %xmm0 ; AVX512F-NEXT: vcvtdq2pd %xmm0, %xmm0
; AVX512F-NEXT: ret{{[l|q]}} ; AVX512F-NEXT: ret{{[l|q]}}
; ;
; AVX512VL-32-LABEL: uitofp_v2i1_v2f64: ; AVX512VL-32-LABEL: uitofp_v2i1_v2f64:
; AVX512VL-32: # %bb.0: ; AVX512VL-32: # %bb.0:
; AVX512VL-32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; AVX512VL-32-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; AVX512VL-32-NEXT: vpandd {{\.LCPI.*}}{1to4}, %xmm0, %xmm0 ; AVX512VL-32-NEXT: vpandd {{\.LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0
; AVX512VL-32-NEXT: vcvtdq2pd %xmm0, %xmm0 ; AVX512VL-32-NEXT: vcvtdq2pd %xmm0, %xmm0
; AVX512VL-32-NEXT: retl ; AVX512VL-32-NEXT: retl
; ;
; AVX512VL-64-LABEL: uitofp_v2i1_v2f64: ; AVX512VL-64-LABEL: uitofp_v2i1_v2f64:
; AVX512VL-64: # %bb.0: ; AVX512VL-64: # %bb.0:
; AVX512VL-64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; AVX512VL-64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; AVX512VL-64-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm0, %xmm0 ; AVX512VL-64-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm0, %xmm0
; AVX512VL-64-NEXT: vcvtdq2pd %xmm0, %xmm0 ; AVX512VL-64-NEXT: vcvtdq2pd %xmm0, %xmm0
; AVX512VL-64-NEXT: retq ; AVX512VL-64-NEXT: retq
; ;
; AVX512DQ-LABEL: uitofp_v2i1_v2f64: ; AVX512DQ-LABEL: uitofp_v2i1_v2f64:
; AVX512DQ: # %bb.0: ; AVX512DQ: # %bb.0:
; AVX512DQ-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,2,3] ; AVX512DQ-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,2,3]
; AVX512DQ-NEXT: vbroadcastss {{.*#+}} xmm1 = [1,1,1,1] ; AVX512DQ-NEXT: vbroadcastss {{.*#+}} xmm1 = [1,1,1,1]
; AVX512DQ-NEXT: vandps %xmm1, %xmm0, %xmm0 ; AVX512DQ-NEXT: vandps %xmm1, %xmm0, %xmm0
; AVX512DQ-NEXT: vcvtdq2pd %xmm0, %xmm0 ; AVX512DQ-NEXT: vcvtdq2pd %xmm0, %xmm0
; AVX512DQ-NEXT: ret{{[l|q]}} ; AVX512DQ-NEXT: ret{{[l|q]}}
; ;
; AVX512DQVL-32-LABEL: uitofp_v2i1_v2f64: ; AVX512DQVL-32-LABEL: uitofp_v2i1_v2f64:
; AVX512DQVL-32: # %bb.0: ; AVX512DQVL-32: # %bb.0:
; AVX512DQVL-32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,2,3] ; AVX512DQVL-32-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,2,3]
; AVX512DQVL-32-NEXT: vandps {{\.LCPI.*}}{1to4}, %xmm0, %xmm0 ; AVX512DQVL-32-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0
; AVX512DQVL-32-NEXT: vcvtdq2pd %xmm0, %xmm0 ; AVX512DQVL-32-NEXT: vcvtdq2pd %xmm0, %xmm0
; AVX512DQVL-32-NEXT: retl ; AVX512DQVL-32-NEXT: retl
; ;
; AVX512DQVL-64-LABEL: uitofp_v2i1_v2f64: ; AVX512DQVL-64-LABEL: uitofp_v2i1_v2f64:
; AVX512DQVL-64: # %bb.0: ; AVX512DQVL-64: # %bb.0:
; AVX512DQVL-64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,2,3] ; AVX512DQVL-64-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[0,2,2,3]
; AVX512DQVL-64-NEXT: vandps {{.*}}(%rip){1to4}, %xmm0, %xmm0 ; AVX512DQVL-64-NEXT: vandps {{.*}}(%rip){1to4}, %xmm0, %xmm0
; AVX512DQVL-64-NEXT: vcvtdq2pd %xmm0, %xmm0 ; AVX512DQVL-64-NEXT: vcvtdq2pd %xmm0, %xmm0
▲ Show 20 Lines • Show All 327 Lines • ▼ Show 20 Lines
; SSE-32-NEXT: subl $32, %esp ; SSE-32-NEXT: subl $32, %esp
; SSE-32-NEXT: movq %xmm0, {{[0-9]+}}(%esp) ; SSE-32-NEXT: movq %xmm0, {{[0-9]+}}(%esp)
; SSE-32-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3] ; SSE-32-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; SSE-32-NEXT: movq %xmm1, {{[0-9]+}}(%esp) ; SSE-32-NEXT: movq %xmm1, {{[0-9]+}}(%esp)
; SSE-32-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1] ; SSE-32-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
; SSE-32-NEXT: movd %xmm1, %eax ; SSE-32-NEXT: movd %xmm1, %eax
; SSE-32-NEXT: shrl $31, %eax ; SSE-32-NEXT: shrl $31, %eax
; SSE-32-NEXT: fildll {{[0-9]+}}(%esp) ; SSE-32-NEXT: fildll {{[0-9]+}}(%esp)
; SSE-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; SSE-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; SSE-32-NEXT: fstpl {{[0-9]+}}(%esp) ; SSE-32-NEXT: fstpl {{[0-9]+}}(%esp)
; SSE-32-NEXT: wait ; SSE-32-NEXT: wait
; SSE-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE-32-NEXT: movd %xmm0, %eax ; SSE-32-NEXT: movd %xmm0, %eax
; SSE-32-NEXT: shrl $31, %eax ; SSE-32-NEXT: shrl $31, %eax
; SSE-32-NEXT: fildll {{[0-9]+}}(%esp) ; SSE-32-NEXT: fildll {{[0-9]+}}(%esp)
; SSE-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; SSE-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; SSE-32-NEXT: fstpl (%esp) ; SSE-32-NEXT: fstpl (%esp)
; SSE-32-NEXT: wait ; SSE-32-NEXT: wait
; SSE-32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE-32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; SSE-32-NEXT: movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1] ; SSE-32-NEXT: movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]
; SSE-32-NEXT: movl %ebp, %esp ; SSE-32-NEXT: movl %ebp, %esp
; SSE-32-NEXT: popl %ebp ; SSE-32-NEXT: popl %ebp
; SSE-32-NEXT: .cfi_def_cfa %esp, 4 ; SSE-32-NEXT: .cfi_def_cfa %esp, 4
; SSE-32-NEXT: retl ; SSE-32-NEXT: retl
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; SSE41-32-NEXT: subl $32, %esp ; SSE41-32-NEXT: subl $32, %esp
; SSE41-32-NEXT: movq %xmm0, {{[0-9]+}}(%esp) ; SSE41-32-NEXT: movq %xmm0, {{[0-9]+}}(%esp)
; SSE41-32-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3] ; SSE41-32-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
; SSE41-32-NEXT: movq %xmm1, {{[0-9]+}}(%esp) ; SSE41-32-NEXT: movq %xmm1, {{[0-9]+}}(%esp)
; SSE41-32-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1] ; SSE41-32-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
; SSE41-32-NEXT: movd %xmm1, %eax ; SSE41-32-NEXT: movd %xmm1, %eax
; SSE41-32-NEXT: shrl $31, %eax ; SSE41-32-NEXT: shrl $31, %eax
; SSE41-32-NEXT: fildll {{[0-9]+}}(%esp) ; SSE41-32-NEXT: fildll {{[0-9]+}}(%esp)
; SSE41-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; SSE41-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; SSE41-32-NEXT: fstpl {{[0-9]+}}(%esp) ; SSE41-32-NEXT: fstpl {{[0-9]+}}(%esp)
; SSE41-32-NEXT: wait ; SSE41-32-NEXT: wait
; SSE41-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3] ; SSE41-32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,3,3,3]
; SSE41-32-NEXT: movd %xmm0, %eax ; SSE41-32-NEXT: movd %xmm0, %eax
; SSE41-32-NEXT: shrl $31, %eax ; SSE41-32-NEXT: shrl $31, %eax
; SSE41-32-NEXT: fildll {{[0-9]+}}(%esp) ; SSE41-32-NEXT: fildll {{[0-9]+}}(%esp)
; SSE41-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; SSE41-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; SSE41-32-NEXT: fstpl (%esp) ; SSE41-32-NEXT: fstpl (%esp)
; SSE41-32-NEXT: wait ; SSE41-32-NEXT: wait
; SSE41-32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; SSE41-32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; SSE41-32-NEXT: movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1] ; SSE41-32-NEXT: movhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]
; SSE41-32-NEXT: movl %ebp, %esp ; SSE41-32-NEXT: movl %ebp, %esp
; SSE41-32-NEXT: popl %ebp ; SSE41-32-NEXT: popl %ebp
; SSE41-32-NEXT: .cfi_def_cfa %esp, 4 ; SSE41-32-NEXT: .cfi_def_cfa %esp, 4
; SSE41-32-NEXT: retl ; SSE41-32-NEXT: retl
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; AVX-32-NEXT: andl $-8, %esp ; AVX-32-NEXT: andl $-8, %esp
; AVX-32-NEXT: subl $32, %esp ; AVX-32-NEXT: subl $32, %esp
; AVX-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp) ; AVX-32-NEXT: vmovlps %xmm0, {{[0-9]+}}(%esp)
; AVX-32-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,2,3] ; AVX-32-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,2,3]
; AVX-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp) ; AVX-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp)
; AVX-32-NEXT: vextractps $1, %xmm0, %eax ; AVX-32-NEXT: vextractps $1, %xmm0, %eax
; AVX-32-NEXT: shrl $31, %eax ; AVX-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp) ; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; AVX-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX-32-NEXT: fstpl {{[0-9]+}}(%esp) ; AVX-32-NEXT: fstpl {{[0-9]+}}(%esp)
; AVX-32-NEXT: wait ; AVX-32-NEXT: wait
; AVX-32-NEXT: vextractps $3, %xmm0, %eax ; AVX-32-NEXT: vextractps $3, %xmm0, %eax
; AVX-32-NEXT: shrl $31, %eax ; AVX-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp) ; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; AVX-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX-32-NEXT: fstpl (%esp) ; AVX-32-NEXT: fstpl (%esp)
; AVX-32-NEXT: wait ; AVX-32-NEXT: wait
; AVX-32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; AVX-32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX-32-NEXT: vmovhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1] ; AVX-32-NEXT: vmovhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]
; AVX-32-NEXT: movl %ebp, %esp ; AVX-32-NEXT: movl %ebp, %esp
; AVX-32-NEXT: popl %ebp ; AVX-32-NEXT: popl %ebp
; AVX-32-NEXT: .cfi_def_cfa %esp, 4 ; AVX-32-NEXT: .cfi_def_cfa %esp, 4
; AVX-32-NEXT: retl ; AVX-32-NEXT: retl
▲ Show 20 Lines • Show All 69 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vec-strict-inttofp-256.ll

Show First 20 Lines • Show All 88 Lines • ▼ Show 20 Lines %result = call <8 x float> @llvm.experimental.constrained.sitofp.v8f32.v8i1(<8 x i1> %x,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <8 x float> %result ret <8 x float> %result
} }
define <8 x float> @uitofp_v8i1_v8f32(<8 x i1> %x) #0 { define <8 x float> @uitofp_v8i1_v8f32(<8 x i1> %x) #0 {
; AVX1-32-LABEL: uitofp_v8i1_v8f32: ; AVX1-32-LABEL: uitofp_v8i1_v8f32:
; AVX1-32: # %bb.0: ; AVX1-32: # %bb.0:
; AVX1-32-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; AVX1-32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX1-32-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX1-32-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-32-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] ; AVX1-32-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; AVX1-32-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero ; AVX1-32-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; AVX1-32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-32-NEXT: vcvtdq2ps %ymm0, %ymm0 ; AVX1-32-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX1-32-NEXT: retl ; AVX1-32-NEXT: retl
; ;
; AVX1-64-LABEL: uitofp_v8i1_v8f32: ; AVX1-64-LABEL: uitofp_v8i1_v8f32:
; AVX1-64: # %bb.0: ; AVX1-64: # %bb.0:
; AVX1-64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; AVX1-64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; AVX1-64-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX1-64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-64-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] ; AVX1-64-NEXT: vpunpckhwd {{.*#+}} xmm1 = xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; AVX1-64-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero ; AVX1-64-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
; AVX1-64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-64-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-64-NEXT: vcvtdq2ps %ymm0, %ymm0 ; AVX1-64-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX1-64-NEXT: retq ; AVX1-64-NEXT: retq
; ;
; AVX2-32-LABEL: uitofp_v8i1_v8f32: ; AVX2-32-LABEL: uitofp_v8i1_v8f32:
; AVX2-32: # %bb.0: ; AVX2-32: # %bb.0:
; AVX2-32-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; AVX2-32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX2-32-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; AVX2-32-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX2-32-NEXT: vcvtdq2ps %ymm0, %ymm0 ; AVX2-32-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX2-32-NEXT: retl ; AVX2-32-NEXT: retl
; ;
; AVX2-64-LABEL: uitofp_v8i1_v8f32: ; AVX2-64-LABEL: uitofp_v8i1_v8f32:
; AVX2-64: # %bb.0: ; AVX2-64: # %bb.0:
; AVX2-64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; AVX2-64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; AVX2-64-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; AVX2-64-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX2-64-NEXT: vcvtdq2ps %ymm0, %ymm0 ; AVX2-64-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX2-64-NEXT: retq ; AVX2-64-NEXT: retq
; ;
; AVX512F-32-LABEL: uitofp_v8i1_v8f32: ; AVX512F-32-LABEL: uitofp_v8i1_v8f32:
; AVX512F-32: # %bb.0: ; AVX512F-32: # %bb.0:
; AVX512F-32-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; AVX512F-32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX512F-32-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; AVX512F-32-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512F-32-NEXT: vcvtdq2ps %ymm0, %ymm0 ; AVX512F-32-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX512F-32-NEXT: retl ; AVX512F-32-NEXT: retl
; ;
; AVX512F-64-LABEL: uitofp_v8i1_v8f32: ; AVX512F-64-LABEL: uitofp_v8i1_v8f32:
; AVX512F-64: # %bb.0: ; AVX512F-64: # %bb.0:
; AVX512F-64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; AVX512F-64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; AVX512F-64-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; AVX512F-64-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512F-64-NEXT: vcvtdq2ps %ymm0, %ymm0 ; AVX512F-64-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX512F-64-NEXT: retq ; AVX512F-64-NEXT: retq
; ;
; AVX512VL-32-LABEL: uitofp_v8i1_v8f32: ; AVX512VL-32-LABEL: uitofp_v8i1_v8f32:
; AVX512VL-32: # %bb.0: ; AVX512VL-32: # %bb.0:
; AVX512VL-32-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; AVX512VL-32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX512VL-32-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; AVX512VL-32-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VL-32-NEXT: vcvtdq2ps %ymm0, %ymm0 ; AVX512VL-32-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX512VL-32-NEXT: retl ; AVX512VL-32-NEXT: retl
; ;
; AVX512VL-64-LABEL: uitofp_v8i1_v8f32: ; AVX512VL-64-LABEL: uitofp_v8i1_v8f32:
; AVX512VL-64: # %bb.0: ; AVX512VL-64: # %bb.0:
; AVX512VL-64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; AVX512VL-64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; AVX512VL-64-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; AVX512VL-64-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512VL-64-NEXT: vcvtdq2ps %ymm0, %ymm0 ; AVX512VL-64-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX512VL-64-NEXT: retq ; AVX512VL-64-NEXT: retq
; ;
; AVX512DQ-32-LABEL: uitofp_v8i1_v8f32: ; AVX512DQ-32-LABEL: uitofp_v8i1_v8f32:
; AVX512DQ-32: # %bb.0: ; AVX512DQ-32: # %bb.0:
; AVX512DQ-32-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; AVX512DQ-32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX512DQ-32-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; AVX512DQ-32-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512DQ-32-NEXT: vcvtdq2ps %ymm0, %ymm0 ; AVX512DQ-32-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX512DQ-32-NEXT: retl ; AVX512DQ-32-NEXT: retl
; ;
; AVX512DQ-64-LABEL: uitofp_v8i1_v8f32: ; AVX512DQ-64-LABEL: uitofp_v8i1_v8f32:
; AVX512DQ-64: # %bb.0: ; AVX512DQ-64: # %bb.0:
; AVX512DQ-64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; AVX512DQ-64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; AVX512DQ-64-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; AVX512DQ-64-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512DQ-64-NEXT: vcvtdq2ps %ymm0, %ymm0 ; AVX512DQ-64-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX512DQ-64-NEXT: retq ; AVX512DQ-64-NEXT: retq
; ;
; AVX512DQVL-32-LABEL: uitofp_v8i1_v8f32: ; AVX512DQVL-32-LABEL: uitofp_v8i1_v8f32:
; AVX512DQVL-32: # %bb.0: ; AVX512DQVL-32: # %bb.0:
; AVX512DQVL-32-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; AVX512DQVL-32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX512DQVL-32-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; AVX512DQVL-32-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; AVX512DQVL-32-NEXT: vcvtdq2ps %ymm0, %ymm0 ; AVX512DQVL-32-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX512DQVL-32-NEXT: retl ; AVX512DQVL-32-NEXT: retl
; ;
; AVX512DQVL-64-LABEL: uitofp_v8i1_v8f32: ; AVX512DQVL-64-LABEL: uitofp_v8i1_v8f32:
; AVX512DQVL-64: # %bb.0: ; AVX512DQVL-64: # %bb.0:
; AVX512DQVL-64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; AVX512DQVL-64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; AVX512DQVL-64-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; AVX512DQVL-64-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
▲ Show 20 Lines • Show All 199 Lines • ▼ Show 20 Lines
define <8 x float> @uitofp_v8i32_v8f32(<8 x i32> %x) #0 { define <8 x float> @uitofp_v8i32_v8f32(<8 x i32> %x) #0 {
; AVX1-32-LABEL: uitofp_v8i32_v8f32: ; AVX1-32-LABEL: uitofp_v8i32_v8f32:
; AVX1-32: # %bb.0: ; AVX1-32: # %bb.0:
; AVX1-32-NEXT: vpsrld $16, %xmm0, %xmm1 ; AVX1-32-NEXT: vpsrld $16, %xmm0, %xmm1
; AVX1-32-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-32-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-32-NEXT: vpsrld $16, %xmm2, %xmm2 ; AVX1-32-NEXT: vpsrld $16, %xmm2, %xmm2
; AVX1-32-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1 ; AVX1-32-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
; AVX1-32-NEXT: vcvtdq2ps %ymm1, %ymm1 ; AVX1-32-NEXT: vcvtdq2ps %ymm1, %ymm1
; AVX1-32-NEXT: vmulps {{\.LCPI.*}}, %ymm1, %ymm1 ; AVX1-32-NEXT: vmulps {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm1
; AVX1-32-NEXT: vandps {{\.LCPI.*}}, %ymm0, %ymm0 ; AVX1-32-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; AVX1-32-NEXT: vcvtdq2ps %ymm0, %ymm0 ; AVX1-32-NEXT: vcvtdq2ps %ymm0, %ymm0
; AVX1-32-NEXT: vaddps %ymm0, %ymm1, %ymm0 ; AVX1-32-NEXT: vaddps %ymm0, %ymm1, %ymm0
; AVX1-32-NEXT: retl ; AVX1-32-NEXT: retl
; ;
; AVX1-64-LABEL: uitofp_v8i32_v8f32: ; AVX1-64-LABEL: uitofp_v8i32_v8f32:
; AVX1-64: # %bb.0: ; AVX1-64: # %bb.0:
; AVX1-64-NEXT: vpsrld $16, %xmm0, %xmm1 ; AVX1-64-NEXT: vpsrld $16, %xmm0, %xmm1
; AVX1-64-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-64-NEXT: vextractf128 $1, %ymm0, %xmm2
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines %result = call <4 x double> @llvm.experimental.constrained.sitofp.v4f64.v4i1(<4 x i1> %x,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <4 x double> %result ret <4 x double> %result
} }
define <4 x double> @uitofp_v4i1_v4f64(<4 x i1> %x) #0 { define <4 x double> @uitofp_v4i1_v4f64(<4 x i1> %x) #0 {
; AVX1-32-LABEL: uitofp_v4i1_v4f64: ; AVX1-32-LABEL: uitofp_v4i1_v4f64:
; AVX1-32: # %bb.0: ; AVX1-32: # %bb.0:
; AVX1-32-NEXT: vandps {{\.LCPI.*}}, %xmm0, %xmm0 ; AVX1-32-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX1-32-NEXT: vcvtdq2pd %xmm0, %ymm0 ; AVX1-32-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX1-32-NEXT: retl ; AVX1-32-NEXT: retl
; ;
; AVX1-64-LABEL: uitofp_v4i1_v4f64: ; AVX1-64-LABEL: uitofp_v4i1_v4f64:
; AVX1-64: # %bb.0: ; AVX1-64: # %bb.0:
; AVX1-64-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 ; AVX1-64-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
; AVX1-64-NEXT: vcvtdq2pd %xmm0, %ymm0 ; AVX1-64-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX1-64-NEXT: retq ; AVX1-64-NEXT: retq
Show All 9 Lines
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: vbroadcastss {{.*#+}} xmm1 = [1,1,1,1] ; AVX512F-NEXT: vbroadcastss {{.*#+}} xmm1 = [1,1,1,1]
; AVX512F-NEXT: vandps %xmm1, %xmm0, %xmm0 ; AVX512F-NEXT: vandps %xmm1, %xmm0, %xmm0
; AVX512F-NEXT: vcvtdq2pd %xmm0, %ymm0 ; AVX512F-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX512F-NEXT: ret{{[l|q]}} ; AVX512F-NEXT: ret{{[l|q]}}
; ;
; AVX512VL-32-LABEL: uitofp_v4i1_v4f64: ; AVX512VL-32-LABEL: uitofp_v4i1_v4f64:
; AVX512VL-32: # %bb.0: ; AVX512VL-32: # %bb.0:
; AVX512VL-32-NEXT: vpandd {{\.LCPI.*}}{1to4}, %xmm0, %xmm0 ; AVX512VL-32-NEXT: vpandd {{\.LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0
; AVX512VL-32-NEXT: vcvtdq2pd %xmm0, %ymm0 ; AVX512VL-32-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX512VL-32-NEXT: retl ; AVX512VL-32-NEXT: retl
; ;
; AVX512VL-64-LABEL: uitofp_v4i1_v4f64: ; AVX512VL-64-LABEL: uitofp_v4i1_v4f64:
; AVX512VL-64: # %bb.0: ; AVX512VL-64: # %bb.0:
; AVX512VL-64-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm0, %xmm0 ; AVX512VL-64-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm0, %xmm0
; AVX512VL-64-NEXT: vcvtdq2pd %xmm0, %ymm0 ; AVX512VL-64-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX512VL-64-NEXT: retq ; AVX512VL-64-NEXT: retq
; ;
; AVX512DQ-LABEL: uitofp_v4i1_v4f64: ; AVX512DQ-LABEL: uitofp_v4i1_v4f64:
; AVX512DQ: # %bb.0: ; AVX512DQ: # %bb.0:
; AVX512DQ-NEXT: vbroadcastss {{.*#+}} xmm1 = [1,1,1,1] ; AVX512DQ-NEXT: vbroadcastss {{.*#+}} xmm1 = [1,1,1,1]
; AVX512DQ-NEXT: vandps %xmm1, %xmm0, %xmm0 ; AVX512DQ-NEXT: vandps %xmm1, %xmm0, %xmm0
; AVX512DQ-NEXT: vcvtdq2pd %xmm0, %ymm0 ; AVX512DQ-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX512DQ-NEXT: ret{{[l|q]}} ; AVX512DQ-NEXT: ret{{[l|q]}}
; ;
; AVX512DQVL-32-LABEL: uitofp_v4i1_v4f64: ; AVX512DQVL-32-LABEL: uitofp_v4i1_v4f64:
; AVX512DQVL-32: # %bb.0: ; AVX512DQVL-32: # %bb.0:
; AVX512DQVL-32-NEXT: vandps {{\.LCPI.*}}{1to4}, %xmm0, %xmm0 ; AVX512DQVL-32-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0
; AVX512DQVL-32-NEXT: vcvtdq2pd %xmm0, %ymm0 ; AVX512DQVL-32-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX512DQVL-32-NEXT: retl ; AVX512DQVL-32-NEXT: retl
; ;
; AVX512DQVL-64-LABEL: uitofp_v4i1_v4f64: ; AVX512DQVL-64-LABEL: uitofp_v4i1_v4f64:
; AVX512DQVL-64: # %bb.0: ; AVX512DQVL-64: # %bb.0:
; AVX512DQVL-64-NEXT: vandps {{.*}}(%rip){1to4}, %xmm0, %xmm0 ; AVX512DQVL-64-NEXT: vandps {{.*}}(%rip){1to4}, %xmm0, %xmm0
; AVX512DQVL-64-NEXT: vcvtdq2pd %xmm0, %ymm0 ; AVX512DQVL-64-NEXT: vcvtdq2pd %xmm0, %ymm0
; AVX512DQVL-64-NEXT: retq ; AVX512DQVL-64-NEXT: retq
▲ Show 20 Lines • Show All 243 Lines • ▼ Show 20 Lines
; AVX-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp) ; AVX-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp)
; AVX-32-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX-32-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp) ; AVX-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp)
; AVX-32-NEXT: vpermilps {{.*#+}} xmm2 = xmm1[2,3,2,3] ; AVX-32-NEXT: vpermilps {{.*#+}} xmm2 = xmm1[2,3,2,3]
; AVX-32-NEXT: vmovlps %xmm2, {{[0-9]+}}(%esp) ; AVX-32-NEXT: vmovlps %xmm2, {{[0-9]+}}(%esp)
; AVX-32-NEXT: vextractps $1, %xmm0, %eax ; AVX-32-NEXT: vextractps $1, %xmm0, %eax
; AVX-32-NEXT: shrl $31, %eax ; AVX-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp) ; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; AVX-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX-32-NEXT: fstpl (%esp) ; AVX-32-NEXT: fstpl (%esp)
; AVX-32-NEXT: wait ; AVX-32-NEXT: wait
; AVX-32-NEXT: vextractps $3, %xmm0, %eax ; AVX-32-NEXT: vextractps $3, %xmm0, %eax
; AVX-32-NEXT: shrl $31, %eax ; AVX-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp) ; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; AVX-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX-32-NEXT: fstpl {{[0-9]+}}(%esp) ; AVX-32-NEXT: fstpl {{[0-9]+}}(%esp)
; AVX-32-NEXT: wait ; AVX-32-NEXT: wait
; AVX-32-NEXT: vextractps $1, %xmm1, %eax ; AVX-32-NEXT: vextractps $1, %xmm1, %eax
; AVX-32-NEXT: shrl $31, %eax ; AVX-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp) ; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; AVX-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX-32-NEXT: fstpl {{[0-9]+}}(%esp) ; AVX-32-NEXT: fstpl {{[0-9]+}}(%esp)
; AVX-32-NEXT: wait ; AVX-32-NEXT: wait
; AVX-32-NEXT: vextractps $3, %xmm1, %eax ; AVX-32-NEXT: vextractps $3, %xmm1, %eax
; AVX-32-NEXT: shrl $31, %eax ; AVX-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp) ; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; AVX-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX-32-NEXT: fstpl {{[0-9]+}}(%esp) ; AVX-32-NEXT: fstpl {{[0-9]+}}(%esp)
; AVX-32-NEXT: wait ; AVX-32-NEXT: wait
; AVX-32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; AVX-32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX-32-NEXT: vmovhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1] ; AVX-32-NEXT: vmovhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]
; AVX-32-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero ; AVX-32-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; AVX-32-NEXT: vmovhps {{.*#+}} xmm1 = xmm1[0,1],mem[0,1] ; AVX-32-NEXT: vmovhps {{.*#+}} xmm1 = xmm1[0,1],mem[0,1]
; AVX-32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX-32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX-32-NEXT: movl %ebp, %esp ; AVX-32-NEXT: movl %ebp, %esp
▲ Show 20 Lines • Show All 249 Lines • ▼ Show 20 Lines
; AVX-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp) ; AVX-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp)
; AVX-32-NEXT: vextractf128 $1, %ymm0, %xmm1 ; AVX-32-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp) ; AVX-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp)
; AVX-32-NEXT: vpermilps {{.*#+}} xmm2 = xmm1[2,3,2,3] ; AVX-32-NEXT: vpermilps {{.*#+}} xmm2 = xmm1[2,3,2,3]
; AVX-32-NEXT: vmovlps %xmm2, {{[0-9]+}}(%esp) ; AVX-32-NEXT: vmovlps %xmm2, {{[0-9]+}}(%esp)
; AVX-32-NEXT: vextractps $1, %xmm0, %eax ; AVX-32-NEXT: vextractps $1, %xmm0, %eax
; AVX-32-NEXT: shrl $31, %eax ; AVX-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp) ; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; AVX-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX-32-NEXT: fstps (%esp) ; AVX-32-NEXT: fstps (%esp)
; AVX-32-NEXT: wait ; AVX-32-NEXT: wait
; AVX-32-NEXT: vextractps $3, %xmm0, %eax ; AVX-32-NEXT: vextractps $3, %xmm0, %eax
; AVX-32-NEXT: shrl $31, %eax ; AVX-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp) ; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; AVX-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX-32-NEXT: fstps {{[0-9]+}}(%esp) ; AVX-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX-32-NEXT: wait ; AVX-32-NEXT: wait
; AVX-32-NEXT: vextractps $1, %xmm1, %eax ; AVX-32-NEXT: vextractps $1, %xmm1, %eax
; AVX-32-NEXT: shrl $31, %eax ; AVX-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp) ; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; AVX-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX-32-NEXT: fstps {{[0-9]+}}(%esp) ; AVX-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX-32-NEXT: wait ; AVX-32-NEXT: wait
; AVX-32-NEXT: vextractps $3, %xmm1, %eax ; AVX-32-NEXT: vextractps $3, %xmm1, %eax
; AVX-32-NEXT: shrl $31, %eax ; AVX-32-NEXT: shrl $31, %eax
; AVX-32-NEXT: fildll {{[0-9]+}}(%esp) ; AVX-32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; AVX-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; AVX-32-NEXT: fstps {{[0-9]+}}(%esp) ; AVX-32-NEXT: fstps {{[0-9]+}}(%esp)
; AVX-32-NEXT: wait ; AVX-32-NEXT: wait
; AVX-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; AVX-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; AVX-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] ; AVX-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]
; AVX-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] ; AVX-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
; AVX-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] ; AVX-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
; AVX-32-NEXT: movl %ebp, %esp ; AVX-32-NEXT: movl %ebp, %esp
; AVX-32-NEXT: popl %ebp ; AVX-32-NEXT: popl %ebp
▲ Show 20 Lines • Show All 111 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vec-strict-inttofp-512.ll

Show All 36 Lines %result = call <16 x float> @llvm.experimental.constrained.sitofp.v16f32.v16i1(<16 x i1> %x,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <16 x float> %result ret <16 x float> %result
} }
define <16 x float> @uitofp_v16i1_v16f32(<16 x i1> %x) #0 { define <16 x float> @uitofp_v16i1_v16f32(<16 x i1> %x) #0 {
; NODQ-32-LABEL: uitofp_v16i1_v16f32: ; NODQ-32-LABEL: uitofp_v16i1_v16f32:
; NODQ-32: # %bb.0: ; NODQ-32: # %bb.0:
; NODQ-32-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; NODQ-32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; NODQ-32-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero ; NODQ-32-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; NODQ-32-NEXT: vcvtdq2ps %zmm0, %zmm0 ; NODQ-32-NEXT: vcvtdq2ps %zmm0, %zmm0
; NODQ-32-NEXT: retl ; NODQ-32-NEXT: retl
; ;
; NODQ-64-LABEL: uitofp_v16i1_v16f32: ; NODQ-64-LABEL: uitofp_v16i1_v16f32:
; NODQ-64: # %bb.0: ; NODQ-64: # %bb.0:
; NODQ-64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; NODQ-64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; NODQ-64-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero ; NODQ-64-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; NODQ-64-NEXT: vcvtdq2ps %zmm0, %zmm0 ; NODQ-64-NEXT: vcvtdq2ps %zmm0, %zmm0
; NODQ-64-NEXT: retq ; NODQ-64-NEXT: retq
; ;
; DQ-32-LABEL: uitofp_v16i1_v16f32: ; DQ-32-LABEL: uitofp_v16i1_v16f32:
; DQ-32: # %bb.0: ; DQ-32: # %bb.0:
; DQ-32-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; DQ-32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; DQ-32-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero ; DQ-32-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
; DQ-32-NEXT: vcvtdq2ps %zmm0, %zmm0 ; DQ-32-NEXT: vcvtdq2ps %zmm0, %zmm0
; DQ-32-NEXT: retl ; DQ-32-NEXT: retl
; ;
; DQ-64-LABEL: uitofp_v16i1_v16f32: ; DQ-64-LABEL: uitofp_v16i1_v16f32:
; DQ-64: # %bb.0: ; DQ-64: # %bb.0:
; DQ-64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; DQ-64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; DQ-64-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero ; DQ-64-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Lines %result = call <8 x double> @llvm.experimental.constrained.sitofp.v8f64.v8i1(<8 x i1> %x,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <8 x double> %result ret <8 x double> %result
} }
define <8 x double> @uitofp_v8i1_v8f64(<8 x i1> %x) #0 { define <8 x double> @uitofp_v8i1_v8f64(<8 x i1> %x) #0 {
; NODQ-32-LABEL: uitofp_v8i1_v8f64: ; NODQ-32-LABEL: uitofp_v8i1_v8f64:
; NODQ-32: # %bb.0: ; NODQ-32: # %bb.0:
; NODQ-32-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; NODQ-32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; NODQ-32-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; NODQ-32-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; NODQ-32-NEXT: vcvtdq2pd %ymm0, %zmm0 ; NODQ-32-NEXT: vcvtdq2pd %ymm0, %zmm0
; NODQ-32-NEXT: retl ; NODQ-32-NEXT: retl
; ;
; NODQ-64-LABEL: uitofp_v8i1_v8f64: ; NODQ-64-LABEL: uitofp_v8i1_v8f64:
; NODQ-64: # %bb.0: ; NODQ-64: # %bb.0:
; NODQ-64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; NODQ-64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; NODQ-64-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; NODQ-64-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; NODQ-64-NEXT: vcvtdq2pd %ymm0, %zmm0 ; NODQ-64-NEXT: vcvtdq2pd %ymm0, %zmm0
; NODQ-64-NEXT: retq ; NODQ-64-NEXT: retq
; ;
; DQ-32-LABEL: uitofp_v8i1_v8f64: ; DQ-32-LABEL: uitofp_v8i1_v8f64:
; DQ-32: # %bb.0: ; DQ-32: # %bb.0:
; DQ-32-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; DQ-32-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; DQ-32-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; DQ-32-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; DQ-32-NEXT: vcvtdq2pd %ymm0, %zmm0 ; DQ-32-NEXT: vcvtdq2pd %ymm0, %zmm0
; DQ-32-NEXT: retl ; DQ-32-NEXT: retl
; ;
; DQ-64-LABEL: uitofp_v8i1_v8f64: ; DQ-64-LABEL: uitofp_v8i1_v8f64:
; DQ-64: # %bb.0: ; DQ-64: # %bb.0:
; DQ-64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; DQ-64-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; DQ-64-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; DQ-64-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
▲ Show 20 Lines • Show All 196 Lines • ▼ Show 20 Lines
; NODQ-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp) ; NODQ-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp)
; NODQ-32-NEXT: vextractf128 $1, %ymm0, %xmm1 ; NODQ-32-NEXT: vextractf128 $1, %ymm0, %xmm1
; NODQ-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp) ; NODQ-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp)
; NODQ-32-NEXT: vpermilps {{.*#+}} xmm4 = xmm1[2,3,2,3] ; NODQ-32-NEXT: vpermilps {{.*#+}} xmm4 = xmm1[2,3,2,3]
; NODQ-32-NEXT: vmovlps %xmm4, {{[0-9]+}}(%esp) ; NODQ-32-NEXT: vmovlps %xmm4, {{[0-9]+}}(%esp)
; NODQ-32-NEXT: vextractps $1, %xmm2, %eax ; NODQ-32-NEXT: vextractps $1, %xmm2, %eax
; NODQ-32-NEXT: shrl $31, %eax ; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; NODQ-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; NODQ-32-NEXT: fstpl {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fstpl {{[0-9]+}}(%esp)
; NODQ-32-NEXT: wait ; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vextractps $3, %xmm2, %eax ; NODQ-32-NEXT: vextractps $3, %xmm2, %eax
; NODQ-32-NEXT: shrl $31, %eax ; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; NODQ-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; NODQ-32-NEXT: fstpl {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fstpl {{[0-9]+}}(%esp)
; NODQ-32-NEXT: wait ; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vextractps $1, %xmm3, %eax ; NODQ-32-NEXT: vextractps $1, %xmm3, %eax
; NODQ-32-NEXT: shrl $31, %eax ; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; NODQ-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; NODQ-32-NEXT: fstpl {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fstpl {{[0-9]+}}(%esp)
; NODQ-32-NEXT: wait ; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vextractps $3, %xmm3, %eax ; NODQ-32-NEXT: vextractps $3, %xmm3, %eax
; NODQ-32-NEXT: shrl $31, %eax ; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; NODQ-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; NODQ-32-NEXT: fstpl {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fstpl {{[0-9]+}}(%esp)
; NODQ-32-NEXT: wait ; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vextractps $1, %xmm0, %eax ; NODQ-32-NEXT: vextractps $1, %xmm0, %eax
; NODQ-32-NEXT: shrl $31, %eax ; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; NODQ-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; NODQ-32-NEXT: fstpl (%esp) ; NODQ-32-NEXT: fstpl (%esp)
; NODQ-32-NEXT: wait ; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vextractps $3, %xmm0, %eax ; NODQ-32-NEXT: vextractps $3, %xmm0, %eax
; NODQ-32-NEXT: shrl $31, %eax ; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; NODQ-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; NODQ-32-NEXT: fstpl {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fstpl {{[0-9]+}}(%esp)
; NODQ-32-NEXT: wait ; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vextractps $1, %xmm1, %eax ; NODQ-32-NEXT: vextractps $1, %xmm1, %eax
; NODQ-32-NEXT: shrl $31, %eax ; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; NODQ-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; NODQ-32-NEXT: fstpl {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fstpl {{[0-9]+}}(%esp)
; NODQ-32-NEXT: wait ; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vextractps $3, %xmm1, %eax ; NODQ-32-NEXT: vextractps $3, %xmm1, %eax
; NODQ-32-NEXT: shrl $31, %eax ; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; NODQ-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; NODQ-32-NEXT: fstpl {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fstpl {{[0-9]+}}(%esp)
; NODQ-32-NEXT: wait ; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; NODQ-32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; NODQ-32-NEXT: vmovhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1] ; NODQ-32-NEXT: vmovhps {{.*#+}} xmm0 = xmm0[0,1],mem[0,1]
; NODQ-32-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero ; NODQ-32-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
; NODQ-32-NEXT: vmovhps {{.*#+}} xmm1 = xmm1[0,1],mem[0,1] ; NODQ-32-NEXT: vmovhps {{.*#+}} xmm1 = xmm1[0,1],mem[0,1]
; NODQ-32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; NODQ-32-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; NODQ-32-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero ; NODQ-32-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
▲ Show 20 Lines • Show All 166 Lines • ▼ Show 20 Lines
; NODQ-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp) ; NODQ-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp)
; NODQ-32-NEXT: vextractf32x4 $3, %zmm0, %xmm1 ; NODQ-32-NEXT: vextractf32x4 $3, %zmm0, %xmm1
; NODQ-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp) ; NODQ-32-NEXT: vmovlps %xmm1, {{[0-9]+}}(%esp)
; NODQ-32-NEXT: vpermilps {{.*#+}} xmm4 = xmm1[2,3,2,3] ; NODQ-32-NEXT: vpermilps {{.*#+}} xmm4 = xmm1[2,3,2,3]
; NODQ-32-NEXT: vmovlps %xmm4, {{[0-9]+}}(%esp) ; NODQ-32-NEXT: vmovlps %xmm4, {{[0-9]+}}(%esp)
; NODQ-32-NEXT: vextractps $1, %xmm0, %eax ; NODQ-32-NEXT: vextractps $1, %xmm0, %eax
; NODQ-32-NEXT: shrl $31, %eax ; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; NODQ-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; NODQ-32-NEXT: fstps (%esp) ; NODQ-32-NEXT: fstps (%esp)
; NODQ-32-NEXT: wait ; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vextractps $3, %xmm0, %eax ; NODQ-32-NEXT: vextractps $3, %xmm0, %eax
; NODQ-32-NEXT: shrl $31, %eax ; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; NODQ-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp)
; NODQ-32-NEXT: wait ; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vextractps $1, %xmm3, %eax ; NODQ-32-NEXT: vextractps $1, %xmm3, %eax
; NODQ-32-NEXT: shrl $31, %eax ; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; NODQ-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp)
; NODQ-32-NEXT: wait ; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vextractps $3, %xmm3, %eax ; NODQ-32-NEXT: vextractps $3, %xmm3, %eax
; NODQ-32-NEXT: shrl $31, %eax ; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; NODQ-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp)
; NODQ-32-NEXT: wait ; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vextractps $1, %xmm2, %eax ; NODQ-32-NEXT: vextractps $1, %xmm2, %eax
; NODQ-32-NEXT: shrl $31, %eax ; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; NODQ-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp)
; NODQ-32-NEXT: wait ; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vextractps $3, %xmm2, %eax ; NODQ-32-NEXT: vextractps $3, %xmm2, %eax
; NODQ-32-NEXT: shrl $31, %eax ; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; NODQ-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp)
; NODQ-32-NEXT: wait ; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vextractps $1, %xmm1, %eax ; NODQ-32-NEXT: vextractps $1, %xmm1, %eax
; NODQ-32-NEXT: shrl $31, %eax ; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; NODQ-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp)
; NODQ-32-NEXT: wait ; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vextractps $3, %xmm1, %eax ; NODQ-32-NEXT: vextractps $3, %xmm1, %eax
; NODQ-32-NEXT: shrl $31, %eax ; NODQ-32-NEXT: shrl $31, %eax
; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fildll {{[0-9]+}}(%esp)
; NODQ-32-NEXT: fadds {{\.LCPI.*}}(,%eax,4) ; NODQ-32-NEXT: fadds {{\.LCPI[0-9]+_[0-9]+}}(,%eax,4)
; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp) ; NODQ-32-NEXT: fstps {{[0-9]+}}(%esp)
; NODQ-32-NEXT: wait ; NODQ-32-NEXT: wait
; NODQ-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; NODQ-32-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; NODQ-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] ; NODQ-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]
; NODQ-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] ; NODQ-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
; NODQ-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] ; NODQ-32-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
; NODQ-32-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero ; NODQ-32-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; NODQ-32-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3] ; NODQ-32-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],mem[0],xmm1[2,3]
▲ Show 20 Lines • Show All 49 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vec_fabs.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X86 --check-prefix=X86-AVX ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X86 --check-prefix=X86-AVX
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512vl | FileCheck %s --check-prefix=X86 --check-prefix=X86-AVX512VL ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512vl | FileCheck %s --check-prefix=X86 --check-prefix=X86-AVX512VL
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512dq,+avx512vl | FileCheck %s --check-prefix=X86 --check-prefix=X86-AVX512VLDQ ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512dq,+avx512vl | FileCheck %s --check-prefix=X86 --check-prefix=X86-AVX512VLDQ
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX512VL ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX512VL
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq,+avx512vl | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX512VLDQ ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq,+avx512vl | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX512VLDQ
define <2 x double> @fabs_v2f64(<2 x double> %p) { define <2 x double> @fabs_v2f64(<2 x double> %p) {
; X86-LABEL: fabs_v2f64: ; X86-LABEL: fabs_v2f64:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vandps {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: fabs_v2f64: ; X64-LABEL: fabs_v2f64:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 ; X64-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%t = call <2 x double> @llvm.fabs.v2f64(<2 x double> %p) %t = call <2 x double> @llvm.fabs.v2f64(<2 x double> %p)
ret <2 x double> %t ret <2 x double> %t
} }
declare <2 x double> @llvm.fabs.v2f64(<2 x double> %p) declare <2 x double> @llvm.fabs.v2f64(<2 x double> %p)
define <4 x float> @fabs_v4f32(<4 x float> %p) { define <4 x float> @fabs_v4f32(<4 x float> %p) {
; X86-AVX-LABEL: fabs_v4f32: ; X86-AVX-LABEL: fabs_v4f32:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vandps {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X86-AVX512VL-LABEL: fabs_v4f32: ; X86-AVX512VL-LABEL: fabs_v4f32:
; X86-AVX512VL: # %bb.0: ; X86-AVX512VL: # %bb.0:
; X86-AVX512VL-NEXT: vpandd {{\.LCPI.*}}{1to4}, %xmm0, %xmm0 ; X86-AVX512VL-NEXT: vpandd {{\.LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0
; X86-AVX512VL-NEXT: retl ; X86-AVX512VL-NEXT: retl
; ;
; X86-AVX512VLDQ-LABEL: fabs_v4f32: ; X86-AVX512VLDQ-LABEL: fabs_v4f32:
; X86-AVX512VLDQ: # %bb.0: ; X86-AVX512VLDQ: # %bb.0:
; X86-AVX512VLDQ-NEXT: vandps {{\.LCPI.*}}{1to4}, %xmm0, %xmm0 ; X86-AVX512VLDQ-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}{1to4}, %xmm0, %xmm0
; X86-AVX512VLDQ-NEXT: retl ; X86-AVX512VLDQ-NEXT: retl
; ;
; X64-AVX-LABEL: fabs_v4f32: ; X64-AVX-LABEL: fabs_v4f32:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
; ;
; X64-AVX512VL-LABEL: fabs_v4f32: ; X64-AVX512VL-LABEL: fabs_v4f32:
; X64-AVX512VL: # %bb.0: ; X64-AVX512VL: # %bb.0:
; X64-AVX512VL-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm0, %xmm0 ; X64-AVX512VL-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm0, %xmm0
; X64-AVX512VL-NEXT: retq ; X64-AVX512VL-NEXT: retq
; ;
; X64-AVX512VLDQ-LABEL: fabs_v4f32: ; X64-AVX512VLDQ-LABEL: fabs_v4f32:
; X64-AVX512VLDQ: # %bb.0: ; X64-AVX512VLDQ: # %bb.0:
; X64-AVX512VLDQ-NEXT: vandps {{.*}}(%rip){1to4}, %xmm0, %xmm0 ; X64-AVX512VLDQ-NEXT: vandps {{.*}}(%rip){1to4}, %xmm0, %xmm0
; X64-AVX512VLDQ-NEXT: retq ; X64-AVX512VLDQ-NEXT: retq
%t = call <4 x float> @llvm.fabs.v4f32(<4 x float> %p) %t = call <4 x float> @llvm.fabs.v4f32(<4 x float> %p)
ret <4 x float> %t ret <4 x float> %t
} }
declare <4 x float> @llvm.fabs.v4f32(<4 x float> %p) declare <4 x float> @llvm.fabs.v4f32(<4 x float> %p)
define <4 x double> @fabs_v4f64(<4 x double> %p) { define <4 x double> @fabs_v4f64(<4 x double> %p) {
; X86-AVX-LABEL: fabs_v4f64: ; X86-AVX-LABEL: fabs_v4f64:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vandps {{\.LCPI.*}}, %ymm0, %ymm0 ; X86-AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X86-AVX512VL-LABEL: fabs_v4f64: ; X86-AVX512VL-LABEL: fabs_v4f64:
; X86-AVX512VL: # %bb.0: ; X86-AVX512VL: # %bb.0:
; X86-AVX512VL-NEXT: vpandq {{\.LCPI.*}}{1to4}, %ymm0, %ymm0 ; X86-AVX512VL-NEXT: vpandq {{\.LCPI[0-9]+_[0-9]+}}{1to4}, %ymm0, %ymm0
; X86-AVX512VL-NEXT: retl ; X86-AVX512VL-NEXT: retl
; ;
; X86-AVX512VLDQ-LABEL: fabs_v4f64: ; X86-AVX512VLDQ-LABEL: fabs_v4f64:
; X86-AVX512VLDQ: # %bb.0: ; X86-AVX512VLDQ: # %bb.0:
; X86-AVX512VLDQ-NEXT: vandpd {{\.LCPI.*}}{1to4}, %ymm0, %ymm0 ; X86-AVX512VLDQ-NEXT: vandpd {{\.LCPI[0-9]+_[0-9]+}}{1to4}, %ymm0, %ymm0
; X86-AVX512VLDQ-NEXT: retl ; X86-AVX512VLDQ-NEXT: retl
; ;
; X64-AVX-LABEL: fabs_v4f64: ; X64-AVX-LABEL: fabs_v4f64:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 ; X64-AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
; ;
; X64-AVX512VL-LABEL: fabs_v4f64: ; X64-AVX512VL-LABEL: fabs_v4f64:
; X64-AVX512VL: # %bb.0: ; X64-AVX512VL: # %bb.0:
; X64-AVX512VL-NEXT: vpandq {{.*}}(%rip){1to4}, %ymm0, %ymm0 ; X64-AVX512VL-NEXT: vpandq {{.*}}(%rip){1to4}, %ymm0, %ymm0
; X64-AVX512VL-NEXT: retq ; X64-AVX512VL-NEXT: retq
; ;
; X64-AVX512VLDQ-LABEL: fabs_v4f64: ; X64-AVX512VLDQ-LABEL: fabs_v4f64:
; X64-AVX512VLDQ: # %bb.0: ; X64-AVX512VLDQ: # %bb.0:
; X64-AVX512VLDQ-NEXT: vandpd {{.*}}(%rip){1to4}, %ymm0, %ymm0 ; X64-AVX512VLDQ-NEXT: vandpd {{.*}}(%rip){1to4}, %ymm0, %ymm0
; X64-AVX512VLDQ-NEXT: retq ; X64-AVX512VLDQ-NEXT: retq
%t = call <4 x double> @llvm.fabs.v4f64(<4 x double> %p) %t = call <4 x double> @llvm.fabs.v4f64(<4 x double> %p)
ret <4 x double> %t ret <4 x double> %t
} }
declare <4 x double> @llvm.fabs.v4f64(<4 x double> %p) declare <4 x double> @llvm.fabs.v4f64(<4 x double> %p)
define <8 x float> @fabs_v8f32(<8 x float> %p) { define <8 x float> @fabs_v8f32(<8 x float> %p) {
; X86-AVX-LABEL: fabs_v8f32: ; X86-AVX-LABEL: fabs_v8f32:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vandps {{\.LCPI.*}}, %ymm0, %ymm0 ; X86-AVX-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X86-AVX512VL-LABEL: fabs_v8f32: ; X86-AVX512VL-LABEL: fabs_v8f32:
; X86-AVX512VL: # %bb.0: ; X86-AVX512VL: # %bb.0:
; X86-AVX512VL-NEXT: vpandd {{\.LCPI.*}}{1to8}, %ymm0, %ymm0 ; X86-AVX512VL-NEXT: vpandd {{\.LCPI[0-9]+_[0-9]+}}{1to8}, %ymm0, %ymm0
; X86-AVX512VL-NEXT: retl ; X86-AVX512VL-NEXT: retl
; ;
; X86-AVX512VLDQ-LABEL: fabs_v8f32: ; X86-AVX512VLDQ-LABEL: fabs_v8f32:
; X86-AVX512VLDQ: # %bb.0: ; X86-AVX512VLDQ: # %bb.0:
; X86-AVX512VLDQ-NEXT: vandps {{\.LCPI.*}}{1to8}, %ymm0, %ymm0 ; X86-AVX512VLDQ-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}{1to8}, %ymm0, %ymm0
; X86-AVX512VLDQ-NEXT: retl ; X86-AVX512VLDQ-NEXT: retl
; ;
; X64-AVX-LABEL: fabs_v8f32: ; X64-AVX-LABEL: fabs_v8f32:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 ; X64-AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
; ;
; X64-AVX512VL-LABEL: fabs_v8f32: ; X64-AVX512VL-LABEL: fabs_v8f32:
Show All 15 Lines
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vmovaps {{.*#+}} ymm2 = [NaN,NaN,NaN,NaN] ; X86-AVX-NEXT: vmovaps {{.*#+}} ymm2 = [NaN,NaN,NaN,NaN]
; X86-AVX-NEXT: vandps %ymm2, %ymm0, %ymm0 ; X86-AVX-NEXT: vandps %ymm2, %ymm0, %ymm0
; X86-AVX-NEXT: vandps %ymm2, %ymm1, %ymm1 ; X86-AVX-NEXT: vandps %ymm2, %ymm1, %ymm1
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X86-AVX512VL-LABEL: fabs_v8f64: ; X86-AVX512VL-LABEL: fabs_v8f64:
; X86-AVX512VL: # %bb.0: ; X86-AVX512VL: # %bb.0:
; X86-AVX512VL-NEXT: vpandq {{\.LCPI.*}}{1to8}, %zmm0, %zmm0 ; X86-AVX512VL-NEXT: vpandq {{\.LCPI[0-9]+_[0-9]+}}{1to8}, %zmm0, %zmm0
; X86-AVX512VL-NEXT: retl ; X86-AVX512VL-NEXT: retl
; ;
; X86-AVX512VLDQ-LABEL: fabs_v8f64: ; X86-AVX512VLDQ-LABEL: fabs_v8f64:
; X86-AVX512VLDQ: # %bb.0: ; X86-AVX512VLDQ: # %bb.0:
; X86-AVX512VLDQ-NEXT: vandpd {{\.LCPI.*}}{1to8}, %zmm0, %zmm0 ; X86-AVX512VLDQ-NEXT: vandpd {{\.LCPI[0-9]+_[0-9]+}}{1to8}, %zmm0, %zmm0
; X86-AVX512VLDQ-NEXT: retl ; X86-AVX512VLDQ-NEXT: retl
; ;
; X64-AVX-LABEL: fabs_v8f64: ; X64-AVX-LABEL: fabs_v8f64:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovaps {{.*#+}} ymm2 = [NaN,NaN,NaN,NaN] ; X64-AVX-NEXT: vmovaps {{.*#+}} ymm2 = [NaN,NaN,NaN,NaN]
; X64-AVX-NEXT: vandps %ymm2, %ymm0, %ymm0 ; X64-AVX-NEXT: vandps %ymm2, %ymm0, %ymm0
; X64-AVX-NEXT: vandps %ymm2, %ymm1, %ymm1 ; X64-AVX-NEXT: vandps %ymm2, %ymm1, %ymm1
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
Show All 17 Lines
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vmovaps {{.*#+}} ymm2 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN] ; X86-AVX-NEXT: vmovaps {{.*#+}} ymm2 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN]
; X86-AVX-NEXT: vandps %ymm2, %ymm0, %ymm0 ; X86-AVX-NEXT: vandps %ymm2, %ymm0, %ymm0
; X86-AVX-NEXT: vandps %ymm2, %ymm1, %ymm1 ; X86-AVX-NEXT: vandps %ymm2, %ymm1, %ymm1
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X86-AVX512VL-LABEL: fabs_v16f32: ; X86-AVX512VL-LABEL: fabs_v16f32:
; X86-AVX512VL: # %bb.0: ; X86-AVX512VL: # %bb.0:
; X86-AVX512VL-NEXT: vpandd {{\.LCPI.*}}{1to16}, %zmm0, %zmm0 ; X86-AVX512VL-NEXT: vpandd {{\.LCPI[0-9]+_[0-9]+}}{1to16}, %zmm0, %zmm0
; X86-AVX512VL-NEXT: retl ; X86-AVX512VL-NEXT: retl
; ;
; X86-AVX512VLDQ-LABEL: fabs_v16f32: ; X86-AVX512VLDQ-LABEL: fabs_v16f32:
; X86-AVX512VLDQ: # %bb.0: ; X86-AVX512VLDQ: # %bb.0:
; X86-AVX512VLDQ-NEXT: vandps {{\.LCPI.*}}{1to16}, %zmm0, %zmm0 ; X86-AVX512VLDQ-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}{1to16}, %zmm0, %zmm0
; X86-AVX512VLDQ-NEXT: retl ; X86-AVX512VLDQ-NEXT: retl
; ;
; X64-AVX-LABEL: fabs_v16f32: ; X64-AVX-LABEL: fabs_v16f32:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vmovaps {{.*#+}} ymm2 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN] ; X64-AVX-NEXT: vmovaps {{.*#+}} ymm2 = [NaN,NaN,NaN,NaN,NaN,NaN,NaN,NaN]
; X64-AVX-NEXT: vandps %ymm2, %ymm0, %ymm0 ; X64-AVX-NEXT: vandps %ymm2, %ymm0, %ymm0
; X64-AVX-NEXT: vandps %ymm2, %ymm1, %ymm1 ; X64-AVX-NEXT: vandps %ymm2, %ymm1, %ymm1
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
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llvm/test/CodeGen/X86/vec_fneg.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse | FileCheck %s --check-prefix=X32-SSE --check-prefix=X32-SSE1 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse | FileCheck %s --check-prefix=X32-SSE --check-prefix=X32-SSE1
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32-SSE --check-prefix=X32-SSE2 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32-SSE --check-prefix=X32-SSE2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-sse2 | FileCheck %s --check-prefix=X64-SSE --check-prefix=X64-SSE1 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-sse2 | FileCheck %s --check-prefix=X64-SSE --check-prefix=X64-SSE1
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64-SSE --check-prefix=X64-SSE2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64-SSE --check-prefix=X64-SSE2
; FNEG is defined as subtraction from -0.0. ; FNEG is defined as subtraction from -0.0.
; This test verifies that we use an xor with a constant to flip the sign bits; no subtraction needed. ; This test verifies that we use an xor with a constant to flip the sign bits; no subtraction needed.
define <4 x float> @t1(<4 x float> %Q) nounwind { define <4 x float> @t1(<4 x float> %Q) nounwind {
; X32-SSE-LABEL: t1: ; X32-SSE-LABEL: t1:
; X32-SSE: # %bb.0: ; X32-SSE: # %bb.0:
; X32-SSE-NEXT: xorps {{\.LCPI.*}}, %xmm0 ; X32-SSE-NEXT: xorps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: t1: ; X64-SSE-LABEL: t1:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: xorps {{.*}}(%rip), %xmm0 ; X64-SSE-NEXT: xorps {{.*}}(%rip), %xmm0
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
%tmp = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %Q %tmp = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %Q
ret <4 x float> %tmp ret <4 x float> %tmp
▲ Show 20 Lines • Show All 139 Lines • ▼ Show 20 Lines; X64-SSE2-NEXT: retq
%bitcast = bitcast i64 %i to <2 x float> %bitcast = bitcast i64 %i to <2 x float>
%fneg = fsub <2 x float> <float -0.0, float -0.0>, %bitcast %fneg = fsub <2 x float> <float -0.0, float -0.0>, %bitcast
ret <2 x float> %fneg ret <2 x float> %fneg
} }
define <4 x float> @fneg_undef_elts_v4f32(<4 x float> %x) { define <4 x float> @fneg_undef_elts_v4f32(<4 x float> %x) {
; X32-SSE-LABEL: fneg_undef_elts_v4f32: ; X32-SSE-LABEL: fneg_undef_elts_v4f32:
; X32-SSE: # %bb.0: ; X32-SSE: # %bb.0:
; X32-SSE-NEXT: xorps {{\.LCPI.*}}, %xmm0 ; X32-SSE-NEXT: xorps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: fneg_undef_elts_v4f32: ; X64-SSE-LABEL: fneg_undef_elts_v4f32:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: xorps {{.*}}(%rip), %xmm0 ; X64-SSE-NEXT: xorps {{.*}}(%rip), %xmm0
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
%r = fsub <4 x float> <float -0.0, float undef, float undef, float -0.0>, %x %r = fsub <4 x float> <float -0.0, float undef, float undef, float -0.0>, %x
ret <4 x float> %r ret <4 x float> %r
Show All 11 Lines
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
%r = fsub <4 x float> %x, <float 0.0, float undef, float 0.0, float undef> %r = fsub <4 x float> %x, <float 0.0, float undef, float 0.0, float undef>
ret <4 x float> %r ret <4 x float> %r
} }
define <4 x float> @fneg(<4 x float> %Q) nounwind { define <4 x float> @fneg(<4 x float> %Q) nounwind {
; X32-SSE-LABEL: fneg: ; X32-SSE-LABEL: fneg:
; X32-SSE: # %bb.0: ; X32-SSE: # %bb.0:
; X32-SSE-NEXT: xorps {{\.LCPI.*}}, %xmm0 ; X32-SSE-NEXT: xorps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: fneg: ; X64-SSE-LABEL: fneg:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: xorps {{.*}}(%rip), %xmm0 ; X64-SSE-NEXT: xorps {{.*}}(%rip), %xmm0
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
%tmp = fneg <4 x float> %Q %tmp = fneg <4 x float> %Q
ret <4 x float> %tmp ret <4 x float> %tmp
} }

llvm/test/CodeGen/X86/vec_fpext.ll

Show First 20 Lines • Show All 249 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
define <2 x double> @fpext_fromconst() { define <2 x double> @fpext_fromconst() {
; X32-SSE-LABEL: fpext_fromconst: ; X32-SSE-LABEL: fpext_fromconst:
; X32-SSE: # %bb.0: # %entry ; X32-SSE: # %bb.0: # %entry
; X32-SSE-NEXT: movaps {{.*#+}} xmm0 = [1.0E+0,-2.0E+0] ; X32-SSE-NEXT: movaps {{.*#+}} xmm0 = [1.0E+0,-2.0E+0]
; X32-SSE-NEXT: # encoding: [0x0f,0x28,0x05,A,A,A,A] ; X32-SSE-NEXT: # encoding: [0x0f,0x28,0x05,A,A,A,A]
; X32-SSE-NEXT: # fixup A - offset: 3, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X32-SSE-NEXT: # fixup A - offset: 3, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X32-SSE-NEXT: retl # encoding: [0xc3] ; X32-SSE-NEXT: retl # encoding: [0xc3]
; ;
; X32-AVX-LABEL: fpext_fromconst: ; X32-AVX-LABEL: fpext_fromconst:
; X32-AVX: # %bb.0: # %entry ; X32-AVX: # %bb.0: # %entry
; X32-AVX-NEXT: vmovaps {{.*#+}} xmm0 = [1.0E+0,-2.0E+0] ; X32-AVX-NEXT: vmovaps {{.*#+}} xmm0 = [1.0E+0,-2.0E+0]
; X32-AVX-NEXT: # encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A] ; X32-AVX-NEXT: # encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
; X32-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X32-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X32-AVX-NEXT: retl # encoding: [0xc3] ; X32-AVX-NEXT: retl # encoding: [0xc3]
; ;
; X32-AVX512VL-LABEL: fpext_fromconst: ; X32-AVX512VL-LABEL: fpext_fromconst:
; X32-AVX512VL: # %bb.0: # %entry ; X32-AVX512VL: # %bb.0: # %entry
; X32-AVX512VL-NEXT: vmovaps {{\.LCPI.*}}, %xmm0 # EVEX TO VEX Compression xmm0 = [1.0E+0,-2.0E+0] ; X32-AVX512VL-NEXT: vmovaps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0 # EVEX TO VEX Compression xmm0 = [1.0E+0,-2.0E+0]
; X32-AVX512VL-NEXT: # encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A] ; X32-AVX512VL-NEXT: # encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
; X32-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}, kind: FK_Data_4 ; X32-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}, kind: FK_Data_4
; X32-AVX512VL-NEXT: retl # encoding: [0xc3] ; X32-AVX512VL-NEXT: retl # encoding: [0xc3]
; ;
; X64-SSE-LABEL: fpext_fromconst: ; X64-SSE-LABEL: fpext_fromconst:
; X64-SSE: # %bb.0: # %entry ; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: movaps {{.*#+}} xmm0 = [1.0E+0,-2.0E+0] ; X64-SSE-NEXT: movaps {{.*#+}} xmm0 = [1.0E+0,-2.0E+0]
; X64-SSE-NEXT: # encoding: [0x0f,0x28,0x05,A,A,A,A] ; X64-SSE-NEXT: # encoding: [0x0f,0x28,0x05,A,A,A,A]
; X64-SSE-NEXT: # fixup A - offset: 3, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-SSE-NEXT: # fixup A - offset: 3, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-SSE-NEXT: retq # encoding: [0xc3] ; X64-SSE-NEXT: retq # encoding: [0xc3]
; ;
; X64-AVX-LABEL: fpext_fromconst: ; X64-AVX-LABEL: fpext_fromconst:
; X64-AVX: # %bb.0: # %entry ; X64-AVX: # %bb.0: # %entry
; X64-AVX-NEXT: vmovaps {{.*#+}} xmm0 = [1.0E+0,-2.0E+0] ; X64-AVX-NEXT: vmovaps {{.*#+}} xmm0 = [1.0E+0,-2.0E+0]
; X64-AVX-NEXT: # encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A] ; X64-AVX-NEXT: # encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX-NEXT: retq # encoding: [0xc3] ; X64-AVX-NEXT: retq # encoding: [0xc3]
; ;
; X64-AVX512VL-LABEL: fpext_fromconst: ; X64-AVX512VL-LABEL: fpext_fromconst:
; X64-AVX512VL: # %bb.0: # %entry ; X64-AVX512VL: # %bb.0: # %entry
; X64-AVX512VL-NEXT: vmovaps {{.*}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [1.0E+0,-2.0E+0] ; X64-AVX512VL-NEXT: vmovaps {{.*}}(%rip), %xmm0 # EVEX TO VEX Compression xmm0 = [1.0E+0,-2.0E+0]
; X64-AVX512VL-NEXT: # encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A] ; X64-AVX512VL-NEXT: # encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI.*}}-4, kind: reloc_riprel_4byte ; X64-AVX512VL-NEXT: # fixup A - offset: 4, value: {{\.LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte
; X64-AVX512VL-NEXT: retq # encoding: [0xc3] ; X64-AVX512VL-NEXT: retq # encoding: [0xc3]
entry: entry:
%0 = insertelement <2 x float> undef, float 1.0, i32 0 %0 = insertelement <2 x float> undef, float 1.0, i32 0
%1 = insertelement <2 x float> %0, float -2.0, i32 1 %1 = insertelement <2 x float> %0, float -2.0, i32 1
%2 = fpext <2 x float> %1 to <2 x double> %2 = fpext <2 x float> %1 to <2 x double>
ret <2 x double> %2 ret <2 x double> %2
} }
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llvm/test/CodeGen/X86/vec_fptrunc.ll

Show First 20 Lines • Show All 180 Lines • ▼ Show 20 Lines; X64-AVX-NEXT: retq
%ret = shufflevector <2 x float> %cvt, <2 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 2> %ret = shufflevector <2 x float> %cvt, <2 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
ret <4 x float> %ret ret <4 x float> %ret
} }
; FIXME: For exact truncations we should be able to fold this. ; FIXME: For exact truncations we should be able to fold this.
define <4 x float> @fptrunc_fromconst() { define <4 x float> @fptrunc_fromconst() {
; X32-SSE-LABEL: fptrunc_fromconst: ; X32-SSE-LABEL: fptrunc_fromconst:
; X32-SSE: # %bb.0: # %entry ; X32-SSE: # %bb.0: # %entry
; X32-SSE-NEXT: cvtpd2ps {{\.LCPI.*}}, %xmm1 ; X32-SSE-NEXT: cvtpd2ps {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X32-SSE-NEXT: cvtpd2ps {{\.LCPI.*}}, %xmm0 ; X32-SSE-NEXT: cvtpd2ps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; X32-SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X32-AVX-LABEL: fptrunc_fromconst: ; X32-AVX-LABEL: fptrunc_fromconst:
; X32-AVX: # %bb.0: # %entry ; X32-AVX: # %bb.0: # %entry
; X32-AVX-NEXT: vcvtpd2psy {{\.LCPI.*}}, %xmm0 ; X32-AVX-NEXT: vcvtpd2psy {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-AVX-NEXT: retl ; X32-AVX-NEXT: retl
; ;
; X64-SSE-LABEL: fptrunc_fromconst: ; X64-SSE-LABEL: fptrunc_fromconst:
; X64-SSE: # %bb.0: # %entry ; X64-SSE: # %bb.0: # %entry
; X64-SSE-NEXT: cvtpd2ps {{.*}}(%rip), %xmm1 ; X64-SSE-NEXT: cvtpd2ps {{.*}}(%rip), %xmm1
; X64-SSE-NEXT: cvtpd2ps {{.*}}(%rip), %xmm0 ; X64-SSE-NEXT: cvtpd2ps {{.*}}(%rip), %xmm0
; X64-SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; X64-SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
Show All 13 Lines

llvm/test/CodeGen/X86/vec_logical.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i386-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE ; RUN: llc < %s -mtriple=i386-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE
; RUN: llc < %s -mtriple=i386-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX ; RUN: llc < %s -mtriple=i386-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
define void @t(<4 x float> %A) { define void @t(<4 x float> %A) {
; SSE-LABEL: t: ; SSE-LABEL: t:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: xorps {{\.LCPI.*}}, %xmm0 ; SSE-NEXT: xorps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; SSE-NEXT: movaps %xmm0, 0 ; SSE-NEXT: movaps %xmm0, 0
; SSE-NEXT: retl ; SSE-NEXT: retl
; ;
; AVX-LABEL: t: ; AVX-LABEL: t:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vxorps {{\.LCPI.*}}, %xmm0, %xmm0 ; AVX-NEXT: vxorps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; AVX-NEXT: vmovaps %xmm0, 0 ; AVX-NEXT: vmovaps %xmm0, 0
; AVX-NEXT: retl ; AVX-NEXT: retl
%tmp1277 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %A %tmp1277 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %A
store <4 x float> %tmp1277, <4 x float>* null store <4 x float> %tmp1277, <4 x float>* null
ret void ret void
} }
define <4 x float> @t1(<4 x float> %a, <4 x float> %b) { define <4 x float> @t1(<4 x float> %a, <4 x float> %b) {
▲ Show 20 Lines • Show All 84 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vec_partial.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64
; PR11580 ; PR11580
define <3 x float> @addf3(<3 x float> %x) { define <3 x float> @addf3(<3 x float> %x) {
; X86-LABEL: addf3: ; X86-LABEL: addf3:
; X86: # %bb.0: # %entry ; X86: # %bb.0: # %entry
; X86-NEXT: addps {{\.LCPI.*}}, %xmm0 ; X86-NEXT: addps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: addf3: ; X64-LABEL: addf3:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: addps {{.*}}(%rip), %xmm0 ; X64-NEXT: addps {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
entry: entry:
%add = fadd <3 x float> %x, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00> %add = fadd <3 x float> %x, <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>
Show All 30 Lines

llvm/test/CodeGen/X86/vec_reassociate.ll

Show All 32 Lines; X64-NEXT: retq
%3 = add <4 x i32> %1, %2 %3 = add <4 x i32> %1, %2
ret <4 x i32> %3 ret <4 x i32> %3
} }
define <4 x i32> @mul_4i32(<4 x i32> %a0, <4 x i32> %a1) { define <4 x i32> @mul_4i32(<4 x i32> %a0, <4 x i32> %a1) {
; X86-LABEL: mul_4i32: ; X86-LABEL: mul_4i32:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: pmulld %xmm1, %xmm0 ; X86-NEXT: pmulld %xmm1, %xmm0
; X86-NEXT: pmulld {{\.LCPI.*}}, %xmm0 ; X86-NEXT: pmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: mul_4i32: ; X64-LABEL: mul_4i32:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: pmulld %xmm1, %xmm0 ; X64-NEXT: pmulld %xmm1, %xmm0
; X64-NEXT: pmulld {{.*}}(%rip), %xmm0 ; X64-NEXT: pmulld {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = mul <4 x i32> %a0, <i32 1, i32 2, i32 3, i32 4> %1 = mul <4 x i32> %a0, <i32 1, i32 2, i32 3, i32 4>
%2 = mul <4 x i32> %a1, <i32 4, i32 3, i32 2, i32 1> %2 = mul <4 x i32> %a1, <i32 4, i32 3, i32 2, i32 1>
%3 = mul <4 x i32> %1, %2 %3 = mul <4 x i32> %1, %2
ret <4 x i32> %3 ret <4 x i32> %3
} }
define <4 x i32> @mul_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) { define <4 x i32> @mul_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
; X86-LABEL: mul_4i32_commute: ; X86-LABEL: mul_4i32_commute:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: pmulld %xmm1, %xmm0 ; X86-NEXT: pmulld %xmm1, %xmm0
; X86-NEXT: pmulld {{\.LCPI.*}}, %xmm0 ; X86-NEXT: pmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: mul_4i32_commute: ; X64-LABEL: mul_4i32_commute:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: pmulld %xmm1, %xmm0 ; X64-NEXT: pmulld %xmm1, %xmm0
; X64-NEXT: pmulld {{.*}}(%rip), %xmm0 ; X64-NEXT: pmulld {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = mul <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %a0 %1 = mul <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %a0
%2 = mul <4 x i32> <i32 4, i32 3, i32 2, i32 1>, %a1 %2 = mul <4 x i32> <i32 4, i32 3, i32 2, i32 1>, %a1
%3 = mul <4 x i32> %1, %2 %3 = mul <4 x i32> %1, %2
ret <4 x i32> %3 ret <4 x i32> %3
} }
define <4 x i32> @and_4i32(<4 x i32> %a0, <4 x i32> %a1) { define <4 x i32> @and_4i32(<4 x i32> %a0, <4 x i32> %a1) {
; X86-LABEL: and_4i32: ; X86-LABEL: and_4i32:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: andps %xmm1, %xmm0 ; X86-NEXT: andps %xmm1, %xmm0
; X86-NEXT: andps {{\.LCPI.*}}, %xmm0 ; X86-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: and_4i32: ; X64-LABEL: and_4i32:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: andps %xmm1, %xmm0 ; X64-NEXT: andps %xmm1, %xmm0
; X64-NEXT: andps {{.*}}(%rip), %xmm0 ; X64-NEXT: andps {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = and <4 x i32> %a0, <i32 -2, i32 -2, i32 3, i32 3> %1 = and <4 x i32> %a0, <i32 -2, i32 -2, i32 3, i32 3>
%2 = and <4 x i32> %a1, <i32 -1, i32 -1, i32 1, i32 1> %2 = and <4 x i32> %a1, <i32 -1, i32 -1, i32 1, i32 1>
%3 = and <4 x i32> %1, %2 %3 = and <4 x i32> %1, %2
ret <4 x i32> %3 ret <4 x i32> %3
} }
define <4 x i32> @and_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) { define <4 x i32> @and_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
; X86-LABEL: and_4i32_commute: ; X86-LABEL: and_4i32_commute:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: andps %xmm1, %xmm0 ; X86-NEXT: andps %xmm1, %xmm0
; X86-NEXT: andps {{\.LCPI.*}}, %xmm0 ; X86-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: and_4i32_commute: ; X64-LABEL: and_4i32_commute:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: andps %xmm1, %xmm0 ; X64-NEXT: andps %xmm1, %xmm0
; X64-NEXT: andps {{.*}}(%rip), %xmm0 ; X64-NEXT: andps {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = and <4 x i32> <i32 -2, i32 -2, i32 3, i32 3>, %a0 %1 = and <4 x i32> <i32 -2, i32 -2, i32 3, i32 3>, %a0
%2 = and <4 x i32> <i32 -1, i32 -1, i32 1, i32 1>, %a1 %2 = and <4 x i32> <i32 -1, i32 -1, i32 1, i32 1>, %a1
%3 = and <4 x i32> %1, %2 %3 = and <4 x i32> %1, %2
ret <4 x i32> %3 ret <4 x i32> %3
} }
define <4 x i32> @or_4i32(<4 x i32> %a0, <4 x i32> %a1) { define <4 x i32> @or_4i32(<4 x i32> %a0, <4 x i32> %a1) {
; X86-LABEL: or_4i32: ; X86-LABEL: or_4i32:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: orps %xmm1, %xmm0 ; X86-NEXT: orps %xmm1, %xmm0
; X86-NEXT: orps {{\.LCPI.*}}, %xmm0 ; X86-NEXT: orps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: or_4i32: ; X64-LABEL: or_4i32:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: orps %xmm1, %xmm0 ; X64-NEXT: orps %xmm1, %xmm0
; X64-NEXT: orps {{.*}}(%rip), %xmm0 ; X64-NEXT: orps {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = or <4 x i32> %a0, <i32 -2, i32 -2, i32 3, i32 3> %1 = or <4 x i32> %a0, <i32 -2, i32 -2, i32 3, i32 3>
%2 = or <4 x i32> %a1, <i32 -1, i32 -1, i32 1, i32 1> %2 = or <4 x i32> %a1, <i32 -1, i32 -1, i32 1, i32 1>
%3 = or <4 x i32> %1, %2 %3 = or <4 x i32> %1, %2
ret <4 x i32> %3 ret <4 x i32> %3
} }
define <4 x i32> @or_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) { define <4 x i32> @or_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
; X86-LABEL: or_4i32_commute: ; X86-LABEL: or_4i32_commute:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: orps %xmm1, %xmm0 ; X86-NEXT: orps %xmm1, %xmm0
; X86-NEXT: orps {{\.LCPI.*}}, %xmm0 ; X86-NEXT: orps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: or_4i32_commute: ; X64-LABEL: or_4i32_commute:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: orps %xmm1, %xmm0 ; X64-NEXT: orps %xmm1, %xmm0
; X64-NEXT: orps {{.*}}(%rip), %xmm0 ; X64-NEXT: orps {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = or <4 x i32> <i32 -2, i32 -2, i32 3, i32 3>, %a0 %1 = or <4 x i32> <i32 -2, i32 -2, i32 3, i32 3>, %a0
%2 = or <4 x i32> <i32 -1, i32 -1, i32 1, i32 1>, %a1 %2 = or <4 x i32> <i32 -1, i32 -1, i32 1, i32 1>, %a1
%3 = or <4 x i32> %1, %2 %3 = or <4 x i32> %1, %2
ret <4 x i32> %3 ret <4 x i32> %3
} }
define <4 x i32> @xor_4i32(<4 x i32> %a0, <4 x i32> %a1) { define <4 x i32> @xor_4i32(<4 x i32> %a0, <4 x i32> %a1) {
; X86-LABEL: xor_4i32: ; X86-LABEL: xor_4i32:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: xorps %xmm1, %xmm0 ; X86-NEXT: xorps %xmm1, %xmm0
; X86-NEXT: xorps {{\.LCPI.*}}, %xmm0 ; X86-NEXT: xorps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: xor_4i32: ; X64-LABEL: xor_4i32:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: xorps %xmm1, %xmm0 ; X64-NEXT: xorps %xmm1, %xmm0
; X64-NEXT: xorps {{.*}}(%rip), %xmm0 ; X64-NEXT: xorps {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = xor <4 x i32> %a0, <i32 -2, i32 -2, i32 3, i32 3> %1 = xor <4 x i32> %a0, <i32 -2, i32 -2, i32 3, i32 3>
%2 = xor <4 x i32> %a1, <i32 -1, i32 -1, i32 1, i32 1> %2 = xor <4 x i32> %a1, <i32 -1, i32 -1, i32 1, i32 1>
%3 = xor <4 x i32> %1, %2 %3 = xor <4 x i32> %1, %2
ret <4 x i32> %3 ret <4 x i32> %3
} }
define <4 x i32> @xor_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) { define <4 x i32> @xor_4i32_commute(<4 x i32> %a0, <4 x i32> %a1) {
; X86-LABEL: xor_4i32_commute: ; X86-LABEL: xor_4i32_commute:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: xorps %xmm1, %xmm0 ; X86-NEXT: xorps %xmm1, %xmm0
; X86-NEXT: xorps {{\.LCPI.*}}, %xmm0 ; X86-NEXT: xorps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: xor_4i32_commute: ; X64-LABEL: xor_4i32_commute:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: xorps %xmm1, %xmm0 ; X64-NEXT: xorps %xmm1, %xmm0
; X64-NEXT: xorps {{.*}}(%rip), %xmm0 ; X64-NEXT: xorps {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = xor <4 x i32> <i32 -2, i32 -2, i32 3, i32 3>, %a0 %1 = xor <4 x i32> <i32 -2, i32 -2, i32 3, i32 3>, %a0
%2 = xor <4 x i32> <i32 -1, i32 -1, i32 1, i32 1>, %a1 %2 = xor <4 x i32> <i32 -1, i32 -1, i32 1, i32 1>, %a1
%3 = xor <4 x i32> %1, %2 %3 = xor <4 x i32> %1, %2
ret <4 x i32> %3 ret <4 x i32> %3
} }

llvm/test/CodeGen/X86/vec_shift4.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=X86 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=X64 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=X64
define <2 x i64> @shl1(<4 x i32> %r, <4 x i32> %a) nounwind readnone ssp { define <2 x i64> @shl1(<4 x i32> %r, <4 x i32> %a) nounwind readnone ssp {
; X86-LABEL: shl1: ; X86-LABEL: shl1:
; X86: # %bb.0: # %entry ; X86: # %bb.0: # %entry
; X86-NEXT: pslld $23, %xmm1 ; X86-NEXT: pslld $23, %xmm1
; X86-NEXT: paddd {{\.LCPI.*}}, %xmm1 ; X86-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-NEXT: cvttps2dq %xmm1, %xmm1 ; X86-NEXT: cvttps2dq %xmm1, %xmm1
; X86-NEXT: pmulld %xmm1, %xmm0 ; X86-NEXT: pmulld %xmm1, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: shl1: ; X64-LABEL: shl1:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: pslld $23, %xmm1 ; X64-NEXT: pslld $23, %xmm1
; X64-NEXT: paddd {{.*}}(%rip), %xmm1 ; X64-NEXT: paddd {{.*}}(%rip), %xmm1
; X64-NEXT: cvttps2dq %xmm1, %xmm1 ; X64-NEXT: cvttps2dq %xmm1, %xmm1
; X64-NEXT: pmulld %xmm1, %xmm0 ; X64-NEXT: pmulld %xmm1, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
entry: entry:
%shl = shl <4 x i32> %r, %a ; <<4 x i32>> [#uses=1] %shl = shl <4 x i32> %r, %a ; <<4 x i32>> [#uses=1]
%tmp2 = bitcast <4 x i32> %shl to <2 x i64> ; <<2 x i64>> [#uses=1] %tmp2 = bitcast <4 x i32> %shl to <2 x i64> ; <<2 x i64>> [#uses=1]
ret <2 x i64> %tmp2 ret <2 x i64> %tmp2
} }
define <2 x i64> @shl2(<16 x i8> %r, <16 x i8> %a) nounwind readnone ssp { define <2 x i64> @shl2(<16 x i8> %r, <16 x i8> %a) nounwind readnone ssp {
; X86-LABEL: shl2: ; X86-LABEL: shl2:
; X86: # %bb.0: # %entry ; X86: # %bb.0: # %entry
; X86-NEXT: movdqa %xmm0, %xmm2 ; X86-NEXT: movdqa %xmm0, %xmm2
; X86-NEXT: psllw $5, %xmm1 ; X86-NEXT: psllw $5, %xmm1
; X86-NEXT: movdqa %xmm0, %xmm3 ; X86-NEXT: movdqa %xmm0, %xmm3
; X86-NEXT: psllw $4, %xmm3 ; X86-NEXT: psllw $4, %xmm3
; X86-NEXT: pand {{\.LCPI.*}}, %xmm3 ; X86-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm3
; X86-NEXT: movdqa %xmm1, %xmm0 ; X86-NEXT: movdqa %xmm1, %xmm0
; X86-NEXT: pblendvb %xmm0, %xmm3, %xmm2 ; X86-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; X86-NEXT: movdqa %xmm2, %xmm3 ; X86-NEXT: movdqa %xmm2, %xmm3
; X86-NEXT: psllw $2, %xmm3 ; X86-NEXT: psllw $2, %xmm3
; X86-NEXT: pand {{\.LCPI.*}}, %xmm3 ; X86-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm3
; X86-NEXT: paddb %xmm1, %xmm1 ; X86-NEXT: paddb %xmm1, %xmm1
; X86-NEXT: movdqa %xmm1, %xmm0 ; X86-NEXT: movdqa %xmm1, %xmm0
; X86-NEXT: pblendvb %xmm0, %xmm3, %xmm2 ; X86-NEXT: pblendvb %xmm0, %xmm3, %xmm2
; X86-NEXT: movdqa %xmm2, %xmm3 ; X86-NEXT: movdqa %xmm2, %xmm3
; X86-NEXT: paddb %xmm2, %xmm3 ; X86-NEXT: paddb %xmm2, %xmm3
; X86-NEXT: paddb %xmm1, %xmm1 ; X86-NEXT: paddb %xmm1, %xmm1
; X86-NEXT: movdqa %xmm1, %xmm0 ; X86-NEXT: movdqa %xmm1, %xmm0
; X86-NEXT: pblendvb %xmm0, %xmm3, %xmm2 ; X86-NEXT: pblendvb %xmm0, %xmm3, %xmm2
Show All 30 Lines

llvm/test/CodeGen/X86/vector-fshl-128.ll

Show First 20 Lines • Show All 400 Lines • ▼ Show 20 Lines
; X86-SSE2-NEXT: movdqa %xmm1, %xmm7 ; X86-SSE2-NEXT: movdqa %xmm1, %xmm7
; X86-SSE2-NEXT: psrld %xmm6, %xmm7 ; X86-SSE2-NEXT: psrld %xmm6, %xmm7
; X86-SSE2-NEXT: pshuflw {{.*#+}} xmm5 = xmm5[0,1,1,1,4,5,6,7] ; X86-SSE2-NEXT: pshuflw {{.*#+}} xmm5 = xmm5[0,1,1,1,4,5,6,7]
; X86-SSE2-NEXT: psrld %xmm5, %xmm1 ; X86-SSE2-NEXT: psrld %xmm5, %xmm1
; X86-SSE2-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm7[1] ; X86-SSE2-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm7[1]
; X86-SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,3],xmm1[0,3] ; X86-SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,3],xmm1[0,3]
; X86-SSE2-NEXT: pand %xmm4, %xmm2 ; X86-SSE2-NEXT: pand %xmm4, %xmm2
; X86-SSE2-NEXT: pslld $23, %xmm2 ; X86-SSE2-NEXT: pslld $23, %xmm2
; X86-SSE2-NEXT: paddd {{\.LCPI.*}}, %xmm2 ; X86-SSE2-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: cvttps2dq %xmm2, %xmm1 ; X86-SSE2-NEXT: cvttps2dq %xmm2, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; X86-SSE2-NEXT: pmuludq %xmm1, %xmm0 ; X86-SSE2-NEXT: pmuludq %xmm1, %xmm0
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; X86-SSE2-NEXT: pmuludq %xmm2, %xmm1 ; X86-SSE2-NEXT: pmuludq %xmm2, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
▲ Show 20 Lines • Show All 280 Lines • ▼ Show 20 Lines
; X86-SSE2-NEXT: pand %xmm1, %xmm3 ; X86-SSE2-NEXT: pand %xmm1, %xmm3
; X86-SSE2-NEXT: por %xmm5, %xmm3 ; X86-SSE2-NEXT: por %xmm5, %xmm3
; X86-SSE2-NEXT: paddw %xmm4, %xmm4 ; X86-SSE2-NEXT: paddw %xmm4, %xmm4
; X86-SSE2-NEXT: psraw $15, %xmm4 ; X86-SSE2-NEXT: psraw $15, %xmm4
; X86-SSE2-NEXT: movdqa %xmm4, %xmm5 ; X86-SSE2-NEXT: movdqa %xmm4, %xmm5
; X86-SSE2-NEXT: pandn %xmm3, %xmm5 ; X86-SSE2-NEXT: pandn %xmm3, %xmm5
; X86-SSE2-NEXT: psrlw $1, %xmm3 ; X86-SSE2-NEXT: psrlw $1, %xmm3
; X86-SSE2-NEXT: pand %xmm4, %xmm3 ; X86-SSE2-NEXT: pand %xmm4, %xmm3
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm2 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: movdqa %xmm2, %xmm1 ; X86-SSE2-NEXT: movdqa %xmm2, %xmm1
; X86-SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7] ; X86-SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
; X86-SSE2-NEXT: pslld $23, %xmm1 ; X86-SSE2-NEXT: pslld $23, %xmm1
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm4 = [1065353216,1065353216,1065353216,1065353216] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm4 = [1065353216,1065353216,1065353216,1065353216]
; X86-SSE2-NEXT: paddd %xmm4, %xmm1 ; X86-SSE2-NEXT: paddd %xmm4, %xmm1
; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1 ; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; X86-SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7] ; X86-SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7]
; X86-SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,6,6,7] ; X86-SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,6,6,7]
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; X86-SSE2-NEXT: pandn %xmm4, %xmm6 ; X86-SSE2-NEXT: pandn %xmm4, %xmm6
; X86-SSE2-NEXT: psllw $5, %xmm6 ; X86-SSE2-NEXT: psllw $5, %xmm6
; X86-SSE2-NEXT: pxor %xmm3, %xmm3 ; X86-SSE2-NEXT: pxor %xmm3, %xmm3
; X86-SSE2-NEXT: pcmpgtb %xmm6, %xmm3 ; X86-SSE2-NEXT: pcmpgtb %xmm6, %xmm3
; X86-SSE2-NEXT: movdqa %xmm3, %xmm7 ; X86-SSE2-NEXT: movdqa %xmm3, %xmm7
; X86-SSE2-NEXT: pandn %xmm1, %xmm7 ; X86-SSE2-NEXT: pandn %xmm1, %xmm7
; X86-SSE2-NEXT: psrlw $4, %xmm1 ; X86-SSE2-NEXT: psrlw $4, %xmm1
; X86-SSE2-NEXT: pand %xmm3, %xmm1 ; X86-SSE2-NEXT: pand %xmm3, %xmm1
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: por %xmm7, %xmm1 ; X86-SSE2-NEXT: por %xmm7, %xmm1
; X86-SSE2-NEXT: paddb %xmm6, %xmm6 ; X86-SSE2-NEXT: paddb %xmm6, %xmm6
; X86-SSE2-NEXT: pxor %xmm3, %xmm3 ; X86-SSE2-NEXT: pxor %xmm3, %xmm3
; X86-SSE2-NEXT: pcmpgtb %xmm6, %xmm3 ; X86-SSE2-NEXT: pcmpgtb %xmm6, %xmm3
; X86-SSE2-NEXT: movdqa %xmm3, %xmm7 ; X86-SSE2-NEXT: movdqa %xmm3, %xmm7
; X86-SSE2-NEXT: pandn %xmm1, %xmm7 ; X86-SSE2-NEXT: pandn %xmm1, %xmm7
; X86-SSE2-NEXT: psrlw $2, %xmm1 ; X86-SSE2-NEXT: psrlw $2, %xmm1
; X86-SSE2-NEXT: pand %xmm3, %xmm1 ; X86-SSE2-NEXT: pand %xmm3, %xmm1
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: por %xmm7, %xmm1 ; X86-SSE2-NEXT: por %xmm7, %xmm1
; X86-SSE2-NEXT: paddb %xmm6, %xmm6 ; X86-SSE2-NEXT: paddb %xmm6, %xmm6
; X86-SSE2-NEXT: pxor %xmm3, %xmm3 ; X86-SSE2-NEXT: pxor %xmm3, %xmm3
; X86-SSE2-NEXT: pcmpgtb %xmm6, %xmm3 ; X86-SSE2-NEXT: pcmpgtb %xmm6, %xmm3
; X86-SSE2-NEXT: movdqa %xmm3, %xmm6 ; X86-SSE2-NEXT: movdqa %xmm3, %xmm6
; X86-SSE2-NEXT: pand %xmm5, %xmm3 ; X86-SSE2-NEXT: pand %xmm5, %xmm3
; X86-SSE2-NEXT: pandn %xmm1, %xmm6 ; X86-SSE2-NEXT: pandn %xmm1, %xmm6
; X86-SSE2-NEXT: psrlw $1, %xmm1 ; X86-SSE2-NEXT: psrlw $1, %xmm1
; X86-SSE2-NEXT: pand %xmm1, %xmm3 ; X86-SSE2-NEXT: pand %xmm1, %xmm3
; X86-SSE2-NEXT: por %xmm6, %xmm3 ; X86-SSE2-NEXT: por %xmm6, %xmm3
; X86-SSE2-NEXT: pand %xmm4, %xmm2 ; X86-SSE2-NEXT: pand %xmm4, %xmm2
; X86-SSE2-NEXT: psllw $5, %xmm2 ; X86-SSE2-NEXT: psllw $5, %xmm2
; X86-SSE2-NEXT: pxor %xmm1, %xmm1 ; X86-SSE2-NEXT: pxor %xmm1, %xmm1
; X86-SSE2-NEXT: pcmpgtb %xmm2, %xmm1 ; X86-SSE2-NEXT: pcmpgtb %xmm2, %xmm1
; X86-SSE2-NEXT: movdqa %xmm1, %xmm4 ; X86-SSE2-NEXT: movdqa %xmm1, %xmm4
; X86-SSE2-NEXT: pandn %xmm0, %xmm4 ; X86-SSE2-NEXT: pandn %xmm0, %xmm4
; X86-SSE2-NEXT: psllw $4, %xmm0 ; X86-SSE2-NEXT: psllw $4, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0 ; X86-SSE2-NEXT: pand %xmm1, %xmm0
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: por %xmm4, %xmm0 ; X86-SSE2-NEXT: por %xmm4, %xmm0
; X86-SSE2-NEXT: paddb %xmm2, %xmm2 ; X86-SSE2-NEXT: paddb %xmm2, %xmm2
; X86-SSE2-NEXT: pxor %xmm1, %xmm1 ; X86-SSE2-NEXT: pxor %xmm1, %xmm1
; X86-SSE2-NEXT: pcmpgtb %xmm2, %xmm1 ; X86-SSE2-NEXT: pcmpgtb %xmm2, %xmm1
; X86-SSE2-NEXT: movdqa %xmm1, %xmm4 ; X86-SSE2-NEXT: movdqa %xmm1, %xmm4
; X86-SSE2-NEXT: pandn %xmm0, %xmm4 ; X86-SSE2-NEXT: pandn %xmm0, %xmm4
; X86-SSE2-NEXT: psllw $2, %xmm0 ; X86-SSE2-NEXT: psllw $2, %xmm0
; X86-SSE2-NEXT: pand %xmm1, %xmm0 ; X86-SSE2-NEXT: pand %xmm1, %xmm0
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: por %xmm4, %xmm0 ; X86-SSE2-NEXT: por %xmm4, %xmm0
; X86-SSE2-NEXT: pxor %xmm1, %xmm1 ; X86-SSE2-NEXT: pxor %xmm1, %xmm1
; X86-SSE2-NEXT: paddb %xmm2, %xmm2 ; X86-SSE2-NEXT: paddb %xmm2, %xmm2
; X86-SSE2-NEXT: pcmpgtb %xmm2, %xmm1 ; X86-SSE2-NEXT: pcmpgtb %xmm2, %xmm1
; X86-SSE2-NEXT: movdqa %xmm1, %xmm2 ; X86-SSE2-NEXT: movdqa %xmm1, %xmm2
; X86-SSE2-NEXT: pandn %xmm0, %xmm2 ; X86-SSE2-NEXT: pandn %xmm0, %xmm2
; X86-SSE2-NEXT: por %xmm3, %xmm2 ; X86-SSE2-NEXT: por %xmm3, %xmm2
; X86-SSE2-NEXT: paddb %xmm0, %xmm0 ; X86-SSE2-NEXT: paddb %xmm0, %xmm0
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; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X86-SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm6[0,0,0,0,4,5,6,7] ; X86-SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm6[0,0,0,0,4,5,6,7]
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,0,0,0] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,0,0,0]
; X86-SSE2-NEXT: pand %xmm4, %xmm0 ; X86-SSE2-NEXT: pand %xmm4, %xmm0
; X86-SSE2-NEXT: pandn %xmm3, %xmm2 ; X86-SSE2-NEXT: pandn %xmm3, %xmm2
; X86-SSE2-NEXT: pslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0] ; X86-SSE2-NEXT: pslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0]
; X86-SSE2-NEXT: psrldq {{.*#+}} xmm2 = xmm2[15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; X86-SSE2-NEXT: psrldq {{.*#+}} xmm2 = xmm2[15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; X86-SSE2-NEXT: psrlw $1, %xmm1 ; X86-SSE2-NEXT: psrlw $1, %xmm1
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: psrlw %xmm2, %xmm1 ; X86-SSE2-NEXT: psrlw %xmm2, %xmm1
; X86-SSE2-NEXT: psrlw %xmm2, %xmm5 ; X86-SSE2-NEXT: psrlw %xmm2, %xmm5
; X86-SSE2-NEXT: psrlw $8, %xmm5 ; X86-SSE2-NEXT: psrlw $8, %xmm5
; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X86-SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm5[0,0,0,0,4,5,6,7] ; X86-SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm5[0,0,0,0,4,5,6,7]
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,0,0,0] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,0,0,0]
; X86-SSE2-NEXT: pand %xmm1, %xmm2 ; X86-SSE2-NEXT: pand %xmm1, %xmm2
; X86-SSE2-NEXT: por %xmm2, %xmm0 ; X86-SSE2-NEXT: por %xmm2, %xmm0
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; XOP-NEXT: vpshlw {{.*}}(%rip), %xmm0, %xmm0 ; XOP-NEXT: vpshlw {{.*}}(%rip), %xmm0, %xmm0
; XOP-NEXT: vpsrlw $1, %xmm1, %xmm1 ; XOP-NEXT: vpsrlw $1, %xmm1, %xmm1
; XOP-NEXT: vpshlw {{.*}}(%rip), %xmm1, %xmm1 ; XOP-NEXT: vpshlw {{.*}}(%rip), %xmm1, %xmm1
; XOP-NEXT: vpor %xmm1, %xmm0, %xmm0 ; XOP-NEXT: vpor %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; X86-SSE2-LABEL: constant_funnnel_v8i16: ; X86-SSE2-LABEL: constant_funnnel_v8i16:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlw $1, %xmm1 ; X86-SSE2-NEXT: psrlw $1, %xmm1
; X86-SSE2-NEXT: pmulhuw {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pmulhuw {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: por %xmm1, %xmm0 ; X86-SSE2-NEXT: por %xmm1, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
%res = call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>) %res = call <8 x i16> @llvm.fshl.v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>)
ret <8 x i16> %res ret <8 x i16> %res
} }
define <16 x i8> @constant_funnnel_v16i8(<16 x i8> %x, <16 x i8> %y) nounwind { define <16 x i8> @constant_funnnel_v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {
; SSE2-LABEL: constant_funnnel_v16i8: ; SSE2-LABEL: constant_funnnel_v16i8:
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; XOP-NEXT: vpshlb {{.*}}(%rip), %xmm0, %xmm0 ; XOP-NEXT: vpshlb {{.*}}(%rip), %xmm0, %xmm0
; XOP-NEXT: vpor %xmm1, %xmm0, %xmm0 ; XOP-NEXT: vpor %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; X86-SSE2-LABEL: constant_funnnel_v16i8: ; X86-SSE2-LABEL: constant_funnnel_v16i8:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movdqa %xmm0, %xmm2 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm2
; X86-SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15] ; X86-SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; X86-SSE2-NEXT: pmullw {{\.LCPI.*}}, %xmm2 ; X86-SSE2-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [255,255,255,255,255,255,255,255] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [255,255,255,255,255,255,255,255]
; X86-SSE2-NEXT: pand %xmm3, %xmm2 ; X86-SSE2-NEXT: pand %xmm3, %xmm2
; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X86-SSE2-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pand %xmm3, %xmm0 ; X86-SSE2-NEXT: pand %xmm3, %xmm0
; X86-SSE2-NEXT: packuswb %xmm2, %xmm0 ; X86-SSE2-NEXT: packuswb %xmm2, %xmm0
; X86-SSE2-NEXT: psrlw $1, %xmm1 ; X86-SSE2-NEXT: psrlw $1, %xmm1
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pxor %xmm2, %xmm2 ; X86-SSE2-NEXT: pxor %xmm2, %xmm2
; X86-SSE2-NEXT: movdqa %xmm1, %xmm3 ; X86-SSE2-NEXT: movdqa %xmm1, %xmm3
; X86-SSE2-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm2[8],xmm3[9],xmm2[9],xmm3[10],xmm2[10],xmm3[11],xmm2[11],xmm3[12],xmm2[12],xmm3[13],xmm2[13],xmm3[14],xmm2[14],xmm3[15],xmm2[15] ; X86-SSE2-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm2[8],xmm3[9],xmm2[9],xmm3[10],xmm2[10],xmm3[11],xmm2[11],xmm3[12],xmm2[12],xmm3[13],xmm2[13],xmm3[14],xmm2[14],xmm3[15],xmm2[15]
; X86-SSE2-NEXT: pmullw {{\.LCPI.*}}, %xmm3 ; X86-SSE2-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm3
; X86-SSE2-NEXT: psrlw $8, %xmm3 ; X86-SSE2-NEXT: psrlw $8, %xmm3
; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7] ; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
; X86-SSE2-NEXT: pmullw {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: psrlw $8, %xmm1 ; X86-SSE2-NEXT: psrlw $8, %xmm1
; X86-SSE2-NEXT: packuswb %xmm3, %xmm1 ; X86-SSE2-NEXT: packuswb %xmm3, %xmm1
; X86-SSE2-NEXT: por %xmm1, %xmm0 ; X86-SSE2-NEXT: por %xmm1, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
%res = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1>) %res = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1>)
ret <16 x i8> %res ret <16 x i8> %res
} }
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; XOP-NEXT: vpshlb {{.*}}(%rip), %xmm1, %xmm1 ; XOP-NEXT: vpshlb {{.*}}(%rip), %xmm1, %xmm1
; XOP-NEXT: vpshlb {{.*}}(%rip), %xmm0, %xmm0 ; XOP-NEXT: vpshlb {{.*}}(%rip), %xmm0, %xmm0
; XOP-NEXT: vpor %xmm1, %xmm0, %xmm0 ; XOP-NEXT: vpor %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; X86-SSE2-LABEL: splatconstant_funnnel_v16i8: ; X86-SSE2-LABEL: splatconstant_funnnel_v16i8:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: psrlw $4, %xmm1 ; X86-SSE2-NEXT: psrlw $4, %xmm1
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: psllw $4, %xmm0 ; X86-SSE2-NEXT: psllw $4, %xmm0
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: por %xmm1, %xmm0 ; X86-SSE2-NEXT: por %xmm1, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
%res = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>) %res = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>)
ret <16 x i8> %res ret <16 x i8> %res
} }

llvm/test/CodeGen/X86/vector-fshl-rot-128.ll

Show First 20 Lines • Show All 276 Lines • ▼ Show 20 Lines
; ;
; XOP-LABEL: var_funnnel_v4i32: ; XOP-LABEL: var_funnnel_v4i32:
; XOP: # %bb.0: ; XOP: # %bb.0:
; XOP-NEXT: vprotd %xmm1, %xmm0, %xmm0 ; XOP-NEXT: vprotd %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; X86-SSE2-LABEL: var_funnnel_v4i32: ; X86-SSE2-LABEL: var_funnnel_v4i32:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pslld $23, %xmm1 ; X86-SSE2-NEXT: pslld $23, %xmm1
; X86-SSE2-NEXT: paddd {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1 ; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; X86-SSE2-NEXT: pmuludq %xmm1, %xmm0 ; X86-SSE2-NEXT: pmuludq %xmm1, %xmm0
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3]
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; X86-SSE2-NEXT: pmuludq %xmm2, %xmm1 ; X86-SSE2-NEXT: pmuludq %xmm2, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3]
; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1] ; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
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; ;
; XOP-LABEL: var_funnnel_v8i16: ; XOP-LABEL: var_funnnel_v8i16:
; XOP: # %bb.0: ; XOP: # %bb.0:
; XOP-NEXT: vprotw %xmm1, %xmm0, %xmm0 ; XOP-NEXT: vprotw %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; X86-SSE2-LABEL: var_funnnel_v8i16: ; X86-SSE2-LABEL: var_funnnel_v8i16:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: movdqa %xmm1, %xmm2 ; X86-SSE2-NEXT: movdqa %xmm1, %xmm2
; X86-SSE2-NEXT: punpckhwd {{.*#+}} xmm2 = xmm2[4,4,5,5,6,6,7,7] ; X86-SSE2-NEXT: punpckhwd {{.*#+}} xmm2 = xmm2[4,4,5,5,6,6,7,7]
; X86-SSE2-NEXT: pslld $23, %xmm2 ; X86-SSE2-NEXT: pslld $23, %xmm2
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [1065353216,1065353216,1065353216,1065353216] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [1065353216,1065353216,1065353216,1065353216]
; X86-SSE2-NEXT: paddd %xmm3, %xmm2 ; X86-SSE2-NEXT: paddd %xmm3, %xmm2
; X86-SSE2-NEXT: cvttps2dq %xmm2, %xmm2 ; X86-SSE2-NEXT: cvttps2dq %xmm2, %xmm2
; X86-SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,2,2,3,4,5,6,7] ; X86-SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,2,2,3,4,5,6,7]
; X86-SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,6,6,7] ; X86-SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,6,6,7]
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; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movdqa %xmm0, %xmm2 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm2
; X86-SSE2-NEXT: psllw $5, %xmm1 ; X86-SSE2-NEXT: psllw $5, %xmm1
; X86-SSE2-NEXT: pxor %xmm0, %xmm0 ; X86-SSE2-NEXT: pxor %xmm0, %xmm0
; X86-SSE2-NEXT: pxor %xmm3, %xmm3 ; X86-SSE2-NEXT: pxor %xmm3, %xmm3
; X86-SSE2-NEXT: pcmpgtb %xmm1, %xmm3 ; X86-SSE2-NEXT: pcmpgtb %xmm1, %xmm3
; X86-SSE2-NEXT: movdqa %xmm2, %xmm4 ; X86-SSE2-NEXT: movdqa %xmm2, %xmm4
; X86-SSE2-NEXT: psrlw $4, %xmm4 ; X86-SSE2-NEXT: psrlw $4, %xmm4
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm4 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm4
; X86-SSE2-NEXT: movdqa %xmm2, %xmm5 ; X86-SSE2-NEXT: movdqa %xmm2, %xmm5
; X86-SSE2-NEXT: psllw $4, %xmm5 ; X86-SSE2-NEXT: psllw $4, %xmm5
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm5 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm5
; X86-SSE2-NEXT: por %xmm4, %xmm5 ; X86-SSE2-NEXT: por %xmm4, %xmm5
; X86-SSE2-NEXT: pand %xmm3, %xmm5 ; X86-SSE2-NEXT: pand %xmm3, %xmm5
; X86-SSE2-NEXT: pandn %xmm2, %xmm3 ; X86-SSE2-NEXT: pandn %xmm2, %xmm3
; X86-SSE2-NEXT: por %xmm5, %xmm3 ; X86-SSE2-NEXT: por %xmm5, %xmm3
; X86-SSE2-NEXT: movdqa %xmm3, %xmm2 ; X86-SSE2-NEXT: movdqa %xmm3, %xmm2
; X86-SSE2-NEXT: psrlw $6, %xmm2 ; X86-SSE2-NEXT: psrlw $6, %xmm2
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm2 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: movdqa %xmm3, %xmm4 ; X86-SSE2-NEXT: movdqa %xmm3, %xmm4
; X86-SSE2-NEXT: psllw $2, %xmm4 ; X86-SSE2-NEXT: psllw $2, %xmm4
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm4 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm4
; X86-SSE2-NEXT: por %xmm2, %xmm4 ; X86-SSE2-NEXT: por %xmm2, %xmm4
; X86-SSE2-NEXT: paddb %xmm1, %xmm1 ; X86-SSE2-NEXT: paddb %xmm1, %xmm1
; X86-SSE2-NEXT: pxor %xmm2, %xmm2 ; X86-SSE2-NEXT: pxor %xmm2, %xmm2
; X86-SSE2-NEXT: pcmpgtb %xmm1, %xmm2 ; X86-SSE2-NEXT: pcmpgtb %xmm1, %xmm2
; X86-SSE2-NEXT: pand %xmm2, %xmm4 ; X86-SSE2-NEXT: pand %xmm2, %xmm4
; X86-SSE2-NEXT: pandn %xmm3, %xmm2 ; X86-SSE2-NEXT: pandn %xmm3, %xmm2
; X86-SSE2-NEXT: por %xmm4, %xmm2 ; X86-SSE2-NEXT: por %xmm4, %xmm2
; X86-SSE2-NEXT: movdqa %xmm2, %xmm3 ; X86-SSE2-NEXT: movdqa %xmm2, %xmm3
; X86-SSE2-NEXT: paddb %xmm2, %xmm3 ; X86-SSE2-NEXT: paddb %xmm2, %xmm3
; X86-SSE2-NEXT: movdqa %xmm2, %xmm4 ; X86-SSE2-NEXT: movdqa %xmm2, %xmm4
; X86-SSE2-NEXT: psrlw $7, %xmm4 ; X86-SSE2-NEXT: psrlw $7, %xmm4
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm4 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm4
; X86-SSE2-NEXT: por %xmm3, %xmm4 ; X86-SSE2-NEXT: por %xmm3, %xmm4
; X86-SSE2-NEXT: paddb %xmm1, %xmm1 ; X86-SSE2-NEXT: paddb %xmm1, %xmm1
; X86-SSE2-NEXT: pcmpgtb %xmm1, %xmm0 ; X86-SSE2-NEXT: pcmpgtb %xmm1, %xmm0
; X86-SSE2-NEXT: pand %xmm0, %xmm4 ; X86-SSE2-NEXT: pand %xmm0, %xmm4
; X86-SSE2-NEXT: pandn %xmm2, %xmm0 ; X86-SSE2-NEXT: pandn %xmm2, %xmm0
; X86-SSE2-NEXT: por %xmm4, %xmm0 ; X86-SSE2-NEXT: por %xmm4, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
%res = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %x, <16 x i8> %x, <16 x i8> %amt) %res = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %x, <16 x i8> %x, <16 x i8> %amt)
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; XOPAVX2-LABEL: splatvar_funnnel_v8i16: ; XOPAVX2-LABEL: splatvar_funnnel_v8i16:
; XOPAVX2: # %bb.0: ; XOPAVX2: # %bb.0:
; XOPAVX2-NEXT: vpbroadcastw %xmm1, %xmm1 ; XOPAVX2-NEXT: vpbroadcastw %xmm1, %xmm1
; XOPAVX2-NEXT: vprotw %xmm1, %xmm0, %xmm0 ; XOPAVX2-NEXT: vprotw %xmm1, %xmm0, %xmm0
; XOPAVX2-NEXT: retq ; XOPAVX2-NEXT: retq
; ;
; X86-SSE2-LABEL: splatvar_funnnel_v8i16: ; X86-SSE2-LABEL: splatvar_funnnel_v8i16:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [65535,0,0,0] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [65535,0,0,0]
; X86-SSE2-NEXT: pand %xmm1, %xmm2 ; X86-SSE2-NEXT: pand %xmm1, %xmm2
; X86-SSE2-NEXT: movdqa %xmm0, %xmm3 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm3
; X86-SSE2-NEXT: psllw %xmm2, %xmm3 ; X86-SSE2-NEXT: psllw %xmm2, %xmm3
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [16,16,16,16,16,16,16,16] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [16,16,16,16,16,16,16,16]
; X86-SSE2-NEXT: psubw %xmm1, %xmm2 ; X86-SSE2-NEXT: psubw %xmm1, %xmm2
; X86-SSE2-NEXT: pslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,1] ; X86-SSE2-NEXT: pslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,1]
; X86-SSE2-NEXT: psrldq {{.*#+}} xmm2 = xmm2[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; X86-SSE2-NEXT: psrldq {{.*#+}} xmm2 = xmm2[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
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; XOPAVX2-LABEL: splatvar_funnnel_v16i8: ; XOPAVX2-LABEL: splatvar_funnnel_v16i8:
; XOPAVX2: # %bb.0: ; XOPAVX2: # %bb.0:
; XOPAVX2-NEXT: vpbroadcastb %xmm1, %xmm1 ; XOPAVX2-NEXT: vpbroadcastb %xmm1, %xmm1
; XOPAVX2-NEXT: vprotb %xmm1, %xmm0, %xmm0 ; XOPAVX2-NEXT: vprotb %xmm1, %xmm0, %xmm0
; XOPAVX2-NEXT: retq ; XOPAVX2-NEXT: retq
; ;
; X86-SSE2-LABEL: splatvar_funnnel_v16i8: ; X86-SSE2-LABEL: splatvar_funnnel_v16i8:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]
; X86-SSE2-NEXT: psubb %xmm1, %xmm2 ; X86-SSE2-NEXT: psubb %xmm1, %xmm2
; X86-SSE2-NEXT: movdqa %xmm1, %xmm3 ; X86-SSE2-NEXT: movdqa %xmm1, %xmm3
; X86-SSE2-NEXT: pslldq {{.*#+}} xmm3 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm3[0] ; X86-SSE2-NEXT: pslldq {{.*#+}} xmm3 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm3[0]
; X86-SSE2-NEXT: psrldq {{.*#+}} xmm3 = xmm3[15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; X86-SSE2-NEXT: psrldq {{.*#+}} xmm3 = xmm3[15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; X86-SSE2-NEXT: movdqa %xmm0, %xmm1 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm1
; X86-SSE2-NEXT: psllw %xmm3, %xmm1 ; X86-SSE2-NEXT: psllw %xmm3, %xmm1
; X86-SSE2-NEXT: pcmpeqd %xmm4, %xmm4 ; X86-SSE2-NEXT: pcmpeqd %xmm4, %xmm4
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; XOP-NEXT: vprotb {{.*}}(%rip), %xmm0, %xmm0 ; XOP-NEXT: vprotb {{.*}}(%rip), %xmm0, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; X86-SSE2-LABEL: constant_funnnel_v16i8: ; X86-SSE2-LABEL: constant_funnnel_v16i8:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pxor %xmm1, %xmm1 ; X86-SSE2-NEXT: pxor %xmm1, %xmm1
; X86-SSE2-NEXT: movdqa %xmm0, %xmm2 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm2
; X86-SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15] ; X86-SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
; X86-SSE2-NEXT: pmullw {{\.LCPI.*}}, %xmm2 ; X86-SSE2-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: psrlw $8, %xmm2 ; X86-SSE2-NEXT: psrlw $8, %xmm2
; X86-SSE2-NEXT: movdqa %xmm0, %xmm3 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm3
; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3],xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7] ; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3],xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7]
; X86-SSE2-NEXT: pmullw {{\.LCPI.*}}, %xmm3 ; X86-SSE2-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm3
; X86-SSE2-NEXT: psrlw $8, %xmm3 ; X86-SSE2-NEXT: psrlw $8, %xmm3
; X86-SSE2-NEXT: packuswb %xmm2, %xmm3 ; X86-SSE2-NEXT: packuswb %xmm2, %xmm3
; X86-SSE2-NEXT: movdqa %xmm0, %xmm1 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm1
; X86-SSE2-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15] ; X86-SSE2-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; X86-SSE2-NEXT: pmullw {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
; X86-SSE2-NEXT: pand %xmm2, %xmm1 ; X86-SSE2-NEXT: pand %xmm2, %xmm1
; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X86-SSE2-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pand %xmm2, %xmm0 ; X86-SSE2-NEXT: pand %xmm2, %xmm0
; X86-SSE2-NEXT: packuswb %xmm1, %xmm0 ; X86-SSE2-NEXT: packuswb %xmm1, %xmm0
; X86-SSE2-NEXT: por %xmm3, %xmm0 ; X86-SSE2-NEXT: por %xmm3, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
%res = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %x, <16 x i8> %x, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1>) %res = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %x, <16 x i8> %x, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1>)
ret <16 x i8> %res ret <16 x i8> %res
} }
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; XOP: # %bb.0: ; XOP: # %bb.0:
; XOP-NEXT: vprotb $4, %xmm0, %xmm0 ; XOP-NEXT: vprotb $4, %xmm0, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; X86-SSE2-LABEL: splatconstant_funnnel_v16i8: ; X86-SSE2-LABEL: splatconstant_funnnel_v16i8:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movdqa %xmm0, %xmm1 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm1
; X86-SSE2-NEXT: psrlw $4, %xmm1 ; X86-SSE2-NEXT: psrlw $4, %xmm1
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: psllw $4, %xmm0 ; X86-SSE2-NEXT: psllw $4, %xmm0
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: por %xmm1, %xmm0 ; X86-SSE2-NEXT: por %xmm1, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
%res = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %x, <16 x i8> %x, <16 x i8> <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>) %res = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> %x, <16 x i8> %x, <16 x i8> <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>)
ret <16 x i8> %res ret <16 x i8> %res
} }

llvm/test/CodeGen/X86/vector-fshl-rot-sub128.ll

Show First 20 Lines • Show All 129 Lines • ▼ Show 20 Lines
; ;
; XOP-LABEL: var_funnnel_v2i32: ; XOP-LABEL: var_funnnel_v2i32:
; XOP: # %bb.0: ; XOP: # %bb.0:
; XOP-NEXT: vprotd %xmm1, %xmm0, %xmm0 ; XOP-NEXT: vprotd %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; X86-SSE2-LABEL: var_funnnel_v2i32: ; X86-SSE2-LABEL: var_funnnel_v2i32:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pslld $23, %xmm1 ; X86-SSE2-NEXT: pslld $23, %xmm1
; X86-SSE2-NEXT: paddd {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1 ; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; X86-SSE2-NEXT: pmuludq %xmm1, %xmm0 ; X86-SSE2-NEXT: pmuludq %xmm1, %xmm0
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3]
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; X86-SSE2-NEXT: pmuludq %xmm2, %xmm1 ; X86-SSE2-NEXT: pmuludq %xmm2, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3]
; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1] ; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
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; XOPAVX2: # %bb.0: ; XOPAVX2: # %bb.0:
; XOPAVX2-NEXT: vpbroadcastd %xmm1, %xmm1 ; XOPAVX2-NEXT: vpbroadcastd %xmm1, %xmm1
; XOPAVX2-NEXT: vprotd %xmm1, %xmm0, %xmm0 ; XOPAVX2-NEXT: vprotd %xmm1, %xmm0, %xmm0
; XOPAVX2-NEXT: retq ; XOPAVX2-NEXT: retq
; ;
; X86-SSE2-LABEL: splatvar_funnnel_v2i32: ; X86-SSE2-LABEL: splatvar_funnnel_v2i32:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pslld $23, %xmm1 ; X86-SSE2-NEXT: pslld $23, %xmm1
; X86-SSE2-NEXT: paddd {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1 ; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; X86-SSE2-NEXT: pmuludq %xmm1, %xmm0 ; X86-SSE2-NEXT: pmuludq %xmm1, %xmm0
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3]
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; X86-SSE2-NEXT: pmuludq %xmm2, %xmm1 ; X86-SSE2-NEXT: pmuludq %xmm2, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3]
; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1] ; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
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llvm/test/CodeGen/X86/vector-fshr-128.ll

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; X86-SSE2-NEXT: movdqa %xmm1, %xmm7 ; X86-SSE2-NEXT: movdqa %xmm1, %xmm7
; X86-SSE2-NEXT: psrld %xmm6, %xmm7 ; X86-SSE2-NEXT: psrld %xmm6, %xmm7
; X86-SSE2-NEXT: pshuflw {{.*#+}} xmm5 = xmm5[0,1,1,1,4,5,6,7] ; X86-SSE2-NEXT: pshuflw {{.*#+}} xmm5 = xmm5[0,1,1,1,4,5,6,7]
; X86-SSE2-NEXT: psrld %xmm5, %xmm1 ; X86-SSE2-NEXT: psrld %xmm5, %xmm1
; X86-SSE2-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm7[1] ; X86-SSE2-NEXT: punpckhqdq {{.*#+}} xmm1 = xmm1[1],xmm7[1]
; X86-SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,3],xmm1[0,3] ; X86-SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,3],xmm1[0,3]
; X86-SSE2-NEXT: pandn %xmm4, %xmm2 ; X86-SSE2-NEXT: pandn %xmm4, %xmm2
; X86-SSE2-NEXT: pslld $23, %xmm2 ; X86-SSE2-NEXT: pslld $23, %xmm2
; X86-SSE2-NEXT: paddd {{\.LCPI.*}}, %xmm2 ; X86-SSE2-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: cvttps2dq %xmm2, %xmm1 ; X86-SSE2-NEXT: cvttps2dq %xmm2, %xmm1
; X86-SSE2-NEXT: pslld $1, %xmm0 ; X86-SSE2-NEXT: pslld $1, %xmm0
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; X86-SSE2-NEXT: pmuludq %xmm1, %xmm0 ; X86-SSE2-NEXT: pmuludq %xmm1, %xmm0
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; X86-SSE2-NEXT: pmuludq %xmm2, %xmm1 ; X86-SSE2-NEXT: pmuludq %xmm2, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
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; X86-SSE2-NEXT: pand %xmm4, %xmm1 ; X86-SSE2-NEXT: pand %xmm4, %xmm1
; X86-SSE2-NEXT: por %xmm5, %xmm1 ; X86-SSE2-NEXT: por %xmm5, %xmm1
; X86-SSE2-NEXT: paddw %xmm3, %xmm3 ; X86-SSE2-NEXT: paddw %xmm3, %xmm3
; X86-SSE2-NEXT: psraw $15, %xmm3 ; X86-SSE2-NEXT: psraw $15, %xmm3
; X86-SSE2-NEXT: movdqa %xmm3, %xmm4 ; X86-SSE2-NEXT: movdqa %xmm3, %xmm4
; X86-SSE2-NEXT: pandn %xmm1, %xmm4 ; X86-SSE2-NEXT: pandn %xmm1, %xmm4
; X86-SSE2-NEXT: psrlw $1, %xmm1 ; X86-SSE2-NEXT: psrlw $1, %xmm1
; X86-SSE2-NEXT: pand %xmm3, %xmm1 ; X86-SSE2-NEXT: pand %xmm3, %xmm1
; X86-SSE2-NEXT: pandn {{\.LCPI.*}}, %xmm2 ; X86-SSE2-NEXT: pandn {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: movdqa %xmm2, %xmm3 ; X86-SSE2-NEXT: movdqa %xmm2, %xmm3
; X86-SSE2-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4,4,5,5,6,6,7,7] ; X86-SSE2-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4,4,5,5,6,6,7,7]
; X86-SSE2-NEXT: pslld $23, %xmm3 ; X86-SSE2-NEXT: pslld $23, %xmm3
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm5 = [1065353216,1065353216,1065353216,1065353216] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm5 = [1065353216,1065353216,1065353216,1065353216]
; X86-SSE2-NEXT: paddd %xmm5, %xmm3 ; X86-SSE2-NEXT: paddd %xmm5, %xmm3
; X86-SSE2-NEXT: cvttps2dq %xmm3, %xmm3 ; X86-SSE2-NEXT: cvttps2dq %xmm3, %xmm3
; X86-SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[0,2,2,3,4,5,6,7] ; X86-SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[0,2,2,3,4,5,6,7]
; X86-SSE2-NEXT: pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,4,6,6,7] ; X86-SSE2-NEXT: pshufhw {{.*#+}} xmm3 = xmm3[0,1,2,3,4,6,6,7]
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; X86-SSE2-NEXT: pxor %xmm3, %xmm3 ; X86-SSE2-NEXT: pxor %xmm3, %xmm3
; X86-SSE2-NEXT: pxor %xmm6, %xmm6 ; X86-SSE2-NEXT: pxor %xmm6, %xmm6
; X86-SSE2-NEXT: pcmpgtb %xmm4, %xmm6 ; X86-SSE2-NEXT: pcmpgtb %xmm4, %xmm6
; X86-SSE2-NEXT: paddb %xmm0, %xmm0 ; X86-SSE2-NEXT: paddb %xmm0, %xmm0
; X86-SSE2-NEXT: movdqa %xmm6, %xmm7 ; X86-SSE2-NEXT: movdqa %xmm6, %xmm7
; X86-SSE2-NEXT: pandn %xmm0, %xmm7 ; X86-SSE2-NEXT: pandn %xmm0, %xmm7
; X86-SSE2-NEXT: psllw $4, %xmm0 ; X86-SSE2-NEXT: psllw $4, %xmm0
; X86-SSE2-NEXT: pand %xmm6, %xmm0 ; X86-SSE2-NEXT: pand %xmm6, %xmm0
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: por %xmm7, %xmm0 ; X86-SSE2-NEXT: por %xmm7, %xmm0
; X86-SSE2-NEXT: paddb %xmm4, %xmm4 ; X86-SSE2-NEXT: paddb %xmm4, %xmm4
; X86-SSE2-NEXT: pxor %xmm6, %xmm6 ; X86-SSE2-NEXT: pxor %xmm6, %xmm6
; X86-SSE2-NEXT: pcmpgtb %xmm4, %xmm6 ; X86-SSE2-NEXT: pcmpgtb %xmm4, %xmm6
; X86-SSE2-NEXT: movdqa %xmm6, %xmm7 ; X86-SSE2-NEXT: movdqa %xmm6, %xmm7
; X86-SSE2-NEXT: pandn %xmm0, %xmm7 ; X86-SSE2-NEXT: pandn %xmm0, %xmm7
; X86-SSE2-NEXT: psllw $2, %xmm0 ; X86-SSE2-NEXT: psllw $2, %xmm0
; X86-SSE2-NEXT: pand %xmm6, %xmm0 ; X86-SSE2-NEXT: pand %xmm6, %xmm0
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: por %xmm7, %xmm0 ; X86-SSE2-NEXT: por %xmm7, %xmm0
; X86-SSE2-NEXT: paddb %xmm4, %xmm4 ; X86-SSE2-NEXT: paddb %xmm4, %xmm4
; X86-SSE2-NEXT: pxor %xmm6, %xmm6 ; X86-SSE2-NEXT: pxor %xmm6, %xmm6
; X86-SSE2-NEXT: pcmpgtb %xmm4, %xmm6 ; X86-SSE2-NEXT: pcmpgtb %xmm4, %xmm6
; X86-SSE2-NEXT: movdqa %xmm6, %xmm4 ; X86-SSE2-NEXT: movdqa %xmm6, %xmm4
; X86-SSE2-NEXT: pandn %xmm0, %xmm4 ; X86-SSE2-NEXT: pandn %xmm0, %xmm4
; X86-SSE2-NEXT: paddb %xmm0, %xmm0 ; X86-SSE2-NEXT: paddb %xmm0, %xmm0
; X86-SSE2-NEXT: pand %xmm6, %xmm0 ; X86-SSE2-NEXT: pand %xmm6, %xmm0
; X86-SSE2-NEXT: pand %xmm5, %xmm2 ; X86-SSE2-NEXT: pand %xmm5, %xmm2
; X86-SSE2-NEXT: psllw $5, %xmm2 ; X86-SSE2-NEXT: psllw $5, %xmm2
; X86-SSE2-NEXT: pxor %xmm5, %xmm5 ; X86-SSE2-NEXT: pxor %xmm5, %xmm5
; X86-SSE2-NEXT: pcmpgtb %xmm2, %xmm5 ; X86-SSE2-NEXT: pcmpgtb %xmm2, %xmm5
; X86-SSE2-NEXT: movdqa %xmm5, %xmm6 ; X86-SSE2-NEXT: movdqa %xmm5, %xmm6
; X86-SSE2-NEXT: pandn %xmm1, %xmm6 ; X86-SSE2-NEXT: pandn %xmm1, %xmm6
; X86-SSE2-NEXT: psrlw $4, %xmm1 ; X86-SSE2-NEXT: psrlw $4, %xmm1
; X86-SSE2-NEXT: pand %xmm5, %xmm1 ; X86-SSE2-NEXT: pand %xmm5, %xmm1
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: por %xmm6, %xmm1 ; X86-SSE2-NEXT: por %xmm6, %xmm1
; X86-SSE2-NEXT: paddb %xmm2, %xmm2 ; X86-SSE2-NEXT: paddb %xmm2, %xmm2
; X86-SSE2-NEXT: pxor %xmm5, %xmm5 ; X86-SSE2-NEXT: pxor %xmm5, %xmm5
; X86-SSE2-NEXT: pcmpgtb %xmm2, %xmm5 ; X86-SSE2-NEXT: pcmpgtb %xmm2, %xmm5
; X86-SSE2-NEXT: movdqa %xmm5, %xmm6 ; X86-SSE2-NEXT: movdqa %xmm5, %xmm6
; X86-SSE2-NEXT: pandn %xmm1, %xmm6 ; X86-SSE2-NEXT: pandn %xmm1, %xmm6
; X86-SSE2-NEXT: psrlw $2, %xmm1 ; X86-SSE2-NEXT: psrlw $2, %xmm1
; X86-SSE2-NEXT: pand %xmm5, %xmm1 ; X86-SSE2-NEXT: pand %xmm5, %xmm1
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: por %xmm6, %xmm1 ; X86-SSE2-NEXT: por %xmm6, %xmm1
; X86-SSE2-NEXT: paddb %xmm2, %xmm2 ; X86-SSE2-NEXT: paddb %xmm2, %xmm2
; X86-SSE2-NEXT: pcmpgtb %xmm2, %xmm3 ; X86-SSE2-NEXT: pcmpgtb %xmm2, %xmm3
; X86-SSE2-NEXT: movdqa %xmm3, %xmm2 ; X86-SSE2-NEXT: movdqa %xmm3, %xmm2
; X86-SSE2-NEXT: pandn %xmm1, %xmm2 ; X86-SSE2-NEXT: pandn %xmm1, %xmm2
; X86-SSE2-NEXT: psrlw $1, %xmm1 ; X86-SSE2-NEXT: psrlw $1, %xmm1
; X86-SSE2-NEXT: pand %xmm3, %xmm1 ; X86-SSE2-NEXT: pand %xmm3, %xmm1
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: por %xmm2, %xmm1 ; X86-SSE2-NEXT: por %xmm2, %xmm1
; X86-SSE2-NEXT: por %xmm4, %xmm1 ; X86-SSE2-NEXT: por %xmm4, %xmm1
; X86-SSE2-NEXT: por %xmm1, %xmm0 ; X86-SSE2-NEXT: por %xmm1, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
%res = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %amt) %res = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %amt)
ret <16 x i8> %res ret <16 x i8> %res
} }
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; XOP-NEXT: vpor %xmm1, %xmm0, %xmm0 ; XOP-NEXT: vpor %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; X86-SSE2-LABEL: constant_funnnel_v8i16: ; X86-SSE2-LABEL: constant_funnnel_v8i16:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [0,65535,65535,65535,65535,65535,65535,65535] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [0,65535,65535,65535,65535,65535,65535,65535]
; X86-SSE2-NEXT: movdqa %xmm2, %xmm3 ; X86-SSE2-NEXT: movdqa %xmm2, %xmm3
; X86-SSE2-NEXT: pandn %xmm1, %xmm3 ; X86-SSE2-NEXT: pandn %xmm1, %xmm3
; X86-SSE2-NEXT: pmulhuw {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pmulhuw {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pand %xmm1, %xmm2 ; X86-SSE2-NEXT: pand %xmm1, %xmm2
; X86-SSE2-NEXT: psllw $1, %xmm0 ; X86-SSE2-NEXT: psllw $1, %xmm0
; X86-SSE2-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: por %xmm3, %xmm0 ; X86-SSE2-NEXT: por %xmm3, %xmm0
; X86-SSE2-NEXT: por %xmm2, %xmm0 ; X86-SSE2-NEXT: por %xmm2, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
%res = call <8 x i16> @llvm.fshr.v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>) %res = call <8 x i16> @llvm.fshr.v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>)
ret <8 x i16> %res ret <8 x i16> %res
} }
define <16 x i8> @constant_funnnel_v16i8(<16 x i8> %x, <16 x i8> %y) nounwind { define <16 x i8> @constant_funnnel_v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {
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; XOP-NEXT: vpor %xmm1, %xmm0, %xmm0 ; XOP-NEXT: vpor %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; X86-SSE2-LABEL: constant_funnnel_v16i8: ; X86-SSE2-LABEL: constant_funnnel_v16i8:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pxor %xmm2, %xmm2 ; X86-SSE2-NEXT: pxor %xmm2, %xmm2
; X86-SSE2-NEXT: movdqa %xmm1, %xmm3 ; X86-SSE2-NEXT: movdqa %xmm1, %xmm3
; X86-SSE2-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm2[8],xmm3[9],xmm2[9],xmm3[10],xmm2[10],xmm3[11],xmm2[11],xmm3[12],xmm2[12],xmm3[13],xmm2[13],xmm3[14],xmm2[14],xmm3[15],xmm2[15] ; X86-SSE2-NEXT: punpckhbw {{.*#+}} xmm3 = xmm3[8],xmm2[8],xmm3[9],xmm2[9],xmm3[10],xmm2[10],xmm3[11],xmm2[11],xmm3[12],xmm2[12],xmm3[13],xmm2[13],xmm3[14],xmm2[14],xmm3[15],xmm2[15]
; X86-SSE2-NEXT: pmullw {{\.LCPI.*}}, %xmm3 ; X86-SSE2-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm3
; X86-SSE2-NEXT: psrlw $8, %xmm3 ; X86-SSE2-NEXT: psrlw $8, %xmm3
; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7] ; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
; X86-SSE2-NEXT: pmullw {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: psrlw $8, %xmm1 ; X86-SSE2-NEXT: psrlw $8, %xmm1
; X86-SSE2-NEXT: packuswb %xmm3, %xmm1 ; X86-SSE2-NEXT: packuswb %xmm3, %xmm1
; X86-SSE2-NEXT: paddb %xmm0, %xmm0 ; X86-SSE2-NEXT: paddb %xmm0, %xmm0
; X86-SSE2-NEXT: movdqa %xmm0, %xmm2 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm2
; X86-SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15] ; X86-SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; X86-SSE2-NEXT: pmullw {{\.LCPI.*}}, %xmm2 ; X86-SSE2-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [255,255,255,255,255,255,255,255] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [255,255,255,255,255,255,255,255]
; X86-SSE2-NEXT: pand %xmm3, %xmm2 ; X86-SSE2-NEXT: pand %xmm3, %xmm2
; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X86-SSE2-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pand %xmm3, %xmm0 ; X86-SSE2-NEXT: pand %xmm3, %xmm0
; X86-SSE2-NEXT: packuswb %xmm2, %xmm0 ; X86-SSE2-NEXT: packuswb %xmm2, %xmm0
; X86-SSE2-NEXT: por %xmm1, %xmm0 ; X86-SSE2-NEXT: por %xmm1, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
%res = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1>) %res = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1>)
ret <16 x i8> %res ret <16 x i8> %res
} }
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; XOP-NEXT: vpshlb {{.*}}(%rip), %xmm1, %xmm1 ; XOP-NEXT: vpshlb {{.*}}(%rip), %xmm1, %xmm1
; XOP-NEXT: vpshlb {{.*}}(%rip), %xmm0, %xmm0 ; XOP-NEXT: vpshlb {{.*}}(%rip), %xmm0, %xmm0
; XOP-NEXT: vpor %xmm1, %xmm0, %xmm0 ; XOP-NEXT: vpor %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; X86-SSE2-LABEL: splatconstant_funnnel_v16i8: ; X86-SSE2-LABEL: splatconstant_funnnel_v16i8:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: psrlw $4, %xmm1 ; X86-SSE2-NEXT: psrlw $4, %xmm1
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: psllw $4, %xmm0 ; X86-SSE2-NEXT: psllw $4, %xmm0
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: por %xmm1, %xmm0 ; X86-SSE2-NEXT: por %xmm1, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
%res = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>) %res = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>)
ret <16 x i8> %res ret <16 x i8> %res
} }

llvm/test/CodeGen/X86/vector-fshr-rot-128.ll

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; XOP-NEXT: vpsubd %xmm1, %xmm2, %xmm1 ; XOP-NEXT: vpsubd %xmm1, %xmm2, %xmm1
; XOP-NEXT: vprotd %xmm1, %xmm0, %xmm0 ; XOP-NEXT: vprotd %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; X86-SSE2-LABEL: var_funnnel_v4i32: ; X86-SSE2-LABEL: var_funnnel_v4i32:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pxor %xmm2, %xmm2 ; X86-SSE2-NEXT: pxor %xmm2, %xmm2
; X86-SSE2-NEXT: psubd %xmm1, %xmm2 ; X86-SSE2-NEXT: psubd %xmm1, %xmm2
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm2 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: pslld $23, %xmm2 ; X86-SSE2-NEXT: pslld $23, %xmm2
; X86-SSE2-NEXT: paddd {{\.LCPI.*}}, %xmm2 ; X86-SSE2-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: cvttps2dq %xmm2, %xmm1 ; X86-SSE2-NEXT: cvttps2dq %xmm2, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; X86-SSE2-NEXT: pmuludq %xmm1, %xmm0 ; X86-SSE2-NEXT: pmuludq %xmm1, %xmm0
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3]
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; X86-SSE2-NEXT: pmuludq %xmm2, %xmm1 ; X86-SSE2-NEXT: pmuludq %xmm2, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3]
; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1] ; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
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; XOP-NEXT: vpsubw %xmm1, %xmm2, %xmm1 ; XOP-NEXT: vpsubw %xmm1, %xmm2, %xmm1
; XOP-NEXT: vprotw %xmm1, %xmm0, %xmm0 ; XOP-NEXT: vprotw %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; X86-SSE2-LABEL: var_funnnel_v8i16: ; X86-SSE2-LABEL: var_funnnel_v8i16:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pxor %xmm2, %xmm2 ; X86-SSE2-NEXT: pxor %xmm2, %xmm2
; X86-SSE2-NEXT: psubw %xmm1, %xmm2 ; X86-SSE2-NEXT: psubw %xmm1, %xmm2
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm2 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: movdqa %xmm2, %xmm1 ; X86-SSE2-NEXT: movdqa %xmm2, %xmm1
; X86-SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7] ; X86-SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]
; X86-SSE2-NEXT: pslld $23, %xmm1 ; X86-SSE2-NEXT: pslld $23, %xmm1
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [1065353216,1065353216,1065353216,1065353216] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [1065353216,1065353216,1065353216,1065353216]
; X86-SSE2-NEXT: paddd %xmm3, %xmm1 ; X86-SSE2-NEXT: paddd %xmm3, %xmm1
; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1 ; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; X86-SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7] ; X86-SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7]
; X86-SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,6,6,7] ; X86-SSE2-NEXT: pshufhw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,6,6,7]
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; X86-SSE2-NEXT: pxor %xmm0, %xmm0 ; X86-SSE2-NEXT: pxor %xmm0, %xmm0
; X86-SSE2-NEXT: pxor %xmm3, %xmm3 ; X86-SSE2-NEXT: pxor %xmm3, %xmm3
; X86-SSE2-NEXT: psubb %xmm1, %xmm3 ; X86-SSE2-NEXT: psubb %xmm1, %xmm3
; X86-SSE2-NEXT: psllw $5, %xmm3 ; X86-SSE2-NEXT: psllw $5, %xmm3
; X86-SSE2-NEXT: pxor %xmm1, %xmm1 ; X86-SSE2-NEXT: pxor %xmm1, %xmm1
; X86-SSE2-NEXT: pcmpgtb %xmm3, %xmm1 ; X86-SSE2-NEXT: pcmpgtb %xmm3, %xmm1
; X86-SSE2-NEXT: movdqa %xmm2, %xmm4 ; X86-SSE2-NEXT: movdqa %xmm2, %xmm4
; X86-SSE2-NEXT: psrlw $4, %xmm4 ; X86-SSE2-NEXT: psrlw $4, %xmm4
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm4 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm4
; X86-SSE2-NEXT: movdqa %xmm2, %xmm5 ; X86-SSE2-NEXT: movdqa %xmm2, %xmm5
; X86-SSE2-NEXT: psllw $4, %xmm5 ; X86-SSE2-NEXT: psllw $4, %xmm5
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm5 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm5
; X86-SSE2-NEXT: por %xmm4, %xmm5 ; X86-SSE2-NEXT: por %xmm4, %xmm5
; X86-SSE2-NEXT: pand %xmm1, %xmm5 ; X86-SSE2-NEXT: pand %xmm1, %xmm5
; X86-SSE2-NEXT: pandn %xmm2, %xmm1 ; X86-SSE2-NEXT: pandn %xmm2, %xmm1
; X86-SSE2-NEXT: por %xmm5, %xmm1 ; X86-SSE2-NEXT: por %xmm5, %xmm1
; X86-SSE2-NEXT: movdqa %xmm1, %xmm2 ; X86-SSE2-NEXT: movdqa %xmm1, %xmm2
; X86-SSE2-NEXT: psrlw $6, %xmm2 ; X86-SSE2-NEXT: psrlw $6, %xmm2
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm2 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: movdqa %xmm1, %xmm4 ; X86-SSE2-NEXT: movdqa %xmm1, %xmm4
; X86-SSE2-NEXT: psllw $2, %xmm4 ; X86-SSE2-NEXT: psllw $2, %xmm4
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm4 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm4
; X86-SSE2-NEXT: por %xmm2, %xmm4 ; X86-SSE2-NEXT: por %xmm2, %xmm4
; X86-SSE2-NEXT: paddb %xmm3, %xmm3 ; X86-SSE2-NEXT: paddb %xmm3, %xmm3
; X86-SSE2-NEXT: pxor %xmm2, %xmm2 ; X86-SSE2-NEXT: pxor %xmm2, %xmm2
; X86-SSE2-NEXT: pcmpgtb %xmm3, %xmm2 ; X86-SSE2-NEXT: pcmpgtb %xmm3, %xmm2
; X86-SSE2-NEXT: pand %xmm2, %xmm4 ; X86-SSE2-NEXT: pand %xmm2, %xmm4
; X86-SSE2-NEXT: pandn %xmm1, %xmm2 ; X86-SSE2-NEXT: pandn %xmm1, %xmm2
; X86-SSE2-NEXT: por %xmm4, %xmm2 ; X86-SSE2-NEXT: por %xmm4, %xmm2
; X86-SSE2-NEXT: movdqa %xmm2, %xmm1 ; X86-SSE2-NEXT: movdqa %xmm2, %xmm1
; X86-SSE2-NEXT: paddb %xmm2, %xmm1 ; X86-SSE2-NEXT: paddb %xmm2, %xmm1
; X86-SSE2-NEXT: movdqa %xmm2, %xmm4 ; X86-SSE2-NEXT: movdqa %xmm2, %xmm4
; X86-SSE2-NEXT: psrlw $7, %xmm4 ; X86-SSE2-NEXT: psrlw $7, %xmm4
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm4 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm4
; X86-SSE2-NEXT: por %xmm1, %xmm4 ; X86-SSE2-NEXT: por %xmm1, %xmm4
; X86-SSE2-NEXT: paddb %xmm3, %xmm3 ; X86-SSE2-NEXT: paddb %xmm3, %xmm3
; X86-SSE2-NEXT: pcmpgtb %xmm3, %xmm0 ; X86-SSE2-NEXT: pcmpgtb %xmm3, %xmm0
; X86-SSE2-NEXT: pand %xmm0, %xmm4 ; X86-SSE2-NEXT: pand %xmm0, %xmm4
; X86-SSE2-NEXT: pandn %xmm2, %xmm0 ; X86-SSE2-NEXT: pandn %xmm2, %xmm0
; X86-SSE2-NEXT: por %xmm4, %xmm0 ; X86-SSE2-NEXT: por %xmm4, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
%res = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %x, <16 x i8> %x, <16 x i8> %amt) %res = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %x, <16 x i8> %x, <16 x i8> %amt)
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; XOPAVX2-NEXT: vpsubw %xmm1, %xmm2, %xmm1 ; XOPAVX2-NEXT: vpsubw %xmm1, %xmm2, %xmm1
; XOPAVX2-NEXT: vprotw %xmm1, %xmm0, %xmm0 ; XOPAVX2-NEXT: vprotw %xmm1, %xmm0, %xmm0
; XOPAVX2-NEXT: retq ; XOPAVX2-NEXT: retq
; ;
; X86-SSE2-LABEL: splatvar_funnnel_v8i16: ; X86-SSE2-LABEL: splatvar_funnnel_v8i16:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pxor %xmm2, %xmm2 ; X86-SSE2-NEXT: pxor %xmm2, %xmm2
; X86-SSE2-NEXT: psubw %xmm1, %xmm2 ; X86-SSE2-NEXT: psubw %xmm1, %xmm2
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm2 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,0,0,0] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,0,0,0]
; X86-SSE2-NEXT: pand %xmm2, %xmm1 ; X86-SSE2-NEXT: pand %xmm2, %xmm1
; X86-SSE2-NEXT: movdqa %xmm0, %xmm3 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm3
; X86-SSE2-NEXT: psllw %xmm1, %xmm3 ; X86-SSE2-NEXT: psllw %xmm1, %xmm3
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16]
; X86-SSE2-NEXT: psubw %xmm2, %xmm1 ; X86-SSE2-NEXT: psubw %xmm2, %xmm1
; X86-SSE2-NEXT: pslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1] ; X86-SSE2-NEXT: pslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1]
; X86-SSE2-NEXT: psrldq {{.*#+}} xmm1 = xmm1[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; X86-SSE2-NEXT: psrldq {{.*#+}} xmm1 = xmm1[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
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; XOPAVX2-NEXT: vpsubb %xmm1, %xmm2, %xmm1 ; XOPAVX2-NEXT: vpsubb %xmm1, %xmm2, %xmm1
; XOPAVX2-NEXT: vprotb %xmm1, %xmm0, %xmm0 ; XOPAVX2-NEXT: vprotb %xmm1, %xmm0, %xmm0
; XOPAVX2-NEXT: retq ; XOPAVX2-NEXT: retq
; ;
; X86-SSE2-LABEL: splatvar_funnnel_v16i8: ; X86-SSE2-LABEL: splatvar_funnnel_v16i8:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pxor %xmm2, %xmm2 ; X86-SSE2-NEXT: pxor %xmm2, %xmm2
; X86-SSE2-NEXT: psubb %xmm1, %xmm2 ; X86-SSE2-NEXT: psubb %xmm1, %xmm2
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm2 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]
; X86-SSE2-NEXT: psubb %xmm2, %xmm3 ; X86-SSE2-NEXT: psubb %xmm2, %xmm3
; X86-SSE2-NEXT: pslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0] ; X86-SSE2-NEXT: pslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0]
; X86-SSE2-NEXT: psrldq {{.*#+}} xmm2 = xmm2[15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; X86-SSE2-NEXT: psrldq {{.*#+}} xmm2 = xmm2[15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; X86-SSE2-NEXT: movdqa %xmm0, %xmm1 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm1
; X86-SSE2-NEXT: psllw %xmm2, %xmm1 ; X86-SSE2-NEXT: psllw %xmm2, %xmm1
; X86-SSE2-NEXT: pcmpeqd %xmm4, %xmm4 ; X86-SSE2-NEXT: pcmpeqd %xmm4, %xmm4
; X86-SSE2-NEXT: pcmpeqd %xmm5, %xmm5 ; X86-SSE2-NEXT: pcmpeqd %xmm5, %xmm5
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; XOP-NEXT: vprotb {{.*}}(%rip), %xmm0, %xmm0 ; XOP-NEXT: vprotb {{.*}}(%rip), %xmm0, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; X86-SSE2-LABEL: constant_funnnel_v16i8: ; X86-SSE2-LABEL: constant_funnnel_v16i8:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pxor %xmm1, %xmm1 ; X86-SSE2-NEXT: pxor %xmm1, %xmm1
; X86-SSE2-NEXT: movdqa %xmm0, %xmm2 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm2
; X86-SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15] ; X86-SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
; X86-SSE2-NEXT: pmullw {{\.LCPI.*}}, %xmm2 ; X86-SSE2-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: psrlw $8, %xmm2 ; X86-SSE2-NEXT: psrlw $8, %xmm2
; X86-SSE2-NEXT: movdqa %xmm0, %xmm3 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm3
; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3],xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7] ; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3],xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7]
; X86-SSE2-NEXT: pmullw {{\.LCPI.*}}, %xmm3 ; X86-SSE2-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm3
; X86-SSE2-NEXT: psrlw $8, %xmm3 ; X86-SSE2-NEXT: psrlw $8, %xmm3
; X86-SSE2-NEXT: packuswb %xmm2, %xmm3 ; X86-SSE2-NEXT: packuswb %xmm2, %xmm3
; X86-SSE2-NEXT: movdqa %xmm0, %xmm1 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm1
; X86-SSE2-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15] ; X86-SSE2-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; X86-SSE2-NEXT: pmullw {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
; X86-SSE2-NEXT: pand %xmm2, %xmm1 ; X86-SSE2-NEXT: pand %xmm2, %xmm1
; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X86-SSE2-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pand %xmm2, %xmm0 ; X86-SSE2-NEXT: pand %xmm2, %xmm0
; X86-SSE2-NEXT: packuswb %xmm1, %xmm0 ; X86-SSE2-NEXT: packuswb %xmm1, %xmm0
; X86-SSE2-NEXT: por %xmm3, %xmm0 ; X86-SSE2-NEXT: por %xmm3, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
%res = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %x, <16 x i8> %x, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1>) %res = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %x, <16 x i8> %x, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1>)
ret <16 x i8> %res ret <16 x i8> %res
} }
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; XOP: # %bb.0: ; XOP: # %bb.0:
; XOP-NEXT: vprotb $4, %xmm0, %xmm0 ; XOP-NEXT: vprotb $4, %xmm0, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; X86-SSE2-LABEL: splatconstant_funnnel_v16i8: ; X86-SSE2-LABEL: splatconstant_funnnel_v16i8:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movdqa %xmm0, %xmm1 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm1
; X86-SSE2-NEXT: psrlw $4, %xmm1 ; X86-SSE2-NEXT: psrlw $4, %xmm1
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: psllw $4, %xmm0 ; X86-SSE2-NEXT: psllw $4, %xmm0
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: por %xmm1, %xmm0 ; X86-SSE2-NEXT: por %xmm1, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
%res = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %x, <16 x i8> %x, <16 x i8> <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>) %res = call <16 x i8> @llvm.fshr.v16i8(<16 x i8> %x, <16 x i8> %x, <16 x i8> <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>)
ret <16 x i8> %res ret <16 x i8> %res
} }

llvm/test/CodeGen/X86/vector-fshr-rot-sub128.ll

Show First 20 Lines • Show All 141 Lines • ▼ Show 20 Lines
; XOP-NEXT: vpsubd %xmm1, %xmm2, %xmm1 ; XOP-NEXT: vpsubd %xmm1, %xmm2, %xmm1
; XOP-NEXT: vprotd %xmm1, %xmm0, %xmm0 ; XOP-NEXT: vprotd %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; X86-SSE2-LABEL: var_funnnel_v2i32: ; X86-SSE2-LABEL: var_funnnel_v2i32:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pxor %xmm2, %xmm2 ; X86-SSE2-NEXT: pxor %xmm2, %xmm2
; X86-SSE2-NEXT: psubd %xmm1, %xmm2 ; X86-SSE2-NEXT: psubd %xmm1, %xmm2
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm2 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: pslld $23, %xmm2 ; X86-SSE2-NEXT: pslld $23, %xmm2
; X86-SSE2-NEXT: paddd {{\.LCPI.*}}, %xmm2 ; X86-SSE2-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: cvttps2dq %xmm2, %xmm1 ; X86-SSE2-NEXT: cvttps2dq %xmm2, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; X86-SSE2-NEXT: pmuludq %xmm1, %xmm0 ; X86-SSE2-NEXT: pmuludq %xmm1, %xmm0
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3]
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; X86-SSE2-NEXT: pmuludq %xmm2, %xmm1 ; X86-SSE2-NEXT: pmuludq %xmm2, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3]
; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1] ; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
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; XOPAVX2-NEXT: vprotd %xmm1, %xmm0, %xmm0 ; XOPAVX2-NEXT: vprotd %xmm1, %xmm0, %xmm0
; XOPAVX2-NEXT: retq ; XOPAVX2-NEXT: retq
; ;
; X86-SSE2-LABEL: splatvar_funnnel_v2i32: ; X86-SSE2-LABEL: splatvar_funnnel_v2i32:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,1,1]
; X86-SSE2-NEXT: pxor %xmm2, %xmm2 ; X86-SSE2-NEXT: pxor %xmm2, %xmm2
; X86-SSE2-NEXT: psubd %xmm1, %xmm2 ; X86-SSE2-NEXT: psubd %xmm1, %xmm2
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm2 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: pslld $23, %xmm2 ; X86-SSE2-NEXT: pslld $23, %xmm2
; X86-SSE2-NEXT: paddd {{\.LCPI.*}}, %xmm2 ; X86-SSE2-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: cvttps2dq %xmm2, %xmm1 ; X86-SSE2-NEXT: cvttps2dq %xmm2, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; X86-SSE2-NEXT: pmuludq %xmm1, %xmm0 ; X86-SSE2-NEXT: pmuludq %xmm1, %xmm0
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3]
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; X86-SSE2-NEXT: pmuludq %xmm2, %xmm1 ; X86-SSE2-NEXT: pmuludq %xmm2, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3]
; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1] ; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
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llvm/test/CodeGen/X86/vector-gep.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-linux -mcpu=corei7-avx | FileCheck %s ; RUN: llc < %s -mtriple=i686-linux -mcpu=corei7-avx | FileCheck %s
; RUN: opt -instsimplify -disable-output < %s ; RUN: opt -instsimplify -disable-output < %s
define <4 x i32*> @AGEP0(i32* %ptr) nounwind { define <4 x i32*> @AGEP0(i32* %ptr) nounwind {
; CHECK-LABEL: AGEP0: ; CHECK-LABEL: AGEP0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vbroadcastss {{[0-9]+}}(%esp), %xmm0 ; CHECK-NEXT: vbroadcastss {{[0-9]+}}(%esp), %xmm0
; CHECK-NEXT: vpaddd {{\.LCPI.*}}, %xmm0, %xmm0 ; CHECK-NEXT: vpaddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; CHECK-NEXT: retl ; CHECK-NEXT: retl
%vecinit.i = insertelement <4 x i32*> undef, i32* %ptr, i32 0 %vecinit.i = insertelement <4 x i32*> undef, i32* %ptr, i32 0
%vecinit2.i = insertelement <4 x i32*> %vecinit.i, i32* %ptr, i32 1 %vecinit2.i = insertelement <4 x i32*> %vecinit.i, i32* %ptr, i32 1
%vecinit4.i = insertelement <4 x i32*> %vecinit2.i, i32* %ptr, i32 2 %vecinit4.i = insertelement <4 x i32*> %vecinit2.i, i32* %ptr, i32 2
%vecinit6.i = insertelement <4 x i32*> %vecinit4.i, i32* %ptr, i32 3 %vecinit6.i = insertelement <4 x i32*> %vecinit4.i, i32* %ptr, i32 3
%A2 = getelementptr i32, <4 x i32*> %vecinit6.i, <4 x i32> <i32 1, i32 2, i32 3, i32 4> %A2 = getelementptr i32, <4 x i32*> %vecinit6.i, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
%A3 = getelementptr i32, <4 x i32*> %A2, <4 x i32> <i32 10, i32 14, i32 19, i32 233> %A3 = getelementptr i32, <4 x i32*> %A2, <4 x i32> <i32 10, i32 14, i32 19, i32 233>
ret <4 x i32*> %A3 ret <4 x i32*> %A3
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llvm/test/CodeGen/X86/vector-idiv-v2i32.ll

Show First 20 Lines • Show All 253 Lines • ▼ Show 20 Lines
; X64-NEXT: movq %rax, (%rsi) ; X64-NEXT: movq %rax, (%rsi)
; X64-NEXT: retq ; X64-NEXT: retq
; ;
; X86-LABEL: test_urem_pow2_v2i32: ; X86-LABEL: test_urem_pow2_v2i32:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; X86-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-NEXT: andps {{\.LCPI.*}}, %xmm0 ; X86-NEXT: andps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: movlps %xmm0, (%eax) ; X86-NEXT: movlps %xmm0, (%eax)
; X86-NEXT: retl ; X86-NEXT: retl
%a = load <2 x i32>, <2 x i32>* %x %a = load <2 x i32>, <2 x i32>* %x
%b = urem <2 x i32> %a, <i32 8, i32 8> %b = urem <2 x i32> %a, <i32 8, i32 8>
store <2 x i32> %b, <2 x i32>* %y store <2 x i32> %b, <2 x i32>* %y
ret void ret void
} }
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llvm/test/CodeGen/X86/vector-lzcnt-128.ll

Show First 20 Lines • Show All 230 Lines • ▼ Show 20 Lines
; ;
; X32-SSE-LABEL: testv2i64: ; X32-SSE-LABEL: testv2i64:
; X32-SSE: # %bb.0: ; X32-SSE: # %bb.0:
; X32-SSE-NEXT: movdqa {{.*#+}} xmm2 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; X32-SSE-NEXT: movdqa {{.*#+}} xmm2 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; X32-SSE-NEXT: movdqa %xmm2, %xmm3 ; X32-SSE-NEXT: movdqa %xmm2, %xmm3
; X32-SSE-NEXT: pshufb %xmm0, %xmm3 ; X32-SSE-NEXT: pshufb %xmm0, %xmm3
; X32-SSE-NEXT: movdqa %xmm0, %xmm1 ; X32-SSE-NEXT: movdqa %xmm0, %xmm1
; X32-SSE-NEXT: psrlw $4, %xmm1 ; X32-SSE-NEXT: psrlw $4, %xmm1
; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X32-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X32-SSE-NEXT: pxor %xmm4, %xmm4 ; X32-SSE-NEXT: pxor %xmm4, %xmm4
; X32-SSE-NEXT: pshufb %xmm1, %xmm2 ; X32-SSE-NEXT: pshufb %xmm1, %xmm2
; X32-SSE-NEXT: pcmpeqb %xmm4, %xmm1 ; X32-SSE-NEXT: pcmpeqb %xmm4, %xmm1
; X32-SSE-NEXT: pand %xmm3, %xmm1 ; X32-SSE-NEXT: pand %xmm3, %xmm1
; X32-SSE-NEXT: paddb %xmm2, %xmm1 ; X32-SSE-NEXT: paddb %xmm2, %xmm1
; X32-SSE-NEXT: movdqa %xmm0, %xmm2 ; X32-SSE-NEXT: movdqa %xmm0, %xmm2
; X32-SSE-NEXT: pcmpeqb %xmm4, %xmm2 ; X32-SSE-NEXT: pcmpeqb %xmm4, %xmm2
; X32-SSE-NEXT: psrlw $8, %xmm2 ; X32-SSE-NEXT: psrlw $8, %xmm2
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; ;
; X32-SSE-LABEL: testv2i64u: ; X32-SSE-LABEL: testv2i64u:
; X32-SSE: # %bb.0: ; X32-SSE: # %bb.0:
; X32-SSE-NEXT: movdqa {{.*#+}} xmm2 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; X32-SSE-NEXT: movdqa {{.*#+}} xmm2 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; X32-SSE-NEXT: movdqa %xmm2, %xmm3 ; X32-SSE-NEXT: movdqa %xmm2, %xmm3
; X32-SSE-NEXT: pshufb %xmm0, %xmm3 ; X32-SSE-NEXT: pshufb %xmm0, %xmm3
; X32-SSE-NEXT: movdqa %xmm0, %xmm1 ; X32-SSE-NEXT: movdqa %xmm0, %xmm1
; X32-SSE-NEXT: psrlw $4, %xmm1 ; X32-SSE-NEXT: psrlw $4, %xmm1
; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X32-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X32-SSE-NEXT: pxor %xmm4, %xmm4 ; X32-SSE-NEXT: pxor %xmm4, %xmm4
; X32-SSE-NEXT: pshufb %xmm1, %xmm2 ; X32-SSE-NEXT: pshufb %xmm1, %xmm2
; X32-SSE-NEXT: pcmpeqb %xmm4, %xmm1 ; X32-SSE-NEXT: pcmpeqb %xmm4, %xmm1
; X32-SSE-NEXT: pand %xmm3, %xmm1 ; X32-SSE-NEXT: pand %xmm3, %xmm1
; X32-SSE-NEXT: paddb %xmm2, %xmm1 ; X32-SSE-NEXT: paddb %xmm2, %xmm1
; X32-SSE-NEXT: movdqa %xmm0, %xmm2 ; X32-SSE-NEXT: movdqa %xmm0, %xmm2
; X32-SSE-NEXT: pcmpeqb %xmm4, %xmm2 ; X32-SSE-NEXT: pcmpeqb %xmm4, %xmm2
; X32-SSE-NEXT: psrlw $8, %xmm2 ; X32-SSE-NEXT: psrlw $8, %xmm2
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; ;
; X32-SSE-LABEL: testv4i32: ; X32-SSE-LABEL: testv4i32:
; X32-SSE: # %bb.0: ; X32-SSE: # %bb.0:
; X32-SSE-NEXT: movdqa {{.*#+}} xmm2 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; X32-SSE-NEXT: movdqa {{.*#+}} xmm2 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; X32-SSE-NEXT: movdqa %xmm2, %xmm3 ; X32-SSE-NEXT: movdqa %xmm2, %xmm3
; X32-SSE-NEXT: pshufb %xmm0, %xmm3 ; X32-SSE-NEXT: pshufb %xmm0, %xmm3
; X32-SSE-NEXT: movdqa %xmm0, %xmm1 ; X32-SSE-NEXT: movdqa %xmm0, %xmm1
; X32-SSE-NEXT: psrlw $4, %xmm1 ; X32-SSE-NEXT: psrlw $4, %xmm1
; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X32-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X32-SSE-NEXT: pxor %xmm4, %xmm4 ; X32-SSE-NEXT: pxor %xmm4, %xmm4
; X32-SSE-NEXT: pshufb %xmm1, %xmm2 ; X32-SSE-NEXT: pshufb %xmm1, %xmm2
; X32-SSE-NEXT: pcmpeqb %xmm4, %xmm1 ; X32-SSE-NEXT: pcmpeqb %xmm4, %xmm1
; X32-SSE-NEXT: pand %xmm3, %xmm1 ; X32-SSE-NEXT: pand %xmm3, %xmm1
; X32-SSE-NEXT: paddb %xmm2, %xmm1 ; X32-SSE-NEXT: paddb %xmm2, %xmm1
; X32-SSE-NEXT: movdqa %xmm0, %xmm2 ; X32-SSE-NEXT: movdqa %xmm0, %xmm2
; X32-SSE-NEXT: pcmpeqb %xmm4, %xmm2 ; X32-SSE-NEXT: pcmpeqb %xmm4, %xmm2
; X32-SSE-NEXT: psrlw $8, %xmm2 ; X32-SSE-NEXT: psrlw $8, %xmm2
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; ;
; X32-SSE-LABEL: testv4i32u: ; X32-SSE-LABEL: testv4i32u:
; X32-SSE: # %bb.0: ; X32-SSE: # %bb.0:
; X32-SSE-NEXT: movdqa {{.*#+}} xmm2 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; X32-SSE-NEXT: movdqa {{.*#+}} xmm2 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; X32-SSE-NEXT: movdqa %xmm2, %xmm3 ; X32-SSE-NEXT: movdqa %xmm2, %xmm3
; X32-SSE-NEXT: pshufb %xmm0, %xmm3 ; X32-SSE-NEXT: pshufb %xmm0, %xmm3
; X32-SSE-NEXT: movdqa %xmm0, %xmm1 ; X32-SSE-NEXT: movdqa %xmm0, %xmm1
; X32-SSE-NEXT: psrlw $4, %xmm1 ; X32-SSE-NEXT: psrlw $4, %xmm1
; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X32-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X32-SSE-NEXT: pxor %xmm4, %xmm4 ; X32-SSE-NEXT: pxor %xmm4, %xmm4
; X32-SSE-NEXT: pshufb %xmm1, %xmm2 ; X32-SSE-NEXT: pshufb %xmm1, %xmm2
; X32-SSE-NEXT: pcmpeqb %xmm4, %xmm1 ; X32-SSE-NEXT: pcmpeqb %xmm4, %xmm1
; X32-SSE-NEXT: pand %xmm3, %xmm1 ; X32-SSE-NEXT: pand %xmm3, %xmm1
; X32-SSE-NEXT: paddb %xmm2, %xmm1 ; X32-SSE-NEXT: paddb %xmm2, %xmm1
; X32-SSE-NEXT: movdqa %xmm0, %xmm2 ; X32-SSE-NEXT: movdqa %xmm0, %xmm2
; X32-SSE-NEXT: pcmpeqb %xmm4, %xmm2 ; X32-SSE-NEXT: pcmpeqb %xmm4, %xmm2
; X32-SSE-NEXT: psrlw $8, %xmm2 ; X32-SSE-NEXT: psrlw $8, %xmm2
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; ;
; X32-SSE-LABEL: testv8i16: ; X32-SSE-LABEL: testv8i16:
; X32-SSE: # %bb.0: ; X32-SSE: # %bb.0:
; X32-SSE-NEXT: movdqa {{.*#+}} xmm2 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; X32-SSE-NEXT: movdqa {{.*#+}} xmm2 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; X32-SSE-NEXT: movdqa %xmm2, %xmm3 ; X32-SSE-NEXT: movdqa %xmm2, %xmm3
; X32-SSE-NEXT: pshufb %xmm0, %xmm3 ; X32-SSE-NEXT: pshufb %xmm0, %xmm3
; X32-SSE-NEXT: movdqa %xmm0, %xmm1 ; X32-SSE-NEXT: movdqa %xmm0, %xmm1
; X32-SSE-NEXT: psrlw $4, %xmm1 ; X32-SSE-NEXT: psrlw $4, %xmm1
; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X32-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X32-SSE-NEXT: pxor %xmm4, %xmm4 ; X32-SSE-NEXT: pxor %xmm4, %xmm4
; X32-SSE-NEXT: pshufb %xmm1, %xmm2 ; X32-SSE-NEXT: pshufb %xmm1, %xmm2
; X32-SSE-NEXT: pcmpeqb %xmm4, %xmm1 ; X32-SSE-NEXT: pcmpeqb %xmm4, %xmm1
; X32-SSE-NEXT: pand %xmm3, %xmm1 ; X32-SSE-NEXT: pand %xmm3, %xmm1
; X32-SSE-NEXT: paddb %xmm2, %xmm1 ; X32-SSE-NEXT: paddb %xmm2, %xmm1
; X32-SSE-NEXT: pcmpeqb %xmm4, %xmm0 ; X32-SSE-NEXT: pcmpeqb %xmm4, %xmm0
; X32-SSE-NEXT: psrlw $8, %xmm0 ; X32-SSE-NEXT: psrlw $8, %xmm0
; X32-SSE-NEXT: pand %xmm1, %xmm0 ; X32-SSE-NEXT: pand %xmm1, %xmm0
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; ;
; X32-SSE-LABEL: testv8i16u: ; X32-SSE-LABEL: testv8i16u:
; X32-SSE: # %bb.0: ; X32-SSE: # %bb.0:
; X32-SSE-NEXT: movdqa {{.*#+}} xmm2 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; X32-SSE-NEXT: movdqa {{.*#+}} xmm2 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; X32-SSE-NEXT: movdqa %xmm2, %xmm3 ; X32-SSE-NEXT: movdqa %xmm2, %xmm3
; X32-SSE-NEXT: pshufb %xmm0, %xmm3 ; X32-SSE-NEXT: pshufb %xmm0, %xmm3
; X32-SSE-NEXT: movdqa %xmm0, %xmm1 ; X32-SSE-NEXT: movdqa %xmm0, %xmm1
; X32-SSE-NEXT: psrlw $4, %xmm1 ; X32-SSE-NEXT: psrlw $4, %xmm1
; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X32-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X32-SSE-NEXT: pxor %xmm4, %xmm4 ; X32-SSE-NEXT: pxor %xmm4, %xmm4
; X32-SSE-NEXT: pshufb %xmm1, %xmm2 ; X32-SSE-NEXT: pshufb %xmm1, %xmm2
; X32-SSE-NEXT: pcmpeqb %xmm4, %xmm1 ; X32-SSE-NEXT: pcmpeqb %xmm4, %xmm1
; X32-SSE-NEXT: pand %xmm3, %xmm1 ; X32-SSE-NEXT: pand %xmm3, %xmm1
; X32-SSE-NEXT: paddb %xmm2, %xmm1 ; X32-SSE-NEXT: paddb %xmm2, %xmm1
; X32-SSE-NEXT: pcmpeqb %xmm4, %xmm0 ; X32-SSE-NEXT: pcmpeqb %xmm4, %xmm0
; X32-SSE-NEXT: psrlw $8, %xmm0 ; X32-SSE-NEXT: psrlw $8, %xmm0
; X32-SSE-NEXT: pand %xmm1, %xmm0 ; X32-SSE-NEXT: pand %xmm1, %xmm0
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; AVX512-NEXT: retq ; AVX512-NEXT: retq
; ;
; X32-SSE-LABEL: testv16i8: ; X32-SSE-LABEL: testv16i8:
; X32-SSE: # %bb.0: ; X32-SSE: # %bb.0:
; X32-SSE-NEXT: movdqa {{.*#+}} xmm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; X32-SSE-NEXT: movdqa {{.*#+}} xmm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; X32-SSE-NEXT: movdqa %xmm1, %xmm2 ; X32-SSE-NEXT: movdqa %xmm1, %xmm2
; X32-SSE-NEXT: pshufb %xmm0, %xmm2 ; X32-SSE-NEXT: pshufb %xmm0, %xmm2
; X32-SSE-NEXT: psrlw $4, %xmm0 ; X32-SSE-NEXT: psrlw $4, %xmm0
; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X32-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-SSE-NEXT: pxor %xmm3, %xmm3 ; X32-SSE-NEXT: pxor %xmm3, %xmm3
; X32-SSE-NEXT: pcmpeqb %xmm0, %xmm3 ; X32-SSE-NEXT: pcmpeqb %xmm0, %xmm3
; X32-SSE-NEXT: pand %xmm2, %xmm3 ; X32-SSE-NEXT: pand %xmm2, %xmm3
; X32-SSE-NEXT: pshufb %xmm0, %xmm1 ; X32-SSE-NEXT: pshufb %xmm0, %xmm1
; X32-SSE-NEXT: paddb %xmm3, %xmm1 ; X32-SSE-NEXT: paddb %xmm3, %xmm1
; X32-SSE-NEXT: movdqa %xmm1, %xmm0 ; X32-SSE-NEXT: movdqa %xmm1, %xmm0
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
%out = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %in, i1 0) %out = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %in, i1 0)
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; AVX512-NEXT: retq ; AVX512-NEXT: retq
; ;
; X32-SSE-LABEL: testv16i8u: ; X32-SSE-LABEL: testv16i8u:
; X32-SSE: # %bb.0: ; X32-SSE: # %bb.0:
; X32-SSE-NEXT: movdqa {{.*#+}} xmm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; X32-SSE-NEXT: movdqa {{.*#+}} xmm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; X32-SSE-NEXT: movdqa %xmm1, %xmm2 ; X32-SSE-NEXT: movdqa %xmm1, %xmm2
; X32-SSE-NEXT: pshufb %xmm0, %xmm2 ; X32-SSE-NEXT: pshufb %xmm0, %xmm2
; X32-SSE-NEXT: psrlw $4, %xmm0 ; X32-SSE-NEXT: psrlw $4, %xmm0
; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X32-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X32-SSE-NEXT: pxor %xmm3, %xmm3 ; X32-SSE-NEXT: pxor %xmm3, %xmm3
; X32-SSE-NEXT: pcmpeqb %xmm0, %xmm3 ; X32-SSE-NEXT: pcmpeqb %xmm0, %xmm3
; X32-SSE-NEXT: pand %xmm2, %xmm3 ; X32-SSE-NEXT: pand %xmm2, %xmm3
; X32-SSE-NEXT: pshufb %xmm0, %xmm1 ; X32-SSE-NEXT: pshufb %xmm0, %xmm1
; X32-SSE-NEXT: paddb %xmm3, %xmm1 ; X32-SSE-NEXT: paddb %xmm3, %xmm1
; X32-SSE-NEXT: movdqa %xmm1, %xmm0 ; X32-SSE-NEXT: movdqa %xmm1, %xmm0
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
%out = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %in, i1 -1) %out = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %in, i1 -1)
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llvm/test/CodeGen/X86/vector-lzcnt-256.ll

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; AVX512CD-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512CD-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; AVX512CD-NEXT: retq ; AVX512CD-NEXT: retq
; ;
; X32-AVX-LABEL: testv4i64: ; X32-AVX-LABEL: testv4i64:
; X32-AVX: # %bb.0: ; X32-AVX: # %bb.0:
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2 ; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm3 ; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm3
; X32-AVX-NEXT: vpand {{\.LCPI.*}}, %ymm3, %ymm3 ; X32-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm3
; X32-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4 ; X32-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4
; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5 ; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5
; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2 ; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2
; X32-AVX-NEXT: vpshufb %ymm3, %ymm1, %ymm1 ; X32-AVX-NEXT: vpshufb %ymm3, %ymm1, %ymm1
; X32-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1 ; X32-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1
; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm2 ; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm2
; X32-AVX-NEXT: vpsrlw $8, %ymm2, %ymm2 ; X32-AVX-NEXT: vpsrlw $8, %ymm2, %ymm2
; X32-AVX-NEXT: vpand %ymm2, %ymm1, %ymm2 ; X32-AVX-NEXT: vpand %ymm2, %ymm1, %ymm2
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; AVX512CD-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512CD-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; AVX512CD-NEXT: retq ; AVX512CD-NEXT: retq
; ;
; X32-AVX-LABEL: testv4i64u: ; X32-AVX-LABEL: testv4i64u:
; X32-AVX: # %bb.0: ; X32-AVX: # %bb.0:
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2 ; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm3 ; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm3
; X32-AVX-NEXT: vpand {{\.LCPI.*}}, %ymm3, %ymm3 ; X32-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm3
; X32-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4 ; X32-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4
; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5 ; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5
; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2 ; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2
; X32-AVX-NEXT: vpshufb %ymm3, %ymm1, %ymm1 ; X32-AVX-NEXT: vpshufb %ymm3, %ymm1, %ymm1
; X32-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1 ; X32-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1
; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm2 ; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm2
; X32-AVX-NEXT: vpsrlw $8, %ymm2, %ymm2 ; X32-AVX-NEXT: vpsrlw $8, %ymm2, %ymm2
; X32-AVX-NEXT: vpand %ymm2, %ymm1, %ymm2 ; X32-AVX-NEXT: vpand %ymm2, %ymm1, %ymm2
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; AVX512CD-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512CD-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; AVX512CD-NEXT: retq ; AVX512CD-NEXT: retq
; ;
; X32-AVX-LABEL: testv8i32: ; X32-AVX-LABEL: testv8i32:
; X32-AVX: # %bb.0: ; X32-AVX: # %bb.0:
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2 ; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm3 ; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm3
; X32-AVX-NEXT: vpand {{\.LCPI.*}}, %ymm3, %ymm3 ; X32-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm3
; X32-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4 ; X32-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4
; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5 ; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5
; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2 ; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2
; X32-AVX-NEXT: vpshufb %ymm3, %ymm1, %ymm1 ; X32-AVX-NEXT: vpshufb %ymm3, %ymm1, %ymm1
; X32-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1 ; X32-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1
; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm2 ; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm2
; X32-AVX-NEXT: vpsrlw $8, %ymm2, %ymm2 ; X32-AVX-NEXT: vpsrlw $8, %ymm2, %ymm2
; X32-AVX-NEXT: vpand %ymm2, %ymm1, %ymm2 ; X32-AVX-NEXT: vpand %ymm2, %ymm1, %ymm2
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; AVX512CD-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0 ; AVX512CD-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; AVX512CD-NEXT: retq ; AVX512CD-NEXT: retq
; ;
; X32-AVX-LABEL: testv8i32u: ; X32-AVX-LABEL: testv8i32u:
; X32-AVX: # %bb.0: ; X32-AVX: # %bb.0:
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2 ; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm3 ; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm3
; X32-AVX-NEXT: vpand {{\.LCPI.*}}, %ymm3, %ymm3 ; X32-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm3
; X32-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4 ; X32-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4
; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5 ; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5
; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2 ; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2
; X32-AVX-NEXT: vpshufb %ymm3, %ymm1, %ymm1 ; X32-AVX-NEXT: vpshufb %ymm3, %ymm1, %ymm1
; X32-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1 ; X32-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1
; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm2 ; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm2
; X32-AVX-NEXT: vpsrlw $8, %ymm2, %ymm2 ; X32-AVX-NEXT: vpsrlw $8, %ymm2, %ymm2
; X32-AVX-NEXT: vpand %ymm2, %ymm1, %ymm2 ; X32-AVX-NEXT: vpand %ymm2, %ymm1, %ymm2
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; AVX512-NEXT: vpsubw {{.*}}(%rip), %ymm0, %ymm0 ; AVX512-NEXT: vpsubw {{.*}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
; ;
; X32-AVX-LABEL: testv16i16: ; X32-AVX-LABEL: testv16i16:
; X32-AVX: # %bb.0: ; X32-AVX: # %bb.0:
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2 ; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm3 ; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm3
; X32-AVX-NEXT: vpand {{\.LCPI.*}}, %ymm3, %ymm3 ; X32-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm3
; X32-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4 ; X32-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4
; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5 ; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5
; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2 ; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2
; X32-AVX-NEXT: vpshufb %ymm3, %ymm1, %ymm1 ; X32-AVX-NEXT: vpshufb %ymm3, %ymm1, %ymm1
; X32-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1 ; X32-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1
; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm0 ; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm0
; X32-AVX-NEXT: vpsrlw $8, %ymm0, %ymm0 ; X32-AVX-NEXT: vpsrlw $8, %ymm0, %ymm0
; X32-AVX-NEXT: vpand %ymm0, %ymm1, %ymm0 ; X32-AVX-NEXT: vpand %ymm0, %ymm1, %ymm0
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; AVX512-NEXT: vpsubw {{.*}}(%rip), %ymm0, %ymm0 ; AVX512-NEXT: vpsubw {{.*}}(%rip), %ymm0, %ymm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
; ;
; X32-AVX-LABEL: testv16i16u: ; X32-AVX-LABEL: testv16i16u:
; X32-AVX: # %bb.0: ; X32-AVX: # %bb.0:
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2 ; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm3 ; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm3
; X32-AVX-NEXT: vpand {{\.LCPI.*}}, %ymm3, %ymm3 ; X32-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm3, %ymm3
; X32-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4 ; X32-AVX-NEXT: vpxor %xmm4, %xmm4, %xmm4
; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5 ; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm3, %ymm5
; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2 ; X32-AVX-NEXT: vpand %ymm5, %ymm2, %ymm2
; X32-AVX-NEXT: vpshufb %ymm3, %ymm1, %ymm1 ; X32-AVX-NEXT: vpshufb %ymm3, %ymm1, %ymm1
; X32-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1 ; X32-AVX-NEXT: vpaddb %ymm1, %ymm2, %ymm1
; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm0 ; X32-AVX-NEXT: vpcmpeqb %ymm4, %ymm0, %ymm0
; X32-AVX-NEXT: vpsrlw $8, %ymm0, %ymm0 ; X32-AVX-NEXT: vpsrlw $8, %ymm0, %ymm0
; X32-AVX-NEXT: vpand %ymm0, %ymm1, %ymm0 ; X32-AVX-NEXT: vpand %ymm0, %ymm1, %ymm0
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; AVX512-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0 ; AVX512-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
; ;
; X32-AVX-LABEL: testv32i8: ; X32-AVX-LABEL: testv32i8:
; X32-AVX: # %bb.0: ; X32-AVX: # %bb.0:
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2 ; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0 ; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0
; X32-AVX-NEXT: vpand {{\.LCPI.*}}, %ymm0, %ymm0 ; X32-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-AVX-NEXT: vpxor %xmm3, %xmm3, %xmm3 ; X32-AVX-NEXT: vpxor %xmm3, %xmm3, %xmm3
; X32-AVX-NEXT: vpcmpeqb %ymm3, %ymm0, %ymm3 ; X32-AVX-NEXT: vpcmpeqb %ymm3, %ymm0, %ymm3
; X32-AVX-NEXT: vpand %ymm3, %ymm2, %ymm2 ; X32-AVX-NEXT: vpand %ymm3, %ymm2, %ymm2
; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm0 ; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm0
; X32-AVX-NEXT: vpaddb %ymm0, %ymm2, %ymm0 ; X32-AVX-NEXT: vpaddb %ymm0, %ymm2, %ymm0
; X32-AVX-NEXT: retl ; X32-AVX-NEXT: retl
%out = call <32 x i8> @llvm.ctlz.v32i8(<32 x i8> %in, i1 0) %out = call <32 x i8> @llvm.ctlz.v32i8(<32 x i8> %in, i1 0)
ret <32 x i8> %out ret <32 x i8> %out
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; AVX512-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0 ; AVX512-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
; ;
; X32-AVX-LABEL: testv32i8u: ; X32-AVX-LABEL: testv32i8u:
; X32-AVX: # %bb.0: ; X32-AVX: # %bb.0:
; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0] ; X32-AVX-NEXT: vmovdqa {{.*#+}} ymm1 = [4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0,4,3,2,2,1,1,1,1,0,0,0,0,0,0,0,0]
; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2 ; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm2
; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0 ; X32-AVX-NEXT: vpsrlw $4, %ymm0, %ymm0
; X32-AVX-NEXT: vpand {{\.LCPI.*}}, %ymm0, %ymm0 ; X32-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X32-AVX-NEXT: vpxor %xmm3, %xmm3, %xmm3 ; X32-AVX-NEXT: vpxor %xmm3, %xmm3, %xmm3
; X32-AVX-NEXT: vpcmpeqb %ymm3, %ymm0, %ymm3 ; X32-AVX-NEXT: vpcmpeqb %ymm3, %ymm0, %ymm3
; X32-AVX-NEXT: vpand %ymm3, %ymm2, %ymm2 ; X32-AVX-NEXT: vpand %ymm3, %ymm2, %ymm2
; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm0 ; X32-AVX-NEXT: vpshufb %ymm0, %ymm1, %ymm0
; X32-AVX-NEXT: vpaddb %ymm0, %ymm2, %ymm0 ; X32-AVX-NEXT: vpaddb %ymm0, %ymm2, %ymm0
; X32-AVX-NEXT: retl ; X32-AVX-NEXT: retl
%out = call <32 x i8> @llvm.ctlz.v32i8(<32 x i8> %in, i1 -1) %out = call <32 x i8> @llvm.ctlz.v32i8(<32 x i8> %in, i1 -1)
ret <32 x i8> %out ret <32 x i8> %out
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llvm/test/CodeGen/X86/vector-mul.ll

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%1 = mul <8 x i16> %a0, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> %1 = mul <8 x i16> %a0, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
ret <8 x i16> %1 ret <8 x i16> %1
} }
define <16 x i8> @mul_v16i8_32(<16 x i8> %a0) nounwind { define <16 x i8> @mul_v16i8_32(<16 x i8> %a0) nounwind {
; X86-SSE-LABEL: mul_v16i8_32: ; X86-SSE-LABEL: mul_v16i8_32:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: psllw $5, %xmm0 ; X86-SSE-NEXT: psllw $5, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: mul_v16i8_32: ; X64-SSE-LABEL: mul_v16i8_32:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: psllw $5, %xmm0 ; X64-SSE-NEXT: psllw $5, %xmm0
; X64-SSE-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
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; X64-AVX512DQ-NEXT: retq ; X64-AVX512DQ-NEXT: retq
%1 = mul <2 x i64> %a0, <i64 32, i64 8> %1 = mul <2 x i64> %a0, <i64 32, i64 8>
ret <2 x i64> %1 ret <2 x i64> %1
} }
define <4 x i32> @mul_v4i32_1_2_4_8(<4 x i32> %a0) nounwind { define <4 x i32> @mul_v4i32_1_2_4_8(<4 x i32> %a0) nounwind {
; X86-SSE-LABEL: mul_v4i32_1_2_4_8: ; X86-SSE-LABEL: mul_v4i32_1_2_4_8:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pmulld {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: mul_v4i32_1_2_4_8: ; X64-SSE-LABEL: mul_v4i32_1_2_4_8:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: pmulld {{.*}}(%rip), %xmm0 ; X64-SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-XOP-LABEL: mul_v4i32_1_2_4_8: ; X64-XOP-LABEL: mul_v4i32_1_2_4_8:
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; X64-AVX512DQ-NEXT: retq ; X64-AVX512DQ-NEXT: retq
%1 = mul <4 x i32> %a0, <i32 1, i32 2, i32 4, i32 8> %1 = mul <4 x i32> %a0, <i32 1, i32 2, i32 4, i32 8>
ret <4 x i32> %1 ret <4 x i32> %1
} }
define <8 x i16> @mul_v8i16_1_2_4_8_16_32_64_128(<8 x i16> %a0) nounwind { define <8 x i16> @mul_v8i16_1_2_4_8_16_32_64_128(<8 x i16> %a0) nounwind {
; X86-SSE-LABEL: mul_v8i16_1_2_4_8_16_32_64_128: ; X86-SSE-LABEL: mul_v8i16_1_2_4_8_16_32_64_128:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: mul_v8i16_1_2_4_8_16_32_64_128: ; X64-SSE-LABEL: mul_v8i16_1_2_4_8_16_32_64_128:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: pmullw {{.*}}(%rip), %xmm0 ; X64-SSE-NEXT: pmullw {{.*}}(%rip), %xmm0
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-XOP-LABEL: mul_v8i16_1_2_4_8_16_32_64_128: ; X64-XOP-LABEL: mul_v8i16_1_2_4_8_16_32_64_128:
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; X64-AVX512DQ-NEXT: retq ; X64-AVX512DQ-NEXT: retq
%1 = mul <2 x i64> %a0, <i64 17, i64 17> %1 = mul <2 x i64> %a0, <i64 17, i64 17>
ret <2 x i64> %1 ret <2 x i64> %1
} }
define <4 x i32> @mul_v4i32_17(<4 x i32> %a0) nounwind { define <4 x i32> @mul_v4i32_17(<4 x i32> %a0) nounwind {
; X86-SSE-LABEL: mul_v4i32_17: ; X86-SSE-LABEL: mul_v4i32_17:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pmulld {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: mul_v4i32_17: ; X64-SSE-LABEL: mul_v4i32_17:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: pmulld {{.*}}(%rip), %xmm0 ; X64-SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-XOP-LABEL: mul_v4i32_17: ; X64-XOP-LABEL: mul_v4i32_17:
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; X64-AVX512DQ-NEXT: retq ; X64-AVX512DQ-NEXT: retq
%1 = mul <4 x i32> %a0, <i32 17, i32 17, i32 17, i32 17> %1 = mul <4 x i32> %a0, <i32 17, i32 17, i32 17, i32 17>
ret <4 x i32> %1 ret <4 x i32> %1
} }
define <8 x i16> @mul_v8i16_17(<8 x i16> %a0) nounwind { define <8 x i16> @mul_v8i16_17(<8 x i16> %a0) nounwind {
; X86-SSE-LABEL: mul_v8i16_17: ; X86-SSE-LABEL: mul_v8i16_17:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: mul_v8i16_17: ; X64-SSE-LABEL: mul_v8i16_17:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: pmullw {{.*}}(%rip), %xmm0 ; X64-SSE-NEXT: pmullw {{.*}}(%rip), %xmm0
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX-LABEL: mul_v8i16_17: ; X64-AVX-LABEL: mul_v8i16_17:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%1 = mul <8 x i16> %a0, <i16 17, i16 17, i16 17, i16 17, i16 17, i16 17, i16 17, i16 17> %1 = mul <8 x i16> %a0, <i16 17, i16 17, i16 17, i16 17, i16 17, i16 17, i16 17, i16 17>
ret <8 x i16> %1 ret <8 x i16> %1
} }
define <16 x i8> @mul_v16i8_17(<16 x i8> %a0) nounwind { define <16 x i8> @mul_v16i8_17(<16 x i8> %a0) nounwind {
; X86-SSE-LABEL: mul_v16i8_17: ; X86-SSE-LABEL: mul_v16i8_17:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: movdqa %xmm0, %xmm1 ; X86-SSE-NEXT: movdqa %xmm0, %xmm1
; X86-SSE-NEXT: psllw $4, %xmm1 ; X86-SSE-NEXT: psllw $4, %xmm1
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE-NEXT: paddb %xmm0, %xmm1 ; X86-SSE-NEXT: paddb %xmm0, %xmm1
; X86-SSE-NEXT: movdqa %xmm1, %xmm0 ; X86-SSE-NEXT: movdqa %xmm1, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: mul_v16i8_17: ; X64-SSE-LABEL: mul_v16i8_17:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: movdqa %xmm0, %xmm1 ; X64-SSE-NEXT: movdqa %xmm0, %xmm1
; X64-SSE-NEXT: psllw $4, %xmm1 ; X64-SSE-NEXT: psllw $4, %xmm1
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; X64-AVX512DQ-NEXT: retq ; X64-AVX512DQ-NEXT: retq
%1 = mul <2 x i64> %a0, <i64 -1025, i64 -1025> %1 = mul <2 x i64> %a0, <i64 -1025, i64 -1025>
ret <2 x i64> %1 ret <2 x i64> %1
} }
define <4 x i32> @mul_v4i32_neg33(<4 x i32> %a0) nounwind { define <4 x i32> @mul_v4i32_neg33(<4 x i32> %a0) nounwind {
; X86-SSE-LABEL: mul_v4i32_neg33: ; X86-SSE-LABEL: mul_v4i32_neg33:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pmulld {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: mul_v4i32_neg33: ; X64-SSE-LABEL: mul_v4i32_neg33:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: pmulld {{.*}}(%rip), %xmm0 ; X64-SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-XOP-LABEL: mul_v4i32_neg33: ; X64-XOP-LABEL: mul_v4i32_neg33:
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; X64-AVX512DQ-NEXT: retq ; X64-AVX512DQ-NEXT: retq
%1 = mul <4 x i32> %a0, <i32 -33, i32 -33, i32 -33, i32 -33> %1 = mul <4 x i32> %a0, <i32 -33, i32 -33, i32 -33, i32 -33>
ret <4 x i32> %1 ret <4 x i32> %1
} }
define <8 x i16> @mul_v8i16_neg9(<8 x i16> %a0) nounwind { define <8 x i16> @mul_v8i16_neg9(<8 x i16> %a0) nounwind {
; X86-SSE-LABEL: mul_v8i16_neg9: ; X86-SSE-LABEL: mul_v8i16_neg9:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: mul_v8i16_neg9: ; X64-SSE-LABEL: mul_v8i16_neg9:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: pmullw {{.*}}(%rip), %xmm0 ; X64-SSE-NEXT: pmullw {{.*}}(%rip), %xmm0
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX-LABEL: mul_v8i16_neg9: ; X64-AVX-LABEL: mul_v8i16_neg9:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%1 = mul <8 x i16> %a0, <i16 -9, i16 -9, i16 -9, i16 -9, i16 -9, i16 -9, i16 -9, i16 -9> %1 = mul <8 x i16> %a0, <i16 -9, i16 -9, i16 -9, i16 -9, i16 -9, i16 -9, i16 -9, i16 -9>
ret <8 x i16> %1 ret <8 x i16> %1
} }
define <16 x i8> @mul_v16i8_neg5(<16 x i8> %a0) nounwind { define <16 x i8> @mul_v16i8_neg5(<16 x i8> %a0) nounwind {
; X86-SSE-LABEL: mul_v16i8_neg5: ; X86-SSE-LABEL: mul_v16i8_neg5:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: movdqa %xmm0, %xmm1 ; X86-SSE-NEXT: movdqa %xmm0, %xmm1
; X86-SSE-NEXT: psllw $2, %xmm1 ; X86-SSE-NEXT: psllw $2, %xmm1
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE-NEXT: paddb %xmm0, %xmm1 ; X86-SSE-NEXT: paddb %xmm0, %xmm1
; X86-SSE-NEXT: pxor %xmm0, %xmm0 ; X86-SSE-NEXT: pxor %xmm0, %xmm0
; X86-SSE-NEXT: psubb %xmm1, %xmm0 ; X86-SSE-NEXT: psubb %xmm1, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: mul_v16i8_neg5: ; X64-SSE-LABEL: mul_v16i8_neg5:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: movdqa %xmm0, %xmm1 ; X64-SSE-NEXT: movdqa %xmm0, %xmm1
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; X64-AVX512DQ-NEXT: retq ; X64-AVX512DQ-NEXT: retq
%1 = mul <2 x i64> %a0, <i64 17, i64 65> %1 = mul <2 x i64> %a0, <i64 17, i64 65>
ret <2 x i64> %1 ret <2 x i64> %1
} }
define <4 x i32> @mul_v4i32_5_17_33_65(<4 x i32> %a0) nounwind { define <4 x i32> @mul_v4i32_5_17_33_65(<4 x i32> %a0) nounwind {
; X86-SSE-LABEL: mul_v4i32_5_17_33_65: ; X86-SSE-LABEL: mul_v4i32_5_17_33_65:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pmulld {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: mul_v4i32_5_17_33_65: ; X64-SSE-LABEL: mul_v4i32_5_17_33_65:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: pmulld {{.*}}(%rip), %xmm0 ; X64-SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX-LABEL: mul_v4i32_5_17_33_65: ; X64-AVX-LABEL: mul_v4i32_5_17_33_65:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%1 = mul <4 x i32> %a0, <i32 5, i32 17, i32 33, i32 65> %1 = mul <4 x i32> %a0, <i32 5, i32 17, i32 33, i32 65>
ret <4 x i32> %1 ret <4 x i32> %1
} }
define <8 x i16> @mul_v8i16_2_3_9_17_33_65_129_257(<8 x i16> %a0) nounwind { define <8 x i16> @mul_v8i16_2_3_9_17_33_65_129_257(<8 x i16> %a0) nounwind {
; X86-SSE-LABEL: mul_v8i16_2_3_9_17_33_65_129_257: ; X86-SSE-LABEL: mul_v8i16_2_3_9_17_33_65_129_257:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: mul_v8i16_2_3_9_17_33_65_129_257: ; X64-SSE-LABEL: mul_v8i16_2_3_9_17_33_65_129_257:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: pmullw {{.*}}(%rip), %xmm0 ; X64-SSE-NEXT: pmullw {{.*}}(%rip), %xmm0
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX-LABEL: mul_v8i16_2_3_9_17_33_65_129_257: ; X64-AVX-LABEL: mul_v8i16_2_3_9_17_33_65_129_257:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%1 = mul <8 x i16> %a0, <i16 2, i16 3, i16 9, i16 17, i16 33, i16 65, i16 129, i16 257> %1 = mul <8 x i16> %a0, <i16 2, i16 3, i16 9, i16 17, i16 33, i16 65, i16 129, i16 257>
ret <8 x i16> %1 ret <8 x i16> %1
} }
define <16 x i8> @mul_v16i8_2_3_9_17_33_65_129_2_3_9_17_33_65_129_2_3(<16 x i8> %a0) nounwind { define <16 x i8> @mul_v16i8_2_3_9_17_33_65_129_2_3_9_17_33_65_129_2_3(<16 x i8> %a0) nounwind {
; X86-SSE-LABEL: mul_v16i8_2_3_9_17_33_65_129_2_3_9_17_33_65_129_2_3: ; X86-SSE-LABEL: mul_v16i8_2_3_9_17_33_65_129_2_3_9_17_33_65_129_2_3:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pmovzxbw {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; X86-SSE-NEXT: pmovzxbw {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
; X86-SSE-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15] ; X86-SSE-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; X86-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255] ; X86-SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
; X86-SSE-NEXT: pand %xmm2, %xmm0 ; X86-SSE-NEXT: pand %xmm2, %xmm0
; X86-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm1 ; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE-NEXT: pand %xmm2, %xmm1 ; X86-SSE-NEXT: pand %xmm2, %xmm1
; X86-SSE-NEXT: packuswb %xmm0, %xmm1 ; X86-SSE-NEXT: packuswb %xmm0, %xmm1
; X86-SSE-NEXT: movdqa %xmm1, %xmm0 ; X86-SSE-NEXT: movdqa %xmm1, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: mul_v16i8_2_3_9_17_33_65_129_2_3_9_17_33_65_129_2_3: ; X64-SSE-LABEL: mul_v16i8_2_3_9_17_33_65_129_2_3_9_17_33_65_129_2_3:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: pmovzxbw {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero ; X64-SSE-NEXT: pmovzxbw {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
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; X64-AVX512DQ-NEXT: retq ; X64-AVX512DQ-NEXT: retq
%1 = mul <2 x i64> %a0, <i64 7, i64 7> %1 = mul <2 x i64> %a0, <i64 7, i64 7>
ret <2 x i64> %1 ret <2 x i64> %1
} }
define <4 x i32> @mul_v4i32_7(<4 x i32> %a0) nounwind { define <4 x i32> @mul_v4i32_7(<4 x i32> %a0) nounwind {
; X86-SSE-LABEL: mul_v4i32_7: ; X86-SSE-LABEL: mul_v4i32_7:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pmulld {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: mul_v4i32_7: ; X64-SSE-LABEL: mul_v4i32_7:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: pmulld {{.*}}(%rip), %xmm0 ; X64-SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-XOP-LABEL: mul_v4i32_7: ; X64-XOP-LABEL: mul_v4i32_7:
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; X64-AVX512DQ-NEXT: retq ; X64-AVX512DQ-NEXT: retq
%1 = mul <4 x i32> %a0, <i32 7, i32 7, i32 7, i32 7> %1 = mul <4 x i32> %a0, <i32 7, i32 7, i32 7, i32 7>
ret <4 x i32> %1 ret <4 x i32> %1
} }
define <8 x i16> @mul_v8i16_7(<8 x i16> %a0) nounwind { define <8 x i16> @mul_v8i16_7(<8 x i16> %a0) nounwind {
; X86-SSE-LABEL: mul_v8i16_7: ; X86-SSE-LABEL: mul_v8i16_7:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: mul_v8i16_7: ; X64-SSE-LABEL: mul_v8i16_7:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: pmullw {{.*}}(%rip), %xmm0 ; X64-SSE-NEXT: pmullw {{.*}}(%rip), %xmm0
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX-LABEL: mul_v8i16_7: ; X64-AVX-LABEL: mul_v8i16_7:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%1 = mul <8 x i16> %a0, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7> %1 = mul <8 x i16> %a0, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
ret <8 x i16> %1 ret <8 x i16> %1
} }
define <16 x i8> @mul_v16i8_31(<16 x i8> %a0) nounwind { define <16 x i8> @mul_v16i8_31(<16 x i8> %a0) nounwind {
; X86-SSE-LABEL: mul_v16i8_31: ; X86-SSE-LABEL: mul_v16i8_31:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: movdqa %xmm0, %xmm1 ; X86-SSE-NEXT: movdqa %xmm0, %xmm1
; X86-SSE-NEXT: psllw $5, %xmm1 ; X86-SSE-NEXT: psllw $5, %xmm1
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE-NEXT: psubb %xmm0, %xmm1 ; X86-SSE-NEXT: psubb %xmm0, %xmm1
; X86-SSE-NEXT: movdqa %xmm1, %xmm0 ; X86-SSE-NEXT: movdqa %xmm1, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: mul_v16i8_31: ; X64-SSE-LABEL: mul_v16i8_31:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: movdqa %xmm0, %xmm1 ; X64-SSE-NEXT: movdqa %xmm0, %xmm1
; X64-SSE-NEXT: psllw $5, %xmm1 ; X64-SSE-NEXT: psllw $5, %xmm1
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; X64-AVX512DQ-NEXT: retq ; X64-AVX512DQ-NEXT: retq
%1 = mul <2 x i64> %a0, <i64 -7, i64 -7> %1 = mul <2 x i64> %a0, <i64 -7, i64 -7>
ret <2 x i64> %1 ret <2 x i64> %1
} }
define <4 x i32> @mul_v4i32_neg63(<4 x i32> %a0) nounwind { define <4 x i32> @mul_v4i32_neg63(<4 x i32> %a0) nounwind {
; X86-SSE-LABEL: mul_v4i32_neg63: ; X86-SSE-LABEL: mul_v4i32_neg63:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pmulld {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: mul_v4i32_neg63: ; X64-SSE-LABEL: mul_v4i32_neg63:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: pmulld {{.*}}(%rip), %xmm0 ; X64-SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-XOP-LABEL: mul_v4i32_neg63: ; X64-XOP-LABEL: mul_v4i32_neg63:
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; X64-AVX512DQ-NEXT: retq ; X64-AVX512DQ-NEXT: retq
%1 = mul <4 x i32> %a0, <i32 -63, i32 -63, i32 -63, i32 -63> %1 = mul <4 x i32> %a0, <i32 -63, i32 -63, i32 -63, i32 -63>
ret <4 x i32> %1 ret <4 x i32> %1
} }
define <8 x i16> @mul_v8i16_neg31(<8 x i16> %a0) nounwind { define <8 x i16> @mul_v8i16_neg31(<8 x i16> %a0) nounwind {
; X86-SSE-LABEL: mul_v8i16_neg31: ; X86-SSE-LABEL: mul_v8i16_neg31:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: mul_v8i16_neg31: ; X64-SSE-LABEL: mul_v8i16_neg31:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: pmullw {{.*}}(%rip), %xmm0 ; X64-SSE-NEXT: pmullw {{.*}}(%rip), %xmm0
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX-LABEL: mul_v8i16_neg31: ; X64-AVX-LABEL: mul_v8i16_neg31:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%1 = mul <8 x i16> %a0, <i16 -31, i16 -31, i16 -31, i16 -31, i16 -31, i16 -31, i16 -31, i16 -31> %1 = mul <8 x i16> %a0, <i16 -31, i16 -31, i16 -31, i16 -31, i16 -31, i16 -31, i16 -31, i16 -31>
ret <8 x i16> %1 ret <8 x i16> %1
} }
define <16 x i8> @mul_v16i8_neg15(<16 x i8> %a0) nounwind { define <16 x i8> @mul_v16i8_neg15(<16 x i8> %a0) nounwind {
; X86-SSE-LABEL: mul_v16i8_neg15: ; X86-SSE-LABEL: mul_v16i8_neg15:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: movdqa %xmm0, %xmm1 ; X86-SSE-NEXT: movdqa %xmm0, %xmm1
; X86-SSE-NEXT: psllw $4, %xmm1 ; X86-SSE-NEXT: psllw $4, %xmm1
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE-NEXT: psubb %xmm1, %xmm0 ; X86-SSE-NEXT: psubb %xmm1, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: mul_v16i8_neg15: ; X64-SSE-LABEL: mul_v16i8_neg15:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: movdqa %xmm0, %xmm1 ; X64-SSE-NEXT: movdqa %xmm0, %xmm1
; X64-SSE-NEXT: psllw $4, %xmm1 ; X64-SSE-NEXT: psllw $4, %xmm1
; X64-SSE-NEXT: pand {{.*}}(%rip), %xmm1 ; X64-SSE-NEXT: pand {{.*}}(%rip), %xmm1
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; X64-AVX512DQ-NEXT: retq ; X64-AVX512DQ-NEXT: retq
%1 = mul <2 x i64> %a0, <i64 15, i64 -63> %1 = mul <2 x i64> %a0, <i64 15, i64 -63>
ret <2 x i64> %1 ret <2 x i64> %1
} }
define <4 x i32> @mul_v4i32_0_15_31_7(<4 x i32> %a0) nounwind { define <4 x i32> @mul_v4i32_0_15_31_7(<4 x i32> %a0) nounwind {
; X86-SSE-LABEL: mul_v4i32_0_15_31_7: ; X86-SSE-LABEL: mul_v4i32_0_15_31_7:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pmulld {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: mul_v4i32_0_15_31_7: ; X64-SSE-LABEL: mul_v4i32_0_15_31_7:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: pmulld {{.*}}(%rip), %xmm0 ; X64-SSE-NEXT: pmulld {{.*}}(%rip), %xmm0
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX-LABEL: mul_v4i32_0_15_31_7: ; X64-AVX-LABEL: mul_v4i32_0_15_31_7:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%1 = mul <4 x i32> %a0, <i32 0, i32 15, i32 31, i32 7> %1 = mul <4 x i32> %a0, <i32 0, i32 15, i32 31, i32 7>
ret <4 x i32> %1 ret <4 x i32> %1
} }
define <8 x i16> @mul_v8i16_0_1_7_15_31_63_127_255(<8 x i16> %a0) nounwind { define <8 x i16> @mul_v8i16_0_1_7_15_31_63_127_255(<8 x i16> %a0) nounwind {
; X86-SSE-LABEL: mul_v8i16_0_1_7_15_31_63_127_255: ; X86-SSE-LABEL: mul_v8i16_0_1_7_15_31_63_127_255:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: mul_v8i16_0_1_7_15_31_63_127_255: ; X64-SSE-LABEL: mul_v8i16_0_1_7_15_31_63_127_255:
; X64-SSE: # %bb.0: ; X64-SSE: # %bb.0:
; X64-SSE-NEXT: pmullw {{.*}}(%rip), %xmm0 ; X64-SSE-NEXT: pmullw {{.*}}(%rip), %xmm0
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
; ;
; X64-AVX-LABEL: mul_v8i16_0_1_7_15_31_63_127_255: ; X64-AVX-LABEL: mul_v8i16_0_1_7_15_31_63_127_255:
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llvm/test/CodeGen/X86/vector-rotate-128.ll

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; ;
; XOP-LABEL: var_rotate_v4i32: ; XOP-LABEL: var_rotate_v4i32:
; XOP: # %bb.0: ; XOP: # %bb.0:
; XOP-NEXT: vprotd %xmm1, %xmm0, %xmm0 ; XOP-NEXT: vprotd %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; X86-SSE2-LABEL: var_rotate_v4i32: ; X86-SSE2-LABEL: var_rotate_v4i32:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: pslld $23, %xmm1 ; X86-SSE2-NEXT: pslld $23, %xmm1
; X86-SSE2-NEXT: paddd {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1 ; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; X86-SSE2-NEXT: pmuludq %xmm1, %xmm0 ; X86-SSE2-NEXT: pmuludq %xmm1, %xmm0
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3]
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; X86-SSE2-NEXT: pmuludq %xmm2, %xmm1 ; X86-SSE2-NEXT: pmuludq %xmm2, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3]
; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1] ; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
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; ;
; XOP-LABEL: var_rotate_v8i16: ; XOP-LABEL: var_rotate_v8i16:
; XOP: # %bb.0: ; XOP: # %bb.0:
; XOP-NEXT: vprotw %xmm1, %xmm0, %xmm0 ; XOP-NEXT: vprotw %xmm1, %xmm0, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; X86-SSE2-LABEL: var_rotate_v8i16: ; X86-SSE2-LABEL: var_rotate_v8i16:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: movdqa %xmm1, %xmm2 ; X86-SSE2-NEXT: movdqa %xmm1, %xmm2
; X86-SSE2-NEXT: punpckhwd {{.*#+}} xmm2 = xmm2[4,4,5,5,6,6,7,7] ; X86-SSE2-NEXT: punpckhwd {{.*#+}} xmm2 = xmm2[4,4,5,5,6,6,7,7]
; X86-SSE2-NEXT: pslld $23, %xmm2 ; X86-SSE2-NEXT: pslld $23, %xmm2
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [1065353216,1065353216,1065353216,1065353216] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [1065353216,1065353216,1065353216,1065353216]
; X86-SSE2-NEXT: paddd %xmm3, %xmm2 ; X86-SSE2-NEXT: paddd %xmm3, %xmm2
; X86-SSE2-NEXT: cvttps2dq %xmm2, %xmm2 ; X86-SSE2-NEXT: cvttps2dq %xmm2, %xmm2
; X86-SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,2,2,3,4,5,6,7] ; X86-SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,2,2,3,4,5,6,7]
; X86-SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,6,6,7] ; X86-SSE2-NEXT: pshufhw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,6,6,7]
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; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movdqa %xmm0, %xmm2 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm2
; X86-SSE2-NEXT: psllw $5, %xmm1 ; X86-SSE2-NEXT: psllw $5, %xmm1
; X86-SSE2-NEXT: pxor %xmm0, %xmm0 ; X86-SSE2-NEXT: pxor %xmm0, %xmm0
; X86-SSE2-NEXT: pxor %xmm3, %xmm3 ; X86-SSE2-NEXT: pxor %xmm3, %xmm3
; X86-SSE2-NEXT: pcmpgtb %xmm1, %xmm3 ; X86-SSE2-NEXT: pcmpgtb %xmm1, %xmm3
; X86-SSE2-NEXT: movdqa %xmm2, %xmm4 ; X86-SSE2-NEXT: movdqa %xmm2, %xmm4
; X86-SSE2-NEXT: psrlw $4, %xmm4 ; X86-SSE2-NEXT: psrlw $4, %xmm4
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm4 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm4
; X86-SSE2-NEXT: movdqa %xmm2, %xmm5 ; X86-SSE2-NEXT: movdqa %xmm2, %xmm5
; X86-SSE2-NEXT: psllw $4, %xmm5 ; X86-SSE2-NEXT: psllw $4, %xmm5
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm5 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm5
; X86-SSE2-NEXT: por %xmm4, %xmm5 ; X86-SSE2-NEXT: por %xmm4, %xmm5
; X86-SSE2-NEXT: pand %xmm3, %xmm5 ; X86-SSE2-NEXT: pand %xmm3, %xmm5
; X86-SSE2-NEXT: pandn %xmm2, %xmm3 ; X86-SSE2-NEXT: pandn %xmm2, %xmm3
; X86-SSE2-NEXT: por %xmm5, %xmm3 ; X86-SSE2-NEXT: por %xmm5, %xmm3
; X86-SSE2-NEXT: movdqa %xmm3, %xmm2 ; X86-SSE2-NEXT: movdqa %xmm3, %xmm2
; X86-SSE2-NEXT: psrlw $6, %xmm2 ; X86-SSE2-NEXT: psrlw $6, %xmm2
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm2 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: movdqa %xmm3, %xmm4 ; X86-SSE2-NEXT: movdqa %xmm3, %xmm4
; X86-SSE2-NEXT: psllw $2, %xmm4 ; X86-SSE2-NEXT: psllw $2, %xmm4
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm4 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm4
; X86-SSE2-NEXT: por %xmm2, %xmm4 ; X86-SSE2-NEXT: por %xmm2, %xmm4
; X86-SSE2-NEXT: paddb %xmm1, %xmm1 ; X86-SSE2-NEXT: paddb %xmm1, %xmm1
; X86-SSE2-NEXT: pxor %xmm2, %xmm2 ; X86-SSE2-NEXT: pxor %xmm2, %xmm2
; X86-SSE2-NEXT: pcmpgtb %xmm1, %xmm2 ; X86-SSE2-NEXT: pcmpgtb %xmm1, %xmm2
; X86-SSE2-NEXT: pand %xmm2, %xmm4 ; X86-SSE2-NEXT: pand %xmm2, %xmm4
; X86-SSE2-NEXT: pandn %xmm3, %xmm2 ; X86-SSE2-NEXT: pandn %xmm3, %xmm2
; X86-SSE2-NEXT: por %xmm4, %xmm2 ; X86-SSE2-NEXT: por %xmm4, %xmm2
; X86-SSE2-NEXT: movdqa %xmm2, %xmm3 ; X86-SSE2-NEXT: movdqa %xmm2, %xmm3
; X86-SSE2-NEXT: paddb %xmm2, %xmm3 ; X86-SSE2-NEXT: paddb %xmm2, %xmm3
; X86-SSE2-NEXT: movdqa %xmm2, %xmm4 ; X86-SSE2-NEXT: movdqa %xmm2, %xmm4
; X86-SSE2-NEXT: psrlw $7, %xmm4 ; X86-SSE2-NEXT: psrlw $7, %xmm4
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm4 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm4
; X86-SSE2-NEXT: por %xmm3, %xmm4 ; X86-SSE2-NEXT: por %xmm3, %xmm4
; X86-SSE2-NEXT: paddb %xmm1, %xmm1 ; X86-SSE2-NEXT: paddb %xmm1, %xmm1
; X86-SSE2-NEXT: pcmpgtb %xmm1, %xmm0 ; X86-SSE2-NEXT: pcmpgtb %xmm1, %xmm0
; X86-SSE2-NEXT: pand %xmm0, %xmm4 ; X86-SSE2-NEXT: pand %xmm0, %xmm4
; X86-SSE2-NEXT: pandn %xmm2, %xmm0 ; X86-SSE2-NEXT: pandn %xmm2, %xmm0
; X86-SSE2-NEXT: por %xmm4, %xmm0 ; X86-SSE2-NEXT: por %xmm4, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
%b8 = sub <16 x i8> <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>, %b %b8 = sub <16 x i8> <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>, %b
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; XOPAVX2-LABEL: splatvar_rotate_v8i16: ; XOPAVX2-LABEL: splatvar_rotate_v8i16:
; XOPAVX2: # %bb.0: ; XOPAVX2: # %bb.0:
; XOPAVX2-NEXT: vpbroadcastw %xmm1, %xmm1 ; XOPAVX2-NEXT: vpbroadcastw %xmm1, %xmm1
; XOPAVX2-NEXT: vprotw %xmm1, %xmm0, %xmm0 ; XOPAVX2-NEXT: vprotw %xmm1, %xmm0, %xmm0
; XOPAVX2-NEXT: retq ; XOPAVX2-NEXT: retq
; ;
; X86-SSE2-LABEL: splatvar_rotate_v8i16: ; X86-SSE2-LABEL: splatvar_rotate_v8i16:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [65535,0,0,0] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [65535,0,0,0]
; X86-SSE2-NEXT: pand %xmm1, %xmm2 ; X86-SSE2-NEXT: pand %xmm1, %xmm2
; X86-SSE2-NEXT: movdqa %xmm0, %xmm3 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm3
; X86-SSE2-NEXT: psllw %xmm2, %xmm3 ; X86-SSE2-NEXT: psllw %xmm2, %xmm3
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [16,16,16,16,16,16,16,16] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [16,16,16,16,16,16,16,16]
; X86-SSE2-NEXT: psubw %xmm1, %xmm2 ; X86-SSE2-NEXT: psubw %xmm1, %xmm2
; X86-SSE2-NEXT: pslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,1] ; X86-SSE2-NEXT: pslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,1]
; X86-SSE2-NEXT: psrldq {{.*#+}} xmm2 = xmm2[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; X86-SSE2-NEXT: psrldq {{.*#+}} xmm2 = xmm2[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
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; XOPAVX2-LABEL: splatvar_rotate_v16i8: ; XOPAVX2-LABEL: splatvar_rotate_v16i8:
; XOPAVX2: # %bb.0: ; XOPAVX2: # %bb.0:
; XOPAVX2-NEXT: vpbroadcastb %xmm1, %xmm1 ; XOPAVX2-NEXT: vpbroadcastb %xmm1, %xmm1
; XOPAVX2-NEXT: vprotb %xmm1, %xmm0, %xmm0 ; XOPAVX2-NEXT: vprotb %xmm1, %xmm0, %xmm0
; XOPAVX2-NEXT: retq ; XOPAVX2-NEXT: retq
; ;
; X86-SSE2-LABEL: splatvar_rotate_v16i8: ; X86-SSE2-LABEL: splatvar_rotate_v16i8:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]
; X86-SSE2-NEXT: psubb %xmm1, %xmm2 ; X86-SSE2-NEXT: psubb %xmm1, %xmm2
; X86-SSE2-NEXT: movdqa %xmm1, %xmm3 ; X86-SSE2-NEXT: movdqa %xmm1, %xmm3
; X86-SSE2-NEXT: pslldq {{.*#+}} xmm3 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm3[0] ; X86-SSE2-NEXT: pslldq {{.*#+}} xmm3 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm3[0]
; X86-SSE2-NEXT: psrldq {{.*#+}} xmm3 = xmm3[15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero ; X86-SSE2-NEXT: psrldq {{.*#+}} xmm3 = xmm3[15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
; X86-SSE2-NEXT: movdqa %xmm0, %xmm1 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm1
; X86-SSE2-NEXT: psllw %xmm3, %xmm1 ; X86-SSE2-NEXT: psllw %xmm3, %xmm1
; X86-SSE2-NEXT: pcmpeqd %xmm4, %xmm4 ; X86-SSE2-NEXT: pcmpeqd %xmm4, %xmm4
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; XOP-NEXT: vprotb {{.*}}(%rip), %xmm0, %xmm0 ; XOP-NEXT: vprotb {{.*}}(%rip), %xmm0, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; X86-SSE2-LABEL: constant_rotate_v16i8: ; X86-SSE2-LABEL: constant_rotate_v16i8:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pxor %xmm1, %xmm1 ; X86-SSE2-NEXT: pxor %xmm1, %xmm1
; X86-SSE2-NEXT: movdqa %xmm0, %xmm2 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm2
; X86-SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15] ; X86-SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
; X86-SSE2-NEXT: pmullw {{\.LCPI.*}}, %xmm2 ; X86-SSE2-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE2-NEXT: psrlw $8, %xmm2 ; X86-SSE2-NEXT: psrlw $8, %xmm2
; X86-SSE2-NEXT: movdqa %xmm0, %xmm3 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm3
; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3],xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7] ; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3],xmm3[4],xmm1[4],xmm3[5],xmm1[5],xmm3[6],xmm1[6],xmm3[7],xmm1[7]
; X86-SSE2-NEXT: pmullw {{\.LCPI.*}}, %xmm3 ; X86-SSE2-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm3
; X86-SSE2-NEXT: psrlw $8, %xmm3 ; X86-SSE2-NEXT: psrlw $8, %xmm3
; X86-SSE2-NEXT: packuswb %xmm2, %xmm3 ; X86-SSE2-NEXT: packuswb %xmm2, %xmm3
; X86-SSE2-NEXT: movdqa %xmm0, %xmm1 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm1
; X86-SSE2-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15] ; X86-SSE2-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; X86-SSE2-NEXT: pmullw {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
; X86-SSE2-NEXT: pand %xmm2, %xmm1 ; X86-SSE2-NEXT: pand %xmm2, %xmm1
; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; X86-SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X86-SSE2-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pand %xmm2, %xmm0 ; X86-SSE2-NEXT: pand %xmm2, %xmm0
; X86-SSE2-NEXT: packuswb %xmm1, %xmm0 ; X86-SSE2-NEXT: packuswb %xmm1, %xmm0
; X86-SSE2-NEXT: por %xmm3, %xmm0 ; X86-SSE2-NEXT: por %xmm3, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
%shl = shl <16 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1> %shl = shl <16 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1>
%lshr = lshr <16 x i8> %a, <i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7> %lshr = lshr <16 x i8> %a, <i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7>
%or = or <16 x i8> %shl, %lshr %or = or <16 x i8> %shl, %lshr
ret <16 x i8> %or ret <16 x i8> %or
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; XOP: # %bb.0: ; XOP: # %bb.0:
; XOP-NEXT: vprotb $4, %xmm0, %xmm0 ; XOP-NEXT: vprotb $4, %xmm0, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; X86-SSE2-LABEL: splatconstant_rotate_v16i8: ; X86-SSE2-LABEL: splatconstant_rotate_v16i8:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movdqa %xmm0, %xmm1 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm1
; X86-SSE2-NEXT: psrlw $4, %xmm1 ; X86-SSE2-NEXT: psrlw $4, %xmm1
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: psllw $4, %xmm0 ; X86-SSE2-NEXT: psllw $4, %xmm0
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: por %xmm1, %xmm0 ; X86-SSE2-NEXT: por %xmm1, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
%shl = shl <16 x i8> %a, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4> %shl = shl <16 x i8> %a, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
%lshr = lshr <16 x i8> %a, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4> %lshr = lshr <16 x i8> %a, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
%or = or <16 x i8> %shl, %lshr %or = or <16 x i8> %shl, %lshr
ret <16 x i8> %or ret <16 x i8> %or
} }
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; XOP: # %bb.0: ; XOP: # %bb.0:
; XOP-NEXT: vprotq $15, %xmm0, %xmm0 ; XOP-NEXT: vprotq $15, %xmm0, %xmm0
; XOP-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; XOP-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; X86-SSE2-LABEL: splatconstant_rotate_mask_v2i64: ; X86-SSE2-LABEL: splatconstant_rotate_mask_v2i64:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: psrlq $49, %xmm0 ; X86-SSE2-NEXT: psrlq $49, %xmm0
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
%shl = shl <2 x i64> %a, <i64 15, i64 15> %shl = shl <2 x i64> %a, <i64 15, i64 15>
%lshr = lshr <2 x i64> %a, <i64 49, i64 49> %lshr = lshr <2 x i64> %a, <i64 49, i64 49>
%rmask = and <2 x i64> %lshr, <i64 255, i64 127> %rmask = and <2 x i64> %lshr, <i64 255, i64 127>
%lmask = and <2 x i64> %shl, <i64 65, i64 33> %lmask = and <2 x i64> %shl, <i64 65, i64 33>
%or = or <2 x i64> %lmask, %rmask %or = or <2 x i64> %lmask, %rmask
ret <2 x i64> %or ret <2 x i64> %or
} }
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; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; X86-SSE2-LABEL: splatconstant_rotate_mask_v4i32: ; X86-SSE2-LABEL: splatconstant_rotate_mask_v4i32:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movdqa %xmm0, %xmm1 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm1
; X86-SSE2-NEXT: psrld $28, %xmm1 ; X86-SSE2-NEXT: psrld $28, %xmm1
; X86-SSE2-NEXT: pslld $4, %xmm0 ; X86-SSE2-NEXT: pslld $4, %xmm0
; X86-SSE2-NEXT: por %xmm1, %xmm0 ; X86-SSE2-NEXT: por %xmm1, %xmm0
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
%shl = shl <4 x i32> %a, <i32 4, i32 4, i32 4, i32 4> %shl = shl <4 x i32> %a, <i32 4, i32 4, i32 4, i32 4>
%lshr = lshr <4 x i32> %a, <i32 28, i32 28, i32 28, i32 28> %lshr = lshr <4 x i32> %a, <i32 28, i32 28, i32 28, i32 28>
%rmask = and <4 x i32> %lshr, <i32 127, i32 255, i32 511, i32 1023> %rmask = and <4 x i32> %lshr, <i32 127, i32 255, i32 511, i32 1023>
%lmask = and <4 x i32> %shl, <i32 1023, i32 511, i32 255, i32 127> %lmask = and <4 x i32> %shl, <i32 1023, i32 511, i32 255, i32 127>
%or = or <4 x i32> %lmask, %rmask %or = or <4 x i32> %lmask, %rmask
ret <4 x i32> %or ret <4 x i32> %or
} }
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; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; X86-SSE2-LABEL: splatconstant_rotate_mask_v8i16: ; X86-SSE2-LABEL: splatconstant_rotate_mask_v8i16:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movdqa %xmm0, %xmm1 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm1
; X86-SSE2-NEXT: psrlw $11, %xmm1 ; X86-SSE2-NEXT: psrlw $11, %xmm1
; X86-SSE2-NEXT: psllw $5, %xmm0 ; X86-SSE2-NEXT: psllw $5, %xmm0
; X86-SSE2-NEXT: por %xmm1, %xmm0 ; X86-SSE2-NEXT: por %xmm1, %xmm0
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
%shl = shl <8 x i16> %a, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5> %shl = shl <8 x i16> %a, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
%lshr = lshr <8 x i16> %a, <i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11> %lshr = lshr <8 x i16> %a, <i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11>
%rmask = and <8 x i16> %lshr, <i16 55, i16 55, i16 55, i16 55, i16 55, i16 55, i16 55, i16 55> %rmask = and <8 x i16> %lshr, <i16 55, i16 55, i16 55, i16 55, i16 55, i16 55, i16 55, i16 55>
%lmask = and <8 x i16> %shl, <i16 33, i16 33, i16 33, i16 33, i16 33, i16 33, i16 33, i16 33> %lmask = and <8 x i16> %shl, <i16 33, i16 33, i16 33, i16 33, i16 33, i16 33, i16 33, i16 33>
%or = or <8 x i16> %lmask, %rmask %or = or <8 x i16> %lmask, %rmask
ret <8 x i16> %or ret <8 x i16> %or
} }
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; XOP-NEXT: vprotb $4, %xmm0, %xmm0 ; XOP-NEXT: vprotb $4, %xmm0, %xmm0
; XOP-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; XOP-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; X86-SSE2-LABEL: splatconstant_rotate_mask_v16i8: ; X86-SSE2-LABEL: splatconstant_rotate_mask_v16i8:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movdqa %xmm0, %xmm1 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm1
; X86-SSE2-NEXT: psrlw $4, %xmm1 ; X86-SSE2-NEXT: psrlw $4, %xmm1
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm1 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE2-NEXT: psllw $4, %xmm0 ; X86-SSE2-NEXT: psllw $4, %xmm0
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: por %xmm1, %xmm0 ; X86-SSE2-NEXT: por %xmm1, %xmm0
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
%shl = shl <16 x i8> %a, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4> %shl = shl <16 x i8> %a, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
%lshr = lshr <16 x i8> %a, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4> %lshr = lshr <16 x i8> %a, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
%rmask = and <16 x i8> %lshr, <i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55> %rmask = and <16 x i8> %lshr, <i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55, i8 55>
%lmask = and <16 x i8> %shl, <i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33> %lmask = and <16 x i8> %shl, <i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33>
%or = or <16 x i8> %lmask, %rmask %or = or <16 x i8> %lmask, %rmask
ret <16 x i8> %or ret <16 x i8> %or
} }
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; XOP-NEXT: retq ; XOP-NEXT: retq
; ;
; X86-SSE2-LABEL: rot16_demandedbits: ; X86-SSE2-LABEL: rot16_demandedbits:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: movdqa %xmm0, %xmm1 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm1
; X86-SSE2-NEXT: psrld $11, %xmm1 ; X86-SSE2-NEXT: psrld $11, %xmm1
; X86-SSE2-NEXT: pslld $11, %xmm0 ; X86-SSE2-NEXT: pslld $11, %xmm0
; X86-SSE2-NEXT: por %xmm1, %xmm0 ; X86-SSE2-NEXT: por %xmm1, %xmm0
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
%t0 = lshr <4 x i32> %x, <i32 11, i32 11, i32 11, i32 11> %t0 = lshr <4 x i32> %x, <i32 11, i32 11, i32 11, i32 11>
%t1 = shl <4 x i32> %x, <i32 11, i32 11, i32 11, i32 11> %t1 = shl <4 x i32> %x, <i32 11, i32 11, i32 11, i32 11>
%t2 = or <4 x i32> %t0, %t1 %t2 = or <4 x i32> %t0, %t1
%t3 = and <4 x i32> %t2, <i32 65535, i32 65535, i32 65535, i32 65535> %t3 = and <4 x i32> %t2, <i32 65535, i32 65535, i32 65535, i32 65535>
ret <4 x i32> %t3 ret <4 x i32> %t3
} }
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llvm/test/CodeGen/X86/vector-sext.ll

Show First 20 Lines • Show All 3,785 Lines • ▼ Show 20 Lines
; AVX512-NEXT: vpsraq $58, %zmm0, %zmm0 ; AVX512-NEXT: vpsraq $58, %zmm0, %zmm0
; AVX512-NEXT: retq ; AVX512-NEXT: retq
; ;
; X86-SSE2-LABEL: sext_8i6_to_8i64: ; X86-SSE2-LABEL: sext_8i6_to_8i64:
; X86-SSE2: # %bb.0: # %entry ; X86-SSE2: # %bb.0: # %entry
; X86-SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] ; X86-SSE2-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[0,0,0,0] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[0,0,0,0]
; X86-SSE2-NEXT: paddw {{\.LCPI.*}}, %xmm3 ; X86-SSE2-NEXT: paddw {{\.LCPI[0-9]+_[0-9]+}}, %xmm3
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,0,0,0] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,0,0,0]
; X86-SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,5,5,5] ; X86-SSE2-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,5,5,5]
; X86-SSE2-NEXT: psllq $58, %xmm0 ; X86-SSE2-NEXT: psllq $58, %xmm0
; X86-SSE2-NEXT: movdqa %xmm0, %xmm1 ; X86-SSE2-NEXT: movdqa %xmm0, %xmm1
; X86-SSE2-NEXT: psrad $31, %xmm1 ; X86-SSE2-NEXT: psrad $31, %xmm1
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]
; X86-SSE2-NEXT: psrad $26, %xmm0 ; X86-SSE2-NEXT: psrad $26, %xmm0
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
Show All 27 Lines
; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1] ; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1]
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-SSE41-LABEL: sext_8i6_to_8i64: ; X86-SSE41-LABEL: sext_8i6_to_8i64:
; X86-SSE41: # %bb.0: # %entry ; X86-SSE41: # %bb.0: # %entry
; X86-SSE41-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-SSE41-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-SSE41-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7] ; X86-SSE41-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,0,0,4,5,6,7]
; X86-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[0,0,0,0] ; X86-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[0,0,0,0]
; X86-SSE41-NEXT: paddw {{\.LCPI.*}}, %xmm3 ; X86-SSE41-NEXT: paddw {{\.LCPI[0-9]+_[0-9]+}}, %xmm3
; X86-SSE41-NEXT: pmovzxwq {{.*#+}} xmm0 = xmm3[0],zero,zero,zero,xmm3[1],zero,zero,zero ; X86-SSE41-NEXT: pmovzxwq {{.*#+}} xmm0 = xmm3[0],zero,zero,zero,xmm3[1],zero,zero,zero
; X86-SSE41-NEXT: psllq $58, %xmm0 ; X86-SSE41-NEXT: psllq $58, %xmm0
; X86-SSE41-NEXT: movdqa %xmm0, %xmm1 ; X86-SSE41-NEXT: movdqa %xmm0, %xmm1
; X86-SSE41-NEXT: psrad $31, %xmm1 ; X86-SSE41-NEXT: psrad $31, %xmm1
; X86-SSE41-NEXT: psrad $26, %xmm0 ; X86-SSE41-NEXT: psrad $26, %xmm0
; X86-SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; X86-SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
; X86-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; X86-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; X86-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,1,1,1] ; X86-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,1,1,1]
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llvm/test/CodeGen/X86/vector-shift-ashr-128.ll

Show First 20 Lines • Show All 1,249 Lines • ▼ Show 20 Lines
; AVX512BWVL-NEXT: vzeroupper ; AVX512BWVL-NEXT: vzeroupper
; AVX512BWVL-NEXT: retq ; AVX512BWVL-NEXT: retq
; ;
; X86-SSE-LABEL: constant_shift_v16i8: ; X86-SSE-LABEL: constant_shift_v16i8:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: movdqa %xmm0, %xmm1 ; X86-SSE-NEXT: movdqa %xmm0, %xmm1
; X86-SSE-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15] ; X86-SSE-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8],xmm0[8],xmm1[9],xmm0[9],xmm1[10],xmm0[10],xmm1[11],xmm0[11],xmm1[12],xmm0[12],xmm1[13],xmm0[13],xmm1[14],xmm0[14],xmm1[15],xmm0[15]
; X86-SSE-NEXT: psraw $8, %xmm1 ; X86-SSE-NEXT: psraw $8, %xmm1
; X86-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm1 ; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE-NEXT: psrlw $8, %xmm1 ; X86-SSE-NEXT: psrlw $8, %xmm1
; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X86-SSE-NEXT: psraw $8, %xmm0 ; X86-SSE-NEXT: psraw $8, %xmm0
; X86-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: psrlw $8, %xmm0 ; X86-SSE-NEXT: psrlw $8, %xmm0
; X86-SSE-NEXT: packuswb %xmm1, %xmm0 ; X86-SSE-NEXT: packuswb %xmm1, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = ashr <16 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0> %shift = ashr <16 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
ret <16 x i8> %shift ret <16 x i8> %shift
} }
; ;
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; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16] ; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
; AVX512VL-NEXT: vpternlogq $108, {{.*}}(%rip), %xmm1, %xmm0 ; AVX512VL-NEXT: vpternlogq $108, {{.*}}(%rip), %xmm1, %xmm0
; AVX512VL-NEXT: vpsubb %xmm1, %xmm0, %xmm0 ; AVX512VL-NEXT: vpsubb %xmm1, %xmm0, %xmm0
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
; X86-SSE-LABEL: splatconstant_shift_v16i8: ; X86-SSE-LABEL: splatconstant_shift_v16i8:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: psrlw $3, %xmm0 ; X86-SSE-NEXT: psrlw $3, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16] ; X86-SSE-NEXT: movdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
; X86-SSE-NEXT: pxor %xmm1, %xmm0 ; X86-SSE-NEXT: pxor %xmm1, %xmm0
; X86-SSE-NEXT: psubb %xmm1, %xmm0 ; X86-SSE-NEXT: psubb %xmm1, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = ashr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> %shift = ashr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <16 x i8> %shift ret <16 x i8> %shift
} }

llvm/test/CodeGen/X86/vector-shift-ashr-256.ll

Show First 20 Lines • Show All 1,152 Lines • ▼ Show 20 Lines
; X86-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7] ; X86-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
; X86-AVX1-NEXT: vpsrad $8, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpsrad $8, %xmm0, %xmm0
; X86-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7] ; X86-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; X86-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; X86-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: constant_shift_v8i32: ; X86-AVX2-LABEL: constant_shift_v8i32:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpsravd {{\.LCPI.*}}, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpsravd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-AVX2-NEXT: retl ; X86-AVX2-NEXT: retl
%shift = ashr <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 8, i32 7> %shift = ashr <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 8, i32 7>
ret <8 x i32> %shift ret <8 x i32> %shift
} }
define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) nounwind { define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) nounwind {
; AVX1-LABEL: constant_shift_v16i16: ; AVX1-LABEL: constant_shift_v16i16:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
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; ;
; AVX512BWVL-LABEL: constant_shift_v16i16: ; AVX512BWVL-LABEL: constant_shift_v16i16:
; AVX512BWVL: # %bb.0: ; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vpsravw {{.*}}(%rip), %ymm0, %ymm0 ; AVX512BWVL-NEXT: vpsravw {{.*}}(%rip), %ymm0, %ymm0
; AVX512BWVL-NEXT: retq ; AVX512BWVL-NEXT: retq
; ;
; X86-AVX1-LABEL: constant_shift_v16i16: ; X86-AVX1-LABEL: constant_shift_v16i16:
; X86-AVX1: # %bb.0: ; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vpmulhw {{\.LCPI.*}}, %xmm0, %xmm1 ; X86-AVX1-NEXT: vpmulhw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm1
; X86-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3,4,5,6,7] ; X86-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3,4,5,6,7]
; X86-AVX1-NEXT: vpsraw $1, %xmm0, %xmm2 ; X86-AVX1-NEXT: vpsraw $1, %xmm0, %xmm2
; X86-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2,3,4,5,6,7] ; X86-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2,3,4,5,6,7]
; X86-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; X86-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; X86-AVX1-NEXT: vpmulhw {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpmulhw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; X86-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: constant_shift_v16i16: ; X86-AVX2-LABEL: constant_shift_v16i16:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpmulhw {{\.LCPI.*}}, %ymm0, %ymm1 ; X86-AVX2-NEXT: vpmulhw {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm1
; X86-AVX2-NEXT: vpblendw {{.*#+}} xmm2 = xmm0[0],xmm1[1,2,3,4,5,6,7] ; X86-AVX2-NEXT: vpblendw {{.*#+}} xmm2 = xmm0[0],xmm1[1,2,3,4,5,6,7]
; X86-AVX2-NEXT: vpsraw $1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpsraw $1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2,3,4,5,6,7] ; X86-AVX2-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2,3,4,5,6,7]
; X86-AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; X86-AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7]
; X86-AVX2-NEXT: retl ; X86-AVX2-NEXT: retl
%shift = ashr <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15> %shift = ashr <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
ret <16 x i16> %shift ret <16 x i16> %shift
} }
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; X86-AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
; X86-AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; X86-AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: constant_shift_v32i8: ; X86-AVX2-LABEL: constant_shift_v32i8:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpunpckhbw {{.*#+}} ymm1 = ymm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31] ; X86-AVX2-NEXT: vpunpckhbw {{.*#+}} ymm1 = ymm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]
; X86-AVX2-NEXT: vpsraw $8, %ymm1, %ymm1 ; X86-AVX2-NEXT: vpsraw $8, %ymm1, %ymm1
; X86-AVX2-NEXT: vpmullw {{\.LCPI.*}}, %ymm1, %ymm1 ; X86-AVX2-NEXT: vpmullw {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm1
; X86-AVX2-NEXT: vpsrlw $8, %ymm1, %ymm1 ; X86-AVX2-NEXT: vpsrlw $8, %ymm1, %ymm1
; X86-AVX2-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23] ; X86-AVX2-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]
; X86-AVX2-NEXT: vpsraw $8, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpsraw $8, %ymm0, %ymm0
; X86-AVX2-NEXT: vpmullw {{\.LCPI.*}}, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpmullw {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-AVX2-NEXT: vpsrlw $8, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpsrlw $8, %ymm0, %ymm0
; X86-AVX2-NEXT: vpackuswb %ymm1, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpackuswb %ymm1, %ymm0, %ymm0
; X86-AVX2-NEXT: retl ; X86-AVX2-NEXT: retl
%shift = ashr <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0> %shift = ashr <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
ret <32 x i8> %shift ret <32 x i8> %shift
} }
; ;
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; X86-AVX1-NEXT: vpxor %xmm3, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpxor %xmm3, %xmm0, %xmm0
; X86-AVX1-NEXT: vpsubb %xmm3, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpsubb %xmm3, %xmm0, %xmm0
; X86-AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; X86-AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: splatconstant_shift_v32i8: ; X86-AVX2-LABEL: splatconstant_shift_v32i8:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpsrlw $3, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpsrlw $3, %ymm0, %ymm0
; X86-AVX2-NEXT: vpand {{\.LCPI.*}}, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16] ; X86-AVX2-NEXT: vmovdqa {{.*#+}} ymm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
; X86-AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0
; X86-AVX2-NEXT: vpsubb %ymm1, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpsubb %ymm1, %ymm0, %ymm0
; X86-AVX2-NEXT: retl ; X86-AVX2-NEXT: retl
%shift = ashr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> %shift = ashr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <32 x i8> %shift ret <32 x i8> %shift
} }

llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll

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; ;
; X86-SSE-LABEL: constant_shift_v8i8: ; X86-SSE-LABEL: constant_shift_v8i8:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pxor %xmm1, %xmm1 ; X86-SSE-NEXT: pxor %xmm1, %xmm1
; X86-SSE-NEXT: movdqa %xmm0, %xmm2 ; X86-SSE-NEXT: movdqa %xmm0, %xmm2
; X86-SSE-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15] ; X86-SSE-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X86-SSE-NEXT: psraw $8, %xmm0 ; X86-SSE-NEXT: psraw $8, %xmm0
; X86-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: psrlw $8, %xmm0 ; X86-SSE-NEXT: psrlw $8, %xmm0
; X86-SSE-NEXT: packuswb %xmm2, %xmm0 ; X86-SSE-NEXT: packuswb %xmm2, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = ashr <8 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7> %shift = ashr <8 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7>
ret <8 x i8> %shift ret <8 x i8> %shift
} }
define <4 x i8> @constant_shift_v4i8(<4 x i8> %a) nounwind { define <4 x i8> @constant_shift_v4i8(<4 x i8> %a) nounwind {
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; ;
; X86-SSE-LABEL: constant_shift_v4i8: ; X86-SSE-LABEL: constant_shift_v4i8:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pxor %xmm1, %xmm1 ; X86-SSE-NEXT: pxor %xmm1, %xmm1
; X86-SSE-NEXT: movdqa %xmm0, %xmm2 ; X86-SSE-NEXT: movdqa %xmm0, %xmm2
; X86-SSE-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15] ; X86-SSE-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X86-SSE-NEXT: psraw $8, %xmm0 ; X86-SSE-NEXT: psraw $8, %xmm0
; X86-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: psrlw $8, %xmm0 ; X86-SSE-NEXT: psrlw $8, %xmm0
; X86-SSE-NEXT: packuswb %xmm2, %xmm0 ; X86-SSE-NEXT: packuswb %xmm2, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = ashr <4 x i8> %a, <i8 0, i8 1, i8 2, i8 3> %shift = ashr <4 x i8> %a, <i8 0, i8 1, i8 2, i8 3>
ret <4 x i8> %shift ret <4 x i8> %shift
} }
define <2 x i8> @constant_shift_v2i8(<2 x i8> %a) nounwind { define <2 x i8> @constant_shift_v2i8(<2 x i8> %a) nounwind {
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; ;
; X86-SSE-LABEL: constant_shift_v2i8: ; X86-SSE-LABEL: constant_shift_v2i8:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pxor %xmm1, %xmm1 ; X86-SSE-NEXT: pxor %xmm1, %xmm1
; X86-SSE-NEXT: movdqa %xmm0, %xmm2 ; X86-SSE-NEXT: movdqa %xmm0, %xmm2
; X86-SSE-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15] ; X86-SSE-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X86-SSE-NEXT: psraw $8, %xmm0 ; X86-SSE-NEXT: psraw $8, %xmm0
; X86-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: psrlw $8, %xmm0 ; X86-SSE-NEXT: psrlw $8, %xmm0
; X86-SSE-NEXT: packuswb %xmm2, %xmm0 ; X86-SSE-NEXT: packuswb %xmm2, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = ashr <2 x i8> %a, <i8 2, i8 3> %shift = ashr <2 x i8> %a, <i8 2, i8 3>
ret <2 x i8> %shift ret <2 x i8> %shift
} }
; ;
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; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16] ; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
; AVX512VL-NEXT: vpternlogq $108, {{.*}}(%rip), %xmm1, %xmm0 ; AVX512VL-NEXT: vpternlogq $108, {{.*}}(%rip), %xmm1, %xmm0
; AVX512VL-NEXT: vpsubb %xmm1, %xmm0, %xmm0 ; AVX512VL-NEXT: vpsubb %xmm1, %xmm0, %xmm0
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
; X86-SSE-LABEL: splatconstant_shift_v8i8: ; X86-SSE-LABEL: splatconstant_shift_v8i8:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: psrlw $3, %xmm0 ; X86-SSE-NEXT: psrlw $3, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16] ; X86-SSE-NEXT: movdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
; X86-SSE-NEXT: pxor %xmm1, %xmm0 ; X86-SSE-NEXT: pxor %xmm1, %xmm0
; X86-SSE-NEXT: psubb %xmm1, %xmm0 ; X86-SSE-NEXT: psubb %xmm1, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = ashr <8 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> %shift = ashr <8 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <8 x i8> %shift ret <8 x i8> %shift
} }
Show All 36 Lines
; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16] ; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
; AVX512VL-NEXT: vpternlogq $108, {{.*}}(%rip), %xmm1, %xmm0 ; AVX512VL-NEXT: vpternlogq $108, {{.*}}(%rip), %xmm1, %xmm0
; AVX512VL-NEXT: vpsubb %xmm1, %xmm0, %xmm0 ; AVX512VL-NEXT: vpsubb %xmm1, %xmm0, %xmm0
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
; X86-SSE-LABEL: splatconstant_shift_v4i8: ; X86-SSE-LABEL: splatconstant_shift_v4i8:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: psrlw $3, %xmm0 ; X86-SSE-NEXT: psrlw $3, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16] ; X86-SSE-NEXT: movdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
; X86-SSE-NEXT: pxor %xmm1, %xmm0 ; X86-SSE-NEXT: pxor %xmm1, %xmm0
; X86-SSE-NEXT: psubb %xmm1, %xmm0 ; X86-SSE-NEXT: psubb %xmm1, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = ashr <4 x i8> %a, <i8 3, i8 3, i8 3, i8 3> %shift = ashr <4 x i8> %a, <i8 3, i8 3, i8 3, i8 3>
ret <4 x i8> %shift ret <4 x i8> %shift
} }
Show All 36 Lines
; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16] ; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
; AVX512VL-NEXT: vpternlogq $108, {{.*}}(%rip), %xmm1, %xmm0 ; AVX512VL-NEXT: vpternlogq $108, {{.*}}(%rip), %xmm1, %xmm0
; AVX512VL-NEXT: vpsubb %xmm1, %xmm0, %xmm0 ; AVX512VL-NEXT: vpsubb %xmm1, %xmm0, %xmm0
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
; X86-SSE-LABEL: splatconstant_shift_v2i8: ; X86-SSE-LABEL: splatconstant_shift_v2i8:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: psrlw $3, %xmm0 ; X86-SSE-NEXT: psrlw $3, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: movdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16] ; X86-SSE-NEXT: movdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
; X86-SSE-NEXT: pxor %xmm1, %xmm0 ; X86-SSE-NEXT: pxor %xmm1, %xmm0
; X86-SSE-NEXT: psubb %xmm1, %xmm0 ; X86-SSE-NEXT: psubb %xmm1, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = ashr <2 x i8> %a, <i8 3, i8 3> %shift = ashr <2 x i8> %a, <i8 3, i8 3>
ret <2 x i8> %shift ret <2 x i8> %shift
} }

llvm/test/CodeGen/X86/vector-shift-lshr-128.ll

Show First 20 Lines • Show All 482 Lines • ▼ Show 20 Lines
; X86-SSE-NEXT: psllw $5, %xmm1 ; X86-SSE-NEXT: psllw $5, %xmm1
; X86-SSE-NEXT: pxor %xmm2, %xmm2 ; X86-SSE-NEXT: pxor %xmm2, %xmm2
; X86-SSE-NEXT: pxor %xmm3, %xmm3 ; X86-SSE-NEXT: pxor %xmm3, %xmm3
; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3 ; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3
; X86-SSE-NEXT: movdqa %xmm3, %xmm4 ; X86-SSE-NEXT: movdqa %xmm3, %xmm4
; X86-SSE-NEXT: pandn %xmm0, %xmm4 ; X86-SSE-NEXT: pandn %xmm0, %xmm4
; X86-SSE-NEXT: psrlw $4, %xmm0 ; X86-SSE-NEXT: psrlw $4, %xmm0
; X86-SSE-NEXT: pand %xmm3, %xmm0 ; X86-SSE-NEXT: pand %xmm3, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: por %xmm4, %xmm0 ; X86-SSE-NEXT: por %xmm4, %xmm0
; X86-SSE-NEXT: paddb %xmm1, %xmm1 ; X86-SSE-NEXT: paddb %xmm1, %xmm1
; X86-SSE-NEXT: pxor %xmm3, %xmm3 ; X86-SSE-NEXT: pxor %xmm3, %xmm3
; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3 ; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3
; X86-SSE-NEXT: movdqa %xmm3, %xmm4 ; X86-SSE-NEXT: movdqa %xmm3, %xmm4
; X86-SSE-NEXT: pandn %xmm0, %xmm4 ; X86-SSE-NEXT: pandn %xmm0, %xmm4
; X86-SSE-NEXT: psrlw $2, %xmm0 ; X86-SSE-NEXT: psrlw $2, %xmm0
; X86-SSE-NEXT: pand %xmm3, %xmm0 ; X86-SSE-NEXT: pand %xmm3, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: por %xmm4, %xmm0 ; X86-SSE-NEXT: por %xmm4, %xmm0
; X86-SSE-NEXT: paddb %xmm1, %xmm1 ; X86-SSE-NEXT: paddb %xmm1, %xmm1
; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm2 ; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm2
; X86-SSE-NEXT: movdqa %xmm2, %xmm1 ; X86-SSE-NEXT: movdqa %xmm2, %xmm1
; X86-SSE-NEXT: pandn %xmm0, %xmm1 ; X86-SSE-NEXT: pandn %xmm0, %xmm1
; X86-SSE-NEXT: psrlw $1, %xmm0 ; X86-SSE-NEXT: psrlw $1, %xmm0
; X86-SSE-NEXT: pand %xmm2, %xmm0 ; X86-SSE-NEXT: pand %xmm2, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: por %xmm1, %xmm0 ; X86-SSE-NEXT: por %xmm1, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = lshr <16 x i8> %a, %b %shift = lshr <16 x i8> %a, %b
ret <16 x i8> %shift ret <16 x i8> %shift
} }
; ;
; Uniform Variable Shifts ; Uniform Variable Shifts
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; AVX512BWVL-NEXT: vpsrlvw {{.*}}(%rip), %xmm0, %xmm0 ; AVX512BWVL-NEXT: vpsrlvw {{.*}}(%rip), %xmm0, %xmm0
; AVX512BWVL-NEXT: retq ; AVX512BWVL-NEXT: retq
; ;
; X86-SSE-LABEL: constant_shift_v8i16: ; X86-SSE-LABEL: constant_shift_v8i16:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: movdqa {{.*#+}} xmm1 = [0,65535,65535,65535,65535,65535,65535,65535] ; X86-SSE-NEXT: movdqa {{.*#+}} xmm1 = [0,65535,65535,65535,65535,65535,65535,65535]
; X86-SSE-NEXT: movdqa %xmm1, %xmm2 ; X86-SSE-NEXT: movdqa %xmm1, %xmm2
; X86-SSE-NEXT: pandn %xmm0, %xmm2 ; X86-SSE-NEXT: pandn %xmm0, %xmm2
; X86-SSE-NEXT: pmulhuw {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmulhuw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: pand %xmm1, %xmm0 ; X86-SSE-NEXT: pand %xmm1, %xmm0
; X86-SSE-NEXT: por %xmm2, %xmm0 ; X86-SSE-NEXT: por %xmm2, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = lshr <8 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7> %shift = lshr <8 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
ret <8 x i16> %shift ret <8 x i16> %shift
} }
define <16 x i8> @constant_shift_v16i8(<16 x i8> %a) nounwind { define <16 x i8> @constant_shift_v16i8(<16 x i8> %a) nounwind {
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; AVX512BWVL-NEXT: vzeroupper ; AVX512BWVL-NEXT: vzeroupper
; AVX512BWVL-NEXT: retq ; AVX512BWVL-NEXT: retq
; ;
; X86-SSE-LABEL: constant_shift_v16i8: ; X86-SSE-LABEL: constant_shift_v16i8:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pxor %xmm1, %xmm1 ; X86-SSE-NEXT: pxor %xmm1, %xmm1
; X86-SSE-NEXT: movdqa %xmm0, %xmm2 ; X86-SSE-NEXT: movdqa %xmm0, %xmm2
; X86-SSE-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15] ; X86-SSE-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
; X86-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm2 ; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm2
; X86-SSE-NEXT: psrlw $8, %xmm2 ; X86-SSE-NEXT: psrlw $8, %xmm2
; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] ; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; X86-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: psrlw $8, %xmm0 ; X86-SSE-NEXT: psrlw $8, %xmm0
; X86-SSE-NEXT: packuswb %xmm2, %xmm0 ; X86-SSE-NEXT: packuswb %xmm2, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = lshr <16 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0> %shift = lshr <16 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
ret <16 x i8> %shift ret <16 x i8> %shift
} }
; ;
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; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsrlw $3, %xmm0, %xmm0 ; AVX512VL-NEXT: vpsrlw $3, %xmm0, %xmm0
; AVX512VL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; AVX512VL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
; X86-SSE-LABEL: splatconstant_shift_v16i8: ; X86-SSE-LABEL: splatconstant_shift_v16i8:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: psrlw $3, %xmm0 ; X86-SSE-NEXT: psrlw $3, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = lshr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> %shift = lshr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <16 x i8> %shift ret <16 x i8> %shift
} }
define <4 x i32> @vector_variable_shift_right(<4 x i1> %cond, <4 x i32> %x, <4 x i32> %y, <4 x i32> %z) nounwind { define <4 x i32> @vector_variable_shift_right(<4 x i1> %cond, <4 x i32> %x, <4 x i32> %y, <4 x i32> %z) nounwind {
; SSE2-LABEL: vector_variable_shift_right: ; SSE2-LABEL: vector_variable_shift_right:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
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llvm/test/CodeGen/X86/vector-shift-lshr-256.ll

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; X86-AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
; X86-AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; X86-AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: var_shift_v32i8: ; X86-AVX2-LABEL: var_shift_v32i8:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpsllw $5, %ymm1, %ymm1 ; X86-AVX2-NEXT: vpsllw $5, %ymm1, %ymm1
; X86-AVX2-NEXT: vpsrlw $4, %ymm0, %ymm2 ; X86-AVX2-NEXT: vpsrlw $4, %ymm0, %ymm2
; X86-AVX2-NEXT: vpand {{\.LCPI.*}}, %ymm2, %ymm2 ; X86-AVX2-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm2, %ymm2
; X86-AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; X86-AVX2-NEXT: vpsrlw $2, %ymm0, %ymm2 ; X86-AVX2-NEXT: vpsrlw $2, %ymm0, %ymm2
; X86-AVX2-NEXT: vpand {{\.LCPI.*}}, %ymm2, %ymm2 ; X86-AVX2-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm2, %ymm2
; X86-AVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1 ; X86-AVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1
; X86-AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; X86-AVX2-NEXT: vpsrlw $1, %ymm0, %ymm2 ; X86-AVX2-NEXT: vpsrlw $1, %ymm0, %ymm2
; X86-AVX2-NEXT: vpand {{\.LCPI.*}}, %ymm2, %ymm2 ; X86-AVX2-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm2, %ymm2
; X86-AVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1 ; X86-AVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1
; X86-AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; X86-AVX2-NEXT: retl ; X86-AVX2-NEXT: retl
%shift = lshr <32 x i8> %a, %b %shift = lshr <32 x i8> %a, %b
ret <32 x i8> %shift ret <32 x i8> %shift
} }
; ;
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; X86-AVX1-NEXT: vpsrlq $7, %xmm0, %xmm2 ; X86-AVX1-NEXT: vpsrlq $7, %xmm0, %xmm2
; X86-AVX1-NEXT: vpsrlq $1, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpsrlq $1, %xmm0, %xmm0
; X86-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7] ; X86-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
; X86-AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; X86-AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: constant_shift_v4i64: ; X86-AVX2-LABEL: constant_shift_v4i64:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpsrlvq {{\.LCPI.*}}, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpsrlvq {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-AVX2-NEXT: retl ; X86-AVX2-NEXT: retl
%shift = lshr <4 x i64> %a, <i64 1, i64 7, i64 31, i64 62> %shift = lshr <4 x i64> %a, <i64 1, i64 7, i64 31, i64 62>
ret <4 x i64> %shift ret <4 x i64> %shift
} }
define <8 x i32> @constant_shift_v8i32(<8 x i32> %a) nounwind { define <8 x i32> @constant_shift_v8i32(<8 x i32> %a) nounwind {
; AVX1-LABEL: constant_shift_v8i32: ; AVX1-LABEL: constant_shift_v8i32:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
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; X86-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7] ; X86-AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
; X86-AVX1-NEXT: vpsrld $8, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpsrld $8, %xmm0, %xmm0
; X86-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7] ; X86-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
; X86-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; X86-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: constant_shift_v8i32: ; X86-AVX2-LABEL: constant_shift_v8i32:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpsrlvd {{\.LCPI.*}}, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpsrlvd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-AVX2-NEXT: retl ; X86-AVX2-NEXT: retl
%shift = lshr <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 8, i32 7> %shift = lshr <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 8, i32 7>
ret <8 x i32> %shift ret <8 x i32> %shift
} }
define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) nounwind { define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) nounwind {
; AVX1-LABEL: constant_shift_v16i16: ; AVX1-LABEL: constant_shift_v16i16:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
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; ;
; AVX512BWVL-LABEL: constant_shift_v16i16: ; AVX512BWVL-LABEL: constant_shift_v16i16:
; AVX512BWVL: # %bb.0: ; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vpsrlvw {{.*}}(%rip), %ymm0, %ymm0 ; AVX512BWVL-NEXT: vpsrlvw {{.*}}(%rip), %ymm0, %ymm0
; AVX512BWVL-NEXT: retq ; AVX512BWVL-NEXT: retq
; ;
; X86-AVX1-LABEL: constant_shift_v16i16: ; X86-AVX1-LABEL: constant_shift_v16i16:
; X86-AVX1: # %bb.0: ; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vpmulhuw {{\.LCPI.*}}, %xmm0, %xmm1 ; X86-AVX1-NEXT: vpmulhuw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm1
; X86-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3,4,5,6,7] ; X86-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3,4,5,6,7]
; X86-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; X86-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; X86-AVX1-NEXT: vpmulhuw {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpmulhuw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; X86-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: constant_shift_v16i16: ; X86-AVX2-LABEL: constant_shift_v16i16:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpmulhuw {{\.LCPI.*}}, %ymm0, %ymm1 ; X86-AVX2-NEXT: vpmulhuw {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm1
; X86-AVX2-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3,4,5,6,7] ; X86-AVX2-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3,4,5,6,7]
; X86-AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7] ; X86-AVX2-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7]
; X86-AVX2-NEXT: retl ; X86-AVX2-NEXT: retl
%shift = lshr <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15> %shift = lshr <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
ret <16 x i16> %shift ret <16 x i16> %shift
} }
define <32 x i8> @constant_shift_v32i8(<32 x i8> %a) nounwind { define <32 x i8> @constant_shift_v32i8(<32 x i8> %a) nounwind {
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; X86-AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
; X86-AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; X86-AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: constant_shift_v32i8: ; X86-AVX2-LABEL: constant_shift_v32i8:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; X86-AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X86-AVX2-NEXT: vpunpckhbw {{.*#+}} ymm2 = ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15],ymm0[24],ymm1[24],ymm0[25],ymm1[25],ymm0[26],ymm1[26],ymm0[27],ymm1[27],ymm0[28],ymm1[28],ymm0[29],ymm1[29],ymm0[30],ymm1[30],ymm0[31],ymm1[31] ; X86-AVX2-NEXT: vpunpckhbw {{.*#+}} ymm2 = ymm0[8],ymm1[8],ymm0[9],ymm1[9],ymm0[10],ymm1[10],ymm0[11],ymm1[11],ymm0[12],ymm1[12],ymm0[13],ymm1[13],ymm0[14],ymm1[14],ymm0[15],ymm1[15],ymm0[24],ymm1[24],ymm0[25],ymm1[25],ymm0[26],ymm1[26],ymm0[27],ymm1[27],ymm0[28],ymm1[28],ymm0[29],ymm1[29],ymm0[30],ymm1[30],ymm0[31],ymm1[31]
; X86-AVX2-NEXT: vpmullw {{\.LCPI.*}}, %ymm2, %ymm2 ; X86-AVX2-NEXT: vpmullw {{\.LCPI[0-9]+_[0-9]+}}, %ymm2, %ymm2
; X86-AVX2-NEXT: vpsrlw $8, %ymm2, %ymm2 ; X86-AVX2-NEXT: vpsrlw $8, %ymm2, %ymm2
; X86-AVX2-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[16],ymm1[16],ymm0[17],ymm1[17],ymm0[18],ymm1[18],ymm0[19],ymm1[19],ymm0[20],ymm1[20],ymm0[21],ymm1[21],ymm0[22],ymm1[22],ymm0[23],ymm1[23] ; X86-AVX2-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[4],ymm1[4],ymm0[5],ymm1[5],ymm0[6],ymm1[6],ymm0[7],ymm1[7],ymm0[16],ymm1[16],ymm0[17],ymm1[17],ymm0[18],ymm1[18],ymm0[19],ymm1[19],ymm0[20],ymm1[20],ymm0[21],ymm1[21],ymm0[22],ymm1[22],ymm0[23],ymm1[23]
; X86-AVX2-NEXT: vpmullw {{\.LCPI.*}}, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpmullw {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-AVX2-NEXT: vpsrlw $8, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpsrlw $8, %ymm0, %ymm0
; X86-AVX2-NEXT: vpackuswb %ymm2, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
; X86-AVX2-NEXT: retl ; X86-AVX2-NEXT: retl
%shift = lshr <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0> %shift = lshr <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
ret <32 x i8> %shift ret <32 x i8> %shift
} }
; ;
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; X86-AVX1-NEXT: vpsrlw $3, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpsrlw $3, %xmm0, %xmm0
; X86-AVX1-NEXT: vpand %xmm2, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpand %xmm2, %xmm0, %xmm0
; X86-AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; X86-AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: splatconstant_shift_v32i8: ; X86-AVX2-LABEL: splatconstant_shift_v32i8:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpsrlw $3, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpsrlw $3, %ymm0, %ymm0
; X86-AVX2-NEXT: vpand {{\.LCPI.*}}, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-AVX2-NEXT: retl ; X86-AVX2-NEXT: retl
%shift = lshr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> %shift = lshr <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <32 x i8> %shift ret <32 x i8> %shift
} }
define <4 x i32> @sh_trunc_sh_vec(<4 x i64> %x) { define <4 x i32> @sh_trunc_sh_vec(<4 x i64> %x) {
; AVX1-LABEL: sh_trunc_sh_vec: ; AVX1-LABEL: sh_trunc_sh_vec:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
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; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
; X86-AVX1-LABEL: sh_trunc_sh_vec: ; X86-AVX1-LABEL: sh_trunc_sh_vec:
; X86-AVX1: # %bb.0: ; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1 ; X86-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; X86-AVX1-NEXT: vpsrlq $36, %xmm1, %xmm1 ; X86-AVX1-NEXT: vpsrlq $36, %xmm1, %xmm1
; X86-AVX1-NEXT: vpsrlq $36, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpsrlq $36, %xmm0, %xmm0
; X86-AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; X86-AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
; X86-AVX1-NEXT: vandps {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX1-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vzeroupper ; X86-AVX1-NEXT: vzeroupper
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: sh_trunc_sh_vec: ; X86-AVX2-LABEL: sh_trunc_sh_vec:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpsrlq $36, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpsrlq $36, %ymm0, %ymm0
; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 ; X86-AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; X86-AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2] ; X86-AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
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llvm/test/CodeGen/X86/vector-shift-lshr-sub128.ll

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; X86-SSE-NEXT: psllw $5, %xmm1 ; X86-SSE-NEXT: psllw $5, %xmm1
; X86-SSE-NEXT: pxor %xmm2, %xmm2 ; X86-SSE-NEXT: pxor %xmm2, %xmm2
; X86-SSE-NEXT: pxor %xmm3, %xmm3 ; X86-SSE-NEXT: pxor %xmm3, %xmm3
; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3 ; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3
; X86-SSE-NEXT: movdqa %xmm3, %xmm4 ; X86-SSE-NEXT: movdqa %xmm3, %xmm4
; X86-SSE-NEXT: pandn %xmm0, %xmm4 ; X86-SSE-NEXT: pandn %xmm0, %xmm4
; X86-SSE-NEXT: psrlw $4, %xmm0 ; X86-SSE-NEXT: psrlw $4, %xmm0
; X86-SSE-NEXT: pand %xmm3, %xmm0 ; X86-SSE-NEXT: pand %xmm3, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: por %xmm4, %xmm0 ; X86-SSE-NEXT: por %xmm4, %xmm0
; X86-SSE-NEXT: paddb %xmm1, %xmm1 ; X86-SSE-NEXT: paddb %xmm1, %xmm1
; X86-SSE-NEXT: pxor %xmm3, %xmm3 ; X86-SSE-NEXT: pxor %xmm3, %xmm3
; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3 ; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3
; X86-SSE-NEXT: movdqa %xmm3, %xmm4 ; X86-SSE-NEXT: movdqa %xmm3, %xmm4
; X86-SSE-NEXT: pandn %xmm0, %xmm4 ; X86-SSE-NEXT: pandn %xmm0, %xmm4
; X86-SSE-NEXT: psrlw $2, %xmm0 ; X86-SSE-NEXT: psrlw $2, %xmm0
; X86-SSE-NEXT: pand %xmm3, %xmm0 ; X86-SSE-NEXT: pand %xmm3, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: por %xmm4, %xmm0 ; X86-SSE-NEXT: por %xmm4, %xmm0
; X86-SSE-NEXT: paddb %xmm1, %xmm1 ; X86-SSE-NEXT: paddb %xmm1, %xmm1
; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm2 ; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm2
; X86-SSE-NEXT: movdqa %xmm2, %xmm1 ; X86-SSE-NEXT: movdqa %xmm2, %xmm1
; X86-SSE-NEXT: pandn %xmm0, %xmm1 ; X86-SSE-NEXT: pandn %xmm0, %xmm1
; X86-SSE-NEXT: psrlw $1, %xmm0 ; X86-SSE-NEXT: psrlw $1, %xmm0
; X86-SSE-NEXT: pand %xmm2, %xmm0 ; X86-SSE-NEXT: pand %xmm2, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: por %xmm1, %xmm0 ; X86-SSE-NEXT: por %xmm1, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = lshr <8 x i8> %a, %b %shift = lshr <8 x i8> %a, %b
ret <8 x i8> %shift ret <8 x i8> %shift
} }
define <4 x i8> @var_shift_v4i8(<4 x i8> %a, <4 x i8> %b) nounwind { define <4 x i8> @var_shift_v4i8(<4 x i8> %a, <4 x i8> %b) nounwind {
; SSE2-LABEL: var_shift_v4i8: ; SSE2-LABEL: var_shift_v4i8:
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; X86-SSE-NEXT: psllw $5, %xmm1 ; X86-SSE-NEXT: psllw $5, %xmm1
; X86-SSE-NEXT: pxor %xmm2, %xmm2 ; X86-SSE-NEXT: pxor %xmm2, %xmm2
; X86-SSE-NEXT: pxor %xmm3, %xmm3 ; X86-SSE-NEXT: pxor %xmm3, %xmm3
; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3 ; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3
; X86-SSE-NEXT: movdqa %xmm3, %xmm4 ; X86-SSE-NEXT: movdqa %xmm3, %xmm4
; X86-SSE-NEXT: pandn %xmm0, %xmm4 ; X86-SSE-NEXT: pandn %xmm0, %xmm4
; X86-SSE-NEXT: psrlw $4, %xmm0 ; X86-SSE-NEXT: psrlw $4, %xmm0
; X86-SSE-NEXT: pand %xmm3, %xmm0 ; X86-SSE-NEXT: pand %xmm3, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: por %xmm4, %xmm0 ; X86-SSE-NEXT: por %xmm4, %xmm0
; X86-SSE-NEXT: paddb %xmm1, %xmm1 ; X86-SSE-NEXT: paddb %xmm1, %xmm1
; X86-SSE-NEXT: pxor %xmm3, %xmm3 ; X86-SSE-NEXT: pxor %xmm3, %xmm3
; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3 ; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3
; X86-SSE-NEXT: movdqa %xmm3, %xmm4 ; X86-SSE-NEXT: movdqa %xmm3, %xmm4
; X86-SSE-NEXT: pandn %xmm0, %xmm4 ; X86-SSE-NEXT: pandn %xmm0, %xmm4
; X86-SSE-NEXT: psrlw $2, %xmm0 ; X86-SSE-NEXT: psrlw $2, %xmm0
; X86-SSE-NEXT: pand %xmm3, %xmm0 ; X86-SSE-NEXT: pand %xmm3, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: por %xmm4, %xmm0 ; X86-SSE-NEXT: por %xmm4, %xmm0
; X86-SSE-NEXT: paddb %xmm1, %xmm1 ; X86-SSE-NEXT: paddb %xmm1, %xmm1
; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm2 ; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm2
; X86-SSE-NEXT: movdqa %xmm2, %xmm1 ; X86-SSE-NEXT: movdqa %xmm2, %xmm1
; X86-SSE-NEXT: pandn %xmm0, %xmm1 ; X86-SSE-NEXT: pandn %xmm0, %xmm1
; X86-SSE-NEXT: psrlw $1, %xmm0 ; X86-SSE-NEXT: psrlw $1, %xmm0
; X86-SSE-NEXT: pand %xmm2, %xmm0 ; X86-SSE-NEXT: pand %xmm2, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: por %xmm1, %xmm0 ; X86-SSE-NEXT: por %xmm1, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = lshr <4 x i8> %a, %b %shift = lshr <4 x i8> %a, %b
ret <4 x i8> %shift ret <4 x i8> %shift
} }
define <2 x i8> @var_shift_v2i8(<2 x i8> %a, <2 x i8> %b) nounwind { define <2 x i8> @var_shift_v2i8(<2 x i8> %a, <2 x i8> %b) nounwind {
; SSE2-LABEL: var_shift_v2i8: ; SSE2-LABEL: var_shift_v2i8:
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; X86-SSE-NEXT: psllw $5, %xmm1 ; X86-SSE-NEXT: psllw $5, %xmm1
; X86-SSE-NEXT: pxor %xmm2, %xmm2 ; X86-SSE-NEXT: pxor %xmm2, %xmm2
; X86-SSE-NEXT: pxor %xmm3, %xmm3 ; X86-SSE-NEXT: pxor %xmm3, %xmm3
; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3 ; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3
; X86-SSE-NEXT: movdqa %xmm3, %xmm4 ; X86-SSE-NEXT: movdqa %xmm3, %xmm4
; X86-SSE-NEXT: pandn %xmm0, %xmm4 ; X86-SSE-NEXT: pandn %xmm0, %xmm4
; X86-SSE-NEXT: psrlw $4, %xmm0 ; X86-SSE-NEXT: psrlw $4, %xmm0
; X86-SSE-NEXT: pand %xmm3, %xmm0 ; X86-SSE-NEXT: pand %xmm3, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: por %xmm4, %xmm0 ; X86-SSE-NEXT: por %xmm4, %xmm0
; X86-SSE-NEXT: paddb %xmm1, %xmm1 ; X86-SSE-NEXT: paddb %xmm1, %xmm1
; X86-SSE-NEXT: pxor %xmm3, %xmm3 ; X86-SSE-NEXT: pxor %xmm3, %xmm3
; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3 ; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3
; X86-SSE-NEXT: movdqa %xmm3, %xmm4 ; X86-SSE-NEXT: movdqa %xmm3, %xmm4
; X86-SSE-NEXT: pandn %xmm0, %xmm4 ; X86-SSE-NEXT: pandn %xmm0, %xmm4
; X86-SSE-NEXT: psrlw $2, %xmm0 ; X86-SSE-NEXT: psrlw $2, %xmm0
; X86-SSE-NEXT: pand %xmm3, %xmm0 ; X86-SSE-NEXT: pand %xmm3, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: por %xmm4, %xmm0 ; X86-SSE-NEXT: por %xmm4, %xmm0
; X86-SSE-NEXT: paddb %xmm1, %xmm1 ; X86-SSE-NEXT: paddb %xmm1, %xmm1
; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm2 ; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm2
; X86-SSE-NEXT: movdqa %xmm2, %xmm1 ; X86-SSE-NEXT: movdqa %xmm2, %xmm1
; X86-SSE-NEXT: pandn %xmm0, %xmm1 ; X86-SSE-NEXT: pandn %xmm0, %xmm1
; X86-SSE-NEXT: psrlw $1, %xmm0 ; X86-SSE-NEXT: psrlw $1, %xmm0
; X86-SSE-NEXT: pand %xmm2, %xmm0 ; X86-SSE-NEXT: pand %xmm2, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: por %xmm1, %xmm0 ; X86-SSE-NEXT: por %xmm1, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = lshr <2 x i8> %a, %b %shift = lshr <2 x i8> %a, %b
ret <2 x i8> %shift ret <2 x i8> %shift
} }
; ;
; Uniform Variable Shifts ; Uniform Variable Shifts
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; AVX512BWVL-NEXT: vpsrlvw {{.*}}(%rip), %xmm0, %xmm0 ; AVX512BWVL-NEXT: vpsrlvw {{.*}}(%rip), %xmm0, %xmm0
; AVX512BWVL-NEXT: retq ; AVX512BWVL-NEXT: retq
; ;
; X86-SSE-LABEL: constant_shift_v4i16: ; X86-SSE-LABEL: constant_shift_v4i16:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: movdqa {{.*#+}} xmm1 = [0,65535,65535,65535,65535,65535,65535,65535] ; X86-SSE-NEXT: movdqa {{.*#+}} xmm1 = [0,65535,65535,65535,65535,65535,65535,65535]
; X86-SSE-NEXT: movdqa %xmm1, %xmm2 ; X86-SSE-NEXT: movdqa %xmm1, %xmm2
; X86-SSE-NEXT: pandn %xmm0, %xmm2 ; X86-SSE-NEXT: pandn %xmm0, %xmm2
; X86-SSE-NEXT: pmulhuw {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmulhuw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: pand %xmm1, %xmm0 ; X86-SSE-NEXT: pand %xmm1, %xmm0
; X86-SSE-NEXT: por %xmm2, %xmm0 ; X86-SSE-NEXT: por %xmm2, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = lshr <4 x i16> %a, <i16 0, i16 1, i16 2, i16 3> %shift = lshr <4 x i16> %a, <i16 0, i16 1, i16 2, i16 3>
ret <4 x i16> %shift ret <4 x i16> %shift
} }
define <2 x i16> @constant_shift_v2i16(<2 x i16> %a) nounwind { define <2 x i16> @constant_shift_v2i16(<2 x i16> %a) nounwind {
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; AVX512BWVL-NEXT: retq ; AVX512BWVL-NEXT: retq
; ;
; X86-SSE-LABEL: constant_shift_v8i8: ; X86-SSE-LABEL: constant_shift_v8i8:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pxor %xmm1, %xmm1 ; X86-SSE-NEXT: pxor %xmm1, %xmm1
; X86-SSE-NEXT: movdqa %xmm0, %xmm2 ; X86-SSE-NEXT: movdqa %xmm0, %xmm2
; X86-SSE-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15] ; X86-SSE-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] ; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; X86-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: psrlw $8, %xmm0 ; X86-SSE-NEXT: psrlw $8, %xmm0
; X86-SSE-NEXT: packuswb %xmm2, %xmm0 ; X86-SSE-NEXT: packuswb %xmm2, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = lshr <8 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7> %shift = lshr <8 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7>
ret <8 x i8> %shift ret <8 x i8> %shift
} }
define <4 x i8> @constant_shift_v4i8(<4 x i8> %a) nounwind { define <4 x i8> @constant_shift_v4i8(<4 x i8> %a) nounwind {
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; AVX512BWVL-NEXT: retq ; AVX512BWVL-NEXT: retq
; ;
; X86-SSE-LABEL: constant_shift_v4i8: ; X86-SSE-LABEL: constant_shift_v4i8:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pxor %xmm1, %xmm1 ; X86-SSE-NEXT: pxor %xmm1, %xmm1
; X86-SSE-NEXT: movdqa %xmm0, %xmm2 ; X86-SSE-NEXT: movdqa %xmm0, %xmm2
; X86-SSE-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15] ; X86-SSE-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] ; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; X86-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: psrlw $8, %xmm0 ; X86-SSE-NEXT: psrlw $8, %xmm0
; X86-SSE-NEXT: packuswb %xmm2, %xmm0 ; X86-SSE-NEXT: packuswb %xmm2, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = lshr <4 x i8> %a, <i8 0, i8 1, i8 2, i8 3> %shift = lshr <4 x i8> %a, <i8 0, i8 1, i8 2, i8 3>
ret <4 x i8> %shift ret <4 x i8> %shift
} }
define <2 x i8> @constant_shift_v2i8(<2 x i8> %a) nounwind { define <2 x i8> @constant_shift_v2i8(<2 x i8> %a) nounwind {
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; AVX512BWVL-NEXT: retq ; AVX512BWVL-NEXT: retq
; ;
; X86-SSE-LABEL: constant_shift_v2i8: ; X86-SSE-LABEL: constant_shift_v2i8:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pxor %xmm1, %xmm1 ; X86-SSE-NEXT: pxor %xmm1, %xmm1
; X86-SSE-NEXT: movdqa %xmm0, %xmm2 ; X86-SSE-NEXT: movdqa %xmm0, %xmm2
; X86-SSE-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15] ; X86-SSE-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] ; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
; X86-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: psrlw $8, %xmm0 ; X86-SSE-NEXT: psrlw $8, %xmm0
; X86-SSE-NEXT: packuswb %xmm2, %xmm0 ; X86-SSE-NEXT: packuswb %xmm2, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = lshr <2 x i8> %a, <i8 2, i8 3> %shift = lshr <2 x i8> %a, <i8 2, i8 3>
ret <2 x i8> %shift ret <2 x i8> %shift
} }
; ;
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; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsrlw $3, %xmm0, %xmm0 ; AVX512VL-NEXT: vpsrlw $3, %xmm0, %xmm0
; AVX512VL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; AVX512VL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
; X86-SSE-LABEL: splatconstant_shift_v8i8: ; X86-SSE-LABEL: splatconstant_shift_v8i8:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: psrlw $3, %xmm0 ; X86-SSE-NEXT: psrlw $3, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = lshr <8 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> %shift = lshr <8 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <8 x i8> %shift ret <8 x i8> %shift
} }
define <4 x i8> @splatconstant_shift_v4i8(<4 x i8> %a) nounwind { define <4 x i8> @splatconstant_shift_v4i8(<4 x i8> %a) nounwind {
; SSE-LABEL: splatconstant_shift_v4i8: ; SSE-LABEL: splatconstant_shift_v4i8:
; SSE: # %bb.0: ; SSE: # %bb.0:
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; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsrlw $3, %xmm0, %xmm0 ; AVX512VL-NEXT: vpsrlw $3, %xmm0, %xmm0
; AVX512VL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; AVX512VL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
; X86-SSE-LABEL: splatconstant_shift_v4i8: ; X86-SSE-LABEL: splatconstant_shift_v4i8:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: psrlw $3, %xmm0 ; X86-SSE-NEXT: psrlw $3, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = lshr <4 x i8> %a, <i8 3, i8 3, i8 3, i8 3> %shift = lshr <4 x i8> %a, <i8 3, i8 3, i8 3, i8 3>
ret <4 x i8> %shift ret <4 x i8> %shift
} }
define <2 x i8> @splatconstant_shift_v2i8(<2 x i8> %a) nounwind { define <2 x i8> @splatconstant_shift_v2i8(<2 x i8> %a) nounwind {
; SSE-LABEL: splatconstant_shift_v2i8: ; SSE-LABEL: splatconstant_shift_v2i8:
; SSE: # %bb.0: ; SSE: # %bb.0:
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; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsrlw $3, %xmm0, %xmm0 ; AVX512VL-NEXT: vpsrlw $3, %xmm0, %xmm0
; AVX512VL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; AVX512VL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
; X86-SSE-LABEL: splatconstant_shift_v2i8: ; X86-SSE-LABEL: splatconstant_shift_v2i8:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: psrlw $3, %xmm0 ; X86-SSE-NEXT: psrlw $3, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = lshr <2 x i8> %a, <i8 3, i8 3> %shift = lshr <2 x i8> %a, <i8 3, i8 3>
ret <2 x i8> %shift ret <2 x i8> %shift
} }

llvm/test/CodeGen/X86/vector-shift-shl-128.ll

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; AVX512VL-LABEL: var_shift_v4i32: ; AVX512VL-LABEL: var_shift_v4i32:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsllvd %xmm1, %xmm0, %xmm0 ; AVX512VL-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
; X86-SSE-LABEL: var_shift_v4i32: ; X86-SSE-LABEL: var_shift_v4i32:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pslld $23, %xmm1 ; X86-SSE-NEXT: pslld $23, %xmm1
; X86-SSE-NEXT: paddd {{\.LCPI.*}}, %xmm1 ; X86-SSE-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE-NEXT: cvttps2dq %xmm1, %xmm1 ; X86-SSE-NEXT: cvttps2dq %xmm1, %xmm1
; X86-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; X86-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; X86-SSE-NEXT: pmuludq %xmm1, %xmm0 ; X86-SSE-NEXT: pmuludq %xmm1, %xmm0
; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; X86-SSE-NEXT: pmuludq %xmm2, %xmm1 ; X86-SSE-NEXT: pmuludq %xmm2, %xmm1
; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; X86-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; X86-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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; X86-SSE-NEXT: psllw $5, %xmm1 ; X86-SSE-NEXT: psllw $5, %xmm1
; X86-SSE-NEXT: pxor %xmm2, %xmm2 ; X86-SSE-NEXT: pxor %xmm2, %xmm2
; X86-SSE-NEXT: pxor %xmm3, %xmm3 ; X86-SSE-NEXT: pxor %xmm3, %xmm3
; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3 ; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3
; X86-SSE-NEXT: movdqa %xmm3, %xmm4 ; X86-SSE-NEXT: movdqa %xmm3, %xmm4
; X86-SSE-NEXT: pandn %xmm0, %xmm4 ; X86-SSE-NEXT: pandn %xmm0, %xmm4
; X86-SSE-NEXT: psllw $4, %xmm0 ; X86-SSE-NEXT: psllw $4, %xmm0
; X86-SSE-NEXT: pand %xmm3, %xmm0 ; X86-SSE-NEXT: pand %xmm3, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: por %xmm4, %xmm0 ; X86-SSE-NEXT: por %xmm4, %xmm0
; X86-SSE-NEXT: paddb %xmm1, %xmm1 ; X86-SSE-NEXT: paddb %xmm1, %xmm1
; X86-SSE-NEXT: pxor %xmm3, %xmm3 ; X86-SSE-NEXT: pxor %xmm3, %xmm3
; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3 ; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3
; X86-SSE-NEXT: movdqa %xmm3, %xmm4 ; X86-SSE-NEXT: movdqa %xmm3, %xmm4
; X86-SSE-NEXT: pandn %xmm0, %xmm4 ; X86-SSE-NEXT: pandn %xmm0, %xmm4
; X86-SSE-NEXT: psllw $2, %xmm0 ; X86-SSE-NEXT: psllw $2, %xmm0
; X86-SSE-NEXT: pand %xmm3, %xmm0 ; X86-SSE-NEXT: pand %xmm3, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: por %xmm4, %xmm0 ; X86-SSE-NEXT: por %xmm4, %xmm0
; X86-SSE-NEXT: paddb %xmm1, %xmm1 ; X86-SSE-NEXT: paddb %xmm1, %xmm1
; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm2 ; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm2
; X86-SSE-NEXT: movdqa %xmm2, %xmm1 ; X86-SSE-NEXT: movdqa %xmm2, %xmm1
; X86-SSE-NEXT: pandn %xmm0, %xmm1 ; X86-SSE-NEXT: pandn %xmm0, %xmm1
; X86-SSE-NEXT: paddb %xmm0, %xmm0 ; X86-SSE-NEXT: paddb %xmm0, %xmm0
; X86-SSE-NEXT: pand %xmm2, %xmm0 ; X86-SSE-NEXT: pand %xmm2, %xmm0
; X86-SSE-NEXT: por %xmm1, %xmm0 ; X86-SSE-NEXT: por %xmm1, %xmm0
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; ;
; AVX512BWVL-LABEL: constant_shift_v8i16: ; AVX512BWVL-LABEL: constant_shift_v8i16:
; AVX512BWVL: # %bb.0: ; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vpsllvw {{.*}}(%rip), %xmm0, %xmm0 ; AVX512BWVL-NEXT: vpsllvw {{.*}}(%rip), %xmm0, %xmm0
; AVX512BWVL-NEXT: retq ; AVX512BWVL-NEXT: retq
; ;
; X86-SSE-LABEL: constant_shift_v8i16: ; X86-SSE-LABEL: constant_shift_v8i16:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = shl <8 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7> %shift = shl <8 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
ret <8 x i16> %shift ret <8 x i16> %shift
} }
define <16 x i8> @constant_shift_v16i8(<16 x i8> %a) nounwind { define <16 x i8> @constant_shift_v16i8(<16 x i8> %a) nounwind {
; SSE2-LABEL: constant_shift_v16i8: ; SSE2-LABEL: constant_shift_v16i8:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
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; AVX512BWVL-NEXT: vpmovwb %ymm0, %xmm0 ; AVX512BWVL-NEXT: vpmovwb %ymm0, %xmm0
; AVX512BWVL-NEXT: vzeroupper ; AVX512BWVL-NEXT: vzeroupper
; AVX512BWVL-NEXT: retq ; AVX512BWVL-NEXT: retq
; ;
; X86-SSE-LABEL: constant_shift_v16i8: ; X86-SSE-LABEL: constant_shift_v16i8:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: movdqa %xmm0, %xmm1 ; X86-SSE-NEXT: movdqa %xmm0, %xmm1
; X86-SSE-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15] ; X86-SSE-NEXT: punpckhbw {{.*#+}} xmm1 = xmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; X86-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm1 ; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255] ; X86-SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
; X86-SSE-NEXT: pand %xmm2, %xmm1 ; X86-SSE-NEXT: pand %xmm2, %xmm1
; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X86-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: pand %xmm2, %xmm0 ; X86-SSE-NEXT: pand %xmm2, %xmm0
; X86-SSE-NEXT: packuswb %xmm1, %xmm0 ; X86-SSE-NEXT: packuswb %xmm1, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = shl <16 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0> %shift = shl <16 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
ret <16 x i8> %shift ret <16 x i8> %shift
} }
; ;
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; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsllw $3, %xmm0, %xmm0 ; AVX512VL-NEXT: vpsllw $3, %xmm0, %xmm0
; AVX512VL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; AVX512VL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
; X86-SSE-LABEL: splatconstant_shift_v16i8: ; X86-SSE-LABEL: splatconstant_shift_v16i8:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: psllw $3, %xmm0 ; X86-SSE-NEXT: psllw $3, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = shl <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> %shift = shl <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <16 x i8> %shift ret <16 x i8> %shift
} }

llvm/test/CodeGen/X86/vector-shift-shl-256.ll

Show First 20 Lines • Show All 429 Lines • ▼ Show 20 Lines
; X86-AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
; X86-AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0 ; X86-AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: var_shift_v32i8: ; X86-AVX2-LABEL: var_shift_v32i8:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpsllw $5, %ymm1, %ymm1 ; X86-AVX2-NEXT: vpsllw $5, %ymm1, %ymm1
; X86-AVX2-NEXT: vpsllw $4, %ymm0, %ymm2 ; X86-AVX2-NEXT: vpsllw $4, %ymm0, %ymm2
; X86-AVX2-NEXT: vpand {{\.LCPI.*}}, %ymm2, %ymm2 ; X86-AVX2-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm2, %ymm2
; X86-AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; X86-AVX2-NEXT: vpsllw $2, %ymm0, %ymm2 ; X86-AVX2-NEXT: vpsllw $2, %ymm0, %ymm2
; X86-AVX2-NEXT: vpand {{\.LCPI.*}}, %ymm2, %ymm2 ; X86-AVX2-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm2, %ymm2
; X86-AVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1 ; X86-AVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1
; X86-AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; X86-AVX2-NEXT: vpaddb %ymm0, %ymm0, %ymm2 ; X86-AVX2-NEXT: vpaddb %ymm0, %ymm0, %ymm2
; X86-AVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1 ; X86-AVX2-NEXT: vpaddb %ymm1, %ymm1, %ymm1
; X86-AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpblendvb %ymm1, %ymm2, %ymm0, %ymm0
; X86-AVX2-NEXT: retl ; X86-AVX2-NEXT: retl
%shift = shl <32 x i8> %a, %b %shift = shl <32 x i8> %a, %b
ret <32 x i8> %shift ret <32 x i8> %shift
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; X86-AVX1-NEXT: vpsllq $7, %xmm0, %xmm2 ; X86-AVX1-NEXT: vpsllq $7, %xmm0, %xmm2
; X86-AVX1-NEXT: vpsllq $1, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpsllq $1, %xmm0, %xmm0
; X86-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7] ; X86-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
; X86-AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; X86-AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: constant_shift_v4i64: ; X86-AVX2-LABEL: constant_shift_v4i64:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpsllvq {{\.LCPI.*}}, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpsllvq {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-AVX2-NEXT: retl ; X86-AVX2-NEXT: retl
%shift = shl <4 x i64> %a, <i64 1, i64 7, i64 31, i64 62> %shift = shl <4 x i64> %a, <i64 1, i64 7, i64 31, i64 62>
ret <4 x i64> %shift ret <4 x i64> %shift
} }
define <8 x i32> @constant_shift_v8i32(<8 x i32> %a) nounwind { define <8 x i32> @constant_shift_v8i32(<8 x i32> %a) nounwind {
; AVX1-LABEL: constant_shift_v8i32: ; AVX1-LABEL: constant_shift_v8i32:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
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; ;
; AVX512VL-LABEL: constant_shift_v8i32: ; AVX512VL-LABEL: constant_shift_v8i32:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsllvd {{.*}}(%rip), %ymm0, %ymm0 ; AVX512VL-NEXT: vpsllvd {{.*}}(%rip), %ymm0, %ymm0
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
; X86-AVX1-LABEL: constant_shift_v8i32: ; X86-AVX1-LABEL: constant_shift_v8i32:
; X86-AVX1: # %bb.0: ; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vpmulld {{\.LCPI.*}}, %xmm0, %xmm1 ; X86-AVX1-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm1
; X86-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; X86-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; X86-AVX1-NEXT: vpmulld {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpmulld {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; X86-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: constant_shift_v8i32: ; X86-AVX2-LABEL: constant_shift_v8i32:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpsllvd {{\.LCPI.*}}, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpsllvd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-AVX2-NEXT: retl ; X86-AVX2-NEXT: retl
%shift = shl <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 8, i32 7> %shift = shl <8 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 8, i32 7>
ret <8 x i32> %shift ret <8 x i32> %shift
} }
define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) nounwind { define <16 x i16> @constant_shift_v16i16(<16 x i16> %a) nounwind {
; AVX1-LABEL: constant_shift_v16i16: ; AVX1-LABEL: constant_shift_v16i16:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
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; ;
; AVX512BWVL-LABEL: constant_shift_v16i16: ; AVX512BWVL-LABEL: constant_shift_v16i16:
; AVX512BWVL: # %bb.0: ; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vpsllvw {{.*}}(%rip), %ymm0, %ymm0 ; AVX512BWVL-NEXT: vpsllvw {{.*}}(%rip), %ymm0, %ymm0
; AVX512BWVL-NEXT: retq ; AVX512BWVL-NEXT: retq
; ;
; X86-AVX1-LABEL: constant_shift_v16i16: ; X86-AVX1-LABEL: constant_shift_v16i16:
; X86-AVX1: # %bb.0: ; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vpmullw {{\.LCPI.*}}, %xmm0, %xmm1 ; X86-AVX1-NEXT: vpmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm1
; X86-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 ; X86-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; X86-AVX1-NEXT: vpmullw {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; X86-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: constant_shift_v16i16: ; X86-AVX2-LABEL: constant_shift_v16i16:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpmullw {{\.LCPI.*}}, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpmullw {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-AVX2-NEXT: retl ; X86-AVX2-NEXT: retl
%shift = shl <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15> %shift = shl <16 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
ret <16 x i16> %shift ret <16 x i16> %shift
} }
define <32 x i8> @constant_shift_v32i8(<32 x i8> %a) nounwind { define <32 x i8> @constant_shift_v32i8(<32 x i8> %a) nounwind {
; AVX1-LABEL: constant_shift_v32i8: ; AVX1-LABEL: constant_shift_v32i8:
; AVX1: # %bb.0: ; AVX1: # %bb.0:
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; X86-AVX1-NEXT: vpand %xmm4, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpand %xmm4, %xmm0, %xmm0
; X86-AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
; X86-AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; X86-AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: constant_shift_v32i8: ; X86-AVX2-LABEL: constant_shift_v32i8:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpsllw $4, %ymm0, %ymm1 ; X86-AVX2-NEXT: vpsllw $4, %ymm0, %ymm1
; X86-AVX2-NEXT: vpand {{\.LCPI.*}}, %ymm1, %ymm1 ; X86-AVX2-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm1
; X86-AVX2-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [8192,24640,41088,57536,49376,32928,16480,32,8192,24640,41088,57536,49376,32928,16480,32] ; X86-AVX2-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [8192,24640,41088,57536,49376,32928,16480,32,8192,24640,41088,57536,49376,32928,16480,32]
; X86-AVX2-NEXT: # ymm2 = mem[0,1,0,1] ; X86-AVX2-NEXT: # ymm2 = mem[0,1,0,1]
; X86-AVX2-NEXT: vpblendvb %ymm2, %ymm1, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
; X86-AVX2-NEXT: vpsllw $2, %ymm0, %ymm1 ; X86-AVX2-NEXT: vpsllw $2, %ymm0, %ymm1
; X86-AVX2-NEXT: vpand {{\.LCPI.*}}, %ymm1, %ymm1 ; X86-AVX2-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm1, %ymm1
; X86-AVX2-NEXT: vpaddb %ymm2, %ymm2, %ymm2 ; X86-AVX2-NEXT: vpaddb %ymm2, %ymm2, %ymm2
; X86-AVX2-NEXT: vpblendvb %ymm2, %ymm1, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
; X86-AVX2-NEXT: vpaddb %ymm0, %ymm0, %ymm1 ; X86-AVX2-NEXT: vpaddb %ymm0, %ymm0, %ymm1
; X86-AVX2-NEXT: vpaddb %ymm2, %ymm2, %ymm2 ; X86-AVX2-NEXT: vpaddb %ymm2, %ymm2, %ymm2
; X86-AVX2-NEXT: vpblendvb %ymm2, %ymm1, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpblendvb %ymm2, %ymm1, %ymm0, %ymm0
; X86-AVX2-NEXT: retl ; X86-AVX2-NEXT: retl
%shift = shl <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0> %shift = shl <32 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
ret <32 x i8> %shift ret <32 x i8> %shift
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; X86-AVX1-NEXT: vpsllw $3, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpsllw $3, %xmm0, %xmm0
; X86-AVX1-NEXT: vpand %xmm2, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpand %xmm2, %xmm0, %xmm0
; X86-AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; X86-AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: splatconstant_shift_v32i8: ; X86-AVX2-LABEL: splatconstant_shift_v32i8:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpsllw $3, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpsllw $3, %ymm0, %ymm0
; X86-AVX2-NEXT: vpand {{\.LCPI.*}}, %ymm0, %ymm0 ; X86-AVX2-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-AVX2-NEXT: retl ; X86-AVX2-NEXT: retl
%shift = shl <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> %shift = shl <32 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <32 x i8> %shift ret <32 x i8> %shift
} }

llvm/test/CodeGen/X86/vector-shift-shl-sub128.ll

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; AVX512VL-LABEL: var_shift_v2i32: ; AVX512VL-LABEL: var_shift_v2i32:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsllvd %xmm1, %xmm0, %xmm0 ; AVX512VL-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
; X86-SSE-LABEL: var_shift_v2i32: ; X86-SSE-LABEL: var_shift_v2i32:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pslld $23, %xmm1 ; X86-SSE-NEXT: pslld $23, %xmm1
; X86-SSE-NEXT: paddd {{\.LCPI.*}}, %xmm1 ; X86-SSE-NEXT: paddd {{\.LCPI[0-9]+_[0-9]+}}, %xmm1
; X86-SSE-NEXT: cvttps2dq %xmm1, %xmm1 ; X86-SSE-NEXT: cvttps2dq %xmm1, %xmm1
; X86-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3] ; X86-SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
; X86-SSE-NEXT: pmuludq %xmm1, %xmm0 ; X86-SSE-NEXT: pmuludq %xmm1, %xmm0
; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; X86-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3] ; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
; X86-SSE-NEXT: pmuludq %xmm2, %xmm1 ; X86-SSE-NEXT: pmuludq %xmm2, %xmm1
; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3] ; X86-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
; X86-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; X86-SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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; X86-SSE-NEXT: psllw $5, %xmm1 ; X86-SSE-NEXT: psllw $5, %xmm1
; X86-SSE-NEXT: pxor %xmm2, %xmm2 ; X86-SSE-NEXT: pxor %xmm2, %xmm2
; X86-SSE-NEXT: pxor %xmm3, %xmm3 ; X86-SSE-NEXT: pxor %xmm3, %xmm3
; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3 ; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3
; X86-SSE-NEXT: movdqa %xmm3, %xmm4 ; X86-SSE-NEXT: movdqa %xmm3, %xmm4
; X86-SSE-NEXT: pandn %xmm0, %xmm4 ; X86-SSE-NEXT: pandn %xmm0, %xmm4
; X86-SSE-NEXT: psllw $4, %xmm0 ; X86-SSE-NEXT: psllw $4, %xmm0
; X86-SSE-NEXT: pand %xmm3, %xmm0 ; X86-SSE-NEXT: pand %xmm3, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: por %xmm4, %xmm0 ; X86-SSE-NEXT: por %xmm4, %xmm0
; X86-SSE-NEXT: paddb %xmm1, %xmm1 ; X86-SSE-NEXT: paddb %xmm1, %xmm1
; X86-SSE-NEXT: pxor %xmm3, %xmm3 ; X86-SSE-NEXT: pxor %xmm3, %xmm3
; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3 ; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3
; X86-SSE-NEXT: movdqa %xmm3, %xmm4 ; X86-SSE-NEXT: movdqa %xmm3, %xmm4
; X86-SSE-NEXT: pandn %xmm0, %xmm4 ; X86-SSE-NEXT: pandn %xmm0, %xmm4
; X86-SSE-NEXT: psllw $2, %xmm0 ; X86-SSE-NEXT: psllw $2, %xmm0
; X86-SSE-NEXT: pand %xmm3, %xmm0 ; X86-SSE-NEXT: pand %xmm3, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: por %xmm4, %xmm0 ; X86-SSE-NEXT: por %xmm4, %xmm0
; X86-SSE-NEXT: paddb %xmm1, %xmm1 ; X86-SSE-NEXT: paddb %xmm1, %xmm1
; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm2 ; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm2
; X86-SSE-NEXT: movdqa %xmm2, %xmm1 ; X86-SSE-NEXT: movdqa %xmm2, %xmm1
; X86-SSE-NEXT: pandn %xmm0, %xmm1 ; X86-SSE-NEXT: pandn %xmm0, %xmm1
; X86-SSE-NEXT: paddb %xmm0, %xmm0 ; X86-SSE-NEXT: paddb %xmm0, %xmm0
; X86-SSE-NEXT: pand %xmm2, %xmm0 ; X86-SSE-NEXT: pand %xmm2, %xmm0
; X86-SSE-NEXT: por %xmm1, %xmm0 ; X86-SSE-NEXT: por %xmm1, %xmm0
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; X86-SSE-NEXT: psllw $5, %xmm1 ; X86-SSE-NEXT: psllw $5, %xmm1
; X86-SSE-NEXT: pxor %xmm2, %xmm2 ; X86-SSE-NEXT: pxor %xmm2, %xmm2
; X86-SSE-NEXT: pxor %xmm3, %xmm3 ; X86-SSE-NEXT: pxor %xmm3, %xmm3
; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3 ; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3
; X86-SSE-NEXT: movdqa %xmm3, %xmm4 ; X86-SSE-NEXT: movdqa %xmm3, %xmm4
; X86-SSE-NEXT: pandn %xmm0, %xmm4 ; X86-SSE-NEXT: pandn %xmm0, %xmm4
; X86-SSE-NEXT: psllw $4, %xmm0 ; X86-SSE-NEXT: psllw $4, %xmm0
; X86-SSE-NEXT: pand %xmm3, %xmm0 ; X86-SSE-NEXT: pand %xmm3, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: por %xmm4, %xmm0 ; X86-SSE-NEXT: por %xmm4, %xmm0
; X86-SSE-NEXT: paddb %xmm1, %xmm1 ; X86-SSE-NEXT: paddb %xmm1, %xmm1
; X86-SSE-NEXT: pxor %xmm3, %xmm3 ; X86-SSE-NEXT: pxor %xmm3, %xmm3
; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3 ; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3
; X86-SSE-NEXT: movdqa %xmm3, %xmm4 ; X86-SSE-NEXT: movdqa %xmm3, %xmm4
; X86-SSE-NEXT: pandn %xmm0, %xmm4 ; X86-SSE-NEXT: pandn %xmm0, %xmm4
; X86-SSE-NEXT: psllw $2, %xmm0 ; X86-SSE-NEXT: psllw $2, %xmm0
; X86-SSE-NEXT: pand %xmm3, %xmm0 ; X86-SSE-NEXT: pand %xmm3, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: por %xmm4, %xmm0 ; X86-SSE-NEXT: por %xmm4, %xmm0
; X86-SSE-NEXT: paddb %xmm1, %xmm1 ; X86-SSE-NEXT: paddb %xmm1, %xmm1
; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm2 ; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm2
; X86-SSE-NEXT: movdqa %xmm2, %xmm1 ; X86-SSE-NEXT: movdqa %xmm2, %xmm1
; X86-SSE-NEXT: pandn %xmm0, %xmm1 ; X86-SSE-NEXT: pandn %xmm0, %xmm1
; X86-SSE-NEXT: paddb %xmm0, %xmm0 ; X86-SSE-NEXT: paddb %xmm0, %xmm0
; X86-SSE-NEXT: pand %xmm2, %xmm0 ; X86-SSE-NEXT: pand %xmm2, %xmm0
; X86-SSE-NEXT: por %xmm1, %xmm0 ; X86-SSE-NEXT: por %xmm1, %xmm0
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; X86-SSE-NEXT: psllw $5, %xmm1 ; X86-SSE-NEXT: psllw $5, %xmm1
; X86-SSE-NEXT: pxor %xmm2, %xmm2 ; X86-SSE-NEXT: pxor %xmm2, %xmm2
; X86-SSE-NEXT: pxor %xmm3, %xmm3 ; X86-SSE-NEXT: pxor %xmm3, %xmm3
; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3 ; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3
; X86-SSE-NEXT: movdqa %xmm3, %xmm4 ; X86-SSE-NEXT: movdqa %xmm3, %xmm4
; X86-SSE-NEXT: pandn %xmm0, %xmm4 ; X86-SSE-NEXT: pandn %xmm0, %xmm4
; X86-SSE-NEXT: psllw $4, %xmm0 ; X86-SSE-NEXT: psllw $4, %xmm0
; X86-SSE-NEXT: pand %xmm3, %xmm0 ; X86-SSE-NEXT: pand %xmm3, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: por %xmm4, %xmm0 ; X86-SSE-NEXT: por %xmm4, %xmm0
; X86-SSE-NEXT: paddb %xmm1, %xmm1 ; X86-SSE-NEXT: paddb %xmm1, %xmm1
; X86-SSE-NEXT: pxor %xmm3, %xmm3 ; X86-SSE-NEXT: pxor %xmm3, %xmm3
; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3 ; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm3
; X86-SSE-NEXT: movdqa %xmm3, %xmm4 ; X86-SSE-NEXT: movdqa %xmm3, %xmm4
; X86-SSE-NEXT: pandn %xmm0, %xmm4 ; X86-SSE-NEXT: pandn %xmm0, %xmm4
; X86-SSE-NEXT: psllw $2, %xmm0 ; X86-SSE-NEXT: psllw $2, %xmm0
; X86-SSE-NEXT: pand %xmm3, %xmm0 ; X86-SSE-NEXT: pand %xmm3, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: por %xmm4, %xmm0 ; X86-SSE-NEXT: por %xmm4, %xmm0
; X86-SSE-NEXT: paddb %xmm1, %xmm1 ; X86-SSE-NEXT: paddb %xmm1, %xmm1
; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm2 ; X86-SSE-NEXT: pcmpgtb %xmm1, %xmm2
; X86-SSE-NEXT: movdqa %xmm2, %xmm1 ; X86-SSE-NEXT: movdqa %xmm2, %xmm1
; X86-SSE-NEXT: pandn %xmm0, %xmm1 ; X86-SSE-NEXT: pandn %xmm0, %xmm1
; X86-SSE-NEXT: paddb %xmm0, %xmm0 ; X86-SSE-NEXT: paddb %xmm0, %xmm0
; X86-SSE-NEXT: pand %xmm2, %xmm0 ; X86-SSE-NEXT: pand %xmm2, %xmm0
; X86-SSE-NEXT: por %xmm1, %xmm0 ; X86-SSE-NEXT: por %xmm1, %xmm0
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; ;
; AVX512BWVL-LABEL: constant_shift_v4i16: ; AVX512BWVL-LABEL: constant_shift_v4i16:
; AVX512BWVL: # %bb.0: ; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vpsllvw {{.*}}(%rip), %xmm0, %xmm0 ; AVX512BWVL-NEXT: vpsllvw {{.*}}(%rip), %xmm0, %xmm0
; AVX512BWVL-NEXT: retq ; AVX512BWVL-NEXT: retq
; ;
; X86-SSE-LABEL: constant_shift_v4i16: ; X86-SSE-LABEL: constant_shift_v4i16:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = shl <4 x i16> %a, <i16 0, i16 1, i16 2, i16 3> %shift = shl <4 x i16> %a, <i16 0, i16 1, i16 2, i16 3>
ret <4 x i16> %shift ret <4 x i16> %shift
} }
define <2 x i16> @constant_shift_v2i16(<2 x i16> %a) nounwind { define <2 x i16> @constant_shift_v2i16(<2 x i16> %a) nounwind {
; SSE2-LABEL: constant_shift_v2i16: ; SSE2-LABEL: constant_shift_v2i16:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
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; ;
; AVX512BWVL-LABEL: constant_shift_v2i16: ; AVX512BWVL-LABEL: constant_shift_v2i16:
; AVX512BWVL: # %bb.0: ; AVX512BWVL: # %bb.0:
; AVX512BWVL-NEXT: vpsllvw {{.*}}(%rip), %xmm0, %xmm0 ; AVX512BWVL-NEXT: vpsllvw {{.*}}(%rip), %xmm0, %xmm0
; AVX512BWVL-NEXT: retq ; AVX512BWVL-NEXT: retq
; ;
; X86-SSE-LABEL: constant_shift_v2i16: ; X86-SSE-LABEL: constant_shift_v2i16:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = shl <2 x i16> %a, <i16 2, i16 3> %shift = shl <2 x i16> %a, <i16 2, i16 3>
ret <2 x i16> %shift ret <2 x i16> %shift
} }
define <8 x i8> @constant_shift_v8i8(<8 x i8> %a) nounwind { define <8 x i8> @constant_shift_v8i8(<8 x i8> %a) nounwind {
; SSE2-LABEL: constant_shift_v8i8: ; SSE2-LABEL: constant_shift_v8i8:
; SSE2: # %bb.0: ; SSE2: # %bb.0:
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; AVX512BWVL-NEXT: vpsllvw {{.*}}(%rip), %ymm0, %ymm0 ; AVX512BWVL-NEXT: vpsllvw {{.*}}(%rip), %ymm0, %ymm0
; AVX512BWVL-NEXT: vpmovwb %ymm0, %xmm0 ; AVX512BWVL-NEXT: vpmovwb %ymm0, %xmm0
; AVX512BWVL-NEXT: vzeroupper ; AVX512BWVL-NEXT: vzeroupper
; AVX512BWVL-NEXT: retq ; AVX512BWVL-NEXT: retq
; ;
; X86-SSE-LABEL: constant_shift_v8i8: ; X86-SSE-LABEL: constant_shift_v8i8:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X86-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: pxor %xmm1, %xmm1 ; X86-SSE-NEXT: pxor %xmm1, %xmm1
; X86-SSE-NEXT: packuswb %xmm1, %xmm0 ; X86-SSE-NEXT: packuswb %xmm1, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = shl <8 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7> %shift = shl <8 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7>
ret <8 x i8> %shift ret <8 x i8> %shift
} }
define <4 x i8> @constant_shift_v4i8(<4 x i8> %a) nounwind { define <4 x i8> @constant_shift_v4i8(<4 x i8> %a) nounwind {
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; AVX512BWVL-NEXT: vpsllvw {{.*}}(%rip), %ymm0, %ymm0 ; AVX512BWVL-NEXT: vpsllvw {{.*}}(%rip), %ymm0, %ymm0
; AVX512BWVL-NEXT: vpmovwb %ymm0, %xmm0 ; AVX512BWVL-NEXT: vpmovwb %ymm0, %xmm0
; AVX512BWVL-NEXT: vzeroupper ; AVX512BWVL-NEXT: vzeroupper
; AVX512BWVL-NEXT: retq ; AVX512BWVL-NEXT: retq
; ;
; X86-SSE-LABEL: constant_shift_v4i8: ; X86-SSE-LABEL: constant_shift_v4i8:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X86-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: pxor %xmm1, %xmm1 ; X86-SSE-NEXT: pxor %xmm1, %xmm1
; X86-SSE-NEXT: packuswb %xmm1, %xmm0 ; X86-SSE-NEXT: packuswb %xmm1, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = shl <4 x i8> %a, <i8 0, i8 1, i8 2, i8 3> %shift = shl <4 x i8> %a, <i8 0, i8 1, i8 2, i8 3>
ret <4 x i8> %shift ret <4 x i8> %shift
} }
define <2 x i8> @constant_shift_v2i8(<2 x i8> %a) nounwind { define <2 x i8> @constant_shift_v2i8(<2 x i8> %a) nounwind {
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; AVX512BWVL-NEXT: vpsllvw {{.*}}(%rip), %ymm0, %ymm0 ; AVX512BWVL-NEXT: vpsllvw {{.*}}(%rip), %ymm0, %ymm0
; AVX512BWVL-NEXT: vpmovwb %ymm0, %xmm0 ; AVX512BWVL-NEXT: vpmovwb %ymm0, %xmm0
; AVX512BWVL-NEXT: vzeroupper ; AVX512BWVL-NEXT: vzeroupper
; AVX512BWVL-NEXT: retq ; AVX512BWVL-NEXT: retq
; ;
; X86-SSE-LABEL: constant_shift_v2i8: ; X86-SSE-LABEL: constant_shift_v2i8:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7] ; X86-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
; X86-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: pxor %xmm1, %xmm1 ; X86-SSE-NEXT: pxor %xmm1, %xmm1
; X86-SSE-NEXT: packuswb %xmm1, %xmm0 ; X86-SSE-NEXT: packuswb %xmm1, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = shl <2 x i8> %a, <i8 2, i8 3> %shift = shl <2 x i8> %a, <i8 2, i8 3>
ret <2 x i8> %shift ret <2 x i8> %shift
} }
; ;
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; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsllw $3, %xmm0, %xmm0 ; AVX512VL-NEXT: vpsllw $3, %xmm0, %xmm0
; AVX512VL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; AVX512VL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
; X86-SSE-LABEL: splatconstant_shift_v8i8: ; X86-SSE-LABEL: splatconstant_shift_v8i8:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: psllw $3, %xmm0 ; X86-SSE-NEXT: psllw $3, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = shl <8 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> %shift = shl <8 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <8 x i8> %shift ret <8 x i8> %shift
} }
define <4 x i8> @splatconstant_shift_v4i8(<4 x i8> %a) nounwind { define <4 x i8> @splatconstant_shift_v4i8(<4 x i8> %a) nounwind {
; SSE-LABEL: splatconstant_shift_v4i8: ; SSE-LABEL: splatconstant_shift_v4i8:
; SSE: # %bb.0: ; SSE: # %bb.0:
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; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsllw $3, %xmm0, %xmm0 ; AVX512VL-NEXT: vpsllw $3, %xmm0, %xmm0
; AVX512VL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; AVX512VL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
; X86-SSE-LABEL: splatconstant_shift_v4i8: ; X86-SSE-LABEL: splatconstant_shift_v4i8:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: psllw $3, %xmm0 ; X86-SSE-NEXT: psllw $3, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = shl <4 x i8> %a, <i8 3, i8 3, i8 3, i8 3> %shift = shl <4 x i8> %a, <i8 3, i8 3, i8 3, i8 3>
ret <4 x i8> %shift ret <4 x i8> %shift
} }
define <2 x i8> @splatconstant_shift_v2i8(<2 x i8> %a) nounwind { define <2 x i8> @splatconstant_shift_v2i8(<2 x i8> %a) nounwind {
; SSE-LABEL: splatconstant_shift_v2i8: ; SSE-LABEL: splatconstant_shift_v2i8:
; SSE: # %bb.0: ; SSE: # %bb.0:
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; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsllw $3, %xmm0, %xmm0 ; AVX512VL-NEXT: vpsllw $3, %xmm0, %xmm0
; AVX512VL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; AVX512VL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
; X86-SSE-LABEL: splatconstant_shift_v2i8: ; X86-SSE-LABEL: splatconstant_shift_v2i8:
; X86-SSE: # %bb.0: ; X86-SSE: # %bb.0:
; X86-SSE-NEXT: psllw $3, %xmm0 ; X86-SSE-NEXT: psllw $3, %xmm0
; X86-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE-NEXT: retl ; X86-SSE-NEXT: retl
%shift = shl <2 x i8> %a, <i8 3, i8 3> %shift = shl <2 x i8> %a, <i8 3, i8 3>
ret <2 x i8> %shift ret <2 x i8> %shift
} }

llvm/test/CodeGen/X86/vector-shuffle-avx512.ll

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; ;
; KNL64-LABEL: test_mm512_mask_blend_epi16: ; KNL64-LABEL: test_mm512_mask_blend_epi16:
; KNL64: # %bb.0: # %entry ; KNL64: # %bb.0: # %entry
; KNL64-NEXT: vpternlogd $216, {{.*}}(%rip){1to16}, %zmm1, %zmm0 ; KNL64-NEXT: vpternlogd $216, {{.*}}(%rip){1to16}, %zmm1, %zmm0
; KNL64-NEXT: retq ; KNL64-NEXT: retq
; ;
; KNL32-LABEL: test_mm512_mask_blend_epi16: ; KNL32-LABEL: test_mm512_mask_blend_epi16:
; KNL32: # %bb.0: # %entry ; KNL32: # %bb.0: # %entry
; KNL32-NEXT: vpternlogd $216, {{\.LCPI.*}}{1to16}, %zmm1, %zmm0 ; KNL32-NEXT: vpternlogd $216, {{\.LCPI[0-9]+_[0-9]+}}{1to16}, %zmm1, %zmm0
; KNL32-NEXT: retl ; KNL32-NEXT: retl
entry: entry:
%0 = shufflevector <32 x i16> %A, <32 x i16> %W, <32 x i32> <i32 32, i32 1, i32 34, i32 3, i32 36, i32 5, i32 38, i32 7, i32 40, i32 9, i32 42, i32 11, i32 44, i32 13, i32 46, i32 15, i32 48, i32 17, i32 50, i32 19, i32 52, i32 21, i32 54, i32 23, i32 56, i32 25, i32 58, i32 27, i32 60, i32 29, i32 62, i32 31> %0 = shufflevector <32 x i16> %A, <32 x i16> %W, <32 x i32> <i32 32, i32 1, i32 34, i32 3, i32 36, i32 5, i32 38, i32 7, i32 40, i32 9, i32 42, i32 11, i32 44, i32 13, i32 46, i32 15, i32 48, i32 17, i32 50, i32 19, i32 52, i32 21, i32 54, i32 23, i32 56, i32 25, i32 58, i32 27, i32 60, i32 29, i32 62, i32 31>
ret <32 x i16> %0 ret <32 x i16> %0
} }
define <16 x i32> @test_mm512_mask_blend_epi32(<16 x i32> %A, <16 x i32> %W){ define <16 x i32> @test_mm512_mask_blend_epi32(<16 x i32> %A, <16 x i32> %W){
; SKX-LABEL: test_mm512_mask_blend_epi32: ; SKX-LABEL: test_mm512_mask_blend_epi32:
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llvm/test/CodeGen/X86/vector-shuffle-combining-avx2.ll

Show First 20 Lines • Show All 71 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret{{[l|q]}}
%2 = shufflevector <32 x i8> %1, <32 x i8> zeroinitializer, <32 x i32> <i32 0, i32 1, i32 32, i32 32, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> %2 = shufflevector <32 x i8> %1, <32 x i8> zeroinitializer, <32 x i32> <i32 0, i32 1, i32 32, i32 32, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
ret <32 x i8> %2 ret <32 x i8> %2
} }
define <4 x i64> @combine_permq_pshufb_as_vextracti128(<4 x i64> %a0) { define <4 x i64> @combine_permq_pshufb_as_vextracti128(<4 x i64> %a0) {
; X86-LABEL: combine_permq_pshufb_as_vextracti128: ; X86-LABEL: combine_permq_pshufb_as_vextracti128:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vextracti128 $1, %ymm0, %xmm0 ; X86-NEXT: vextracti128 $1, %ymm0, %xmm0
; X86-NEXT: vpaddq {{\.LCPI.*}}, %ymm0, %ymm0 ; X86-NEXT: vpaddq {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: combine_permq_pshufb_as_vextracti128: ; X64-LABEL: combine_permq_pshufb_as_vextracti128:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vextracti128 $1, %ymm0, %xmm0 ; X64-NEXT: vextracti128 $1, %ymm0, %xmm0
; X64-NEXT: vpaddq {{.*}}(%rip), %ymm0, %ymm0 ; X64-NEXT: vpaddq {{.*}}(%rip), %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = shufflevector <4 x i64> %a0, <4 x i64> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> %1 = shufflevector <4 x i64> %a0, <4 x i64> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
%2 = bitcast <4 x i64> %1 to <32 x i8> %2 = bitcast <4 x i64> %1 to <32 x i8>
%3 = call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %2, <32 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255>) %3 = call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %2, <32 x i8> <i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255, i8 255>)
%4 = bitcast <32 x i8> %3 to <4 x i64> %4 = bitcast <32 x i8> %3 to <4 x i64>
%5 = add <4 x i64> %4, <i64 1, i64 1, i64 3, i64 3> %5 = add <4 x i64> %4, <i64 1, i64 1, i64 3, i64 3>
ret <4 x i64> %5 ret <4 x i64> %5
} }
define <4 x i64> @combine_permq_pshufb_as_vmovdqa(<4 x i64> %a0) { define <4 x i64> @combine_permq_pshufb_as_vmovdqa(<4 x i64> %a0) {
; X86-LABEL: combine_permq_pshufb_as_vmovdqa: ; X86-LABEL: combine_permq_pshufb_as_vmovdqa:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vmovdqa %xmm0, %xmm0 ; X86-NEXT: vmovdqa %xmm0, %xmm0
; X86-NEXT: vpaddq {{\.LCPI.*}}, %ymm0, %ymm0 ; X86-NEXT: vpaddq {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: combine_permq_pshufb_as_vmovdqa: ; X64-LABEL: combine_permq_pshufb_as_vmovdqa:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vmovdqa %xmm0, %xmm0 ; X64-NEXT: vmovdqa %xmm0, %xmm0
; X64-NEXT: vpaddq {{.*}}(%rip), %ymm0, %ymm0 ; X64-NEXT: vpaddq {{.*}}(%rip), %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = shufflevector <4 x i64> %a0, <4 x i64> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> %1 = shufflevector <4 x i64> %a0, <4 x i64> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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%6 = bitcast <8 x i32> %5 to <32 x i8> %6 = bitcast <8 x i32> %5 to <32 x i8>
ret <32 x i8> %6 ret <32 x i8> %6
} }
define <16 x i8> @combine_pshufb_as_vpbroadcastd128(<16 x i8> %a) { define <16 x i8> @combine_pshufb_as_vpbroadcastd128(<16 x i8> %a) {
; X86-LABEL: combine_pshufb_as_vpbroadcastd128: ; X86-LABEL: combine_pshufb_as_vpbroadcastd128:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vpbroadcastd %xmm0, %xmm0 ; X86-NEXT: vpbroadcastd %xmm0, %xmm0
; X86-NEXT: vpaddb {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-NEXT: vpaddb {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: combine_pshufb_as_vpbroadcastd128: ; X64-LABEL: combine_pshufb_as_vpbroadcastd128:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpbroadcastd %xmm0, %xmm0 ; X64-NEXT: vpbroadcastd %xmm0, %xmm0
; X64-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm0 ; X64-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 0, i8 1, i8 2, i8 3, i8 0, i8 1, i8 2, i8 3, i8 0, i8 1, i8 2, i8 3>) %1 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 0, i8 1, i8 2, i8 3, i8 0, i8 1, i8 2, i8 3, i8 0, i8 1, i8 2, i8 3>)
%2 = add <16 x i8> %1, <i8 0, i8 1, i8 2, i8 3, i8 0, i8 1, i8 2, i8 3, i8 0, i8 1, i8 2, i8 3, i8 0, i8 1, i8 2, i8 3> %2 = add <16 x i8> %1, <i8 0, i8 1, i8 2, i8 3, i8 0, i8 1, i8 2, i8 3, i8 0, i8 1, i8 2, i8 3, i8 0, i8 1, i8 2, i8 3>
ret <16 x i8> %2 ret <16 x i8> %2
} }
define <8 x i32> @combine_permd_as_vpbroadcastd256(<4 x i32> %a) { define <8 x i32> @combine_permd_as_vpbroadcastd256(<4 x i32> %a) {
; X86-LABEL: combine_permd_as_vpbroadcastd256: ; X86-LABEL: combine_permd_as_vpbroadcastd256:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vpbroadcastd %xmm0, %ymm0 ; X86-NEXT: vpbroadcastd %xmm0, %ymm0
; X86-NEXT: vpaddd {{\.LCPI.*}}, %ymm0, %ymm0 ; X86-NEXT: vpaddd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: combine_permd_as_vpbroadcastd256: ; X64-LABEL: combine_permd_as_vpbroadcastd256:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpbroadcastd %xmm0, %ymm0 ; X64-NEXT: vpbroadcastd %xmm0, %ymm0
; X64-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0 ; X64-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = shufflevector <4 x i32> %a, <4 x i32> undef, <8 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <8 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
Show All 10 Lines; CHECK-NEXT: ret{{[l|q]}}
%1 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7>) %1 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %a, <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7>)
ret <16 x i8> %1 ret <16 x i8> %1
} }
define <8 x i32> @combine_permd_as_vpbroadcastq256(<4 x i32> %a) { define <8 x i32> @combine_permd_as_vpbroadcastq256(<4 x i32> %a) {
; X86-LABEL: combine_permd_as_vpbroadcastq256: ; X86-LABEL: combine_permd_as_vpbroadcastq256:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vpbroadcastq %xmm0, %ymm0 ; X86-NEXT: vpbroadcastq %xmm0, %ymm0
; X86-NEXT: vpaddd {{\.LCPI.*}}, %ymm0, %ymm0 ; X86-NEXT: vpaddd {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: combine_permd_as_vpbroadcastq256: ; X64-LABEL: combine_permd_as_vpbroadcastq256:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpbroadcastq %xmm0, %ymm0 ; X64-NEXT: vpbroadcastq %xmm0, %ymm0
; X64-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0 ; X64-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = shufflevector <4 x i32> %a, <4 x i32> undef, <8 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %1 = shufflevector <4 x i32> %a, <4 x i32> undef, <8 x i32> <i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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; CHECK-NEXT: ret{{[l|q]}} ; CHECK-NEXT: ret{{[l|q]}}
%1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %a0, <32 x i8> <i8 -1, i8 8, i8 -1, i8 9, i8 -1, i8 10, i8 -1, i8 11, i8 -1, i8 12, i8 -1, i8 13, i8 -1, i8 14, i8 -1, i8 15, i8 -1, i8 24, i8 -1, i8 25, i8 -1, i8 26, i8 -1, i8 27, i8 -1, i8 28, i8 -1, i8 29, i8 -1, i8 30, i8 -1, i8 31>) %1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %a0, <32 x i8> <i8 -1, i8 8, i8 -1, i8 9, i8 -1, i8 10, i8 -1, i8 11, i8 -1, i8 12, i8 -1, i8 13, i8 -1, i8 14, i8 -1, i8 15, i8 -1, i8 24, i8 -1, i8 25, i8 -1, i8 26, i8 -1, i8 27, i8 -1, i8 28, i8 -1, i8 29, i8 -1, i8 30, i8 -1, i8 31>)
ret <32 x i8> %1 ret <32 x i8> %1
} }
define <32 x i8> @combine_psrlw_pshufb(<16 x i16> %a0) { define <32 x i8> @combine_psrlw_pshufb(<16 x i16> %a0) {
; X86-LABEL: combine_psrlw_pshufb: ; X86-LABEL: combine_psrlw_pshufb:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vandps {{\.LCPI.*}}, %ymm0, %ymm0 ; X86-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: combine_psrlw_pshufb: ; X64-LABEL: combine_psrlw_pshufb:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 ; X64-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = lshr <16 x i16> %a0, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> %1 = lshr <16 x i16> %a0, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
%2 = bitcast <16 x i16> %1 to <32 x i8> %2 = bitcast <16 x i16> %1 to <32 x i8>
%3 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %2, <32 x i8> <i8 1, i8 0, i8 3, i8 2, i8 5, i8 4, i8 7, i8 6, i8 9, i8 8, i8 11, i8 10, i8 13, i8 12, i8 15, i8 14, i8 17, i8 16, i8 19, i8 18, i8 21, i8 20, i8 23, i8 22, i8 25, i8 24, i8 27, i8 26, i8 29, i8 28, i8 31, i8 30>) %3 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %2, <32 x i8> <i8 1, i8 0, i8 3, i8 2, i8 5, i8 4, i8 7, i8 6, i8 9, i8 8, i8 11, i8 10, i8 13, i8 12, i8 15, i8 14, i8 17, i8 16, i8 19, i8 18, i8 21, i8 20, i8 23, i8 22, i8 25, i8 24, i8 27, i8 26, i8 29, i8 28, i8 31, i8 30>)
ret <32 x i8> %3 ret <32 x i8> %3
} }
define <32 x i8> @combine_pslld_pshufb(<8 x i32> %a0) { define <32 x i8> @combine_pslld_pshufb(<8 x i32> %a0) {
; X86-LABEL: combine_pslld_pshufb: ; X86-LABEL: combine_pslld_pshufb:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vandps {{\.LCPI.*}}, %ymm0, %ymm0 ; X86-NEXT: vandps {{\.LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: combine_pslld_pshufb: ; X64-LABEL: combine_pslld_pshufb:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0 ; X64-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = shl <8 x i32> %a0, <i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24> %1 = shl <8 x i32> %a0, <i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24, i32 24>
%2 = bitcast <8 x i32> %1 to <32 x i8> %2 = bitcast <8 x i32> %1 to <32 x i8>
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llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll

Show First 20 Lines • Show All 895 Lines • ▼ Show 20 Lines; X64-NEXT: retq
ret <8 x double> %res1 ret <8 x double> %res1
} }
define <8 x double> @combine_vpermi2var_8f64_as_permpd(<8 x double> %x0, <8 x double> %x1, i64 %a2) { define <8 x double> @combine_vpermi2var_8f64_as_permpd(<8 x double> %x0, <8 x double> %x1, i64 %a2) {
; X86-LABEL: combine_vpermi2var_8f64_as_permpd: ; X86-LABEL: combine_vpermi2var_8f64_as_permpd:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero ; X86-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
; X86-NEXT: vunpcklpd {{.*#+}} xmm2 = xmm2[0],mem[0] ; X86-NEXT: vunpcklpd {{.*#+}} xmm2 = xmm2[0],mem[0]
; X86-NEXT: vinsertf128 $1, {{\.LCPI.*}}, %ymm2, %ymm2 ; X86-NEXT: vinsertf128 $1, {{\.LCPI[0-9]+_[0-9]+}}, %ymm2, %ymm2
; X86-NEXT: vinsertf64x4 $1, {{\.LCPI.*}}, %zmm2, %zmm2 ; X86-NEXT: vinsertf64x4 $1, {{\.LCPI[0-9]+_[0-9]+}}, %zmm2, %zmm2
; X86-NEXT: vpermi2pd %zmm1, %zmm0, %zmm2 ; X86-NEXT: vpermi2pd %zmm1, %zmm0, %zmm2
; X86-NEXT: vpermpd {{.*#+}} zmm0 = zmm2[2,3,1,1,6,7,5,5] ; X86-NEXT: vpermpd {{.*#+}} zmm0 = zmm2[2,3,1,1,6,7,5,5]
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: combine_vpermi2var_8f64_as_permpd: ; X64-LABEL: combine_vpermi2var_8f64_as_permpd:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpermpd {{.*#+}} zmm0 = zmm0[1,3,2,2,5,7,6,6] ; X64-NEXT: vpermpd {{.*#+}} zmm0 = zmm0[1,3,2,2,5,7,6,6]
; X64-NEXT: retq ; X64-NEXT: retq
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llvm/test/CodeGen/X86/vector-shuffle-combining-xop.ll

Show First 20 Lines • Show All 129 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret{{[l|q]}}
ret <4 x double> %res0 ret <4 x double> %res0
} }
define <4 x double> @demandedelts_vpermil2pd256_as_shufpd(<4 x double> %a0, <4 x double> %a1, i64 %a2) { define <4 x double> @demandedelts_vpermil2pd256_as_shufpd(<4 x double> %a0, <4 x double> %a1, i64 %a2) {
; X86-LABEL: demandedelts_vpermil2pd256_as_shufpd: ; X86-LABEL: demandedelts_vpermil2pd256_as_shufpd:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero ; X86-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
; X86-NEXT: vunpcklpd {{.*#+}} xmm2 = xmm2[0],mem[0] ; X86-NEXT: vunpcklpd {{.*#+}} xmm2 = xmm2[0],mem[0]
; X86-NEXT: vinsertf128 $1, {{\.LCPI.*}}, %ymm2, %ymm2 ; X86-NEXT: vinsertf128 $1, {{\.LCPI[0-9]+_[0-9]+}}, %ymm2, %ymm2
; X86-NEXT: vpermil2pd $0, %ymm2, %ymm1, %ymm0, %ymm0 ; X86-NEXT: vpermil2pd $0, %ymm2, %ymm1, %ymm0, %ymm0
; X86-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,1,2,3] ; X86-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,1,2,3]
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: demandedelts_vpermil2pd256_as_shufpd: ; X64-LABEL: demandedelts_vpermil2pd256_as_shufpd:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpermil2pd {{.*#+}} ymm0 = ymm1[0,0],ymm0[3],ymm1[3] ; X64-NEXT: vpermil2pd {{.*#+}} ymm0 = ymm1[0,0],ymm0[3],ymm1[3]
; X64-NEXT: retq ; X64-NEXT: retq
Show All 22 Lines; CHECK-NEXT: ret{{[l|q]}}
%res1 = call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %res0, <16 x i8> undef, <16 x i8> <i8 0, i8 128, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>) %res1 = call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %res0, <16 x i8> undef, <16 x i8> <i8 0, i8 128, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>)
%res2 = call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %res1, <16 x i8> undef, <16 x i8> <i8 0, i8 1, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>) %res2 = call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %res1, <16 x i8> undef, <16 x i8> <i8 0, i8 1, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>)
ret <16 x i8> %res2 ret <16 x i8> %res2
} }
define <16 x i8> @combine_vpperm_identity_bitcast(<16 x i8> %a0, <16 x i8> %a1) { define <16 x i8> @combine_vpperm_identity_bitcast(<16 x i8> %a0, <16 x i8> %a1) {
; X86-LABEL: combine_vpperm_identity_bitcast: ; X86-LABEL: combine_vpperm_identity_bitcast:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vpaddq {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-NEXT: vpaddq {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: combine_vpperm_identity_bitcast: ; X64-LABEL: combine_vpperm_identity_bitcast:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm0 ; X64-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%mask = bitcast <2 x i64> <i64 1084818905618843912, i64 506097522914230528> to <16 x i8> %mask = bitcast <2 x i64> <i64 1084818905618843912, i64 506097522914230528> to <16 x i8>
%res0 = call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> %mask) %res0 = call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> %mask)
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llvm/test/CodeGen/X86/vector-shuffle-combining.ll

Show First 20 Lines • Show All 3,106 Lines • ▼ Show 20 Lines
; SSE-NEXT: addss %xmm1, %xmm0 ; SSE-NEXT: addss %xmm1, %xmm0
; SSE-NEXT: movss %xmm0, (%rax) ; SSE-NEXT: movss %xmm0, (%rax)
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX-LABEL: PR43024: ; AVX-LABEL: PR43024:
; AVX: # %bb.0: ; AVX: # %bb.0:
; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [NaN,NaN,0.0E+0,0.0E+0] ; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [NaN,NaN,0.0E+0,0.0E+0]
; AVX-NEXT: vmovaps %xmm0, (%rax) ; AVX-NEXT: vmovaps %xmm0, (%rax)
; AVX-NEXT: vaddss {{\.LCPI.*}}+{{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: vaddss {{\.LCPI[0-9]+_[0-9]+}}+{{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0 ; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0
; AVX-NEXT: vaddss {{\.LCPI.*}}+{{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: vaddss {{\.LCPI[0-9]+_[0-9]+}}+{{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vmovss %xmm0, (%rax) ; AVX-NEXT: vmovss %xmm0, (%rax)
; AVX-NEXT: retq ; AVX-NEXT: retq
store <4 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x0, float 0x0>, <4 x float>* undef, align 16 store <4 x float> <float 0x7FF8000000000000, float 0x7FF8000000000000, float 0x0, float 0x0>, <4 x float>* undef, align 16
%1 = load <4 x float>, <4 x float>* undef, align 16 %1 = load <4 x float>, <4 x float>* undef, align 16
%2 = fmul <4 x float> %1, <float 0x0, float 0x0, float 0x0, float 0x0> %2 = fmul <4 x float> %1, <float 0x0, float 0x0, float 0x0, float 0x0>
%3 = shufflevector <4 x float> %2, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> %3 = shufflevector <4 x float> %2, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
%4 = fadd <4 x float> %2, %3 %4 = fadd <4 x float> %2, %3
%5 = fadd <4 x float> zeroinitializer, %4 %5 = fadd <4 x float> zeroinitializer, %4
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llvm/test/CodeGen/X86/vector_splat-const-shift-of-constmasked.ll

Show All 11 Lines
; 128-bit vector; 8-bit elements = 16 elements ; 128-bit vector; 8-bit elements = 16 elements
;------------------------------------------------------------------------------; ;------------------------------------------------------------------------------;
; lshr ; lshr
define <16 x i8> @test_128_i8_x_16_7_mask_lshr_1(<16 x i8> %a0) { define <16 x i8> @test_128_i8_x_16_7_mask_lshr_1(<16 x i8> %a0) {
; X86-SSE2-LABEL: test_128_i8_x_16_7_mask_lshr_1: ; X86-SSE2-LABEL: test_128_i8_x_16_7_mask_lshr_1:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlw $1, %xmm0 ; X86-SSE2-NEXT: psrlw $1, %xmm0
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i8_x_16_7_mask_lshr_1: ; X86-AVX-LABEL: test_128_i8_x_16_7_mask_lshr_1:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i8_x_16_7_mask_lshr_1: ; X64-SSE2-LABEL: test_128_i8_x_16_7_mask_lshr_1:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlw $1, %xmm0 ; X64-SSE2-NEXT: psrlw $1, %xmm0
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i8_x_16_7_mask_lshr_1: ; X64-AVX-LABEL: test_128_i8_x_16_7_mask_lshr_1:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> %t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
%t1 = lshr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> %t1 = lshr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
ret <16 x i8> %t1 ret <16 x i8> %t1
} }
define <16 x i8> @test_128_i8_x_16_28_mask_lshr_1(<16 x i8> %a0) { define <16 x i8> @test_128_i8_x_16_28_mask_lshr_1(<16 x i8> %a0) {
; X86-SSE2-LABEL: test_128_i8_x_16_28_mask_lshr_1: ; X86-SSE2-LABEL: test_128_i8_x_16_28_mask_lshr_1:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlw $1, %xmm0 ; X86-SSE2-NEXT: psrlw $1, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i8_x_16_28_mask_lshr_1: ; X86-AVX-LABEL: test_128_i8_x_16_28_mask_lshr_1:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i8_x_16_28_mask_lshr_1: ; X64-SSE2-LABEL: test_128_i8_x_16_28_mask_lshr_1:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlw $1, %xmm0 ; X64-SSE2-NEXT: psrlw $1, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i8_x_16_28_mask_lshr_1: ; X64-AVX-LABEL: test_128_i8_x_16_28_mask_lshr_1:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28> %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
%t1 = lshr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> %t1 = lshr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
ret <16 x i8> %t1 ret <16 x i8> %t1
} }
define <16 x i8> @test_128_i8_x_16_28_mask_lshr_2(<16 x i8> %a0) { define <16 x i8> @test_128_i8_x_16_28_mask_lshr_2(<16 x i8> %a0) {
; X86-SSE2-LABEL: test_128_i8_x_16_28_mask_lshr_2: ; X86-SSE2-LABEL: test_128_i8_x_16_28_mask_lshr_2:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlw $2, %xmm0 ; X86-SSE2-NEXT: psrlw $2, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i8_x_16_28_mask_lshr_2: ; X86-AVX-LABEL: test_128_i8_x_16_28_mask_lshr_2:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlw $2, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlw $2, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i8_x_16_28_mask_lshr_2: ; X64-SSE2-LABEL: test_128_i8_x_16_28_mask_lshr_2:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlw $2, %xmm0 ; X64-SSE2-NEXT: psrlw $2, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i8_x_16_28_mask_lshr_2: ; X64-AVX-LABEL: test_128_i8_x_16_28_mask_lshr_2:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlw $2, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlw $2, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28> %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
%t1 = lshr <16 x i8> %t0, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2> %t1 = lshr <16 x i8> %t0, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
ret <16 x i8> %t1 ret <16 x i8> %t1
} }
define <16 x i8> @test_128_i8_x_16_28_mask_lshr_3(<16 x i8> %a0) { define <16 x i8> @test_128_i8_x_16_28_mask_lshr_3(<16 x i8> %a0) {
; X86-SSE2-LABEL: test_128_i8_x_16_28_mask_lshr_3: ; X86-SSE2-LABEL: test_128_i8_x_16_28_mask_lshr_3:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlw $3, %xmm0 ; X86-SSE2-NEXT: psrlw $3, %xmm0
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i8_x_16_28_mask_lshr_3: ; X86-AVX-LABEL: test_128_i8_x_16_28_mask_lshr_3:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlw $3, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlw $3, %xmm0, %xmm0
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i8_x_16_28_mask_lshr_3: ; X64-SSE2-LABEL: test_128_i8_x_16_28_mask_lshr_3:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlw $3, %xmm0 ; X64-SSE2-NEXT: psrlw $3, %xmm0
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i8_x_16_28_mask_lshr_3: ; X64-AVX-LABEL: test_128_i8_x_16_28_mask_lshr_3:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlw $3, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlw $3, %xmm0, %xmm0
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28> %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
%t1 = lshr <16 x i8> %t0, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> %t1 = lshr <16 x i8> %t0, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <16 x i8> %t1 ret <16 x i8> %t1
} }
define <16 x i8> @test_128_i8_x_16_28_mask_lshr_4(<16 x i8> %a0) { define <16 x i8> @test_128_i8_x_16_28_mask_lshr_4(<16 x i8> %a0) {
; X86-SSE2-LABEL: test_128_i8_x_16_28_mask_lshr_4: ; X86-SSE2-LABEL: test_128_i8_x_16_28_mask_lshr_4:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlw $4, %xmm0 ; X86-SSE2-NEXT: psrlw $4, %xmm0
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i8_x_16_28_mask_lshr_4: ; X86-AVX-LABEL: test_128_i8_x_16_28_mask_lshr_4:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlw $4, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlw $4, %xmm0, %xmm0
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i8_x_16_28_mask_lshr_4: ; X64-SSE2-LABEL: test_128_i8_x_16_28_mask_lshr_4:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlw $4, %xmm0 ; X64-SSE2-NEXT: psrlw $4, %xmm0
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i8_x_16_28_mask_lshr_4: ; X64-AVX-LABEL: test_128_i8_x_16_28_mask_lshr_4:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlw $4, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlw $4, %xmm0, %xmm0
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28> %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
%t1 = lshr <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4> %t1 = lshr <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
ret <16 x i8> %t1 ret <16 x i8> %t1
} }
define <16 x i8> @test_128_i8_x_16_224_mask_lshr_1(<16 x i8> %a0) { define <16 x i8> @test_128_i8_x_16_224_mask_lshr_1(<16 x i8> %a0) {
; X86-SSE2-LABEL: test_128_i8_x_16_224_mask_lshr_1: ; X86-SSE2-LABEL: test_128_i8_x_16_224_mask_lshr_1:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlw $1, %xmm0 ; X86-SSE2-NEXT: psrlw $1, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i8_x_16_224_mask_lshr_1: ; X86-AVX-LABEL: test_128_i8_x_16_224_mask_lshr_1:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i8_x_16_224_mask_lshr_1: ; X64-SSE2-LABEL: test_128_i8_x_16_224_mask_lshr_1:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlw $1, %xmm0 ; X64-SSE2-NEXT: psrlw $1, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i8_x_16_224_mask_lshr_1: ; X64-AVX-LABEL: test_128_i8_x_16_224_mask_lshr_1:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224> %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
%t1 = lshr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> %t1 = lshr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
ret <16 x i8> %t1 ret <16 x i8> %t1
} }
define <16 x i8> @test_128_i8_x_16_224_mask_lshr_4(<16 x i8> %a0) { define <16 x i8> @test_128_i8_x_16_224_mask_lshr_4(<16 x i8> %a0) {
; X86-SSE2-LABEL: test_128_i8_x_16_224_mask_lshr_4: ; X86-SSE2-LABEL: test_128_i8_x_16_224_mask_lshr_4:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlw $4, %xmm0 ; X86-SSE2-NEXT: psrlw $4, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i8_x_16_224_mask_lshr_4: ; X86-AVX-LABEL: test_128_i8_x_16_224_mask_lshr_4:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlw $4, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlw $4, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i8_x_16_224_mask_lshr_4: ; X64-SSE2-LABEL: test_128_i8_x_16_224_mask_lshr_4:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlw $4, %xmm0 ; X64-SSE2-NEXT: psrlw $4, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i8_x_16_224_mask_lshr_4: ; X64-AVX-LABEL: test_128_i8_x_16_224_mask_lshr_4:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlw $4, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlw $4, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224> %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
%t1 = lshr <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4> %t1 = lshr <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
ret <16 x i8> %t1 ret <16 x i8> %t1
} }
define <16 x i8> @test_128_i8_x_16_224_mask_lshr_5(<16 x i8> %a0) { define <16 x i8> @test_128_i8_x_16_224_mask_lshr_5(<16 x i8> %a0) {
; X86-SSE2-LABEL: test_128_i8_x_16_224_mask_lshr_5: ; X86-SSE2-LABEL: test_128_i8_x_16_224_mask_lshr_5:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: psrlw $5, %xmm0 ; X86-SSE2-NEXT: psrlw $5, %xmm0
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i8_x_16_224_mask_lshr_5: ; X86-AVX-LABEL: test_128_i8_x_16_224_mask_lshr_5:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpsrlw $5, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlw $5, %xmm0, %xmm0
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i8_x_16_224_mask_lshr_5: ; X64-SSE2-LABEL: test_128_i8_x_16_224_mask_lshr_5:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: psrlw $5, %xmm0 ; X64-SSE2-NEXT: psrlw $5, %xmm0
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i8_x_16_224_mask_lshr_5: ; X64-AVX-LABEL: test_128_i8_x_16_224_mask_lshr_5:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpsrlw $5, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlw $5, %xmm0, %xmm0
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224> %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
%t1 = lshr <16 x i8> %t0, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5> %t1 = lshr <16 x i8> %t0, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
ret <16 x i8> %t1 ret <16 x i8> %t1
} }
define <16 x i8> @test_128_i8_x_16_224_mask_lshr_6(<16 x i8> %a0) { define <16 x i8> @test_128_i8_x_16_224_mask_lshr_6(<16 x i8> %a0) {
; X86-SSE2-LABEL: test_128_i8_x_16_224_mask_lshr_6: ; X86-SSE2-LABEL: test_128_i8_x_16_224_mask_lshr_6:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: psrlw $6, %xmm0 ; X86-SSE2-NEXT: psrlw $6, %xmm0
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i8_x_16_224_mask_lshr_6: ; X86-AVX-LABEL: test_128_i8_x_16_224_mask_lshr_6:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpsrlw $6, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlw $6, %xmm0, %xmm0
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i8_x_16_224_mask_lshr_6: ; X64-SSE2-LABEL: test_128_i8_x_16_224_mask_lshr_6:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: psrlw $6, %xmm0 ; X64-SSE2-NEXT: psrlw $6, %xmm0
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i8_x_16_224_mask_lshr_6: ; X64-AVX-LABEL: test_128_i8_x_16_224_mask_lshr_6:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpsrlw $6, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlw $6, %xmm0, %xmm0
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224> %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
%t1 = lshr <16 x i8> %t0, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6> %t1 = lshr <16 x i8> %t0, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6>
ret <16 x i8> %t1 ret <16 x i8> %t1
} }
; ashr ; ashr
define <16 x i8> @test_128_i8_x_16_7_mask_ashr_1(<16 x i8> %a0) { define <16 x i8> @test_128_i8_x_16_7_mask_ashr_1(<16 x i8> %a0) {
; X86-SSE2-LABEL: test_128_i8_x_16_7_mask_ashr_1: ; X86-SSE2-LABEL: test_128_i8_x_16_7_mask_ashr_1:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlw $1, %xmm0 ; X86-SSE2-NEXT: psrlw $1, %xmm0
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i8_x_16_7_mask_ashr_1: ; X86-AVX-LABEL: test_128_i8_x_16_7_mask_ashr_1:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i8_x_16_7_mask_ashr_1: ; X64-SSE2-LABEL: test_128_i8_x_16_7_mask_ashr_1:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlw $1, %xmm0 ; X64-SSE2-NEXT: psrlw $1, %xmm0
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i8_x_16_7_mask_ashr_1: ; X64-AVX-LABEL: test_128_i8_x_16_7_mask_ashr_1:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> %t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
%t1 = ashr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> %t1 = ashr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
ret <16 x i8> %t1 ret <16 x i8> %t1
} }
define <16 x i8> @test_128_i8_x_16_28_mask_ashr_1(<16 x i8> %a0) { define <16 x i8> @test_128_i8_x_16_28_mask_ashr_1(<16 x i8> %a0) {
; X86-SSE2-LABEL: test_128_i8_x_16_28_mask_ashr_1: ; X86-SSE2-LABEL: test_128_i8_x_16_28_mask_ashr_1:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlw $1, %xmm0 ; X86-SSE2-NEXT: psrlw $1, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i8_x_16_28_mask_ashr_1: ; X86-AVX-LABEL: test_128_i8_x_16_28_mask_ashr_1:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i8_x_16_28_mask_ashr_1: ; X64-SSE2-LABEL: test_128_i8_x_16_28_mask_ashr_1:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlw $1, %xmm0 ; X64-SSE2-NEXT: psrlw $1, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i8_x_16_28_mask_ashr_1: ; X64-AVX-LABEL: test_128_i8_x_16_28_mask_ashr_1:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28> %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
%t1 = ashr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> %t1 = ashr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
ret <16 x i8> %t1 ret <16 x i8> %t1
} }
define <16 x i8> @test_128_i8_x_16_28_mask_ashr_2(<16 x i8> %a0) { define <16 x i8> @test_128_i8_x_16_28_mask_ashr_2(<16 x i8> %a0) {
; X86-SSE2-LABEL: test_128_i8_x_16_28_mask_ashr_2: ; X86-SSE2-LABEL: test_128_i8_x_16_28_mask_ashr_2:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlw $2, %xmm0 ; X86-SSE2-NEXT: psrlw $2, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i8_x_16_28_mask_ashr_2: ; X86-AVX-LABEL: test_128_i8_x_16_28_mask_ashr_2:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlw $2, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlw $2, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i8_x_16_28_mask_ashr_2: ; X64-SSE2-LABEL: test_128_i8_x_16_28_mask_ashr_2:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlw $2, %xmm0 ; X64-SSE2-NEXT: psrlw $2, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i8_x_16_28_mask_ashr_2: ; X64-AVX-LABEL: test_128_i8_x_16_28_mask_ashr_2:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlw $2, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlw $2, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28> %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
%t1 = ashr <16 x i8> %t0, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2> %t1 = ashr <16 x i8> %t0, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
ret <16 x i8> %t1 ret <16 x i8> %t1
} }
define <16 x i8> @test_128_i8_x_16_28_mask_ashr_3(<16 x i8> %a0) { define <16 x i8> @test_128_i8_x_16_28_mask_ashr_3(<16 x i8> %a0) {
; X86-SSE2-LABEL: test_128_i8_x_16_28_mask_ashr_3: ; X86-SSE2-LABEL: test_128_i8_x_16_28_mask_ashr_3:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlw $3, %xmm0 ; X86-SSE2-NEXT: psrlw $3, %xmm0
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i8_x_16_28_mask_ashr_3: ; X86-AVX-LABEL: test_128_i8_x_16_28_mask_ashr_3:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlw $3, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlw $3, %xmm0, %xmm0
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i8_x_16_28_mask_ashr_3: ; X64-SSE2-LABEL: test_128_i8_x_16_28_mask_ashr_3:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlw $3, %xmm0 ; X64-SSE2-NEXT: psrlw $3, %xmm0
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i8_x_16_28_mask_ashr_3: ; X64-AVX-LABEL: test_128_i8_x_16_28_mask_ashr_3:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlw $3, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlw $3, %xmm0, %xmm0
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28> %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
%t1 = ashr <16 x i8> %t0, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> %t1 = ashr <16 x i8> %t0, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <16 x i8> %t1 ret <16 x i8> %t1
} }
define <16 x i8> @test_128_i8_x_16_28_mask_ashr_4(<16 x i8> %a0) { define <16 x i8> @test_128_i8_x_16_28_mask_ashr_4(<16 x i8> %a0) {
; X86-SSE2-LABEL: test_128_i8_x_16_28_mask_ashr_4: ; X86-SSE2-LABEL: test_128_i8_x_16_28_mask_ashr_4:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlw $4, %xmm0 ; X86-SSE2-NEXT: psrlw $4, %xmm0
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i8_x_16_28_mask_ashr_4: ; X86-AVX-LABEL: test_128_i8_x_16_28_mask_ashr_4:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlw $4, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlw $4, %xmm0, %xmm0
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i8_x_16_28_mask_ashr_4: ; X64-SSE2-LABEL: test_128_i8_x_16_28_mask_ashr_4:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlw $4, %xmm0 ; X64-SSE2-NEXT: psrlw $4, %xmm0
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i8_x_16_28_mask_ashr_4: ; X64-AVX-LABEL: test_128_i8_x_16_28_mask_ashr_4:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlw $4, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlw $4, %xmm0, %xmm0
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28> %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
%t1 = ashr <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4> %t1 = ashr <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
ret <16 x i8> %t1 ret <16 x i8> %t1
} }
define <16 x i8> @test_128_i8_x_16_224_mask_ashr_1(<16 x i8> %a0) { define <16 x i8> @test_128_i8_x_16_224_mask_ashr_1(<16 x i8> %a0) {
; X86-SSE2-LABEL: test_128_i8_x_16_224_mask_ashr_1: ; X86-SSE2-LABEL: test_128_i8_x_16_224_mask_ashr_1:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlw $1, %xmm0 ; X86-SSE2-NEXT: psrlw $1, %xmm0
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64]
; X86-SSE2-NEXT: pxor %xmm1, %xmm0 ; X86-SSE2-NEXT: pxor %xmm1, %xmm0
; X86-SSE2-NEXT: psubb %xmm1, %xmm0 ; X86-SSE2-NEXT: psubb %xmm1, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i8_x_16_224_mask_ashr_1: ; X86-AVX-LABEL: test_128_i8_x_16_224_mask_ashr_1:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0
; X86-AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64] ; X86-AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64]
; X86-AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X86-AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X86-AVX-NEXT: vpsubb %xmm1, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsubb %xmm1, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i8_x_16_224_mask_ashr_1: ; X64-SSE2-LABEL: test_128_i8_x_16_224_mask_ashr_1:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
Show All 14 Lines
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224> %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
%t1 = ashr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> %t1 = ashr <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
ret <16 x i8> %t1 ret <16 x i8> %t1
} }
define <16 x i8> @test_128_i8_x_16_224_mask_ashr_4(<16 x i8> %a0) { define <16 x i8> @test_128_i8_x_16_224_mask_ashr_4(<16 x i8> %a0) {
; X86-SSE2-LABEL: test_128_i8_x_16_224_mask_ashr_4: ; X86-SSE2-LABEL: test_128_i8_x_16_224_mask_ashr_4:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlw $4, %xmm0 ; X86-SSE2-NEXT: psrlw $4, %xmm0
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]
; X86-SSE2-NEXT: pxor %xmm1, %xmm0 ; X86-SSE2-NEXT: pxor %xmm1, %xmm0
; X86-SSE2-NEXT: psubb %xmm1, %xmm0 ; X86-SSE2-NEXT: psubb %xmm1, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i8_x_16_224_mask_ashr_4: ; X86-AVX-LABEL: test_128_i8_x_16_224_mask_ashr_4:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlw $4, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlw $4, %xmm0, %xmm0
; X86-AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8] ; X86-AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8]
; X86-AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X86-AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X86-AVX-NEXT: vpsubb %xmm1, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsubb %xmm1, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i8_x_16_224_mask_ashr_4: ; X64-SSE2-LABEL: test_128_i8_x_16_224_mask_ashr_4:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
Show All 15 Lines; X64-AVX-NEXT: retq
%t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224> %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
%t1 = ashr <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4> %t1 = ashr <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
ret <16 x i8> %t1 ret <16 x i8> %t1
} }
define <16 x i8> @test_128_i8_x_16_224_mask_ashr_5(<16 x i8> %a0) { define <16 x i8> @test_128_i8_x_16_224_mask_ashr_5(<16 x i8> %a0) {
; X86-SSE2-LABEL: test_128_i8_x_16_224_mask_ashr_5: ; X86-SSE2-LABEL: test_128_i8_x_16_224_mask_ashr_5:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: psrlw $5, %xmm0 ; X86-SSE2-NEXT: psrlw $5, %xmm0
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4]
; X86-SSE2-NEXT: pxor %xmm1, %xmm0 ; X86-SSE2-NEXT: pxor %xmm1, %xmm0
; X86-SSE2-NEXT: psubb %xmm1, %xmm0 ; X86-SSE2-NEXT: psubb %xmm1, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i8_x_16_224_mask_ashr_5: ; X86-AVX-LABEL: test_128_i8_x_16_224_mask_ashr_5:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpsrlw $5, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlw $5, %xmm0, %xmm0
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4] ; X86-AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4]
; X86-AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X86-AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X86-AVX-NEXT: vpsubb %xmm1, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsubb %xmm1, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i8_x_16_224_mask_ashr_5: ; X64-SSE2-LABEL: test_128_i8_x_16_224_mask_ashr_5:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: psrlw $5, %xmm0 ; X64-SSE2-NEXT: psrlw $5, %xmm0
Show All 14 Lines; X64-AVX-NEXT: retq
%t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224> %t0 = and <16 x i8> %a0, <i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224, i8 224>
%t1 = ashr <16 x i8> %t0, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5> %t1 = ashr <16 x i8> %t0, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
ret <16 x i8> %t1 ret <16 x i8> %t1
} }
define <16 x i8> @test_128_i8_x_16_224_mask_ashr_6(<16 x i8> %a0) { define <16 x i8> @test_128_i8_x_16_224_mask_ashr_6(<16 x i8> %a0) {
; X86-SSE2-LABEL: test_128_i8_x_16_224_mask_ashr_6: ; X86-SSE2-LABEL: test_128_i8_x_16_224_mask_ashr_6:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: psrlw $6, %xmm0 ; X86-SSE2-NEXT: psrlw $6, %xmm0
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2] ; X86-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2]
; X86-SSE2-NEXT: pxor %xmm1, %xmm0 ; X86-SSE2-NEXT: pxor %xmm1, %xmm0
; X86-SSE2-NEXT: psubb %xmm1, %xmm0 ; X86-SSE2-NEXT: psubb %xmm1, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i8_x_16_224_mask_ashr_6: ; X86-AVX-LABEL: test_128_i8_x_16_224_mask_ashr_6:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpsrlw $6, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlw $6, %xmm0, %xmm0
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2] ; X86-AVX-NEXT: vmovdqa {{.*#+}} xmm1 = [2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2]
; X86-AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0 ; X86-AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0
; X86-AVX-NEXT: vpsubb %xmm1, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsubb %xmm1, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i8_x_16_224_mask_ashr_6: ; X64-SSE2-LABEL: test_128_i8_x_16_224_mask_ashr_6:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: psrlw $6, %xmm0 ; X64-SSE2-NEXT: psrlw $6, %xmm0
Show All 16 Lines; X64-AVX-NEXT: retq
ret <16 x i8> %t1 ret <16 x i8> %t1
} }
; shl ; shl
define <16 x i8> @test_128_i8_x_16_7_mask_shl_1(<16 x i8> %a0) { define <16 x i8> @test_128_i8_x_16_7_mask_shl_1(<16 x i8> %a0) {
; X86-SSE2-LABEL: test_128_i8_x_16_7_mask_shl_1: ; X86-SSE2-LABEL: test_128_i8_x_16_7_mask_shl_1:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: paddb %xmm0, %xmm0 ; X86-SSE2-NEXT: paddb %xmm0, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i8_x_16_7_mask_shl_1: ; X86-AVX-LABEL: test_128_i8_x_16_7_mask_shl_1:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpaddb %xmm0, %xmm0, %xmm0 ; X86-AVX-NEXT: vpaddb %xmm0, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i8_x_16_7_mask_shl_1: ; X64-SSE2-LABEL: test_128_i8_x_16_7_mask_shl_1:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: paddb %xmm0, %xmm0 ; X64-SSE2-NEXT: paddb %xmm0, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i8_x_16_7_mask_shl_1: ; X64-AVX-LABEL: test_128_i8_x_16_7_mask_shl_1:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpaddb %xmm0, %xmm0, %xmm0 ; X64-AVX-NEXT: vpaddb %xmm0, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> %t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
%t1 = shl <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> %t1 = shl <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
ret <16 x i8> %t1 ret <16 x i8> %t1
} }
define <16 x i8> @test_128_i8_x_16_7_mask_shl_4(<16 x i8> %a0) { define <16 x i8> @test_128_i8_x_16_7_mask_shl_4(<16 x i8> %a0) {
; X86-SSE2-LABEL: test_128_i8_x_16_7_mask_shl_4: ; X86-SSE2-LABEL: test_128_i8_x_16_7_mask_shl_4:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psllw $4, %xmm0 ; X86-SSE2-NEXT: psllw $4, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i8_x_16_7_mask_shl_4: ; X86-AVX-LABEL: test_128_i8_x_16_7_mask_shl_4:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsllw $4, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsllw $4, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i8_x_16_7_mask_shl_4: ; X64-SSE2-LABEL: test_128_i8_x_16_7_mask_shl_4:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psllw $4, %xmm0 ; X64-SSE2-NEXT: psllw $4, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i8_x_16_7_mask_shl_4: ; X64-AVX-LABEL: test_128_i8_x_16_7_mask_shl_4:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsllw $4, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsllw $4, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> %t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
%t1 = shl <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4> %t1 = shl <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
ret <16 x i8> %t1 ret <16 x i8> %t1
} }
define <16 x i8> @test_128_i8_x_16_7_mask_shl_5(<16 x i8> %a0) { define <16 x i8> @test_128_i8_x_16_7_mask_shl_5(<16 x i8> %a0) {
; X86-SSE2-LABEL: test_128_i8_x_16_7_mask_shl_5: ; X86-SSE2-LABEL: test_128_i8_x_16_7_mask_shl_5:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: psllw $5, %xmm0 ; X86-SSE2-NEXT: psllw $5, %xmm0
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i8_x_16_7_mask_shl_5: ; X86-AVX-LABEL: test_128_i8_x_16_7_mask_shl_5:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpsllw $5, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsllw $5, %xmm0, %xmm0
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i8_x_16_7_mask_shl_5: ; X64-SSE2-LABEL: test_128_i8_x_16_7_mask_shl_5:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: psllw $5, %xmm0 ; X64-SSE2-NEXT: psllw $5, %xmm0
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i8_x_16_7_mask_shl_5: ; X64-AVX-LABEL: test_128_i8_x_16_7_mask_shl_5:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpsllw $5, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsllw $5, %xmm0, %xmm0
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> %t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
%t1 = shl <16 x i8> %t0, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5> %t1 = shl <16 x i8> %t0, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
ret <16 x i8> %t1 ret <16 x i8> %t1
} }
define <16 x i8> @test_128_i8_x_16_7_mask_shl_6(<16 x i8> %a0) { define <16 x i8> @test_128_i8_x_16_7_mask_shl_6(<16 x i8> %a0) {
; X86-SSE2-LABEL: test_128_i8_x_16_7_mask_shl_6: ; X86-SSE2-LABEL: test_128_i8_x_16_7_mask_shl_6:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: psllw $6, %xmm0 ; X86-SSE2-NEXT: psllw $6, %xmm0
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i8_x_16_7_mask_shl_6: ; X86-AVX-LABEL: test_128_i8_x_16_7_mask_shl_6:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpsllw $6, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsllw $6, %xmm0, %xmm0
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i8_x_16_7_mask_shl_6: ; X64-SSE2-LABEL: test_128_i8_x_16_7_mask_shl_6:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: psllw $6, %xmm0 ; X64-SSE2-NEXT: psllw $6, %xmm0
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i8_x_16_7_mask_shl_6: ; X64-AVX-LABEL: test_128_i8_x_16_7_mask_shl_6:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpsllw $6, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsllw $6, %xmm0, %xmm0
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> %t0 = and <16 x i8> %a0, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
%t1 = shl <16 x i8> %t0, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6> %t1 = shl <16 x i8> %t0, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6>
ret <16 x i8> %t1 ret <16 x i8> %t1
} }
define <16 x i8> @test_128_i8_x_16_28_mask_shl_1(<16 x i8> %a0) { define <16 x i8> @test_128_i8_x_16_28_mask_shl_1(<16 x i8> %a0) {
; X86-SSE2-LABEL: test_128_i8_x_16_28_mask_shl_1: ; X86-SSE2-LABEL: test_128_i8_x_16_28_mask_shl_1:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: paddb %xmm0, %xmm0 ; X86-SSE2-NEXT: paddb %xmm0, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i8_x_16_28_mask_shl_1: ; X86-AVX-LABEL: test_128_i8_x_16_28_mask_shl_1:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpaddb %xmm0, %xmm0, %xmm0 ; X86-AVX-NEXT: vpaddb %xmm0, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i8_x_16_28_mask_shl_1: ; X64-SSE2-LABEL: test_128_i8_x_16_28_mask_shl_1:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: paddb %xmm0, %xmm0 ; X64-SSE2-NEXT: paddb %xmm0, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i8_x_16_28_mask_shl_1: ; X64-AVX-LABEL: test_128_i8_x_16_28_mask_shl_1:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpaddb %xmm0, %xmm0, %xmm0 ; X64-AVX-NEXT: vpaddb %xmm0, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28> %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
%t1 = shl <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> %t1 = shl <16 x i8> %t0, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
ret <16 x i8> %t1 ret <16 x i8> %t1
} }
define <16 x i8> @test_128_i8_x_16_28_mask_shl_2(<16 x i8> %a0) { define <16 x i8> @test_128_i8_x_16_28_mask_shl_2(<16 x i8> %a0) {
; X86-SSE2-LABEL: test_128_i8_x_16_28_mask_shl_2: ; X86-SSE2-LABEL: test_128_i8_x_16_28_mask_shl_2:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psllw $2, %xmm0 ; X86-SSE2-NEXT: psllw $2, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i8_x_16_28_mask_shl_2: ; X86-AVX-LABEL: test_128_i8_x_16_28_mask_shl_2:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsllw $2, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsllw $2, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i8_x_16_28_mask_shl_2: ; X64-SSE2-LABEL: test_128_i8_x_16_28_mask_shl_2:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psllw $2, %xmm0 ; X64-SSE2-NEXT: psllw $2, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i8_x_16_28_mask_shl_2: ; X64-AVX-LABEL: test_128_i8_x_16_28_mask_shl_2:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsllw $2, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsllw $2, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28> %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
%t1 = shl <16 x i8> %t0, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2> %t1 = shl <16 x i8> %t0, <i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2, i8 2>
ret <16 x i8> %t1 ret <16 x i8> %t1
} }
define <16 x i8> @test_128_i8_x_16_28_mask_shl_3(<16 x i8> %a0) { define <16 x i8> @test_128_i8_x_16_28_mask_shl_3(<16 x i8> %a0) {
; X86-SSE2-LABEL: test_128_i8_x_16_28_mask_shl_3: ; X86-SSE2-LABEL: test_128_i8_x_16_28_mask_shl_3:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psllw $3, %xmm0 ; X86-SSE2-NEXT: psllw $3, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i8_x_16_28_mask_shl_3: ; X86-AVX-LABEL: test_128_i8_x_16_28_mask_shl_3:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsllw $3, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsllw $3, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i8_x_16_28_mask_shl_3: ; X64-SSE2-LABEL: test_128_i8_x_16_28_mask_shl_3:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psllw $3, %xmm0 ; X64-SSE2-NEXT: psllw $3, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i8_x_16_28_mask_shl_3: ; X64-AVX-LABEL: test_128_i8_x_16_28_mask_shl_3:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsllw $3, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsllw $3, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28> %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
%t1 = shl <16 x i8> %t0, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> %t1 = shl <16 x i8> %t0, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <16 x i8> %t1 ret <16 x i8> %t1
} }
define <16 x i8> @test_128_i8_x_16_28_mask_shl_4(<16 x i8> %a0) { define <16 x i8> @test_128_i8_x_16_28_mask_shl_4(<16 x i8> %a0) {
; X86-SSE2-LABEL: test_128_i8_x_16_28_mask_shl_4: ; X86-SSE2-LABEL: test_128_i8_x_16_28_mask_shl_4:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psllw $4, %xmm0 ; X86-SSE2-NEXT: psllw $4, %xmm0
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i8_x_16_28_mask_shl_4: ; X86-AVX-LABEL: test_128_i8_x_16_28_mask_shl_4:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsllw $4, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsllw $4, %xmm0, %xmm0
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i8_x_16_28_mask_shl_4: ; X64-SSE2-LABEL: test_128_i8_x_16_28_mask_shl_4:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psllw $4, %xmm0 ; X64-SSE2-NEXT: psllw $4, %xmm0
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i8_x_16_28_mask_shl_4: ; X64-AVX-LABEL: test_128_i8_x_16_28_mask_shl_4:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsllw $4, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsllw $4, %xmm0, %xmm0
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28> %t0 = and <16 x i8> %a0, <i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28, i8 28>
%t1 = shl <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4> %t1 = shl <16 x i8> %t0, <i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4>
ret <16 x i8> %t1 ret <16 x i8> %t1
} }
define <16 x i8> @test_128_i8_x_16_224_mask_shl_1(<16 x i8> %a0) { define <16 x i8> @test_128_i8_x_16_224_mask_shl_1(<16 x i8> %a0) {
; X86-SSE2-LABEL: test_128_i8_x_16_224_mask_shl_1: ; X86-SSE2-LABEL: test_128_i8_x_16_224_mask_shl_1:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: paddb %xmm0, %xmm0 ; X86-SSE2-NEXT: paddb %xmm0, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i8_x_16_224_mask_shl_1: ; X86-AVX-LABEL: test_128_i8_x_16_224_mask_shl_1:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpaddb %xmm0, %xmm0, %xmm0 ; X86-AVX-NEXT: vpaddb %xmm0, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i8_x_16_224_mask_shl_1: ; X64-SSE2-LABEL: test_128_i8_x_16_224_mask_shl_1:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: paddb %xmm0, %xmm0 ; X64-SSE2-NEXT: paddb %xmm0, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
Show All 12 Lines
; 128-bit vector; 16-bit elements = 8 elements ; 128-bit vector; 16-bit elements = 8 elements
;------------------------------------------------------------------------------; ;------------------------------------------------------------------------------;
; lshr ; lshr
define <8 x i16> @test_128_i16_x_8_127_mask_lshr_1(<8 x i16> %a0) { define <8 x i16> @test_128_i16_x_8_127_mask_lshr_1(<8 x i16> %a0) {
; X86-SSE2-LABEL: test_128_i16_x_8_127_mask_lshr_1: ; X86-SSE2-LABEL: test_128_i16_x_8_127_mask_lshr_1:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlw $1, %xmm0 ; X86-SSE2-NEXT: psrlw $1, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i16_x_8_127_mask_lshr_1: ; X86-AVX-LABEL: test_128_i16_x_8_127_mask_lshr_1:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i16_x_8_127_mask_lshr_1: ; X64-SSE2-LABEL: test_128_i16_x_8_127_mask_lshr_1:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlw $1, %xmm0 ; X64-SSE2-NEXT: psrlw $1, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i16_x_8_127_mask_lshr_1: ; X64-AVX-LABEL: test_128_i16_x_8_127_mask_lshr_1:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127> %t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
%t1 = lshr <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> %t1 = lshr <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
ret <8 x i16> %t1 ret <8 x i16> %t1
} }
define <8 x i16> @test_128_i16_x_8_2032_mask_lshr_3(<8 x i16> %a0) { define <8 x i16> @test_128_i16_x_8_2032_mask_lshr_3(<8 x i16> %a0) {
; X86-SSE2-LABEL: test_128_i16_x_8_2032_mask_lshr_3: ; X86-SSE2-LABEL: test_128_i16_x_8_2032_mask_lshr_3:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlw $3, %xmm0 ; X86-SSE2-NEXT: psrlw $3, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i16_x_8_2032_mask_lshr_3: ; X86-AVX-LABEL: test_128_i16_x_8_2032_mask_lshr_3:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlw $3, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlw $3, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i16_x_8_2032_mask_lshr_3: ; X64-SSE2-LABEL: test_128_i16_x_8_2032_mask_lshr_3:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlw $3, %xmm0 ; X64-SSE2-NEXT: psrlw $3, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i16_x_8_2032_mask_lshr_3: ; X64-AVX-LABEL: test_128_i16_x_8_2032_mask_lshr_3:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlw $3, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlw $3, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032> %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
%t1 = lshr <8 x i16> %t0, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3> %t1 = lshr <8 x i16> %t0, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
ret <8 x i16> %t1 ret <8 x i16> %t1
} }
define <8 x i16> @test_128_i16_x_8_2032_mask_lshr_4(<8 x i16> %a0) { define <8 x i16> @test_128_i16_x_8_2032_mask_lshr_4(<8 x i16> %a0) {
; X86-SSE2-LABEL: test_128_i16_x_8_2032_mask_lshr_4: ; X86-SSE2-LABEL: test_128_i16_x_8_2032_mask_lshr_4:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlw $4, %xmm0 ; X86-SSE2-NEXT: psrlw $4, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i16_x_8_2032_mask_lshr_4: ; X86-AVX-LABEL: test_128_i16_x_8_2032_mask_lshr_4:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlw $4, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlw $4, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i16_x_8_2032_mask_lshr_4: ; X64-SSE2-LABEL: test_128_i16_x_8_2032_mask_lshr_4:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlw $4, %xmm0 ; X64-SSE2-NEXT: psrlw $4, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i16_x_8_2032_mask_lshr_4: ; X64-AVX-LABEL: test_128_i16_x_8_2032_mask_lshr_4:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlw $4, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlw $4, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032> %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
%t1 = lshr <8 x i16> %t0, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4> %t1 = lshr <8 x i16> %t0, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
ret <8 x i16> %t1 ret <8 x i16> %t1
} }
define <8 x i16> @test_128_i16_x_8_2032_mask_lshr_5(<8 x i16> %a0) { define <8 x i16> @test_128_i16_x_8_2032_mask_lshr_5(<8 x i16> %a0) {
; X86-SSE2-LABEL: test_128_i16_x_8_2032_mask_lshr_5: ; X86-SSE2-LABEL: test_128_i16_x_8_2032_mask_lshr_5:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlw $5, %xmm0 ; X86-SSE2-NEXT: psrlw $5, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i16_x_8_2032_mask_lshr_5: ; X86-AVX-LABEL: test_128_i16_x_8_2032_mask_lshr_5:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlw $5, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlw $5, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i16_x_8_2032_mask_lshr_5: ; X64-SSE2-LABEL: test_128_i16_x_8_2032_mask_lshr_5:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlw $5, %xmm0 ; X64-SSE2-NEXT: psrlw $5, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i16_x_8_2032_mask_lshr_5: ; X64-AVX-LABEL: test_128_i16_x_8_2032_mask_lshr_5:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlw $5, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlw $5, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032> %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
%t1 = lshr <8 x i16> %t0, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5> %t1 = lshr <8 x i16> %t0, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
ret <8 x i16> %t1 ret <8 x i16> %t1
} }
define <8 x i16> @test_128_i16_x_8_2032_mask_lshr_6(<8 x i16> %a0) { define <8 x i16> @test_128_i16_x_8_2032_mask_lshr_6(<8 x i16> %a0) {
; X86-SSE2-LABEL: test_128_i16_x_8_2032_mask_lshr_6: ; X86-SSE2-LABEL: test_128_i16_x_8_2032_mask_lshr_6:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlw $6, %xmm0 ; X86-SSE2-NEXT: psrlw $6, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i16_x_8_2032_mask_lshr_6: ; X86-AVX-LABEL: test_128_i16_x_8_2032_mask_lshr_6:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlw $6, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlw $6, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i16_x_8_2032_mask_lshr_6: ; X64-SSE2-LABEL: test_128_i16_x_8_2032_mask_lshr_6:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlw $6, %xmm0 ; X64-SSE2-NEXT: psrlw $6, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i16_x_8_2032_mask_lshr_6: ; X64-AVX-LABEL: test_128_i16_x_8_2032_mask_lshr_6:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlw $6, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlw $6, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032> %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
%t1 = lshr <8 x i16> %t0, <i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6> %t1 = lshr <8 x i16> %t0, <i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6>
ret <8 x i16> %t1 ret <8 x i16> %t1
} }
define <8 x i16> @test_128_i16_x_8_65024_mask_lshr_1(<8 x i16> %a0) { define <8 x i16> @test_128_i16_x_8_65024_mask_lshr_1(<8 x i16> %a0) {
; X86-SSE2-LABEL: test_128_i16_x_8_65024_mask_lshr_1: ; X86-SSE2-LABEL: test_128_i16_x_8_65024_mask_lshr_1:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlw $1, %xmm0 ; X86-SSE2-NEXT: psrlw $1, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i16_x_8_65024_mask_lshr_1: ; X86-AVX-LABEL: test_128_i16_x_8_65024_mask_lshr_1:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i16_x_8_65024_mask_lshr_1: ; X64-SSE2-LABEL: test_128_i16_x_8_65024_mask_lshr_1:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlw $1, %xmm0 ; X64-SSE2-NEXT: psrlw $1, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i16_x_8_65024_mask_lshr_1: ; X64-AVX-LABEL: test_128_i16_x_8_65024_mask_lshr_1:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024> %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>
%t1 = lshr <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> %t1 = lshr <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
ret <8 x i16> %t1 ret <8 x i16> %t1
} }
define <8 x i16> @test_128_i16_x_8_65024_mask_lshr_8(<8 x i16> %a0) { define <8 x i16> @test_128_i16_x_8_65024_mask_lshr_8(<8 x i16> %a0) {
; X86-SSE2-LABEL: test_128_i16_x_8_65024_mask_lshr_8: ; X86-SSE2-LABEL: test_128_i16_x_8_65024_mask_lshr_8:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlw $8, %xmm0 ; X86-SSE2-NEXT: psrlw $8, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i16_x_8_65024_mask_lshr_8: ; X86-AVX-LABEL: test_128_i16_x_8_65024_mask_lshr_8:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlw $8, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlw $8, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i16_x_8_65024_mask_lshr_8: ; X64-SSE2-LABEL: test_128_i16_x_8_65024_mask_lshr_8:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlw $8, %xmm0 ; X64-SSE2-NEXT: psrlw $8, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines; X64-AVX-NEXT: retq
ret <8 x i16> %t1 ret <8 x i16> %t1
} }
; ashr ; ashr
define <8 x i16> @test_128_i16_x_8_127_mask_ashr_1(<8 x i16> %a0) { define <8 x i16> @test_128_i16_x_8_127_mask_ashr_1(<8 x i16> %a0) {
; X86-SSE2-LABEL: test_128_i16_x_8_127_mask_ashr_1: ; X86-SSE2-LABEL: test_128_i16_x_8_127_mask_ashr_1:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlw $1, %xmm0 ; X86-SSE2-NEXT: psrlw $1, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i16_x_8_127_mask_ashr_1: ; X86-AVX-LABEL: test_128_i16_x_8_127_mask_ashr_1:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i16_x_8_127_mask_ashr_1: ; X64-SSE2-LABEL: test_128_i16_x_8_127_mask_ashr_1:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlw $1, %xmm0 ; X64-SSE2-NEXT: psrlw $1, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i16_x_8_127_mask_ashr_1: ; X64-AVX-LABEL: test_128_i16_x_8_127_mask_ashr_1:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlw $1, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127> %t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
%t1 = ashr <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> %t1 = ashr <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
ret <8 x i16> %t1 ret <8 x i16> %t1
} }
define <8 x i16> @test_128_i16_x_8_2032_mask_ashr_3(<8 x i16> %a0) { define <8 x i16> @test_128_i16_x_8_2032_mask_ashr_3(<8 x i16> %a0) {
; X86-SSE2-LABEL: test_128_i16_x_8_2032_mask_ashr_3: ; X86-SSE2-LABEL: test_128_i16_x_8_2032_mask_ashr_3:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlw $3, %xmm0 ; X86-SSE2-NEXT: psrlw $3, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i16_x_8_2032_mask_ashr_3: ; X86-AVX-LABEL: test_128_i16_x_8_2032_mask_ashr_3:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlw $3, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlw $3, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i16_x_8_2032_mask_ashr_3: ; X64-SSE2-LABEL: test_128_i16_x_8_2032_mask_ashr_3:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlw $3, %xmm0 ; X64-SSE2-NEXT: psrlw $3, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i16_x_8_2032_mask_ashr_3: ; X64-AVX-LABEL: test_128_i16_x_8_2032_mask_ashr_3:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlw $3, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlw $3, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032> %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
%t1 = ashr <8 x i16> %t0, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3> %t1 = ashr <8 x i16> %t0, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
ret <8 x i16> %t1 ret <8 x i16> %t1
} }
define <8 x i16> @test_128_i16_x_8_2032_mask_ashr_4(<8 x i16> %a0) { define <8 x i16> @test_128_i16_x_8_2032_mask_ashr_4(<8 x i16> %a0) {
; X86-SSE2-LABEL: test_128_i16_x_8_2032_mask_ashr_4: ; X86-SSE2-LABEL: test_128_i16_x_8_2032_mask_ashr_4:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlw $4, %xmm0 ; X86-SSE2-NEXT: psrlw $4, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i16_x_8_2032_mask_ashr_4: ; X86-AVX-LABEL: test_128_i16_x_8_2032_mask_ashr_4:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlw $4, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlw $4, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i16_x_8_2032_mask_ashr_4: ; X64-SSE2-LABEL: test_128_i16_x_8_2032_mask_ashr_4:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlw $4, %xmm0 ; X64-SSE2-NEXT: psrlw $4, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i16_x_8_2032_mask_ashr_4: ; X64-AVX-LABEL: test_128_i16_x_8_2032_mask_ashr_4:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlw $4, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlw $4, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032> %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
%t1 = ashr <8 x i16> %t0, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4> %t1 = ashr <8 x i16> %t0, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
ret <8 x i16> %t1 ret <8 x i16> %t1
} }
define <8 x i16> @test_128_i16_x_8_2032_mask_ashr_5(<8 x i16> %a0) { define <8 x i16> @test_128_i16_x_8_2032_mask_ashr_5(<8 x i16> %a0) {
; X86-SSE2-LABEL: test_128_i16_x_8_2032_mask_ashr_5: ; X86-SSE2-LABEL: test_128_i16_x_8_2032_mask_ashr_5:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlw $5, %xmm0 ; X86-SSE2-NEXT: psrlw $5, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i16_x_8_2032_mask_ashr_5: ; X86-AVX-LABEL: test_128_i16_x_8_2032_mask_ashr_5:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlw $5, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlw $5, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i16_x_8_2032_mask_ashr_5: ; X64-SSE2-LABEL: test_128_i16_x_8_2032_mask_ashr_5:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlw $5, %xmm0 ; X64-SSE2-NEXT: psrlw $5, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i16_x_8_2032_mask_ashr_5: ; X64-AVX-LABEL: test_128_i16_x_8_2032_mask_ashr_5:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlw $5, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlw $5, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032> %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
%t1 = ashr <8 x i16> %t0, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5> %t1 = ashr <8 x i16> %t0, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
ret <8 x i16> %t1 ret <8 x i16> %t1
} }
define <8 x i16> @test_128_i16_x_8_2032_mask_ashr_6(<8 x i16> %a0) { define <8 x i16> @test_128_i16_x_8_2032_mask_ashr_6(<8 x i16> %a0) {
; X86-SSE2-LABEL: test_128_i16_x_8_2032_mask_ashr_6: ; X86-SSE2-LABEL: test_128_i16_x_8_2032_mask_ashr_6:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlw $6, %xmm0 ; X86-SSE2-NEXT: psrlw $6, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i16_x_8_2032_mask_ashr_6: ; X86-AVX-LABEL: test_128_i16_x_8_2032_mask_ashr_6:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlw $6, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlw $6, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i16_x_8_2032_mask_ashr_6: ; X64-SSE2-LABEL: test_128_i16_x_8_2032_mask_ashr_6:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlw $6, %xmm0 ; X64-SSE2-NEXT: psrlw $6, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i16_x_8_2032_mask_ashr_6: ; X64-AVX-LABEL: test_128_i16_x_8_2032_mask_ashr_6:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlw $6, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlw $6, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032> %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
%t1 = ashr <8 x i16> %t0, <i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6> %t1 = ashr <8 x i16> %t0, <i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6>
ret <8 x i16> %t1 ret <8 x i16> %t1
} }
define <8 x i16> @test_128_i16_x_8_65024_mask_ashr_1(<8 x i16> %a0) { define <8 x i16> @test_128_i16_x_8_65024_mask_ashr_1(<8 x i16> %a0) {
; X86-SSE2-LABEL: test_128_i16_x_8_65024_mask_ashr_1: ; X86-SSE2-LABEL: test_128_i16_x_8_65024_mask_ashr_1:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psraw $1, %xmm0 ; X86-SSE2-NEXT: psraw $1, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i16_x_8_65024_mask_ashr_1: ; X86-AVX-LABEL: test_128_i16_x_8_65024_mask_ashr_1:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsraw $1, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsraw $1, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i16_x_8_65024_mask_ashr_1: ; X64-SSE2-LABEL: test_128_i16_x_8_65024_mask_ashr_1:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psraw $1, %xmm0 ; X64-SSE2-NEXT: psraw $1, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i16_x_8_65024_mask_ashr_1: ; X64-AVX-LABEL: test_128_i16_x_8_65024_mask_ashr_1:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsraw $1, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsraw $1, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024> %t0 = and <8 x i16> %a0, <i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024, i16 65024>
%t1 = ashr <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> %t1 = ashr <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
ret <8 x i16> %t1 ret <8 x i16> %t1
} }
define <8 x i16> @test_128_i16_x_8_65024_mask_ashr_8(<8 x i16> %a0) { define <8 x i16> @test_128_i16_x_8_65024_mask_ashr_8(<8 x i16> %a0) {
; X86-SSE2-LABEL: test_128_i16_x_8_65024_mask_ashr_8: ; X86-SSE2-LABEL: test_128_i16_x_8_65024_mask_ashr_8:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psraw $8, %xmm0 ; X86-SSE2-NEXT: psraw $8, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i16_x_8_65024_mask_ashr_8: ; X86-AVX-LABEL: test_128_i16_x_8_65024_mask_ashr_8:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsraw $8, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsraw $8, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i16_x_8_65024_mask_ashr_8: ; X64-SSE2-LABEL: test_128_i16_x_8_65024_mask_ashr_8:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psraw $8, %xmm0 ; X64-SSE2-NEXT: psraw $8, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
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ret <8 x i16> %t1 ret <8 x i16> %t1
} }
; shl ; shl
define <8 x i16> @test_128_i16_x_8_127_mask_shl_1(<8 x i16> %a0) { define <8 x i16> @test_128_i16_x_8_127_mask_shl_1(<8 x i16> %a0) {
; X86-SSE2-LABEL: test_128_i16_x_8_127_mask_shl_1: ; X86-SSE2-LABEL: test_128_i16_x_8_127_mask_shl_1:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: paddw %xmm0, %xmm0 ; X86-SSE2-NEXT: paddw %xmm0, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i16_x_8_127_mask_shl_1: ; X86-AVX-LABEL: test_128_i16_x_8_127_mask_shl_1:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpaddw %xmm0, %xmm0, %xmm0 ; X86-AVX-NEXT: vpaddw %xmm0, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i16_x_8_127_mask_shl_1: ; X64-SSE2-LABEL: test_128_i16_x_8_127_mask_shl_1:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: paddw %xmm0, %xmm0 ; X64-SSE2-NEXT: paddw %xmm0, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i16_x_8_127_mask_shl_1: ; X64-AVX-LABEL: test_128_i16_x_8_127_mask_shl_1:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpaddw %xmm0, %xmm0, %xmm0 ; X64-AVX-NEXT: vpaddw %xmm0, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127> %t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
%t1 = shl <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> %t1 = shl <8 x i16> %t0, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
ret <8 x i16> %t1 ret <8 x i16> %t1
} }
define <8 x i16> @test_128_i16_x_8_127_mask_shl_8(<8 x i16> %a0) { define <8 x i16> @test_128_i16_x_8_127_mask_shl_8(<8 x i16> %a0) {
; X86-SSE2-LABEL: test_128_i16_x_8_127_mask_shl_8: ; X86-SSE2-LABEL: test_128_i16_x_8_127_mask_shl_8:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psllw $8, %xmm0 ; X86-SSE2-NEXT: psllw $8, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i16_x_8_127_mask_shl_8: ; X86-AVX-LABEL: test_128_i16_x_8_127_mask_shl_8:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsllw $8, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsllw $8, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i16_x_8_127_mask_shl_8: ; X64-SSE2-LABEL: test_128_i16_x_8_127_mask_shl_8:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psllw $8, %xmm0 ; X64-SSE2-NEXT: psllw $8, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
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%t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127> %t0 = and <8 x i16> %a0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
%t1 = shl <8 x i16> %t0, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10> %t1 = shl <8 x i16> %t0, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>
ret <8 x i16> %t1 ret <8 x i16> %t1
} }
define <8 x i16> @test_128_i16_x_8_2032_mask_shl_3(<8 x i16> %a0) { define <8 x i16> @test_128_i16_x_8_2032_mask_shl_3(<8 x i16> %a0) {
; X86-SSE2-LABEL: test_128_i16_x_8_2032_mask_shl_3: ; X86-SSE2-LABEL: test_128_i16_x_8_2032_mask_shl_3:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psllw $3, %xmm0 ; X86-SSE2-NEXT: psllw $3, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i16_x_8_2032_mask_shl_3: ; X86-AVX-LABEL: test_128_i16_x_8_2032_mask_shl_3:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsllw $3, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsllw $3, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i16_x_8_2032_mask_shl_3: ; X64-SSE2-LABEL: test_128_i16_x_8_2032_mask_shl_3:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psllw $3, %xmm0 ; X64-SSE2-NEXT: psllw $3, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i16_x_8_2032_mask_shl_3: ; X64-AVX-LABEL: test_128_i16_x_8_2032_mask_shl_3:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsllw $3, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsllw $3, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032> %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
%t1 = shl <8 x i16> %t0, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3> %t1 = shl <8 x i16> %t0, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
ret <8 x i16> %t1 ret <8 x i16> %t1
} }
define <8 x i16> @test_128_i16_x_8_2032_mask_shl_4(<8 x i16> %a0) { define <8 x i16> @test_128_i16_x_8_2032_mask_shl_4(<8 x i16> %a0) {
; X86-SSE2-LABEL: test_128_i16_x_8_2032_mask_shl_4: ; X86-SSE2-LABEL: test_128_i16_x_8_2032_mask_shl_4:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psllw $4, %xmm0 ; X86-SSE2-NEXT: psllw $4, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i16_x_8_2032_mask_shl_4: ; X86-AVX-LABEL: test_128_i16_x_8_2032_mask_shl_4:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsllw $4, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsllw $4, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i16_x_8_2032_mask_shl_4: ; X64-SSE2-LABEL: test_128_i16_x_8_2032_mask_shl_4:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psllw $4, %xmm0 ; X64-SSE2-NEXT: psllw $4, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i16_x_8_2032_mask_shl_4: ; X64-AVX-LABEL: test_128_i16_x_8_2032_mask_shl_4:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsllw $4, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsllw $4, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032> %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
%t1 = shl <8 x i16> %t0, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4> %t1 = shl <8 x i16> %t0, <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>
ret <8 x i16> %t1 ret <8 x i16> %t1
} }
define <8 x i16> @test_128_i16_x_8_2032_mask_shl_5(<8 x i16> %a0) { define <8 x i16> @test_128_i16_x_8_2032_mask_shl_5(<8 x i16> %a0) {
; X86-SSE2-LABEL: test_128_i16_x_8_2032_mask_shl_5: ; X86-SSE2-LABEL: test_128_i16_x_8_2032_mask_shl_5:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psllw $5, %xmm0 ; X86-SSE2-NEXT: psllw $5, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i16_x_8_2032_mask_shl_5: ; X86-AVX-LABEL: test_128_i16_x_8_2032_mask_shl_5:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsllw $5, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsllw $5, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i16_x_8_2032_mask_shl_5: ; X64-SSE2-LABEL: test_128_i16_x_8_2032_mask_shl_5:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psllw $5, %xmm0 ; X64-SSE2-NEXT: psllw $5, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i16_x_8_2032_mask_shl_5: ; X64-AVX-LABEL: test_128_i16_x_8_2032_mask_shl_5:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsllw $5, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsllw $5, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032> %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
%t1 = shl <8 x i16> %t0, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5> %t1 = shl <8 x i16> %t0, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
ret <8 x i16> %t1 ret <8 x i16> %t1
} }
define <8 x i16> @test_128_i16_x_8_2032_mask_shl_6(<8 x i16> %a0) { define <8 x i16> @test_128_i16_x_8_2032_mask_shl_6(<8 x i16> %a0) {
; X86-SSE2-LABEL: test_128_i16_x_8_2032_mask_shl_6: ; X86-SSE2-LABEL: test_128_i16_x_8_2032_mask_shl_6:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psllw $6, %xmm0 ; X86-SSE2-NEXT: psllw $6, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i16_x_8_2032_mask_shl_6: ; X86-AVX-LABEL: test_128_i16_x_8_2032_mask_shl_6:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsllw $6, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsllw $6, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i16_x_8_2032_mask_shl_6: ; X64-SSE2-LABEL: test_128_i16_x_8_2032_mask_shl_6:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psllw $6, %xmm0 ; X64-SSE2-NEXT: psllw $6, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i16_x_8_2032_mask_shl_6: ; X64-AVX-LABEL: test_128_i16_x_8_2032_mask_shl_6:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsllw $6, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsllw $6, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032> %t0 = and <8 x i16> %a0, <i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032, i16 2032>
%t1 = shl <8 x i16> %t0, <i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6> %t1 = shl <8 x i16> %t0, <i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6, i16 6>
ret <8 x i16> %t1 ret <8 x i16> %t1
} }
define <8 x i16> @test_128_i16_x_8_65024_mask_shl_1(<8 x i16> %a0) { define <8 x i16> @test_128_i16_x_8_65024_mask_shl_1(<8 x i16> %a0) {
; X86-SSE2-LABEL: test_128_i16_x_8_65024_mask_shl_1: ; X86-SSE2-LABEL: test_128_i16_x_8_65024_mask_shl_1:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: paddw %xmm0, %xmm0 ; X86-SSE2-NEXT: paddw %xmm0, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i16_x_8_65024_mask_shl_1: ; X86-AVX-LABEL: test_128_i16_x_8_65024_mask_shl_1:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpaddw %xmm0, %xmm0, %xmm0 ; X86-AVX-NEXT: vpaddw %xmm0, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i16_x_8_65024_mask_shl_1: ; X64-SSE2-LABEL: test_128_i16_x_8_65024_mask_shl_1:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: paddw %xmm0, %xmm0 ; X64-SSE2-NEXT: paddw %xmm0, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
Show All 12 Lines
; 128-bit vector; 32-bit elements = 4 elements ; 128-bit vector; 32-bit elements = 4 elements
;------------------------------------------------------------------------------; ;------------------------------------------------------------------------------;
; lshr ; lshr
define <4 x i32> @test_128_i32_x_4_32767_mask_lshr_1(<4 x i32> %a0) { define <4 x i32> @test_128_i32_x_4_32767_mask_lshr_1(<4 x i32> %a0) {
; X86-SSE2-LABEL: test_128_i32_x_4_32767_mask_lshr_1: ; X86-SSE2-LABEL: test_128_i32_x_4_32767_mask_lshr_1:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrld $1, %xmm0 ; X86-SSE2-NEXT: psrld $1, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX1-LABEL: test_128_i32_x_4_32767_mask_lshr_1: ; X86-AVX1-LABEL: test_128_i32_x_4_32767_mask_lshr_1:
; X86-AVX1: # %bb.0: ; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vpsrld $1, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpsrld $1, %xmm0, %xmm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: test_128_i32_x_4_32767_mask_lshr_1: ; X86-AVX2-LABEL: test_128_i32_x_4_32767_mask_lshr_1:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [32767,32767,32767,32767] ; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [32767,32767,32767,32767]
; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpsrld $1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpsrld $1, %xmm0, %xmm0
Show All 20 Lines; X64-AVX2-NEXT: retq
%t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767> %t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>
%t1 = lshr <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1> %t1 = lshr <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @test_128_i32_x_4_8388352_mask_lshr_7(<4 x i32> %a0) { define <4 x i32> @test_128_i32_x_4_8388352_mask_lshr_7(<4 x i32> %a0) {
; X86-SSE2-LABEL: test_128_i32_x_4_8388352_mask_lshr_7: ; X86-SSE2-LABEL: test_128_i32_x_4_8388352_mask_lshr_7:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrld $7, %xmm0 ; X86-SSE2-NEXT: psrld $7, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX1-LABEL: test_128_i32_x_4_8388352_mask_lshr_7: ; X86-AVX1-LABEL: test_128_i32_x_4_8388352_mask_lshr_7:
; X86-AVX1: # %bb.0: ; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vpsrld $7, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpsrld $7, %xmm0, %xmm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: test_128_i32_x_4_8388352_mask_lshr_7: ; X86-AVX2-LABEL: test_128_i32_x_4_8388352_mask_lshr_7:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352] ; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpsrld $7, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpsrld $7, %xmm0, %xmm0
Show All 19 Lines
; X64-AVX2-NEXT: retq ; X64-AVX2-NEXT: retq
%t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352> %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
%t1 = lshr <4 x i32> %t0, <i32 7, i32 7, i32 7, i32 7> %t1 = lshr <4 x i32> %t0, <i32 7, i32 7, i32 7, i32 7>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @test_128_i32_x_4_8388352_mask_lshr_8(<4 x i32> %a0) { define <4 x i32> @test_128_i32_x_4_8388352_mask_lshr_8(<4 x i32> %a0) {
; X86-SSE2-LABEL: test_128_i32_x_4_8388352_mask_lshr_8: ; X86-SSE2-LABEL: test_128_i32_x_4_8388352_mask_lshr_8:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrld $8, %xmm0 ; X86-SSE2-NEXT: psrld $8, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX1-LABEL: test_128_i32_x_4_8388352_mask_lshr_8: ; X86-AVX1-LABEL: test_128_i32_x_4_8388352_mask_lshr_8:
; X86-AVX1: # %bb.0: ; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vpsrld $8, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpsrld $8, %xmm0, %xmm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: test_128_i32_x_4_8388352_mask_lshr_8: ; X86-AVX2-LABEL: test_128_i32_x_4_8388352_mask_lshr_8:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352] ; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpsrld $8, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpsrld $8, %xmm0, %xmm0
Show All 19 Lines
; X64-AVX2-NEXT: retq ; X64-AVX2-NEXT: retq
%t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352> %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
%t1 = lshr <4 x i32> %t0, <i32 8, i32 8, i32 8, i32 8> %t1 = lshr <4 x i32> %t0, <i32 8, i32 8, i32 8, i32 8>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @test_128_i32_x_4_8388352_mask_lshr_9(<4 x i32> %a0) { define <4 x i32> @test_128_i32_x_4_8388352_mask_lshr_9(<4 x i32> %a0) {
; X86-SSE2-LABEL: test_128_i32_x_4_8388352_mask_lshr_9: ; X86-SSE2-LABEL: test_128_i32_x_4_8388352_mask_lshr_9:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrld $9, %xmm0 ; X86-SSE2-NEXT: psrld $9, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX1-LABEL: test_128_i32_x_4_8388352_mask_lshr_9: ; X86-AVX1-LABEL: test_128_i32_x_4_8388352_mask_lshr_9:
; X86-AVX1: # %bb.0: ; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vpsrld $9, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpsrld $9, %xmm0, %xmm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: test_128_i32_x_4_8388352_mask_lshr_9: ; X86-AVX2-LABEL: test_128_i32_x_4_8388352_mask_lshr_9:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352] ; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpsrld $9, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpsrld $9, %xmm0, %xmm0
Show All 19 Lines
; X64-AVX2-NEXT: retq ; X64-AVX2-NEXT: retq
%t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352> %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
%t1 = lshr <4 x i32> %t0, <i32 9, i32 9, i32 9, i32 9> %t1 = lshr <4 x i32> %t0, <i32 9, i32 9, i32 9, i32 9>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @test_128_i32_x_4_8388352_mask_lshr_10(<4 x i32> %a0) { define <4 x i32> @test_128_i32_x_4_8388352_mask_lshr_10(<4 x i32> %a0) {
; X86-SSE2-LABEL: test_128_i32_x_4_8388352_mask_lshr_10: ; X86-SSE2-LABEL: test_128_i32_x_4_8388352_mask_lshr_10:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrld $10, %xmm0 ; X86-SSE2-NEXT: psrld $10, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX1-LABEL: test_128_i32_x_4_8388352_mask_lshr_10: ; X86-AVX1-LABEL: test_128_i32_x_4_8388352_mask_lshr_10:
; X86-AVX1: # %bb.0: ; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vpsrld $10, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpsrld $10, %xmm0, %xmm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: test_128_i32_x_4_8388352_mask_lshr_10: ; X86-AVX2-LABEL: test_128_i32_x_4_8388352_mask_lshr_10:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352] ; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpsrld $10, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpsrld $10, %xmm0, %xmm0
Show All 20 Lines; X64-AVX2-NEXT: retq
%t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352> %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
%t1 = lshr <4 x i32> %t0, <i32 10, i32 10, i32 10, i32 10> %t1 = lshr <4 x i32> %t0, <i32 10, i32 10, i32 10, i32 10>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @test_128_i32_x_4_4294836224_mask_lshr_1(<4 x i32> %a0) { define <4 x i32> @test_128_i32_x_4_4294836224_mask_lshr_1(<4 x i32> %a0) {
; X86-SSE2-LABEL: test_128_i32_x_4_4294836224_mask_lshr_1: ; X86-SSE2-LABEL: test_128_i32_x_4_4294836224_mask_lshr_1:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrld $1, %xmm0 ; X86-SSE2-NEXT: psrld $1, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX1-LABEL: test_128_i32_x_4_4294836224_mask_lshr_1: ; X86-AVX1-LABEL: test_128_i32_x_4_4294836224_mask_lshr_1:
; X86-AVX1: # %bb.0: ; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vpsrld $1, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpsrld $1, %xmm0, %xmm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: test_128_i32_x_4_4294836224_mask_lshr_1: ; X86-AVX2-LABEL: test_128_i32_x_4_4294836224_mask_lshr_1:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [4294836224,4294836224,4294836224,4294836224] ; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [4294836224,4294836224,4294836224,4294836224]
; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpsrld $1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpsrld $1, %xmm0, %xmm0
Show All 19 Lines
; X64-AVX2-NEXT: retq ; X64-AVX2-NEXT: retq
%t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224> %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>
%t1 = lshr <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1> %t1 = lshr <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @test_128_i32_x_4_4294836224_mask_lshr_16(<4 x i32> %a0) { define <4 x i32> @test_128_i32_x_4_4294836224_mask_lshr_16(<4 x i32> %a0) {
; X86-SSE2-LABEL: test_128_i32_x_4_4294836224_mask_lshr_16: ; X86-SSE2-LABEL: test_128_i32_x_4_4294836224_mask_lshr_16:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrld $16, %xmm0 ; X86-SSE2-NEXT: psrld $16, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX1-LABEL: test_128_i32_x_4_4294836224_mask_lshr_16: ; X86-AVX1-LABEL: test_128_i32_x_4_4294836224_mask_lshr_16:
; X86-AVX1: # %bb.0: ; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vpsrld $16, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpsrld $16, %xmm0, %xmm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: test_128_i32_x_4_4294836224_mask_lshr_16: ; X86-AVX2-LABEL: test_128_i32_x_4_4294836224_mask_lshr_16:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [4294836224,4294836224,4294836224,4294836224] ; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [4294836224,4294836224,4294836224,4294836224]
; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpsrld $16, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpsrld $16, %xmm0, %xmm0
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines; X64-AVX-NEXT: retq
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
; ashr ; ashr
define <4 x i32> @test_128_i32_x_4_32767_mask_ashr_1(<4 x i32> %a0) { define <4 x i32> @test_128_i32_x_4_32767_mask_ashr_1(<4 x i32> %a0) {
; X86-SSE2-LABEL: test_128_i32_x_4_32767_mask_ashr_1: ; X86-SSE2-LABEL: test_128_i32_x_4_32767_mask_ashr_1:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrld $1, %xmm0 ; X86-SSE2-NEXT: psrld $1, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX1-LABEL: test_128_i32_x_4_32767_mask_ashr_1: ; X86-AVX1-LABEL: test_128_i32_x_4_32767_mask_ashr_1:
; X86-AVX1: # %bb.0: ; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vpsrld $1, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpsrld $1, %xmm0, %xmm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: test_128_i32_x_4_32767_mask_ashr_1: ; X86-AVX2-LABEL: test_128_i32_x_4_32767_mask_ashr_1:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [32767,32767,32767,32767] ; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [32767,32767,32767,32767]
; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpsrld $1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpsrld $1, %xmm0, %xmm0
Show All 20 Lines; X64-AVX2-NEXT: retq
%t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767> %t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>
%t1 = ashr <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1> %t1 = ashr <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @test_128_i32_x_4_8388352_mask_ashr_7(<4 x i32> %a0) { define <4 x i32> @test_128_i32_x_4_8388352_mask_ashr_7(<4 x i32> %a0) {
; X86-SSE2-LABEL: test_128_i32_x_4_8388352_mask_ashr_7: ; X86-SSE2-LABEL: test_128_i32_x_4_8388352_mask_ashr_7:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrld $7, %xmm0 ; X86-SSE2-NEXT: psrld $7, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX1-LABEL: test_128_i32_x_4_8388352_mask_ashr_7: ; X86-AVX1-LABEL: test_128_i32_x_4_8388352_mask_ashr_7:
; X86-AVX1: # %bb.0: ; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vpsrld $7, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpsrld $7, %xmm0, %xmm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: test_128_i32_x_4_8388352_mask_ashr_7: ; X86-AVX2-LABEL: test_128_i32_x_4_8388352_mask_ashr_7:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352] ; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpsrld $7, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpsrld $7, %xmm0, %xmm0
Show All 19 Lines
; X64-AVX2-NEXT: retq ; X64-AVX2-NEXT: retq
%t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352> %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
%t1 = ashr <4 x i32> %t0, <i32 7, i32 7, i32 7, i32 7> %t1 = ashr <4 x i32> %t0, <i32 7, i32 7, i32 7, i32 7>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @test_128_i32_x_4_8388352_mask_ashr_8(<4 x i32> %a0) { define <4 x i32> @test_128_i32_x_4_8388352_mask_ashr_8(<4 x i32> %a0) {
; X86-SSE2-LABEL: test_128_i32_x_4_8388352_mask_ashr_8: ; X86-SSE2-LABEL: test_128_i32_x_4_8388352_mask_ashr_8:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrld $8, %xmm0 ; X86-SSE2-NEXT: psrld $8, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX1-LABEL: test_128_i32_x_4_8388352_mask_ashr_8: ; X86-AVX1-LABEL: test_128_i32_x_4_8388352_mask_ashr_8:
; X86-AVX1: # %bb.0: ; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vpsrld $8, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpsrld $8, %xmm0, %xmm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: test_128_i32_x_4_8388352_mask_ashr_8: ; X86-AVX2-LABEL: test_128_i32_x_4_8388352_mask_ashr_8:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352] ; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpsrld $8, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpsrld $8, %xmm0, %xmm0
Show All 19 Lines
; X64-AVX2-NEXT: retq ; X64-AVX2-NEXT: retq
%t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352> %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
%t1 = ashr <4 x i32> %t0, <i32 8, i32 8, i32 8, i32 8> %t1 = ashr <4 x i32> %t0, <i32 8, i32 8, i32 8, i32 8>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @test_128_i32_x_4_8388352_mask_ashr_9(<4 x i32> %a0) { define <4 x i32> @test_128_i32_x_4_8388352_mask_ashr_9(<4 x i32> %a0) {
; X86-SSE2-LABEL: test_128_i32_x_4_8388352_mask_ashr_9: ; X86-SSE2-LABEL: test_128_i32_x_4_8388352_mask_ashr_9:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrld $9, %xmm0 ; X86-SSE2-NEXT: psrld $9, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX1-LABEL: test_128_i32_x_4_8388352_mask_ashr_9: ; X86-AVX1-LABEL: test_128_i32_x_4_8388352_mask_ashr_9:
; X86-AVX1: # %bb.0: ; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vpsrld $9, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpsrld $9, %xmm0, %xmm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: test_128_i32_x_4_8388352_mask_ashr_9: ; X86-AVX2-LABEL: test_128_i32_x_4_8388352_mask_ashr_9:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352] ; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpsrld $9, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpsrld $9, %xmm0, %xmm0
Show All 19 Lines
; X64-AVX2-NEXT: retq ; X64-AVX2-NEXT: retq
%t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352> %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
%t1 = ashr <4 x i32> %t0, <i32 9, i32 9, i32 9, i32 9> %t1 = ashr <4 x i32> %t0, <i32 9, i32 9, i32 9, i32 9>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @test_128_i32_x_4_8388352_mask_ashr_10(<4 x i32> %a0) { define <4 x i32> @test_128_i32_x_4_8388352_mask_ashr_10(<4 x i32> %a0) {
; X86-SSE2-LABEL: test_128_i32_x_4_8388352_mask_ashr_10: ; X86-SSE2-LABEL: test_128_i32_x_4_8388352_mask_ashr_10:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrld $10, %xmm0 ; X86-SSE2-NEXT: psrld $10, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX1-LABEL: test_128_i32_x_4_8388352_mask_ashr_10: ; X86-AVX1-LABEL: test_128_i32_x_4_8388352_mask_ashr_10:
; X86-AVX1: # %bb.0: ; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vpsrld $10, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpsrld $10, %xmm0, %xmm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: test_128_i32_x_4_8388352_mask_ashr_10: ; X86-AVX2-LABEL: test_128_i32_x_4_8388352_mask_ashr_10:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352] ; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpsrld $10, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpsrld $10, %xmm0, %xmm0
Show All 20 Lines; X64-AVX2-NEXT: retq
%t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352> %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
%t1 = ashr <4 x i32> %t0, <i32 10, i32 10, i32 10, i32 10> %t1 = ashr <4 x i32> %t0, <i32 10, i32 10, i32 10, i32 10>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @test_128_i32_x_4_4294836224_mask_ashr_1(<4 x i32> %a0) { define <4 x i32> @test_128_i32_x_4_4294836224_mask_ashr_1(<4 x i32> %a0) {
; X86-SSE2-LABEL: test_128_i32_x_4_4294836224_mask_ashr_1: ; X86-SSE2-LABEL: test_128_i32_x_4_4294836224_mask_ashr_1:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrad $1, %xmm0 ; X86-SSE2-NEXT: psrad $1, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX1-LABEL: test_128_i32_x_4_4294836224_mask_ashr_1: ; X86-AVX1-LABEL: test_128_i32_x_4_4294836224_mask_ashr_1:
; X86-AVX1: # %bb.0: ; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vpsrad $1, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpsrad $1, %xmm0, %xmm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: test_128_i32_x_4_4294836224_mask_ashr_1: ; X86-AVX2-LABEL: test_128_i32_x_4_4294836224_mask_ashr_1:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [4294836224,4294836224,4294836224,4294836224] ; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [4294836224,4294836224,4294836224,4294836224]
; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpsrad $1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpsrad $1, %xmm0, %xmm0
Show All 19 Lines
; X64-AVX2-NEXT: retq ; X64-AVX2-NEXT: retq
%t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224> %t0 = and <4 x i32> %a0, <i32 4294836224, i32 4294836224, i32 4294836224, i32 4294836224>
%t1 = ashr <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1> %t1 = ashr <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @test_128_i32_x_4_4294836224_mask_ashr_16(<4 x i32> %a0) { define <4 x i32> @test_128_i32_x_4_4294836224_mask_ashr_16(<4 x i32> %a0) {
; X86-SSE2-LABEL: test_128_i32_x_4_4294836224_mask_ashr_16: ; X86-SSE2-LABEL: test_128_i32_x_4_4294836224_mask_ashr_16:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrad $16, %xmm0 ; X86-SSE2-NEXT: psrad $16, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX1-LABEL: test_128_i32_x_4_4294836224_mask_ashr_16: ; X86-AVX1-LABEL: test_128_i32_x_4_4294836224_mask_ashr_16:
; X86-AVX1: # %bb.0: ; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vpsrad $16, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpsrad $16, %xmm0, %xmm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: test_128_i32_x_4_4294836224_mask_ashr_16: ; X86-AVX2-LABEL: test_128_i32_x_4_4294836224_mask_ashr_16:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [4294836224,4294836224,4294836224,4294836224] ; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [4294836224,4294836224,4294836224,4294836224]
; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpsrad $16, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpsrad $16, %xmm0, %xmm0
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines; X64-AVX-NEXT: retq
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
; shl ; shl
define <4 x i32> @test_128_i32_x_4_32767_mask_shl_1(<4 x i32> %a0) { define <4 x i32> @test_128_i32_x_4_32767_mask_shl_1(<4 x i32> %a0) {
; X86-SSE2-LABEL: test_128_i32_x_4_32767_mask_shl_1: ; X86-SSE2-LABEL: test_128_i32_x_4_32767_mask_shl_1:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: paddd %xmm0, %xmm0 ; X86-SSE2-NEXT: paddd %xmm0, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX1-LABEL: test_128_i32_x_4_32767_mask_shl_1: ; X86-AVX1-LABEL: test_128_i32_x_4_32767_mask_shl_1:
; X86-AVX1: # %bb.0: ; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vpaddd %xmm0, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpaddd %xmm0, %xmm0, %xmm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: test_128_i32_x_4_32767_mask_shl_1: ; X86-AVX2-LABEL: test_128_i32_x_4_32767_mask_shl_1:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [32767,32767,32767,32767] ; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [32767,32767,32767,32767]
; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpaddd %xmm0, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpaddd %xmm0, %xmm0, %xmm0
Show All 19 Lines
; X64-AVX2-NEXT: retq ; X64-AVX2-NEXT: retq
%t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767> %t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>
%t1 = shl <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1> %t1 = shl <4 x i32> %t0, <i32 1, i32 1, i32 1, i32 1>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @test_128_i32_x_4_32767_mask_shl_16(<4 x i32> %a0) { define <4 x i32> @test_128_i32_x_4_32767_mask_shl_16(<4 x i32> %a0) {
; X86-SSE2-LABEL: test_128_i32_x_4_32767_mask_shl_16: ; X86-SSE2-LABEL: test_128_i32_x_4_32767_mask_shl_16:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pslld $16, %xmm0 ; X86-SSE2-NEXT: pslld $16, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX1-LABEL: test_128_i32_x_4_32767_mask_shl_16: ; X86-AVX1-LABEL: test_128_i32_x_4_32767_mask_shl_16:
; X86-AVX1: # %bb.0: ; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vpslld $16, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpslld $16, %xmm0, %xmm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: test_128_i32_x_4_32767_mask_shl_16: ; X86-AVX2-LABEL: test_128_i32_x_4_32767_mask_shl_16:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [32767,32767,32767,32767] ; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [32767,32767,32767,32767]
; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpslld $16, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpslld $16, %xmm0, %xmm0
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines; X64-AVX-NEXT: retq
%t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767> %t0 = and <4 x i32> %a0, <i32 32767, i32 32767, i32 32767, i32 32767>
%t1 = shl <4 x i32> %t0, <i32 18, i32 18, i32 18, i32 18> %t1 = shl <4 x i32> %t0, <i32 18, i32 18, i32 18, i32 18>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @test_128_i32_x_4_8388352_mask_shl_7(<4 x i32> %a0) { define <4 x i32> @test_128_i32_x_4_8388352_mask_shl_7(<4 x i32> %a0) {
; X86-SSE2-LABEL: test_128_i32_x_4_8388352_mask_shl_7: ; X86-SSE2-LABEL: test_128_i32_x_4_8388352_mask_shl_7:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pslld $7, %xmm0 ; X86-SSE2-NEXT: pslld $7, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX1-LABEL: test_128_i32_x_4_8388352_mask_shl_7: ; X86-AVX1-LABEL: test_128_i32_x_4_8388352_mask_shl_7:
; X86-AVX1: # %bb.0: ; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vpslld $7, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpslld $7, %xmm0, %xmm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: test_128_i32_x_4_8388352_mask_shl_7: ; X86-AVX2-LABEL: test_128_i32_x_4_8388352_mask_shl_7:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352] ; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpslld $7, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpslld $7, %xmm0, %xmm0
Show All 19 Lines
; X64-AVX2-NEXT: retq ; X64-AVX2-NEXT: retq
%t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352> %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
%t1 = shl <4 x i32> %t0, <i32 7, i32 7, i32 7, i32 7> %t1 = shl <4 x i32> %t0, <i32 7, i32 7, i32 7, i32 7>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @test_128_i32_x_4_8388352_mask_shl_8(<4 x i32> %a0) { define <4 x i32> @test_128_i32_x_4_8388352_mask_shl_8(<4 x i32> %a0) {
; X86-SSE2-LABEL: test_128_i32_x_4_8388352_mask_shl_8: ; X86-SSE2-LABEL: test_128_i32_x_4_8388352_mask_shl_8:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pslld $8, %xmm0 ; X86-SSE2-NEXT: pslld $8, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX1-LABEL: test_128_i32_x_4_8388352_mask_shl_8: ; X86-AVX1-LABEL: test_128_i32_x_4_8388352_mask_shl_8:
; X86-AVX1: # %bb.0: ; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vpslld $8, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpslld $8, %xmm0, %xmm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: test_128_i32_x_4_8388352_mask_shl_8: ; X86-AVX2-LABEL: test_128_i32_x_4_8388352_mask_shl_8:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352] ; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpslld $8, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpslld $8, %xmm0, %xmm0
Show All 19 Lines
; X64-AVX2-NEXT: retq ; X64-AVX2-NEXT: retq
%t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352> %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
%t1 = shl <4 x i32> %t0, <i32 8, i32 8, i32 8, i32 8> %t1 = shl <4 x i32> %t0, <i32 8, i32 8, i32 8, i32 8>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @test_128_i32_x_4_8388352_mask_shl_9(<4 x i32> %a0) { define <4 x i32> @test_128_i32_x_4_8388352_mask_shl_9(<4 x i32> %a0) {
; X86-SSE2-LABEL: test_128_i32_x_4_8388352_mask_shl_9: ; X86-SSE2-LABEL: test_128_i32_x_4_8388352_mask_shl_9:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pslld $9, %xmm0 ; X86-SSE2-NEXT: pslld $9, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX1-LABEL: test_128_i32_x_4_8388352_mask_shl_9: ; X86-AVX1-LABEL: test_128_i32_x_4_8388352_mask_shl_9:
; X86-AVX1: # %bb.0: ; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vpslld $9, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpslld $9, %xmm0, %xmm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: test_128_i32_x_4_8388352_mask_shl_9: ; X86-AVX2-LABEL: test_128_i32_x_4_8388352_mask_shl_9:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352] ; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpslld $9, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpslld $9, %xmm0, %xmm0
Show All 19 Lines
; X64-AVX2-NEXT: retq ; X64-AVX2-NEXT: retq
%t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352> %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
%t1 = shl <4 x i32> %t0, <i32 9, i32 9, i32 9, i32 9> %t1 = shl <4 x i32> %t0, <i32 9, i32 9, i32 9, i32 9>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @test_128_i32_x_4_8388352_mask_shl_10(<4 x i32> %a0) { define <4 x i32> @test_128_i32_x_4_8388352_mask_shl_10(<4 x i32> %a0) {
; X86-SSE2-LABEL: test_128_i32_x_4_8388352_mask_shl_10: ; X86-SSE2-LABEL: test_128_i32_x_4_8388352_mask_shl_10:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pslld $10, %xmm0 ; X86-SSE2-NEXT: pslld $10, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX1-LABEL: test_128_i32_x_4_8388352_mask_shl_10: ; X86-AVX1-LABEL: test_128_i32_x_4_8388352_mask_shl_10:
; X86-AVX1: # %bb.0: ; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vpslld $10, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpslld $10, %xmm0, %xmm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: test_128_i32_x_4_8388352_mask_shl_10: ; X86-AVX2-LABEL: test_128_i32_x_4_8388352_mask_shl_10:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352] ; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [8388352,8388352,8388352,8388352]
; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpslld $10, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpslld $10, %xmm0, %xmm0
Show All 20 Lines; X64-AVX2-NEXT: retq
%t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352> %t0 = and <4 x i32> %a0, <i32 8388352, i32 8388352, i32 8388352, i32 8388352>
%t1 = shl <4 x i32> %t0, <i32 10, i32 10, i32 10, i32 10> %t1 = shl <4 x i32> %t0, <i32 10, i32 10, i32 10, i32 10>
ret <4 x i32> %t1 ret <4 x i32> %t1
} }
define <4 x i32> @test_128_i32_x_4_4294836224_mask_shl_1(<4 x i32> %a0) { define <4 x i32> @test_128_i32_x_4_4294836224_mask_shl_1(<4 x i32> %a0) {
; X86-SSE2-LABEL: test_128_i32_x_4_4294836224_mask_shl_1: ; X86-SSE2-LABEL: test_128_i32_x_4_4294836224_mask_shl_1:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: paddd %xmm0, %xmm0 ; X86-SSE2-NEXT: paddd %xmm0, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX1-LABEL: test_128_i32_x_4_4294836224_mask_shl_1: ; X86-AVX1-LABEL: test_128_i32_x_4_4294836224_mask_shl_1:
; X86-AVX1: # %bb.0: ; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vpaddd %xmm0, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpaddd %xmm0, %xmm0, %xmm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: test_128_i32_x_4_4294836224_mask_shl_1: ; X86-AVX2-LABEL: test_128_i32_x_4_4294836224_mask_shl_1:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [4294836224,4294836224,4294836224,4294836224] ; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [4294836224,4294836224,4294836224,4294836224]
; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpaddd %xmm0, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpaddd %xmm0, %xmm0, %xmm0
Show All 26 Lines
; 128-bit vector; 64-bit elements = 2 elements ; 128-bit vector; 64-bit elements = 2 elements
;------------------------------------------------------------------------------; ;------------------------------------------------------------------------------;
; lshr ; lshr
define <2 x i64> @test_128_i64_x_2_2147483647_mask_lshr_1(<2 x i64> %a0) { define <2 x i64> @test_128_i64_x_2_2147483647_mask_lshr_1(<2 x i64> %a0) {
; X86-SSE2-LABEL: test_128_i64_x_2_2147483647_mask_lshr_1: ; X86-SSE2-LABEL: test_128_i64_x_2_2147483647_mask_lshr_1:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlq $1, %xmm0 ; X86-SSE2-NEXT: psrlq $1, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i64_x_2_2147483647_mask_lshr_1: ; X86-AVX-LABEL: test_128_i64_x_2_2147483647_mask_lshr_1:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlq $1, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlq $1, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i64_x_2_2147483647_mask_lshr_1: ; X64-SSE2-LABEL: test_128_i64_x_2_2147483647_mask_lshr_1:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlq $1, %xmm0 ; X64-SSE2-NEXT: psrlq $1, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i64_x_2_2147483647_mask_lshr_1: ; X64-AVX-LABEL: test_128_i64_x_2_2147483647_mask_lshr_1:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlq $1, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlq $1, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647> %t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647>
%t1 = lshr <2 x i64> %t0, <i64 1, i64 1> %t1 = lshr <2 x i64> %t0, <i64 1, i64 1>
ret <2 x i64> %t1 ret <2 x i64> %t1
} }
define <2 x i64> @test_128_i64_x_2_140737488289792_mask_lshr_15(<2 x i64> %a0) { define <2 x i64> @test_128_i64_x_2_140737488289792_mask_lshr_15(<2 x i64> %a0) {
; X86-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_15: ; X86-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_15:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlq $15, %xmm0 ; X86-SSE2-NEXT: psrlq $15, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_15: ; X86-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_15:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlq $15, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlq $15, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_15: ; X64-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_15:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlq $15, %xmm0 ; X64-SSE2-NEXT: psrlq $15, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_15: ; X64-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_15:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlq $15, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlq $15, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792> %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
%t1 = lshr <2 x i64> %t0, <i64 15, i64 15> %t1 = lshr <2 x i64> %t0, <i64 15, i64 15>
ret <2 x i64> %t1 ret <2 x i64> %t1
} }
define <2 x i64> @test_128_i64_x_2_140737488289792_mask_lshr_16(<2 x i64> %a0) { define <2 x i64> @test_128_i64_x_2_140737488289792_mask_lshr_16(<2 x i64> %a0) {
; X86-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_16: ; X86-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_16:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlq $16, %xmm0 ; X86-SSE2-NEXT: psrlq $16, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_16: ; X86-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_16:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlq $16, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlq $16, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_16: ; X64-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_16:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlq $16, %xmm0 ; X64-SSE2-NEXT: psrlq $16, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_16: ; X64-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_16:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlq $16, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlq $16, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792> %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
%t1 = lshr <2 x i64> %t0, <i64 16, i64 16> %t1 = lshr <2 x i64> %t0, <i64 16, i64 16>
ret <2 x i64> %t1 ret <2 x i64> %t1
} }
define <2 x i64> @test_128_i64_x_2_140737488289792_mask_lshr_17(<2 x i64> %a0) { define <2 x i64> @test_128_i64_x_2_140737488289792_mask_lshr_17(<2 x i64> %a0) {
; X86-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_17: ; X86-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_17:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlq $17, %xmm0 ; X86-SSE2-NEXT: psrlq $17, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_17: ; X86-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_17:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlq $17, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlq $17, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_17: ; X64-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_17:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlq $17, %xmm0 ; X64-SSE2-NEXT: psrlq $17, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_17: ; X64-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_17:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlq $17, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlq $17, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792> %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
%t1 = lshr <2 x i64> %t0, <i64 17, i64 17> %t1 = lshr <2 x i64> %t0, <i64 17, i64 17>
ret <2 x i64> %t1 ret <2 x i64> %t1
} }
define <2 x i64> @test_128_i64_x_2_140737488289792_mask_lshr_18(<2 x i64> %a0) { define <2 x i64> @test_128_i64_x_2_140737488289792_mask_lshr_18(<2 x i64> %a0) {
; X86-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_18: ; X86-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_18:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlq $18, %xmm0 ; X86-SSE2-NEXT: psrlq $18, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_18: ; X86-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_18:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlq $18, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlq $18, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_18: ; X64-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_18:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlq $18, %xmm0 ; X64-SSE2-NEXT: psrlq $18, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_18: ; X64-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_lshr_18:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlq $18, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlq $18, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792> %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
%t1 = lshr <2 x i64> %t0, <i64 18, i64 18> %t1 = lshr <2 x i64> %t0, <i64 18, i64 18>
ret <2 x i64> %t1 ret <2 x i64> %t1
} }
define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_lshr_1(<2 x i64> %a0) { define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_lshr_1(<2 x i64> %a0) {
; X86-SSE2-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_1: ; X86-SSE2-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_1:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlq $1, %xmm0 ; X86-SSE2-NEXT: psrlq $1, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_1: ; X86-AVX-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_1:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlq $1, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlq $1, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_1: ; X64-SSE2-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_1:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlq $1, %xmm0 ; X64-SSE2-NEXT: psrlq $1, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_1: ; X64-AVX-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_1:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlq $1, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlq $1, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024> %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>
%t1 = lshr <2 x i64> %t0, <i64 1, i64 1> %t1 = lshr <2 x i64> %t0, <i64 1, i64 1>
ret <2 x i64> %t1 ret <2 x i64> %t1
} }
define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_lshr_32(<2 x i64> %a0) { define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_lshr_32(<2 x i64> %a0) {
; X86-SSE2-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_32: ; X86-SSE2-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_32:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlq $32, %xmm0 ; X86-SSE2-NEXT: psrlq $32, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX1-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_32: ; X86-AVX1-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_32:
; X86-AVX1: # %bb.0: ; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vpsrlq $32, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpsrlq $32, %xmm0, %xmm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_32: ; X86-AVX2-LABEL: test_128_i64_x_2_18446744065119617024_mask_lshr_32:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [4294967294,4294967294,4294967294,4294967294] ; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [4294967294,4294967294,4294967294,4294967294]
; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpsrlq $32, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpsrlq $32, %xmm0, %xmm0
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines; X64-AVX-NEXT: retq
ret <2 x i64> %t1 ret <2 x i64> %t1
} }
; ashr ; ashr
define <2 x i64> @test_128_i64_x_2_2147483647_mask_ashr_1(<2 x i64> %a0) { define <2 x i64> @test_128_i64_x_2_2147483647_mask_ashr_1(<2 x i64> %a0) {
; X86-SSE2-LABEL: test_128_i64_x_2_2147483647_mask_ashr_1: ; X86-SSE2-LABEL: test_128_i64_x_2_2147483647_mask_ashr_1:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlq $1, %xmm0 ; X86-SSE2-NEXT: psrlq $1, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i64_x_2_2147483647_mask_ashr_1: ; X86-AVX-LABEL: test_128_i64_x_2_2147483647_mask_ashr_1:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlq $1, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlq $1, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i64_x_2_2147483647_mask_ashr_1: ; X64-SSE2-LABEL: test_128_i64_x_2_2147483647_mask_ashr_1:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlq $1, %xmm0 ; X64-SSE2-NEXT: psrlq $1, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i64_x_2_2147483647_mask_ashr_1: ; X64-AVX-LABEL: test_128_i64_x_2_2147483647_mask_ashr_1:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlq $1, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlq $1, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647> %t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647>
%t1 = ashr <2 x i64> %t0, <i64 1, i64 1> %t1 = ashr <2 x i64> %t0, <i64 1, i64 1>
ret <2 x i64> %t1 ret <2 x i64> %t1
} }
define <2 x i64> @test_128_i64_x_2_140737488289792_mask_ashr_15(<2 x i64> %a0) { define <2 x i64> @test_128_i64_x_2_140737488289792_mask_ashr_15(<2 x i64> %a0) {
; X86-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_15: ; X86-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_15:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlq $15, %xmm0 ; X86-SSE2-NEXT: psrlq $15, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_15: ; X86-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_15:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlq $15, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlq $15, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_15: ; X64-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_15:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlq $15, %xmm0 ; X64-SSE2-NEXT: psrlq $15, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_15: ; X64-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_15:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlq $15, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlq $15, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792> %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
%t1 = ashr <2 x i64> %t0, <i64 15, i64 15> %t1 = ashr <2 x i64> %t0, <i64 15, i64 15>
ret <2 x i64> %t1 ret <2 x i64> %t1
} }
define <2 x i64> @test_128_i64_x_2_140737488289792_mask_ashr_16(<2 x i64> %a0) { define <2 x i64> @test_128_i64_x_2_140737488289792_mask_ashr_16(<2 x i64> %a0) {
; X86-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_16: ; X86-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_16:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlq $16, %xmm0 ; X86-SSE2-NEXT: psrlq $16, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_16: ; X86-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_16:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlq $16, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlq $16, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_16: ; X64-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_16:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlq $16, %xmm0 ; X64-SSE2-NEXT: psrlq $16, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_16: ; X64-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_16:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlq $16, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlq $16, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792> %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
%t1 = ashr <2 x i64> %t0, <i64 16, i64 16> %t1 = ashr <2 x i64> %t0, <i64 16, i64 16>
ret <2 x i64> %t1 ret <2 x i64> %t1
} }
define <2 x i64> @test_128_i64_x_2_140737488289792_mask_ashr_17(<2 x i64> %a0) { define <2 x i64> @test_128_i64_x_2_140737488289792_mask_ashr_17(<2 x i64> %a0) {
; X86-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_17: ; X86-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_17:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlq $17, %xmm0 ; X86-SSE2-NEXT: psrlq $17, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_17: ; X86-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_17:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlq $17, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlq $17, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_17: ; X64-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_17:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlq $17, %xmm0 ; X64-SSE2-NEXT: psrlq $17, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_17: ; X64-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_17:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlq $17, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlq $17, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792> %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
%t1 = ashr <2 x i64> %t0, <i64 17, i64 17> %t1 = ashr <2 x i64> %t0, <i64 17, i64 17>
ret <2 x i64> %t1 ret <2 x i64> %t1
} }
define <2 x i64> @test_128_i64_x_2_140737488289792_mask_ashr_18(<2 x i64> %a0) { define <2 x i64> @test_128_i64_x_2_140737488289792_mask_ashr_18(<2 x i64> %a0) {
; X86-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_18: ; X86-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_18:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrlq $18, %xmm0 ; X86-SSE2-NEXT: psrlq $18, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_18: ; X86-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_18:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsrlq $18, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsrlq $18, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_18: ; X64-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_18:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psrlq $18, %xmm0 ; X64-SSE2-NEXT: psrlq $18, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_18: ; X64-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_ashr_18:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsrlq $18, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsrlq $18, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792> %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
%t1 = ashr <2 x i64> %t0, <i64 18, i64 18> %t1 = ashr <2 x i64> %t0, <i64 18, i64 18>
ret <2 x i64> %t1 ret <2 x i64> %t1
} }
define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_ashr_1(<2 x i64> %a0) { define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_ashr_1(<2 x i64> %a0) {
; X86-SSE2-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_1: ; X86-SSE2-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_1:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psrad $1, %xmm0 ; X86-SSE2-NEXT: psrad $1, %xmm0
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX1-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_1: ; X86-AVX1-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_1:
; X86-AVX1: # %bb.0: ; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vpsrad $1, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpsrad $1, %xmm0, %xmm0
; X86-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; X86-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X86-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7] ; X86-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5],xmm0[6,7]
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_1: ; X86-AVX2-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_1:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [4294967294,4294967294,4294967294,4294967294] ; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [4294967294,4294967294,4294967294,4294967294]
Show All 27 Lines
; X64-AVX2-NEXT: retq ; X64-AVX2-NEXT: retq
%t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024> %t0 = and <2 x i64> %a0, <i64 18446744065119617024, i64 18446744065119617024>
%t1 = ashr <2 x i64> %t0, <i64 1, i64 1> %t1 = ashr <2 x i64> %t0, <i64 1, i64 1>
ret <2 x i64> %t1 ret <2 x i64> %t1
} }
define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_ashr_32(<2 x i64> %a0) { define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_ashr_32(<2 x i64> %a0) {
; X86-SSE2-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_32: ; X86-SSE2-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_32:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3]
; X86-SSE2-NEXT: psrad $31, %xmm0 ; X86-SSE2-NEXT: psrad $31, %xmm0
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3] ; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]
; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1] ; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; X86-SSE2-NEXT: movdqa %xmm1, %xmm0 ; X86-SSE2-NEXT: movdqa %xmm1, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX1-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_32: ; X86-AVX1-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_32:
; X86-AVX1: # %bb.0: ; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vpsrad $31, %xmm0, %xmm1 ; X86-AVX1-NEXT: vpsrad $31, %xmm0, %xmm1
; X86-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; X86-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
; X86-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7] ; X86-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_32: ; X86-AVX2-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_32:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX2-NEXT: vpsrad $31, %xmm0, %xmm1 ; X86-AVX2-NEXT: vpsrad $31, %xmm0, %xmm1
; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3] ; X86-AVX2-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
; X86-AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3] ; X86-AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
; X86-AVX2-NEXT: retl ; X86-AVX2-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_32: ; X64-SSE2-LABEL: test_128_i64_x_2_18446744065119617024_mask_ashr_32:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
▲ Show 20 Lines • Show All 136 Lines • ▼ Show 20 Lines; X64-AVX2-NEXT: retq
ret <2 x i64> %t1 ret <2 x i64> %t1
} }
; shl ; shl
define <2 x i64> @test_128_i64_x_2_2147483647_mask_shl_1(<2 x i64> %a0) { define <2 x i64> @test_128_i64_x_2_2147483647_mask_shl_1(<2 x i64> %a0) {
; X86-SSE2-LABEL: test_128_i64_x_2_2147483647_mask_shl_1: ; X86-SSE2-LABEL: test_128_i64_x_2_2147483647_mask_shl_1:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: paddq %xmm0, %xmm0 ; X86-SSE2-NEXT: paddq %xmm0, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i64_x_2_2147483647_mask_shl_1: ; X86-AVX-LABEL: test_128_i64_x_2_2147483647_mask_shl_1:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpaddq %xmm0, %xmm0, %xmm0 ; X86-AVX-NEXT: vpaddq %xmm0, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i64_x_2_2147483647_mask_shl_1: ; X64-SSE2-LABEL: test_128_i64_x_2_2147483647_mask_shl_1:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: paddq %xmm0, %xmm0 ; X64-SSE2-NEXT: paddq %xmm0, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i64_x_2_2147483647_mask_shl_1: ; X64-AVX-LABEL: test_128_i64_x_2_2147483647_mask_shl_1:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpaddq %xmm0, %xmm0, %xmm0 ; X64-AVX-NEXT: vpaddq %xmm0, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647> %t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647>
%t1 = shl <2 x i64> %t0, <i64 1, i64 1> %t1 = shl <2 x i64> %t0, <i64 1, i64 1>
ret <2 x i64> %t1 ret <2 x i64> %t1
} }
define <2 x i64> @test_128_i64_x_2_2147483647_mask_shl_32(<2 x i64> %a0) { define <2 x i64> @test_128_i64_x_2_2147483647_mask_shl_32(<2 x i64> %a0) {
; X86-SSE2-LABEL: test_128_i64_x_2_2147483647_mask_shl_32: ; X86-SSE2-LABEL: test_128_i64_x_2_2147483647_mask_shl_32:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psllq $32, %xmm0 ; X86-SSE2-NEXT: psllq $32, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX1-LABEL: test_128_i64_x_2_2147483647_mask_shl_32: ; X86-AVX1-LABEL: test_128_i64_x_2_2147483647_mask_shl_32:
; X86-AVX1: # %bb.0: ; X86-AVX1: # %bb.0:
; X86-AVX1-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX1-NEXT: vpsllq $32, %xmm0, %xmm0 ; X86-AVX1-NEXT: vpsllq $32, %xmm0, %xmm0
; X86-AVX1-NEXT: retl ; X86-AVX1-NEXT: retl
; ;
; X86-AVX2-LABEL: test_128_i64_x_2_2147483647_mask_shl_32: ; X86-AVX2-LABEL: test_128_i64_x_2_2147483647_mask_shl_32:
; X86-AVX2: # %bb.0: ; X86-AVX2: # %bb.0:
; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [2147483647,2147483647,2147483647,2147483647] ; X86-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [2147483647,2147483647,2147483647,2147483647]
; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-AVX2-NEXT: vpsllq $32, %xmm0, %xmm0 ; X86-AVX2-NEXT: vpsllq $32, %xmm0, %xmm0
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines; X64-AVX-NEXT: retq
%t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647> %t0 = and <2 x i64> %a0, <i64 2147483647, i64 2147483647>
%t1 = shl <2 x i64> %t0, <i64 34, i64 34> %t1 = shl <2 x i64> %t0, <i64 34, i64 34>
ret <2 x i64> %t1 ret <2 x i64> %t1
} }
define <2 x i64> @test_128_i64_x_2_140737488289792_mask_shl_15(<2 x i64> %a0) { define <2 x i64> @test_128_i64_x_2_140737488289792_mask_shl_15(<2 x i64> %a0) {
; X86-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_shl_15: ; X86-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_shl_15:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psllq $15, %xmm0 ; X86-SSE2-NEXT: psllq $15, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_shl_15: ; X86-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_shl_15:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsllq $15, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsllq $15, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_shl_15: ; X64-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_shl_15:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psllq $15, %xmm0 ; X64-SSE2-NEXT: psllq $15, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_shl_15: ; X64-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_shl_15:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsllq $15, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsllq $15, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792> %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
%t1 = shl <2 x i64> %t0, <i64 15, i64 15> %t1 = shl <2 x i64> %t0, <i64 15, i64 15>
ret <2 x i64> %t1 ret <2 x i64> %t1
} }
define <2 x i64> @test_128_i64_x_2_140737488289792_mask_shl_16(<2 x i64> %a0) { define <2 x i64> @test_128_i64_x_2_140737488289792_mask_shl_16(<2 x i64> %a0) {
; X86-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_shl_16: ; X86-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_shl_16:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psllq $16, %xmm0 ; X86-SSE2-NEXT: psllq $16, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_shl_16: ; X86-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_shl_16:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsllq $16, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsllq $16, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_shl_16: ; X64-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_shl_16:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psllq $16, %xmm0 ; X64-SSE2-NEXT: psllq $16, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_shl_16: ; X64-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_shl_16:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsllq $16, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsllq $16, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792> %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
%t1 = shl <2 x i64> %t0, <i64 16, i64 16> %t1 = shl <2 x i64> %t0, <i64 16, i64 16>
ret <2 x i64> %t1 ret <2 x i64> %t1
} }
define <2 x i64> @test_128_i64_x_2_140737488289792_mask_shl_17(<2 x i64> %a0) { define <2 x i64> @test_128_i64_x_2_140737488289792_mask_shl_17(<2 x i64> %a0) {
; X86-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_shl_17: ; X86-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_shl_17:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psllq $17, %xmm0 ; X86-SSE2-NEXT: psllq $17, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_shl_17: ; X86-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_shl_17:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsllq $17, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsllq $17, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_shl_17: ; X64-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_shl_17:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psllq $17, %xmm0 ; X64-SSE2-NEXT: psllq $17, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_shl_17: ; X64-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_shl_17:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsllq $17, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsllq $17, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792> %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
%t1 = shl <2 x i64> %t0, <i64 17, i64 17> %t1 = shl <2 x i64> %t0, <i64 17, i64 17>
ret <2 x i64> %t1 ret <2 x i64> %t1
} }
define <2 x i64> @test_128_i64_x_2_140737488289792_mask_shl_18(<2 x i64> %a0) { define <2 x i64> @test_128_i64_x_2_140737488289792_mask_shl_18(<2 x i64> %a0) {
; X86-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_shl_18: ; X86-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_shl_18:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: psllq $18, %xmm0 ; X86-SSE2-NEXT: psllq $18, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_shl_18: ; X86-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_shl_18:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpsllq $18, %xmm0, %xmm0 ; X86-AVX-NEXT: vpsllq $18, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_shl_18: ; X64-SSE2-LABEL: test_128_i64_x_2_140737488289792_mask_shl_18:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: psllq $18, %xmm0 ; X64-SSE2-NEXT: psllq $18, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
; ;
; X64-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_shl_18: ; X64-AVX-LABEL: test_128_i64_x_2_140737488289792_mask_shl_18:
; X64-AVX: # %bb.0: ; X64-AVX: # %bb.0:
; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 ; X64-AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; X64-AVX-NEXT: vpsllq $18, %xmm0, %xmm0 ; X64-AVX-NEXT: vpsllq $18, %xmm0, %xmm0
; X64-AVX-NEXT: retq ; X64-AVX-NEXT: retq
%t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792> %t0 = and <2 x i64> %a0, <i64 140737488289792, i64 140737488289792>
%t1 = shl <2 x i64> %t0, <i64 18, i64 18> %t1 = shl <2 x i64> %t0, <i64 18, i64 18>
ret <2 x i64> %t1 ret <2 x i64> %t1
} }
define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_shl_1(<2 x i64> %a0) { define <2 x i64> @test_128_i64_x_2_18446744065119617024_mask_shl_1(<2 x i64> %a0) {
; X86-SSE2-LABEL: test_128_i64_x_2_18446744065119617024_mask_shl_1: ; X86-SSE2-LABEL: test_128_i64_x_2_18446744065119617024_mask_shl_1:
; X86-SSE2: # %bb.0: ; X86-SSE2: # %bb.0:
; X86-SSE2-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-SSE2-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-SSE2-NEXT: paddq %xmm0, %xmm0 ; X86-SSE2-NEXT: paddq %xmm0, %xmm0
; X86-SSE2-NEXT: retl ; X86-SSE2-NEXT: retl
; ;
; X86-AVX-LABEL: test_128_i64_x_2_18446744065119617024_mask_shl_1: ; X86-AVX-LABEL: test_128_i64_x_2_18446744065119617024_mask_shl_1:
; X86-AVX: # %bb.0: ; X86-AVX: # %bb.0:
; X86-AVX-NEXT: vpand {{\.LCPI.*}}, %xmm0, %xmm0 ; X86-AVX-NEXT: vpand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0
; X86-AVX-NEXT: vpaddq %xmm0, %xmm0, %xmm0 ; X86-AVX-NEXT: vpaddq %xmm0, %xmm0, %xmm0
; X86-AVX-NEXT: retl ; X86-AVX-NEXT: retl
; ;
; X64-SSE2-LABEL: test_128_i64_x_2_18446744065119617024_mask_shl_1: ; X64-SSE2-LABEL: test_128_i64_x_2_18446744065119617024_mask_shl_1:
; X64-SSE2: # %bb.0: ; X64-SSE2: # %bb.0:
; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
; X64-SSE2-NEXT: paddq %xmm0, %xmm0 ; X64-SSE2-NEXT: paddq %xmm0, %xmm0
; X64-SSE2-NEXT: retq ; X64-SSE2-NEXT: retq
Show All 10 Lines

llvm/test/CodeGen/X86/vshift-6.ll

Show All 36 Lines
; X86-NEXT: pandn %xmm0, %xmm1 ; X86-NEXT: pandn %xmm0, %xmm1
; X86-NEXT: por %xmm2, %xmm1 ; X86-NEXT: por %xmm2, %xmm1
; X86-NEXT: pcmpeqd %xmm2, %xmm2 ; X86-NEXT: pcmpeqd %xmm2, %xmm2
; X86-NEXT: psllw $5, %xmm1 ; X86-NEXT: psllw $5, %xmm1
; X86-NEXT: pxor %xmm3, %xmm3 ; X86-NEXT: pxor %xmm3, %xmm3
; X86-NEXT: pxor %xmm0, %xmm0 ; X86-NEXT: pxor %xmm0, %xmm0
; X86-NEXT: pcmpgtb %xmm1, %xmm0 ; X86-NEXT: pcmpgtb %xmm1, %xmm0
; X86-NEXT: pxor %xmm0, %xmm2 ; X86-NEXT: pxor %xmm0, %xmm2
; X86-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: por %xmm2, %xmm0 ; X86-NEXT: por %xmm2, %xmm0
; X86-NEXT: paddb %xmm1, %xmm1 ; X86-NEXT: paddb %xmm1, %xmm1
; X86-NEXT: pxor %xmm2, %xmm2 ; X86-NEXT: pxor %xmm2, %xmm2
; X86-NEXT: pcmpgtb %xmm1, %xmm2 ; X86-NEXT: pcmpgtb %xmm1, %xmm2
; X86-NEXT: movdqa %xmm2, %xmm4 ; X86-NEXT: movdqa %xmm2, %xmm4
; X86-NEXT: pandn %xmm0, %xmm4 ; X86-NEXT: pandn %xmm0, %xmm4
; X86-NEXT: psllw $2, %xmm0 ; X86-NEXT: psllw $2, %xmm0
; X86-NEXT: pand %xmm2, %xmm0 ; X86-NEXT: pand %xmm2, %xmm0
; X86-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: por %xmm4, %xmm0 ; X86-NEXT: por %xmm4, %xmm0
; X86-NEXT: paddb %xmm1, %xmm1 ; X86-NEXT: paddb %xmm1, %xmm1
; X86-NEXT: pcmpgtb %xmm1, %xmm3 ; X86-NEXT: pcmpgtb %xmm1, %xmm3
; X86-NEXT: movdqa %xmm3, %xmm1 ; X86-NEXT: movdqa %xmm3, %xmm1
; X86-NEXT: pandn %xmm0, %xmm1 ; X86-NEXT: pandn %xmm0, %xmm1
; X86-NEXT: paddb %xmm0, %xmm0 ; X86-NEXT: paddb %xmm0, %xmm0
; X86-NEXT: pand %xmm3, %xmm0 ; X86-NEXT: pand %xmm3, %xmm0
; X86-NEXT: por %xmm1, %xmm0 ; X86-NEXT: por %xmm1, %xmm0
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llvm/test/CodeGen/X86/widen_load-2.ll

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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movb $-98, 2(%edx) ; X86-NEXT: movb $-98, 2(%edx)
; X86-NEXT: movw $-24930, (%edx) # imm = 0x9E9E ; X86-NEXT: movw $-24930, (%edx) # imm = 0x9E9E
; X86-NEXT: movb $1, 2(%ecx) ; X86-NEXT: movb $1, 2(%ecx)
; X86-NEXT: movw $257, (%ecx) # imm = 0x101 ; X86-NEXT: movw $257, (%ecx) # imm = 0x101
; X86-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero ; X86-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-NEXT: psrlw $1, %xmm0 ; X86-NEXT: psrlw $1, %xmm0
; X86-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: pextrb $2, %xmm0, 2(%eax) ; X86-NEXT: pextrb $2, %xmm0, 2(%eax)
; X86-NEXT: pextrw $0, %xmm0, (%eax) ; X86-NEXT: pextrw $0, %xmm0, (%eax)
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
; ;
; X64-LABEL: rot: ; X64-LABEL: rot:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: movq %rdi, %rax ; X64-NEXT: movq %rdi, %rax
; X64-NEXT: movb $-98, 2(%rsi) ; X64-NEXT: movb $-98, 2(%rsi)
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llvm/test/CodeGen/X86/x86-shifts.ll

Show First 20 Lines • Show All 125 Lines • ▼ Show 20 Lines
; non-splat test ; non-splat test
define <8 x i16> @sll8_nosplat(<8 x i16> %A) nounwind { define <8 x i16> @sll8_nosplat(<8 x i16> %A) nounwind {
; X86-LABEL: sll8_nosplat: ; X86-LABEL: sll8_nosplat:
; X86: # %bb.0: # %entry ; X86: # %bb.0: # %entry
; X86-NEXT: movdqa {{.*#+}} xmm1 = [2,4,8,64,4,4,4,4] ; X86-NEXT: movdqa {{.*#+}} xmm1 = [2,4,8,64,4,4,4,4]
; X86-NEXT: pmullw %xmm0, %xmm1 ; X86-NEXT: pmullw %xmm0, %xmm1
; X86-NEXT: pmullw {{\.LCPI.*}}, %xmm0 ; X86-NEXT: pmullw {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: pxor %xmm1, %xmm0 ; X86-NEXT: pxor %xmm1, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: sll8_nosplat: ; X64-LABEL: sll8_nosplat:
; X64: # %bb.0: # %entry ; X64: # %bb.0: # %entry
; X64-NEXT: movdqa {{.*#+}} xmm1 = [2,4,8,64,4,4,4,4] ; X64-NEXT: movdqa {{.*#+}} xmm1 = [2,4,8,64,4,4,4,4]
; X64-NEXT: pmullw %xmm0, %xmm1 ; X64-NEXT: pmullw %xmm0, %xmm1
; X64-NEXT: pmullw {{.*}}(%rip), %xmm0 ; X64-NEXT: pmullw {{.*}}(%rip), %xmm0
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Linesentry:
%K = xor <2 x i32> %B, %C %K = xor <2 x i32> %B, %C
ret <2 x i32> %K ret <2 x i32> %K
} }
define <16 x i8> @shl9(<16 x i8> %A) nounwind { define <16 x i8> @shl9(<16 x i8> %A) nounwind {
; X86-LABEL: shl9: ; X86-LABEL: shl9:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: psllw $3, %xmm0 ; X86-NEXT: psllw $3, %xmm0
; X86-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: shl9: ; X64-LABEL: shl9:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: psllw $3, %xmm0 ; X64-NEXT: psllw $3, %xmm0
; X64-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-NEXT: pand {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%B = shl <16 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> %B = shl <16 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <16 x i8> %B ret <16 x i8> %B
} }
define <16 x i8> @shr9(<16 x i8> %A) nounwind { define <16 x i8> @shr9(<16 x i8> %A) nounwind {
; X86-LABEL: shr9: ; X86-LABEL: shr9:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: psrlw $3, %xmm0 ; X86-NEXT: psrlw $3, %xmm0
; X86-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: shr9: ; X64-LABEL: shr9:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: psrlw $3, %xmm0 ; X64-NEXT: psrlw $3, %xmm0
; X64-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-NEXT: pand {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%B = lshr <16 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> %B = lshr <16 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
Show All 10 Lines; CHECK-NEXT: ret{{[l|q]}}
%B = ashr <16 x i8> %A, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7> %B = ashr <16 x i8> %A, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
ret <16 x i8> %B ret <16 x i8> %B
} }
define <16 x i8> @sra_v16i8(<16 x i8> %A) nounwind { define <16 x i8> @sra_v16i8(<16 x i8> %A) nounwind {
; X86-LABEL: sra_v16i8: ; X86-LABEL: sra_v16i8:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: psrlw $3, %xmm0 ; X86-NEXT: psrlw $3, %xmm0
; X86-NEXT: pand {{\.LCPI.*}}, %xmm0 ; X86-NEXT: pand {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: movdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16] ; X86-NEXT: movdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
; X86-NEXT: pxor %xmm1, %xmm0 ; X86-NEXT: pxor %xmm1, %xmm0
; X86-NEXT: psubb %xmm1, %xmm0 ; X86-NEXT: psubb %xmm1, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: sra_v16i8: ; X64-LABEL: sra_v16i8:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: psrlw $3, %xmm0 ; X64-NEXT: psrlw $3, %xmm0
; X64-NEXT: pand {{.*}}(%rip), %xmm0 ; X64-NEXT: pand {{.*}}(%rip), %xmm0
; X64-NEXT: movdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16] ; X64-NEXT: movdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
; X64-NEXT: pxor %xmm1, %xmm0 ; X64-NEXT: pxor %xmm1, %xmm0
; X64-NEXT: psubb %xmm1, %xmm0 ; X64-NEXT: psubb %xmm1, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%B = ashr <16 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3> %B = ashr <16 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <16 x i8> %B ret <16 x i8> %B
} }

llvm/test/CodeGen/X86/xop-mask-comments.ll

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret{{[l|q]}}
%1 = tail call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> <i8 31, i8 14, i8 29, i8 12, i8 27, i8 10, i8 25, i8 8, i8 23, i8 6, i8 21, i8 4, i8 147, i8 130, i8 145, i8 128>) %1 = tail call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %a1, <16 x i8> <i8 31, i8 14, i8 29, i8 12, i8 27, i8 10, i8 25, i8 8, i8 23, i8 6, i8 21, i8 4, i8 147, i8 130, i8 145, i8 128>)
ret <16 x i8> %1 ret <16 x i8> %1
} }
; we can't decode vpperm's other permute ops ; we can't decode vpperm's other permute ops
define <16 x i8> @vpperm_shuffle_general(<16 x i8> %a0, <16 x i8> %a1) { define <16 x i8> @vpperm_shuffle_general(<16 x i8> %a0, <16 x i8> %a1) {
; X86-LABEL: vpperm_shuffle_general: ; X86-LABEL: vpperm_shuffle_general:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: vpperm {{\.LCPI.*}}, %xmm0, %xmm0, %xmm0 ; X86-NEXT: vpperm {{\.LCPI[0-9]+_[0-9]+}}, %xmm0, %xmm0, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LABEL: vpperm_shuffle_general: ; X64-LABEL: vpperm_shuffle_general:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: vpperm {{.*}}(%rip), %xmm0, %xmm0, %xmm0 ; X64-NEXT: vpperm {{.*}}(%rip), %xmm0, %xmm0, %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%1 = tail call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %a0, <16 x i8> <i8 31, i8 14, i8 29, i8 12, i8 27, i8 10, i8 25, i8 8, i8 23, i8 6, i8 21, i8 4, i8 179, i8 162, i8 177, i8 160>) %1 = tail call <16 x i8> @llvm.x86.xop.vpperm(<16 x i8> %a0, <16 x i8> %a0, <16 x i8> <i8 31, i8 14, i8 29, i8 12, i8 27, i8 10, i8 25, i8 8, i8 23, i8 6, i8 21, i8 4, i8 179, i8 162, i8 177, i8 160>)
ret <16 x i8> %1 ret <16 x i8> %1
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llvm/test/CodeGen/X86/xor.ll

Show First 20 Lines • Show All 367 Lines • ▼ Show 20 Lines; X64-WIN-NEXT: retq
%2 = xor i32 %1, 4096 %2 = xor i32 %1, 4096
ret i32 %2 ret i32 %2
} }
; PR15948 ; PR15948
define <4 x i32> @test10(<4 x i32> %a) nounwind { define <4 x i32> @test10(<4 x i32> %a) nounwind {
; X86-LABEL: test10: ; X86-LABEL: test10:
; X86: # %bb.0: ; X86: # %bb.0:
; X86-NEXT: andnps {{\.LCPI.*}}, %xmm0 ; X86-NEXT: andnps {{\.LCPI[0-9]+_[0-9]+}}, %xmm0
; X86-NEXT: retl ; X86-NEXT: retl
; ;
; X64-LIN-LABEL: test10: ; X64-LIN-LABEL: test10:
; X64-LIN: # %bb.0: ; X64-LIN: # %bb.0:
; X64-LIN-NEXT: andnps {{.*}}(%rip), %xmm0 ; X64-LIN-NEXT: andnps {{.*}}(%rip), %xmm0
; X64-LIN-NEXT: retq ; X64-LIN-NEXT: retq
; ;
; X64-WIN-LABEL: test10: ; X64-WIN-LABEL: test10:
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llvm/utils/UpdateTestChecks/asm.py

Show First 20 Lines • Show All 191 Lines • ▼ Show 20 Linesdef scrub_asm_x86(asm, args):
asm = SCRUB_X86_SPILL_RELOAD_RE.sub(r'{{[-0-9]+}}(%\1{{[sb]}}p)\2', asm) asm = SCRUB_X86_SPILL_RELOAD_RE.sub(r'{{[-0-9]+}}(%\1{{[sb]}}p)\2', asm)
if getattr(args, 'x86_scrub_sp', True): if getattr(args, 'x86_scrub_sp', True):
# Generically match the stack offset of a memory operand. # Generically match the stack offset of a memory operand.
asm = SCRUB_X86_SP_RE.sub(r'{{[0-9]+}}(%\1)', asm) asm = SCRUB_X86_SP_RE.sub(r'{{[0-9]+}}(%\1)', asm)
if getattr(args, 'x86_scrub_rip', False): if getattr(args, 'x86_scrub_rip', False):
# Generically match a RIP-relative memory operand. # Generically match a RIP-relative memory operand.
asm = SCRUB_X86_RIP_RE.sub(r'{{.*}}(%rip)', asm) asm = SCRUB_X86_RIP_RE.sub(r'{{.*}}(%rip)', asm)
# Generically match a LCP symbol. # Generically match a LCP symbol.
asm = SCRUB_X86_LCP_RE.sub(r'{{\.LCPI.*}}', asm) asm = SCRUB_X86_LCP_RE.sub(r'{{\.LCPI[0-9]+_[0-9]+}}', asm)
if getattr(args, 'extra_scrub', False): if getattr(args, 'extra_scrub', False):
# Avoid generating different checks for 32- and 64-bit because of 'retl' vs 'retq'. # Avoid generating different checks for 32- and 64-bit because of 'retl' vs 'retq'.
asm = SCRUB_X86_RET_RE.sub(r'ret{{[l|q]}}', asm) asm = SCRUB_X86_RET_RE.sub(r'ret{{[l|q]}}', asm)
# Strip kill operands inserted into the asm. # Strip kill operands inserted into the asm.
asm = common.SCRUB_KILL_COMMENT_RE.sub('', asm) asm = common.SCRUB_KILL_COMMENT_RE.sub('', asm)
# Strip trailing whitespace. # Strip trailing whitespace.
asm = common.SCRUB_TRAILING_WHITESPACE_RE.sub(r'', asm) asm = common.SCRUB_TRAILING_WHITESPACE_RE.sub(r'', asm)
return asm return asm
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