[WebAssembly] Finalize SIMD names and opcodes

[tlively]

Summary

Updates the names (e.g. widen => extend, saturate => sat) and opcodes of all
SIMD instructions to match the finalized SIMD spec. Deliberately does not change
the public interface in wasm_simd128.h yet; that will require more care.

Depends on D98466.

[aheejin]

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

1243

If they are finalized, can we delete these "prototype" comments here and elsewhere? (not necessarily in this CL)

[tlively]

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

1243

Yes, this definitely makes sense. I think I will leave it for future patches that also replace the intrinsics with proper patterns where applicable, though.

clang/include/clang/Basic/BuiltinsWebAssembly.def

 
 TARGET_BUILTIN(__builtin_wasm_replace_lane_i8x16, "V16ScV16ScIii", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_replace_lane_i16x8, "V8sV8sIii", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_replace_lane_i32x4, "V4iV4iIii", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_replace_lane_i64x2, "V2LLiV2LLiIiLLi", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_replace_lane_f32x4, "V4fV4fIif", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_replace_lane_f64x2, "V2dV2dIid", "nc", "simd128")
 
-TARGET_BUILTIN(__builtin_wasm_add_saturate_s_i8x16, "V16ScV16ScV16Sc", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_add_saturate_u_i8x16, "V16UcV16UcV16Uc", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_add_saturate_s_i16x8, "V8sV8sV8s", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_add_saturate_u_i16x8, "V8UsV8UsV8Us", "nc", "simd128")
-
-TARGET_BUILTIN(__builtin_wasm_sub_saturate_s_i8x16, "V16ScV16ScV16Sc", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_sub_saturate_u_i8x16, "V16UcV16UcV16Uc", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_sub_saturate_s_i16x8, "V8sV8sV8s", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_sub_saturate_u_i16x8, "V8UsV8UsV8Us", "nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_add_sat_s_i8x16, "V16ScV16ScV16Sc", "nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_add_sat_u_i8x16, "V16UcV16UcV16Uc", "nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_add_sat_s_i16x8, "V8sV8sV8s", "nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_add_sat_u_i16x8, "V8UsV8UsV8Us", "nc", "simd128")
+
+TARGET_BUILTIN(__builtin_wasm_sub_sat_s_i8x16, "V16ScV16ScV16Sc", "nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_sub_sat_u_i8x16, "V16UcV16UcV16Uc", "nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_sub_sat_s_i16x8, "V8sV8sV8s", "nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_sub_sat_u_i16x8, "V8UsV8UsV8Us", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_abs_i8x16, "V16ScV16Sc", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_abs_i16x8, "V8sV8s", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_abs_i32x4, "V4iV4i", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_min_s_i8x16, "V16ScV16ScV16Sc", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_min_u_i8x16, "V16UcV16UcV16Uc", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_max_s_i8x16, "V16ScV16ScV16Sc", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_max_u_i8x16, "V16UcV16UcV16Uc", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_min_s_i16x8, "V8sV8sV8s", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_min_u_i16x8, "V8UsV8UsV8Us", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_max_s_i16x8, "V8sV8sV8s", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_max_u_i16x8, "V8UsV8UsV8Us", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_min_s_i32x4, "V4iV4iV4i", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_min_u_i32x4, "V4UiV4UiV4Ui", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_max_s_i32x4, "V4iV4iV4i", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_max_u_i32x4, "V4UiV4UiV4Ui", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_avgr_u_i8x16, "V16UcV16UcV16Uc", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_avgr_u_i16x8, "V8UsV8UsV8Us", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_popcnt_i8x16, "V16ScV16Sc", "nc", "simd128")
 
-TARGET_BUILTIN(__builtin_wasm_q15mulr_saturate_s_i16x8, "V8sV8sV8s", "nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_q15mulr_sat_s_i16x8, "V8sV8sV8s", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_extmul_low_i8x16_s_i16x8, "V8sV16ScV16Sc", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_extmul_high_i8x16_s_i16x8, "V8sV16ScV16Sc", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_extmul_low_i8x16_u_i16x8, "V8UsV16UcV16Uc", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_extmul_high_i8x16_u_i16x8, "V8UsV16UcV16Uc", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_extmul_low_i16x8_s_i32x4, "V4iV8sV8s", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_extmul_high_i16x8_s_i32x4, "V4iV8sV8s", "nc", "simd128")

 TARGET_BUILTIN(__builtin_wasm_trunc_saturate_s_i32x4_f32x4, "V4iV4f", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_trunc_saturate_u_i32x4_f32x4, "V4iV4f", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_narrow_s_i8x16_i16x8, "V16ScV8sV8s", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_narrow_u_i8x16_i16x8, "V16UcV8UsV8Us", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_narrow_s_i16x8_i32x4, "V8sV4iV4i", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_narrow_u_i16x8_i32x4, "V8UsV4UiV4Ui", "nc", "simd128")
 
-TARGET_BUILTIN(__builtin_wasm_widen_low_s_i32x4_i64x2, "V2LLiV4i", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_widen_high_s_i32x4_i64x2, "V2LLiV4i", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_widen_low_u_i32x4_i64x2, "V2LLUiV4Ui", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_widen_high_u_i32x4_i64x2, "V2LLUiV4Ui", "nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_extend_low_s_i32x4_i64x2, "V2LLiV4i", "nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_extend_high_s_i32x4_i64x2, "V2LLiV4i", "nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_extend_low_u_i32x4_i64x2, "V2LLUiV4Ui", "nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_extend_high_u_i32x4_i64x2, "V2LLUiV4Ui", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_convert_low_s_i32x4_f64x2, "V2dV4i", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_convert_low_u_i32x4_f64x2, "V2dV4Ui", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_trunc_saturate_zero_s_f64x2_i32x4, "V4iV2d", "nc", "simd128")
-TARGET_BUILTIN(__builtin_wasm_trunc_saturate_zero_u_f64x2_i32x4, "V4UiV2d", "nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_trunc_sat_zero_s_f64x2_i32x4, "V4iV2d", "nc", "simd128")
+TARGET_BUILTIN(__builtin_wasm_trunc_sat_zero_u_f64x2_i32x4, "V4UiV2d", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_demote_zero_f64x2_f32x4, "V4fV2d", "nc", "simd128")
 TARGET_BUILTIN(__builtin_wasm_promote_low_f32x4_f64x2, "V2dV4f", "nc", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_load32_zero, "V4ii*", "n", "simd128")
 TARGET_BUILTIN(__builtin_wasm_load64_zero, "V2LLiLLi*", "n", "simd128")
 
 TARGET_BUILTIN(__builtin_wasm_load8_lane, "V16ScSc*V16ScIi", "n", "simd128")
 TARGET_BUILTIN(__builtin_wasm_load16_lane, "V8ss*V8sIi", "n", "simd128")

clang/lib/CodeGen/CGBuiltin.cpp

case WebAssembly::BI__builtin_wasm_replace_lane_f64x2: {
     case WebAssembly::BI__builtin_wasm_replace_lane_i64x2:
     case WebAssembly::BI__builtin_wasm_replace_lane_f32x4:
     case WebAssembly::BI__builtin_wasm_replace_lane_f64x2:
       return Builder.CreateInsertElement(Vec, Val, Lane);
     default:
       llvm_unreachable("unexpected builtin ID");
     }
   }
-  case WebAssembly::BI__builtin_wasm_add_saturate_s_i8x16:
-  case WebAssembly::BI__builtin_wasm_add_saturate_u_i8x16:
-  case WebAssembly::BI__builtin_wasm_add_saturate_s_i16x8:
-  case WebAssembly::BI__builtin_wasm_add_saturate_u_i16x8:
-  case WebAssembly::BI__builtin_wasm_sub_saturate_s_i8x16:
-  case WebAssembly::BI__builtin_wasm_sub_saturate_u_i8x16:
-  case WebAssembly::BI__builtin_wasm_sub_saturate_s_i16x8:
-  case WebAssembly::BI__builtin_wasm_sub_saturate_u_i16x8: {
+  case WebAssembly::BI__builtin_wasm_add_sat_s_i8x16:
+  case WebAssembly::BI__builtin_wasm_add_sat_u_i8x16:
+  case WebAssembly::BI__builtin_wasm_add_sat_s_i16x8:
+  case WebAssembly::BI__builtin_wasm_add_sat_u_i16x8:
+  case WebAssembly::BI__builtin_wasm_sub_sat_s_i8x16:
+  case WebAssembly::BI__builtin_wasm_sub_sat_u_i8x16:
+  case WebAssembly::BI__builtin_wasm_sub_sat_s_i16x8:
+  case WebAssembly::BI__builtin_wasm_sub_sat_u_i16x8: {
     unsigned IntNo;
     switch (BuiltinID) {
-    case WebAssembly::BI__builtin_wasm_add_saturate_s_i8x16:
-    case WebAssembly::BI__builtin_wasm_add_saturate_s_i16x8:
+    case WebAssembly::BI__builtin_wasm_add_sat_s_i8x16:
+    case WebAssembly::BI__builtin_wasm_add_sat_s_i16x8:
       IntNo = Intrinsic::sadd_sat;
       break;
-    case WebAssembly::BI__builtin_wasm_add_saturate_u_i8x16:
-    case WebAssembly::BI__builtin_wasm_add_saturate_u_i16x8:
+    case WebAssembly::BI__builtin_wasm_add_sat_u_i8x16:
+    case WebAssembly::BI__builtin_wasm_add_sat_u_i16x8:
       IntNo = Intrinsic::uadd_sat;
       break;
-    case WebAssembly::BI__builtin_wasm_sub_saturate_s_i8x16:
-    case WebAssembly::BI__builtin_wasm_sub_saturate_s_i16x8:
-      IntNo = Intrinsic::wasm_sub_saturate_signed;
-      break;
-    case WebAssembly::BI__builtin_wasm_sub_saturate_u_i8x16:
-    case WebAssembly::BI__builtin_wasm_sub_saturate_u_i16x8:
-      IntNo = Intrinsic::wasm_sub_saturate_unsigned;
+    case WebAssembly::BI__builtin_wasm_sub_sat_s_i8x16:
+    case WebAssembly::BI__builtin_wasm_sub_sat_s_i16x8:
+      IntNo = Intrinsic::wasm_sub_sat_signed;
+      break;
+    case WebAssembly::BI__builtin_wasm_sub_sat_u_i8x16:
+    case WebAssembly::BI__builtin_wasm_sub_sat_u_i16x8:
+      IntNo = Intrinsic::wasm_sub_sat_unsigned;
       break;
     default:
       llvm_unreachable("unexpected builtin ID");
     }
     Value *LHS = EmitScalarExpr(E->getArg(0));
     Value *RHS = EmitScalarExpr(E->getArg(1));
     Function *Callee = CGM.getIntrinsic(IntNo, ConvertType(E->getType()));
     return Builder.CreateCall(Callee, {LHS, RHS});
Value *CodeGenFunction::EmitWebAssemblyBuiltinExpr(unsigned BuiltinID,
   case WebAssembly::BI__builtin_wasm_avgr_u_i8x16:
   case WebAssembly::BI__builtin_wasm_avgr_u_i16x8: {
     Value *LHS = EmitScalarExpr(E->getArg(0));
     Value *RHS = EmitScalarExpr(E->getArg(1));
     Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_avgr_unsigned,
                                         ConvertType(E->getType()));
     return Builder.CreateCall(Callee, {LHS, RHS});
   }
-  case WebAssembly::BI__builtin_wasm_q15mulr_saturate_s_i16x8: {
+  case WebAssembly::BI__builtin_wasm_q15mulr_sat_s_i16x8: {
     Value *LHS = EmitScalarExpr(E->getArg(0));
     Value *RHS = EmitScalarExpr(E->getArg(1));
-    Function *Callee =
-        CGM.getIntrinsic(Intrinsic::wasm_q15mulr_saturate_signed);
+    Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_q15mulr_sat_signed);
     return Builder.CreateCall(Callee, {LHS, RHS});
   }
   case WebAssembly::BI__builtin_wasm_extmul_low_i8x16_s_i16x8:
   case WebAssembly::BI__builtin_wasm_extmul_high_i8x16_s_i16x8:
   case WebAssembly::BI__builtin_wasm_extmul_low_i8x16_u_i16x8:
   case WebAssembly::BI__builtin_wasm_extmul_high_i8x16_u_i16x8:
   case WebAssembly::BI__builtin_wasm_extmul_low_i16x8_s_i32x4:
   case WebAssembly::BI__builtin_wasm_extmul_high_i16x8_s_i32x4:
case WebAssembly::BI__builtin_wasm_narrow_u_i16x8_i32x4:
       break;
     default:
       llvm_unreachable("unexpected builtin ID");
     }
     Function *Callee =
         CGM.getIntrinsic(IntNo, {ConvertType(E->getType()), Low->getType()});
     return Builder.CreateCall(Callee, {Low, High});
   }
-  case WebAssembly::BI__builtin_wasm_widen_low_s_i32x4_i64x2:
-  case WebAssembly::BI__builtin_wasm_widen_high_s_i32x4_i64x2:
-  case WebAssembly::BI__builtin_wasm_widen_low_u_i32x4_i64x2:
-  case WebAssembly::BI__builtin_wasm_widen_high_u_i32x4_i64x2: {
+  case WebAssembly::BI__builtin_wasm_extend_low_s_i32x4_i64x2:
+  case WebAssembly::BI__builtin_wasm_extend_high_s_i32x4_i64x2:
+  case WebAssembly::BI__builtin_wasm_extend_low_u_i32x4_i64x2:
+  case WebAssembly::BI__builtin_wasm_extend_high_u_i32x4_i64x2: {
     Value *Vec = EmitScalarExpr(E->getArg(0));
     unsigned IntNo;
     switch (BuiltinID) {
-    case WebAssembly::BI__builtin_wasm_widen_low_s_i32x4_i64x2:
-      IntNo = Intrinsic::wasm_widen_low_signed;
+    case WebAssembly::BI__builtin_wasm_extend_low_s_i32x4_i64x2:
+      IntNo = Intrinsic::wasm_extend_low_signed;
       break;
-    case WebAssembly::BI__builtin_wasm_widen_high_s_i32x4_i64x2:
-      IntNo = Intrinsic::wasm_widen_high_signed;
+    case WebAssembly::BI__builtin_wasm_extend_high_s_i32x4_i64x2:
+      IntNo = Intrinsic::wasm_extend_high_signed;
       break;
-    case WebAssembly::BI__builtin_wasm_widen_low_u_i32x4_i64x2:
-      IntNo = Intrinsic::wasm_widen_low_unsigned;
+    case WebAssembly::BI__builtin_wasm_extend_low_u_i32x4_i64x2:
+      IntNo = Intrinsic::wasm_extend_low_unsigned;
       break;
-    case WebAssembly::BI__builtin_wasm_widen_high_u_i32x4_i64x2:
-      IntNo = Intrinsic::wasm_widen_high_unsigned;
+    case WebAssembly::BI__builtin_wasm_extend_high_u_i32x4_i64x2:
+      IntNo = Intrinsic::wasm_extend_high_unsigned;
       break;
     }
     Function *Callee = CGM.getIntrinsic(IntNo);
     return Builder.CreateCall(Callee, Vec);
   }
   case WebAssembly::BI__builtin_wasm_convert_low_s_i32x4_f64x2:
   case WebAssembly::BI__builtin_wasm_convert_low_u_i32x4_f64x2: {
     Value *Vec = EmitScalarExpr(E->getArg(0));
     unsigned IntNo;
     switch (BuiltinID) {
     case WebAssembly::BI__builtin_wasm_convert_low_s_i32x4_f64x2:
       IntNo = Intrinsic::wasm_convert_low_signed;
       break;
     case WebAssembly::BI__builtin_wasm_convert_low_u_i32x4_f64x2:
       IntNo = Intrinsic::wasm_convert_low_unsigned;
       break;
     }
     Function *Callee = CGM.getIntrinsic(IntNo);
     return Builder.CreateCall(Callee, Vec);
   }
-  case WebAssembly::BI__builtin_wasm_trunc_saturate_zero_s_f64x2_i32x4:
-  case WebAssembly::BI__builtin_wasm_trunc_saturate_zero_u_f64x2_i32x4: {
+  case WebAssembly::BI__builtin_wasm_trunc_sat_zero_s_f64x2_i32x4:
+  case WebAssembly::BI__builtin_wasm_trunc_sat_zero_u_f64x2_i32x4: {
     Value *Vec = EmitScalarExpr(E->getArg(0));
     unsigned IntNo;
     switch (BuiltinID) {
-    case WebAssembly::BI__builtin_wasm_trunc_saturate_zero_s_f64x2_i32x4:
-      IntNo = Intrinsic::wasm_trunc_saturate_zero_signed;
+    case WebAssembly::BI__builtin_wasm_trunc_sat_zero_s_f64x2_i32x4:
+      IntNo = Intrinsic::wasm_trunc_sat_zero_signed;
       break;
-    case WebAssembly::BI__builtin_wasm_trunc_saturate_zero_u_f64x2_i32x4:
-      IntNo = Intrinsic::wasm_trunc_saturate_zero_unsigned;
+    case WebAssembly::BI__builtin_wasm_trunc_sat_zero_u_f64x2_i32x4:
+      IntNo = Intrinsic::wasm_trunc_sat_zero_unsigned;
       break;
     }
     Function *Callee = CGM.getIntrinsic(IntNo);
     return Builder.CreateCall(Callee, Vec);
   }
   case WebAssembly::BI__builtin_wasm_demote_zero_f64x2_f32x4: {
     Value *Vec = EmitScalarExpr(E->getArg(0));
     Function *Callee = CGM.getIntrinsic(Intrinsic::wasm_demote_zero);

clang/lib/Headers/wasm_simd128.h

 static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_v128_andnot(v128_t __a,
                                                              v128_t __b) {
   return __a & ~__b;
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_v128_bitselect(v128_t __a,
                                                                 v128_t __b,
                                                                 v128_t __mask) {
   return (v128_t)__builtin_wasm_bitselect((__i32x4)__a, (__i32x4)__b,
                                           (__i32x4)__mask);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i8x16_abs(v128_t __a) {
   return (v128_t)__builtin_wasm_abs_i8x16((__i8x16)__a);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i8x16_neg(v128_t __a) {
   return (v128_t)(-(__u8x16)__a);
 }
 
 static __inline__ bool __DEFAULT_FN_ATTRS wasm_i8x16_any_true(v128_t __a) {
   return __builtin_wasm_any_true_i8x16((__i8x16)__a);
 }
 
 static __inline__ bool __DEFAULT_FN_ATTRS wasm_i8x16_all_true(v128_t __a) {
   return __builtin_wasm_all_true_i8x16((__i8x16)__a);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i8x16_shl(v128_t __a,
                                                            int32_t __b) {
   return (v128_t)((__i8x16)__a << __b);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i8x16_shr(v128_t __a,
                                                            int32_t __b) {
   return (v128_t)((__i8x16)__a >> __b);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_u8x16_shr(v128_t __a,
                                                            int32_t __b) {
   return (v128_t)((__u8x16)__a >> __b);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i8x16_add(v128_t __a,
                                                            v128_t __b) {
   return (v128_t)((__u8x16)__a + (__u8x16)__b);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS
 wasm_i8x16_add_saturate(v128_t __a, v128_t __b) {
-  return (v128_t)__builtin_wasm_add_saturate_s_i8x16((__i8x16)__a,
-                                                     (__i8x16)__b);
+  return (v128_t)__builtin_wasm_add_sat_s_i8x16((__i8x16)__a, (__i8x16)__b);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS
 wasm_u8x16_add_saturate(v128_t __a, v128_t __b) {
-  return (v128_t)__builtin_wasm_add_saturate_u_i8x16((__u8x16)__a,
-                                                     (__u8x16)__b);
+  return (v128_t)__builtin_wasm_add_sat_u_i8x16((__u8x16)__a, (__u8x16)__b);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i8x16_sub(v128_t __a,
                                                            v128_t __b) {
   return (v128_t)((__u8x16)__a - (__u8x16)__b);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS
 wasm_i8x16_sub_saturate(v128_t __a, v128_t __b) {
-  return (v128_t)__builtin_wasm_sub_saturate_s_i8x16((__i8x16)__a,
-                                                     (__i8x16)__b);
+  return (v128_t)__builtin_wasm_sub_sat_s_i8x16((__i8x16)__a, (__i8x16)__b);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS
 wasm_u8x16_sub_saturate(v128_t __a, v128_t __b) {
-  return (v128_t)__builtin_wasm_sub_saturate_u_i8x16((__u8x16)__a,
-                                                     (__u8x16)__b);
+  return (v128_t)__builtin_wasm_sub_sat_u_i8x16((__u8x16)__a, (__u8x16)__b);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i8x16_min(v128_t __a,
                                                            v128_t __b) {
   return (v128_t)__builtin_wasm_min_s_i8x16((__i8x16)__a, (__i8x16)__b);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_u8x16_min(v128_t __a,
                                                            v128_t __b) {
   return (v128_t)__builtin_wasm_min_u_i8x16((__u8x16)__a, (__u8x16)__b);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i8x16_max(v128_t __a,
                                                            v128_t __b) {
   return (v128_t)__builtin_wasm_max_s_i8x16((__i8x16)__a, (__i8x16)__b);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_u8x16_max(v128_t __a,
                                                            v128_t __b) {
   return (v128_t)__builtin_wasm_max_u_i8x16((__u8x16)__a, (__u8x16)__b);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_u8x16_avgr(v128_t __a,
                                                             v128_t __b) {
   return (v128_t)__builtin_wasm_avgr_u_i8x16((__u8x16)__a, (__u8x16)__b);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i16x8_abs(v128_t __a) {
   return (v128_t)__builtin_wasm_abs_i16x8((__i16x8)__a);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i16x8_neg(v128_t __a) {
   return (v128_t)(-(__u16x8)__a);
 }
 
 static __inline__ bool __DEFAULT_FN_ATTRS wasm_i16x8_any_true(v128_t __a) {
   return __builtin_wasm_any_true_i16x8((__i16x8)__a);
 }
 
 static __inline__ bool __DEFAULT_FN_ATTRS wasm_i16x8_all_true(v128_t __a) {
   return __builtin_wasm_all_true_i16x8((__i16x8)__a);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i16x8_shl(v128_t __a,
                                                            int32_t __b) {
   return (v128_t)((__i16x8)__a << __b);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i16x8_shr(v128_t __a,
                                                            int32_t __b) {
   return (v128_t)((__i16x8)__a >> __b);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_u16x8_shr(v128_t __a,
                                                            int32_t __b) {
   return (v128_t)((__u16x8)__a >> __b);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i16x8_add(v128_t __a,
                                                            v128_t __b) {
   return (v128_t)((__u16x8)__a + (__u16x8)__b);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS
 wasm_i16x8_add_saturate(v128_t __a, v128_t __b) {
-  return (v128_t)__builtin_wasm_add_saturate_s_i16x8((__i16x8)__a,
-                                                     (__i16x8)__b);
+  return (v128_t)__builtin_wasm_add_sat_s_i16x8((__i16x8)__a, (__i16x8)__b);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS
 wasm_u16x8_add_saturate(v128_t __a, v128_t __b) {
-  return (v128_t)__builtin_wasm_add_saturate_u_i16x8((__u16x8)__a,
-                                                     (__u16x8)__b);
+  return (v128_t)__builtin_wasm_add_sat_u_i16x8((__u16x8)__a, (__u16x8)__b);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i16x8_sub(v128_t __a,
                                                            v128_t __b) {
   return (v128_t)((__i16x8)__a - (__i16x8)__b);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS
 wasm_i16x8_sub_saturate(v128_t __a, v128_t __b) {
-  return (v128_t)__builtin_wasm_sub_saturate_s_i16x8((__i16x8)__a,
-                                                     (__i16x8)__b);
+  return (v128_t)__builtin_wasm_sub_sat_s_i16x8((__i16x8)__a, (__i16x8)__b);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS
 wasm_u16x8_sub_saturate(v128_t __a, v128_t __b) {
-  return (v128_t)__builtin_wasm_sub_saturate_u_i16x8((__u16x8)__a,
-                                                     (__u16x8)__b);
+  return (v128_t)__builtin_wasm_sub_sat_u_i16x8((__u16x8)__a, (__u16x8)__b);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i16x8_mul(v128_t __a,
                                                            v128_t __b) {
   return (v128_t)((__u16x8)__a * (__u16x8)__b);
 }
 
 static __inline__ v128_t __DEFAULT_FN_ATTRS wasm_i16x8_min(v128_t __a,

clang/test/CodeGen/builtins-wasm.c

 
 void store64_lane(long long *p, i64x2 v) {
   __builtin_wasm_store64_lane(p, v, 0);
   // WEBASSEMBLY: call void @llvm.wasm.store64.lane(
   // WEBASSEMBLY-SAME: i64* %p, <2 x i64> %v, i32 0)
   // WEBASSEMBLY-NEXT: ret
 }
 
-i8x16 add_saturate_s_i8x16(i8x16 x, i8x16 y) {
-  return __builtin_wasm_add_saturate_s_i8x16(x, y);
+i8x16 add_sat_s_i8x16(i8x16 x, i8x16 y) {
+  return __builtin_wasm_add_sat_s_i8x16(x, y);
   // WEBASSEMBLY: call <16 x i8> @llvm.sadd.sat.v16i8(
   // WEBASSEMBLY-SAME: <16 x i8> %x, <16 x i8> %y)
   // WEBASSEMBLY-NEXT: ret
 }
 
-u8x16 add_saturate_u_i8x16(u8x16 x, u8x16 y) {
-  return __builtin_wasm_add_saturate_u_i8x16(x, y);
+u8x16 add_sat_u_i8x16(u8x16 x, u8x16 y) {
+  return __builtin_wasm_add_sat_u_i8x16(x, y);
   // WEBASSEMBLY: call <16 x i8> @llvm.uadd.sat.v16i8(
   // WEBASSEMBLY-SAME: <16 x i8> %x, <16 x i8> %y)
   // WEBASSEMBLY-NEXT: ret
 }
 
-i16x8 add_saturate_s_i16x8(i16x8 x, i16x8 y) {
-  return __builtin_wasm_add_saturate_s_i16x8(x, y);
+i16x8 add_sat_s_i16x8(i16x8 x, i16x8 y) {
+  return __builtin_wasm_add_sat_s_i16x8(x, y);
   // WEBASSEMBLY: call <8 x i16> @llvm.sadd.sat.v8i16(
   // WEBASSEMBLY-SAME: <8 x i16> %x, <8 x i16> %y)
   // WEBASSEMBLY-NEXT: ret
 }
 
-u16x8 add_saturate_u_i16x8(u16x8 x, u16x8 y) {
-  return __builtin_wasm_add_saturate_u_i16x8(x, y);
+u16x8 add_sat_u_i16x8(u16x8 x, u16x8 y) {
+  return __builtin_wasm_add_sat_u_i16x8(x, y);
   // WEBASSEMBLY: call <8 x i16> @llvm.uadd.sat.v8i16(
   // WEBASSEMBLY-SAME: <8 x i16> %x, <8 x i16> %y)
   // WEBASSEMBLY-NEXT: ret
 }
 
-i8x16 sub_saturate_s_i8x16(i8x16 x, i8x16 y) {
-  return __builtin_wasm_sub_saturate_s_i8x16(x, y);
-  // WEBASSEMBLY: call <16 x i8> @llvm.wasm.sub.saturate.signed.v16i8(
+i8x16 sub_sat_s_i8x16(i8x16 x, i8x16 y) {
+  return __builtin_wasm_sub_sat_s_i8x16(x, y);
+  // WEBASSEMBLY: call <16 x i8> @llvm.wasm.sub.sat.signed.v16i8(
   // WEBASSEMBLY-SAME: <16 x i8> %x, <16 x i8> %y)
   // WEBASSEMBLY-NEXT: ret
 }
 
-u8x16 sub_saturate_u_i8x16(u8x16 x, u8x16 y) {
-  return __builtin_wasm_sub_saturate_u_i8x16(x, y);
-  // WEBASSEMBLY: call <16 x i8> @llvm.wasm.sub.saturate.unsigned.v16i8(
+u8x16 sub_sat_u_i8x16(u8x16 x, u8x16 y) {
+  return __builtin_wasm_sub_sat_u_i8x16(x, y);
+  // WEBASSEMBLY: call <16 x i8> @llvm.wasm.sub.sat.unsigned.v16i8(
   // WEBASSEMBLY-SAME: <16 x i8> %x, <16 x i8> %y)
   // WEBASSEMBLY-NEXT: ret
 }
 
 i8x16 abs_i8x16(i8x16 v) {
   return __builtin_wasm_abs_i8x16(v);
   // WEBASSEMBLY: call <16 x i8> @llvm.abs.v16i8(<16 x i8> %v, i1 false)
   // WEBASSEMBLY-NEXT: ret

 
 u32x4 max_u_i32x4(u32x4 x, u32x4 y) {
   return __builtin_wasm_max_u_i32x4(x, y);
   // WEBASSEMBLY: %0 = icmp ugt <4 x i32> %x, %y
   // WEBASSEMBLY-NEXT: %1 = select <4 x i1> %0, <4 x i32> %x, <4 x i32> %y
   // WEBASSEMBLY-NEXT: ret <4 x i32> %1
 }
 
-i16x8 sub_saturate_s_i16x8(i16x8 x, i16x8 y) {
-  return __builtin_wasm_sub_saturate_s_i16x8(x, y);
-  // WEBASSEMBLY: call <8 x i16> @llvm.wasm.sub.saturate.signed.v8i16(
+i16x8 sub_sat_s_i16x8(i16x8 x, i16x8 y) {
+  return __builtin_wasm_sub_sat_s_i16x8(x, y);
+  // WEBASSEMBLY: call <8 x i16> @llvm.wasm.sub.sat.signed.v8i16(
   // WEBASSEMBLY-SAME: <8 x i16> %x, <8 x i16> %y)
   // WEBASSEMBLY-NEXT: ret
 }
 
-u16x8 sub_saturate_u_i16x8(u16x8 x, u16x8 y) {
-  return __builtin_wasm_sub_saturate_u_i16x8(x, y);
-  // WEBASSEMBLY: call <8 x i16> @llvm.wasm.sub.saturate.unsigned.v8i16(
+u16x8 sub_sat_u_i16x8(u16x8 x, u16x8 y) {
+  return __builtin_wasm_sub_sat_u_i16x8(x, y);
+  // WEBASSEMBLY: call <8 x i16> @llvm.wasm.sub.sat.unsigned.v8i16(
   // WEBASSEMBLY-SAME: <8 x i16> %x, <8 x i16> %y)
   // WEBASSEMBLY-NEXT: ret
 }
 
 u8x16 avgr_u_i8x16(u8x16 x, u8x16 y) {
   return __builtin_wasm_avgr_u_i8x16(x, y);
   // WEBASSEMBLY: call <16 x i8> @llvm.wasm.avgr.unsigned.v16i8(
   // WEBASSEMBLY-SAME: <16 x i8> %x, <16 x i8> %y)
   // WEBASSEMBLY-NEXT: ret
 }
 
 u16x8 avgr_u_i16x8(u16x8 x, u16x8 y) {
   return __builtin_wasm_avgr_u_i16x8(x, y);
   // WEBASSEMBLY: call <8 x i16> @llvm.wasm.avgr.unsigned.v8i16(
   // WEBASSEMBLY-SAME: <8 x i16> %x, <8 x i16> %y)
   // WEBASSEMBLY-NEXT: ret
 }
 
-i16x8 q15mulr_saturate_s_i16x8(i16x8 x, i16x8 y) {
-  return __builtin_wasm_q15mulr_saturate_s_i16x8(x, y);
-  // WEBASSEMBLY: call <8 x i16> @llvm.wasm.q15mulr.saturate.signed(
+i16x8 q15mulr_sat_s_i16x8(i16x8 x, i16x8 y) {
+  return __builtin_wasm_q15mulr_sat_s_i16x8(x, y);
+  // WEBASSEMBLY: call <8 x i16> @llvm.wasm.q15mulr.sat.signed(
   // WEBASSEMBLY-SAME: <8 x i16> %x, <8 x i16> %y)
   // WEBASSEMBLY-NEXT: ret
 }
 
 i16x8 extmul_low_i8x16_s_i16x8(i8x16 x, i8x16 y) {
   return __builtin_wasm_extmul_low_i8x16_s_i16x8(x, y);
   // WEBASSEMBLY: call <8 x i16> @llvm.wasm.extmul.low.signed.v8i16(
   // WEBASSEMBLY-SAME: <16 x i8> %x, <16 x i8> %y)

 
 u16x8 narrow_u_i16x8_i32x4(u32x4 low, u32x4 high) {
   return __builtin_wasm_narrow_u_i16x8_i32x4(low, high);
   // WEBASSEMBLY: call <8 x i16> @llvm.wasm.narrow.unsigned.v8i16.v4i32(
   // WEBASSEMBLY-SAME: <4 x i32> %low, <4 x i32> %high)
   // WEBASSEMBLY: ret
 }
 
-i64x2 widen_low_s_i32x4_i64x2(i32x4 x) {
-  return __builtin_wasm_widen_low_s_i32x4_i64x2(x);
-  // WEBASSEMBLY: call <2 x i64> @llvm.wasm.widen.low.signed(<4 x i32> %x)
+i64x2 extend_low_s_i32x4_i64x2(i32x4 x) {
+  return __builtin_wasm_extend_low_s_i32x4_i64x2(x);
+  // WEBASSEMBLY: call <2 x i64> @llvm.wasm.extend.low.signed(<4 x i32> %x)
   // WEBASSEMBLY: ret
 }
 
-i64x2 widen_high_s_i32x4_i64x2(i32x4 x) {
-  return __builtin_wasm_widen_high_s_i32x4_i64x2(x);
-  // WEBASSEMBLY: call <2 x i64> @llvm.wasm.widen.high.signed(<4 x i32> %x)
+i64x2 extend_high_s_i32x4_i64x2(i32x4 x) {
+  return __builtin_wasm_extend_high_s_i32x4_i64x2(x);
+  // WEBASSEMBLY: call <2 x i64> @llvm.wasm.extend.high.signed(<4 x i32> %x)
   // WEBASSEMBLY: ret
 }
 
-u64x2 widen_low_u_i32x4_i64x2(u32x4 x) {
-  return __builtin_wasm_widen_low_u_i32x4_i64x2(x);
-  // WEBASSEMBLY: call <2 x i64> @llvm.wasm.widen.low.unsigned(<4 x i32> %x)
+u64x2 extend_low_u_i32x4_i64x2(u32x4 x) {
+  return __builtin_wasm_extend_low_u_i32x4_i64x2(x);
+  // WEBASSEMBLY: call <2 x i64> @llvm.wasm.extend.low.unsigned(<4 x i32> %x)
   // WEBASSEMBLY: ret
 }
 
-u64x2 widen_high_u_i32x4_i64x2(u32x4 x) {
-  return __builtin_wasm_widen_high_u_i32x4_i64x2(x);
-  // WEBASSEMBLY: call <2 x i64> @llvm.wasm.widen.high.unsigned(<4 x i32> %x)
+u64x2 extend_high_u_i32x4_i64x2(u32x4 x) {
+  return __builtin_wasm_extend_high_u_i32x4_i64x2(x);
+  // WEBASSEMBLY: call <2 x i64> @llvm.wasm.extend.high.unsigned(<4 x i32> %x)
   // WEBASSEMBLY: ret
 }
 
 f64x2 convert_low_s_i32x4_f64x2(i32x4 x) {
   return __builtin_wasm_convert_low_s_i32x4_f64x2(x);
   // WEBASSEMBLY: call <2 x double> @llvm.wasm.convert.low.signed(<4 x i32> %x)
   // WEBASSEMBLY: ret
 }
 
 f64x2 convert_low_u_i32x4_f64x2(u32x4 x) {
   return __builtin_wasm_convert_low_u_i32x4_f64x2(x);
   // WEBASSEMBLY: call <2 x double> @llvm.wasm.convert.low.unsigned(<4 x i32> %x)
   // WEBASSEMBLY: ret
 }
 
-i32x4 trunc_saturate_zero_s_f64x2_i32x4(f64x2 x) {
-  return __builtin_wasm_trunc_saturate_zero_s_f64x2_i32x4(x);
-  // WEBASSEMBLY: call <4 x i32> @llvm.wasm.trunc.saturate.zero.signed(<2 x double> %x)
+i32x4 trunc_sat_zero_s_f64x2_i32x4(f64x2 x) {
+  return __builtin_wasm_trunc_sat_zero_s_f64x2_i32x4(x);
+  // WEBASSEMBLY: call <4 x i32> @llvm.wasm.trunc.sat.zero.signed(<2 x double> %x)
   // WEBASSEMBLY: ret
 }
 
-u32x4 trunc_saturate_zero_u_f64x2_i32x4(f64x2 x) {
-  return __builtin_wasm_trunc_saturate_zero_u_f64x2_i32x4(x);
-  // WEBASSEMBLY: call <4 x i32> @llvm.wasm.trunc.saturate.zero.unsigned(<2 x double> %x)
+u32x4 trunc_sat_zero_u_f64x2_i32x4(f64x2 x) {
+  return __builtin_wasm_trunc_sat_zero_u_f64x2_i32x4(x);
+  // WEBASSEMBLY: call <4 x i32> @llvm.wasm.trunc.sat.zero.unsigned(<2 x double> %x)
   // WEBASSEMBLY: ret
 }
 
 f32x4 wasm_demote_zero_f64x2_f32x4(f64x2 x) {
   return __builtin_wasm_demote_zero_f64x2_f32x4(x);
   // WEBASSEMBLY: call <4 x float> @llvm.wasm.demote.zero(<2 x double> %x)
   // WEBASSEMBLY: ret
 }

llvm/include/llvm/IR/IntrinsicsWebAssembly.td

Intrinsic<[llvm_v16i8_ty],
             [IntrNoMem, IntrSpeculatable]>;
 def int_wasm_shuffle :
   Intrinsic<[llvm_v16i8_ty],
             [llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty, llvm_i32_ty,
              llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
              llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
              llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
             [IntrNoMem, IntrSpeculatable]>;
-def int_wasm_sub_saturate_signed :
+def int_wasm_sub_sat_signed :
   Intrinsic<[llvm_anyvector_ty],
             [LLVMMatchType<0>, LLVMMatchType<0>],
             [IntrNoMem, IntrSpeculatable]>;
-def int_wasm_sub_saturate_unsigned :
+def int_wasm_sub_sat_unsigned :
   Intrinsic<[llvm_anyvector_ty],
             [LLVMMatchType<0>, LLVMMatchType<0>],
             [IntrNoMem, IntrSpeculatable]>;
 def int_wasm_avgr_unsigned :
   Intrinsic<[llvm_anyvector_ty],
             [LLVMMatchType<0>, LLVMMatchType<0>],
             [IntrNoMem, IntrSpeculatable]>;
 def int_wasm_bitselect :
Intrinsic<[llvm_anyvector_ty],
             [llvm_anyvector_ty, LLVMMatchType<1>],
             [IntrNoMem, IntrSpeculatable]>;
 def int_wasm_narrow_unsigned :
   Intrinsic<[llvm_anyvector_ty],
             [llvm_anyvector_ty, LLVMMatchType<1>],
             [IntrNoMem, IntrSpeculatable]>;
 
 // TODO: Replace these intrinsics with normal ISel patterns once i32x4 to i64x2
-// widening is merged to the proposal.
-def int_wasm_widen_low_signed :
+// extending is merged to the proposal.
+def int_wasm_extend_low_signed :
   Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty], [IntrNoMem, IntrSpeculatable]>;
-def int_wasm_widen_high_signed :
+def int_wasm_extend_high_signed :
   Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty], [IntrNoMem, IntrSpeculatable]>;
-def int_wasm_widen_low_unsigned :
+def int_wasm_extend_low_unsigned :
   Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty], [IntrNoMem, IntrSpeculatable]>;
-def int_wasm_widen_high_unsigned :
+def int_wasm_extend_high_unsigned :
   Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty], [IntrNoMem, IntrSpeculatable]>;
 
-def int_wasm_q15mulr_saturate_signed :
+def int_wasm_q15mulr_sat_signed :
   Intrinsic<[llvm_v8i16_ty],
             [llvm_v8i16_ty, llvm_v8i16_ty],
             [IntrNoMem, IntrSpeculatable]>;
 
 // TODO: Replace these intrinsics with normal ISel patterns
 def int_wasm_pmin :
   Intrinsic<[llvm_anyvector_ty],
             [LLVMMatchType<0>, LLVMMatchType<0>],

 
 // TODO: Remove these if possible if they are merged to the spec.
 def int_wasm_convert_low_signed :
   Intrinsic<[llvm_v2f64_ty], [llvm_v4i32_ty],
             [IntrNoMem, IntrSpeculatable]>;
 def int_wasm_convert_low_unsigned :
   Intrinsic<[llvm_v2f64_ty], [llvm_v4i32_ty],
             [IntrNoMem, IntrSpeculatable]>;
-def int_wasm_trunc_saturate_zero_signed :
+def int_wasm_trunc_sat_zero_signed :
   Intrinsic<[llvm_v4i32_ty], [llvm_v2f64_ty],
             [IntrNoMem, IntrSpeculatable]>;
-def int_wasm_trunc_saturate_zero_unsigned :
+def int_wasm_trunc_sat_zero_unsigned :
   Intrinsic<[llvm_v4i32_ty], [llvm_v2f64_ty],
             [IntrNoMem, IntrSpeculatable]>;
 def int_wasm_demote_zero :
   Intrinsic<[llvm_v4f32_ty], [llvm_v2f64_ty],
             [IntrNoMem, IntrSpeculatable]>;
 def int_wasm_promote_low :
   Intrinsic<[llvm_v2f64_ty], [llvm_v4f32_ty],
             [IntrNoMem, IntrSpeculatable]>;

llvm/lib/Target/WebAssembly/WebAssemblyISD.def

 HANDLE_NODETYPE(WrapperPIC)
 HANDLE_NODETYPE(BR_IF)
 HANDLE_NODETYPE(BR_TABLE)
 HANDLE_NODETYPE(SHUFFLE)
 HANDLE_NODETYPE(SWIZZLE)
 HANDLE_NODETYPE(VEC_SHL)
 HANDLE_NODETYPE(VEC_SHR_S)
 HANDLE_NODETYPE(VEC_SHR_U)
-HANDLE_NODETYPE(WIDEN_LOW_S)
-HANDLE_NODETYPE(WIDEN_LOW_U)
-HANDLE_NODETYPE(WIDEN_HIGH_S)
-HANDLE_NODETYPE(WIDEN_HIGH_U)
+HANDLE_NODETYPE(EXTEND_LOW_S)
+HANDLE_NODETYPE(EXTEND_LOW_U)
+HANDLE_NODETYPE(EXTEND_HIGH_S)
+HANDLE_NODETYPE(EXTEND_HIGH_U)
 HANDLE_NODETYPE(THROW)
 HANDLE_NODETYPE(CATCH)
 HANDLE_NODETYPE(MEMORY_COPY)
 HANDLE_NODETYPE(MEMORY_FILL)
 
 // Memory intrinsics
 HANDLE_MEM_NODETYPE(LOAD_SPLAT)

llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

performVECTOR_SHUFFLECombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
   if (!SrcType.is128BitVector() ||
       SrcType.getVectorNumElements() != DstType.getVectorNumElements())
     return SDValue();
   SDValue NewShuffle = DAG.getVectorShuffle(
       SrcType, SDLoc(N), CastOp, DAG.getUNDEF(SrcType), Shuffle->getMask());
   return DAG.getBitcast(DstType, NewShuffle);
 }
 
-static SDValue performVectorWidenCombine(SDNode *N,
-                                         TargetLowering::DAGCombinerInfo &DCI) {
+static SDValue
+performVectorExtendCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
   auto &DAG = DCI.DAG;
   assert(N->getOpcode() == ISD::SIGN_EXTEND ||
          N->getOpcode() == ISD::ZERO_EXTEND);
 
   // Combine ({s,z}ext (extract_subvector src, i)) into a widening operation if
   // possible before the extract_subvector can be expanded.
   auto Extract = N->getOperand(0);
   if (Extract.getOpcode() != ISD::EXTRACT_SUBVECTOR)
if (Extract.getValueType() != MVT::v4i16 ||
       return SDValue();
   } else {
     return SDValue();
   }
 
   bool IsSext = N->getOpcode() == ISD::SIGN_EXTEND;
   bool IsLow = Index == 0;
 
-  unsigned Op = IsSext ? (IsLow ? WebAssemblyISD::WIDEN_LOW_S
-                                : WebAssemblyISD::WIDEN_HIGH_S)
-                       : (IsLow ? WebAssemblyISD::WIDEN_LOW_U
-                                : WebAssemblyISD::WIDEN_HIGH_U);
+  unsigned Op = IsSext ? (IsLow ? WebAssemblyISD::EXTEND_LOW_S
+                                : WebAssemblyISD::EXTEND_HIGH_S)
+                       : (IsLow ? WebAssemblyISD::EXTEND_LOW_U
+                                : WebAssemblyISD::EXTEND_HIGH_U);
 
   return DAG.getNode(Op, SDLoc(N), ResVT, Source);
 }
 
 SDValue
 WebAssemblyTargetLowering::PerformDAGCombine(SDNode *N,
                                              DAGCombinerInfo &DCI) const {
   switch (N->getOpcode()) {
   default:
     return SDValue();
   case ISD::VECTOR_SHUFFLE:
     return performVECTOR_SHUFFLECombine(N, DCI);
   case ISD::SIGN_EXTEND:
   case ISD::ZERO_EXTEND:
-    return performVectorWidenCombine(N, DCI);
+    return performVectorExtendCombine(N, DCI);
   }
 }

llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

SIMD_I<(outs V128:$dst),
            (outs), (ins P2Align:$p2align, offset64_op:$off), [],
            name#"\t$dst, ${off}(${addr})$p2align",
            name#"\t$off$p2align", simdop>;
   } // mayLoad = 1, UseNamedOperandTable = 1
 }
 
 // TODO: Also support v4f32 and v2f64 once the instructions are merged
 // to the proposal
-defm "" : SIMDLoadZero<I32x4, 252>;
-defm "" : SIMDLoadZero<I64x2, 253>;
+defm "" : SIMDLoadZero<I32x4, 0x5c>;
+defm "" : SIMDLoadZero<I64x2, 0x5d>;
 
 foreach vec = [I32x4, I64x2] in {
 defvar loadpat = !cast<Intrinsic>("int_wasm_load"#vec.lane_bits#"_zero");
 defvar inst = "LOAD_ZERO_"#vec;
 defm : LoadPatNoOffset<vec.vt, loadpat, inst>;
 defm : LoadPatImmOff<vec.vt, loadpat, regPlusImm, inst>;
 defm : LoadPatImmOff<vec.vt, loadpat, or_is_add, inst>;
 defm : LoadPatOffsetOnly<vec.vt, loadpat, inst>;
SIMD_I<(outs V128:$dst),
            (outs), (ins P2Align:$p2align, offset64_op:$off, vec_i8imm_op:$idx),
            [], name#"\t$dst, ${off}(${addr})$p2align, $vec, $idx",
            name#"\t$off$p2align, $idx", simdop>;
   } // mayLoad = 1, UseNamedOperandTable = 1
 }
 
 // TODO: Also support v4f32 and v2f64 once the instructions are merged
 // to the proposal
-defm "" : SIMDLoadLane<I8x16, 88>;
-defm "" : SIMDLoadLane<I16x8, 89>;
-defm "" : SIMDLoadLane<I32x4, 90>;
-defm "" : SIMDLoadLane<I64x2, 91>;
+defm "" : SIMDLoadLane<I8x16, 0x54>;
+defm "" : SIMDLoadLane<I16x8, 0x55>;
+defm "" : SIMDLoadLane<I32x4, 0x56>;
+defm "" : SIMDLoadLane<I64x2, 0x57>;
 
 // Select loads with no constant offset.
 multiclass LoadLanePatNoOffset<Vec vec, SDPatternOperator kind> {
   defvar load_lane_a32 = !cast<NI>("LOAD_LANE_"#vec#"_A32");
   defvar load_lane_a64 = !cast<NI>("LOAD_LANE_"#vec#"_A64");
   def : Pat<(vec.vt (kind (i32 I32:$addr),
               (vec.vt V128:$vec), (i32 vec.lane_idx:$idx))),
             (load_lane_a32 0, 0, imm:$idx, $addr, $vec)>,
SIMD_I<(outs V128:$dst),
            (outs), (ins P2Align:$p2align, offset64_op:$off, vec_i8imm_op:$idx),
            [], name#"\t${off}(${addr})$p2align, $vec, $idx",
            name#"\t$off$p2align, $idx", simdop>;
   } // mayStore = 1, UseNamedOperandTable = 1
 }
 
 // TODO: Also support v4f32 and v2f64 once the instructions are merged
 // to the proposal
-defm "" : SIMDStoreLane<I8x16, 92>;
-defm "" : SIMDStoreLane<I16x8, 93>;
-defm "" : SIMDStoreLane<I32x4, 94>;
-defm "" : SIMDStoreLane<I64x2, 95>;
+defm "" : SIMDStoreLane<I8x16, 0x58>;
+defm "" : SIMDStoreLane<I16x8, 0x59>;
+defm "" : SIMDStoreLane<I32x4, 0x5a>;
+defm "" : SIMDStoreLane<I64x2, 0x5b>;
 
 // Select stores with no constant offset.
 multiclass StoreLanePatNoOffset<Vec vec, Intrinsic kind> {
   def : Pat<(kind (i32 I32:$addr), (vec.vt V128:$vec), (i32 vec.lane_idx:$idx)),
             (!cast<NI>("STORE_LANE_"#vec#"_A32") 0, 0, imm:$idx, $addr, $vec)>,
         Requires<[HasAddr32]>;
   def : Pat<(kind (i64 I64:$addr), (vec.vt V128:$vec), (i32 vec.lane_idx:$idx)),
             (!cast<NI>("STORE_LANE_"#vec#"_A64") 0, 0, imm:$idx, $addr, $vec)>,
multiclass SIMDBinaryIntNoI64x2<SDPatternOperator node, string name, bits<32> baseInst> {
   defm "" : SIMDBinary<I32x4, node, name, !add(baseInst, 64)>;
 }
 
 multiclass SIMDBinaryInt<SDPatternOperator node, string name, bits<32> baseInst> {
   defm "" : SIMDBinaryIntNoI64x2<node, name, baseInst>;
   defm "" : SIMDBinary<I64x2, node, name, !add(baseInst, 96)>;
 }
 
-// Integer addition: add / add_saturate_s / add_saturate_u
+// Integer addition: add / add_sat_s / add_sat_u
 let isCommutable = 1 in {
 defm ADD : SIMDBinaryInt<add, "add", 110>;
-defm ADD_SAT_S : SIMDBinaryIntSmall<saddsat, "add_saturate_s", 111>;
-defm ADD_SAT_U : SIMDBinaryIntSmall<uaddsat, "add_saturate_u", 112>;
+defm ADD_SAT_S : SIMDBinaryIntSmall<saddsat, "add_sat_s", 111>;
+defm ADD_SAT_U : SIMDBinaryIntSmall<uaddsat, "add_sat_u", 112>;
 } // isCommutable = 1
 
-// Integer subtraction: sub / sub_saturate_s / sub_saturate_u
+// Integer subtraction: sub / sub_sat_s / sub_sat_u
 defm SUB : SIMDBinaryInt<sub, "sub", 113>;
 defm SUB_SAT_S :
-  SIMDBinaryIntSmall<int_wasm_sub_saturate_signed, "sub_saturate_s", 114>;
+  SIMDBinaryIntSmall<int_wasm_sub_sat_signed, "sub_sat_s", 114>;
 defm SUB_SAT_U :
-  SIMDBinaryIntSmall<int_wasm_sub_saturate_unsigned, "sub_saturate_u", 115>;
+  SIMDBinaryIntSmall<int_wasm_sub_sat_unsigned, "sub_sat_u", 115>;
 
 // Integer multiplication: mul
 let isCommutable = 1 in
 defm MUL : SIMDBinaryIntNoI8x16<mul, "mul", 117>;
 
 // Integer min_s / min_u / max_s / max_u
 let isCommutable = 1 in {
 defm MIN_S : SIMDBinaryIntNoI64x2<smin, "min_s", 118>;
defm _#vec : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
                       (outs), (ins),
                       [(set (vec.vt V128:$dst), (node
                          (vec.split.vt V128:$lhs),(vec.split.vt V128:$rhs)))],
                       vec.prefix#"."#name#"\t$dst, $lhs, $rhs",
                       vec.prefix#"."#name, simdop>;
 }
 
 defm EXTMUL_LOW_S :
-  SIMDExtBinary<I16x8, int_wasm_extmul_low_signed, "extmul_low_i8x16_s", 154>;
+  SIMDExtBinary<I16x8, int_wasm_extmul_low_signed, "extmul_low_i8x16_s", 0x9c>;
 defm EXTMUL_HIGH_S :
-  SIMDExtBinary<I16x8, int_wasm_extmul_high_signed, "extmul_high_i8x16_s", 157>;
+  SIMDExtBinary<I16x8, int_wasm_extmul_high_signed, "extmul_high_i8x16_s", 0x9d>;
 defm EXTMUL_LOW_U :
-  SIMDExtBinary<I16x8, int_wasm_extmul_low_unsigned, "extmul_low_i8x16_u", 158>;
+  SIMDExtBinary<I16x8, int_wasm_extmul_low_unsigned, "extmul_low_i8x16_u", 0x9e>;
 defm EXTMUL_HIGH_U :
-  SIMDExtBinary<I16x8, int_wasm_extmul_high_unsigned, "extmul_high_i8x16_u", 159>;
+  SIMDExtBinary<I16x8, int_wasm_extmul_high_unsigned, "extmul_high_i8x16_u", 0x9f>;
 
 defm EXTMUL_LOW_S :
-  SIMDExtBinary<I32x4, int_wasm_extmul_low_signed, "extmul_low_i16x8_s", 187>;
+  SIMDExtBinary<I32x4, int_wasm_extmul_low_signed, "extmul_low_i16x8_s", 0xbc>;
 defm EXTMUL_HIGH_S :
-  SIMDExtBinary<I32x4, int_wasm_extmul_high_signed, "extmul_high_i16x8_s", 189>;
+  SIMDExtBinary<I32x4, int_wasm_extmul_high_signed, "extmul_high_i16x8_s", 0xbd>;
 defm EXTMUL_LOW_U :
-  SIMDExtBinary<I32x4, int_wasm_extmul_low_unsigned, "extmul_low_i16x8_u", 190>;
+  SIMDExtBinary<I32x4, int_wasm_extmul_low_unsigned, "extmul_low_i16x8_u", 0xbe>;
 defm EXTMUL_HIGH_U :
-  SIMDExtBinary<I32x4, int_wasm_extmul_high_unsigned, "extmul_high_i16x8_u", 191>;
+  SIMDExtBinary<I32x4, int_wasm_extmul_high_unsigned, "extmul_high_i16x8_u", 0xbf>;
 
 defm EXTMUL_LOW_S :
-  SIMDExtBinary<I64x2, int_wasm_extmul_low_signed, "extmul_low_i32x4_s", 210>;
+  SIMDExtBinary<I64x2, int_wasm_extmul_low_signed, "extmul_low_i32x4_s", 0xdc>;
 defm EXTMUL_HIGH_S :
-  SIMDExtBinary<I64x2, int_wasm_extmul_high_signed, "extmul_high_i32x4_s", 211>;
+  SIMDExtBinary<I64x2, int_wasm_extmul_high_signed, "extmul_high_i32x4_s", 0xdd>;
 defm EXTMUL_LOW_U :
-  SIMDExtBinary<I64x2, int_wasm_extmul_low_unsigned, "extmul_low_i32x4_u", 214>;
+  SIMDExtBinary<I64x2, int_wasm_extmul_low_unsigned, "extmul_low_i32x4_u", 0xde>;
 defm EXTMUL_HIGH_U :
-  SIMDExtBinary<I64x2, int_wasm_extmul_high_unsigned, "extmul_high_i32x4_u", 215>;
+  SIMDExtBinary<I64x2, int_wasm_extmul_high_unsigned, "extmul_high_i32x4_u", 0xdf>;
 
 //===----------------------------------------------------------------------===//
 // Floating-point unary arithmetic
 //===----------------------------------------------------------------------===//
 
 multiclass SIMDUnaryFP<SDNode node, string name, bits<32> baseInst> {
   defm "" : SIMDUnary<F32x4, node, name, baseInst>;
   defm "" : SIMDUnary<F64x2, node, name, !add(baseInst, 12)>;
 }
 
 // Absolute value: abs
 defm ABS : SIMDUnaryFP<fabs, "abs", 224>;
 
 // Negation: neg
 defm NEG : SIMDUnaryFP<fneg, "neg", 225>;
 
 // Square root: sqrt
 defm SQRT : SIMDUnaryFP<fsqrt, "sqrt", 227>;
 
 // Rounding: ceil, floor, trunc, nearest
-defm CEIL : SIMDUnary<F32x4, int_wasm_ceil, "ceil", 216>;
-defm FLOOR : SIMDUnary<F32x4, int_wasm_floor, "floor", 217>;
-defm TRUNC: SIMDUnary<F32x4, int_wasm_trunc, "trunc", 218>;
-defm NEAREST: SIMDUnary<F32x4, int_wasm_nearest, "nearest", 219>;
-defm CEIL : SIMDUnary<F64x2, int_wasm_ceil, "ceil", 220>;
-defm FLOOR : SIMDUnary<F64x2, int_wasm_floor, "floor", 221>;
-defm TRUNC: SIMDUnary<F64x2, int_wasm_trunc, "trunc", 222>;
-defm NEAREST: SIMDUnary<F64x2, int_wasm_nearest, "nearest", 223>;
+defm CEIL : SIMDUnary<F32x4, int_wasm_ceil, "ceil", 0x67>;
+defm FLOOR : SIMDUnary<F32x4, int_wasm_floor, "floor", 0x68>;
+defm TRUNC: SIMDUnary<F32x4, int_wasm_trunc, "trunc", 0x69>;
+defm NEAREST: SIMDUnary<F32x4, int_wasm_nearest, "nearest", 0x6a>;
+defm CEIL : SIMDUnary<F64x2, int_wasm_ceil, "ceil", 0x74>;
+defm FLOOR : SIMDUnary<F64x2, int_wasm_floor, "floor", 0x75>;
+defm TRUNC: SIMDUnary<F64x2, int_wasm_trunc, "trunc", 0x7a>;
+defm NEAREST: SIMDUnary<F64x2, int_wasm_nearest, "nearest", 0x94>;
 
 //===----------------------------------------------------------------------===//
 // Floating-point binary arithmetic
 //===----------------------------------------------------------------------===//
 
 multiclass SIMDBinaryFP<SDPatternOperator node, string name, bits<32> baseInst> {
   defm "" : SIMDBinary<F32x4, node, name, baseInst>;
   defm "" : SIMDBinary<F64x2, node, name, !add(baseInst, 12)>;

 // Floating point to integer with saturation: trunc_sat
 defm "" : SIMDConvert<I32x4, F32x4, fp_to_sint, "trunc_sat_f32x4_s", 248>;
 defm "" : SIMDConvert<I32x4, F32x4, fp_to_uint, "trunc_sat_f32x4_u", 249>;
 
 // Integer to floating point: convert
 defm "" : SIMDConvert<F32x4, I32x4, sint_to_fp, "convert_i32x4_s", 250>;
 defm "" : SIMDConvert<F32x4, I32x4, uint_to_fp, "convert_i32x4_u", 251>;
 
-// Lower llvm.wasm.trunc.saturate.* to saturating instructions
+// Lower llvm.wasm.trunc.sat.* to saturating instructions
 def : Pat<(v4i32 (int_wasm_trunc_saturate_signed (v4f32 V128:$src))),
           (fp_to_sint_I32x4 $src)>;
 def : Pat<(v4i32 (int_wasm_trunc_saturate_unsigned (v4f32 V128:$src))),
           (fp_to_uint_I32x4 $src)>;
 
-// Widening operations
-def widen_t : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>;
-def widen_low_s : SDNode<"WebAssemblyISD::WIDEN_LOW_S", widen_t>;
-def widen_high_s : SDNode<"WebAssemblyISD::WIDEN_HIGH_S", widen_t>;
-def widen_low_u : SDNode<"WebAssemblyISD::WIDEN_LOW_U", widen_t>;
-def widen_high_u : SDNode<"WebAssemblyISD::WIDEN_HIGH_U", widen_t>;
+// Extending operations
+def extend_t : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>;
+def extend_low_s : SDNode<"WebAssemblyISD::EXTEND_LOW_S", extend_t>;
+def extend_high_s : SDNode<"WebAssemblyISD::EXTEND_HIGH_S", extend_t>;
+def extend_low_u : SDNode<"WebAssemblyISD::EXTEND_LOW_U", extend_t>;
+def extend_high_u : SDNode<"WebAssemblyISD::EXTEND_HIGH_U", extend_t>;
 
 // TODO: refactor this to be uniform for i64x2 if the numbering is not changed.
-multiclass SIMDWiden<Vec vec, bits<32> baseInst> {
-  defm "" : SIMDConvert<vec, vec.split, widen_low_s,
-                        "widen_low_"#vec.split.prefix#"_s", baseInst>;
-  defm "" : SIMDConvert<vec, vec.split, widen_high_s,
-                        "widen_high_"#vec.split.prefix#"_s", !add(baseInst, 1)>;
-  defm "" : SIMDConvert<vec, vec.split, widen_low_u,
-                        "widen_low_"#vec.split.prefix#"_u", !add(baseInst, 2)>;
-  defm "" : SIMDConvert<vec, vec.split, widen_high_u,
-                        "widen_high_"#vec.split.prefix#"_u", !add(baseInst, 3)>;
-}
-
-defm "" : SIMDWiden<I16x8, 135>;
-defm "" : SIMDWiden<I32x4, 167>;
-
-defm "" : SIMDConvert<I64x2, I32x4, int_wasm_widen_low_signed,
-                      "widen_low_i32x4_s", 199>;
-defm "" : SIMDConvert<I64x2, I32x4, int_wasm_widen_high_signed,
-                      "widen_high_i32x4_s", 200>;
-defm "" : SIMDConvert<I64x2, I32x4, int_wasm_widen_low_unsigned,
-                      "widen_low_i32x4_u", 201>;
-defm "" : SIMDConvert<I64x2, I32x4, int_wasm_widen_high_unsigned,
-                      "widen_high_i32x4_u", 202>;
+multiclass SIMDExtend<Vec vec, bits<32> baseInst> {
+  defm "" : SIMDConvert<vec, vec.split, extend_low_s,
+                        "extend_low_"#vec.split.prefix#"_s", baseInst>;
+  defm "" : SIMDConvert<vec, vec.split, extend_high_s,
+                        "extend_high_"#vec.split.prefix#"_s", !add(baseInst, 1)>;
+  defm "" : SIMDConvert<vec, vec.split, extend_low_u,
+                        "extend_low_"#vec.split.prefix#"_u", !add(baseInst, 2)>;
+  defm "" : SIMDConvert<vec, vec.split, extend_high_u,
+                        "extend_high_"#vec.split.prefix#"_u", !add(baseInst, 3)>;
+}
+
+defm "" : SIMDExtend<I16x8, 135>;
+defm "" : SIMDExtend<I32x4, 167>;
+
+defm "" : SIMDConvert<I64x2, I32x4, int_wasm_extend_low_signed,
+                      "extend_low_i32x4_s", 199>;
+defm "" : SIMDConvert<I64x2, I32x4, int_wasm_extend_high_signed,
+                      "extend_high_i32x4_s", 200>;
+defm "" : SIMDConvert<I64x2, I32x4, int_wasm_extend_low_unsigned,
+                      "extend_low_i32x4_u", 201>;
+defm "" : SIMDConvert<I64x2, I32x4, int_wasm_extend_high_unsigned,
+                      "extend_high_i32x4_u", 202>;
 
 // Narrowing operations
 multiclass SIMDNarrow<Vec vec, bits<32> baseInst> {
   defvar name = vec.split.prefix#".narrow_"#vec.prefix;
   defm NARROW_S_#vec.split :
     SIMD_I<(outs V128:$dst), (ins V128:$low, V128:$high), (outs), (ins),
            [(set (vec.split.vt V128:$dst), (vec.split.vt (int_wasm_narrow_signed
              (vec.vt V128:$low), (vec.vt V128:$high))))],
foreach t2 = !foldl(
   acc, cur, !if(!eq(!cast<string>(t1), !cast<string>(cur)),
     acc, !listconcat(acc, [cur])
   )
 ) in
 def : Pat<(t1 (bitconvert (t2 V128:$v))), (t1 V128:$v)>;
 
 // Extended pairwise addition
 defm "" : SIMDConvert<I16x8, I8x16, int_wasm_extadd_pairwise_signed,
-                      "extadd_pairwise_i8x16_s", 0xc2>;
+                      "extadd_pairwise_i8x16_s", 0x7c>;
 defm "" : SIMDConvert<I16x8, I8x16, int_wasm_extadd_pairwise_unsigned,
-                      "extadd_pairwise_i8x16_u", 0xc3>;
+                      "extadd_pairwise_i8x16_u", 0x7d>;
 defm "" : SIMDConvert<I32x4, I16x8, int_wasm_extadd_pairwise_signed,
-                      "extadd_pairwise_i16x8_s", 0xa5>;
+                      "extadd_pairwise_i16x8_s", 0x7e>;
 defm "" : SIMDConvert<I32x4, I16x8, int_wasm_extadd_pairwise_unsigned,
-                      "extadd_pairwise_i16x8_u", 0xa6>;
+                      "extadd_pairwise_i16x8_u", 0x7f>;
 
 // Prototype f64x2 conversions
-defm "" : SIMDConvert<F64x2, I32x4, int_wasm_convert_low_signed,
-                      "convert_low_i32x4_s", 0x53>;
-defm "" : SIMDConvert<F64x2, I32x4, int_wasm_convert_low_unsigned,
-                      "convert_low_i32x4_u", 0x54>;
-defm "" : SIMDConvert<I32x4, F64x2, int_wasm_trunc_saturate_zero_signed,
-                      "trunc_sat_zero_f64x2_s", 0x55>;
-defm "" : SIMDConvert<I32x4, F64x2, int_wasm_trunc_saturate_zero_unsigned,
-                      "trunc_sat_zero_f64x2_u", 0x56>;
 defm "" : SIMDConvert<F32x4, F64x2, int_wasm_demote_zero,
-                      "demote_zero_f64x2", 0x57>;
+                      "demote_zero_f64x2", 0x5e>;
 defm "" : SIMDConvert<F64x2, F32x4, int_wasm_promote_low,
-                      "promote_low_f32x4", 0x69>;
+                      "promote_low_f32x4", 0x5f>;
+defm "" : SIMDConvert<I32x4, F64x2, int_wasm_trunc_sat_zero_signed,
+                      "trunc_sat_zero_f64x2_s", 0xfc>;
+defm "" : SIMDConvert<I32x4, F64x2, int_wasm_trunc_sat_zero_unsigned,
+                      "trunc_sat_zero_f64x2_u", 0xfd>;
+defm "" : SIMDConvert<F64x2, I32x4, int_wasm_convert_low_signed,
+                      "convert_low_i32x4_s", 0xfe>;
+defm "" : SIMDConvert<F64x2, I32x4, int_wasm_convert_low_unsigned,
+                      "convert_low_i32x4_u", 0xff>;
 
 //===----------------------------------------------------------------------===//
 // Saturating Rounding Q-Format Multiplication
 //===----------------------------------------------------------------------===//
 
 defm Q15MULR_SAT_S :
-  SIMDBinary<I16x8, int_wasm_q15mulr_saturate_signed, "q15mulr_sat_s", 156>;
+  SIMDBinary<I16x8, int_wasm_q15mulr_sat_signed, "q15mulr_sat_s", 0x82>;

llvm/test/CodeGen/WebAssembly/simd-extending.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mattr=+simd128 | FileCheck %s
 
-;; Test that SIMD widening operations can be successfully selected
+;; Test that SIMD extending operations can be successfully selected
 
 target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
 target triple = "wasm32-unknown-unknown"
 
-define <8 x i16> @widen_low_i8x16_s(<16 x i8> %v) {
-; CHECK-LABEL: widen_low_i8x16_s:
-; CHECK:         .functype widen_low_i8x16_s (v128) -> (v128)
+define <8 x i16> @extend_low_i8x16_s(<16 x i8> %v) {
+; CHECK-LABEL: extend_low_i8x16_s:
+; CHECK:         .functype extend_low_i8x16_s (v128) -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
-; CHECK-NEXT:    i16x8.widen_low_i8x16_s
+; CHECK-NEXT:    i16x8.extend_low_i8x16_s
 ; CHECK-NEXT:    # fallthrough-return
   %low = shufflevector <16 x i8> %v, <16 x i8> undef,
            <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
-  %widened = sext <8 x i8> %low to <8 x i16>
-  ret <8 x i16> %widened
+  %extended = sext <8 x i8> %low to <8 x i16>
+  ret <8 x i16> %extended
 }
 
-define <8 x i16> @widen_low_i8x16_u(<16 x i8> %v) {
-; CHECK-LABEL: widen_low_i8x16_u:
-; CHECK:         .functype widen_low_i8x16_u (v128) -> (v128)
+define <8 x i16> @extend_low_i8x16_u(<16 x i8> %v) {
+; CHECK-LABEL: extend_low_i8x16_u:
+; CHECK:         .functype extend_low_i8x16_u (v128) -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
-; CHECK-NEXT:    i16x8.widen_low_i8x16_u
+; CHECK-NEXT:    i16x8.extend_low_i8x16_u
 ; CHECK-NEXT:    # fallthrough-return
   %low = shufflevector <16 x i8> %v, <16 x i8> undef,
            <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
-  %widened = zext <8 x i8> %low to <8 x i16>
-  ret <8 x i16> %widened
+  %extended = zext <8 x i8> %low to <8 x i16>
+  ret <8 x i16> %extended
 }
 
-define <8 x i16> @widen_high_i8x16_s(<16 x i8> %v) {
-; CHECK-LABEL: widen_high_i8x16_s:
-; CHECK:         .functype widen_high_i8x16_s (v128) -> (v128)
+define <8 x i16> @extend_high_i8x16_s(<16 x i8> %v) {
+; CHECK-LABEL: extend_high_i8x16_s:
+; CHECK:         .functype extend_high_i8x16_s (v128) -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
-; CHECK-NEXT:    i16x8.widen_high_i8x16_s
+; CHECK-NEXT:    i16x8.extend_high_i8x16_s
 ; CHECK-NEXT:    # fallthrough-return
   %low = shufflevector <16 x i8> %v, <16 x i8> undef,
            <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
-  %widened = sext <8 x i8> %low to <8 x i16>
-  ret <8 x i16> %widened
+  %extended = sext <8 x i8> %low to <8 x i16>
+  ret <8 x i16> %extended
 }
 
-define <8 x i16> @widen_high_i8x16_u(<16 x i8> %v) {
-; CHECK-LABEL: widen_high_i8x16_u:
-; CHECK:         .functype widen_high_i8x16_u (v128) -> (v128)
+define <8 x i16> @extend_high_i8x16_u(<16 x i8> %v) {
+; CHECK-LABEL: extend_high_i8x16_u:
+; CHECK:         .functype extend_high_i8x16_u (v128) -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
-; CHECK-NEXT:    i16x8.widen_high_i8x16_u
+; CHECK-NEXT:    i16x8.extend_high_i8x16_u
 ; CHECK-NEXT:    # fallthrough-return
   %low = shufflevector <16 x i8> %v, <16 x i8> undef,
            <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
-  %widened = zext <8 x i8> %low to <8 x i16>
-  ret <8 x i16> %widened
+  %extended = zext <8 x i8> %low to <8 x i16>
+  ret <8 x i16> %extended
 }
 
-define <4 x i32> @widen_low_i16x8_s(<8 x i16> %v) {
-; CHECK-LABEL: widen_low_i16x8_s:
-; CHECK:         .functype widen_low_i16x8_s (v128) -> (v128)
+define <4 x i32> @extend_low_i16x8_s(<8 x i16> %v) {
+; CHECK-LABEL: extend_low_i16x8_s:
+; CHECK:         .functype extend_low_i16x8_s (v128) -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
-; CHECK-NEXT:    i32x4.widen_low_i16x8_s
+; CHECK-NEXT:    i32x4.extend_low_i16x8_s
 ; CHECK-NEXT:    # fallthrough-return
   %low = shufflevector <8 x i16> %v, <8 x i16> undef,
            <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-  %widened = sext <4 x i16> %low to <4 x i32>
-  ret <4 x i32> %widened
+  %extended = sext <4 x i16> %low to <4 x i32>
+  ret <4 x i32> %extended
 }
 
-define <4 x i32> @widen_low_i16x8_u(<8 x i16> %v) {
-; CHECK-LABEL: widen_low_i16x8_u:
-; CHECK:         .functype widen_low_i16x8_u (v128) -> (v128)
+define <4 x i32> @extend_low_i16x8_u(<8 x i16> %v) {
+; CHECK-LABEL: extend_low_i16x8_u:
+; CHECK:         .functype extend_low_i16x8_u (v128) -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
-; CHECK-NEXT:    i32x4.widen_low_i16x8_u
+; CHECK-NEXT:    i32x4.extend_low_i16x8_u
 ; CHECK-NEXT:    # fallthrough-return
   %low = shufflevector <8 x i16> %v, <8 x i16> undef,
            <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-  %widened = zext <4 x i16> %low to <4 x i32>
-  ret <4 x i32> %widened
+  %extended = zext <4 x i16> %low to <4 x i32>
+  ret <4 x i32> %extended
 }
 
-define <4 x i32> @widen_high_i16x8_s(<8 x i16> %v) {
-; CHECK-LABEL: widen_high_i16x8_s:
-; CHECK:         .functype widen_high_i16x8_s (v128) -> (v128)
+define <4 x i32> @extend_high_i16x8_s(<8 x i16> %v) {
+; CHECK-LABEL: extend_high_i16x8_s:
+; CHECK:         .functype extend_high_i16x8_s (v128) -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
-; CHECK-NEXT:    i32x4.widen_high_i16x8_s
+; CHECK-NEXT:    i32x4.extend_high_i16x8_s
 ; CHECK-NEXT:    # fallthrough-return
   %low = shufflevector <8 x i16> %v, <8 x i16> undef,
            <4 x i32> <i32 4, i32 5, i32 6, i32 7>
-  %widened = sext <4 x i16> %low to <4 x i32>
-  ret <4 x i32> %widened
+  %extended = sext <4 x i16> %low to <4 x i32>
+  ret <4 x i32> %extended
 }
 
-define <4 x i32> @widen_high_i16x8_u(<8 x i16> %v) {
-; CHECK-LABEL: widen_high_i16x8_u:
-; CHECK:         .functype widen_high_i16x8_u (v128) -> (v128)
+define <4 x i32> @extend_high_i16x8_u(<8 x i16> %v) {
+; CHECK-LABEL: extend_high_i16x8_u:
+; CHECK:         .functype extend_high_i16x8_u (v128) -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
-; CHECK-NEXT:    i32x4.widen_high_i16x8_u
+; CHECK-NEXT:    i32x4.extend_high_i16x8_u
 ; CHECK-NEXT:    # fallthrough-return
   %low = shufflevector <8 x i16> %v, <8 x i16> undef,
            <4 x i32> <i32 4, i32 5, i32 6, i32 7>
-  %widened = zext <4 x i16> %low to <4 x i32>
-  ret <4 x i32> %widened
+  %extended = zext <4 x i16> %low to <4 x i32>
+  ret <4 x i32> %extended
 }
 
 ;; Also test that similar patterns with offsets not corresponding to
 ;; the low or high half are correctly expanded.
 
-define <8 x i16> @widen_lowish_i8x16_s(<16 x i8> %v) {
-; CHECK-LABEL: widen_lowish_i8x16_s:
-; CHECK:         .functype widen_lowish_i8x16_s (v128) -> (v128)
+define <8 x i16> @extend_lowish_i8x16_s(<16 x i8> %v) {
+; CHECK-LABEL: extend_lowish_i8x16_s:
+; CHECK:         .functype extend_lowish_i8x16_s (v128) -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    i8x16.extract_lane_u 1
 ; CHECK-NEXT:    i16x8.splat
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    i8x16.extract_lane_u 2
 ; CHECK-NEXT:    i16x8.replace_lane 1
 ; CHECK-NEXT:    local.get 0

 ; CHECK-NEXT:    i16x8.replace_lane 7
 ; CHECK-NEXT:    i32.const 8
 ; CHECK-NEXT:    i16x8.shl
 ; CHECK-NEXT:    i32.const 8
 ; CHECK-NEXT:    i16x8.shr_s
 ; CHECK-NEXT:    # fallthrough-return
   %lowish = shufflevector <16 x i8> %v, <16 x i8> undef,
            <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>
-  %widened = sext <8 x i8> %lowish to <8 x i16>
-  ret <8 x i16> %widened
+  %extended = sext <8 x i8> %lowish to <8 x i16>
+  ret <8 x i16> %extended
 }
 
-define <4 x i32> @widen_lowish_i16x8_s(<8 x i16> %v) {
-; CHECK-LABEL: widen_lowish_i16x8_s:
-; CHECK:         .functype widen_lowish_i16x8_s (v128) -> (v128)
+define <4 x i32> @extend_lowish_i16x8_s(<8 x i16> %v) {
+; CHECK-LABEL: extend_lowish_i16x8_s:
+; CHECK:         .functype extend_lowish_i16x8_s (v128) -> (v128)
 ; CHECK-NEXT:  # %bb.0:
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    i16x8.extract_lane_u 1
 ; CHECK-NEXT:    i32x4.splat
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    i16x8.extract_lane_u 2
 ; CHECK-NEXT:    i32x4.replace_lane 1
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    i16x8.extract_lane_u 3
 ; CHECK-NEXT:    i32x4.replace_lane 2
 ; CHECK-NEXT:    local.get 0
 ; CHECK-NEXT:    i16x8.extract_lane_u 4
 ; CHECK-NEXT:    i32x4.replace_lane 3
 ; CHECK-NEXT:    i32.const 16
 ; CHECK-NEXT:    i32x4.shl
 ; CHECK-NEXT:    i32.const 16
 ; CHECK-NEXT:    i32x4.shr_s
 ; CHECK-NEXT:    # fallthrough-return
   %lowish = shufflevector <8 x i16> %v, <8 x i16> undef,
            <4 x i32> <i32 1, i32 2, i32 3, i32 4>
-  %widened = sext <4 x i16> %lowish to <4 x i32>
-  ret <4 x i32> %widened
+  %extended = sext <4 x i16> %lowish to <4 x i32>
+  ret <4 x i32> %extended
 }

llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll

 declare <16 x i8> @llvm.wasm.swizzle(<16 x i8>, <16 x i8>)
 define <16 x i8> @swizzle_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = call <16 x i8> @llvm.wasm.swizzle(<16 x i8> %x, <16 x i8> %y)
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: add_sat_s_v16i8:
 ; CHECK-NEXT: .functype add_sat_s_v16i8 (v128, v128) -> (v128){{$}}
-; CHECK-NEXT: i8x16.add_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: i8x16.add_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8>, <16 x i8>)
 define <16 x i8> @add_sat_s_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: add_sat_u_v16i8:
 ; CHECK-NEXT: .functype add_sat_u_v16i8 (v128, v128) -> (v128){{$}}
-; CHECK-NEXT: i8x16.add_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: i8x16.add_sat_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>)
 define <16 x i8> @add_sat_u_v16i8(<16 x i8> %x, <16 x i8> %y) {
   %a = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: sub_sat_s_v16i8:
 ; CHECK-NEXT: .functype sub_sat_s_v16i8 (v128, v128) -> (v128){{$}}
-; CHECK-NEXT: i8x16.sub_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: i8x16.sub_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <16 x i8> @llvm.wasm.sub.saturate.signed.v16i8(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.wasm.sub.sat.signed.v16i8(<16 x i8>, <16 x i8>)
 define <16 x i8> @sub_sat_s_v16i8(<16 x i8> %x, <16 x i8> %y) {
-  %a = call <16 x i8> @llvm.wasm.sub.saturate.signed.v16i8(
+  %a = call <16 x i8> @llvm.wasm.sub.sat.signed.v16i8(
     <16 x i8> %x, <16 x i8> %y
   )
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: sub_sat_u_v16i8:
 ; CHECK-NEXT: .functype sub_sat_u_v16i8 (v128, v128) -> (v128){{$}}
-; CHECK-NEXT: i8x16.sub_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: i8x16.sub_sat_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <16 x i8> @llvm.wasm.sub.saturate.unsigned.v16i8(<16 x i8>, <16 x i8>)
+declare <16 x i8> @llvm.wasm.sub.sat.unsigned.v16i8(<16 x i8>, <16 x i8>)
 define <16 x i8> @sub_sat_u_v16i8(<16 x i8> %x, <16 x i8> %y) {
-  %a = call <16 x i8> @llvm.wasm.sub.saturate.unsigned.v16i8(
+  %a = call <16 x i8> @llvm.wasm.sub.sat.unsigned.v16i8(
     <16 x i8> %x, <16 x i8> %y
   )
   ret <16 x i8> %a
 }
 
 ; CHECK-LABEL: avgr_u_v16i8:
 ; CHECK-NEXT: .functype avgr_u_v16i8 (v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i8x16.avgr_u $push[[R:[0-9]+]]=, $0, $1{{$}}
define <16 x i8> @shuffle_undef_v16i8(<16 x i8> %x, <16 x i8> %y) {
   ret <16 x i8> %res
 }
 
 ; ==============================================================================
 ; 8 x i16
 ; ==============================================================================
 ; CHECK-LABEL: add_sat_s_v8i16:
 ; CHECK-NEXT: .functype add_sat_s_v8i16 (v128, v128) -> (v128){{$}}
-; CHECK-NEXT: i16x8.add_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: i16x8.add_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>)
 define <8 x i16> @add_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %a = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: add_sat_u_v8i16:
 ; CHECK-NEXT: .functype add_sat_u_v8i16 (v128, v128) -> (v128){{$}}
-; CHECK-NEXT: i16x8.add_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: i16x8.add_sat_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16>, <8 x i16>)
 define <8 x i16> @add_sat_u_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %a = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: sub_sat_s_v8i16:
 ; CHECK-NEXT: .functype sub_sat_s_v8i16 (v128, v128) -> (v128){{$}}
-; CHECK-NEXT: i16x8.sub_saturate_s $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: i16x8.sub_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <8 x i16> @llvm.wasm.sub.saturate.signed.v8i16(<8 x i16>, <8 x i16>)
+declare <8 x i16> @llvm.wasm.sub.sat.signed.v8i16(<8 x i16>, <8 x i16>)
 define <8 x i16> @sub_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) {
-  %a = call <8 x i16> @llvm.wasm.sub.saturate.signed.v8i16(
+  %a = call <8 x i16> @llvm.wasm.sub.sat.signed.v8i16(
     <8 x i16> %x, <8 x i16> %y
   )
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: sub_sat_u_v8i16:
 ; CHECK-NEXT: .functype sub_sat_u_v8i16 (v128, v128) -> (v128){{$}}
-; CHECK-NEXT: i16x8.sub_saturate_u $push[[R:[0-9]+]]=, $0, $1{{$}}
+; CHECK-NEXT: i16x8.sub_sat_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <8 x i16> @llvm.wasm.sub.saturate.unsigned.v8i16(<8 x i16>, <8 x i16>)
+declare <8 x i16> @llvm.wasm.sub.sat.unsigned.v8i16(<8 x i16>, <8 x i16>)
 define <8 x i16> @sub_sat_u_v8i16(<8 x i16> %x, <8 x i16> %y) {
-  %a = call <8 x i16> @llvm.wasm.sub.saturate.unsigned.v8i16(
+  %a = call <8 x i16> @llvm.wasm.sub.sat.unsigned.v8i16(
     <8 x i16> %x, <8 x i16> %y
   )
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: avgr_u_v8i16:
 ; CHECK-NEXT: .functype avgr_u_v8i16 (v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i16x8.avgr_u $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <8 x i16> @llvm.wasm.avgr.unsigned.v8i16(<8 x i16>, <8 x i16>)
 define <8 x i16> @avgr_u_v8i16(<8 x i16> %x, <8 x i16> %y) {
   %a = call <8 x i16> @llvm.wasm.avgr.unsigned.v8i16(<8 x i16> %x, <8 x i16> %y)
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: q15mulr_sat_s_v8i16:
 ; CHECK-NEXT: .functype q15mulr_sat_s_v8i16 (v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i16x8.q15mulr_sat_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <8 x i16> @llvm.wasm.q15mulr.saturate.signed(<8 x i16>, <8 x i16>)
+declare <8 x i16> @llvm.wasm.q15mulr.sat.signed(<8 x i16>, <8 x i16>)
 define <8 x i16> @q15mulr_sat_s_v8i16(<8 x i16> %x, <8 x i16> %y) {
-  %a = call <8 x i16> @llvm.wasm.q15mulr.saturate.signed(<8 x i16> %x,
+  %a = call <8 x i16> @llvm.wasm.q15mulr.sat.signed(<8 x i16> %x,
                                                          <8 x i16> %y)
   ret <8 x i16> %a
 }
 
 ; CHECK-LABEL: extmul_low_s_v8i16:
 ; CHECK-NEXT: .functype extmul_low_s_v8i16 (v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i16x8.extmul_low_i8x16_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
define <4 x i32> @trunc_sat_u_v4i32(<4 x float> %x) {
   %a = call <4 x i32> @llvm.wasm.trunc.saturate.unsigned.v4i32.v4f32(<4 x float> %x)
   ret <4 x i32> %a
 }
 
 ; CHECK-LABEL: trunc_sat_zero_signed_v4i32:
 ; CHECK-NEXT: .functype trunc_sat_zero_signed_v4i32 (v128) -> (v128){{$}}
 ; CHECK-NEXT: i32x4.trunc_sat_zero_f64x2_s $push[[R:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <4 x i32> @llvm.wasm.trunc.saturate.zero.signed(<2 x double>)
+declare <4 x i32> @llvm.wasm.trunc.sat.zero.signed(<2 x double>)
 define <4 x i32> @trunc_sat_zero_signed_v4i32(<2 x double> %a) {
-  %v = call <4 x i32> @llvm.wasm.trunc.saturate.zero.signed(<2 x double> %a)
+  %v = call <4 x i32> @llvm.wasm.trunc.sat.zero.signed(<2 x double> %a)
   ret <4 x i32> %v
 }
 
 ; CHECK-LABEL: trunc_sat_zero_unsigned_v4i32:
 ; CHECK-NEXT: .functype trunc_sat_zero_unsigned_v4i32 (v128) -> (v128){{$}}
 ; CHECK-NEXT: i32x4.trunc_sat_zero_f64x2_u $push[[R:[0-9]+]]=, $0{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <4 x i32> @llvm.wasm.trunc.saturate.zero.unsigned(<2 x double>)
+declare <4 x i32> @llvm.wasm.trunc.sat.zero.unsigned(<2 x double>)
 define <4 x i32> @trunc_sat_zero_unsigned_v4i32(<2 x double> %a) {
-  %v = call <4 x i32> @llvm.wasm.trunc.saturate.zero.unsigned(<2 x double> %a)
+  %v = call <4 x i32> @llvm.wasm.trunc.sat.zero.unsigned(<2 x double> %a)
   ret <4 x i32> %v
 }
 
 ; ==============================================================================
 ; 2 x i64
 ; ==============================================================================
 ; CHECK-LABEL: eq_v2i64:
 ; CHECK-NEXT: .functype eq_v2i64 (v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i64x2.eq $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x i64> @llvm.wasm.eq(<2 x i64>, <2 x i64>)
 define <2 x i64> @eq_v2i64(<2 x i64> %x, <2 x i64> %y) {
   %a = call <2 x i64> @llvm.wasm.eq(<2 x i64> %x, <2 x i64> %y)
   ret <2 x i64> %a
 }
 
-; CHECK-LABEL: widen_low_s_v2i64:
-; CHECK-NEXT: .functype widen_low_s_v2i64 (v128) -> (v128){{$}}
-; CHECK-NEXT: i64x2.widen_low_i32x4_s $push[[R:[0-9]+]]=, $0{{$}}
-; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <2 x i64> @llvm.wasm.widen.low.signed(<4 x i32>)
-define <2 x i64> @widen_low_s_v2i64(<4 x i32> %x) {
-  %a = call <2 x i64> @llvm.wasm.widen.low.signed(<4 x i32> %x)
+; CHECK-LABEL: extend_low_s_v2i64:
+; CHECK-NEXT: .functype extend_low_s_v2i64 (v128) -> (v128){{$}}
+; CHECK-NEXT: i64x2.extend_low_i32x4_s $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+declare <2 x i64> @llvm.wasm.extend.low.signed(<4 x i32>)
+define <2 x i64> @extend_low_s_v2i64(<4 x i32> %x) {
+  %a = call <2 x i64> @llvm.wasm.extend.low.signed(<4 x i32> %x)
   ret <2 x i64> %a
 }
 
-; CHECK-LABEL: widen_high_s_v2i64:
-; CHECK-NEXT: .functype widen_high_s_v2i64 (v128) -> (v128){{$}}
-; CHECK-NEXT: i64x2.widen_high_i32x4_s $push[[R:[0-9]+]]=, $0{{$}}
-; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <2 x i64> @llvm.wasm.widen.high.signed(<4 x i32>)
-define <2 x i64> @widen_high_s_v2i64(<4 x i32> %x) {
-  %a = call <2 x i64> @llvm.wasm.widen.high.signed(<4 x i32> %x)
+; CHECK-LABEL: extend_high_s_v2i64:
+; CHECK-NEXT: .functype extend_high_s_v2i64 (v128) -> (v128){{$}}
+; CHECK-NEXT: i64x2.extend_high_i32x4_s $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+declare <2 x i64> @llvm.wasm.extend.high.signed(<4 x i32>)
+define <2 x i64> @extend_high_s_v2i64(<4 x i32> %x) {
+  %a = call <2 x i64> @llvm.wasm.extend.high.signed(<4 x i32> %x)
   ret <2 x i64> %a
 }
 
-; CHECK-LABEL: widen_low_u_v2i64:
-; CHECK-NEXT: .functype widen_low_u_v2i64 (v128) -> (v128){{$}}
-; CHECK-NEXT: i64x2.widen_low_i32x4_u $push[[R:[0-9]+]]=, $0{{$}}
-; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <2 x i64> @llvm.wasm.widen.low.unsigned(<4 x i32>)
-define <2 x i64> @widen_low_u_v2i64(<4 x i32> %x) {
-  %a = call <2 x i64> @llvm.wasm.widen.low.unsigned(<4 x i32> %x)
+; CHECK-LABEL: extend_low_u_v2i64:
+; CHECK-NEXT: .functype extend_low_u_v2i64 (v128) -> (v128){{$}}
+; CHECK-NEXT: i64x2.extend_low_i32x4_u $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+declare <2 x i64> @llvm.wasm.extend.low.unsigned(<4 x i32>)
+define <2 x i64> @extend_low_u_v2i64(<4 x i32> %x) {
+  %a = call <2 x i64> @llvm.wasm.extend.low.unsigned(<4 x i32> %x)
   ret <2 x i64> %a
 }
 
-; CHECK-LABEL: widen_high_u_v2i64:
-; CHECK-NEXT: .functype widen_high_u_v2i64 (v128) -> (v128){{$}}
-; CHECK-NEXT: i64x2.widen_high_i32x4_u $push[[R:[0-9]+]]=, $0{{$}}
-; CHECK-NEXT: return $pop[[R]]{{$}}
-declare <2 x i64> @llvm.wasm.widen.high.unsigned(<4 x i32>)
-define <2 x i64> @widen_high_u_v2i64(<4 x i32> %x) {
-  %a = call <2 x i64> @llvm.wasm.widen.high.unsigned(<4 x i32> %x)
+; CHECK-LABEL: extend_high_u_v2i64:
+; CHECK-NEXT: .functype extend_high_u_v2i64 (v128) -> (v128){{$}}
+; CHECK-NEXT: i64x2.extend_high_i32x4_u $push[[R:[0-9]+]]=, $0{{$}}
+; CHECK-NEXT: return $pop[[R]]{{$}}
+declare <2 x i64> @llvm.wasm.extend.high.unsigned(<4 x i32>)
+define <2 x i64> @extend_high_u_v2i64(<4 x i32> %x) {
+  %a = call <2 x i64> @llvm.wasm.extend.high.unsigned(<4 x i32> %x)
   ret <2 x i64> %a
 }
 
 ; CHECK-LABEL: extmul_low_s_v2i64:
 ; CHECK-NEXT: .functype extmul_low_s_v2i64 (v128, v128) -> (v128){{$}}
 ; CHECK-NEXT: i64x2.extmul_low_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}}
 ; CHECK-NEXT: return $pop[[R]]{{$}}
 declare <2 x i64> @llvm.wasm.extmul.low.signed.v2i64(<4 x i32>, <4 x i32>)

llvm/test/MC/WebAssembly/simd-encodings.s

main:
     v128.or
 
     # CHECK: v128.xor # encoding: [0xfd,0x51]
     v128.xor
 
     # CHECK: v128.bitselect # encoding: [0xfd,0x52]
     v128.bitselect
 
-    # CHECK: v128.load8_lane 32, 1 # encoding: [0xfd,0x58,0x00,0x20,0x01]
+    # TODO: v128.any_true # encoding: [0xfd,0x53]
+
+    # CHECK: v128.load8_lane 32, 1 # encoding: [0xfd,0x54,0x00,0x20,0x01]
     v128.load8_lane 32, 1
 
-    # CHECK: v128.load16_lane 32, 1 # encoding: [0xfd,0x59,0x01,0x20,0x01]
+    # CHECK: v128.load16_lane 32, 1 # encoding: [0xfd,0x55,0x01,0x20,0x01]
     v128.load16_lane 32, 1
 
-    # CHECK: v128.load32_lane 32, 1 # encoding: [0xfd,0x5a,0x02,0x20,0x01]
+    # CHECK: v128.load32_lane 32, 1 # encoding: [0xfd,0x56,0x02,0x20,0x01]
     v128.load32_lane 32, 1
 
-    # CHECK: v128.load64_lane 32, 1 # encoding: [0xfd,0x5b,0x03,0x20,0x01]
+    # CHECK: v128.load64_lane 32, 1 # encoding: [0xfd,0x57,0x03,0x20,0x01]
     v128.load64_lane 32, 1
 
-    # CHECK: v128.store8_lane 32, 1 # encoding: [0xfd,0x5c,0x00,0x20,0x01]
+    # CHECK: v128.store8_lane 32, 1 # encoding: [0xfd,0x58,0x00,0x20,0x01]
     v128.store8_lane 32, 1
 
-    # CHECK: v128.store16_lane 32, 1 # encoding: [0xfd,0x5d,0x01,0x20,0x01]
+    # CHECK: v128.store16_lane 32, 1 # encoding: [0xfd,0x59,0x01,0x20,0x01]
     v128.store16_lane 32, 1
 
-    # CHECK: v128.store32_lane 32, 1 # encoding: [0xfd,0x5e,0x02,0x20,0x01]
+    # CHECK: v128.store32_lane 32, 1 # encoding: [0xfd,0x5a,0x02,0x20,0x01]
     v128.store32_lane 32, 1
 
-    # CHECK: v128.store64_lane 32, 1 # encoding: [0xfd,0x5f,0x03,0x20,0x01]
+    # CHECK: v128.store64_lane 32, 1 # encoding: [0xfd,0x5b,0x03,0x20,0x01]
     v128.store64_lane 32, 1
 
+    # CHECK: v128.load32_zero 32 # encoding: [0xfd,0x5c,0x02,0x20]
+    v128.load32_zero 32
+
+    # CHECK: v128.load64_zero 32 # encoding: [0xfd,0x5d,0x03,0x20]
+    v128.load64_zero 32
+
+    # CHECK: f32x4.demote_zero_f64x2 # encoding: [0xfd,0x5e]
+    f32x4.demote_zero_f64x2
+
+    # CHECK: f64x2.promote_low_f32x4 # encoding: [0xfd,0x5f]
+    f64x2.promote_low_f32x4
+
     # CHECK: i8x16.abs # encoding: [0xfd,0x60]
     i8x16.abs
 
     # CHECK: i8x16.neg # encoding: [0xfd,0x61]
     i8x16.neg
 
-    # CHECK: i8x16.any_true # encoding: [0xfd,0x62]
-    i8x16.any_true
+    # TODO: i8x16.popcnt # encoding: [0xfd,0x62]
 
     # CHECK: i8x16.all_true # encoding: [0xfd,0x63]
     i8x16.all_true
 
     # CHECK: i8x16.bitmask # encoding: [0xfd,0x64]
     i8x16.bitmask
 
     # CHECK: i8x16.narrow_i16x8_s # encoding: [0xfd,0x65]
     i8x16.narrow_i16x8_s
 
     # CHECK: i8x16.narrow_i16x8_u # encoding: [0xfd,0x66]
     i8x16.narrow_i16x8_u
 
+    # CHECK: f32x4.ceil # encoding: [0xfd,0x67]
+    f32x4.ceil
+
+    # CHECK: f32x4.floor # encoding: [0xfd,0x68]
+    f32x4.floor
+
+    # CHECK: f32x4.trunc # encoding: [0xfd,0x69]
+    f32x4.trunc
+
+    # CHECK: f32x4.nearest # encoding: [0xfd,0x6a]
+    f32x4.nearest
+
     # CHECK: i8x16.shl # encoding: [0xfd,0x6b]
     i8x16.shl
 
     # CHECK: i8x16.shr_s # encoding: [0xfd,0x6c]
     i8x16.shr_s
 
     # CHECK: i8x16.shr_u # encoding: [0xfd,0x6d]
     i8x16.shr_u
 
     # CHECK: i8x16.add # encoding: [0xfd,0x6e]
     i8x16.add
 
-    # CHECK: i8x16.add_saturate_s # encoding: [0xfd,0x6f]
-    i8x16.add_saturate_s
+    # CHECK: i8x16.add_sat_s # encoding: [0xfd,0x6f]
+    i8x16.add_sat_s
 
-    # CHECK: i8x16.add_saturate_u # encoding: [0xfd,0x70]
-    i8x16.add_saturate_u
+    # CHECK: i8x16.add_sat_u # encoding: [0xfd,0x70]
+    i8x16.add_sat_u
 
     # CHECK: i8x16.sub # encoding: [0xfd,0x71]
     i8x16.sub
 
-    # CHECK: i8x16.sub_saturate_s # encoding: [0xfd,0x72]
-    i8x16.sub_saturate_s
+    # CHECK: i8x16.sub_sat_s # encoding: [0xfd,0x72]
+    i8x16.sub_sat_s
 
-    # CHECK: i8x16.sub_saturate_u # encoding: [0xfd,0x73]
-    i8x16.sub_saturate_u
+    # CHECK: i8x16.sub_sat_u # encoding: [0xfd,0x73]
+    i8x16.sub_sat_u
+
+    # CHECK: f64x2.ceil # encoding: [0xfd,0x74]
+    f64x2.ceil
+
+    # CHECK: f64x2.floor # encoding: [0xfd,0x75]
+    f64x2.floor
 
     # CHECK: i8x16.min_s # encoding: [0xfd,0x76]
     i8x16.min_s
 
     # CHECK: i8x16.min_u # encoding: [0xfd,0x77]
     i8x16.min_u
 
     # CHECK: i8x16.max_s # encoding: [0xfd,0x78]
     i8x16.max_s
 
     # CHECK: i8x16.max_u # encoding: [0xfd,0x79]
     i8x16.max_u
 
+    # CHECK: f64x2.trunc # encoding: [0xfd,0x7a]
+    f64x2.trunc
+
     # CHECK: i8x16.avgr_u # encoding: [0xfd,0x7b]
     i8x16.avgr_u
 
-    # CHECK: i8x16.popcnt # encoding: [0xfd,0x7c]
-    i8x16.popcnt
+    # CHECK: i16x8.extadd_pairwise_i8x16_s # encoding: [0xfd,0x7c]
+    i16x8.extadd_pairwise_i8x16_s
+
+    # CHECK: i16x8.extadd_pairwise_i8x16_u # encoding: [0xfd,0x7d]
+    i16x8.extadd_pairwise_i8x16_u
+
+    # CHECK: i32x4.extadd_pairwise_i16x8_s # encoding: [0xfd,0x7e]
+    i32x4.extadd_pairwise_i16x8_s
+
+    # CHECK: i32x4.extadd_pairwise_i16x8_u # encoding: [0xfd,0x7f]
+    i32x4.extadd_pairwise_i16x8_u
 
     # CHECK: i16x8.abs # encoding: [0xfd,0x80,0x01]
     i16x8.abs
 
     # CHECK: i16x8.neg # encoding: [0xfd,0x81,0x01]
     i16x8.neg
 
-    # CHECK: i16x8.any_true # encoding: [0xfd,0x82,0x01]
-    i16x8.any_true
+    # CHECK: i16x8.q15mulr_sat_s # encoding: [0xfd,0x82,0x01]
+    i16x8.q15mulr_sat_s
 
     # CHECK: i16x8.all_true # encoding: [0xfd,0x83,0x01]
     i16x8.all_true
 
     # CHECK: i16x8.bitmask # encoding: [0xfd,0x84,0x01]
     i16x8.bitmask
 
     # CHECK: i16x8.narrow_i32x4_s # encoding: [0xfd,0x85,0x01]
     i16x8.narrow_i32x4_s
 
     # CHECK: i16x8.narrow_i32x4_u # encoding: [0xfd,0x86,0x01]
     i16x8.narrow_i32x4_u
 
-    # CHECK: i16x8.widen_low_i8x16_s # encoding: [0xfd,0x87,0x01]
-    i16x8.widen_low_i8x16_s
+    # CHECK: i16x8.extend_low_i8x16_s # encoding: [0xfd,0x87,0x01]
+    i16x8.extend_low_i8x16_s
 
-    # CHECK: i16x8.widen_high_i8x16_s # encoding: [0xfd,0x88,0x01]
-    i16x8.widen_high_i8x16_s
+    # CHECK: i16x8.extend_high_i8x16_s # encoding: [0xfd,0x88,0x01]
+    i16x8.extend_high_i8x16_s
 
-    # CHECK: i16x8.widen_low_i8x16_u # encoding: [0xfd,0x89,0x01]
-    i16x8.widen_low_i8x16_u
+    # CHECK: i16x8.extend_low_i8x16_u # encoding: [0xfd,0x89,0x01]
+    i16x8.extend_low_i8x16_u
 
-    # CHECK: i16x8.widen_high_i8x16_u # encoding: [0xfd,0x8a,0x01]
-    i16x8.widen_high_i8x16_u
+    # CHECK: i16x8.extend_high_i8x16_u # encoding: [0xfd,0x8a,0x01]
+    i16x8.extend_high_i8x16_u
 
     # CHECK: i16x8.shl # encoding: [0xfd,0x8b,0x01]
     i16x8.shl
 
     # CHECK: i16x8.shr_s # encoding: [0xfd,0x8c,0x01]
     i16x8.shr_s
 
     # CHECK: i16x8.shr_u # encoding: [0xfd,0x8d,0x01]
     i16x8.shr_u
 
     # CHECK: i16x8.add # encoding: [0xfd,0x8e,0x01]
     i16x8.add
 
-    # CHECK: i16x8.add_saturate_s # encoding: [0xfd,0x8f,0x01]
-    i16x8.add_saturate_s
+    # CHECK: i16x8.add_sat_s # encoding: [0xfd,0x8f,0x01]
+    i16x8.add_sat_s
 
-    # CHECK: i16x8.add_saturate_u # encoding: [0xfd,0x90,0x01]
-    i16x8.add_saturate_u
+    # CHECK: i16x8.add_sat_u # encoding: [0xfd,0x90,0x01]
+    i16x8.add_sat_u
 
     # CHECK: i16x8.sub # encoding: [0xfd,0x91,0x01]
     i16x8.sub
 
-    # CHECK: i16x8.sub_saturate_s # encoding: [0xfd,0x92,0x01]
-    i16x8.sub_saturate_s
+    # CHECK: i16x8.sub_sat_s # encoding: [0xfd,0x92,0x01]
+    i16x8.sub_sat_s
 
-    # CHECK: i16x8.sub_saturate_u # encoding: [0xfd,0x93,0x01]
-    i16x8.sub_saturate_u
+    # CHECK: i16x8.sub_sat_u # encoding: [0xfd,0x93,0x01]
+    i16x8.sub_sat_u
+
+    # CHECK: f64x2.nearest # encoding: [0xfd,0x94,0x01]
+    f64x2.nearest
 
     # CHECK: i16x8.mul # encoding: [0xfd,0x95,0x01]
     i16x8.mul
 
     # CHECK: i16x8.min_s # encoding: [0xfd,0x96,0x01]
     i16x8.min_s
 
     # CHECK: i16x8.min_u # encoding: [0xfd,0x97,0x01]
     i16x8.min_u
 
     # CHECK: i16x8.max_s # encoding: [0xfd,0x98,0x01]
     i16x8.max_s
 
     # CHECK: i16x8.max_u # encoding: [0xfd,0x99,0x01]
     i16x8.max_u
 
+    # 0x0a unused
+
     # CHECK: i16x8.avgr_u # encoding: [0xfd,0x9b,0x01]
     i16x8.avgr_u
 
-    # CHECK: i16x8.q15mulr_sat_s # encoding: [0xfd,0x9c,0x01]
-    i16x8.q15mulr_sat_s
+    # CHECK: i16x8.extmul_low_i8x16_s # encoding: [0xfd,0x9c,0x01]
+    i16x8.extmul_low_i8x16_s
+
+    # CHECK: i16x8.extmul_high_i8x16_s # encoding: [0xfd,0x9d,0x01]
+    i16x8.extmul_high_i8x16_s
+
+    # CHECK: i16x8.extmul_low_i8x16_u # encoding: [0xfd,0x9e,0x01]
+    i16x8.extmul_low_i8x16_u
+
+    # CHECK: i16x8.extmul_high_i8x16_u # encoding: [0xfd,0x9f,0x01]
+    i16x8.extmul_high_i8x16_u
 
     # CHECK: i32x4.abs # encoding: [0xfd,0xa0,0x01]
     i32x4.abs
 
     # CHECK: i32x4.neg # encoding: [0xfd,0xa1,0x01]
     i32x4.neg
 
-    # CHECK: i32x4.any_true # encoding: [0xfd,0xa2,0x01]
-    i32x4.any_true
+    # 0xa2 unused
 
     # CHECK: i32x4.all_true # encoding: [0xfd,0xa3,0x01]
     i32x4.all_true
 
     # CHECK: i32x4.bitmask # encoding: [0xfd,0xa4,0x01]
     i32x4.bitmask
 
-    # CHECK: i32x4.widen_low_i16x8_s # encoding: [0xfd,0xa7,0x01]
-    i32x4.widen_low_i16x8_s
+    # 0xa5 unused
+
+    # 0xa6 unused
 
-    # CHECK: i32x4.widen_high_i16x8_s # encoding: [0xfd,0xa8,0x01]
-    i32x4.widen_high_i16x8_s
+    # CHECK: i32x4.extend_low_i16x8_s # encoding: [0xfd,0xa7,0x01]
+    i32x4.extend_low_i16x8_s
 
-    # CHECK: i32x4.widen_low_i16x8_u # encoding: [0xfd,0xa9,0x01]
-    i32x4.widen_low_i16x8_u
+    # CHECK: i32x4.extend_high_i16x8_s # encoding: [0xfd,0xa8,0x01]
+    i32x4.extend_high_i16x8_s
 
-    # CHECK: i32x4.widen_high_i16x8_u # encoding: [0xfd,0xaa,0x01]
-    i32x4.widen_high_i16x8_u
+    # CHECK: i32x4.extend_low_i16x8_u # encoding: [0xfd,0xa9,0x01]
+    i32x4.extend_low_i16x8_u
+
+    # CHECK: i32x4.extend_high_i16x8_u # encoding: [0xfd,0xaa,0x01]
+    i32x4.extend_high_i16x8_u
 
     # CHECK: i32x4.shl # encoding: [0xfd,0xab,0x01]
     i32x4.shl
 
     # CHECK: i32x4.shr_s # encoding: [0xfd,0xac,0x01]
     i32x4.shr_s
 
     # CHECK: i32x4.shr_u # encoding: [0xfd,0xad,0x01]
     i32x4.shr_u
 
     # CHECK: i32x4.add # encoding: [0xfd,0xae,0x01]
     i32x4.add
 
+    # 0xaf unused
+
+    # 0xb0 unused
+
     # CHECK: i32x4.sub # encoding: [0xfd,0xb1,0x01]
     i32x4.sub
 
+    # 0xb2 unused
+
+    # 0xb3 unused
+
+    # 0xb4 unused
+
     # CHECK: i32x4.mul # encoding: [0xfd,0xb5,0x01]
     i32x4.mul
 
     # CHECK: i32x4.min_s # encoding: [0xfd,0xb6,0x01]
     i32x4.min_s
 
     # CHECK: i32x4.min_u # encoding: [0xfd,0xb7,0x01]
     i32x4.min_u
 
     # CHECK: i32x4.max_s # encoding: [0xfd,0xb8,0x01]
     i32x4.max_s
 
     # CHECK: i32x4.max_u # encoding: [0xfd,0xb9,0x01]
     i32x4.max_u
 
     # CHECK: i32x4.dot_i16x8_s # encoding: [0xfd,0xba,0x01]
     i32x4.dot_i16x8_s
 
-    # CHECK: i64x2.eq # encoding: [0xfd,0xc0,0x01]
-    i64x2.eq
+    # 0xbb unused
+
+    # CHECK: i32x4.extmul_low_i16x8_s # encoding: [0xfd,0xbc,0x01]
+    i32x4.extmul_low_i16x8_s
+
+    # CHECK: i32x4.extmul_high_i16x8_s # encoding: [0xfd,0xbd,0x01]
+    i32x4.extmul_high_i16x8_s
+
+    # CHECK: i32x4.extmul_low_i16x8_u # encoding: [0xfd,0xbe,0x01]
+    i32x4.extmul_low_i16x8_u
+
+    # CHECK: i32x4.extmul_high_i16x8_u # encoding: [0xfd,0xbf,0x01]
+    i32x4.extmul_high_i16x8_u
+
+    # TODO: i64x2.abs # encoding: [0xfd,0xc0,0x01]
 
     # CHECK: i64x2.neg # encoding: [0xfd,0xc1,0x01]
     i64x2.neg
 
-    # CHECK: i64x2.any_true # encoding: [0xfd,0xc2,0x01]
-    i64x2.any_true
+    # 0xc2 unused
 
     # CHECK: i64x2.all_true # encoding: [0xfd,0xc3,0x01]
     i64x2.all_true
 
     # CHECK: i64x2.bitmask # encoding: [0xfd,0xc4,0x01]
     i64x2.bitmask
 
-    # CHECK: i64x2.widen_low_i32x4_s # encoding: [0xfd,0xc7,0x01]
-    i64x2.widen_low_i32x4_s
+    # 0xc5 unused
+
+    # 0xc6 unused
 
-    # CHECK: i64x2.widen_high_i32x4_s # encoding: [0xfd,0xc8,0x01]
-    i64x2.widen_high_i32x4_s
+    # CHECK: i64x2.extend_low_i32x4_s # encoding: [0xfd,0xc7,0x01]
+    i64x2.extend_low_i32x4_s
 
-    # CHECK: i64x2.widen_low_i32x4_u # encoding: [0xfd,0xc9,0x01]
-    i64x2.widen_low_i32x4_u
+    # CHECK: i64x2.extend_high_i32x4_s # encoding: [0xfd,0xc8,0x01]
+    i64x2.extend_high_i32x4_s
 
-    # CHECK: i64x2.widen_high_i32x4_u # encoding: [0xfd,0xca,0x01]
-    i64x2.widen_high_i32x4_u
+    # CHECK: i64x2.extend_low_i32x4_u # encoding: [0xfd,0xc9,0x01]
+    i64x2.extend_low_i32x4_u
+
+    # CHECK: i64x2.extend_high_i32x4_u # encoding: [0xfd,0xca,0x01]
+    i64x2.extend_high_i32x4_u
 
     # CHECK: i64x2.shl # encoding: [0xfd,0xcb,0x01]
     i64x2.shl
 
     # CHECK: i64x2.shr_s # encoding: [0xfd,0xcc,0x01]
     i64x2.shr_s
 
     # CHECK: i64x2.shr_u # encoding: [0xfd,0xcd,0x01]
     i64x2.shr_u
 
     # CHECK: i64x2.add # encoding: [0xfd,0xce,0x01]
     i64x2.add
 
+    # 0xcf unused
+
+    # 0xd0 unused
+
     # CHECK: i64x2.sub # encoding: [0xfd,0xd1,0x01]
     i64x2.sub
 
+    # 0xd2 unused
+
+    # 0xd3 unused
+
+    # 0xd4 unused
+
     # CHECK: i64x2.mul # encoding: [0xfd,0xd5,0x01]
     i64x2.mul
 
-    # CHECK: f32x4.ceil # encoding: [0xfd,0xd8,0x01]
-    f32x4.ceil
+    # TODO: i64x2.eq # encoding: [0xfd,0xd6,0x01]
 
-    # CHECK: f32x4.floor # encoding: [0xfd,0xd9,0x01]
-    f32x4.floor
+    # TODO: i64x2.ne # encoding: [0xfd,0xd7,0x01]
 
-    # CHECK: f32x4.trunc # encoding: [0xfd,0xda,0x01]
-    f32x4.trunc
+    # TODO: i64x2.lt_s # encoding: [0xfd,0xd8,0x01]
 
-    # CHECK: f32x4.nearest # encoding: [0xfd,0xdb,0x01]
-    f32x4.nearest
+    # TODO: i64x2.gt_s # encoding: [0xfd,0xd9,0x01]
 
-    # CHECK: f64x2.ceil # encoding: [0xfd,0xdc,0x01]
-    f64x2.ceil
+    # TODO: i64x2.le_s # encoding: [0xfd,0xda,0x01]
 
-    # CHECK: f64x2.floor # encoding: [0xfd,0xdd,0x01]
-    f64x2.floor
+    # TODO: i64x2.ge_s # encoding: [0xfd,0xdb,0x01]
 
-    # CHECK: f64x2.trunc # encoding: [0xfd,0xde,0x01]
-    f64x2.trunc
+    # CHECK: i64x2.extmul_low_i32x4_s # encoding: [0xfd,0xdc,0x01]
+    i64x2.extmul_low_i32x4_s
 
-    # CHECK: f64x2.nearest # encoding: [0xfd,0xdf,0x01]
-    f64x2.nearest
+    # CHECK: i64x2.extmul_high_i32x4_s # encoding: [0xfd,0xdd,0x01]
+    i64x2.extmul_high_i32x4_s
+
+    # CHECK: i64x2.extmul_low_i32x4_u # encoding: [0xfd,0xde,0x01]
+    i64x2.extmul_low_i32x4_u
+
+    # CHECK: i64x2.extmul_high_i32x4_u # encoding: [0xfd,0xdf,0x01]
+    i64x2.extmul_high_i32x4_u
 
     # CHECK: f32x4.abs # encoding: [0xfd,0xe0,0x01]
     f32x4.abs
 
     # CHECK: f32x4.neg # encoding: [0xfd,0xe1,0x01]
     f32x4.neg
 
+    # 0xe2 unused
+
     # CHECK: f32x4.sqrt # encoding: [0xfd,0xe3,0x01]
     f32x4.sqrt
 
     # CHECK: f32x4.add # encoding: [0xfd,0xe4,0x01]
     f32x4.add
 
     # CHECK: f32x4.sub # encoding: [0xfd,0xe5,0x01]
     f32x4.sub
main:
     f32x4.pmax
 
     # CHECK: f64x2.abs # encoding: [0xfd,0xec,0x01]
     f64x2.abs
 
     # CHECK: f64x2.neg # encoding: [0xfd,0xed,0x01]
     f64x2.neg
 
+    # 0xee unused
+
     # CHECK: f64x2.sqrt # encoding: [0xfd,0xef,0x01]
     f64x2.sqrt
 
     # CHECK: f64x2.add # encoding: [0xfd,0xf0,0x01]
     f64x2.add
 
     # CHECK: f64x2.sub # encoding: [0xfd,0xf1,0x01]
     f64x2.sub
main:
     i32x4.trunc_sat_f32x4_u
 
     # CHECK: f32x4.convert_i32x4_s # encoding: [0xfd,0xfa,0x01]
     f32x4.convert_i32x4_s
 
     # CHECK: f32x4.convert_i32x4_u # encoding: [0xfd,0xfb,0x01]
     f32x4.convert_i32x4_u
 
-    # CHECK: v128.load32_zero 32 # encoding: [0xfd,0xfc,0x01,0x02,0x20]
-    v128.load32_zero 32
-
-    # CHECK: v128.load64_zero 32 # encoding: [0xfd,0xfd,0x01,0x03,0x20]
-    v128.load64_zero 32
-
-    # CHECK: i16x8.extmul_low_i8x16_s # encoding: [0xfd,0x9a,0x01]
-    i16x8.extmul_low_i8x16_s
-
-    # CHECK: i16x8.extmul_high_i8x16_s # encoding: [0xfd,0x9d,0x01]
-    i16x8.extmul_high_i8x16_s
-
-    # CHECK: i16x8.extmul_low_i8x16_u # encoding: [0xfd,0x9e,0x01]
-    i16x8.extmul_low_i8x16_u
-
-    # CHECK: i16x8.extmul_high_i8x16_u # encoding: [0xfd,0x9f,0x01]
-    i16x8.extmul_high_i8x16_u
-
-    # CHECK: i32x4.extmul_low_i16x8_s # encoding: [0xfd,0xbb,0x01]
-    i32x4.extmul_low_i16x8_s
-
-    # CHECK: i32x4.extmul_high_i16x8_s # encoding: [0xfd,0xbd,0x01]
-    i32x4.extmul_high_i16x8_s
-
-    # CHECK: i32x4.extmul_low_i16x8_u # encoding: [0xfd,0xbe,0x01]
-    i32x4.extmul_low_i16x8_u
-
-    # CHECK: i32x4.extmul_high_i16x8_u # encoding: [0xfd,0xbf,0x01]
-    i32x4.extmul_high_i16x8_u
-
-    # CHECK: i64x2.extmul_low_i32x4_s # encoding: [0xfd,0xd2,0x01]
-    i64x2.extmul_low_i32x4_s
-
-    # CHECK: i64x2.extmul_high_i32x4_s # encoding: [0xfd,0xd3,0x01]
-    i64x2.extmul_high_i32x4_s
-
-    # CHECK: i64x2.extmul_low_i32x4_u # encoding: [0xfd,0xd6,0x01]
-    i64x2.extmul_low_i32x4_u
-
-    # CHECK: i64x2.extmul_high_i32x4_u # encoding: [0xfd,0xd7,0x01]
-    i64x2.extmul_high_i32x4_u
-
-    # CHECK: i16x8.extadd_pairwise_i8x16_s # encoding: [0xfd,0xc2,0x01]
-    i16x8.extadd_pairwise_i8x16_s
-
-    # CHECK: i16x8.extadd_pairwise_i8x16_u # encoding: [0xfd,0xc3,0x01]
-    i16x8.extadd_pairwise_i8x16_u
-
-    # CHECK: i32x4.extadd_pairwise_i16x8_s # encoding: [0xfd,0xa5,0x01]
-    i32x4.extadd_pairwise_i16x8_s
-
-    # CHECK: i32x4.extadd_pairwise_i16x8_u # encoding: [0xfd,0xa6,0x01]
-    i32x4.extadd_pairwise_i16x8_u
-
-    # CHECK: f64x2.convert_low_i32x4_s # encoding: [0xfd,0x53]
-    f64x2.convert_low_i32x4_s
-
-    # CHECK: f64x2.convert_low_i32x4_u # encoding: [0xfd,0x54]
-    f64x2.convert_low_i32x4_u
-
-    # CHECK: i32x4.trunc_sat_zero_f64x2_s # encoding: [0xfd,0x55]
+    # CHECK: i32x4.trunc_sat_zero_f64x2_s # encoding: [0xfd,0xfc,0x01]
     i32x4.trunc_sat_zero_f64x2_s
 
-    # CHECK: i32x4.trunc_sat_zero_f64x2_u # encoding: [0xfd,0x56]
+    # CHECK: i32x4.trunc_sat_zero_f64x2_u # encoding: [0xfd,0xfd,0x01]
     i32x4.trunc_sat_zero_f64x2_u
 
-    # CHECK: f32x4.demote_zero_f64x2 # encoding: [0xfd,0x57]
-    f32x4.demote_zero_f64x2
+    # CHECK: f64x2.convert_low_i32x4_s # encoding: [0xfd,0xfe,0x01]
+    f64x2.convert_low_i32x4_s
 
-    # CHECK: f64x2.promote_low_f32x4 # encoding: [0xfd,0x69]
-    f64x2.promote_low_f32x4
+    # CHECK: f64x2.convert_low_i32x4_u # encoding: [0xfd,0xff,0x01]
+    f64x2.convert_low_i32x4_u
 
     end_function