[RISCV] Teach CleanupVSETVLI to remove 'vsetvli zero, zero, vtype' when the vtype matches the previous vsetvli or vsetivli

[arcbbb]

LGTM

[frasercrmck]

LGTM

llvm/lib/Target/RISCV/RISCVCleanupVSETVLI.cpp

 
 } // end anonymous namespace
 
 char RISCVCleanupVSETVLI::ID = 0;
 
 INITIALIZE_PASS(RISCVCleanupVSETVLI, DEBUG_TYPE,
                 RISCV_CLEANUP_VSETVLI_NAME, false, false)
 
+static bool isRedundantVSETVLI(MachineInstr &MI, MachineInstr *PrevVSETVLI) {
+  // If we don't have a previous VSET{I}VLI or the VL output isn't dead, we
+  // can't remove this VSETVLI.
+  if (!PrevVSETVLI || !MI.getOperand(0).isDead())
+    return false;
+
+  // Does this VSET{I}VLI use the same VTYPE immediate.
+  int64_t PrevVTYPEImm = PrevVSETVLI->getOperand(2).getImm();
+  int64_t VTYPEImm = MI.getOperand(2).getImm();
+  if (PrevVTYPEImm != VTYPEImm)
+    return false;
+
+  if (MI.getOpcode() == RISCV::PseudoVSETIVLI) {
+    // If the previous opcode wasn't vsetivli we can't compare them.
+    if (PrevVSETVLI->getOpcode() != RISCV::PseudoVSETIVLI)
+      return false;
+
+    // For VSETIVLI, we can just compare the immediates.
+    return PrevVSETVLI->getOperand(1).getImm() == MI.getOperand(1).getImm();
+  }
+
+  assert(MI.getOpcode() == RISCV::PseudoVSETVLI);
+  Register AVLReg = MI.getOperand(1).getReg();
+
+  // If this VSETVLI isn't changing VL, it is redundant.
+  if (AVLReg == RISCV::X0 && MI.getOperand(0).getReg() == RISCV::X0)
+    return true;
+
+  // If the previous opcode isn't vsetvli we can't do any more comparison.
+  if (PrevVSETVLI->getOpcode() != RISCV::PseudoVSETVLI)
+    return false;
+
+  // Does this VSETVLI use the same AVL register?
+  if (AVLReg != PrevVSETVLI->getOperand(1).getReg())
+    return false;
+
+  // If the AVLReg is X0 we must be setting VL to VLMAX. Keeping VL unchanged
+  // was handled above.
+  if (AVLReg == RISCV::X0) {
+    // This instruction is setting VL to VLMAX, this is redundant if the
+    // previous VSETVLI was also setting VL to VLMAX. But it is not redundant
+    // if they were setting it to any other value or leaving VL unchanged.
+    Register PrevOutVL = PrevVSETVLI->getOperand(0).getReg();
+    return PrevOutVL != RISCV::X0;
+  }
+
+  // This vsetvli is redundant.
+  return true;
+}
+
 bool RISCVCleanupVSETVLI::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
   bool Changed = false;
   MachineInstr *PrevVSETVLI = nullptr;
 
   for (auto MII = MBB.begin(), MIE = MBB.end(); MII != MIE;) {
     MachineInstr &MI = *MII++;
 
     if (MI.getOpcode() != RISCV::PseudoVSETVLI &&
         MI.getOpcode() != RISCV::PseudoVSETIVLI) {
       if (PrevVSETVLI &&
           (MI.isCall() || MI.modifiesRegister(RISCV::VL) ||
            MI.modifiesRegister(RISCV::VTYPE))) {
         // Old VL/VTYPE is overwritten.
         PrevVSETVLI = nullptr;
       }
       continue;
     }
 
-    // If we don't have a previous VSET{I}VLI or the VL output isn't dead, we
-    // can't remove this VSETVLI.
-    if (!PrevVSETVLI || !MI.getOperand(0).isDead()) {
-      PrevVSETVLI = &MI;
-      continue;
-    }
-
-    // If a previous "set vl" instruction opcode is different from this one, we
-    // can't differentiate the AVL values.
-    if (PrevVSETVLI->getOpcode() != MI.getOpcode()) {
-      PrevVSETVLI = &MI;
-      continue;
-    }
-
-    // The remaining two cases are
-    // 1. PrevVSETVLI = PseudoVSETVLI
-    //    MI = PseudoVSETVLI
-    //
-    // 2. PrevVSETVLI = PseudoVSETIVLI
-    //    MI = PseudoVSETIVLI
-    Register AVLReg;
-    bool SameAVL = false;
-    if (MI.getOpcode() == RISCV::PseudoVSETVLI) {
-      AVLReg = MI.getOperand(1).getReg();
-      SameAVL = PrevVSETVLI->getOperand(1).getReg() == AVLReg;
-    } else { // RISCV::PseudoVSETIVLI
-      SameAVL =
-          PrevVSETVLI->getOperand(1).getImm() == MI.getOperand(1).getImm();
-    }
-    int64_t PrevVTYPEImm = PrevVSETVLI->getOperand(2).getImm();
-    int64_t VTYPEImm = MI.getOperand(2).getImm();
-
-    // Does this VSET{I}VLI use the same AVL register/value and VTYPE immediate?
-    if (!SameAVL || PrevVTYPEImm != VTYPEImm) {
-      PrevVSETVLI = &MI;
-      continue;
-    }
-
-    // If the AVLReg is X0 we need to look at the output VL of both VSETVLIs.
-    if ((MI.getOpcode() == RISCV::PseudoVSETVLI) && (AVLReg == RISCV::X0)) {
-      assert((PrevVSETVLI->getOpcode() == RISCV::PseudoVSETVLI) &&
-             "Unexpected vsetvli opcode.");
-      Register PrevOutVL = PrevVSETVLI->getOperand(0).getReg();
-      Register OutVL = MI.getOperand(0).getReg();
-      // We can't remove if the previous VSETVLI left VL unchanged and the
-      // current instruction is setting it to VLMAX. Without knowing the VL
-      // before the previous instruction we don't know if this is a change.
-      if (PrevOutVL == RISCV::X0 && OutVL != RISCV::X0) {
-        PrevVSETVLI = &MI;
-        continue;
-      }
-    }
-
+    if (isRedundantVSETVLI(MI, PrevVSETVLI)) {
       // This VSETVLI is redundant, remove it.
       MI.eraseFromParent();
       Changed = true;
+    } else {
+      // Otherwise update VSET{I}VLI for the next iteration.
+      PrevVSETVLI = &MI;
+    }
   }
 
   return Changed;
 }
 
 bool RISCVCleanupVSETVLI::runOnMachineFunction(MachineFunction &MF) {
   if (skipFunction(MF.getFunction()))
     return false;

llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll

; CHECK-NEXT:    ret
   ret half %r
 }
 
 define half @extractelt_nxv1f16_imm(<vscale x 1 x half> %v) {
 ; CHECK-LABEL: extractelt_nxv1f16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x half> %v, i32 2
   ret half %r
 }
 
 define half @extractelt_nxv1f16_idx(<vscale x 1 x half> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv1f16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x half> %v, i32 %idx
   ret half %r
 }
 
 define half @extractelt_nxv2f16_0(<vscale x 2 x half> %v) {
 ; CHECK-LABEL: extractelt_nxv2f16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x half> %v, i32 0
   ret half %r
 }
 
 define half @extractelt_nxv2f16_imm(<vscale x 2 x half> %v) {
 ; CHECK-LABEL: extractelt_nxv2f16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e16,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x half> %v, i32 2
   ret half %r
 }
 
 define half @extractelt_nxv2f16_idx(<vscale x 2 x half> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv2f16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x half> %v, i32 %idx
   ret half %r
 }
 
 define half @extractelt_nxv4f16_0(<vscale x 4 x half> %v) {
 ; CHECK-LABEL: extractelt_nxv4f16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x half> %v, i32 0
   ret half %r
 }
 
 define half @extractelt_nxv4f16_imm(<vscale x 4 x half> %v) {
 ; CHECK-LABEL: extractelt_nxv4f16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x half> %v, i32 2
   ret half %r
 }
 
 define half @extractelt_nxv4f16_idx(<vscale x 4 x half> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv4f16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x half> %v, i32 %idx
   ret half %r
 }
 
 define half @extractelt_nxv8f16_0(<vscale x 8 x half> %v) {
 ; CHECK-LABEL: extractelt_nxv8f16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x half> %v, i32 0
   ret half %r
 }
 
 define half @extractelt_nxv8f16_imm(<vscale x 8 x half> %v) {
 ; CHECK-LABEL: extractelt_nxv8f16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e16,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v26, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v26
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x half> %v, i32 2
   ret half %r
 }
 
 define half @extractelt_nxv8f16_idx(<vscale x 8 x half> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv8f16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v26, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v26
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x half> %v, i32 %idx
   ret half %r
 }
 
 define half @extractelt_nxv16f16_0(<vscale x 16 x half> %v) {
 ; CHECK-LABEL: extractelt_nxv16f16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,m4,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x half> %v, i32 0
   ret half %r
 }
 
 define half @extractelt_nxv16f16_imm(<vscale x 16 x half> %v) {
 ; CHECK-LABEL: extractelt_nxv16f16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e16,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v28, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e16,m4,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v28
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x half> %v, i32 2
   ret half %r
 }
 
 define half @extractelt_nxv16f16_idx(<vscale x 16 x half> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv16f16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v28, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e16,m4,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v28
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x half> %v, i32 %idx
   ret half %r
 }
 
 define half @extractelt_nxv32f16_0(<vscale x 32 x half> %v) {
 ; CHECK-LABEL: extractelt_nxv32f16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x half> %v, i32 0
   ret half %r
 }
 
 define half @extractelt_nxv32f16_imm(<vscale x 32 x half> %v) {
 ; CHECK-LABEL: extractelt_nxv32f16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e16,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v8, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x half> %v, i32 2
   ret half %r
 }
 
 define half @extractelt_nxv32f16_idx(<vscale x 32 x half> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv32f16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v8, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x half> %v, i32 %idx
   ret half %r
 }
 
 define float @extractelt_nxv1f32_0(<vscale x 1 x float> %v) {
 ; CHECK-LABEL: extractelt_nxv1f32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x float> %v, i32 0
   ret float %r
 }
 
 define float @extractelt_nxv1f32_imm(<vscale x 1 x float> %v) {
 ; CHECK-LABEL: extractelt_nxv1f32_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e32,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x float> %v, i32 2
   ret float %r
 }
 
 define float @extractelt_nxv1f32_idx(<vscale x 1 x float> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv1f32_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x float> %v, i32 %idx
   ret float %r
 }
 
 define float @extractelt_nxv2f32_0(<vscale x 2 x float> %v) {
 ; CHECK-LABEL: extractelt_nxv2f32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x float> %v, i32 0
   ret float %r
 }
 
 define float @extractelt_nxv2f32_imm(<vscale x 2 x float> %v) {
 ; CHECK-LABEL: extractelt_nxv2f32_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e32,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x float> %v, i32 2
   ret float %r
 }
 
 define float @extractelt_nxv2f32_idx(<vscale x 2 x float> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv2f32_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x float> %v, i32 %idx
   ret float %r
 }
 
 define float @extractelt_nxv4f32_0(<vscale x 4 x float> %v) {
 ; CHECK-LABEL: extractelt_nxv4f32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x float> %v, i32 0
   ret float %r
 }
 
 define float @extractelt_nxv4f32_imm(<vscale x 4 x float> %v) {
 ; CHECK-LABEL: extractelt_nxv4f32_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e32,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v26, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v26
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x float> %v, i32 2
   ret float %r
 }
 
 define float @extractelt_nxv4f32_idx(<vscale x 4 x float> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv4f32_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v26, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v26
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x float> %v, i32 %idx
   ret float %r
 }
 
 define float @extractelt_nxv8f32_0(<vscale x 8 x float> %v) {
 ; CHECK-LABEL: extractelt_nxv8f32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e32,m4,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x float> %v, i32 0
   ret float %r
 }
 
 define float @extractelt_nxv8f32_imm(<vscale x 8 x float> %v) {
 ; CHECK-LABEL: extractelt_nxv8f32_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e32,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v28, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e32,m4,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v28
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x float> %v, i32 2
   ret float %r
 }
 
 define float @extractelt_nxv8f32_idx(<vscale x 8 x float> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv8f32_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v28, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32,m4,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v28
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x float> %v, i32 %idx
   ret float %r
 }
 
 define float @extractelt_nxv16f32_0(<vscale x 16 x float> %v) {
 ; CHECK-LABEL: extractelt_nxv16f32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e32,m8,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x float> %v, i32 0
   ret float %r
 }
 
 define float @extractelt_nxv16f32_imm(<vscale x 16 x float> %v) {
 ; CHECK-LABEL: extractelt_nxv16f32_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e32,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v8, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e32,m8,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x float> %v, i32 2
   ret float %r
 }
 
 define float @extractelt_nxv16f32_idx(<vscale x 16 x float> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv16f32_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e32,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v8, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32,m8,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x float> %v, i32 %idx
   ret float %r
 }
 
 define double @extractelt_nxv1f64_0(<vscale x 1 x double> %v) {
 ; CHECK-LABEL: extractelt_nxv1f64_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x double> %v, i32 0
   ret double %r
 }
 
 define double @extractelt_nxv1f64_imm(<vscale x 1 x double> %v) {
 ; CHECK-LABEL: extractelt_nxv1f64_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x double> %v, i32 2
   ret double %r
 }
 
 define double @extractelt_nxv1f64_idx(<vscale x 1 x double> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv1f64_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x double> %v, i32 %idx
   ret double %r
 }
 
 define double @extractelt_nxv2f64_0(<vscale x 2 x double> %v) {
 ; CHECK-LABEL: extractelt_nxv2f64_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x double> %v, i32 0
   ret double %r
 }
 
 define double @extractelt_nxv2f64_imm(<vscale x 2 x double> %v) {
 ; CHECK-LABEL: extractelt_nxv2f64_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e64,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v26, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v26
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x double> %v, i32 2
   ret double %r
 }
 
 define double @extractelt_nxv2f64_idx(<vscale x 2 x double> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv2f64_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v26, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v26
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x double> %v, i32 %idx
   ret double %r
 }
 
 define double @extractelt_nxv4f64_0(<vscale x 4 x double> %v) {
 ; CHECK-LABEL: extractelt_nxv4f64_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x double> %v, i32 0
   ret double %r
 }
 
 define double @extractelt_nxv4f64_imm(<vscale x 4 x double> %v) {
 ; CHECK-LABEL: extractelt_nxv4f64_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e64,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v28, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v28
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x double> %v, i32 2
   ret double %r
 }
 
 define double @extractelt_nxv4f64_idx(<vscale x 4 x double> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv4f64_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v28, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v28
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x double> %v, i32 %idx
   ret double %r
 }
 
 define double @extractelt_nxv8f64_0(<vscale x 8 x double> %v) {
 ; CHECK-LABEL: extractelt_nxv8f64_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e64,m8,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x double> %v, i32 0
   ret double %r
 }
 
 define double @extractelt_nxv8f64_imm(<vscale x 8 x double> %v) {
 ; CHECK-LABEL: extractelt_nxv8f64_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e64,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v8, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e64,m8,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x double> %v, i32 2
   ret double %r
 }
 
 define double @extractelt_nxv8f64_idx(<vscale x 8 x double> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv8f64_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v8, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e64,m8,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x double> %v, i32 %idx
   ret double %r
 }
 

llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll

; CHECK-NEXT:    ret
   ret half %r
 }
 
 define half @extractelt_nxv1f16_imm(<vscale x 1 x half> %v) {
 ; CHECK-LABEL: extractelt_nxv1f16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x half> %v, i32 2
   ret half %r
 }
 
 define half @extractelt_nxv1f16_idx(<vscale x 1 x half> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv1f16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x half> %v, i32 %idx
   ret half %r
 }
 
 define half @extractelt_nxv2f16_0(<vscale x 2 x half> %v) {
 ; CHECK-LABEL: extractelt_nxv2f16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x half> %v, i32 0
   ret half %r
 }
 
 define half @extractelt_nxv2f16_imm(<vscale x 2 x half> %v) {
 ; CHECK-LABEL: extractelt_nxv2f16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e16,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x half> %v, i32 2
   ret half %r
 }
 
 define half @extractelt_nxv2f16_idx(<vscale x 2 x half> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv2f16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x half> %v, i32 %idx
   ret half %r
 }
 
 define half @extractelt_nxv4f16_0(<vscale x 4 x half> %v) {
 ; CHECK-LABEL: extractelt_nxv4f16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x half> %v, i32 0
   ret half %r
 }
 
 define half @extractelt_nxv4f16_imm(<vscale x 4 x half> %v) {
 ; CHECK-LABEL: extractelt_nxv4f16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x half> %v, i32 2
   ret half %r
 }
 
 define half @extractelt_nxv4f16_idx(<vscale x 4 x half> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv4f16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x half> %v, i32 %idx
   ret half %r
 }
 
 define half @extractelt_nxv8f16_0(<vscale x 8 x half> %v) {
 ; CHECK-LABEL: extractelt_nxv8f16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x half> %v, i32 0
   ret half %r
 }
 
 define half @extractelt_nxv8f16_imm(<vscale x 8 x half> %v) {
 ; CHECK-LABEL: extractelt_nxv8f16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e16,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v26, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v26
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x half> %v, i32 2
   ret half %r
 }
 
 define half @extractelt_nxv8f16_idx(<vscale x 8 x half> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv8f16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v26, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v26
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x half> %v, i32 %idx
   ret half %r
 }
 
 define half @extractelt_nxv16f16_0(<vscale x 16 x half> %v) {
 ; CHECK-LABEL: extractelt_nxv16f16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,m4,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x half> %v, i32 0
   ret half %r
 }
 
 define half @extractelt_nxv16f16_imm(<vscale x 16 x half> %v) {
 ; CHECK-LABEL: extractelt_nxv16f16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e16,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v28, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e16,m4,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v28
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x half> %v, i32 2
   ret half %r
 }
 
 define half @extractelt_nxv16f16_idx(<vscale x 16 x half> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv16f16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v28, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e16,m4,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v28
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x half> %v, i32 %idx
   ret half %r
 }
 
 define half @extractelt_nxv32f16_0(<vscale x 32 x half> %v) {
 ; CHECK-LABEL: extractelt_nxv32f16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x half> %v, i32 0
   ret half %r
 }
 
 define half @extractelt_nxv32f16_imm(<vscale x 32 x half> %v) {
 ; CHECK-LABEL: extractelt_nxv32f16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e16,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v8, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x half> %v, i32 2
   ret half %r
 }
 
 define half @extractelt_nxv32f16_idx(<vscale x 32 x half> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv32f16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v8, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x half> %v, i32 %idx
   ret half %r
 }
 
 define float @extractelt_nxv1f32_0(<vscale x 1 x float> %v) {
 ; CHECK-LABEL: extractelt_nxv1f32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x float> %v, i32 0
   ret float %r
 }
 
 define float @extractelt_nxv1f32_imm(<vscale x 1 x float> %v) {
 ; CHECK-LABEL: extractelt_nxv1f32_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e32,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x float> %v, i32 2
   ret float %r
 }
 
 define float @extractelt_nxv1f32_idx(<vscale x 1 x float> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv1f32_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x float> %v, i32 %idx
   ret float %r
 }
 
 define float @extractelt_nxv2f32_0(<vscale x 2 x float> %v) {
 ; CHECK-LABEL: extractelt_nxv2f32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x float> %v, i32 0
   ret float %r
 }
 
 define float @extractelt_nxv2f32_imm(<vscale x 2 x float> %v) {
 ; CHECK-LABEL: extractelt_nxv2f32_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e32,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x float> %v, i32 2
   ret float %r
 }
 
 define float @extractelt_nxv2f32_idx(<vscale x 2 x float> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv2f32_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x float> %v, i32 %idx
   ret float %r
 }
 
 define float @extractelt_nxv4f32_0(<vscale x 4 x float> %v) {
 ; CHECK-LABEL: extractelt_nxv4f32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x float> %v, i32 0
   ret float %r
 }
 
 define float @extractelt_nxv4f32_imm(<vscale x 4 x float> %v) {
 ; CHECK-LABEL: extractelt_nxv4f32_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e32,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v26, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v26
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x float> %v, i32 2
   ret float %r
 }
 
 define float @extractelt_nxv4f32_idx(<vscale x 4 x float> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv4f32_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v26, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v26
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x float> %v, i32 %idx
   ret float %r
 }
 
 define float @extractelt_nxv8f32_0(<vscale x 8 x float> %v) {
 ; CHECK-LABEL: extractelt_nxv8f32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e32,m4,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x float> %v, i32 0
   ret float %r
 }
 
 define float @extractelt_nxv8f32_imm(<vscale x 8 x float> %v) {
 ; CHECK-LABEL: extractelt_nxv8f32_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e32,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v28, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e32,m4,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v28
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x float> %v, i32 2
   ret float %r
 }
 
 define float @extractelt_nxv8f32_idx(<vscale x 8 x float> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv8f32_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v28, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32,m4,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v28
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x float> %v, i32 %idx
   ret float %r
 }
 
 define float @extractelt_nxv16f32_0(<vscale x 16 x float> %v) {
 ; CHECK-LABEL: extractelt_nxv16f32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e32,m8,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x float> %v, i32 0
   ret float %r
 }
 
 define float @extractelt_nxv16f32_imm(<vscale x 16 x float> %v) {
 ; CHECK-LABEL: extractelt_nxv16f32_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e32,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v8, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e32,m8,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x float> %v, i32 2
   ret float %r
 }
 
 define float @extractelt_nxv16f32_idx(<vscale x 16 x float> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv16f32_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e32,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v8, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32,m8,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x float> %v, i32 %idx
   ret float %r
 }
 
 define double @extractelt_nxv1f64_0(<vscale x 1 x double> %v) {
 ; CHECK-LABEL: extractelt_nxv1f64_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x double> %v, i32 0
   ret double %r
 }
 
 define double @extractelt_nxv1f64_imm(<vscale x 1 x double> %v) {
 ; CHECK-LABEL: extractelt_nxv1f64_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x double> %v, i32 2
   ret double %r
 }
 
 define double @extractelt_nxv1f64_idx(<vscale x 1 x double> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv1f64_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x double> %v, i32 %idx
   ret double %r
 }
 
 define double @extractelt_nxv2f64_0(<vscale x 2 x double> %v) {
 ; CHECK-LABEL: extractelt_nxv2f64_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x double> %v, i32 0
   ret double %r
 }
 
 define double @extractelt_nxv2f64_imm(<vscale x 2 x double> %v) {
 ; CHECK-LABEL: extractelt_nxv2f64_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e64,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v26, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v26
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x double> %v, i32 2
   ret double %r
 }
 
 define double @extractelt_nxv2f64_idx(<vscale x 2 x double> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv2f64_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v26, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v26
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x double> %v, i32 %idx
   ret double %r
 }
 
 define double @extractelt_nxv4f64_0(<vscale x 4 x double> %v) {
 ; CHECK-LABEL: extractelt_nxv4f64_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x double> %v, i32 0
   ret double %r
 }
 
 define double @extractelt_nxv4f64_imm(<vscale x 4 x double> %v) {
 ; CHECK-LABEL: extractelt_nxv4f64_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e64,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v28, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v28
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x double> %v, i32 2
   ret double %r
 }
 
 define double @extractelt_nxv4f64_idx(<vscale x 4 x double> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv4f64_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v28, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v28
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x double> %v, i32 %idx
   ret double %r
 }
 
 define double @extractelt_nxv8f64_0(<vscale x 8 x double> %v) {
 ; CHECK-LABEL: extractelt_nxv8f64_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e64,m8,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x double> %v, i32 0
   ret double %r
 }
 
 define double @extractelt_nxv8f64_imm(<vscale x 8 x double> %v) {
 ; CHECK-LABEL: extractelt_nxv8f64_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e64,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v8, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e64,m8,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x double> %v, i32 2
   ret double %r
 }
 
 define double @extractelt_nxv8f64_idx(<vscale x 8 x double> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv8f64_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v8, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e64,m8,ta,mu
 ; CHECK-NEXT:    vfmv.f.s fa0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x double> %v, i32 %idx
   ret double %r
 }
 

llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll

; CHECK-NEXT:    ret
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv1i8_imm(<vscale x 1 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv1i8_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i8> %v, i32 2
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv1i8_idx(<vscale x 1 x i8> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv1i8_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i8> %v, i32 %idx
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv2i8_0(<vscale x 2 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv2i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i8> %v, i32 0
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv2i8_imm(<vscale x 2 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv2i8_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e8,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i8> %v, i32 2
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv2i8_idx(<vscale x 2 x i8> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv2i8_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e8,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i8> %v, i32 %idx
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv4i8_0(<vscale x 4 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv4i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i8> %v, i32 0
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv4i8_imm(<vscale x 4 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv4i8_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e8,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i8> %v, i32 2
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv4i8_idx(<vscale x 4 x i8> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv4i8_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e8,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i8> %v, i32 %idx
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv8i8_0(<vscale x 8 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv8i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i8> %v, i32 0
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv8i8_imm(<vscale x 8 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv8i8_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e8,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i8> %v, i32 2
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv8i8_idx(<vscale x 8 x i8> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv8i8_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i8> %v, i32 %idx
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv16i8_0(<vscale x 16 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv16i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i8> %v, i32 0
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv16i8_imm(<vscale x 16 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv16i8_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e8,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v26, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e8,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v26
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i8> %v, i32 2
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv16i8_idx(<vscale x 16 x i8> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv16i8_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e8,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v26, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e8,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v26
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i8> %v, i32 %idx
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv32i8_0(<vscale x 32 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv32i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i8> %v, i32 0
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv32i8_imm(<vscale x 32 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv32i8_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e8,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v28, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e8,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v28
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i8> %v, i32 2
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv32i8_idx(<vscale x 32 x i8> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv32i8_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e8,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v28, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e8,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v28
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i8> %v, i32 %idx
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv64i8_0(<vscale x 64 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv64i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 64 x i8> %v, i32 0
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv64i8_imm(<vscale x 64 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv64i8_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e8,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v8, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e8,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 64 x i8> %v, i32 2
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv64i8_idx(<vscale x 64 x i8> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv64i8_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e8,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v8, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e8,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 64 x i8> %v, i32 %idx
   ret i8 %r
 }
 
 define signext i16 @extractelt_nxv1i16_0(<vscale x 1 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv1i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i16> %v, i32 0
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv1i16_imm(<vscale x 1 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv1i16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i16> %v, i32 2
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv1i16_idx(<vscale x 1 x i16> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv1i16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i16> %v, i32 %idx
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv2i16_0(<vscale x 2 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv2i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i16> %v, i32 0
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv2i16_imm(<vscale x 2 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv2i16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e16,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i16> %v, i32 2
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv2i16_idx(<vscale x 2 x i16> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv2i16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i16> %v, i32 %idx
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv4i16_0(<vscale x 4 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv4i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i16> %v, i32 0
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv4i16_imm(<vscale x 4 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv4i16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i16> %v, i32 2
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv4i16_idx(<vscale x 4 x i16> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv4i16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i16> %v, i32 %idx
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv8i16_0(<vscale x 8 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv8i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i16> %v, i32 0
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv8i16_imm(<vscale x 8 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv8i16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e16,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v26, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v26
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i16> %v, i32 2
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv8i16_idx(<vscale x 8 x i16> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv8i16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v26, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v26
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i16> %v, i32 %idx
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv16i16_0(<vscale x 16 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv16i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i16> %v, i32 0
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv16i16_imm(<vscale x 16 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv16i16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e16,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v28, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e16,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v28
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i16> %v, i32 2
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv16i16_idx(<vscale x 16 x i16> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv16i16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v28, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e16,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v28
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i16> %v, i32 %idx
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv32i16_0(<vscale x 32 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv32i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i16> %v, i32 0
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv32i16_imm(<vscale x 32 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv32i16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e16,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v8, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i16> %v, i32 2
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv32i16_idx(<vscale x 32 x i16> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv32i16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v8, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i16> %v, i32 %idx
   ret i16 %r
 }
 
 define i32 @extractelt_nxv1i32_0(<vscale x 1 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv1i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i32> %v, i32 0
   ret i32 %r
 }
 
 define i32 @extractelt_nxv1i32_imm(<vscale x 1 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv1i32_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e32,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i32> %v, i32 2
   ret i32 %r
 }
 
 define i32 @extractelt_nxv1i32_idx(<vscale x 1 x i32> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv1i32_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i32> %v, i32 %idx
   ret i32 %r
 }
 
 define i32 @extractelt_nxv2i32_0(<vscale x 2 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv2i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i32> %v, i32 0
   ret i32 %r
 }
 
 define i32 @extractelt_nxv2i32_imm(<vscale x 2 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv2i32_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e32,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i32> %v, i32 2
   ret i32 %r
 }
 
 define i32 @extractelt_nxv2i32_idx(<vscale x 2 x i32> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv2i32_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i32> %v, i32 %idx
   ret i32 %r
 }
 
 define i32 @extractelt_nxv4i32_0(<vscale x 4 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv4i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i32> %v, i32 0
   ret i32 %r
 }
 
 define i32 @extractelt_nxv4i32_imm(<vscale x 4 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv4i32_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e32,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v26, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v26
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i32> %v, i32 2
   ret i32 %r
 }
 
 define i32 @extractelt_nxv4i32_idx(<vscale x 4 x i32> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv4i32_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v26, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v26
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i32> %v, i32 %idx
   ret i32 %r
 }
 
 define i32 @extractelt_nxv8i32_0(<vscale x 8 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv8i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e32,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i32> %v, i32 0
   ret i32 %r
 }
 
 define i32 @extractelt_nxv8i32_imm(<vscale x 8 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv8i32_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e32,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v28, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e32,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v28
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i32> %v, i32 2
   ret i32 %r
 }
 
 define i32 @extractelt_nxv8i32_idx(<vscale x 8 x i32> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv8i32_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v28, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v28
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i32> %v, i32 %idx
   ret i32 %r
 }
 
 define i32 @extractelt_nxv16i32_0(<vscale x 16 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv16i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e32,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i32> %v, i32 0
   ret i32 %r
 }
 
 define i32 @extractelt_nxv16i32_imm(<vscale x 16 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv16i32_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e32,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v8, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e32,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i32> %v, i32 2
   ret i32 %r
 }
 
 define i32 @extractelt_nxv16i32_idx(<vscale x 16 x i32> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv16i32_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e32,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v8, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i32> %v, i32 %idx
   ret i32 %r
 }
 
 define i64 @extractelt_nxv1i64_0(<vscale x 1 x i64> %v) {
 ; CHECK-LABEL: extractelt_nxv1i64_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 32
 ; CHECK-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i64> %v, i32 0
   ret i64 %r
 }
 
 define i64 @extractelt_nxv1i64_imm(<vscale x 1 x i64> %v) {
 ; CHECK-LABEL: extractelt_nxv1i64_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
-; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i64> %v, i32 2
   ret i64 %r
 }
 
 define i64 @extractelt_nxv1i64_idx(<vscale x 1 x i64> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv1i64_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
-; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i64> %v, i32 %idx
   ret i64 %r
 }
 
 define i64 @extractelt_nxv2i64_0(<vscale x 2 x i64> %v) {
 ; CHECK-LABEL: extractelt_nxv2i64_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 32
 ; CHECK-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
 ; CHECK-NEXT:    vsrl.vx v26, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v26
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i64> %v, i32 0
   ret i64 %r
 }
 
 define i64 @extractelt_nxv2i64_imm(<vscale x 2 x i64> %v) {
 ; CHECK-LABEL: extractelt_nxv2i64_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e64,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v26, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v26
 ; CHECK-NEXT:    addi a1, zero, 32
-; CHECK-NEXT:    vsetivli a2, 1, e64,m2,ta,mu
 ; CHECK-NEXT:    vsrl.vx v26, v26, a1
-; CHECK-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v26
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i64> %v, i32 2
   ret i64 %r
 }
 
 define i64 @extractelt_nxv2i64_idx(<vscale x 2 x i64> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv2i64_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v26, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v26
 ; CHECK-NEXT:    addi a1, zero, 32
-; CHECK-NEXT:    vsetivli a2, 1, e64,m2,ta,mu
 ; CHECK-NEXT:    vsrl.vx v26, v26, a1
-; CHECK-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v26
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i64> %v, i32 %idx
   ret i64 %r
 }
 
 define i64 @extractelt_nxv4i64_0(<vscale x 4 x i64> %v) {
 ; CHECK-LABEL: extractelt_nxv4i64_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 32
 ; CHECK-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; CHECK-NEXT:    vsrl.vx v28, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v28
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i64> %v, i32 0
   ret i64 %r
 }
 
 define i64 @extractelt_nxv4i64_imm(<vscale x 4 x i64> %v) {
 ; CHECK-LABEL: extractelt_nxv4i64_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e64,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v28, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v28
 ; CHECK-NEXT:    addi a1, zero, 32
-; CHECK-NEXT:    vsetivli a2, 1, e64,m4,ta,mu
 ; CHECK-NEXT:    vsrl.vx v28, v28, a1
-; CHECK-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v28
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i64> %v, i32 2
   ret i64 %r
 }
 
 define i64 @extractelt_nxv4i64_idx(<vscale x 4 x i64> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv4i64_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v28, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v28
 ; CHECK-NEXT:    addi a1, zero, 32
-; CHECK-NEXT:    vsetivli a2, 1, e64,m4,ta,mu
 ; CHECK-NEXT:    vsrl.vx v28, v28, a1
-; CHECK-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v28
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i64> %v, i32 %idx
   ret i64 %r
 }
 
 define i64 @extractelt_nxv8i64_0(<vscale x 8 x i64> %v) {
 ; CHECK-LABEL: extractelt_nxv8i64_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, 32
 ; CHECK-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; CHECK-NEXT:    vsrl.vx v16, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e64,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v16
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i64> %v, i32 0
   ret i64 %r
 }
 
 define i64 @extractelt_nxv8i64_imm(<vscale x 8 x i64> %v) {
 ; CHECK-LABEL: extractelt_nxv8i64_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e64,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v8, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e64,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    addi a1, zero, 32
-; CHECK-NEXT:    vsetivli a2, 1, e64,m8,ta,mu
 ; CHECK-NEXT:    vsrl.vx v8, v8, a1
-; CHECK-NEXT:    vsetvli zero, zero, e64,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i64> %v, i32 2
   ret i64 %r
 }
 
 define i64 @extractelt_nxv8i64_idx(<vscale x 8 x i64> %v, i32 %idx) {
 ; CHECK-LABEL: extractelt_nxv8i64_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v8, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e64,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    addi a1, zero, 32
-; CHECK-NEXT:    vsetivli a2, 1, e64,m8,ta,mu
 ; CHECK-NEXT:    vsrl.vx v8, v8, a1
-; CHECK-NEXT:    vsetvli zero, zero, e64,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i64> %v, i32 %idx
   ret i64 %r
 }
 

llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll

; CHECK-NEXT:    ret
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv1i8_imm(<vscale x 1 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv1i8_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i8> %v, i32 2
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv1i8_idx(<vscale x 1 x i8> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv1i8_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e8,mf8,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e8,mf8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i8> %v, i32 %idx
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv2i8_0(<vscale x 2 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv2i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i8> %v, i32 0
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv2i8_imm(<vscale x 2 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv2i8_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e8,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i8> %v, i32 2
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv2i8_idx(<vscale x 2 x i8> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv2i8_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e8,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e8,mf4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i8> %v, i32 %idx
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv4i8_0(<vscale x 4 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv4i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i8> %v, i32 0
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv4i8_imm(<vscale x 4 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv4i8_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e8,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i8> %v, i32 2
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv4i8_idx(<vscale x 4 x i8> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv4i8_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e8,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e8,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i8> %v, i32 %idx
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv8i8_0(<vscale x 8 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv8i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i8> %v, i32 0
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv8i8_imm(<vscale x 8 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv8i8_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e8,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i8> %v, i32 2
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv8i8_idx(<vscale x 8 x i8> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv8i8_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i8> %v, i32 %idx
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv16i8_0(<vscale x 16 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv16i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i8> %v, i32 0
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv16i8_imm(<vscale x 16 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv16i8_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e8,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v26, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e8,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v26
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i8> %v, i32 2
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv16i8_idx(<vscale x 16 x i8> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv16i8_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e8,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v26, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e8,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v26
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i8> %v, i32 %idx
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv32i8_0(<vscale x 32 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv32i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i8> %v, i32 0
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv32i8_imm(<vscale x 32 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv32i8_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e8,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v28, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e8,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v28
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i8> %v, i32 2
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv32i8_idx(<vscale x 32 x i8> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv32i8_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e8,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v28, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e8,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v28
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i8> %v, i32 %idx
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv64i8_0(<vscale x 64 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv64i8_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e8,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 64 x i8> %v, i32 0
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv64i8_imm(<vscale x 64 x i8> %v) {
 ; CHECK-LABEL: extractelt_nxv64i8_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e8,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v8, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e8,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 64 x i8> %v, i32 2
   ret i8 %r
 }
 
 define signext i8 @extractelt_nxv64i8_idx(<vscale x 64 x i8> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv64i8_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e8,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v8, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e8,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 64 x i8> %v, i32 %idx
   ret i8 %r
 }
 
 define signext i16 @extractelt_nxv1i16_0(<vscale x 1 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv1i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i16> %v, i32 0
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv1i16_imm(<vscale x 1 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv1i16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i16> %v, i32 2
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv1i16_idx(<vscale x 1 x i16> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv1i16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,mf4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e16,mf4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i16> %v, i32 %idx
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv2i16_0(<vscale x 2 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv2i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i16> %v, i32 0
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv2i16_imm(<vscale x 2 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv2i16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e16,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i16> %v, i32 2
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv2i16_idx(<vscale x 2 x i16> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv2i16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e16,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i16> %v, i32 %idx
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv4i16_0(<vscale x 4 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv4i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i16> %v, i32 0
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv4i16_imm(<vscale x 4 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv4i16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i16> %v, i32 2
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv4i16_idx(<vscale x 4 x i16> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv4i16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i16> %v, i32 %idx
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv8i16_0(<vscale x 8 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv8i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i16> %v, i32 0
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv8i16_imm(<vscale x 8 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv8i16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e16,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v26, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v26
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i16> %v, i32 2
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv8i16_idx(<vscale x 8 x i16> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv8i16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v26, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v26
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i16> %v, i32 %idx
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv16i16_0(<vscale x 16 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv16i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i16> %v, i32 0
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv16i16_imm(<vscale x 16 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv16i16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e16,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v28, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e16,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v28
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i16> %v, i32 2
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv16i16_idx(<vscale x 16 x i16> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv16i16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v28, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e16,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v28
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i16> %v, i32 %idx
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv32i16_0(<vscale x 32 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv32i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i16> %v, i32 0
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv32i16_imm(<vscale x 32 x i16> %v) {
 ; CHECK-LABEL: extractelt_nxv32i16_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e16,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v8, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i16> %v, i32 2
   ret i16 %r
 }
 
 define signext i16 @extractelt_nxv32i16_idx(<vscale x 32 x i16> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv32i16_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e16,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v8, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e16,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 32 x i16> %v, i32 %idx
   ret i16 %r
 }
 
 define signext i32 @extractelt_nxv1i32_0(<vscale x 1 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv1i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i32> %v, i32 0
   ret i32 %r
 }
 
 define signext i32 @extractelt_nxv1i32_imm(<vscale x 1 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv1i32_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e32,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i32> %v, i32 2
   ret i32 %r
 }
 
 define signext i32 @extractelt_nxv1i32_idx(<vscale x 1 x i32> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv1i32_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e32,mf2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32,mf2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i32> %v, i32 %idx
   ret i32 %r
 }
 
 define signext i32 @extractelt_nxv2i32_0(<vscale x 2 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv2i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i32> %v, i32 0
   ret i32 %r
 }
 
 define signext i32 @extractelt_nxv2i32_imm(<vscale x 2 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv2i32_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e32,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i32> %v, i32 2
   ret i32 %r
 }
 
 define signext i32 @extractelt_nxv2i32_idx(<vscale x 2 x i32> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv2i32_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e32,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i32> %v, i32 %idx
   ret i32 %r
 }
 
 define signext i32 @extractelt_nxv4i32_0(<vscale x 4 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv4i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i32> %v, i32 0
   ret i32 %r
 }
 
 define signext i32 @extractelt_nxv4i32_imm(<vscale x 4 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv4i32_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e32,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v26, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v26
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i32> %v, i32 2
   ret i32 %r
 }
 
 define signext i32 @extractelt_nxv4i32_idx(<vscale x 4 x i32> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv4i32_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v26, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v26
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i32> %v, i32 %idx
   ret i32 %r
 }
 
 define signext i32 @extractelt_nxv8i32_0(<vscale x 8 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv8i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e32,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i32> %v, i32 0
   ret i32 %r
 }
 
 define signext i32 @extractelt_nxv8i32_imm(<vscale x 8 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv8i32_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e32,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v28, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e32,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v28
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i32> %v, i32 2
   ret i32 %r
 }
 
 define signext i32 @extractelt_nxv8i32_idx(<vscale x 8 x i32> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv8i32_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e32,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v28, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v28
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i32> %v, i32 %idx
   ret i32 %r
 }
 
 define signext i32 @extractelt_nxv16i32_0(<vscale x 16 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv16i32_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e32,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i32> %v, i32 0
   ret i32 %r
 }
 
 define signext i32 @extractelt_nxv16i32_imm(<vscale x 16 x i32> %v) {
 ; CHECK-LABEL: extractelt_nxv16i32_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e32,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v8, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e32,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i32> %v, i32 2
   ret i32 %r
 }
 
 define signext i32 @extractelt_nxv16i32_idx(<vscale x 16 x i32> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv16i32_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e32,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v8, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e32,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 16 x i32> %v, i32 %idx
   ret i32 %r
 }
 
 define i64 @extractelt_nxv1i64_0(<vscale x 1 x i64> %v) {
 ; CHECK-LABEL: extractelt_nxv1i64_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i64> %v, i32 0
   ret i64 %r
 }
 
 define i64 @extractelt_nxv1i64_imm(<vscale x 1 x i64> %v) {
 ; CHECK-LABEL: extractelt_nxv1i64_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v25, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i64> %v, i32 2
   ret i64 %r
 }
 
 define i64 @extractelt_nxv1i64_idx(<vscale x 1 x i64> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv1i64_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v25, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 1 x i64> %v, i32 %idx
   ret i64 %r
 }
 
 define i64 @extractelt_nxv2i64_0(<vscale x 2 x i64> %v) {
 ; CHECK-LABEL: extractelt_nxv2i64_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i64> %v, i32 0
   ret i64 %r
 }
 
 define i64 @extractelt_nxv2i64_imm(<vscale x 2 x i64> %v) {
 ; CHECK-LABEL: extractelt_nxv2i64_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e64,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v26, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v26
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i64> %v, i32 2
   ret i64 %r
 }
 
 define i64 @extractelt_nxv2i64_idx(<vscale x 2 x i64> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv2i64_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v26, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v26
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 2 x i64> %v, i32 %idx
   ret i64 %r
 }
 
 define i64 @extractelt_nxv4i64_0(<vscale x 4 x i64> %v) {
 ; CHECK-LABEL: extractelt_nxv4i64_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i64> %v, i32 0
   ret i64 %r
 }
 
 define i64 @extractelt_nxv4i64_imm(<vscale x 4 x i64> %v) {
 ; CHECK-LABEL: extractelt_nxv4i64_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e64,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v28, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v28
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i64> %v, i32 2
   ret i64 %r
 }
 
 define i64 @extractelt_nxv4i64_idx(<vscale x 4 x i64> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv4i64_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e64,m4,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v28, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v28
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 4 x i64> %v, i32 %idx
   ret i64 %r
 }
 
 define i64 @extractelt_nxv8i64_0(<vscale x 8 x i64> %v) {
 ; CHECK-LABEL: extractelt_nxv8i64_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, zero, e64,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i64> %v, i32 0
   ret i64 %r
 }
 
 define i64 @extractelt_nxv8i64_imm(<vscale x 8 x i64> %v) {
 ; CHECK-LABEL: extractelt_nxv8i64_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a0, 1, e64,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vi v8, v8, 2
-; CHECK-NEXT:    vsetvli zero, zero, e64,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i64> %v, i32 2
   ret i64 %r
 }
 
 define i64 @extractelt_nxv8i64_idx(<vscale x 8 x i64> %v, i32 signext %idx) {
 ; CHECK-LABEL: extractelt_nxv8i64_idx:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli a1, 1, e64,m8,ta,mu
 ; CHECK-NEXT:    vslidedown.vx v8, v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e64,m8,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v8
 ; CHECK-NEXT:    ret
   %r = extractelement <vscale x 8 x i64> %v, i32 %idx
   ret i64 %r
 }
 

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32
 ; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+experimental-v,+experimental-zfh,+f,+d -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64
 
 define i8 @extractelt_v16i8(<16 x i8>* %x) nounwind {
 ; RV32-LABEL: extractelt_v16i8:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; RV32-NEXT:    vle8.v v25, (a0)
 ; RV32-NEXT:    vsetivli a0, 1, e8,m1,ta,mu
 ; RV32-NEXT:    vslidedown.vi v25, v25, 7
-; RV32-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: extractelt_v16i8:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 16, e8,m1,ta,mu
 ; RV64-NEXT:    vle8.v v25, (a0)
 ; RV64-NEXT:    vsetivli a0, 1, e8,m1,ta,mu
 ; RV64-NEXT:    vslidedown.vi v25, v25, 7
-; RV64-NEXT:    vsetvli zero, zero, e8,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %a = load <16 x i8>, <16 x i8>* %x
   %b = extractelement <16 x i8> %a, i32 7
   ret i8 %b
 }
 
 define i16 @extractelt_v8i16(<8 x i16>* %x) nounwind {
 ; RV32-LABEL: extractelt_v8i16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; RV32-NEXT:    vle16.v v25, (a0)
 ; RV32-NEXT:    vsetivli a0, 1, e16,m1,ta,mu
 ; RV32-NEXT:    vslidedown.vi v25, v25, 7
-; RV32-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: extractelt_v8i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; RV64-NEXT:    vle16.v v25, (a0)
 ; RV64-NEXT:    vsetivli a0, 1, e16,m1,ta,mu
 ; RV64-NEXT:    vslidedown.vi v25, v25, 7
-; RV64-NEXT:    vsetvli zero, zero, e16,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %a = load <8 x i16>, <8 x i16>* %x
   %b = extractelement <8 x i16> %a, i32 7
   ret i16 %b
 }
 
 define i32 @extractelt_v4i32(<4 x i32>* %x) nounwind {
 ; RV32-LABEL: extractelt_v4i32:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; RV32-NEXT:    vle32.v v25, (a0)
 ; RV32-NEXT:    vsetivli a0, 1, e32,m1,ta,mu
 ; RV32-NEXT:    vslidedown.vi v25, v25, 2
-; RV32-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: extractelt_v4i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; RV64-NEXT:    vle32.v v25, (a0)
 ; RV64-NEXT:    vsetivli a0, 1, e32,m1,ta,mu
 ; RV64-NEXT:    vslidedown.vi v25, v25, 2
-; RV64-NEXT:    vsetvli zero, zero, e32,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %a = load <4 x i32>, <4 x i32>* %x
   %b = extractelement <4 x i32> %a, i32 2
   ret i32 %b
 }
 
 define i64 @extractelt_v2i64(<2 x i64>* %x) nounwind {
 ; RV32-LABEL: extractelt_v2i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; RV32-NEXT:    vle64.v v25, (a0)
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v25
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; RV32-NEXT:    vsrl.vx v25, v25, a1
-; RV32-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: extractelt_v2i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; RV64-NEXT:    vle64.v v25, (a0)
-; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %a = load <2 x i64>, <2 x i64>* %x
   %b = extractelement <2 x i64> %a, i32 0
   ret i64 %b
 }
 
 define i8 @extractelt_v32i8(<32 x i8>* %x) nounwind {
 ; RV32-LABEL: extractelt_v32i8:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    addi a1, zero, 32
 ; RV32-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
 ; RV32-NEXT:    vle8.v v26, (a0)
 ; RV32-NEXT:    vsetivli a0, 1, e8,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v26, 7
-; RV32-NEXT:    vsetvli zero, zero, e8,m2,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v26
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: extractelt_v32i8:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi a1, zero, 32
 ; RV64-NEXT:    vsetvli a1, a1, e8,m2,ta,mu
 ; RV64-NEXT:    vle8.v v26, (a0)
 ; RV64-NEXT:    vsetivli a0, 1, e8,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v26, 7
-; RV64-NEXT:    vsetvli zero, zero, e8,m2,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v26
 ; RV64-NEXT:    ret
   %a = load <32 x i8>, <32 x i8>* %x
   %b = extractelement <32 x i8> %a, i32 7
   ret i8 %b
 }
 
 define i16 @extractelt_v16i16(<16 x i16>* %x) nounwind {
 ; RV32-LABEL: extractelt_v16i16:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 16, e16,m2,ta,mu
 ; RV32-NEXT:    vle16.v v26, (a0)
 ; RV32-NEXT:    vsetivli a0, 1, e16,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v26, 7
-; RV32-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v26
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: extractelt_v16i16:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 16, e16,m2,ta,mu
 ; RV64-NEXT:    vle16.v v26, (a0)
 ; RV64-NEXT:    vsetivli a0, 1, e16,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v26, 7
-; RV64-NEXT:    vsetvli zero, zero, e16,m2,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v26
 ; RV64-NEXT:    ret
   %a = load <16 x i16>, <16 x i16>* %x
   %b = extractelement <16 x i16> %a, i32 7
   ret i16 %b
 }
 
 define i32 @extractelt_v8i32(<8 x i32>* %x) nounwind {
 ; RV32-LABEL: extractelt_v8i32:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; RV32-NEXT:    vle32.v v26, (a0)
 ; RV32-NEXT:    vsetivli a0, 1, e32,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v26, 6
-; RV32-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v26
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: extractelt_v8i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; RV64-NEXT:    vle32.v v26, (a0)
 ; RV64-NEXT:    vsetivli a0, 1, e32,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v26, 6
-; RV64-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v26
 ; RV64-NEXT:    ret
   %a = load <8 x i32>, <8 x i32>* %x
   %b = extractelement <8 x i32> %a, i32 6
   ret i32 %b
 }
 
 define i64 @extractelt_v4i64(<4 x i64>* %x) nounwind {
 ; RV32-LABEL: extractelt_v4i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; RV32-NEXT:    vle64.v v26, (a0)
 ; RV32-NEXT:    vsetivli a0, 1, e64,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v26, 3
-; RV32-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v26
 ; RV32-NEXT:    addi a1, zero, 32
-; RV32-NEXT:    vsetivli a2, 1, e64,m2,ta,mu
 ; RV32-NEXT:    vsrl.vx v26, v26, a1
-; RV32-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
 ; RV32-NEXT:    vmv.x.s a1, v26
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: extractelt_v4i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vle64.v v26, (a0)
 ; RV64-NEXT:    vsetivli a0, 1, e64,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v26, 3
-; RV64-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v26
 ; RV64-NEXT:    ret
   %a = load <4 x i64>, <4 x i64>* %x
   %b = extractelement <4 x i64> %a, i32 3
   ret i64 %b
 }
 
 ; This uses a non-power of 2 type so that it isn't an MVT to catch an
 ; incorrect use of getSimpleValueType().
 ; NOTE: Type legalization is bitcasting to vXi32 and doing 2 independent
 ; slidedowns and extracts.
 define i64 @extractelt_v3i64(<3 x i64>* %x) nounwind {
 ; RV32-LABEL: extractelt_v3i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; RV32-NEXT:    vle32.v v26, (a0)
 ; RV32-NEXT:    vsetivli a0, 1, e32,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v26, 4
-; RV32-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
 ; RV32-NEXT:    vmv.x.s a0, v28
-; RV32-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v26, 5
-; RV32-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
 ; RV32-NEXT:    vmv.x.s a1, v26
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: extractelt_v3i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vle64.v v26, (a0)
 ; RV64-NEXT:    vsetivli a0, 1, e64,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v26, 2
-; RV64-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v26
 ; RV64-NEXT:    ret
   %a = load <3 x i64>, <3 x i64>* %x
   %b = extractelement <3 x i64> %a, i32 2
   ret i64 %b
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll

 ; RV32-NEXT:    .cfi_offset s0, -8
 ; RV32-NEXT:    addi s0, sp, 128
 ; RV32-NEXT:    .cfi_def_cfa s0, 0
 ; RV32-NEXT:    andi sp, sp, -32
 ; RV32-NEXT:    sw a2, 32(sp)
 ; RV32-NEXT:    sw a1, 64(sp)
 ; RV32-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; RV32-NEXT:    vle32.v v26, (a0)
-; RV32-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
 ; RV32-NEXT:    vmv.x.s a1, v26
 ; RV32-NEXT:    sw a1, 0(sp)
-; RV32-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; RV32-NEXT:    addi a1, sp, 32
 ; RV32-NEXT:    vle32.v v28, (a1)
-; RV32-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
 ; RV32-NEXT:    vmv.x.s a1, v28
 ; RV32-NEXT:    sw a1, 28(sp)
-; RV32-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; RV32-NEXT:    addi a1, sp, 64
 ; RV32-NEXT:    vle32.v v28, (a1)
-; RV32-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
 ; RV32-NEXT:    vmv.x.s a1, v28
 ; RV32-NEXT:    sw a1, 24(sp)
 ; RV32-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v26, 5
-; RV32-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
 ; RV32-NEXT:    vmv.x.s a1, v28
 ; RV32-NEXT:    sw a1, 20(sp)
-; RV32-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v26, 4
-; RV32-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
 ; RV32-NEXT:    vmv.x.s a1, v28
 ; RV32-NEXT:    sw a1, 16(sp)
-; RV32-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v26, 3
-; RV32-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
 ; RV32-NEXT:    vmv.x.s a1, v28
 ; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v28, v26, 2
-; RV32-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
 ; RV32-NEXT:    vmv.x.s a1, v28
 ; RV32-NEXT:    sw a1, 8(sp)
-; RV32-NEXT:    vsetivli a1, 1, e32,m2,ta,mu
 ; RV32-NEXT:    vslidedown.vi v26, v26, 1
-; RV32-NEXT:    vsetvli zero, zero, e32,m2,ta,mu
 ; RV32-NEXT:    vmv.x.s a1, v26
 ; RV32-NEXT:    sw a1, 4(sp)
 ; RV32-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
 ; RV32-NEXT:    vle32.v v26, (sp)
 ; RV32-NEXT:    vse32.v v26, (a0)
 ; RV32-NEXT:    addi sp, s0, -128
 ; RV32-NEXT:    lw s0, 120(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    lw ra, 124(sp) # 4-byte Folded Reload

 ; RV64-NEXT:    .cfi_offset ra, -8
 ; RV64-NEXT:    .cfi_offset s0, -16
 ; RV64-NEXT:    addi s0, sp, 96
 ; RV64-NEXT:    .cfi_def_cfa s0, 0
 ; RV64-NEXT:    andi sp, sp, -32
 ; RV64-NEXT:    vsetivli a2, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vle64.v v26, (a0)
 ; RV64-NEXT:    sd a1, 32(sp)
-; RV64-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
 ; RV64-NEXT:    vmv.x.s a1, v26
 ; RV64-NEXT:    sd a1, 0(sp)
-; RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; RV64-NEXT:    addi a1, sp, 32
 ; RV64-NEXT:    vle64.v v28, (a1)
-; RV64-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
 ; RV64-NEXT:    vmv.x.s a1, v28
 ; RV64-NEXT:    sd a1, 24(sp)
 ; RV64-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v28, v26, 2
-; RV64-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
 ; RV64-NEXT:    vmv.x.s a1, v28
 ; RV64-NEXT:    sd a1, 16(sp)
-; RV64-NEXT:    vsetivli a1, 1, e64,m2,ta,mu
 ; RV64-NEXT:    vslidedown.vi v26, v26, 1
-; RV64-NEXT:    vsetvli zero, zero, e64,m2,ta,mu
 ; RV64-NEXT:    vmv.x.s a1, v26
 ; RV64-NEXT:    sd a1, 8(sp)
 ; RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vle64.v v26, (sp)
 ; RV64-NEXT:    vse64.v v26, (a0)
 ; RV64-NEXT:    addi sp, s0, -96
 ; RV64-NEXT:    ld s0, 80(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    ld ra, 88(sp) # 8-byte Folded Reload

llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll

 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vredsum.vs v25, v8, v25
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.add.nxv1i64(<vscale x 1 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.umax.nxv1i64(<vscale x 1 x i64>)
 
 define i64 @vreduce_umax_nxv1i64(<vscale x 1 x i64> %v) {
 ; CHECK-LABEL: vreduce_umax_nxv1i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.umax.nxv1i64(<vscale x 1 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.smax.nxv1i64(<vscale x 1 x i64>)
 
 define i64 @vreduce_smax_nxv1i64(<vscale x 1 x i64> %v) {
 ; CHECK-LABEL: vreduce_smax_nxv1i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, 524288
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsll.vx v25, v25, a1
 ; CHECK-NEXT:    vmv.v.i v26, 0
 ; CHECK-NEXT:    vsll.vx v26, v26, a1
 ; CHECK-NEXT:    vsrl.vx v26, v26, a1
 ; CHECK-NEXT:    vor.vv v25, v26, v25
 ; CHECK-NEXT:    vredmax.vs v25, v8, v25
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.smax.nxv1i64(<vscale x 1 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.umin.nxv1i64(<vscale x 1 x i64>)
 
 define i64 @vreduce_umin_nxv1i64(<vscale x 1 x i64> %v) {
 ; CHECK-LABEL: vreduce_umin_nxv1i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vredminu.vs v25, v8, v25
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.umin.nxv1i64(<vscale x 1 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.smin.nxv1i64(<vscale x 1 x i64>)
 

 ; CHECK-NEXT:    addi a0, a0, -1
 ; CHECK-NEXT:    vmv.v.x v26, a0
 ; CHECK-NEXT:    vsll.vx v26, v26, a1
 ; CHECK-NEXT:    vor.vv v25, v25, v26
 ; CHECK-NEXT:    vredmin.vs v25, v8, v25
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.smin.nxv1i64(<vscale x 1 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.and.nxv1i64(<vscale x 1 x i64>)
 
 define i64 @vreduce_and_nxv1i64(<vscale x 1 x i64> %v) {
 ; CHECK-LABEL: vreduce_and_nxv1i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vredand.vs v25, v8, v25
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.and.nxv1i64(<vscale x 1 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.or.nxv1i64(<vscale x 1 x i64>)
 
 define i64 @vreduce_or_nxv1i64(<vscale x 1 x i64> %v) {
 ; CHECK-LABEL: vreduce_or_nxv1i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vredor.vs v25, v8, v25
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.or.nxv1i64(<vscale x 1 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.xor.nxv1i64(<vscale x 1 x i64>)
 
 define i64 @vreduce_xor_nxv1i64(<vscale x 1 x i64> %v) {
 ; CHECK-LABEL: vreduce_xor_nxv1i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vredxor.vs v25, v8, v25
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.xor.nxv1i64(<vscale x 1 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64>)
 
 define i64 @vreduce_add_nxv2i64(<vscale x 2 x i64> %v) {
 ; CHECK-LABEL: vreduce_add_nxv2i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v8, v25
 ; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.add.nxv2i64(<vscale x 2 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.umax.nxv2i64(<vscale x 2 x i64>)
 
 define i64 @vreduce_umax_nxv2i64(<vscale x 2 x i64> %v) {
 ; CHECK-LABEL: vreduce_umax_nxv2i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
 ; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.umax.nxv2i64(<vscale x 2 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.smax.nxv2i64(<vscale x 2 x i64>)
 

 ; CHECK-NEXT:    vsrl.vx v26, v26, a1
 ; CHECK-NEXT:    vor.vv v25, v26, v25
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v8, v25
 ; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.smax.nxv2i64(<vscale x 2 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.umin.nxv2i64(<vscale x 2 x i64>)
 
 define i64 @vreduce_umin_nxv2i64(<vscale x 2 x i64> %v) {
 ; CHECK-LABEL: vreduce_umin_nxv2i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v8, v25
 ; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.umin.nxv2i64(<vscale x 2 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.smin.nxv2i64(<vscale x 2 x i64>)
 

 ; CHECK-NEXT:    vsll.vx v26, v26, a1
 ; CHECK-NEXT:    vor.vv v25, v25, v26
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vredmin.vs v25, v8, v25
 ; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.smin.nxv2i64(<vscale x 2 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.and.nxv2i64(<vscale x 2 x i64>)
 
 define i64 @vreduce_and_nxv2i64(<vscale x 2 x i64> %v) {
 ; CHECK-LABEL: vreduce_and_nxv2i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v8, v25
 ; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.and.nxv2i64(<vscale x 2 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.or.nxv2i64(<vscale x 2 x i64>)
 
 define i64 @vreduce_or_nxv2i64(<vscale x 2 x i64> %v) {
 ; CHECK-LABEL: vreduce_or_nxv2i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v8, v25
 ; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.or.nxv2i64(<vscale x 2 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.xor.nxv2i64(<vscale x 2 x i64>)
 
 define i64 @vreduce_xor_nxv2i64(<vscale x 2 x i64> %v) {
 ; CHECK-LABEL: vreduce_xor_nxv2i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v8, v25
 ; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.xor.nxv2i64(<vscale x 2 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.add.nxv4i64(<vscale x 4 x i64>)
 
 define i64 @vreduce_add_nxv4i64(<vscale x 4 x i64> %v) {
 ; CHECK-LABEL: vreduce_add_nxv4i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vredsum.vs v25, v8, v25
 ; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.add.nxv4i64(<vscale x 4 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.umax.nxv4i64(<vscale x 4 x i64>)
 
 define i64 @vreduce_umax_nxv4i64(<vscale x 4 x i64> %v) {
 ; CHECK-LABEL: vreduce_umax_nxv4i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vredmaxu.vs v25, v8, v25
 ; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.umax.nxv4i64(<vscale x 4 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.smax.nxv4i64(<vscale x 4 x i64>)
 

 ; CHECK-NEXT:    vsrl.vx v26, v26, a1
 ; CHECK-NEXT:    vor.vv v25, v26, v25
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vredmax.vs v25, v8, v25
 ; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.smax.nxv4i64(<vscale x 4 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.umin.nxv4i64(<vscale x 4 x i64>)
 
 define i64 @vreduce_umin_nxv4i64(<vscale x 4 x i64> %v) {
 ; CHECK-LABEL: vreduce_umin_nxv4i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vredminu.vs v25, v8, v25
 ; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.umin.nxv4i64(<vscale x 4 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.smin.nxv4i64(<vscale x 4 x i64>)
 

 ; CHECK-NEXT:    vsll.vx v26, v26, a1
 ; CHECK-NEXT:    vor.vv v25, v25, v26
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vredmin.vs v25, v8, v25
 ; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.smin.nxv4i64(<vscale x 4 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.and.nxv4i64(<vscale x 4 x i64>)
 
 define i64 @vreduce_and_nxv4i64(<vscale x 4 x i64> %v) {
 ; CHECK-LABEL: vreduce_and_nxv4i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, -1
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vredand.vs v25, v8, v25
 ; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.and.nxv4i64(<vscale x 4 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.or.nxv4i64(<vscale x 4 x i64>)
 
 define i64 @vreduce_or_nxv4i64(<vscale x 4 x i64> %v) {
 ; CHECK-LABEL: vreduce_or_nxv4i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vredor.vs v25, v8, v25
 ; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.or.nxv4i64(<vscale x 4 x i64> %v)
   ret i64 %red
 }
 
 declare i64 @llvm.vector.reduce.xor.nxv4i64(<vscale x 4 x i64>)
 
 define i64 @vreduce_xor_nxv4i64(<vscale x 4 x i64> %v) {
 ; CHECK-LABEL: vreduce_xor_nxv4i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.i v25, 0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vredxor.vs v25, v8, v25
 ; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    addi a1, zero, 32
 ; CHECK-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
 ; CHECK-NEXT:    vsrl.vx v25, v25, a1
-; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a1, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.xor.nxv4i64(<vscale x 4 x i64> %v)
   ret i64 %red
 }