[ARM] Handle Splats in MVE lane interleaving

[dmgreen]

Summary

As another addition to MVE lane interleaving, this handles Splat shuffle vectors, as the shuffle of a splat is a splat.

[dmgreen]

ping

llvm/lib/Target/ARM/MVELaneInterleavingPass.cpp

case Instruction::Select:
         else
           OtherLeafs.insert(&Op);
       }
 
       for (auto *Use : I->users())
         Worklist.push_back(cast<Instruction>(Use));
       break;
 
+    case Instruction::ShuffleVector:
+      // A shuffle of a splat is a splat.
+      if (cast<ShuffleVectorInst>(I)->isZeroEltSplat())
+        continue;
+      LLVM_FALLTHROUGH;
+
     default:
       LLVM_DEBUG(dbgs() << "  Unhandled instruction: " << *I << "\n");
       return false;
     }
   }
 
   if (Exts.empty() && OtherLeafs.empty())
     return false;

llvm/test/CodeGen/Thumb2/mve-laneinterleaving-cost.ll

entry:
   %t = trunc <4 x i64> %sh to <4 x i32>
   store <4 x i32> %t, <4 x i32> *%D, align 4
   ret void
 }
 
 define arm_aapcs_vfpcc void @mul_i16(<8 x i16> *%A, <8 x i16> *%B, i32 %C, <8 x i16> *%D) {
 ; CHECK-LABEL: mul_i16:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vldrh.s32 q0, [r1]
-; CHECK-NEXT:    vldrh.s32 q1, [r0]
-; CHECK-NEXT:    vldrh.s32 q2, [r0, #8]
+; CHECK-NEXT:    vldrw.u32 q0, [r1]
+; CHECK-NEXT:    vldrw.u32 q1, [r0]
 ; CHECK-NEXT:    rsbs r2, r2, #0
-; CHECK-NEXT:    vmul.i32 q0, q1, q0
-; CHECK-NEXT:    vldrh.s32 q1, [r1, #8]
+; CHECK-NEXT:    vmullt.s16 q2, q1, q0
+; CHECK-NEXT:    vmullb.s16 q0, q1, q0
+; CHECK-NEXT:    vshl.s32 q2, r2
 ; CHECK-NEXT:    vshl.s32 q0, r2
-; CHECK-NEXT:    vmul.i32 q1, q2, q1
-; CHECK-NEXT:    vstrh.32 q0, [r3]
-; CHECK-NEXT:    vshl.s32 q1, r2
-; CHECK-NEXT:    vstrh.32 q1, [r3, #8]
+; CHECK-NEXT:    vmovnt.i32 q0, q2
+; CHECK-NEXT:    vstrw.32 q0, [r3]
 ; CHECK-NEXT:    bx lr
 entry:
   %a = load <8 x i16>, <8 x i16> *%A, align 4
   %b = load <8 x i16>, <8 x i16> *%B, align 4
   %i = insertelement <8 x i32> undef, i32 %C, i32 0
   %c = shufflevector <8 x i32> %i, <8 x i32> undef, <8 x i32> zeroinitializer
   %sa = sext <8 x i16> %a to <8 x i32>
   %sb = sext <8 x i16> %b to <8 x i32>
   %add = mul <8 x i32> %sa, %sb
   %sh = ashr <8 x i32> %add, %c
   %t = trunc <8 x i32> %sh to <8 x i16>
   store <8 x i16> %t, <8 x i16> *%D, align 4
   ret void
 }
 
 define arm_aapcs_vfpcc void @mul_i8(<16 x i8> *%A, <16 x i8> *%B, i16 %C, <16 x i8> *%D) {
 ; CHECK-LABEL: mul_i8:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    vldrb.s16 q0, [r1]
-; CHECK-NEXT:    vldrb.s16 q1, [r0]
-; CHECK-NEXT:    vldrb.s16 q2, [r0, #8]
+; CHECK-NEXT:    vldrw.u32 q0, [r1]
+; CHECK-NEXT:    vldrw.u32 q1, [r0]
 ; CHECK-NEXT:    rsbs r2, r2, #0
-; CHECK-NEXT:    vmul.i16 q0, q1, q0
-; CHECK-NEXT:    vldrb.s16 q1, [r1, #8]
+; CHECK-NEXT:    vmullt.s8 q2, q1, q0
+; CHECK-NEXT:    vmullb.s8 q0, q1, q0
+; CHECK-NEXT:    vshl.s16 q2, r2
 ; CHECK-NEXT:    vshl.s16 q0, r2
-; CHECK-NEXT:    vmul.i16 q1, q2, q1
-; CHECK-NEXT:    vstrb.16 q0, [r3]
-; CHECK-NEXT:    vshl.s16 q1, r2
-; CHECK-NEXT:    vstrb.16 q1, [r3, #8]
+; CHECK-NEXT:    vmovnt.i16 q0, q2
+; CHECK-NEXT:    vstrw.32 q0, [r3]
 ; CHECK-NEXT:    bx lr
 entry:
   %a = load <16 x i8>, <16 x i8> *%A, align 4
   %b = load <16 x i8>, <16 x i8> *%B, align 4
   %i = insertelement <16 x i16> undef, i16 %C, i32 0
   %c = shufflevector <16 x i16> %i, <16 x i16> undef, <16 x i32> zeroinitializer
   %sa = sext <16 x i8> %a to <16 x i16>
   %sb = sext <16 x i8> %b to <16 x i16>
   %add = mul <16 x i16> %sa, %sb
   %sh = ashr <16 x i16> %add, %c
   %t = trunc <16 x i16> %sh to <16 x i8>
   store <16 x i8> %t, <16 x i8> *%D, align 4
   ret void
 }