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Differential D97289

[ARM] Extend MVE lane interleaving to handle other non-instruction leaves
ClosedPublic

Authored by dmgreen on Feb 23 2021, 7:01 AM.

Details

Reviewers
SjoerdMeijer
simon_tatham
ostannard
efriedma
samtebbs
Commits
rG3a68c6d26c94: [ARM] Extend MVE lane interleaving to handle other non-instruction leaves
Summary

This extends the MVE lane interleaving from D95804 to handle other non-instruction leaves, for which a new shuffle is added. This helps especially for constants and potentially for arguments.

Diff Detail

Event Timeline

dmgreen created this revision.Feb 23 2021, 7:01 AM
Herald added subscribers: danielkiss, hiraditya, kristof.beyls. · View Herald TranscriptFeb 23 2021, 7:01 AM
dmgreen requested review of this revision.Feb 23 2021, 7:01 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 23 2021, 7:01 AM
dmgreen added a parent revision: D95804: [ARM] MVE vector lane interleaving.Feb 23 2021, 7:01 AM
dmgreen added a child revision: D97291: [ARM] Handle Splats in MVE lane interleaving.Feb 23 2021, 7:08 AM
dmgreen added a comment.Mar 12 2021, 1:34 AM

Ping for this and the related patches, which are hopefully relatively simple extensions to the mve lane interleaving pass.

samtebbs accepted this revision.Mar 25 2021, 7:25 AM

Sorry for not looking at this earlier. It looks like a really good improvement.

This revision is now accepted and ready to land.Mar 25 2021, 7:25 AM
Closed by commit rG3a68c6d26c94: [ARM] Extend MVE lane interleaving to handle other non-instruction leaves (authored by dmgreen). · Explain WhyMar 29 2021, 1:06 AM
This revision was automatically updated to reflect the committed changes.
dmgreen added a commit: rG3a68c6d26c94: [ARM] Extend MVE lane interleaving to handle other non-instruction leaves.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
18 lines
test/
CodeGen/
Thumb2/
168 lines
363 lines
320 lines
304 lines

Diff 333781

llvm/lib/Target/ARM/MVELaneInterleavingPass.cpp

Show First 20 Lines • Show All 156 Lines • ▼ Show 20 Linesstatic bool tryInterleave(Instruction *Start,
// Look for connected operations starting from Ext's, terminating at Truncs. // Look for connected operations starting from Ext's, terminating at Truncs.
std::vector<Instruction *> Worklist; std::vector<Instruction *> Worklist;
Worklist.push_back(Start); Worklist.push_back(Start);
Worklist.push_back(cast<Instruction>(Start->getOperand(0))); Worklist.push_back(cast<Instruction>(Start->getOperand(0)));
SmallSetVector<Instruction *, 4> Truncs; SmallSetVector<Instruction *, 4> Truncs;
SmallSetVector<Instruction *, 4> Exts; SmallSetVector<Instruction *, 4> Exts;
SmallSetVector<Use *, 4> OtherLeafs;
SmallSetVector<Instruction *, 4> Ops; SmallSetVector<Instruction *, 4> Ops;
while (!Worklist.empty()) { while (!Worklist.empty()) {
Instruction *I = Worklist.back(); Instruction *I = Worklist.back();
Worklist.pop_back(); Worklist.pop_back();
switch (I->getOpcode()) { switch (I->getOpcode()) {
// Truncs // Truncs
Show All 26 Lines case Instruction::Select:
if (Ops.count(I)) if (Ops.count(I))
continue; continue;
Ops.insert(I); Ops.insert(I);
for (Use &Op : I->operands()) { for (Use &Op : I->operands()) {
if (isa<Instruction>(Op)) if (isa<Instruction>(Op))
Worklist.push_back(cast<Instruction>(&Op)); Worklist.push_back(cast<Instruction>(&Op));
else else
return false; OtherLeafs.insert(&Op);
} }
for (auto *Use : I->users()) for (auto *Use : I->users())
Worklist.push_back(cast<Instruction>(Use)); Worklist.push_back(cast<Instruction>(Use));
break; break;
default: default:
LLVM_DEBUG(dbgs() << " Unhandled instruction: " << *I << "\n"); LLVM_DEBUG(dbgs() << " Unhandled instruction: " << *I << "\n");
return false; return false;
} }
} }
if (Exts.empty() && OtherLeafs.empty())
return false;
LLVM_DEBUG({ LLVM_DEBUG({
dbgs() << "Found group:\n Exts:"; dbgs() << "Found group:\n Exts:";
for (auto *I : Exts) for (auto *I : Exts)
dbgs() << " " << *I << "\n"; dbgs() << " " << *I << "\n";
dbgs() << " Ops:"; dbgs() << " Ops:";
for (auto *I : Ops) for (auto *I : Ops)
dbgs() << " " << *I << "\n"; dbgs() << " " << *I << "\n";
dbgs() << " OtherLeafs:";
for (auto *I : OtherLeafs)
dbgs() << " " << *I << "\n";
dbgs() << "Truncs:"; dbgs() << "Truncs:";
for (auto *I : Truncs) for (auto *I : Truncs)
dbgs() << " " << *I << "\n"; dbgs() << " " << *I << "\n";
}); });
assert(!Truncs.empty() && "Expected some truncs"); assert(!Truncs.empty() && "Expected some truncs");
assert(!Exts.empty() && "Expected some leaves");
// Check types // Check types
unsigned NumElts = VT->getNumElements(); unsigned NumElts = VT->getNumElements();
unsigned BaseElts = VT->getScalarSizeInBits() == 16 unsigned BaseElts = VT->getScalarSizeInBits() == 16
? 8 ? 8
: (VT->getScalarSizeInBits() == 8 ? 16 : 0); : (VT->getScalarSizeInBits() == 8 ? 16 : 0);
if (BaseElts == 0 || NumElts % BaseElts != 0) { if (BaseElts == 0 || NumElts % BaseElts != 0) {
LLVM_DEBUG(dbgs() << " Type is unsupported\n"); LLVM_DEBUG(dbgs() << " Type is unsupported\n");
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines for (Instruction *I : Exts) {
Value *Shuffle = Builder.CreateShuffleVector(I->getOperand(0), LeafMask); Value *Shuffle = Builder.CreateShuffleVector(I->getOperand(0), LeafMask);
bool Sext = isa<SExtInst>(I); bool Sext = isa<SExtInst>(I);
Value *Ext = Sext ? Builder.CreateSExt(Shuffle, I->getType()) Value *Ext = Sext ? Builder.CreateSExt(Shuffle, I->getType())
: Builder.CreateZExt(Shuffle, I->getType()); : Builder.CreateZExt(Shuffle, I->getType());
I->replaceAllUsesWith(Ext); I->replaceAllUsesWith(Ext);
LLVM_DEBUG(dbgs() << " with " << *Shuffle << "\n"); LLVM_DEBUG(dbgs() << " with " << *Shuffle << "\n");
} }
for (Use *I : OtherLeafs) {
LLVM_DEBUG(dbgs() << "Replacing leaf " << *I << "\n");
Builder.SetInsertPoint(cast<Instruction>(I->getUser()));
Value *Shuffle = Builder.CreateShuffleVector(I->get(), LeafMask);
I->getUser()->setOperand(I->getOperandNo(), Shuffle);
LLVM_DEBUG(dbgs() << " with " << *Shuffle << "\n");
}
for (Instruction *I : Truncs) { for (Instruction *I : Truncs) {
LLVM_DEBUG(dbgs() << "Replacing trunc " << *I << "\n"); LLVM_DEBUG(dbgs() << "Replacing trunc " << *I << "\n");
Builder.SetInsertPoint(I->getParent(), ++I->getIterator()); Builder.SetInsertPoint(I->getParent(), ++I->getIterator());
Value *Shuf = Builder.CreateShuffleVector(I, TruncMask); Value *Shuf = Builder.CreateShuffleVector(I, TruncMask);
I->replaceAllUsesWith(Shuf); I->replaceAllUsesWith(Shuf);
cast<Instruction>(Shuf)->setOperand(0, I); cast<Instruction>(Shuf)->setOperand(0, I);
Show All 26 Lines

llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll

Show First 20 Lines • Show All 232 Lines • ▼ Show 20 Linesentry:
%sh = ashr <4 x i64> %add, <i64 1, i64 1, i64 1, i64 1> %sh = ashr <4 x i64> %add, <i64 1, i64 1, i64 1, i64 1>
%t = trunc <4 x i64> %sh to <4 x i32> %t = trunc <4 x i64> %sh to <4 x i32>
ret <4 x i32> %t ret <4 x i32> %t
} }
define arm_aapcs_vfpcc <8 x i16> @ext_add_ashr_trunc_i16(<8 x i16> %a, <8 x i16> %b) { define arm_aapcs_vfpcc <8 x i16> @ext_add_ashr_trunc_i16(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: ext_add_ashr_trunc_i16: ; CHECK-LABEL: ext_add_ashr_trunc_i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.u16 r0, q1[2] ; CHECK-NEXT: vmovlb.u16 q2, q1
; CHECK-NEXT: vmov.u16 r1, q1[0] ; CHECK-NEXT: vmovlb.s16 q3, q0
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0 ; CHECK-NEXT: vmovlt.u16 q1, q1
; CHECK-NEXT: vmov.u16 r0, q1[3] ; CHECK-NEXT: vmovlt.s16 q0, q0
; CHECK-NEXT: vmov.u16 r1, q1[1]
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
; CHECK-NEXT: vmov.u16 r0, q0[2]
; CHECK-NEXT: vmov.u16 r1, q0[0]
; CHECK-NEXT: vmovlb.u16 q2, q2
; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
; CHECK-NEXT: vmov.u16 r0, q0[3]
; CHECK-NEXT: vmov.u16 r1, q0[1]
; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
; CHECK-NEXT: vmov.u16 r1, q1[4]
; CHECK-NEXT: vmovlb.s16 q3, q3
; CHECK-NEXT: vadd.i32 q2, q3, q2
; CHECK-NEXT: vshr.u32 q3, q2, #1
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmov.16 q2[0], r0
; CHECK-NEXT: vmov r0, s13
; CHECK-NEXT: vmov.16 q2[1], r0
; CHECK-NEXT: vmov r0, s14
; CHECK-NEXT: vmov.16 q2[2], r0
; CHECK-NEXT: vmov r0, s15
; CHECK-NEXT: vmov.16 q2[3], r0
; CHECK-NEXT: vmov.u16 r0, q1[6]
; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
; CHECK-NEXT: vmov.u16 r0, q1[7]
; CHECK-NEXT: vmov.u16 r1, q1[5]
; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
; CHECK-NEXT: vmov.u16 r0, q0[6]
; CHECK-NEXT: vmov.u16 r1, q0[4]
; CHECK-NEXT: vmovlb.u16 q1, q3
; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
; CHECK-NEXT: vmov.u16 r0, q0[7]
; CHECK-NEXT: vmov.u16 r1, q0[5]
; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
; CHECK-NEXT: vmovlb.s16 q0, q3
; CHECK-NEXT: vadd.i32 q0, q0, q1 ; CHECK-NEXT: vadd.i32 q0, q0, q1
; CHECK-NEXT: vshr.u32 q0, q0, #1 ; CHECK-NEXT: vadd.i32 q2, q3, q2
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vshr.u32 q1, q0, #1
; CHECK-NEXT: vmov.16 q2[4], r0 ; CHECK-NEXT: vshr.u32 q0, q2, #1
; CHECK-NEXT: vmov r0, s1 ; CHECK-NEXT: vmovnt.i32 q0, q1
; CHECK-NEXT: vmov.16 q2[5], r0
; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: vmov.16 q2[6], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: vmov.16 q2[7], r0
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%sa = sext <8 x i16> %a to <8 x i32> %sa = sext <8 x i16> %a to <8 x i32>
%sb = zext <8 x i16> %b to <8 x i32> %sb = zext <8 x i16> %b to <8 x i32>
%add = add <8 x i32> %sa, %sb %add = add <8 x i32> %sa, %sb
%sh = ashr <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> %sh = ashr <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
%t = trunc <8 x i32> %sh to <8 x i16> %t = trunc <8 x i32> %sh to <8 x i16>
ret <8 x i16> %t ret <8 x i16> %t
} }
define arm_aapcs_vfpcc <16 x i8> @ext_add_ashr_trunc_i8(<16 x i8> %a, <16 x i8> %b) { define arm_aapcs_vfpcc <16 x i8> @ext_add_ashr_trunc_i8(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: ext_add_ashr_trunc_i8: ; CHECK-LABEL: ext_add_ashr_trunc_i8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.u8 r0, q1[0] ; CHECK-NEXT: vmovlb.u8 q2, q1
; CHECK-NEXT: vmov.16 q2[0], r0 ; CHECK-NEXT: vmovlb.s8 q3, q0
; CHECK-NEXT: vmov.u8 r0, q1[1] ; CHECK-NEXT: vmovlt.u8 q1, q1
; CHECK-NEXT: vmov.16 q2[1], r0 ; CHECK-NEXT: vmovlt.s8 q0, q0
; CHECK-NEXT: vmov.u8 r0, q1[2]
; CHECK-NEXT: vmov.16 q2[2], r0
; CHECK-NEXT: vmov.u8 r0, q1[3]
; CHECK-NEXT: vmov.16 q2[3], r0
; CHECK-NEXT: vmov.u8 r0, q1[4]
; CHECK-NEXT: vmov.16 q2[4], r0
; CHECK-NEXT: vmov.u8 r0, q1[5]
; CHECK-NEXT: vmov.16 q2[5], r0
; CHECK-NEXT: vmov.u8 r0, q1[6]
; CHECK-NEXT: vmov.16 q2[6], r0
; CHECK-NEXT: vmov.u8 r0, q1[7]
; CHECK-NEXT: vmov.16 q2[7], r0
; CHECK-NEXT: vmov.u8 r0, q0[0]
; CHECK-NEXT: vmov.16 q3[0], r0
; CHECK-NEXT: vmov.u8 r0, q0[1]
; CHECK-NEXT: vmov.16 q3[1], r0
; CHECK-NEXT: vmov.u8 r0, q0[2]
; CHECK-NEXT: vmov.16 q3[2], r0
; CHECK-NEXT: vmov.u8 r0, q0[3]
; CHECK-NEXT: vmov.16 q3[3], r0
; CHECK-NEXT: vmov.u8 r0, q0[4]
; CHECK-NEXT: vmov.16 q3[4], r0
; CHECK-NEXT: vmov.u8 r0, q0[5]
; CHECK-NEXT: vmov.16 q3[5], r0
; CHECK-NEXT: vmov.u8 r0, q0[6]
; CHECK-NEXT: vmov.16 q3[6], r0
; CHECK-NEXT: vmov.u8 r0, q0[7]
; CHECK-NEXT: vmov.16 q3[7], r0
; CHECK-NEXT: vmovlb.u8 q2, q2
; CHECK-NEXT: vmovlb.s8 q3, q3
; CHECK-NEXT: vadd.i16 q2, q3, q2
; CHECK-NEXT: vshr.u16 q3, q2, #1
; CHECK-NEXT: vmov.u16 r0, q3[0]
; CHECK-NEXT: vmov.8 q2[0], r0
; CHECK-NEXT: vmov.u16 r0, q3[1]
; CHECK-NEXT: vmov.8 q2[1], r0
; CHECK-NEXT: vmov.u16 r0, q3[2]
; CHECK-NEXT: vmov.8 q2[2], r0
; CHECK-NEXT: vmov.u16 r0, q3[3]
; CHECK-NEXT: vmov.8 q2[3], r0
; CHECK-NEXT: vmov.u16 r0, q3[4]
; CHECK-NEXT: vmov.8 q2[4], r0
; CHECK-NEXT: vmov.u16 r0, q3[5]
; CHECK-NEXT: vmov.8 q2[5], r0
; CHECK-NEXT: vmov.u16 r0, q3[6]
; CHECK-NEXT: vmov.8 q2[6], r0
; CHECK-NEXT: vmov.u16 r0, q3[7]
; CHECK-NEXT: vmov.8 q2[7], r0
; CHECK-NEXT: vmov.u8 r0, q1[8]
; CHECK-NEXT: vmov.16 q3[0], r0
; CHECK-NEXT: vmov.u8 r0, q1[9]
; CHECK-NEXT: vmov.16 q3[1], r0
; CHECK-NEXT: vmov.u8 r0, q1[10]
; CHECK-NEXT: vmov.16 q3[2], r0
; CHECK-NEXT: vmov.u8 r0, q1[11]
; CHECK-NEXT: vmov.16 q3[3], r0
; CHECK-NEXT: vmov.u8 r0, q1[12]
; CHECK-NEXT: vmov.16 q3[4], r0
; CHECK-NEXT: vmov.u8 r0, q1[13]
; CHECK-NEXT: vmov.16 q3[5], r0
; CHECK-NEXT: vmov.u8 r0, q1[14]
; CHECK-NEXT: vmov.16 q3[6], r0
; CHECK-NEXT: vmov.u8 r0, q1[15]
; CHECK-NEXT: vmov.16 q3[7], r0
; CHECK-NEXT: vmov.u8 r0, q0[8]
; CHECK-NEXT: vmovlb.u8 q1, q3
; CHECK-NEXT: vmov.16 q3[0], r0
; CHECK-NEXT: vmov.u8 r0, q0[9]
; CHECK-NEXT: vmov.16 q3[1], r0
; CHECK-NEXT: vmov.u8 r0, q0[10]
; CHECK-NEXT: vmov.16 q3[2], r0
; CHECK-NEXT: vmov.u8 r0, q0[11]
; CHECK-NEXT: vmov.16 q3[3], r0
; CHECK-NEXT: vmov.u8 r0, q0[12]
; CHECK-NEXT: vmov.16 q3[4], r0
; CHECK-NEXT: vmov.u8 r0, q0[13]
; CHECK-NEXT: vmov.16 q3[5], r0
; CHECK-NEXT: vmov.u8 r0, q0[14]
; CHECK-NEXT: vmov.16 q3[6], r0
; CHECK-NEXT: vmov.u8 r0, q0[15]
; CHECK-NEXT: vmov.16 q3[7], r0
; CHECK-NEXT: vmovlb.s8 q0, q3
; CHECK-NEXT: vadd.i16 q0, q0, q1 ; CHECK-NEXT: vadd.i16 q0, q0, q1
; CHECK-NEXT: vshr.u16 q0, q0, #1 ; CHECK-NEXT: vadd.i16 q2, q3, q2
; CHECK-NEXT: vmov.u16 r0, q0[0] ; CHECK-NEXT: vshr.u16 q1, q0, #1
; CHECK-NEXT: vmov.8 q2[8], r0 ; CHECK-NEXT: vshr.u16 q0, q2, #1
; CHECK-NEXT: vmov.u16 r0, q0[1] ; CHECK-NEXT: vmovnt.i16 q0, q1
; CHECK-NEXT: vmov.8 q2[9], r0
; CHECK-NEXT: vmov.u16 r0, q0[2]
; CHECK-NEXT: vmov.8 q2[10], r0
; CHECK-NEXT: vmov.u16 r0, q0[3]
; CHECK-NEXT: vmov.8 q2[11], r0
; CHECK-NEXT: vmov.u16 r0, q0[4]
; CHECK-NEXT: vmov.8 q2[12], r0
; CHECK-NEXT: vmov.u16 r0, q0[5]
; CHECK-NEXT: vmov.8 q2[13], r0
; CHECK-NEXT: vmov.u16 r0, q0[6]
; CHECK-NEXT: vmov.8 q2[14], r0
; CHECK-NEXT: vmov.u16 r0, q0[7]
; CHECK-NEXT: vmov.8 q2[15], r0
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%sa = sext <16 x i8> %a to <16 x i16> %sa = sext <16 x i8> %a to <16 x i16>
%sb = zext <16 x i8> %b to <16 x i16> %sb = zext <16 x i8> %b to <16 x i16>
%add = add <16 x i16> %sa, %sb %add = add <16 x i16> %sa, %sb
%sh = ashr <16 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> %sh = ashr <16 x i16> %add, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
%t = trunc <16 x i16> %sh to <16 x i8> %t = trunc <16 x i16> %sh to <16 x i8>
ret <16 x i8> %t ret <16 x i8> %t
▲ Show 20 Lines • Show All 519 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll

Show First 20 Lines • Show All 1,180 Lines • ▼ Show 20 Linesfor.body: ; preds = %for.body.preheader21, %for.body
br i1 %exitcond, label %for.cond.cleanup, label %for.body br i1 %exitcond, label %for.cond.cleanup, label %for.body
} }
define arm_aapcs_vfpcc void @ssatmul_8_q15(i16* nocapture readonly %pSrcA, i16* nocapture readonly %pSrcB, i16* noalias nocapture %pDst, i32 %N) { define arm_aapcs_vfpcc void @ssatmul_8_q15(i16* nocapture readonly %pSrcA, i16* nocapture readonly %pSrcB, i16* noalias nocapture %pDst, i32 %N) {
; CHECK-LABEL: ssatmul_8_q15: ; CHECK-LABEL: ssatmul_8_q15:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, lr} ; CHECK-NEXT: .save {r4, r5, r6, lr}
; CHECK-NEXT: push {r4, r5, r6, lr} ; CHECK-NEXT: push {r4, r5, r6, lr}
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cbz r3, .LBB6_8
; CHECK-NEXT: beq .LBB6_8
; CHECK-NEXT: @ %bb.1: @ %for.body.preheader ; CHECK-NEXT: @ %bb.1: @ %for.body.preheader
; CHECK-NEXT: cmp r3, #7 ; CHECK-NEXT: cmp r3, #7
; CHECK-NEXT: bhi .LBB6_3 ; CHECK-NEXT: bhi .LBB6_3
; CHECK-NEXT: @ %bb.2: ; CHECK-NEXT: @ %bb.2:
; CHECK-NEXT: movs r5, #0 ; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: mov r12, r0 ; CHECK-NEXT: mov r12, r0
; CHECK-NEXT: mov r6, r1 ; CHECK-NEXT: mov r6, r1
; CHECK-NEXT: mov r4, r2 ; CHECK-NEXT: mov r4, r2
; CHECK-NEXT: b .LBB6_6 ; CHECK-NEXT: b .LBB6_6
; CHECK-NEXT: .LBB6_3: @ %vector.ph ; CHECK-NEXT: .LBB6_3: @ %vector.ph
; CHECK-NEXT: bic r5, r3, #7 ; CHECK-NEXT: bic r5, r3, #7
; CHECK-NEXT: movs r4, #1 ; CHECK-NEXT: movs r4, #1
; CHECK-NEXT: sub.w r6, r5, #8 ; CHECK-NEXT: sub.w r6, r5, #8
; CHECK-NEXT: add.w r12, r0, r5, lsl #1 ; CHECK-NEXT: add.w r12, r0, r5, lsl #1
; CHECK-NEXT: add.w lr, r4, r6, lsr #3 ; CHECK-NEXT: add.w lr, r4, r6, lsr #3
; CHECK-NEXT: add.w r4, r2, r5, lsl #1 ; CHECK-NEXT: add.w r4, r2, r5, lsl #1
; CHECK-NEXT: add.w r6, r1, r5, lsl #1 ; CHECK-NEXT: add.w r6, r1, r5, lsl #1
; CHECK-NEXT: .LBB6_4: @ %vector.body ; CHECK-NEXT: .LBB6_4: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrh.s32 q0, [r0, #8] ; CHECK-NEXT: vldrh.u16 q0, [r0], #16
; CHECK-NEXT: vldrh.s32 q1, [r1, #8] ; CHECK-NEXT: vldrh.u16 q1, [r1], #16
; CHECK-NEXT: vmul.i32 q0, q1, q0 ; CHECK-NEXT: vmullt.s16 q2, q1, q0
; CHECK-NEXT: vldrh.s32 q1, [r1], #16 ; CHECK-NEXT: vmullb.s16 q0, q1, q0
; CHECK-NEXT: vqshrnb.s32 q0, q0, #15
; CHECK-NEXT: vstrh.32 q0, [r2, #8]
; CHECK-NEXT: vldrh.s32 q0, [r0], #16
; CHECK-NEXT: vmul.i32 q0, q1, q0
; CHECK-NEXT: vqshrnb.s32 q0, q0, #15 ; CHECK-NEXT: vqshrnb.s32 q0, q0, #15
; CHECK-NEXT: vstrh.32 q0, [r2], #16 ; CHECK-NEXT: vqshrnt.s32 q0, q2, #15
; CHECK-NEXT: vstrb.8 q0, [r2], #16
; CHECK-NEXT: le lr, .LBB6_4 ; CHECK-NEXT: le lr, .LBB6_4
; CHECK-NEXT: @ %bb.5: @ %middle.block ; CHECK-NEXT: @ %bb.5: @ %middle.block
; CHECK-NEXT: cmp r5, r3 ; CHECK-NEXT: cmp r5, r3
; CHECK-NEXT: it eq ; CHECK-NEXT: it eq
; CHECK-NEXT: popeq {r4, r5, r6, pc} ; CHECK-NEXT: popeq {r4, r5, r6, pc}
; CHECK-NEXT: .LBB6_6: @ %for.body.preheader21 ; CHECK-NEXT: .LBB6_6: @ %for.body.preheader21
; CHECK-NEXT: sub.w lr, r3, r5 ; CHECK-NEXT: sub.w lr, r3, r5
; CHECK-NEXT: .LBB6_7: @ %for.body ; CHECK-NEXT: .LBB6_7: @ %for.body
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for.cond.cleanup: ; preds = %vector.body, %entry for.cond.cleanup: ; preds = %vector.body, %entry
ret void ret void
} }
define arm_aapcs_vfpcc void @ssatmul_8t_q15(i16* nocapture readonly %pSrcA, i16* nocapture readonly %pSrcB, i16* noalias nocapture %pDst, i32 %N) { define arm_aapcs_vfpcc void @ssatmul_8t_q15(i16* nocapture readonly %pSrcA, i16* nocapture readonly %pSrcB, i16* noalias nocapture %pDst, i32 %N) {
; CHECK-LABEL: ssatmul_8t_q15: ; CHECK-LABEL: ssatmul_8t_q15:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r7, lr} ; CHECK-NEXT: .save {r4, lr}
; CHECK-NEXT: push {r4, r5, r7, lr} ; CHECK-NEXT: push {r4, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #16
; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: beq.w .LBB9_3 ; CHECK-NEXT: beq .LBB9_3
; CHECK-NEXT: @ %bb.1: @ %vector.ph ; CHECK-NEXT: @ %bb.1: @ %vector.ph
; CHECK-NEXT: add.w r12, r3, #7 ; CHECK-NEXT: add.w r12, r3, #7
; CHECK-NEXT: adr r4, .LCPI9_0 ; CHECK-NEXT: adr r4, .LCPI9_0
; CHECK-NEXT: bic r12, r12, #7 ; CHECK-NEXT: bic r12, r12, #7
; CHECK-NEXT: mov.w lr, #1 ; CHECK-NEXT: mov.w lr, #1
; CHECK-NEXT: sub.w r12, r12, #8 ; CHECK-NEXT: sub.w r12, r12, #8
; CHECK-NEXT: vldrw.u32 q0, [r4] ; CHECK-NEXT: vldrw.u32 q0, [r4]
; CHECK-NEXT: adr r4, .LCPI9_1 ; CHECK-NEXT: adr r4, .LCPI9_1
; CHECK-NEXT: movs r5, #0 ; CHECK-NEXT: vmov.i8 q2, #0x0
; CHECK-NEXT: add.w lr, lr, r12, lsr #3 ; CHECK-NEXT: add.w lr, lr, r12, lsr #3
; CHECK-NEXT: sub.w r12, r3, #1 ; CHECK-NEXT: sub.w r12, r3, #1
; CHECK-NEXT: vldrw.u32 q4, [r4] ; CHECK-NEXT: vldrw.u32 q4, [r4]
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: vdup.32 q1, r12 ; CHECK-NEXT: vdup.32 q1, r12
; CHECK-NEXT: vmov.i8 q2, #0x0
; CHECK-NEXT: vmov.i8 q3, #0xff ; CHECK-NEXT: vmov.i8 q3, #0xff
; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill
; CHECK-NEXT: .LBB9_2: @ %vector.body ; CHECK-NEXT: .LBB9_2: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q0, [sp] @ 16-byte Reload ; CHECK-NEXT: vdup.32 q6, r3
; CHECK-NEXT: vdup.32 q6, r5 ; CHECK-NEXT: adds r3, #8
; CHECK-NEXT: adds r5, #8
; CHECK-NEXT: vorr q5, q6, q0 ; CHECK-NEXT: vorr q5, q6, q0
; CHECK-NEXT: vorr q6, q6, q4 ; CHECK-NEXT: vorr q6, q6, q4
; CHECK-NEXT: vcmp.u32 cs, q1, q5 ; CHECK-NEXT: vcmp.u32 cs, q1, q5
; CHECK-NEXT: vpsel q7, q3, q2 ; CHECK-NEXT: vpsel q7, q3, q2
; CHECK-NEXT: vcmp.u32 cs, q1, q6 ; CHECK-NEXT: vcmp.u32 cs, q1, q6
; CHECK-NEXT: vmov r4, s28 ; CHECK-NEXT: vmov r4, s28
; CHECK-NEXT: vpsel q6, q3, q2 ; CHECK-NEXT: vpsel q6, q3, q2
; CHECK-NEXT: vmov.16 q5[0], r4 ; CHECK-NEXT: vmov.16 q5[0], r4
; CHECK-NEXT: vmov r4, s29 ; CHECK-NEXT: vmov r4, s29
; CHECK-NEXT: vmov.16 q5[1], r4 ; CHECK-NEXT: vmov.16 q5[1], r4
; CHECK-NEXT: vmov r4, s30 ; CHECK-NEXT: vmov r4, s30
; CHECK-NEXT: vmov.16 q5[2], r4 ; CHECK-NEXT: vmov.16 q5[2], r4
; CHECK-NEXT: vmov r4, s31 ; CHECK-NEXT: vmov r4, s31
; CHECK-NEXT: vmov.16 q5[3], r4 ; CHECK-NEXT: vmov.16 q5[3], r4
; CHECK-NEXT: vmov r4, s24 ; CHECK-NEXT: vmov r4, s24
; CHECK-NEXT: vmov.16 q5[4], r4 ; CHECK-NEXT: vmov.16 q5[4], r4
; CHECK-NEXT: vmov r4, s25 ; CHECK-NEXT: vmov r4, s25
; CHECK-NEXT: vmov.16 q5[5], r4 ; CHECK-NEXT: vmov.16 q5[5], r4
; CHECK-NEXT: vmov r4, s26 ; CHECK-NEXT: vmov r4, s26
; CHECK-NEXT: vmov.16 q5[6], r4 ; CHECK-NEXT: vmov.16 q5[6], r4
; CHECK-NEXT: vmov r4, s27 ; CHECK-NEXT: vmov r4, s27
; CHECK-NEXT: vmov.16 q5[7], r4 ; CHECK-NEXT: vmov.16 q5[7], r4
; CHECK-NEXT: vpt.i16 ne, q5, zr ; CHECK-NEXT: vptt.i16 ne, q5, zr
; CHECK-NEXT: vldrht.u16 q6, [r0], #16 ; CHECK-NEXT: vldrht.u16 q5, [r0], #16
; CHECK-NEXT: vmov.u16 r4, q6[2] ; CHECK-NEXT: vldrht.u16 q6, [r1], #16
; CHECK-NEXT: vmov.u16 r3, q6[0] ; CHECK-NEXT: vmullt.s16 q7, q6, q5
; CHECK-NEXT: vmov q5[2], q5[0], r3, r4 ; CHECK-NEXT: vmullb.s16 q5, q6, q5
; CHECK-NEXT: vmov.u16 r3, q6[3] ; CHECK-NEXT: vqshrnb.s32 q5, q5, #15
; CHECK-NEXT: vmov.u16 r4, q6[1] ; CHECK-NEXT: vqshrnt.s32 q5, q7, #15
; CHECK-NEXT: vpst
; CHECK-NEXT: vldrht.u16 q7, [r1], #16
; CHECK-NEXT: vmov q5[3], q5[1], r4, r3
; CHECK-NEXT: vmov.u16 r3, q7[2]
; CHECK-NEXT: vmov.u16 r4, q7[0]
; CHECK-NEXT: vmov q0[2], q0[0], r4, r3
; CHECK-NEXT: vmov.u16 r3, q7[3]
; CHECK-NEXT: vmov.u16 r4, q7[1]
; CHECK-NEXT: vmov q0[3], q0[1], r4, r3
; CHECK-NEXT: vmov.u16 r4, q6[4]
; CHECK-NEXT: vmullb.s16 q0, q0, q5
; CHECK-NEXT: vqshrnb.s32 q0, q0, #15
; CHECK-NEXT: vmovlb.s16 q0, q0
; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vmov.16 q5[0], r3
; CHECK-NEXT: vmov r3, s1
; CHECK-NEXT: vmov.16 q5[1], r3
; CHECK-NEXT: vmov r3, s2
; CHECK-NEXT: vmov.16 q5[2], r3
; CHECK-NEXT: vmov r3, s3
; CHECK-NEXT: vmov.16 q5[3], r3
; CHECK-NEXT: vmov.u16 r3, q6[6]
; CHECK-NEXT: vmov q0[2], q0[0], r4, r3
; CHECK-NEXT: vmov.u16 r3, q6[7]
; CHECK-NEXT: vmov.u16 r4, q6[5]
; CHECK-NEXT: vmov q0[3], q0[1], r4, r3
; CHECK-NEXT: vmov.u16 r3, q7[6]
; CHECK-NEXT: vmov.u16 r4, q7[4]
; CHECK-NEXT: vmov q6[2], q6[0], r4, r3
; CHECK-NEXT: vmov.u16 r3, q7[7]
; CHECK-NEXT: vmov.u16 r4, q7[5]
; CHECK-NEXT: vmov q6[3], q6[1], r4, r3
; CHECK-NEXT: vmullb.s16 q0, q6, q0
; CHECK-NEXT: vqshrnb.s32 q0, q0, #15
; CHECK-NEXT: vmovlb.s16 q0, q0
; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vmov.16 q5[4], r3
; CHECK-NEXT: vmov r3, s1
; CHECK-NEXT: vmov.16 q5[5], r3
; CHECK-NEXT: vmov r3, s2
; CHECK-NEXT: vmov.16 q5[6], r3
; CHECK-NEXT: vmov r3, s3
; CHECK-NEXT: vmov.16 q5[7], r3
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vstrht.16 q5, [r2], #16 ; CHECK-NEXT: vstrht.16 q5, [r2], #16
; CHECK-NEXT: le lr, .LBB9_2 ; CHECK-NEXT: le lr, .LBB9_2
; CHECK-NEXT: .LBB9_3: @ %for.cond.cleanup ; CHECK-NEXT: .LBB9_3: @ %for.cond.cleanup
; CHECK-NEXT: add sp, #16
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: pop {r4, r5, r7, pc} ; CHECK-NEXT: pop {r4, pc}
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: @ %bb.4: ; CHECK-NEXT: @ %bb.4:
; CHECK-NEXT: .LCPI9_0: ; CHECK-NEXT: .LCPI9_0:
; CHECK-NEXT: .long 0 @ 0x0 ; CHECK-NEXT: .long 0 @ 0x0
; CHECK-NEXT: .long 1 @ 0x1 ; CHECK-NEXT: .long 1 @ 0x1
; CHECK-NEXT: .long 2 @ 0x2 ; CHECK-NEXT: .long 2 @ 0x2
; CHECK-NEXT: .long 3 @ 0x3 ; CHECK-NEXT: .long 3 @ 0x3
; CHECK-NEXT: .LCPI9_1: ; CHECK-NEXT: .LCPI9_1:
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; CHECK-NEXT: movs r4, #1 ; CHECK-NEXT: movs r4, #1
; CHECK-NEXT: sub.w r6, r5, #8 ; CHECK-NEXT: sub.w r6, r5, #8
; CHECK-NEXT: add.w r12, r0, r5, lsl #1 ; CHECK-NEXT: add.w r12, r0, r5, lsl #1
; CHECK-NEXT: add.w lr, r4, r6, lsr #3 ; CHECK-NEXT: add.w lr, r4, r6, lsr #3
; CHECK-NEXT: add.w r4, r2, r5, lsl #1 ; CHECK-NEXT: add.w r4, r2, r5, lsl #1
; CHECK-NEXT: add.w r6, r1, r5, lsl #1 ; CHECK-NEXT: add.w r6, r1, r5, lsl #1
; CHECK-NEXT: .LBB12_4: @ %vector.body ; CHECK-NEXT: .LBB12_4: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrh.u32 q0, [r0, #8] ; CHECK-NEXT: vldrh.u16 q0, [r0], #16
; CHECK-NEXT: vldrh.u32 q1, [r1, #8] ; CHECK-NEXT: vldrh.u16 q1, [r1], #16
; CHECK-NEXT: vmul.i32 q0, q1, q0 ; CHECK-NEXT: vmullt.u16 q2, q1, q0
; CHECK-NEXT: vldrh.u32 q1, [r1], #16 ; CHECK-NEXT: vmullb.u16 q0, q1, q0
; CHECK-NEXT: vqshrnb.u32 q0, q0, #15 ; CHECK-NEXT: vqshrnb.u32 q2, q2, #15
; CHECK-NEXT: vstrh.32 q0, [r2, #8]
; CHECK-NEXT: vldrh.u32 q0, [r0], #16
; CHECK-NEXT: vmul.i32 q0, q1, q0
; CHECK-NEXT: vqshrnb.u32 q0, q0, #15 ; CHECK-NEXT: vqshrnb.u32 q0, q0, #15
; CHECK-NEXT: vstrh.32 q0, [r2], #16 ; CHECK-NEXT: vmovlb.u16 q2, q2
; CHECK-NEXT: vmovlb.u16 q0, q0
; CHECK-NEXT: vmovnt.i32 q0, q2
; CHECK-NEXT: vstrb.8 q0, [r2], #16
; CHECK-NEXT: le lr, .LBB12_4 ; CHECK-NEXT: le lr, .LBB12_4
; CHECK-NEXT: @ %bb.5: @ %middle.block ; CHECK-NEXT: @ %bb.5: @ %middle.block
; CHECK-NEXT: cmp r5, r3 ; CHECK-NEXT: cmp r5, r3
; CHECK-NEXT: it eq ; CHECK-NEXT: it eq
; CHECK-NEXT: popeq {r4, r5, r6, pc} ; CHECK-NEXT: popeq {r4, r5, r6, pc}
; CHECK-NEXT: .LBB12_6: @ %for.body.preheader21 ; CHECK-NEXT: .LBB12_6: @ %for.body.preheader21
; CHECK-NEXT: sub.w lr, r3, r5 ; CHECK-NEXT: sub.w lr, r3, r5
; CHECK-NEXT: movw r0, #65535 ; CHECK-NEXT: movw r0, #65535
▲ Show 20 Lines • Show All 343 Lines • ▼ Show 20 Linesfor.body: ; preds = %for.body.preheader23, %for.body
br i1 %exitcond, label %for.cond.cleanup, label %for.body br i1 %exitcond, label %for.cond.cleanup, label %for.body
} }
define arm_aapcs_vfpcc void @ssatmul_16_q7(i8* nocapture readonly %pSrcA, i8* nocapture readonly %pSrcB, i8* noalias nocapture %pDst, i32 %N) { define arm_aapcs_vfpcc void @ssatmul_16_q7(i8* nocapture readonly %pSrcA, i8* nocapture readonly %pSrcB, i8* noalias nocapture %pDst, i32 %N) {
; CHECK-LABEL: ssatmul_16_q7: ; CHECK-LABEL: ssatmul_16_q7:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, r5, r6, lr} ; CHECK-NEXT: .save {r4, r5, r6, lr}
; CHECK-NEXT: push {r4, r5, r6, lr} ; CHECK-NEXT: push {r4, r5, r6, lr}
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cbz r3, .LBB15_8
; CHECK-NEXT: beq .LBB15_8
; CHECK-NEXT: @ %bb.1: @ %for.body.preheader ; CHECK-NEXT: @ %bb.1: @ %for.body.preheader
; CHECK-NEXT: cmp r3, #15 ; CHECK-NEXT: cmp r3, #15
; CHECK-NEXT: bhi .LBB15_3 ; CHECK-NEXT: bhi .LBB15_3
; CHECK-NEXT: @ %bb.2: ; CHECK-NEXT: @ %bb.2:
; CHECK-NEXT: movs r5, #0 ; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: mov r12, r0 ; CHECK-NEXT: mov r12, r0
; CHECK-NEXT: mov r6, r1 ; CHECK-NEXT: mov r6, r1
; CHECK-NEXT: mov r4, r2 ; CHECK-NEXT: mov r4, r2
; CHECK-NEXT: b .LBB15_6 ; CHECK-NEXT: b .LBB15_6
; CHECK-NEXT: .LBB15_3: @ %vector.ph ; CHECK-NEXT: .LBB15_3: @ %vector.ph
; CHECK-NEXT: bic r5, r3, #15 ; CHECK-NEXT: bic r5, r3, #15
; CHECK-NEXT: movs r4, #1 ; CHECK-NEXT: movs r4, #1
; CHECK-NEXT: sub.w r6, r5, #16 ; CHECK-NEXT: sub.w r6, r5, #16
; CHECK-NEXT: add.w r12, r0, r5 ; CHECK-NEXT: add.w r12, r0, r5
; CHECK-NEXT: add.w lr, r4, r6, lsr #4 ; CHECK-NEXT: add.w lr, r4, r6, lsr #4
; CHECK-NEXT: adds r4, r2, r5 ; CHECK-NEXT: adds r4, r2, r5
; CHECK-NEXT: adds r6, r1, r5 ; CHECK-NEXT: adds r6, r1, r5
; CHECK-NEXT: .LBB15_4: @ %vector.body ; CHECK-NEXT: .LBB15_4: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrb.s16 q0, [r0, #8] ; CHECK-NEXT: vldrb.u8 q0, [r0], #16
; CHECK-NEXT: vldrb.s16 q1, [r1, #8] ; CHECK-NEXT: vldrb.u8 q1, [r1], #16
; CHECK-NEXT: vmul.i16 q0, q1, q0 ; CHECK-NEXT: vmullt.s8 q2, q1, q0
; CHECK-NEXT: vldrb.s16 q1, [r1], #16 ; CHECK-NEXT: vmullb.s8 q0, q1, q0
; CHECK-NEXT: vqshrnb.s16 q0, q0, #7
; CHECK-NEXT: vstrb.16 q0, [r2, #8]
; CHECK-NEXT: vldrb.s16 q0, [r0], #16
; CHECK-NEXT: vmul.i16 q0, q1, q0
; CHECK-NEXT: vqshrnb.s16 q0, q0, #7 ; CHECK-NEXT: vqshrnb.s16 q0, q0, #7
; CHECK-NEXT: vstrb.16 q0, [r2], #16 ; CHECK-NEXT: vqshrnt.s16 q0, q2, #7
; CHECK-NEXT: vstrb.8 q0, [r2], #16
; CHECK-NEXT: le lr, .LBB15_4 ; CHECK-NEXT: le lr, .LBB15_4
; CHECK-NEXT: @ %bb.5: @ %middle.block ; CHECK-NEXT: @ %bb.5: @ %middle.block
; CHECK-NEXT: cmp r5, r3 ; CHECK-NEXT: cmp r5, r3
; CHECK-NEXT: it eq ; CHECK-NEXT: it eq
; CHECK-NEXT: popeq {r4, r5, r6, pc} ; CHECK-NEXT: popeq {r4, r5, r6, pc}
; CHECK-NEXT: .LBB15_6: @ %for.body.preheader23 ; CHECK-NEXT: .LBB15_6: @ %for.body.preheader23
; CHECK-NEXT: sub.w lr, r3, r5 ; CHECK-NEXT: sub.w lr, r3, r5
; CHECK-NEXT: .LBB15_7: @ %for.body ; CHECK-NEXT: .LBB15_7: @ %for.body
▲ Show 20 Lines • Show All 371 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill
; CHECK-NEXT: vldrw.u32 q0, [r4] ; CHECK-NEXT: vldrw.u32 q0, [r4]
; CHECK-NEXT: adr r4, .LCPI18_3 ; CHECK-NEXT: adr r4, .LCPI18_3
; CHECK-NEXT: vmov.i8 q3, #0xff ; CHECK-NEXT: vmov.i8 q3, #0xff
; CHECK-NEXT: vldrw.u32 q6, [r4] ; CHECK-NEXT: vldrw.u32 q6, [r4]
; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill ; CHECK-NEXT: vstrw.32 q0, [sp] @ 16-byte Spill
; CHECK-NEXT: .LBB18_2: @ %vector.body ; CHECK-NEXT: .LBB18_2: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrw.u32 q0, [sp, #32] @ 16-byte Reload ; CHECK-NEXT: vldrw.u32 q4, [sp, #32] @ 16-byte Reload
; CHECK-NEXT: vdup.32 q4, r3 ; CHECK-NEXT: vdup.32 q0, r3
; CHECK-NEXT: adds r3, #16 ; CHECK-NEXT: adds r3, #16
; CHECK-NEXT: vorr q0, q4, q0 ; CHECK-NEXT: vorr q4, q0, q4
; CHECK-NEXT: vcmp.u32 cs, q1, q0
; CHECK-NEXT: vpsel q5, q3, q2
; CHECK-NEXT: vmov r4, s20
; CHECK-NEXT: vmov.16 q0[0], r4
; CHECK-NEXT: vmov r4, s21
; CHECK-NEXT: vmov.16 q0[1], r4
; CHECK-NEXT: vmov r4, s22
; CHECK-NEXT: vmov.16 q0[2], r4
; CHECK-NEXT: vmov r4, s23
; CHECK-NEXT: vldrw.u32 q5, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vmov.16 q0[3], r4
; CHECK-NEXT: vorr q5, q4, q5
; CHECK-NEXT: vcmp.u32 cs, q1, q5
; CHECK-NEXT: vpsel q5, q3, q2
; CHECK-NEXT: vmov r4, s20
; CHECK-NEXT: vmov.16 q0[4], r4
; CHECK-NEXT: vmov r4, s21
; CHECK-NEXT: vmov.16 q0[5], r4
; CHECK-NEXT: vmov r4, s22
; CHECK-NEXT: vmov.16 q0[6], r4
; CHECK-NEXT: vmov r4, s23
; CHECK-NEXT: vmov.16 q0[7], r4
; CHECK-NEXT: vcmp.i16 ne, q0, zr
; CHECK-NEXT: vpsel q5, q3, q2
; CHECK-NEXT: vmov.u16 r4, q5[0]
; CHECK-NEXT: vmov.8 q0[0], r4
; CHECK-NEXT: vmov.u16 r4, q5[1]
; CHECK-NEXT: vmov.8 q0[1], r4
; CHECK-NEXT: vmov.u16 r4, q5[2]
; CHECK-NEXT: vmov.8 q0[2], r4
; CHECK-NEXT: vmov.u16 r4, q5[3]
; CHECK-NEXT: vmov.8 q0[3], r4
; CHECK-NEXT: vmov.u16 r4, q5[4]
; CHECK-NEXT: vmov.8 q0[4], r4
; CHECK-NEXT: vmov.u16 r4, q5[5]
; CHECK-NEXT: vmov.8 q0[5], r4
; CHECK-NEXT: vmov.u16 r4, q5[6]
; CHECK-NEXT: vmov.8 q0[6], r4
; CHECK-NEXT: vmov.u16 r4, q5[7]
; CHECK-NEXT: vldrw.u32 q5, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.8 q0[7], r4
; CHECK-NEXT: vorr q5, q4, q5
; CHECK-NEXT: vorr q4, q4, q6
; CHECK-NEXT: vcmp.u32 cs, q1, q5
; CHECK-NEXT: vpsel q7, q3, q2
; CHECK-NEXT: vcmp.u32 cs, q1, q4 ; CHECK-NEXT: vcmp.u32 cs, q1, q4
; CHECK-NEXT: vmov r4, s28
; CHECK-NEXT: vpsel q4, q3, q2 ; CHECK-NEXT: vpsel q4, q3, q2
; CHECK-NEXT: vmov.16 q5[0], r4
; CHECK-NEXT: vmov r4, s29
; CHECK-NEXT: vmov.16 q5[1], r4
; CHECK-NEXT: vmov r4, s30
; CHECK-NEXT: vmov.16 q5[2], r4
; CHECK-NEXT: vmov r4, s31
; CHECK-NEXT: vmov.16 q5[3], r4
; CHECK-NEXT: vmov r4, s16 ; CHECK-NEXT: vmov r4, s16
; CHECK-NEXT: vmov.16 q5[4], r4
; CHECK-NEXT: vmov r4, s17
; CHECK-NEXT: vmov.16 q5[5], r4
; CHECK-NEXT: vmov r4, s18
; CHECK-NEXT: vmov.16 q5[6], r4
; CHECK-NEXT: vmov r4, s19
; CHECK-NEXT: vmov.16 q5[7], r4
; CHECK-NEXT: vcmp.i16 ne, q5, zr
; CHECK-NEXT: vpsel q4, q3, q2
; CHECK-NEXT: vmov.u16 r4, q4[0]
; CHECK-NEXT: vmov.8 q0[8], r4
; CHECK-NEXT: vmov.u16 r4, q4[1]
; CHECK-NEXT: vmov.8 q0[9], r4
; CHECK-NEXT: vmov.u16 r4, q4[2]
; CHECK-NEXT: vmov.8 q0[10], r4
; CHECK-NEXT: vmov.u16 r4, q4[3]
; CHECK-NEXT: vmov.8 q0[11], r4
; CHECK-NEXT: vmov.u16 r4, q4[4]
; CHECK-NEXT: vmov.8 q0[12], r4
; CHECK-NEXT: vmov.u16 r4, q4[5]
; CHECK-NEXT: vmov.8 q0[13], r4
; CHECK-NEXT: vmov.u16 r4, q4[6]
; CHECK-NEXT: vmov.8 q0[14], r4
; CHECK-NEXT: vmov.u16 r4, q4[7]
; CHECK-NEXT: vmov.8 q0[15], r4
; CHECK-NEXT: vpt.i8 ne, q0, zr
; CHECK-NEXT: vldrbt.u8 q0, [r0], #16
; CHECK-NEXT: vmov.u8 r4, q0[0]
; CHECK-NEXT: vmov.16 q7[0], r4 ; CHECK-NEXT: vmov.16 q7[0], r4
; CHECK-NEXT: vmov.u8 r4, q0[1] ; CHECK-NEXT: vmov r4, s17
; CHECK-NEXT: vmov.16 q7[1], r4 ; CHECK-NEXT: vmov.16 q7[1], r4
; CHECK-NEXT: vmov.u8 r4, q0[2] ; CHECK-NEXT: vmov r4, s18
; CHECK-NEXT: vmov.16 q7[2], r4 ; CHECK-NEXT: vmov.16 q7[2], r4
; CHECK-NEXT: vmov.u8 r4, q0[3] ; CHECK-NEXT: vmov r4, s19
; CHECK-NEXT: vldrw.u32 q4, [sp, #16] @ 16-byte Reload
; CHECK-NEXT: vmov.16 q7[3], r4 ; CHECK-NEXT: vmov.16 q7[3], r4
; CHECK-NEXT: vmov.u8 r4, q0[4] ; CHECK-NEXT: vorr q4, q0, q4
; CHECK-NEXT: vcmp.u32 cs, q1, q4
; CHECK-NEXT: vpsel q4, q3, q2
; CHECK-NEXT: vmov r4, s16
; CHECK-NEXT: vmov.16 q7[4], r4 ; CHECK-NEXT: vmov.16 q7[4], r4
; CHECK-NEXT: vmov.u8 r4, q0[5] ; CHECK-NEXT: vmov r4, s17
; CHECK-NEXT: vmov.16 q7[5], r4 ; CHECK-NEXT: vmov.16 q7[5], r4
; CHECK-NEXT: vmov.u8 r4, q0[6] ; CHECK-NEXT: vmov r4, s18
; CHECK-NEXT: vmov.16 q7[6], r4 ; CHECK-NEXT: vmov.16 q7[6], r4
; CHECK-NEXT: vmov.u8 r4, q0[7] ; CHECK-NEXT: vmov r4, s19
; CHECK-NEXT: vmov.16 q7[7], r4 ; CHECK-NEXT: vmov.16 q7[7], r4
; CHECK-NEXT: vpst ; CHECK-NEXT: vcmp.i16 ne, q7, zr
; CHECK-NEXT: vldrbt.u8 q4, [r1], #16 ; CHECK-NEXT: vpsel q4, q3, q2
; CHECK-NEXT: vmov.u8 r4, q4[0] ; CHECK-NEXT: vmov.u16 r4, q4[0]
; CHECK-NEXT: vmov.16 q5[0], r4
; CHECK-NEXT: vmov.u8 r4, q4[1]
; CHECK-NEXT: vmov.16 q5[1], r4
; CHECK-NEXT: vmov.u8 r4, q4[2]
; CHECK-NEXT: vmov.16 q5[2], r4
; CHECK-NEXT: vmov.u8 r4, q4[3]
; CHECK-NEXT: vmov.16 q5[3], r4
; CHECK-NEXT: vmov.u8 r4, q4[4]
; CHECK-NEXT: vmov.16 q5[4], r4
; CHECK-NEXT: vmov.u8 r4, q4[5]
; CHECK-NEXT: vmov.16 q5[5], r4
; CHECK-NEXT: vmov.u8 r4, q4[6]
; CHECK-NEXT: vmov.16 q5[6], r4
; CHECK-NEXT: vmov.u8 r4, q4[7]
; CHECK-NEXT: vmov.16 q5[7], r4
; CHECK-NEXT: vmullb.s8 q5, q5, q7
; CHECK-NEXT: vqshrnb.s16 q5, q5, #7
; CHECK-NEXT: vmovlb.s8 q5, q5
; CHECK-NEXT: vmov.u16 r4, q5[0]
; CHECK-NEXT: vmov.8 q7[0], r4 ; CHECK-NEXT: vmov.8 q7[0], r4
; CHECK-NEXT: vmov.u16 r4, q5[1] ; CHECK-NEXT: vmov.u16 r4, q4[1]
; CHECK-NEXT: vmov.8 q7[1], r4 ; CHECK-NEXT: vmov.8 q7[1], r4
; CHECK-NEXT: vmov.u16 r4, q5[2] ; CHECK-NEXT: vmov.u16 r4, q4[2]
; CHECK-NEXT: vmov.8 q7[2], r4 ; CHECK-NEXT: vmov.8 q7[2], r4
; CHECK-NEXT: vmov.u16 r4, q5[3] ; CHECK-NEXT: vmov.u16 r4, q4[3]
; CHECK-NEXT: vmov.8 q7[3], r4 ; CHECK-NEXT: vmov.8 q7[3], r4
; CHECK-NEXT: vmov.u16 r4, q5[4] ; CHECK-NEXT: vmov.u16 r4, q4[4]
; CHECK-NEXT: vmov.8 q7[4], r4 ; CHECK-NEXT: vmov.8 q7[4], r4
; CHECK-NEXT: vmov.u16 r4, q5[5] ; CHECK-NEXT: vmov.u16 r4, q4[5]
; CHECK-NEXT: vmov.8 q7[5], r4 ; CHECK-NEXT: vmov.8 q7[5], r4
; CHECK-NEXT: vmov.u16 r4, q5[6] ; CHECK-NEXT: vmov.u16 r4, q4[6]
; CHECK-NEXT: vmov.8 q7[6], r4 ; CHECK-NEXT: vmov.8 q7[6], r4
; CHECK-NEXT: vmov.u16 r4, q5[7] ; CHECK-NEXT: vmov.u16 r4, q4[7]
; CHECK-NEXT: vldrw.u32 q4, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.8 q7[7], r4 ; CHECK-NEXT: vmov.8 q7[7], r4
; CHECK-NEXT: vmov.u8 r4, q0[8] ; CHECK-NEXT: vorr q4, q0, q4
; CHECK-NEXT: vmov.16 q5[0], r4 ; CHECK-NEXT: vorr q0, q0, q6
; CHECK-NEXT: vmov.u8 r4, q0[9] ; CHECK-NEXT: vcmp.u32 cs, q1, q4
; CHECK-NEXT: vmov.16 q5[1], r4 ; CHECK-NEXT: vpsel q5, q3, q2
; CHECK-NEXT: vmov.u8 r4, q0[10] ; CHECK-NEXT: vcmp.u32 cs, q1, q0
; CHECK-NEXT: vmov.16 q5[2], r4 ; CHECK-NEXT: vmov r4, s20
; CHECK-NEXT: vmov.u8 r4, q0[11] ; CHECK-NEXT: vpsel q0, q3, q2
; CHECK-NEXT: vmov.16 q5[3], r4 ; CHECK-NEXT: vmov.16 q4[0], r4
; CHECK-NEXT: vmov.u8 r4, q0[12] ; CHECK-NEXT: vmov r4, s21
; CHECK-NEXT: vmov.16 q5[4], r4 ; CHECK-NEXT: vmov.16 q4[1], r4
; CHECK-NEXT: vmov.u8 r4, q0[13] ; CHECK-NEXT: vmov r4, s22
; CHECK-NEXT: vmov.16 q5[5], r4 ; CHECK-NEXT: vmov.16 q4[2], r4
; CHECK-NEXT: vmov.u8 r4, q0[14] ; CHECK-NEXT: vmov r4, s23
; CHECK-NEXT: vmov.16 q5[6], r4 ; CHECK-NEXT: vmov.16 q4[3], r4
; CHECK-NEXT: vmov.u8 r4, q0[15] ; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: vmov.16 q5[7], r4 ; CHECK-NEXT: vmov.16 q4[4], r4
; CHECK-NEXT: vmov.u8 r4, q4[8] ; CHECK-NEXT: vmov r4, s1
; CHECK-NEXT: vmov.16 q0[0], r4 ; CHECK-NEXT: vmov.16 q4[5], r4
; CHECK-NEXT: vmov.u8 r4, q4[9] ; CHECK-NEXT: vmov r4, s2
; CHECK-NEXT: vmov.16 q0[1], r4 ; CHECK-NEXT: vmov.16 q4[6], r4
; CHECK-NEXT: vmov.u8 r4, q4[10] ; CHECK-NEXT: vmov r4, s3
; CHECK-NEXT: vmov.16 q0[2], r4 ; CHECK-NEXT: vmov.16 q4[7], r4
; CHECK-NEXT: vmov.u8 r4, q4[11] ; CHECK-NEXT: vcmp.i16 ne, q4, zr
; CHECK-NEXT: vmov.16 q0[3], r4 ; CHECK-NEXT: vpsel q0, q3, q2
; CHECK-NEXT: vmov.u8 r4, q4[12]
; CHECK-NEXT: vmov.16 q0[4], r4
; CHECK-NEXT: vmov.u8 r4, q4[13]
; CHECK-NEXT: vmov.16 q0[5], r4
; CHECK-NEXT: vmov.u8 r4, q4[14]
; CHECK-NEXT: vmov.16 q0[6], r4
; CHECK-NEXT: vmov.u8 r4, q4[15]
; CHECK-NEXT: vmov.16 q0[7], r4
; CHECK-NEXT: vmullb.s8 q0, q0, q5
; CHECK-NEXT: vqshrnb.s16 q0, q0, #7
; CHECK-NEXT: vmovlb.s8 q0, q0
; CHECK-NEXT: vmov.u16 r4, q0[0] ; CHECK-NEXT: vmov.u16 r4, q0[0]
; CHECK-NEXT: vmov.8 q7[8], r4 ; CHECK-NEXT: vmov.8 q7[8], r4
; CHECK-NEXT: vmov.u16 r4, q0[1] ; CHECK-NEXT: vmov.u16 r4, q0[1]
; CHECK-NEXT: vmov.8 q7[9], r4 ; CHECK-NEXT: vmov.8 q7[9], r4
; CHECK-NEXT: vmov.u16 r4, q0[2] ; CHECK-NEXT: vmov.u16 r4, q0[2]
; CHECK-NEXT: vmov.8 q7[10], r4 ; CHECK-NEXT: vmov.8 q7[10], r4
; CHECK-NEXT: vmov.u16 r4, q0[3] ; CHECK-NEXT: vmov.u16 r4, q0[3]
; CHECK-NEXT: vmov.8 q7[11], r4 ; CHECK-NEXT: vmov.8 q7[11], r4
; CHECK-NEXT: vmov.u16 r4, q0[4] ; CHECK-NEXT: vmov.u16 r4, q0[4]
; CHECK-NEXT: vmov.8 q7[12], r4 ; CHECK-NEXT: vmov.8 q7[12], r4
; CHECK-NEXT: vmov.u16 r4, q0[5] ; CHECK-NEXT: vmov.u16 r4, q0[5]
; CHECK-NEXT: vmov.8 q7[13], r4 ; CHECK-NEXT: vmov.8 q7[13], r4
; CHECK-NEXT: vmov.u16 r4, q0[6] ; CHECK-NEXT: vmov.u16 r4, q0[6]
; CHECK-NEXT: vmov.8 q7[14], r4 ; CHECK-NEXT: vmov.8 q7[14], r4
; CHECK-NEXT: vmov.u16 r4, q0[7] ; CHECK-NEXT: vmov.u16 r4, q0[7]
; CHECK-NEXT: vmov.8 q7[15], r4 ; CHECK-NEXT: vmov.8 q7[15], r4
; CHECK-NEXT: vptt.i8 ne, q7, zr
; CHECK-NEXT: vldrbt.u8 q0, [r0], #16
; CHECK-NEXT: vldrbt.u8 q4, [r1], #16
; CHECK-NEXT: vmullt.s8 q5, q4, q0
; CHECK-NEXT: vmullb.s8 q0, q4, q0
; CHECK-NEXT: vqshrnb.s16 q0, q0, #7
; CHECK-NEXT: vqshrnt.s16 q0, q5, #7
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vstrbt.8 q7, [r2], #16 ; CHECK-NEXT: vstrbt.8 q0, [r2], #16
; CHECK-NEXT: le lr, .LBB18_2 ; CHECK-NEXT: le lr, .LBB18_2
; CHECK-NEXT: .LBB18_3: @ %for.cond.cleanup ; CHECK-NEXT: .LBB18_3: @ %for.cond.cleanup
; CHECK-NEXT: add sp, #56 ; CHECK-NEXT: add sp, #56
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: pop {r4, pc} ; CHECK-NEXT: pop {r4, pc}
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: @ %bb.4: ; CHECK-NEXT: @ %bb.4:
; CHECK-NEXT: .LCPI18_0: ; CHECK-NEXT: .LCPI18_0:
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; CHECK-NEXT: movs r4, #1 ; CHECK-NEXT: movs r4, #1
; CHECK-NEXT: sub.w r6, r5, #16 ; CHECK-NEXT: sub.w r6, r5, #16
; CHECK-NEXT: add.w r12, r0, r5 ; CHECK-NEXT: add.w r12, r0, r5
; CHECK-NEXT: add.w lr, r4, r6, lsr #4 ; CHECK-NEXT: add.w lr, r4, r6, lsr #4
; CHECK-NEXT: adds r4, r2, r5 ; CHECK-NEXT: adds r4, r2, r5
; CHECK-NEXT: adds r6, r1, r5 ; CHECK-NEXT: adds r6, r1, r5
; CHECK-NEXT: .LBB21_4: @ %vector.body ; CHECK-NEXT: .LBB21_4: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrb.u16 q0, [r0, #8] ; CHECK-NEXT: vldrb.u8 q0, [r0], #16
; CHECK-NEXT: vldrb.u16 q1, [r1, #8] ; CHECK-NEXT: vldrb.u8 q1, [r1], #16
; CHECK-NEXT: vmul.i16 q0, q1, q0 ; CHECK-NEXT: vmullt.u8 q2, q1, q0
; CHECK-NEXT: vldrb.u16 q1, [r1], #16 ; CHECK-NEXT: vmullb.u8 q0, q1, q0
; CHECK-NEXT: vqshrnb.u16 q0, q0, #7 ; CHECK-NEXT: vqshrnb.u16 q2, q2, #7
; CHECK-NEXT: vmovlb.u8 q0, q0
; CHECK-NEXT: vstrb.16 q0, [r2, #8]
; CHECK-NEXT: vldrb.u16 q0, [r0], #16
; CHECK-NEXT: vmul.i16 q0, q1, q0
; CHECK-NEXT: vqshrnb.u16 q0, q0, #7 ; CHECK-NEXT: vqshrnb.u16 q0, q0, #7
; CHECK-NEXT: vmovlb.u8 q2, q2
; CHECK-NEXT: vmovlb.u8 q0, q0 ; CHECK-NEXT: vmovlb.u8 q0, q0
; CHECK-NEXT: vstrb.16 q0, [r2], #16 ; CHECK-NEXT: vmovnt.i16 q0, q2
; CHECK-NEXT: vstrb.8 q0, [r2], #16
; CHECK-NEXT: le lr, .LBB21_4 ; CHECK-NEXT: le lr, .LBB21_4
; CHECK-NEXT: @ %bb.5: @ %middle.block ; CHECK-NEXT: @ %bb.5: @ %middle.block
; CHECK-NEXT: cmp r5, r3 ; CHECK-NEXT: cmp r5, r3
; CHECK-NEXT: it eq ; CHECK-NEXT: it eq
; CHECK-NEXT: popeq {r4, r5, r6, pc} ; CHECK-NEXT: popeq {r4, r5, r6, pc}
; CHECK-NEXT: .LBB21_6: @ %for.body.preheader23 ; CHECK-NEXT: .LBB21_6: @ %for.body.preheader23
; CHECK-NEXT: sub.w lr, r3, r5 ; CHECK-NEXT: sub.w lr, r3, r5
; CHECK-NEXT: .LBB21_7: @ %for.body ; CHECK-NEXT: .LBB21_7: @ %for.body
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llvm/test/CodeGen/Thumb2/mve-vabdus.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve %s -o - | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve %s -o - | FileCheck %s
define arm_aapcs_vfpcc <16 x i8> @vabd_s8(<16 x i8> %src1, <16 x i8> %src2) { define arm_aapcs_vfpcc <16 x i8> @vabd_s8(<16 x i8> %src1, <16 x i8> %src2) {
; CHECK-LABEL: vabd_s8: ; CHECK-LABEL: vabd_s8:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.u8 r0, q1[0] ; CHECK-NEXT: vmovlt.s8 q2, q1
; CHECK-NEXT: vmov.16 q2[0], r0 ; CHECK-NEXT: vmovlt.s8 q3, q0
; CHECK-NEXT: vmov.u8 r0, q1[1] ; CHECK-NEXT: vmovlb.s8 q1, q1
; CHECK-NEXT: vmov.16 q2[1], r0 ; CHECK-NEXT: vmovlb.s8 q0, q0
; CHECK-NEXT: vmov.u8 r0, q1[2]
; CHECK-NEXT: vmov.16 q2[2], r0
; CHECK-NEXT: vmov.u8 r0, q1[3]
; CHECK-NEXT: vmov.16 q2[3], r0
; CHECK-NEXT: vmov.u8 r0, q1[4]
; CHECK-NEXT: vmov.16 q2[4], r0
; CHECK-NEXT: vmov.u8 r0, q1[5]
; CHECK-NEXT: vmov.16 q2[5], r0
; CHECK-NEXT: vmov.u8 r0, q1[6]
; CHECK-NEXT: vmov.16 q2[6], r0
; CHECK-NEXT: vmov.u8 r0, q1[7]
; CHECK-NEXT: vmov.16 q2[7], r0
; CHECK-NEXT: vmov.u8 r0, q0[0]
; CHECK-NEXT: vmov.16 q3[0], r0
; CHECK-NEXT: vmov.u8 r0, q0[1]
; CHECK-NEXT: vmov.16 q3[1], r0
; CHECK-NEXT: vmov.u8 r0, q0[2]
; CHECK-NEXT: vmov.16 q3[2], r0
; CHECK-NEXT: vmov.u8 r0, q0[3]
; CHECK-NEXT: vmov.16 q3[3], r0
; CHECK-NEXT: vmov.u8 r0, q0[4]
; CHECK-NEXT: vmov.16 q3[4], r0
; CHECK-NEXT: vmov.u8 r0, q0[5]
; CHECK-NEXT: vmov.16 q3[5], r0
; CHECK-NEXT: vmov.u8 r0, q0[6]
; CHECK-NEXT: vmov.16 q3[6], r0
; CHECK-NEXT: vmov.u8 r0, q0[7]
; CHECK-NEXT: vmov.16 q3[7], r0
; CHECK-NEXT: vmovlb.s8 q2, q2
; CHECK-NEXT: vmovlb.s8 q3, q3
; CHECK-NEXT: vsub.i16 q2, q3, q2 ; CHECK-NEXT: vsub.i16 q2, q3, q2
; CHECK-NEXT: vabs.s16 q3, q2
; CHECK-NEXT: vmov.u16 r0, q3[0]
; CHECK-NEXT: vmov.8 q2[0], r0
; CHECK-NEXT: vmov.u16 r0, q3[1]
; CHECK-NEXT: vmov.8 q2[1], r0
; CHECK-NEXT: vmov.u16 r0, q3[2]
; CHECK-NEXT: vmov.8 q2[2], r0
; CHECK-NEXT: vmov.u16 r0, q3[3]
; CHECK-NEXT: vmov.8 q2[3], r0
; CHECK-NEXT: vmov.u16 r0, q3[4]
; CHECK-NEXT: vmov.8 q2[4], r0
; CHECK-NEXT: vmov.u16 r0, q3[5]
; CHECK-NEXT: vmov.8 q2[5], r0
; CHECK-NEXT: vmov.u16 r0, q3[6]
; CHECK-NEXT: vmov.8 q2[6], r0
; CHECK-NEXT: vmov.u16 r0, q3[7]
; CHECK-NEXT: vmov.8 q2[7], r0
; CHECK-NEXT: vmov.u8 r0, q1[8]
; CHECK-NEXT: vmov.16 q3[0], r0
; CHECK-NEXT: vmov.u8 r0, q1[9]
; CHECK-NEXT: vmov.16 q3[1], r0
; CHECK-NEXT: vmov.u8 r0, q1[10]
; CHECK-NEXT: vmov.16 q3[2], r0
; CHECK-NEXT: vmov.u8 r0, q1[11]
; CHECK-NEXT: vmov.16 q3[3], r0
; CHECK-NEXT: vmov.u8 r0, q1[12]
; CHECK-NEXT: vmov.16 q3[4], r0
; CHECK-NEXT: vmov.u8 r0, q1[13]
; CHECK-NEXT: vmov.16 q3[5], r0
; CHECK-NEXT: vmov.u8 r0, q1[14]
; CHECK-NEXT: vmov.16 q3[6], r0
; CHECK-NEXT: vmov.u8 r0, q1[15]
; CHECK-NEXT: vmov.16 q3[7], r0
; CHECK-NEXT: vmov.u8 r0, q0[8]
; CHECK-NEXT: vmovlb.s8 q1, q3
; CHECK-NEXT: vmov.16 q3[0], r0
; CHECK-NEXT: vmov.u8 r0, q0[9]
; CHECK-NEXT: vmov.16 q3[1], r0
; CHECK-NEXT: vmov.u8 r0, q0[10]
; CHECK-NEXT: vmov.16 q3[2], r0
; CHECK-NEXT: vmov.u8 r0, q0[11]
; CHECK-NEXT: vmov.16 q3[3], r0
; CHECK-NEXT: vmov.u8 r0, q0[12]
; CHECK-NEXT: vmov.16 q3[4], r0
; CHECK-NEXT: vmov.u8 r0, q0[13]
; CHECK-NEXT: vmov.16 q3[5], r0
; CHECK-NEXT: vmov.u8 r0, q0[14]
; CHECK-NEXT: vmov.16 q3[6], r0
; CHECK-NEXT: vmov.u8 r0, q0[15]
; CHECK-NEXT: vmov.16 q3[7], r0
; CHECK-NEXT: vmovlb.s8 q0, q3
; CHECK-NEXT: vsub.i16 q0, q0, q1 ; CHECK-NEXT: vsub.i16 q0, q0, q1
; CHECK-NEXT: vabs.s16 q2, q2
; CHECK-NEXT: vabs.s16 q0, q0 ; CHECK-NEXT: vabs.s16 q0, q0
; CHECK-NEXT: vmov.u16 r0, q0[0] ; CHECK-NEXT: vmovnt.i16 q0, q2
; CHECK-NEXT: vmov.8 q2[8], r0
; CHECK-NEXT: vmov.u16 r0, q0[1]
; CHECK-NEXT: vmov.8 q2[9], r0
; CHECK-NEXT: vmov.u16 r0, q0[2]
; CHECK-NEXT: vmov.8 q2[10], r0
; CHECK-NEXT: vmov.u16 r0, q0[3]
; CHECK-NEXT: vmov.8 q2[11], r0
; CHECK-NEXT: vmov.u16 r0, q0[4]
; CHECK-NEXT: vmov.8 q2[12], r0
; CHECK-NEXT: vmov.u16 r0, q0[5]
; CHECK-NEXT: vmov.8 q2[13], r0
; CHECK-NEXT: vmov.u16 r0, q0[6]
; CHECK-NEXT: vmov.8 q2[14], r0
; CHECK-NEXT: vmov.u16 r0, q0[7]
; CHECK-NEXT: vmov.8 q2[15], r0
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
%sextsrc1 = sext <16 x i8> %src1 to <16 x i16> %sextsrc1 = sext <16 x i8> %src1 to <16 x i16>
%sextsrc2 = sext <16 x i8> %src2 to <16 x i16> %sextsrc2 = sext <16 x i8> %src2 to <16 x i16>
%add1 = sub <16 x i16> %sextsrc1, %sextsrc2 %add1 = sub <16 x i16> %sextsrc1, %sextsrc2
%add2 = sub <16 x i16> zeroinitializer, %add1 %add2 = sub <16 x i16> zeroinitializer, %add1
%c = icmp sge <16 x i16> %add1, zeroinitializer %c = icmp sge <16 x i16> %add1, zeroinitializer
%s = select <16 x i1> %c, <16 x i16> %add1, <16 x i16> %add2 %s = select <16 x i1> %c, <16 x i16> %add1, <16 x i16> %add2
%result = trunc <16 x i16> %s to <16 x i8> %result = trunc <16 x i16> %s to <16 x i8>
ret <16 x i8> %result ret <16 x i8> %result
} }
define arm_aapcs_vfpcc <8 x i16> @vabd_s16(<8 x i16> %src1, <8 x i16> %src2) { define arm_aapcs_vfpcc <8 x i16> @vabd_s16(<8 x i16> %src1, <8 x i16> %src2) {
; CHECK-LABEL: vabd_s16: ; CHECK-LABEL: vabd_s16:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.u16 r0, q1[2] ; CHECK-NEXT: vmovlt.s16 q2, q1
; CHECK-NEXT: vmov.u16 r1, q1[0] ; CHECK-NEXT: vmovlt.s16 q3, q0
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0 ; CHECK-NEXT: vmovlb.s16 q1, q1
; CHECK-NEXT: vmov.u16 r0, q1[3] ; CHECK-NEXT: vmovlb.s16 q0, q0
; CHECK-NEXT: vmov.u16 r1, q1[1]
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
; CHECK-NEXT: vmov.u16 r0, q0[2]
; CHECK-NEXT: vmov.u16 r1, q0[0]
; CHECK-NEXT: vmovlb.s16 q2, q2
; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
; CHECK-NEXT: vmov.u16 r0, q0[3]
; CHECK-NEXT: vmov.u16 r1, q0[1]
; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
; CHECK-NEXT: vmov.u16 r1, q1[4]
; CHECK-NEXT: vmovlb.s16 q3, q3
; CHECK-NEXT: vsub.i32 q2, q3, q2 ; CHECK-NEXT: vsub.i32 q2, q3, q2
; CHECK-NEXT: vabs.s32 q3, q2
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmov.16 q2[0], r0
; CHECK-NEXT: vmov r0, s13
; CHECK-NEXT: vmov.16 q2[1], r0
; CHECK-NEXT: vmov r0, s14
; CHECK-NEXT: vmov.16 q2[2], r0
; CHECK-NEXT: vmov r0, s15
; CHECK-NEXT: vmov.16 q2[3], r0
; CHECK-NEXT: vmov.u16 r0, q1[6]
; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
; CHECK-NEXT: vmov.u16 r0, q1[7]
; CHECK-NEXT: vmov.u16 r1, q1[5]
; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
; CHECK-NEXT: vmov.u16 r0, q0[6]
; CHECK-NEXT: vmov.u16 r1, q0[4]
; CHECK-NEXT: vmovlb.s16 q1, q3
; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
; CHECK-NEXT: vmov.u16 r0, q0[7]
; CHECK-NEXT: vmov.u16 r1, q0[5]
; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
; CHECK-NEXT: vmovlb.s16 q0, q3
; CHECK-NEXT: vsub.i32 q0, q0, q1 ; CHECK-NEXT: vsub.i32 q0, q0, q1
; CHECK-NEXT: vabs.s32 q2, q2
; CHECK-NEXT: vabs.s32 q0, q0 ; CHECK-NEXT: vabs.s32 q0, q0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmovnt.i32 q0, q2
; CHECK-NEXT: vmov.16 q2[4], r0
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: vmov.16 q2[5], r0
; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: vmov.16 q2[6], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: vmov.16 q2[7], r0
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
%sextsrc1 = sext <8 x i16> %src1 to <8 x i32> %sextsrc1 = sext <8 x i16> %src1 to <8 x i32>
%sextsrc2 = sext <8 x i16> %src2 to <8 x i32> %sextsrc2 = sext <8 x i16> %src2 to <8 x i32>
%add1 = sub <8 x i32> %sextsrc1, %sextsrc2 %add1 = sub <8 x i32> %sextsrc1, %sextsrc2
%add2 = sub <8 x i32> zeroinitializer, %add1 %add2 = sub <8 x i32> zeroinitializer, %add1
%c = icmp sge <8 x i32> %add1, zeroinitializer %c = icmp sge <8 x i32> %add1, zeroinitializer
%s = select <8 x i1> %c, <8 x i32> %add1, <8 x i32> %add2 %s = select <8 x i1> %c, <8 x i32> %add1, <8 x i32> %add2
%result = trunc <8 x i32> %s to <8 x i16> %result = trunc <8 x i32> %s to <8 x i16>
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines; CHECK-NEXT: bx lr
%s = select <4 x i1> %c, <4 x i64> %add1, <4 x i64> %add2 %s = select <4 x i1> %c, <4 x i64> %add1, <4 x i64> %add2
%result = trunc <4 x i64> %s to <4 x i32> %result = trunc <4 x i64> %s to <4 x i32>
ret <4 x i32> %result ret <4 x i32> %result
} }
define arm_aapcs_vfpcc <16 x i8> @vabd_u8(<16 x i8> %src1, <16 x i8> %src2) { define arm_aapcs_vfpcc <16 x i8> @vabd_u8(<16 x i8> %src1, <16 x i8> %src2) {
; CHECK-LABEL: vabd_u8: ; CHECK-LABEL: vabd_u8:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.u8 r0, q1[0] ; CHECK-NEXT: vmovlt.u8 q2, q1
; CHECK-NEXT: vmov.16 q2[0], r0 ; CHECK-NEXT: vmovlt.u8 q3, q0
; CHECK-NEXT: vmov.u8 r0, q1[1] ; CHECK-NEXT: vmovlb.u8 q1, q1
; CHECK-NEXT: vmov.16 q2[1], r0 ; CHECK-NEXT: vmovlb.u8 q0, q0
; CHECK-NEXT: vmov.u8 r0, q1[2]
; CHECK-NEXT: vmov.16 q2[2], r0
; CHECK-NEXT: vmov.u8 r0, q1[3]
; CHECK-NEXT: vmov.16 q2[3], r0
; CHECK-NEXT: vmov.u8 r0, q1[4]
; CHECK-NEXT: vmov.16 q2[4], r0
; CHECK-NEXT: vmov.u8 r0, q1[5]
; CHECK-NEXT: vmov.16 q2[5], r0
; CHECK-NEXT: vmov.u8 r0, q1[6]
; CHECK-NEXT: vmov.16 q2[6], r0
; CHECK-NEXT: vmov.u8 r0, q1[7]
; CHECK-NEXT: vmov.16 q2[7], r0
; CHECK-NEXT: vmov.u8 r0, q0[0]
; CHECK-NEXT: vmov.16 q3[0], r0
; CHECK-NEXT: vmov.u8 r0, q0[1]
; CHECK-NEXT: vmov.16 q3[1], r0
; CHECK-NEXT: vmov.u8 r0, q0[2]
; CHECK-NEXT: vmov.16 q3[2], r0
; CHECK-NEXT: vmov.u8 r0, q0[3]
; CHECK-NEXT: vmov.16 q3[3], r0
; CHECK-NEXT: vmov.u8 r0, q0[4]
; CHECK-NEXT: vmov.16 q3[4], r0
; CHECK-NEXT: vmov.u8 r0, q0[5]
; CHECK-NEXT: vmov.16 q3[5], r0
; CHECK-NEXT: vmov.u8 r0, q0[6]
; CHECK-NEXT: vmov.16 q3[6], r0
; CHECK-NEXT: vmov.u8 r0, q0[7]
; CHECK-NEXT: vmov.16 q3[7], r0
; CHECK-NEXT: vmovlb.u8 q2, q2
; CHECK-NEXT: vmovlb.u8 q3, q3
; CHECK-NEXT: vsub.i16 q2, q3, q2 ; CHECK-NEXT: vsub.i16 q2, q3, q2
; CHECK-NEXT: vabs.s16 q3, q2
; CHECK-NEXT: vmov.u16 r0, q3[0]
; CHECK-NEXT: vmov.8 q2[0], r0
; CHECK-NEXT: vmov.u16 r0, q3[1]
; CHECK-NEXT: vmov.8 q2[1], r0
; CHECK-NEXT: vmov.u16 r0, q3[2]
; CHECK-NEXT: vmov.8 q2[2], r0
; CHECK-NEXT: vmov.u16 r0, q3[3]
; CHECK-NEXT: vmov.8 q2[3], r0
; CHECK-NEXT: vmov.u16 r0, q3[4]
; CHECK-NEXT: vmov.8 q2[4], r0
; CHECK-NEXT: vmov.u16 r0, q3[5]
; CHECK-NEXT: vmov.8 q2[5], r0
; CHECK-NEXT: vmov.u16 r0, q3[6]
; CHECK-NEXT: vmov.8 q2[6], r0
; CHECK-NEXT: vmov.u16 r0, q3[7]
; CHECK-NEXT: vmov.8 q2[7], r0
; CHECK-NEXT: vmov.u8 r0, q1[8]
; CHECK-NEXT: vmov.16 q3[0], r0
; CHECK-NEXT: vmov.u8 r0, q1[9]
; CHECK-NEXT: vmov.16 q3[1], r0
; CHECK-NEXT: vmov.u8 r0, q1[10]
; CHECK-NEXT: vmov.16 q3[2], r0
; CHECK-NEXT: vmov.u8 r0, q1[11]
; CHECK-NEXT: vmov.16 q3[3], r0
; CHECK-NEXT: vmov.u8 r0, q1[12]
; CHECK-NEXT: vmov.16 q3[4], r0
; CHECK-NEXT: vmov.u8 r0, q1[13]
; CHECK-NEXT: vmov.16 q3[5], r0
; CHECK-NEXT: vmov.u8 r0, q1[14]
; CHECK-NEXT: vmov.16 q3[6], r0
; CHECK-NEXT: vmov.u8 r0, q1[15]
; CHECK-NEXT: vmov.16 q3[7], r0
; CHECK-NEXT: vmov.u8 r0, q0[8]
; CHECK-NEXT: vmovlb.u8 q1, q3
; CHECK-NEXT: vmov.16 q3[0], r0
; CHECK-NEXT: vmov.u8 r0, q0[9]
; CHECK-NEXT: vmov.16 q3[1], r0
; CHECK-NEXT: vmov.u8 r0, q0[10]
; CHECK-NEXT: vmov.16 q3[2], r0
; CHECK-NEXT: vmov.u8 r0, q0[11]
; CHECK-NEXT: vmov.16 q3[3], r0
; CHECK-NEXT: vmov.u8 r0, q0[12]
; CHECK-NEXT: vmov.16 q3[4], r0
; CHECK-NEXT: vmov.u8 r0, q0[13]
; CHECK-NEXT: vmov.16 q3[5], r0
; CHECK-NEXT: vmov.u8 r0, q0[14]
; CHECK-NEXT: vmov.16 q3[6], r0
; CHECK-NEXT: vmov.u8 r0, q0[15]
; CHECK-NEXT: vmov.16 q3[7], r0
; CHECK-NEXT: vmovlb.u8 q0, q3
; CHECK-NEXT: vsub.i16 q0, q0, q1 ; CHECK-NEXT: vsub.i16 q0, q0, q1
; CHECK-NEXT: vabs.s16 q2, q2
; CHECK-NEXT: vabs.s16 q0, q0 ; CHECK-NEXT: vabs.s16 q0, q0
; CHECK-NEXT: vmov.u16 r0, q0[0] ; CHECK-NEXT: vmovnt.i16 q0, q2
; CHECK-NEXT: vmov.8 q2[8], r0
; CHECK-NEXT: vmov.u16 r0, q0[1]
; CHECK-NEXT: vmov.8 q2[9], r0
; CHECK-NEXT: vmov.u16 r0, q0[2]
; CHECK-NEXT: vmov.8 q2[10], r0
; CHECK-NEXT: vmov.u16 r0, q0[3]
; CHECK-NEXT: vmov.8 q2[11], r0
; CHECK-NEXT: vmov.u16 r0, q0[4]
; CHECK-NEXT: vmov.8 q2[12], r0
; CHECK-NEXT: vmov.u16 r0, q0[5]
; CHECK-NEXT: vmov.8 q2[13], r0
; CHECK-NEXT: vmov.u16 r0, q0[6]
; CHECK-NEXT: vmov.8 q2[14], r0
; CHECK-NEXT: vmov.u16 r0, q0[7]
; CHECK-NEXT: vmov.8 q2[15], r0
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
%zextsrc1 = zext <16 x i8> %src1 to <16 x i16> %zextsrc1 = zext <16 x i8> %src1 to <16 x i16>
%zextsrc2 = zext <16 x i8> %src2 to <16 x i16> %zextsrc2 = zext <16 x i8> %src2 to <16 x i16>
%add1 = sub <16 x i16> %zextsrc1, %zextsrc2 %add1 = sub <16 x i16> %zextsrc1, %zextsrc2
%add2 = sub <16 x i16> zeroinitializer, %add1 %add2 = sub <16 x i16> zeroinitializer, %add1
%c = icmp sge <16 x i16> %add1, zeroinitializer %c = icmp sge <16 x i16> %add1, zeroinitializer
%s = select <16 x i1> %c, <16 x i16> %add1, <16 x i16> %add2 %s = select <16 x i1> %c, <16 x i16> %add1, <16 x i16> %add2
%result = trunc <16 x i16> %s to <16 x i8> %result = trunc <16 x i16> %s to <16 x i8>
ret <16 x i8> %result ret <16 x i8> %result
} }
define arm_aapcs_vfpcc <8 x i16> @vabd_u16(<8 x i16> %src1, <8 x i16> %src2) { define arm_aapcs_vfpcc <8 x i16> @vabd_u16(<8 x i16> %src1, <8 x i16> %src2) {
; CHECK-LABEL: vabd_u16: ; CHECK-LABEL: vabd_u16:
; CHECK: @ %bb.0: ; CHECK: @ %bb.0:
; CHECK-NEXT: vmov.u16 r0, q1[2] ; CHECK-NEXT: vmovlt.u16 q2, q1
; CHECK-NEXT: vmov.u16 r1, q1[0] ; CHECK-NEXT: vmovlt.u16 q3, q0
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0 ; CHECK-NEXT: vmovlb.u16 q1, q1
; CHECK-NEXT: vmov.u16 r0, q1[3] ; CHECK-NEXT: vmovlb.u16 q0, q0
; CHECK-NEXT: vmov.u16 r1, q1[1]
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
; CHECK-NEXT: vmov.u16 r0, q0[2]
; CHECK-NEXT: vmov.u16 r1, q0[0]
; CHECK-NEXT: vmovlb.u16 q2, q2
; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
; CHECK-NEXT: vmov.u16 r0, q0[3]
; CHECK-NEXT: vmov.u16 r1, q0[1]
; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
; CHECK-NEXT: vmov.u16 r1, q1[4]
; CHECK-NEXT: vmovlb.u16 q3, q3
; CHECK-NEXT: vsub.i32 q2, q3, q2 ; CHECK-NEXT: vsub.i32 q2, q3, q2
; CHECK-NEXT: vabs.s32 q3, q2
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmov.16 q2[0], r0
; CHECK-NEXT: vmov r0, s13
; CHECK-NEXT: vmov.16 q2[1], r0
; CHECK-NEXT: vmov r0, s14
; CHECK-NEXT: vmov.16 q2[2], r0
; CHECK-NEXT: vmov r0, s15
; CHECK-NEXT: vmov.16 q2[3], r0
; CHECK-NEXT: vmov.u16 r0, q1[6]
; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
; CHECK-NEXT: vmov.u16 r0, q1[7]
; CHECK-NEXT: vmov.u16 r1, q1[5]
; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
; CHECK-NEXT: vmov.u16 r0, q0[6]
; CHECK-NEXT: vmov.u16 r1, q0[4]
; CHECK-NEXT: vmovlb.u16 q1, q3
; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
; CHECK-NEXT: vmov.u16 r0, q0[7]
; CHECK-NEXT: vmov.u16 r1, q0[5]
; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
; CHECK-NEXT: vmovlb.u16 q0, q3
; CHECK-NEXT: vsub.i32 q0, q0, q1 ; CHECK-NEXT: vsub.i32 q0, q0, q1
; CHECK-NEXT: vabs.s32 q2, q2
; CHECK-NEXT: vabs.s32 q0, q0 ; CHECK-NEXT: vabs.s32 q0, q0
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmovnt.i32 q0, q2
; CHECK-NEXT: vmov.16 q2[4], r0
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: vmov.16 q2[5], r0
; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: vmov.16 q2[6], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: vmov.16 q2[7], r0
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
%zextsrc1 = zext <8 x i16> %src1 to <8 x i32> %zextsrc1 = zext <8 x i16> %src1 to <8 x i32>
%zextsrc2 = zext <8 x i16> %src2 to <8 x i32> %zextsrc2 = zext <8 x i16> %src2 to <8 x i32>
%add1 = sub <8 x i32> %zextsrc1, %zextsrc2 %add1 = sub <8 x i32> %zextsrc1, %zextsrc2
%add2 = sub <8 x i32> zeroinitializer, %add1 %add2 = sub <8 x i32> zeroinitializer, %add1
%c = icmp sge <8 x i32> %add1, zeroinitializer %c = icmp sge <8 x i32> %add1, zeroinitializer
%s = select <8 x i1> %c, <8 x i32> %add1, <8 x i32> %add2 %s = select <8 x i1> %c, <8 x i32> %add1, <8 x i32> %add2
%result = trunc <8 x i32> %s to <8 x i16> %result = trunc <8 x i32> %s to <8 x i16>
▲ Show 20 Lines • Show All 494 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-vmulh.ll

Show First 20 Lines • Show All 133 Lines • ▼ Show 20 Linesentry:
%s = lshr <4 x i32> %m, <i32 16, i32 16, i32 16, i32 16> %s = lshr <4 x i32> %m, <i32 16, i32 16, i32 16, i32 16>
%s2 = trunc <4 x i32> %s to <4 x i16> %s2 = trunc <4 x i32> %s to <4 x i16>
ret <4 x i16> %s2 ret <4 x i16> %s2
} }
define arm_aapcs_vfpcc <8 x i16> @vmulhs_v8i16(<8 x i16> %s0, <8 x i16> %s1) { define arm_aapcs_vfpcc <8 x i16> @vmulhs_v8i16(<8 x i16> %s0, <8 x i16> %s1) {
; CHECK-LABEL: vmulhs_v8i16: ; CHECK-LABEL: vmulhs_v8i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.u16 r0, q1[2] ; CHECK-NEXT: vmullt.s16 q2, q0, q1
; CHECK-NEXT: vmov.u16 r1, q1[0] ; CHECK-NEXT: vmullb.s16 q0, q0, q1
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0 ; CHECK-NEXT: vshr.u32 q2, q2, #16
; CHECK-NEXT: vmov.u16 r0, q1[3]
; CHECK-NEXT: vmov.u16 r1, q1[1]
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
; CHECK-NEXT: vmov.u16 r0, q0[2]
; CHECK-NEXT: vmov.u16 r1, q0[0]
; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
; CHECK-NEXT: vmov.u16 r0, q0[3]
; CHECK-NEXT: vmov.u16 r1, q0[1]
; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
; CHECK-NEXT: vmov.u16 r1, q1[4]
; CHECK-NEXT: vmullb.s16 q2, q3, q2
; CHECK-NEXT: vshr.u32 q3, q2, #16
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmov.16 q2[0], r0
; CHECK-NEXT: vmov r0, s13
; CHECK-NEXT: vmov.16 q2[1], r0
; CHECK-NEXT: vmov r0, s14
; CHECK-NEXT: vmov.16 q2[2], r0
; CHECK-NEXT: vmov r0, s15
; CHECK-NEXT: vmov.16 q2[3], r0
; CHECK-NEXT: vmov.u16 r0, q1[6]
; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
; CHECK-NEXT: vmov.u16 r0, q1[7]
; CHECK-NEXT: vmov.u16 r1, q1[5]
; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
; CHECK-NEXT: vmov.u16 r0, q0[6]
; CHECK-NEXT: vmov.u16 r1, q0[4]
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: vmov.u16 r0, q0[7]
; CHECK-NEXT: vmov.u16 r1, q0[5]
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
; CHECK-NEXT: vmullb.s16 q0, q1, q3
; CHECK-NEXT: vshr.u32 q0, q0, #16 ; CHECK-NEXT: vshr.u32 q0, q0, #16
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmovnt.i32 q0, q2
; CHECK-NEXT: vmov.16 q2[4], r0
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: vmov.16 q2[5], r0
; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: vmov.16 q2[6], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: vmov.16 q2[7], r0
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s0s = sext <8 x i16> %s0 to <8 x i32> %s0s = sext <8 x i16> %s0 to <8 x i32>
%s1s = sext <8 x i16> %s1 to <8 x i32> %s1s = sext <8 x i16> %s1 to <8 x i32>
%m = mul <8 x i32> %s0s, %s1s %m = mul <8 x i32> %s0s, %s1s
%s = ashr <8 x i32> %m, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16> %s = ashr <8 x i32> %m, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
%s2 = trunc <8 x i32> %s to <8 x i16> %s2 = trunc <8 x i32> %s to <8 x i16>
ret <8 x i16> %s2 ret <8 x i16> %s2
} }
define arm_aapcs_vfpcc <8 x i16> @vmulhu_v8i16(<8 x i16> %s0, <8 x i16> %s1) { define arm_aapcs_vfpcc <8 x i16> @vmulhu_v8i16(<8 x i16> %s0, <8 x i16> %s1) {
; CHECK-LABEL: vmulhu_v8i16: ; CHECK-LABEL: vmulhu_v8i16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.u16 r0, q1[2] ; CHECK-NEXT: vmullt.u16 q2, q0, q1
; CHECK-NEXT: vmov.u16 r1, q1[0] ; CHECK-NEXT: vmullb.u16 q0, q0, q1
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0 ; CHECK-NEXT: vshr.u32 q2, q2, #16
; CHECK-NEXT: vmov.u16 r0, q1[3]
; CHECK-NEXT: vmov.u16 r1, q1[1]
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
; CHECK-NEXT: vmov.u16 r0, q0[2]
; CHECK-NEXT: vmov.u16 r1, q0[0]
; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
; CHECK-NEXT: vmov.u16 r0, q0[3]
; CHECK-NEXT: vmov.u16 r1, q0[1]
; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
; CHECK-NEXT: vmov.u16 r1, q1[4]
; CHECK-NEXT: vmullb.u16 q2, q3, q2
; CHECK-NEXT: vshr.u32 q3, q2, #16
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmov.16 q2[0], r0
; CHECK-NEXT: vmov r0, s13
; CHECK-NEXT: vmov.16 q2[1], r0
; CHECK-NEXT: vmov r0, s14
; CHECK-NEXT: vmov.16 q2[2], r0
; CHECK-NEXT: vmov r0, s15
; CHECK-NEXT: vmov.16 q2[3], r0
; CHECK-NEXT: vmov.u16 r0, q1[6]
; CHECK-NEXT: vmov q3[2], q3[0], r1, r0
; CHECK-NEXT: vmov.u16 r0, q1[7]
; CHECK-NEXT: vmov.u16 r1, q1[5]
; CHECK-NEXT: vmov q3[3], q3[1], r1, r0
; CHECK-NEXT: vmov.u16 r0, q0[6]
; CHECK-NEXT: vmov.u16 r1, q0[4]
; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
; CHECK-NEXT: vmov.u16 r0, q0[7]
; CHECK-NEXT: vmov.u16 r1, q0[5]
; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
; CHECK-NEXT: vmullb.u16 q0, q1, q3
; CHECK-NEXT: vshr.u32 q0, q0, #16 ; CHECK-NEXT: vshr.u32 q0, q0, #16
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmovnt.i32 q0, q2
; CHECK-NEXT: vmov.16 q2[4], r0
; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: vmov.16 q2[5], r0
; CHECK-NEXT: vmov r0, s2
; CHECK-NEXT: vmov.16 q2[6], r0
; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: vmov.16 q2[7], r0
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s0s = zext <8 x i16> %s0 to <8 x i32> %s0s = zext <8 x i16> %s0 to <8 x i32>
%s1s = zext <8 x i16> %s1 to <8 x i32> %s1s = zext <8 x i16> %s1 to <8 x i32>
%m = mul <8 x i32> %s0s, %s1s %m = mul <8 x i32> %s0s, %s1s
%s = lshr <8 x i32> %m, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16> %s = lshr <8 x i32> %m, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
%s2 = trunc <8 x i32> %s to <8 x i16> %s2 = trunc <8 x i32> %s to <8 x i16>
ret <8 x i16> %s2 ret <8 x i16> %s2
Show All 27 Linesentry:
%s = lshr <8 x i16> %m, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> %s = lshr <8 x i16> %m, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
%s2 = trunc <8 x i16> %s to <8 x i8> %s2 = trunc <8 x i16> %s to <8 x i8>
ret <8 x i8> %s2 ret <8 x i8> %s2
} }
define arm_aapcs_vfpcc <16 x i8> @vmulhs_v16i8(<16 x i8> %s0, <16 x i8> %s1) { define arm_aapcs_vfpcc <16 x i8> @vmulhs_v16i8(<16 x i8> %s0, <16 x i8> %s1) {
; CHECK-LABEL: vmulhs_v16i8: ; CHECK-LABEL: vmulhs_v16i8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.u8 r0, q1[0] ; CHECK-NEXT: vmullt.s8 q2, q0, q1
; CHECK-NEXT: vmov.16 q2[0], r0 ; CHECK-NEXT: vmullb.s8 q0, q0, q1
; CHECK-NEXT: vmov.u8 r0, q1[1] ; CHECK-NEXT: vshr.u16 q2, q2, #8
; CHECK-NEXT: vmov.16 q2[1], r0
; CHECK-NEXT: vmov.u8 r0, q1[2]
; CHECK-NEXT: vmov.16 q2[2], r0
; CHECK-NEXT: vmov.u8 r0, q1[3]
; CHECK-NEXT: vmov.16 q2[3], r0
; CHECK-NEXT: vmov.u8 r0, q1[4]
; CHECK-NEXT: vmov.16 q2[4], r0
; CHECK-NEXT: vmov.u8 r0, q1[5]
; CHECK-NEXT: vmov.16 q2[5], r0
; CHECK-NEXT: vmov.u8 r0, q1[6]
; CHECK-NEXT: vmov.16 q2[6], r0
; CHECK-NEXT: vmov.u8 r0, q1[7]
; CHECK-NEXT: vmov.16 q2[7], r0
; CHECK-NEXT: vmov.u8 r0, q0[0]
; CHECK-NEXT: vmov.16 q3[0], r0
; CHECK-NEXT: vmov.u8 r0, q0[1]
; CHECK-NEXT: vmov.16 q3[1], r0
; CHECK-NEXT: vmov.u8 r0, q0[2]
; CHECK-NEXT: vmov.16 q3[2], r0
; CHECK-NEXT: vmov.u8 r0, q0[3]
; CHECK-NEXT: vmov.16 q3[3], r0
; CHECK-NEXT: vmov.u8 r0, q0[4]
; CHECK-NEXT: vmov.16 q3[4], r0
; CHECK-NEXT: vmov.u8 r0, q0[5]
; CHECK-NEXT: vmov.16 q3[5], r0
; CHECK-NEXT: vmov.u8 r0, q0[6]
; CHECK-NEXT: vmov.16 q3[6], r0
; CHECK-NEXT: vmov.u8 r0, q0[7]
; CHECK-NEXT: vmov.16 q3[7], r0
; CHECK-NEXT: vmullb.s8 q2, q3, q2
; CHECK-NEXT: vshr.u16 q3, q2, #8
; CHECK-NEXT: vmov.u16 r0, q3[0]
; CHECK-NEXT: vmov.8 q2[0], r0
; CHECK-NEXT: vmov.u16 r0, q3[1]
; CHECK-NEXT: vmov.8 q2[1], r0
; CHECK-NEXT: vmov.u16 r0, q3[2]
; CHECK-NEXT: vmov.8 q2[2], r0
; CHECK-NEXT: vmov.u16 r0, q3[3]
; CHECK-NEXT: vmov.8 q2[3], r0
; CHECK-NEXT: vmov.u16 r0, q3[4]
; CHECK-NEXT: vmov.8 q2[4], r0
; CHECK-NEXT: vmov.u16 r0, q3[5]
; CHECK-NEXT: vmov.8 q2[5], r0
; CHECK-NEXT: vmov.u16 r0, q3[6]
; CHECK-NEXT: vmov.8 q2[6], r0
; CHECK-NEXT: vmov.u16 r0, q3[7]
; CHECK-NEXT: vmov.8 q2[7], r0
; CHECK-NEXT: vmov.u8 r0, q1[8]
; CHECK-NEXT: vmov.16 q3[0], r0
; CHECK-NEXT: vmov.u8 r0, q1[9]
; CHECK-NEXT: vmov.16 q3[1], r0
; CHECK-NEXT: vmov.u8 r0, q1[10]
; CHECK-NEXT: vmov.16 q3[2], r0
; CHECK-NEXT: vmov.u8 r0, q1[11]
; CHECK-NEXT: vmov.16 q3[3], r0
; CHECK-NEXT: vmov.u8 r0, q1[12]
; CHECK-NEXT: vmov.16 q3[4], r0
; CHECK-NEXT: vmov.u8 r0, q1[13]
; CHECK-NEXT: vmov.16 q3[5], r0
; CHECK-NEXT: vmov.u8 r0, q1[14]
; CHECK-NEXT: vmov.16 q3[6], r0
; CHECK-NEXT: vmov.u8 r0, q1[15]
; CHECK-NEXT: vmov.16 q3[7], r0
; CHECK-NEXT: vmov.u8 r0, q0[8]
; CHECK-NEXT: vmov.16 q1[0], r0
; CHECK-NEXT: vmov.u8 r0, q0[9]
; CHECK-NEXT: vmov.16 q1[1], r0
; CHECK-NEXT: vmov.u8 r0, q0[10]
; CHECK-NEXT: vmov.16 q1[2], r0
; CHECK-NEXT: vmov.u8 r0, q0[11]
; CHECK-NEXT: vmov.16 q1[3], r0
; CHECK-NEXT: vmov.u8 r0, q0[12]
; CHECK-NEXT: vmov.16 q1[4], r0
; CHECK-NEXT: vmov.u8 r0, q0[13]
; CHECK-NEXT: vmov.16 q1[5], r0
; CHECK-NEXT: vmov.u8 r0, q0[14]
; CHECK-NEXT: vmov.16 q1[6], r0
; CHECK-NEXT: vmov.u8 r0, q0[15]
; CHECK-NEXT: vmov.16 q1[7], r0
; CHECK-NEXT: vmullb.s8 q0, q1, q3
; CHECK-NEXT: vshr.u16 q0, q0, #8 ; CHECK-NEXT: vshr.u16 q0, q0, #8
; CHECK-NEXT: vmov.u16 r0, q0[0] ; CHECK-NEXT: vmovnt.i16 q0, q2
; CHECK-NEXT: vmov.8 q2[8], r0
; CHECK-NEXT: vmov.u16 r0, q0[1]
; CHECK-NEXT: vmov.8 q2[9], r0
; CHECK-NEXT: vmov.u16 r0, q0[2]
; CHECK-NEXT: vmov.8 q2[10], r0
; CHECK-NEXT: vmov.u16 r0, q0[3]
; CHECK-NEXT: vmov.8 q2[11], r0
; CHECK-NEXT: vmov.u16 r0, q0[4]
; CHECK-NEXT: vmov.8 q2[12], r0
; CHECK-NEXT: vmov.u16 r0, q0[5]
; CHECK-NEXT: vmov.8 q2[13], r0
; CHECK-NEXT: vmov.u16 r0, q0[6]
; CHECK-NEXT: vmov.8 q2[14], r0
; CHECK-NEXT: vmov.u16 r0, q0[7]
; CHECK-NEXT: vmov.8 q2[15], r0
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s0s = sext <16 x i8> %s0 to <16 x i16> %s0s = sext <16 x i8> %s0 to <16 x i16>
%s1s = sext <16 x i8> %s1 to <16 x i16> %s1s = sext <16 x i8> %s1 to <16 x i16>
%m = mul <16 x i16> %s0s, %s1s %m = mul <16 x i16> %s0s, %s1s
%s = ashr <16 x i16> %m, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> %s = ashr <16 x i16> %m, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
%s2 = trunc <16 x i16> %s to <16 x i8> %s2 = trunc <16 x i16> %s to <16 x i8>
ret <16 x i8> %s2 ret <16 x i8> %s2
} }
define arm_aapcs_vfpcc <16 x i8> @vmulhu_v16i8(<16 x i8> %s0, <16 x i8> %s1) { define arm_aapcs_vfpcc <16 x i8> @vmulhu_v16i8(<16 x i8> %s0, <16 x i8> %s1) {
; CHECK-LABEL: vmulhu_v16i8: ; CHECK-LABEL: vmulhu_v16i8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.u8 r0, q1[0] ; CHECK-NEXT: vmullt.u8 q2, q0, q1
; CHECK-NEXT: vmov.16 q2[0], r0 ; CHECK-NEXT: vmullb.u8 q0, q0, q1
; CHECK-NEXT: vmov.u8 r0, q1[1] ; CHECK-NEXT: vshr.u16 q2, q2, #8
; CHECK-NEXT: vmov.16 q2[1], r0
; CHECK-NEXT: vmov.u8 r0, q1[2]
; CHECK-NEXT: vmov.16 q2[2], r0
; CHECK-NEXT: vmov.u8 r0, q1[3]
; CHECK-NEXT: vmov.16 q2[3], r0
; CHECK-NEXT: vmov.u8 r0, q1[4]
; CHECK-NEXT: vmov.16 q2[4], r0
; CHECK-NEXT: vmov.u8 r0, q1[5]
; CHECK-NEXT: vmov.16 q2[5], r0
; CHECK-NEXT: vmov.u8 r0, q1[6]
; CHECK-NEXT: vmov.16 q2[6], r0
; CHECK-NEXT: vmov.u8 r0, q1[7]
; CHECK-NEXT: vmov.16 q2[7], r0
; CHECK-NEXT: vmov.u8 r0, q0[0]
; CHECK-NEXT: vmov.16 q3[0], r0
; CHECK-NEXT: vmov.u8 r0, q0[1]
; CHECK-NEXT: vmov.16 q3[1], r0
; CHECK-NEXT: vmov.u8 r0, q0[2]
; CHECK-NEXT: vmov.16 q3[2], r0
; CHECK-NEXT: vmov.u8 r0, q0[3]
; CHECK-NEXT: vmov.16 q3[3], r0
; CHECK-NEXT: vmov.u8 r0, q0[4]
; CHECK-NEXT: vmov.16 q3[4], r0
; CHECK-NEXT: vmov.u8 r0, q0[5]
; CHECK-NEXT: vmov.16 q3[5], r0
; CHECK-NEXT: vmov.u8 r0, q0[6]
; CHECK-NEXT: vmov.16 q3[6], r0
; CHECK-NEXT: vmov.u8 r0, q0[7]
; CHECK-NEXT: vmov.16 q3[7], r0
; CHECK-NEXT: vmullb.u8 q2, q3, q2
; CHECK-NEXT: vshr.u16 q3, q2, #8
; CHECK-NEXT: vmov.u16 r0, q3[0]
; CHECK-NEXT: vmov.8 q2[0], r0
; CHECK-NEXT: vmov.u16 r0, q3[1]
; CHECK-NEXT: vmov.8 q2[1], r0
; CHECK-NEXT: vmov.u16 r0, q3[2]
; CHECK-NEXT: vmov.8 q2[2], r0
; CHECK-NEXT: vmov.u16 r0, q3[3]
; CHECK-NEXT: vmov.8 q2[3], r0
; CHECK-NEXT: vmov.u16 r0, q3[4]
; CHECK-NEXT: vmov.8 q2[4], r0
; CHECK-NEXT: vmov.u16 r0, q3[5]
; CHECK-NEXT: vmov.8 q2[5], r0
; CHECK-NEXT: vmov.u16 r0, q3[6]
; CHECK-NEXT: vmov.8 q2[6], r0
; CHECK-NEXT: vmov.u16 r0, q3[7]
; CHECK-NEXT: vmov.8 q2[7], r0
; CHECK-NEXT: vmov.u8 r0, q1[8]
; CHECK-NEXT: vmov.16 q3[0], r0
; CHECK-NEXT: vmov.u8 r0, q1[9]
; CHECK-NEXT: vmov.16 q3[1], r0
; CHECK-NEXT: vmov.u8 r0, q1[10]
; CHECK-NEXT: vmov.16 q3[2], r0
; CHECK-NEXT: vmov.u8 r0, q1[11]
; CHECK-NEXT: vmov.16 q3[3], r0
; CHECK-NEXT: vmov.u8 r0, q1[12]
; CHECK-NEXT: vmov.16 q3[4], r0
; CHECK-NEXT: vmov.u8 r0, q1[13]
; CHECK-NEXT: vmov.16 q3[5], r0
; CHECK-NEXT: vmov.u8 r0, q1[14]
; CHECK-NEXT: vmov.16 q3[6], r0
; CHECK-NEXT: vmov.u8 r0, q1[15]
; CHECK-NEXT: vmov.16 q3[7], r0
; CHECK-NEXT: vmov.u8 r0, q0[8]
; CHECK-NEXT: vmov.16 q1[0], r0
; CHECK-NEXT: vmov.u8 r0, q0[9]
; CHECK-NEXT: vmov.16 q1[1], r0
; CHECK-NEXT: vmov.u8 r0, q0[10]
; CHECK-NEXT: vmov.16 q1[2], r0
; CHECK-NEXT: vmov.u8 r0, q0[11]
; CHECK-NEXT: vmov.16 q1[3], r0
; CHECK-NEXT: vmov.u8 r0, q0[12]
; CHECK-NEXT: vmov.16 q1[4], r0
; CHECK-NEXT: vmov.u8 r0, q0[13]
; CHECK-NEXT: vmov.16 q1[5], r0
; CHECK-NEXT: vmov.u8 r0, q0[14]
; CHECK-NEXT: vmov.16 q1[6], r0
; CHECK-NEXT: vmov.u8 r0, q0[15]
; CHECK-NEXT: vmov.16 q1[7], r0
; CHECK-NEXT: vmullb.u8 q0, q1, q3
; CHECK-NEXT: vshr.u16 q0, q0, #8 ; CHECK-NEXT: vshr.u16 q0, q0, #8
; CHECK-NEXT: vmov.u16 r0, q0[0] ; CHECK-NEXT: vmovnt.i16 q0, q2
; CHECK-NEXT: vmov.8 q2[8], r0
; CHECK-NEXT: vmov.u16 r0, q0[1]
; CHECK-NEXT: vmov.8 q2[9], r0
; CHECK-NEXT: vmov.u16 r0, q0[2]
; CHECK-NEXT: vmov.8 q2[10], r0
; CHECK-NEXT: vmov.u16 r0, q0[3]
; CHECK-NEXT: vmov.8 q2[11], r0
; CHECK-NEXT: vmov.u16 r0, q0[4]
; CHECK-NEXT: vmov.8 q2[12], r0
; CHECK-NEXT: vmov.u16 r0, q0[5]
; CHECK-NEXT: vmov.8 q2[13], r0
; CHECK-NEXT: vmov.u16 r0, q0[6]
; CHECK-NEXT: vmov.8 q2[14], r0
; CHECK-NEXT: vmov.u16 r0, q0[7]
; CHECK-NEXT: vmov.8 q2[15], r0
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%s0s = zext <16 x i8> %s0 to <16 x i16> %s0s = zext <16 x i8> %s0 to <16 x i16>
%s1s = zext <16 x i8> %s1 to <16 x i16> %s1s = zext <16 x i8> %s1 to <16 x i16>
%m = mul <16 x i16> %s0s, %s1s %m = mul <16 x i16> %s0s, %s1s
%s = lshr <16 x i16> %m, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> %s = lshr <16 x i16> %m, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
%s2 = trunc <16 x i16> %s to <16 x i8> %s2 = trunc <16 x i16> %s to <16 x i8>
ret <16 x i8> %s2 ret <16 x i8> %s2
} }