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[RISCV] Prevent selecting a 0 VL to X0 for the segment load/store intrinsics.
ClosedPublic

Authored by craig.topper on Feb 18 2021, 7:32 PM.

Details

Summary

Just like we do for isel patterns, we need to call selectVLOp
to prevent 0 from being selected to X0 by the default isel.

Diff Detail

Event Timeline

craig.topper created this revision.Feb 18 2021, 7:32 PM
craig.topper requested review of this revision.Feb 18 2021, 7:32 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 18 2021, 7:32 PM
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frasercrmck accepted this revision.Feb 19 2021, 6:18 AM

LGTM otherwise.

llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
6

Stray 1 at the end here?

This revision is now accepted and ready to land.Feb 19 2021, 6:18 AM
This revision was landed with ongoing or failed builds.Feb 19 2021, 10:07 AM
This revision was automatically updated to reflect the committed changes.