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Differential D97021

[RISCV] Prevent selecting a 0 VL to X0 for the segment load/store intrinsics.
ClosedPublic

Authored by craig.topper on Feb 18 2021, 7:32 PM.

Details

Reviewers
frasercrmck
HsiangKai
evandro
khchen
arcbbb
rogfer01
Commits
rGdbf910f0d950: [RISCV] Prevent selecting a 0 VL to X0 for the segment load/store intrinsics.
Summary

Just like we do for isel patterns, we need to call selectVLOp
to prevent 0 from being selected to X0 by the default isel.

Diff Detail

Event Timeline

craig.topper created this revision.Feb 18 2021, 7:32 PM
Herald added subscribers: StephenFan, vkmr, luismarques and 23 others. · View Herald TranscriptFeb 18 2021, 7:32 PM
craig.topper requested review of this revision.Feb 18 2021, 7:32 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 18 2021, 7:32 PM
Herald added a subscriber: MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B89845: Diff 324849.Feb 18 2021, 9:28 PM
frasercrmck accepted this revision.Feb 19 2021, 6:18 AM

LGTM otherwise.

llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
7

Stray 1 at the end here?

This revision is now accepted and ready to land.Feb 19 2021, 6:18 AM
This revision was landed with ongoing or failed builds.Feb 19 2021, 10:07 AM
Closed by commit rGdbf910f0d950: [RISCV] Prevent selecting a 0 VL to X0 for the segment load/store intrinsics. (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rGdbf910f0d950: [RISCV] Prevent selecting a 0 VL to X0 for the segment load/store intrinsics..

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
20 lines
test/
CodeGen/
RISCV/
rvv/
261 lines

Diff 325026

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Show First 20 Lines • Show All 195 Lines • ▼ Show 20 Lines if (IsMasked) {
Operands.push_back(MaskedOff); Operands.push_back(MaskedOff);
CurOp += NF; CurOp += NF;
} }
Operands.push_back(Node->getOperand(CurOp++)); // Base pointer. Operands.push_back(Node->getOperand(CurOp++)); // Base pointer.
if (IsStrided) if (IsStrided)
Operands.push_back(Node->getOperand(CurOp++)); // Stride. Operands.push_back(Node->getOperand(CurOp++)); // Stride.
if (IsMasked) if (IsMasked)
Operands.push_back(Node->getOperand(CurOp++)); // Mask. Operands.push_back(Node->getOperand(CurOp++)); // Mask.
Operands.push_back(Node->getOperand(CurOp++)); // VL. SDValue VL;
selectVLOp(Node->getOperand(CurOp++), VL);
Operands.push_back(VL);
Operands.push_back(SEW); Operands.push_back(SEW);
Operands.push_back(Node->getOperand(0)); // Chain. Operands.push_back(Node->getOperand(0)); // Chain.
const RISCV::VLSEGPseudo *P = const RISCV::VLSEGPseudo *P =
RISCV::getVLSEGPseudo(NF, IsMasked, IsStrided, /*FF*/ false, ScalarSize, RISCV::getVLSEGPseudo(NF, IsMasked, IsStrided, /*FF*/ false, ScalarSize,
static_cast<unsigned>(LMUL)); static_cast<unsigned>(LMUL));
SDNode *Load = SDNode *Load =
CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other, Operands); CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other, Operands);
SDValue SuperReg = SDValue(Load, 0); SDValue SuperReg = SDValue(Load, 0);
Show All 22 Lines SmallVector<SDValue, 8> Regs(Node->op_begin() + CurOp,
Node->op_begin() + CurOp + NF); Node->op_begin() + CurOp + NF);
SDValue MaskedOff = createTuple(*CurDAG, Regs, NF, LMUL); SDValue MaskedOff = createTuple(*CurDAG, Regs, NF, LMUL);
Operands.push_back(MaskedOff); Operands.push_back(MaskedOff);
CurOp += NF; CurOp += NF;
} }
Operands.push_back(Node->getOperand(CurOp++)); // Base pointer. Operands.push_back(Node->getOperand(CurOp++)); // Base pointer.
if (IsMasked) if (IsMasked)
Operands.push_back(Node->getOperand(CurOp++)); // Mask. Operands.push_back(Node->getOperand(CurOp++)); // Mask.
Operands.push_back(Node->getOperand(CurOp++)); // VL. SDValue VL;
selectVLOp(Node->getOperand(CurOp++), VL);
Operands.push_back(VL);
Operands.push_back(SEW); Operands.push_back(SEW);
Operands.push_back(Node->getOperand(0)); // Chain. Operands.push_back(Node->getOperand(0)); // Chain.
const RISCV::VLSEGPseudo *P = const RISCV::VLSEGPseudo *P =
RISCV::getVLSEGPseudo(NF, IsMasked, /*Strided*/ false, /*FF*/ true, RISCV::getVLSEGPseudo(NF, IsMasked, /*Strided*/ false, /*FF*/ true,
ScalarSize, static_cast<unsigned>(LMUL)); ScalarSize, static_cast<unsigned>(LMUL));
SDNode *Load = CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other, SDNode *Load = CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other,
MVT::Glue, Operands); MVT::Glue, Operands);
SDNode *ReadVL = CurDAG->getMachineNode(RISCV::PseudoReadVL, DL, XLenVT, SDNode *ReadVL = CurDAG->getMachineNode(RISCV::PseudoReadVL, DL, XLenVT,
Show All 28 Lines if (IsMasked) {
Operands.push_back(MaskedOff); Operands.push_back(MaskedOff);
CurOp += NF; CurOp += NF;
} }
Operands.push_back(Node->getOperand(CurOp++)); // Base pointer. Operands.push_back(Node->getOperand(CurOp++)); // Base pointer.
Operands.push_back(Node->getOperand(CurOp++)); // Index. Operands.push_back(Node->getOperand(CurOp++)); // Index.
MVT IndexVT = Operands.back()->getSimpleValueType(0); MVT IndexVT = Operands.back()->getSimpleValueType(0);
if (IsMasked) if (IsMasked)
Operands.push_back(Node->getOperand(CurOp++)); // Mask. Operands.push_back(Node->getOperand(CurOp++)); // Mask.
Operands.push_back(Node->getOperand(CurOp++)); // VL. SDValue VL;
selectVLOp(Node->getOperand(CurOp++), VL);
Operands.push_back(VL);
Operands.push_back(SEW); Operands.push_back(SEW);
Operands.push_back(Node->getOperand(0)); // Chain. Operands.push_back(Node->getOperand(0)); // Chain.
RISCVVLMUL IndexLMUL = getLMUL(IndexVT); RISCVVLMUL IndexLMUL = getLMUL(IndexVT);
unsigned IndexScalarSize = IndexVT.getScalarSizeInBits(); unsigned IndexScalarSize = IndexVT.getScalarSizeInBits();
const RISCV::VLXSEGPseudo *P = RISCV::getVLXSEGPseudo( const RISCV::VLXSEGPseudo *P = RISCV::getVLXSEGPseudo(
NF, IsMasked, IsOrdered, IndexScalarSize, static_cast<unsigned>(LMUL), NF, IsMasked, IsOrdered, IndexScalarSize, static_cast<unsigned>(LMUL),
static_cast<unsigned>(IndexLMUL)); static_cast<unsigned>(IndexLMUL));
Show All 27 Linesvoid RISCVDAGToDAGISel::selectVSSEG(SDNode *Node, bool IsMasked,
SmallVector<SDValue, 7> Operands; SmallVector<SDValue, 7> Operands;
Operands.push_back(StoreVal); Operands.push_back(StoreVal);
unsigned CurOp = 2 + NF; unsigned CurOp = 2 + NF;
Operands.push_back(Node->getOperand(CurOp++)); // Base pointer. Operands.push_back(Node->getOperand(CurOp++)); // Base pointer.
if (IsStrided) if (IsStrided)
Operands.push_back(Node->getOperand(CurOp++)); // Stride. Operands.push_back(Node->getOperand(CurOp++)); // Stride.
if (IsMasked) if (IsMasked)
Operands.push_back(Node->getOperand(CurOp++)); // Mask. Operands.push_back(Node->getOperand(CurOp++)); // Mask.
Operands.push_back(Node->getOperand(CurOp++)); // VL. SDValue VL;
selectVLOp(Node->getOperand(CurOp++), VL);
Operands.push_back(VL);
Operands.push_back(SEW); Operands.push_back(SEW);
Operands.push_back(Node->getOperand(0)); // Chain. Operands.push_back(Node->getOperand(0)); // Chain.
const RISCV::VSSEGPseudo *P = RISCV::getVSSEGPseudo( const RISCV::VSSEGPseudo *P = RISCV::getVSSEGPseudo(
NF, IsMasked, IsStrided, ScalarSize, static_cast<unsigned>(LMUL)); NF, IsMasked, IsStrided, ScalarSize, static_cast<unsigned>(LMUL));
SDNode *Store = SDNode *Store =
CurDAG->getMachineNode(P->Pseudo, DL, Node->getValueType(0), Operands); CurDAG->getMachineNode(P->Pseudo, DL, Node->getValueType(0), Operands);
ReplaceNode(Node, Store); ReplaceNode(Node, Store);
} }
Show All 14 Linesvoid RISCVDAGToDAGISel::selectVSXSEG(SDNode *Node, bool IsMasked,
SDValue StoreVal = createTuple(*CurDAG, Regs, NF, LMUL); SDValue StoreVal = createTuple(*CurDAG, Regs, NF, LMUL);
Operands.push_back(StoreVal); Operands.push_back(StoreVal);
unsigned CurOp = 2 + NF; unsigned CurOp = 2 + NF;
Operands.push_back(Node->getOperand(CurOp++)); // Base pointer. Operands.push_back(Node->getOperand(CurOp++)); // Base pointer.
Operands.push_back(Node->getOperand(CurOp++)); // Index. Operands.push_back(Node->getOperand(CurOp++)); // Index.
MVT IndexVT = Operands.back()->getSimpleValueType(0); MVT IndexVT = Operands.back()->getSimpleValueType(0);
if (IsMasked) if (IsMasked)
Operands.push_back(Node->getOperand(CurOp++)); // Mask. Operands.push_back(Node->getOperand(CurOp++)); // Mask.
Operands.push_back(Node->getOperand(CurOp++)); // VL. SDValue VL;
selectVLOp(Node->getOperand(CurOp++), VL);
Operands.push_back(VL);
Operands.push_back(SEW); Operands.push_back(SEW);
Operands.push_back(Node->getOperand(0)); // Chain. Operands.push_back(Node->getOperand(0)); // Chain.
RISCVVLMUL IndexLMUL = getLMUL(IndexVT); RISCVVLMUL IndexLMUL = getLMUL(IndexVT);
unsigned IndexScalarSize = IndexVT.getScalarSizeInBits(); unsigned IndexScalarSize = IndexVT.getScalarSizeInBits();
const RISCV::VSXSEGPseudo *P = RISCV::getVSXSEGPseudo( const RISCV::VSXSEGPseudo *P = RISCV::getVSXSEGPseudo(
NF, IsMasked, IsOrdered, IndexScalarSize, static_cast<unsigned>(LMUL), NF, IsMasked, IsOrdered, IndexScalarSize, static_cast<unsigned>(LMUL),
static_cast<unsigned>(IndexLMUL)); static_cast<unsigned>(IndexLMUL));
▲ Show 20 Lines • Show All 855 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \
; RUN: -verify-machineinstrs < %s | FileCheck %s
; Make sure we don't select a 0 vl to X0 in the custom isel handlers we use
; for these intrinsics.
frasercrmckUnsubmitted
Not Done
ReplyInline Actions

Stray 1 at the end here?

frasercrmck: Stray `1` at the end here?
declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.nxv16i16(i16* , i64)
declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i1>, i64)
define <vscale x 16 x i16> @test_vlseg2_mask_nxv16i16(i16* %base, <vscale x 16 x i1> %mask) {
; CHECK-LABEL: test_vlseg2_mask_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mv a1, zero
; CHECK-NEXT: vsetvli a2, a1, e16,m4,ta,mu
; CHECK-NEXT: vlseg2e16.v v4, (a0)
; CHECK-NEXT: vmv4r.v v8, v4
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vlseg2e16.v v4, (a0), v0.t
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.nxv16i16(i16* %base, i64 0)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
%2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlseg2.mask.nxv16i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 16 x i1> %mask, i64 0)
%3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
ret <vscale x 16 x i16> %3
}
declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.nxv16i16(i16*, i64, i64)
declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i64, <vscale x 16 x i1>, i64)
define <vscale x 16 x i16> @test_vlsseg2_mask_nxv16i16(i16* %base, i64 %offset, <vscale x 16 x i1> %mask) {
; CHECK-LABEL: test_vlsseg2_mask_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mv a2, zero
; CHECK-NEXT: vsetvli a3, a2, e16,m4,ta,mu
; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1
; CHECK-NEXT: vmv4r.v v8, v4
; CHECK-NEXT: vsetvli a2, a2, e16,m4,tu,mu
; CHECK-NEXT: vlsseg2e16.v v4, (a0), a1, v0.t
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.nxv16i16(i16* %base, i64 %offset, i64 0)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
%2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vlsseg2.mask.nxv16i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 0)
%3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
ret <vscale x 16 x i16> %3
}
declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vloxseg2.nxv16i16.nxv16i16(i16*, <vscale x 16 x i16>, i64)
declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vloxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
define <vscale x 16 x i16> @test_vloxseg2_mask_nxv16i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask) {
; CHECK-LABEL: test_vloxseg2_mask_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mv a1, zero
; CHECK-NEXT: vsetvli a2, a1, e16,m4,ta,mu
; CHECK-NEXT: vloxseg2ei16.v v12, (a0), v8
; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vloxseg2ei16.v v12, (a0), v8, v0.t
; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vloxseg2.nxv16i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 0)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
%2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vloxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 0)
%3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
ret <vscale x 16 x i16> %3
}
declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv16i16(i16*, <vscale x 16 x i16>, i64)
declare {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
define <vscale x 16 x i16> @test_vluxseg2_mask_nxv16i16_nxv16i16(i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask) {
; CHECK-LABEL: test_vluxseg2_mask_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mv a1, zero
; CHECK-NEXT: vsetvli a2, a1, e16,m4,ta,mu
; CHECK-NEXT: vluxseg2ei16.v v12, (a0), v8
; CHECK-NEXT: vmv4r.v v16, v12
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vluxseg2ei16.v v12, (a0), v8, v0.t
; CHECK-NEXT: vmv4r.v v8, v16
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.nxv16i16.nxv16i16(i16* %base, <vscale x 16 x i16> %index, i64 0)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %0, 0
%2 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>} @llvm.riscv.vluxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16> %1,<vscale x 16 x i16> %1, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 0)
%3 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>} %2, 1
ret <vscale x 16 x i16> %3
}
declare {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.nxv16i16(i16* , i64)
declare {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i1>, i64)
define <vscale x 16 x i16> @test_vlseg2ff_nxv16i16(i16* %base, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mv a2, zero
; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v4, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a1)
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.nxv16i16(i16* %base, i64 0)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 16 x i16> %1
}
define <vscale x 16 x i16> @test_vlseg2ff_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv4r.v v4, v8
; CHECK-NEXT: mv a2, zero
; CHECK-NEXT: vsetvli a2, a2, e16,m4,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v4, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a1)
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64 0)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 16 x i16> %1
}
declare void @llvm.riscv.vsseg2.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16* , i64)
declare void @llvm.riscv.vsseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i1>, i64)
define void @test_vsseg2_nxv16i16(<vscale x 16 x i16> %val, i16* %base) {
; CHECK-LABEL: test_vsseg2_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: mv a1, zero
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vsseg2e16.v v8, (a0)
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsseg2.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, i64 0)
ret void
}
define void @test_vsseg2_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask) {
; CHECK-LABEL: test_vsseg2_mask_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: mv a1, zero
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vsseg2e16.v v8, (a0), v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsseg2.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64 0)
ret void
}
declare void @llvm.riscv.vssseg2.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i64, i64)
declare void @llvm.riscv.vssseg2.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, i64, <vscale x 16 x i1>, i64)
define void @test_vssseg2_nxv16i16(<vscale x 16 x i16> %val, i16* %base, i64 %offset) {
; CHECK-LABEL: test_vssseg2_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: mv a2, zero
; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu
; CHECK-NEXT: vssseg2e16.v v8, (a0), a1
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vssseg2.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, i64 %offset, i64 0)
ret void
}
define void @test_vssseg2_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, i64 %offset, <vscale x 16 x i1> %mask) {
; CHECK-LABEL: test_vssseg2_mask_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: mv a2, zero
; CHECK-NEXT: vsetvli a2, a2, e16,m4,ta,mu
; CHECK-NEXT: vssseg2e16.v v8, (a0), a1, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vssseg2.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, i64 %offset, <vscale x 16 x i1> %mask, i64 0)
ret void
}
declare void @llvm.riscv.vsoxseg2.nxv16i16.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i16>, i64)
declare void @llvm.riscv.vsoxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
define void @test_vsoxseg2_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index) {
; CHECK-LABEL: test_vsoxseg2_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
; CHECK-NEXT: vmv4r.v v28, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: mv a1, zero
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v28
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 0)
ret void
}
define void @test_vsoxseg2_mask_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask) {
; CHECK-LABEL: test_vsoxseg2_mask_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
; CHECK-NEXT: vmv4r.v v28, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: mv a1, zero
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vsoxseg2ei16.v v8, (a0), v28, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsoxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 0)
ret void
}
declare void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i16>, i64)
declare void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i16>, <vscale x 16 x i1>, i64)
define void @test_vsuxseg2_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index) {
; CHECK-LABEL: test_vsuxseg2_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
; CHECK-NEXT: vmv4r.v v28, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: mv a1, zero
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, i64 0)
ret void
}
define void @test_vsuxseg2_mask_nxv16i16_nxv16i16(<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask) {
; CHECK-LABEL: test_vsuxseg2_mask_nxv16i16_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v8m4_v12m4 def $v8m4_v12m4
; CHECK-NEXT: vmv4r.v v28, v12
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: mv a1, zero
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vsuxseg2ei16.v v8, (a0), v28, v0.t
; CHECK-NEXT: ret
entry:
tail call void @llvm.riscv.vsuxseg2.mask.nxv16i16.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i16> %index, <vscale x 16 x i1> %mask, i64 0)
ret void
}