[THUMB2] add .w suffixes for ldr/str (immediate) T4

[nickdesaulniers]

Summary

The Linux kernel when built with CONFIG_THUMB2_KERNEL makes use of these
instructions with immediate operands and wide encodings.

These are the T4 variants of the follow sections from the Arm ARM.
F5.1.72 LDR (immediate)
F5.1.229 STR (immediate)

I wasn't able to represent these simple aliases using t2InstAlias due to
the Constraints on the non-suffixed existing instructions, which results
in some manual parsing logic needing to be added.

F1.2 Standard assembler syntax fields
describes the use of the .w (wide) vs .n (narrow) encoding suffix.

Link: https://bugs.llvm.org/show_bug.cgi?id=49118
Link: https://github.com/ClangBuiltLinux/linux/issues/1296
Reported-by: Stefan Agner <[e-mail]>
Reported-by: Arnd Bergmann <[e-mail]>
Signed-off-by: Nick Desaulniers <[e-mail]>

[nickdesaulniers]

There's some TODO's I plan to clean up in the test, but looking for feedback before I pursue further additions.

[DavidSpickett]

TLDR: I tried to track down the meaning of .w for the assembler and the encodings. They seem to be slightly different but I think the assembler side is clear and that's what we need here.

The explanation of .w in the armarm:

A8.2 Standard assembler syntax fields

Specifies optional assembler qualifiers on the instruction.

The following qualifiers are defined:
.N Meaning narrow, specifies that the assembler must select a 16-bit encoding for the
instruction. If this is not possible, an assembler error is produced.

.W Meaning wide, specifies that the assembler must select a 32-bit encoding for the
instruction. If this is not possible, an assembler error is produced.

If neither .W nor .N is specified, the assembler can select either 16-bit or 32-bit encodings. If both
are available, it must select a 16-bit encoding. In a few cases, more than one encoding of the same
length can be available for an instruction. The rules for selecting between such encodings are
instruction-specific and are part of the instruction description

Which explains the assembler's point of view. Less clear, is what a .W means in an instruction description.

A8.1.3 Instruction encodings

For example, the assembler
syntax documented for the 32-bit Thumb AND (register) encoding includes the .W qualifier to ensure that the
32-bit encoding is selected even for the small proportion of operand combinations for which the 16-bit
encoding is also available.

Which is not a great example because when I tested this with gcc, it would prefer 16 bit encodings in most situations
that I could come up with. However, AND has conditions for being in or out of an IT block so that might be higher priority than any .w encoding.

For LDR there's no IT block stuff to consider, but gcc still prefers the smaller encoding if possible.

.syntax unified

// This could fit into 16 bit T1, but should prefer T3 with the .w?
// Uses T1
// (which seems to contradict the AND example but hey)
ldr r3, [r1, #124]
// Will be T3 due to us adding .w
ldr.w r3, [r1, #124]
// This can only fit into T3 because of the 12 bit immediate
ldr r3, [r1, #0x1ff]
// T3 because it has the .W suffix in the description, could fit into T4 as well
ldr.w r3, [r1, #255]
// Uses T4 due to post increment
ldr.w r3, [r1], #255

So my best guess is that I am misunderstanding the AND example and that .W marks the preferred 32 bit thumb encoding.

The assembler will:

• try to use 16 bits
• try to use 32 bits
• if there are multiple 32 bit encodings that could apply, use the one with .W

Note that there are some instructions like ADR where T2 and T3 have .W. In this case (and I assume other cases) the two clearly wouldn't overlap so it's still decidable which one should be used.
Also, some instructions have only one 32 bit encoding, which has .W. I expect this just makes the logic easier if you can say "every instruction that has 32 bit encodings has a preferred one".

This is all to support reassembly to the same bit patterns. If we assemble "ldr.w r3, [r1, #255]" and get T3, then disassemble, we get "ldr.w r3, [r1, #255]". Reassembling that we want to know we'll get T3 not T4.

Caveat: I can't cite anywhere in the armarm that says ".W means preferred 32 bit". That's just the conclusion I'm drawing from what I've found.

[DavidSpickett]

I just realised that you're only adding the ones that would encode to T4, so the answer to some of my comments will be no, T3 isn't covered. Correct?

I'm not sure how much complexity adding T3 would be. We're ok to encode any pre increment, non writeback into T3 so it could be another alias, with a different immediate check.

llvm/lib/Target/ARM/ARMInstrThumb2.td

1568

Do you mean "$Rn != $Rn_wb". I see what you mean but out of the context of the armarm, != makes more immediate sense.

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

7672

You'll add a check here for PRE too, or is that not needed for some reason?

This would use the imm12 range from the T3 encoding I think.

llvm/test/MC/ARM/thumb2-ldr.w-str.w.s

82

Add pre-increment, no writeback here.

92

You should check pre-increment without writeback, that would use the T3 encoding and have a greater immediate range.

106

For varying the registers you could cut it down to:

• one gpr
• pc (if allowed)
• sp (if allowed)

There's not much utility to the rest.

127

I'd just pick two here. That shows we pass them through correctly, we can assume the rest are ok.

297

pre-increment without writeback

[rengolin]

In D96632#2563111, @DavidSpickett wrote:

A8.1.3 Instruction encodings

For example, the assembler
syntax documented for the 32-bit Thumb AND (register) encoding includes the .W qualifier to ensure that the
32-bit encoding is selected even for the small proportion of operand combinations for which the 16-bit
encoding is also available.

Which is not a great example because when I tested this with gcc, it would prefer 16 bit encodings in most situations
that I could come up with. However, AND has conditions for being in or out of an IT block so that might be higher priority than any .w encoding.

Note that "the assembler" in the quoted text is not GAS specifically. It is the rule that any "conforming" arm assembler must follow.

However, avoiding this particular rule won't generate execution errors, just pick the wrong encoding for the exact same instruction, so if GAS is picking the wrong encoding, it probably decided it was worth it.

This doesn't mean LLVM should do the same. We strongly prefer to follow the rules of the architecture manuals, when available.

[nickdesaulniers]

• add more to comment in .td.
• add parser check for str to pc.
• fix case lint.
• move TODOs for cases where the non-.w suffix already differs from GAS.
• add comment that T4 PRE is with writeback.
• significantly reduce number of test cases.

llvm/lib/Target/ARM/ARMInstrThumb2.td

1568

No; that's what's above for t2LDR_POST (I guess it should be "$addr.base = $Rn_wb" for PRE in my added comment). I tried wrapping these in let blocks while using t2InstAlias to describe the "Constraint"s but it seems I may not be the first to have hit that: https://reviews.llvm.org/D68916#1741416.

I've updated the comment.

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

7672

I'm not really sure if operands have additional validation, but I suspect that the use of t2addrmode_imm8_pre for PRE is validated elsewhere; and perhaps t2am_imm8_offset used for POST is not. If I add checks for pre here and feed in bad input, it wont matter, because we never get this far. I suspect the operand validation is occurring before instruction matching.

For example, consider:

ldr.w r3, [r1, #4095]!

(so T4 pre increment w/ writeback, only accepts immediates in the range [-255,255]). With this patch applied:

error: invalid instruction, any one of the following would fix this:
ldr.w r3, [r1, #4095]!
^
foo.s:17:11: note: invalid operand for instruction
ldr.w r3, [r1, #4095]!
          ^
foo.s:17:22: note: too many operands for instruction
ldr.w r3, [r1, #4095]!
                     ^

which looks to me like the instruction is not getting matched, BEFORE any of this added parsing logic. Perhaps the error text for t2addrmode_imm8_pre could be improved, somehow?

llvm/test/MC/ARM/thumb2-ldr.w-str.w.s

82

The T3 encodings are already tested in llvm/test/MC/ARM/basic-thumb2-instructions.s.
https://github.com/llvm/llvm-project/blob/f8c1f3b14ad988fd786b896b4b342606bdc760cf/llvm/test/MC/ARM/basic-thumb2-instructions.s#L989-L990

[DavidSpickett]

llvm/lib/Target/ARM/ARMInstrThumb2.td

1568

Makes sense now.

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

7672

I'm sure it could be improved but out of scope here. My concern was that we would leave a gap where valid input would be encoded to T4 but not T3. However, clang already accepts the T3 input so it's not an issue.

ldr.w r3, [r1, #4095]
$ ./bin/clang --target=arm-none-eabi -march=armv7-a /tmp/test.s -c -o /tmp/test.o -Wa,-mthumb

llvm/test/MC/ARM/thumb2-ldr.w-str.w.s

82

92

123

Do you have a plan for how to implement these? I assume it's complicated in the same way the alias constraints are.

297

Addressed above.

[DavidSpickett]

llvm/test/MC/ARM/thumb2-ldr.w-str.w.s

123

Should be possible to warn by "return Warning" from ARMAsmParser::validateInstruction but I haven't tried it myself.

[nickdesaulniers]

llvm/test/MC/ARM/thumb2-ldr.w-str.w.s

123

I don't plan to implement those in this commit. The underlying aliased-to instruction doesn't warn.

Specifically, the warning GAS produces is This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.

I'm not sure we have such a warning.

[DavidSpickett]

llvm/test/MC/ARM/thumb2-ldr.w-str.w.s

123

Ah I thought it was the usual sp/pc is always unpredictable stuff. Fine to leave it out here then.

llvm/lib/Target/ARM/ARMInstrThumb2.td

 
 def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
                           (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
                           AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
                           "ldrsh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>,
                   Sched<[WriteLd]>;
 } // mayLoad = 1, hasSideEffects = 0
 
+// F5.1.72 LDR (immediate) T4
+// .w suffixes; Constraints can't be used on t2InstAlias to describe
+// "$Rn =  $Rn_wb" on POST or "$addr.base = $Rn_wb" on PRE.
+def t2LDR_PRE_imm : t2AsmPseudo<"ldr${p}.w $Rt, $addr!",
+                         (ins GPR:$Rt, t2addrmode_imm8_pre:$addr, pred:$p)>;
+def t2LDR_POST_imm : t2AsmPseudo<"ldr${p}.w $Rt, $Rn, $imm",
+                         (ins GPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$imm, pred:$p)>;
+
 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
   : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc,
           "\t$Rt, $addr", []>, Sched<[WriteLd]> {
   bits<4> Rt;
   bits<13> addr;
   let Inst{31-27} = 0b11111;

 def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb),
                (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p),
                4, IIC_iStore_ru,
       [(set GPRnopc:$Rn_wb,
             (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>,
             Sched<[WriteST]>;
 }
 
+// F5.1.229 STR (immediate) T4
+// .w suffixes; Constraints can't be used on t2InstAlias to describe
+// "$Rn =  $Rn_wb,@earlyclobber $Rn_wb" on POST or
+// "$addr.base = $Rn_wb,@earlyclobber $Rn_wb" on PRE.
+def t2STR_PRE_imm : t2AsmPseudo<"str${p}.w $Rt, $addr!",
+  (ins GPR:$Rt, t2addrmode_imm8_pre:$addr, pred:$p)>;
+def t2STR_POST_imm : t2AsmPseudo<"str${p}.w $Rt, $Rn, $imm",
+  (ins GPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$imm, pred:$p)>;
+
 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
 // only.
 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
   : T2Ii8<(outs), (ins rGPR:$Rt, t2addrmode_imm8:$addr), ii, opc,
           "\t$Rt, $addr", []>, Sched<[WriteST]> {
   let Inst{31-27} = 0b11111;
   let Inst{26-25} = 0b00;

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

case ARM::t2STRB_POST: {
     const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
     const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
 
     if (Rt == Rn)
       return Error(Operands[3]->getStartLoc(),
                    "source register and base register can't be identical");
     return false;
   }
+  case ARM::t2LDR_PRE_imm:
+  case ARM::t2LDR_POST_imm:
+  case ARM::t2STR_PRE_imm:
+  case ARM::t2STR_POST_imm: {
+    // Rt must be different from Rn.
+    const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
+    const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(1).getReg());
+
+    if (Rt == Rn)
+      return Error(Operands[3]->getStartLoc(),
+                   "destination register and base register can't be identical");
+    if (Inst.getOpcode() == ARM::t2LDR_POST_imm ||
+        Inst.getOpcode() == ARM::t2STR_POST_imm) {
+      int Imm = Inst.getOperand(2).getImm();
+      if (Imm > 255 || Imm < -255)
+        return Error(Operands[5]->getStartLoc(),
+                     "operand must be in range [-255, 255]");
+    }
+    if (Inst.getOpcode() == ARM::t2STR_PRE_imm ||
+        Inst.getOpcode() == ARM::t2STR_POST_imm) {
+      if (Inst.getOperand(0).getReg() == ARM::PC) {
+        return Error(Operands[3]->getStartLoc(),
+                     "operand must be a register in range [r0, r14]");
+      }
+    }
+    return false;
+  }
   case ARM::LDR_PRE_IMM:
   case ARM::LDR_PRE_REG:
   case ARM::t2LDR_PRE:
   case ARM::LDR_POST_IMM:
   case ARM::LDR_POST_REG:
   case ARM::t2LDR_POST:
   case ARM::LDRH_PRE:
   case ARM::t2LDRH_PRE:
if (Inst.getOperand(2).isImm()) {
                                                         getContext());
       TmpInst.addOperand(MCOperand::createExpr(FixupAddr));
     }
     TmpInst.addOperand(Inst.getOperand(3));
     TmpInst.addOperand(Inst.getOperand(4));
     Inst = TmpInst;
     return true;
   }
+  // Aliases for imm syntax of LDR instructions.
+  case ARM::t2LDR_PRE_imm:
+  case ARM::t2LDR_POST_imm: {
+    MCInst TmpInst;
+    TmpInst.setOpcode(Inst.getOpcode() == ARM::t2LDR_PRE_imm ? ARM::t2LDR_PRE
+                                                             : ARM::t2LDR_POST);
+    TmpInst.addOperand(Inst.getOperand(0)); // Rt
+    TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb
+    TmpInst.addOperand(Inst.getOperand(1)); // Rn
+    TmpInst.addOperand(Inst.getOperand(2)); // imm
+    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
+    Inst = TmpInst;
+    return true;
+  }
+  // Aliases for imm syntax of STR instructions.
+  case ARM::t2STR_PRE_imm:
+  case ARM::t2STR_POST_imm: {
+    MCInst TmpInst;
+    TmpInst.setOpcode(Inst.getOpcode() == ARM::t2STR_PRE_imm ? ARM::t2STR_PRE
+                                                             : ARM::t2STR_POST);
+    TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb
+    TmpInst.addOperand(Inst.getOperand(0)); // Rt
+    TmpInst.addOperand(Inst.getOperand(1)); // Rn
+    TmpInst.addOperand(Inst.getOperand(2)); // imm
+    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
+    Inst = TmpInst;
+    return true;
+  }
   // Aliases for alternate PC+imm syntax of LDR instructions.
   case ARM::t2LDRpcrel:
     // Select the narrow version if the immediate will fit.
     if (Inst.getOperand(1).getImm() > 0 &&
         Inst.getOperand(1).getImm() <= 0xff &&
         !HasWideQualifier)
       Inst.setOpcode(ARM::tLDRpci);
     else

llvm/test/MC/ARM/thumb2-ldr.w-str.w.s

+@ RUN: not llvm-mc -triple=thumbv7-unknown-linux-gnueabi -arm-implicit-it=thumb -show-encoding < %s 2>&1 | FileCheck %s
+.syntax unified
+
+@ Note: The error stream for XFAIL needs to get checked first.
+
+ldr.w r1, [r1, #-4]!
+ldr.w r1, [r0, #256]!
+ldr.w r1, [r0, #-256]!
+ldr.w r1, [pc, #-4]!
+ldr.w r1, [r1], #4
+ldr.w r0, [r0], #4
+ldr.w r0, [r1], #256
+ldr.w r0, [r1], #-256
+str.w r0, [r0, #-4]!
+str.w pc, [r0, #-4]!
+str.w r1, [pc, #-4]!
+str.w r1, [r2, #256]!
+str.w r1, [r2, #-256]!
+str.w r0, [r0], #4
+str.w pc, [r0], #4
+str.w r1, [r0], #256
+str.w r1, [r0], #-256
+
+@@ XFAIL
+
+@ CHECK: error: destination register and base register can't be identical
+@ CHECK-NEXT: ldr.w r1, [r1, #-4]!
+@ CHECK: error: invalid instruction, any one of the following would fix this:
+@ CHECK-NEXT: ldr.w r1, [r0, #256]!
+@ CHECK: note: invalid operand for instruction
+@ CHECK: note: too many operands for instruction
+@ CHECK: error: invalid operand for instruction
+@ CHECK-NEXT: ldr.w r1, [r0, #-256]!
+@ CHECK: error: invalid instruction, any one of the following would fix this:
+@ CHECK-NEXT: ldr.w r1, [pc, #-4]!
+@ CHECK: note: invalid operand for instruction
+@ CHECK: note: too many operands for instruction
+@ CHECK: error: destination register and base register can't be identical
+@ CHECK-NEXT: ldr.w r1, [r1], #4
+@ CHECK: error: destination register and base register can't be identical
+@ CHECK-NEXT: ldr.w r0, [r0], #4
+@ CHECK: error: operand must be in range [-255, 255]
+@ CHECK-NEXT: ldr.w r0, [r1], #256
+@ CHECK: error: operand must be in range [-255, 255]
+@ CHECK-NEXT: ldr.w r0, [r1], #-256
+@ CHECK: error: destination register and base register can't be identical
+@ CHECK-NEXT: str.w r0, [r0, #-4]!
+@ CHECK: error: operand must be a register in range [r0, r14]
+@ CHECK-NEXT: str.w pc, [r0, #-4]!
+@ CHECK: error: invalid operand for instruction
+@ CHECK-NEXT: str.w r1, [pc, #-4]!
+@ CHECK: error: invalid instruction, any one of the following would fix this:
+@ CHECK-NEXT: str.w r1, [r2, #256]!
+@ CHECK: note: invalid operand for instruction
+@ CHECK: note: too many operands for instruction
+@ CHECK: error: invalid operand for instruction
+@ CHECK-NEXT: str.w r1, [r2, #-256]!
+@ CHECK: error: destination register and base register can't be identical
+@ CHECK-NEXT: str.w r0, [r0], #4
+@ CHECK: error: operand must be a register in range [r0, r14]
+@ CHECK-NEXT: str.w pc, [r0], #4
+@ CHECK: error: operand must be in range [-255, 255]
+@ CHECK-NEXT: str.w r1, [r0], #256
+@ CHECK: error: operand must be in range [-255, 255]
+@ CHECK-NEXT: str.w r1, [r0], #-256
+
+@@ XPASS
+
+@ Simple checks that we get the same encoding w/ and w/o the .w suffix.
+ldr r3, [r1], #4
+ldr.w r3, [r1], #4
+
+str r3, [r0], #4
+str.w r3, [r0], #4
+
+ldr r3, [r1, #-4]!
+ldr.w r3, [r1, #-4]!
+
+str r3, [r0, #-4]!
+str.w r3, [r0, #-4]!
+
+@ CHECK: ldr r3, [r1], #4   @ encoding: [0x51,0xf8,0x04,0x3b]
+@ CHECK: ldr r3, [r1], #4   @ encoding: [0x51,0xf8,0x04,0x3b]
+@ CHECK: str r3, [r0], #4   @ encoding: [0x40,0xf8,0x04,0x3b]
+@ CHECK: str r3, [r0], #4   @ encoding: [0x40,0xf8,0x04,0x3b]
+@ CHECK: ldr r3, [r1, #-4]! @ encoding: [0x51,0xf8,0x04,0x3d]
+@ CHECK: ldr r3, [r1, #-4]! @ encoding: [0x51,0xf8,0x04,0x3d]
+@ CHECK: str r3, [r0, #-4]! @ encoding: [0x40,0xf8,0x04,0x3d]
+@ CHECK: str r3, [r0, #-4]! @ encoding: [0x40,0xf8,0x04,0x3d]
+
+@@ LDR pre-increment w/ writeback
+@ Vary Rt.
+ldr.w r0, [r1, #-4]!
+ldr.w sp, [r1, #-4]! @ TODO: GAS warns for this
+ldr.w pc, [r1, #-4]!
+@ Vary Rn.
+ldr.w r1, [r0, #-4]!
+ldr.w r1, [sp, #-4]!
+@ Vary imm.
+ldr.w r1, [r0, #255]!
+ldr.w r1, [r0, #-255]!
+ldr.w r1, [r0, #0]!
+@ Condition codes.
+ldreq.w r1, [r0, #255]!
+ldrle.w r1, [r0, #255]!
+
+@ CHECK: ldr r0, [r1, #-4]!    @ encoding: [0x51,0xf8,0x04,0x0d]
+@ CHECK: ldr sp, [r1, #-4]!    @ encoding: [0x51,0xf8,0x04,0xdd]
+@ CHECK: ldr pc, [r1, #-4]!    @ encoding: [0x51,0xf8,0x04,0xfd]
+@ CHECK: ldr r1, [r0, #-4]!    @ encoding: [0x50,0xf8,0x04,0x1d]
+@ CHECK: ldr r1, [sp, #-4]!    @ encoding: [0x5d,0xf8,0x04,0x1d]
+@ CHECK: ldr r1, [r0, #255]!   @ encoding: [0x50,0xf8,0xff,0x1f]
+@ CHECK: ldr r1, [r0, #-255]!  @ encoding: [0x50,0xf8,0xff,0x1d]
+@ CHECK: ldr r1, [r0, #0]!     @ encoding: [0x50,0xf8,0x00,0x1f]
+@ CHECK: it    eq              @ encoding: [0x08,0xbf]
+@ CHECK: ldreq r1, [r0, #255]! @ encoding: [0x50,0xf8,0xff,0x1f]
+@ CHECK: it    le              @ encoding: [0xd8,0xbf]
+@ CHECK: ldrle r1, [r0, #255]! @ encoding: [0x50,0xf8,0xff,0x1f]
+
+@@ LDR post-increment
+@ Vary Rt.
+ldr.w r0, [r1], #4
+ldr.w sp, [r1], #4 @ TODO: GAS warns for this
+ldr.w pc, [r1], #4
+@ Vary Rn.
+ldr.w r0, [r1], #4
+ldr.w r0, [sp], #4
+ldr.w r0, [pc], #4 @ TODO: GAS warns for this
+@ Vary imm.
+ldr.w r0, [r1], #255
+ldr.w r0, [r1], #0
+ldr.w r0, [r1], #-255
+@ Condition codes.
+ldreq.w r0, [r1], #255
+ldrle.w r0, [r1], #255
+
+@ CHECK: ldr r0, [r1], #4     @ encoding: [0x51,0xf8,0x04,0x0b]
+@ CHECK: ldr sp, [r1], #4     @ encoding: [0x51,0xf8,0x04,0xdb]
+@ CHECK: ldr pc, [r1], #4     @ encoding: [0x51,0xf8,0x04,0xfb]
+@ CHECK: ldr r0, [r1], #4     @ encoding: [0x51,0xf8,0x04,0x0b]
+@ CHECK: ldr r0, [sp], #4     @ encoding: [0x5d,0xf8,0x04,0x0b]
+@ CHECK: ldr r0, [pc], #4     @ encoding: [0x5f,0xf8,0x04,0x0b]
+@ CHECK: ldr r0, [r1], #255   @ encoding: [0x51,0xf8,0xff,0x0b]
+@ CHECK: ldr r0, [r1], #0     @ encoding: [0x51,0xf8,0x00,0x0b]
+@ CHECK: ldr r0, [r1], #-255  @ encoding: [0x51,0xf8,0xff,0x09]
+@ CHECK: it    eq             @ encoding: [0x08,0xbf]
+@ CHECK: ldreq r0, [r1], #255 @ encoding: [0x51,0xf8,0xff,0x0b]
+@ CHECK: it    le             @ encoding: [0xd8,0xbf]
+@ CHECK: ldrle r0, [r1], #255 @ encoding: [0x51,0xf8,0xff,0x0b]
+
+@@ STR pre-increment w/ writeback
+@ Vary Rt.
+str.w r1, [r0, #-4]!
+str.w sp, [r0, #-4]!
+@ Vary Rn.
+str.w r1, [r2, #-4]!
+str.w r1, [sp, #-4]!
+@ Vary imm.
+str.w r1, [r2, #255]!
+str.w r1, [r2, #0]!
+str.w r1, [r2, #-255]!
+@ Condition codes.
+streq.w r1, [r2, #255]!
+strle.w r1, [r2, #255]!
+
+@ CHECK: str r1, [r0, #-4]!     @ encoding: [0x40,0xf8,0x04,0x1d]
+@ CHECK: str sp, [r0, #-4]!     @ encoding: [0x40,0xf8,0x04,0xdd]
+@ CHECK: str r1, [r2, #-4]!     @ encoding: [0x42,0xf8,0x04,0x1d]
+@ CHECK: str r1, [sp, #-4]!     @ encoding: [0x4d,0xf8,0x04,0x1d]
+@ CHECK: str   r1, [r2, #255]!  @ encoding: [0x42,0xf8,0xff,0x1f]
+@ CHECK: str   r1, [r2, #0]!    @ encoding: [0x42,0xf8,0x00,0x1f]
+@ CHECK: str   r1, [r2, #-255]! @ encoding: [0x42,0xf8,0xff,0x1d]
+@ CHECK: it    eq               @ encoding: [0x08,0xbf]
+@ CHECK: streq r1, [r2, #255]!  @ encoding: [0x42,0xf8,0xff,0x1f]
+@ CHECK: it    le               @ encoding: [0xd8,0xbf]
+@ CHECK: strle r1, [r2, #255]!  @ encoding: [0x42,0xf8,0xff,0x1f]
+
+@@ STR post-increment
+@ Vary Rt.
+str.w r1, [r0], #4
+str.w sp, [r0], #4
+@ Vary Rn.
+str.w r0, [r1], #4
+str.w r0, [sp], #4
+str.w r0, [pc], #4 @ TODO: GAS warns for this.
+@ Vary imm.
+str.w r1, [r0], #255
+str.w r1, [r0], #0
+str.w r1, [r0], #-255
+@ Condition codes.
+streq.w r1, [r0], #255
+strle.w r1, [r0], #255
+
+@ CHECK: str   r1, [r0], #4    @ encoding: [0x40,0xf8,0x04,0x1b]
+@ CHECK: str   sp, [r0], #4    @ encoding: [0x40,0xf8,0x04,0xdb]
+@ CHECK: str   r0, [r1], #4    @ encoding: [0x41,0xf8,0x04,0x0b]
+@ CHECK: str   r0, [sp], #4    @ encoding: [0x4d,0xf8,0x04,0x0b]
+@ CHECK: str   r0, [pc], #4    @ encoding: [0x4f,0xf8,0x04,0x0b]
+@ CHECK: str   r1, [r0], #255  @ encoding: [0x40,0xf8,0xff,0x1b]
+@ CHECK: str   r1, [r0], #0    @ encoding: [0x40,0xf8,0x00,0x1b]
+@ CHECK: str   r1, [r0], #-255 @ encoding: [0x40,0xf8,0xff,0x19]
+@ CHECK: it    eq              @ encoding: [0x08,0xbf]
+@ CHECK: streq r1, [r0], #255  @ encoding: [0x40,0xf8,0xff,0x1b]
+@ CHECK: it    le              @ encoding: [0xd8,0xbf]
+@ CHECK: strle r1, [r0], #255  @ encoding: [0x40,0xf8,0xff,0x1b]