[ARM] Accept .w suffixes for some memory instructions

[JiruiWu]

Summary

Some memory instructions in the following sections of Armv7-M ARM allow
the .w mnemonic suffix, even though the preferred disassembly is without
the suffix.

A7.7.46 LDRB (immediate) T3
A7.7.55 LDRH (immediate) T3
A7.7.59 LDRSB (immediate) T2
A7.7.63 LDRSH (immediate) T2
A7.7.163 STRB (immediate) T3
A7.7.170 STRH (immediate) T3

This patch accepts the .w suffixes for theses instructions.
Pseudo-instructions and custom parsing logic are used instead of simple
aliases. More discussions are in these relevant patches:
https://reviews.llvm.org/D68916
https://reviews.llvm.org/D96632

[olista01]

There are a number of closely related instructions which have the same problem, would it make sense to do them at the same time?

• LDRSB
• LDRH
• LDRSH
• STRH

[JiruiWu]

Addressed review comments. Added code for LDRSB, LDRH, LDRSH and STRH.

[olista01]

LGTM

[JiruiWu]

Updated commit messages.

llvm/lib/Target/ARM/ARMInstrThumb2.td

 // F5.1.72 LDR (immediate) T4
 // .w suffixes; Constraints can't be used on t2InstAlias to describe
 // "$Rn =  $Rn_wb" on POST or "$addr.base = $Rn_wb" on PRE.
 def t2LDR_PRE_imm : t2AsmPseudo<"ldr${p}.w $Rt, $addr!",
                          (ins GPR:$Rt, t2addrmode_imm8_pre:$addr, pred:$p)>;
 def t2LDR_POST_imm : t2AsmPseudo<"ldr${p}.w $Rt, $Rn, $imm",
                          (ins GPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$imm, pred:$p)>;
 
+// A7.7.46 LDRB (immediate) T3
+// .w suffixes; Constraints can't be used on t2InstAlias to describe
+// "$Rn =  $Rn_wb" on POST or "$addr.base = $Rn_wb" on PRE.
+def t2LDRB_OFFSET_imm : t2AsmPseudo<"ldrb${p}.w $Rt, $addr",
+                         (ins GPR:$Rt, t2addrmode_negimm8:$addr, pred:$p)>;
+def t2LDRB_PRE_imm : t2AsmPseudo<"ldrb${p}.w $Rt, $addr!",
+                         (ins GPR:$Rt, t2addrmode_imm8_pre:$addr, pred:$p)>;
+def t2LDRB_POST_imm : t2AsmPseudo<"ldrb${p}.w $Rt, $Rn, $imm",
+                         (ins GPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$imm, pred:$p)>;
+
+// A7.7.55 LDRH (immediate) T3
+// .w suffixes; Constraints can't be used on t2InstAlias to describe
+// "$Rn =  $Rn_wb" on POST or "$addr.base = $Rn_wb" on PRE.
+def t2LDRH_OFFSET_imm : t2AsmPseudo<"ldrh${p}.w $Rt, $addr",
+                         (ins GPR:$Rt, t2addrmode_negimm8:$addr, pred:$p)>;
+def t2LDRH_PRE_imm : t2AsmPseudo<"ldrh${p}.w $Rt, $addr!",
+                         (ins GPR:$Rt, t2addrmode_imm8_pre:$addr, pred:$p)>;
+def t2LDRH_POST_imm : t2AsmPseudo<"ldrh${p}.w $Rt, $Rn, $imm",
+                         (ins GPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$imm, pred:$p)>;
+
+// A7.7.59 LDRSB (immediate) T2
+// .w suffixes; Constraints can't be used on t2InstAlias to describe
+// "$Rn =  $Rn_wb" on POST or "$addr.base = $Rn_wb" on PRE.
+def t2LDRSB_OFFSET_imm : t2AsmPseudo<"ldrsb${p}.w $Rt, $addr",
+                         (ins GPR:$Rt, t2addrmode_negimm8:$addr, pred:$p)>;
+def t2LDRSB_PRE_imm : t2AsmPseudo<"ldrsb${p}.w $Rt, $addr!",
+                         (ins GPR:$Rt, t2addrmode_imm8_pre:$addr, pred:$p)>;
+def t2LDRSB_POST_imm : t2AsmPseudo<"ldrsb${p}.w $Rt, $Rn, $imm",
+                         (ins GPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$imm, pred:$p)>;
+
+// A7.7.63 LDRSH (immediate) T2
+// .w suffixes; Constraints can't be used on t2InstAlias to describe
+// "$Rn =  $Rn_wb" on POST or "$addr.base = $Rn_wb" on PRE.
+def t2LDRSH_OFFSET_imm : t2AsmPseudo<"ldrsh${p}.w $Rt, $addr",
+                         (ins GPR:$Rt, t2addrmode_negimm8:$addr, pred:$p)>;
+def t2LDRSH_PRE_imm : t2AsmPseudo<"ldrsh${p}.w $Rt, $addr!",
+                         (ins GPR:$Rt, t2addrmode_imm8_pre:$addr, pred:$p)>;
+def t2LDRSH_POST_imm : t2AsmPseudo<"ldrsh${p}.w $Rt, $Rn, $imm",
+                         (ins GPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$imm, pred:$p)>;
+
 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4
 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii>
   : T2Ii8p<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc,
            "\t$Rt, $addr", []>, Sched<[WriteLd]> {
   bits<4> Rt;
   bits<13> addr;
   let Inst{31-27} = 0b11111;

 // .w suffixes; Constraints can't be used on t2InstAlias to describe
 // "$Rn =  $Rn_wb,@earlyclobber $Rn_wb" on POST or
 // "$addr.base = $Rn_wb,@earlyclobber $Rn_wb" on PRE.
 def t2STR_PRE_imm : t2AsmPseudo<"str${p}.w $Rt, $addr!",
   (ins GPR:$Rt, t2addrmode_imm8_pre:$addr, pred:$p)>;
 def t2STR_POST_imm : t2AsmPseudo<"str${p}.w $Rt, $Rn, $imm",
   (ins GPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$imm, pred:$p)>;
 
+// A7.7.163 STRB (immediate) T3
+// .w suffixes; Constraints can't be used on t2InstAlias to describe
+// "$Rn =  $Rn_wb" on POST or "$addr.base = $Rn_wb" on PRE.
+def t2STRB_OFFSET_imm : t2AsmPseudo<"strb${p}.w $Rt, $addr",
+  (ins GPR:$Rt, t2addrmode_negimm8:$addr, pred:$p)>;
+def t2STRB_PRE_imm : t2AsmPseudo<"strb${p}.w $Rt, $addr!",
+  (ins GPR:$Rt, t2addrmode_imm8_pre:$addr, pred:$p)>;
+def t2STRB_POST_imm : t2AsmPseudo<"strb${p}.w $Rt, $Rn, $imm",
+  (ins GPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$imm, pred:$p)>;
+
+// A7.7.170 STRH (immediate) T3
+// .w suffixes; Constraints can't be used on t2InstAlias to describe
+// "$Rn =  $Rn_wb" on POST or "$addr.base = $Rn_wb" on PRE.
+def t2STRH_OFFSET_imm : t2AsmPseudo<"strh${p}.w $Rt, $addr",
+  (ins GPR:$Rt, t2addrmode_negimm8:$addr, pred:$p)>;
+def t2STRH_PRE_imm : t2AsmPseudo<"strh${p}.w $Rt, $addr!",
+  (ins GPR:$Rt, t2addrmode_imm8_pre:$addr, pred:$p)>;
+def t2STRH_POST_imm : t2AsmPseudo<"strh${p}.w $Rt, $Rn, $imm",
+  (ins GPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$imm, pred:$p)>;
+
 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
 // only.
 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4
 class T2IstT<bits<2> type, string opc, InstrItinClass ii>
   : T2Ii8p<(outs), (ins rGPR:$Rt, t2addrmode_posimm8:$addr), ii, opc,
            "\t$Rt, $addr", []>, Sched<[WriteST]> {
   let Inst{31-27} = 0b11111;
   let Inst{26-25} = 0b00;

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

if (Inst.getOpcode() == ARM::t2STR_PRE_imm ||
         Inst.getOpcode() == ARM::t2STR_POST_imm) {
       if (Inst.getOperand(0).getReg() == ARM::PC) {
         return Error(Operands[3]->getStartLoc(),
                      "operand must be a register in range [r0, r14]");
       }
     }
     return false;
   }
+
+  case ARM::t2LDRB_OFFSET_imm:
+  case ARM::t2LDRB_PRE_imm:
+  case ARM::t2LDRB_POST_imm:
+  case ARM::t2STRB_OFFSET_imm:
+  case ARM::t2STRB_PRE_imm:
+  case ARM::t2STRB_POST_imm: {
+    if (Inst.getOpcode() == ARM::t2LDRB_POST_imm ||
+        Inst.getOpcode() == ARM::t2STRB_POST_imm ||
+        Inst.getOpcode() == ARM::t2LDRB_PRE_imm ||
+        Inst.getOpcode() == ARM::t2STRB_PRE_imm) {
+      int Imm = Inst.getOperand(2).getImm();
+      if (Imm > 255 || Imm < -255)
+        return Error(Operands[5]->getStartLoc(),
+                     "operand must be in range [-255, 255]");
+    } else if (Inst.getOpcode() == ARM::t2LDRB_OFFSET_imm ||
+               Inst.getOpcode() == ARM::t2STRB_OFFSET_imm) {
+      int Imm = Inst.getOperand(2).getImm();
+      if (Imm > 0 || Imm < -255)
+        return Error(Operands[5]->getStartLoc(),
+                     "operand must be in range [0, 255] with a negative sign");
+    }
+    if (Inst.getOperand(0).getReg() == ARM::PC) {
+      return Error(Operands[3]->getStartLoc(),
+                   "if operand is PC, should call the LDRB (literal)");
+    }
+    return false;
+  }
+
+  case ARM::t2LDRH_OFFSET_imm:
+  case ARM::t2LDRH_PRE_imm:
+  case ARM::t2LDRH_POST_imm:
+  case ARM::t2STRH_OFFSET_imm:
+  case ARM::t2STRH_PRE_imm:
+  case ARM::t2STRH_POST_imm: {
+    if (Inst.getOpcode() == ARM::t2LDRH_POST_imm ||
+        Inst.getOpcode() == ARM::t2STRH_POST_imm ||
+        Inst.getOpcode() == ARM::t2LDRH_PRE_imm ||
+        Inst.getOpcode() == ARM::t2STRH_PRE_imm) {
+      int Imm = Inst.getOperand(2).getImm();
+      if (Imm > 255 || Imm < -255)
+        return Error(Operands[5]->getStartLoc(),
+                     "operand must be in range [-255, 255]");
+    } else if (Inst.getOpcode() == ARM::t2LDRH_OFFSET_imm ||
+               Inst.getOpcode() == ARM::t2STRH_OFFSET_imm) {
+      int Imm = Inst.getOperand(2).getImm();
+      if (Imm > 0 || Imm < -255)
+        return Error(Operands[5]->getStartLoc(),
+                     "operand must be in range [0, 255] with a negative sign");
+    }
+    if (Inst.getOperand(0).getReg() == ARM::PC) {
+      return Error(Operands[3]->getStartLoc(),
+                   "if operand is PC, should call the LDRH (literal)");
+    }
+    return false;
+  }
+
+  case ARM::t2LDRSB_OFFSET_imm:
+  case ARM::t2LDRSB_PRE_imm:
+  case ARM::t2LDRSB_POST_imm: {
+    if (Inst.getOpcode() == ARM::t2LDRSB_POST_imm ||
+        Inst.getOpcode() == ARM::t2LDRSB_PRE_imm) {
+      int Imm = Inst.getOperand(2).getImm();
+      if (Imm > 255 || Imm < -255)
+        return Error(Operands[5]->getStartLoc(),
+                     "operand must be in range [-255, 255]");
+    } else if (Inst.getOpcode() == ARM::t2LDRSB_OFFSET_imm) {
+      int Imm = Inst.getOperand(2).getImm();
+      if (Imm > 0 || Imm < -255)
+        return Error(Operands[5]->getStartLoc(),
+                     "operand must be in range [0, 255] with a negative sign");
+    }
+    if (Inst.getOperand(0).getReg() == ARM::PC) {
+      return Error(Operands[3]->getStartLoc(),
+                   "if operand is PC, should call the LDRH (literal)");
+    }
+    return false;
+  }
+
+  case ARM::t2LDRSH_OFFSET_imm:
+  case ARM::t2LDRSH_PRE_imm:
+  case ARM::t2LDRSH_POST_imm: {
+    if (Inst.getOpcode() == ARM::t2LDRSH_POST_imm ||
+        Inst.getOpcode() == ARM::t2LDRSH_PRE_imm) {
+      int Imm = Inst.getOperand(2).getImm();
+      if (Imm > 255 || Imm < -255)
+        return Error(Operands[5]->getStartLoc(),
+                     "operand must be in range [-255, 255]");
+    } else if (Inst.getOpcode() == ARM::t2LDRSH_OFFSET_imm) {
+      int Imm = Inst.getOperand(2).getImm();
+      if (Imm > 0 || Imm < -255)
+        return Error(Operands[5]->getStartLoc(),
+                     "operand must be in range [0, 255] with a negative sign");
+    }
+    if (Inst.getOperand(0).getReg() == ARM::PC) {
+      return Error(Operands[3]->getStartLoc(),
+                   "if operand is PC, should call the LDRH (literal)");
+    }
+    return false;
+  }
+
   case ARM::LDR_PRE_IMM:
   case ARM::LDR_PRE_REG:
   case ARM::t2LDR_PRE:
   case ARM::LDR_POST_IMM:
   case ARM::LDR_POST_REG:
   case ARM::t2LDR_POST:
   case ARM::LDRH_PRE:
   case ARM::t2LDRH_PRE:
case ARM::t2STR_POST_imm: {
     TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb
     TmpInst.addOperand(Inst.getOperand(0)); // Rt
     TmpInst.addOperand(Inst.getOperand(1)); // Rn
     TmpInst.addOperand(Inst.getOperand(2)); // imm
     TmpInst.addOperand(Inst.getOperand(3)); // CondCode
     Inst = TmpInst;
     return true;
   }
+  // Aliases for imm syntax of LDRB instructions.
+  case ARM::t2LDRB_OFFSET_imm: {
+    MCInst TmpInst;
+    TmpInst.setOpcode(ARM::t2LDRBi8);
+    TmpInst.addOperand(Inst.getOperand(0)); // Rt
+    TmpInst.addOperand(Inst.getOperand(1)); // Rn
+    TmpInst.addOperand(Inst.getOperand(2)); // imm
+    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
+    Inst = TmpInst;
+    return true;
+  }
+  case ARM::t2LDRB_PRE_imm:
+  case ARM::t2LDRB_POST_imm: {
+    MCInst TmpInst;
+    TmpInst.setOpcode(Inst.getOpcode() == ARM::t2LDRB_PRE_imm
+                          ? ARM::t2LDRB_PRE
+                          : ARM::t2LDRB_POST);
+    TmpInst.addOperand(Inst.getOperand(0)); // Rt
+    TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb
+    TmpInst.addOperand(Inst.getOperand(1)); // Rn
+    TmpInst.addOperand(Inst.getOperand(2)); // imm
+    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
+    Inst = TmpInst;
+    return true;
+  }
+  // Aliases for imm syntax of STRB instructions.
+  case ARM::t2STRB_OFFSET_imm: {
+    MCInst TmpInst;
+    TmpInst.setOpcode(ARM::t2STRBi8);
+    TmpInst.addOperand(Inst.getOperand(0)); // Rt
+    TmpInst.addOperand(Inst.getOperand(1)); // Rn
+    TmpInst.addOperand(Inst.getOperand(2)); // imm
+    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
+    Inst = TmpInst;
+    return true;
+  }
+  case ARM::t2STRB_PRE_imm:
+  case ARM::t2STRB_POST_imm: {
+    MCInst TmpInst;
+    TmpInst.setOpcode(Inst.getOpcode() == ARM::t2STRB_PRE_imm
+                          ? ARM::t2STRB_PRE
+                          : ARM::t2STRB_POST);
+    TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb
+    TmpInst.addOperand(Inst.getOperand(0)); // Rt
+    TmpInst.addOperand(Inst.getOperand(1)); // Rn
+    TmpInst.addOperand(Inst.getOperand(2)); // imm
+    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
+    Inst = TmpInst;
+    return true;
+  }
+  // Aliases for imm syntax of LDRH instructions.
+  case ARM::t2LDRH_OFFSET_imm: {
+    MCInst TmpInst;
+    TmpInst.setOpcode(ARM::t2LDRHi8);
+    TmpInst.addOperand(Inst.getOperand(0)); // Rt
+    TmpInst.addOperand(Inst.getOperand(1)); // Rn
+    TmpInst.addOperand(Inst.getOperand(2)); // imm
+    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
+    Inst = TmpInst;
+    return true;
+  }
+  case ARM::t2LDRH_PRE_imm:
+  case ARM::t2LDRH_POST_imm: {
+    MCInst TmpInst;
+    TmpInst.setOpcode(Inst.getOpcode() == ARM::t2LDRH_PRE_imm
+                          ? ARM::t2LDRH_PRE
+                          : ARM::t2LDRH_POST);
+    TmpInst.addOperand(Inst.getOperand(0)); // Rt
+    TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb
+    TmpInst.addOperand(Inst.getOperand(1)); // Rn
+    TmpInst.addOperand(Inst.getOperand(2)); // imm
+    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
+    Inst = TmpInst;
+    return true;
+  }
+  // Aliases for imm syntax of STRH instructions.
+  case ARM::t2STRH_OFFSET_imm: {
+    MCInst TmpInst;
+    TmpInst.setOpcode(ARM::t2STRHi8);
+    TmpInst.addOperand(Inst.getOperand(0)); // Rt
+    TmpInst.addOperand(Inst.getOperand(1)); // Rn
+    TmpInst.addOperand(Inst.getOperand(2)); // imm
+    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
+    Inst = TmpInst;
+    return true;
+  }
+  case ARM::t2STRH_PRE_imm:
+  case ARM::t2STRH_POST_imm: {
+    MCInst TmpInst;
+    TmpInst.setOpcode(Inst.getOpcode() == ARM::t2STRH_PRE_imm
+                          ? ARM::t2STRH_PRE
+                          : ARM::t2STRH_POST);
+    TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb
+    TmpInst.addOperand(Inst.getOperand(0)); // Rt
+    TmpInst.addOperand(Inst.getOperand(1)); // Rn
+    TmpInst.addOperand(Inst.getOperand(2)); // imm
+    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
+    Inst = TmpInst;
+    return true;
+  }
+  // Aliases for imm syntax of LDRSB instructions.
+  case ARM::t2LDRSB_OFFSET_imm: {
+    MCInst TmpInst;
+    TmpInst.setOpcode(ARM::t2LDRSBi8);
+    TmpInst.addOperand(Inst.getOperand(0)); // Rt
+    TmpInst.addOperand(Inst.getOperand(1)); // Rn
+    TmpInst.addOperand(Inst.getOperand(2)); // imm
+    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
+    Inst = TmpInst;
+    return true;
+  }
+  case ARM::t2LDRSB_PRE_imm:
+  case ARM::t2LDRSB_POST_imm: {
+    MCInst TmpInst;
+    TmpInst.setOpcode(Inst.getOpcode() == ARM::t2LDRSB_PRE_imm
+                          ? ARM::t2LDRSB_PRE
+                          : ARM::t2LDRSB_POST);
+    TmpInst.addOperand(Inst.getOperand(0)); // Rt
+    TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb
+    TmpInst.addOperand(Inst.getOperand(1)); // Rn
+    TmpInst.addOperand(Inst.getOperand(2)); // imm
+    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
+    Inst = TmpInst;
+    return true;
+  }
+  // Aliases for imm syntax of LDRSH instructions.
+  case ARM::t2LDRSH_OFFSET_imm: {
+    MCInst TmpInst;
+    TmpInst.setOpcode(ARM::t2LDRSHi8);
+    TmpInst.addOperand(Inst.getOperand(0)); // Rt
+    TmpInst.addOperand(Inst.getOperand(1)); // Rn
+    TmpInst.addOperand(Inst.getOperand(2)); // imm
+    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
+    Inst = TmpInst;
+    return true;
+  }
+  case ARM::t2LDRSH_PRE_imm:
+  case ARM::t2LDRSH_POST_imm: {
+    MCInst TmpInst;
+    TmpInst.setOpcode(Inst.getOpcode() == ARM::t2LDRSH_PRE_imm
+                          ? ARM::t2LDRSH_PRE
+                          : ARM::t2LDRSH_POST);
+    TmpInst.addOperand(Inst.getOperand(0)); // Rt
+    TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb
+    TmpInst.addOperand(Inst.getOperand(1)); // Rn
+    TmpInst.addOperand(Inst.getOperand(2)); // imm
+    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
+    Inst = TmpInst;
+    return true;
+  }
   // Aliases for alternate PC+imm syntax of LDR instructions.
   case ARM::t2LDRpcrel:
     // Select the narrow version if the immediate will fit.
     if (Inst.getOperand(1).getImm() > 0 &&
         Inst.getOperand(1).getImm() <= 0xff &&
         !HasWideQualifier)
       Inst.setOpcode(ARM::tLDRpci);
     else

llvm/test/MC/ARM/basic-thumb2-instructions.s

@------------------------------------------------------------------------------
         ldrb r5, [r6, #257]
         ldrb.w lr, [r7, #257]
         ldrb r5, [r8, #255]!
         ldrb r2, [r5, #4]!
         ldrb r1, [r4, #-4]!
         ldrb lr, [r3], #255
         ldrb r9, [r2], #4
         ldrb r3, [sp], #-4
+        ldrb.w r5, [r5, #-4]
+        ldrb.w r5, [r6, #32]
+        ldrb.w r5, [r8, #255]!
+        ldrb.w r9, [r2], #4
 
 @ CHECK: ldrb  r5, [r5, #-4]           @ encoding: [0x15,0xf8,0x04,0x5c]
 @ CHECK: ldrb.w  r5, [r6, #32]           @ encoding: [0x96,0xf8,0x20,0x50]
 @ CHECK: ldrb.w  r5, [r6, #33]           @ encoding: [0x96,0xf8,0x21,0x50]
 @ CHECK: ldrb.w  r5, [r6, #257]          @ encoding: [0x96,0xf8,0x01,0x51]
 @ CHECK: ldrb.w  lr, [r7, #257]          @ encoding: [0x97,0xf8,0x01,0xe1]
 @ CHECK: ldrb  r5, [r8, #255]!         @ encoding: [0x18,0xf8,0xff,0x5f]
 @ CHECK: ldrb  r2, [r5, #4]!           @ encoding: [0x15,0xf8,0x04,0x2f]
 @ CHECK: ldrb  r1, [r4, #-4]!          @ encoding: [0x14,0xf8,0x04,0x1d]
 @ CHECK: ldrb  lr, [r3], #255          @ encoding: [0x13,0xf8,0xff,0xeb]
 @ CHECK: ldrb  r9, [r2], #4            @ encoding: [0x12,0xf8,0x04,0x9b]
 @ CHECK: ldrb  r3, [sp], #-4           @ encoding: [0x1d,0xf8,0x04,0x39]
+@ CHECK: ldrb   r5, [r5, #-4]           @ encoding: [0x15,0xf8,0x04,0x5c]
+@ CHECK: ldrb.w  r5, [r6, #32]           @ encoding: [0x96,0xf8,0x20,0x50]
+@ CHECK: ldrb  r5, [r8, #255]!         @ encoding: [0x18,0xf8,0xff,0x5f]
+@ CHECK: ldrb  r9, [r2], #4            @ encoding: [0x12,0xf8,0x04,0x9b]
 
 
 @------------------------------------------------------------------------------
 @ LDRB(register)
 @------------------------------------------------------------------------------
         ldrb r1, [r8, r1]
         ldrb.w r4, [r5, r2]
         ldrb r6, [r0, r2, lsl #3]
@------------------------------------------------------------------------------
         ldrh r5, [r6, #257]
         ldrh.w lr, [r7, #257]
         ldrh r5, [r8, #255]!
         ldrh r2, [r5, #4]!
         ldrh r1, [r4, #-4]!
         ldrh lr, [r3], #255
         ldrh r9, [r2], #4
         ldrh r3, [sp], #-4
+        ldrh.w r5, [r5, #-4]
+        ldrh.w r5, [r6, #32]
+        ldrh.w r5, [r8, #255]!
+        ldrh.w r9, [r2], #4
 
 @ CHECK: ldrh  r5, [r5, #-4]           @ encoding: [0x35,0xf8,0x04,0x5c]
 @ CHECK: ldrh  r5, [r6, #32]           @ encoding: [0x35,0x8c]
 @ CHECK: ldrh.w  r5, [r6, #33]           @ encoding: [0xb6,0xf8,0x21,0x50]
 @ CHECK: ldrh.w  r5, [r6, #257]          @ encoding: [0xb6,0xf8,0x01,0x51]
 @ CHECK: ldrh.w  lr, [r7, #257]          @ encoding: [0xb7,0xf8,0x01,0xe1]
 @ CHECK: ldrh  r5, [r8, #255]!         @ encoding: [0x38,0xf8,0xff,0x5f]
 @ CHECK: ldrh  r2, [r5, #4]!           @ encoding: [0x35,0xf8,0x04,0x2f]
 @ CHECK: ldrh  r1, [r4, #-4]!          @ encoding: [0x34,0xf8,0x04,0x1d]
 @ CHECK: ldrh  lr, [r3], #255          @ encoding: [0x33,0xf8,0xff,0xeb]
 @ CHECK: ldrh  r9, [r2], #4            @ encoding: [0x32,0xf8,0x04,0x9b]
 @ CHECK: ldrh  r3, [sp], #-4           @ encoding: [0x3d,0xf8,0x04,0x39]
+@ CHECK: ldrh  r5, [r5, #-4]           @ encoding: [0x35,0xf8,0x04,0x5c]
+@ CHECK: ldrh.w  r5, [r6, #32]           @ encoding: [0xb6,0xf8,0x20,0x50]
+@ CHECK: ldrh  r5, [r8, #255]!         @ encoding: [0x38,0xf8,0xff,0x5f]
+@ CHECK: ldrh  r9, [r2], #4            @ encoding: [0x32,0xf8,0x04,0x9b]
 
 
 @------------------------------------------------------------------------------
 @ LDRH(register)
 @------------------------------------------------------------------------------
         ldrh r1, [r8, r1]
         ldrh.w r4, [r5, r2]
         ldrh r6, [r0, r2, lsl #3]

 @------------------------------------------------------------------------------
 @ LDRSB(immediate)
 @------------------------------------------------------------------------------
         ldrsb r5, [r5, #-4]
         ldrsb r5, [r6, #32]
         ldrsb r5, [r6, #33]
         ldrsb r5, [r6, #257]
         ldrsb.w lr, [r7, #257]
+        ldrsb r5, [r8, #255]!
+        ldrsb r2, [r5, #4]!
+        ldrsb r1, [r4, #-4]!
+        ldrsb lr, [r3], #255
+        ldrsb r9, [r2], #4
+        ldrsb r3, [sp], #-4
+        ldrsb.w r5, [r5, #-4]
+        ldrsb.w r5, [r6, #32]
+        ldrsb.w r5, [r8, #255]!
+        ldrsb.w r9, [r2], #4
 
 @ CHECK: ldrsb  r5, [r5, #-4]            @ encoding: [0x15,0xf9,0x04,0x5c]
 @ CHECK: ldrsb.w r5, [r6, #32]           @ encoding: [0x96,0xf9,0x20,0x50]
 @ CHECK: ldrsb.w r5, [r6, #33]           @ encoding: [0x96,0xf9,0x21,0x50]
 @ CHECK: ldrsb.w r5, [r6, #257]          @ encoding: [0x96,0xf9,0x01,0x51]
 @ CHECK: ldrsb.w lr, [r7, #257]          @ encoding: [0x97,0xf9,0x01,0xe1]
+@ CHECK: ldrsb  r5, [r8, #255]!          @ encoding: [0x18,0xf9,0xff,0x5f]
+@ CHECK: ldrsb  r2, [r5, #4]!            @ encoding: [0x15,0xf9,0x04,0x2f]
+@ CHECK: ldrsb  r1, [r4, #-4]!           @ encoding: [0x14,0xf9,0x04,0x1d]
+@ CHECK: ldrsb  lr, [r3], #255           @ encoding: [0x13,0xf9,0xff,0xeb]
+@ CHECK: ldrsb  r9, [r2], #4             @ encoding: [0x12,0xf9,0x04,0x9b]
+@ CHECK: ldrsb  r3, [sp], #-4            @ encoding: [0x1d,0xf9,0x04,0x39]
+@ CHECK: ldrsb  r5, [r5, #-4]            @ encoding: [0x15,0xf9,0x04,0x5c]
+@ CHECK: ldrsb.w r5, [r6, #32]           @ encoding: [0x96,0xf9,0x20,0x50]
+@ CHECK: ldrsb  r5, [r8, #255]!          @ encoding: [0x18,0xf9,0xff,0x5f]
+@ CHECK: ldrsb  r9, [r2], #4             @ encoding: [0x12,0xf9,0x04,0x9b]
 
 
 @------------------------------------------------------------------------------
 @ LDRSB(register)
 @------------------------------------------------------------------------------
         ldrsb r1, [r8, r1]
         ldrsb.w r4, [r5, r2]
         ldrsb r6, [r0, r2, lsl #3]

 @------------------------------------------------------------------------------
 @ LDRSH(immediate)
 @------------------------------------------------------------------------------
         ldrsh r5, [r5, #-4]
         ldrsh r5, [r6, #32]
         ldrsh r5, [r6, #33]
         ldrsh r5, [r6, #257]
         ldrsh.w lr, [r7, #257]
+        ldrsh r5, [r8, #255]!
+        ldrsh r2, [r5, #4]!
+        ldrsh r1, [r4, #-4]!
+        ldrsh lr, [r3], #255
+        ldrsh r9, [r2], #4
+        ldrsh r3, [sp], #-4
+        ldrsh.w r5, [r5, #-4]
+        ldrsh.w r5, [r6, #32]
+        ldrsh.w r5, [r8, #255]!
+        ldrsh.w r9, [r2], #4
 
 @ CHECK: ldrsh  r5, [r5, #-4]           @ encoding: [0x35,0xf9,0x04,0x5c]
 @ CHECK: ldrsh.w r5, [r6, #32]          @ encoding: [0xb6,0xf9,0x20,0x50]
 @ CHECK: ldrsh.w r5, [r6, #33]          @ encoding: [0xb6,0xf9,0x21,0x50]
 @ CHECK: ldrsh.w r5, [r6, #257]         @ encoding: [0xb6,0xf9,0x01,0x51]
 @ CHECK: ldrsh.w lr, [r7, #257]         @ encoding: [0xb7,0xf9,0x01,0xe1]
+@ CHECK: ldrsh  r5, [r8, #255]!         @ encoding: [0x38,0xf9,0xff,0x5f]
+@ CHECK: ldrsh  r2, [r5, #4]!           @ encoding: [0x35,0xf9,0x04,0x2f]
+@ CHECK: ldrsh  r1, [r4, #-4]!          @ encoding: [0x34,0xf9,0x04,0x1d]
+@ CHECK: ldrsh  lr, [r3], #255          @ encoding: [0x33,0xf9,0xff,0xeb]
+@ CHECK: ldrsh  r9, [r2], #4            @ encoding: [0x32,0xf9,0x04,0x9b]
+@ CHECK: ldrsh  r3, [sp], #-4           @ encoding: [0x3d,0xf9,0x04,0x39]
+@ CHECK: ldrsh  r5, [r5, #-4]           @ encoding: [0x35,0xf9,0x04,0x5c]
+@ CHECK: ldrsh.w r5, [r6, #32]          @ encoding: [0xb6,0xf9,0x20,0x50]
+@ CHECK: ldrsh  r5, [r8, #255]!         @ encoding: [0x38,0xf9,0xff,0x5f]
+@ CHECK: ldrsh  r9, [r2], #4            @ encoding: [0x32,0xf9,0x04,0x9b]
 
 
 @------------------------------------------------------------------------------
 @ LDRSH(register)
 @------------------------------------------------------------------------------
         ldrsh r1, [r8, r1]
         ldrsh.w r4, [r5, r2]
         ldrsh r6, [r0, r2, lsl #3]
@------------------------------------------------------------------------------
         strb r5, [r8, #255]!
         strb r2, [r5, #4]!
         strb r1, [r4, #-4]!
         strb lr, [r3], #255
         strb r9, [r2], #4
         strb r3, [sp], #-4
         strb r4, [r8, #-0]!
         strb r1, [r0], #-0
+        strb.w r5, [r5, #-4]
+        strb.w r5, [r6, #32]
+        strb.w r5, [r8, #255]!
+        strb.w r9, [r2], #4
 
 @ CHECK: strb  r5, [r5, #-4]           @ encoding: [0x05,0xf8,0x04,0x5c]
 @ CHECK: strb.w  r5, [r6, #32]           @ encoding: [0x86,0xf8,0x20,0x50]
 @ CHECK: strb.w  r5, [r6, #33]           @ encoding: [0x86,0xf8,0x21,0x50]
 @ CHECK: strb.w  r5, [r6, #257]          @ encoding: [0x86,0xf8,0x01,0x51]
 @ CHECK: strb.w  lr, [r7, #257]          @ encoding: [0x87,0xf8,0x01,0xe1]
 @ CHECK: strb  r5, [r8, #255]!         @ encoding: [0x08,0xf8,0xff,0x5f]
 @ CHECK: strb  r2, [r5, #4]!           @ encoding: [0x05,0xf8,0x04,0x2f]
 @ CHECK: strb  r1, [r4, #-4]!          @ encoding: [0x04,0xf8,0x04,0x1d]
 @ CHECK: strb  lr, [r3], #255          @ encoding: [0x03,0xf8,0xff,0xeb]
 @ CHECK: strb  r9, [r2], #4            @ encoding: [0x02,0xf8,0x04,0x9b]
 @ CHECK: strb  r3, [sp], #-4           @ encoding: [0x0d,0xf8,0x04,0x39]
 @ CHECK: strb  r4, [r8, #-0]!          @ encoding: [0x08,0xf8,0x00,0x4d]
 @ CHECK: strb  r1, [r0], #-0           @ encoding: [0x00,0xf8,0x00,0x19]
+@ CHECK: strb  r5, [r5, #-4]           @ encoding: [0x05,0xf8,0x04,0x5c]
+@ CHECK: strb.w  r5, [r6, #32]           @ encoding: [0x86,0xf8,0x20,0x50]
+@ CHECK: strb  r5, [r8, #255]!         @ encoding: [0x08,0xf8,0xff,0x5f]
+@ CHECK: strb  r9, [r2], #4            @ encoding: [0x02,0xf8,0x04,0x9b]
 
 
 @------------------------------------------------------------------------------
 @ STRB(register)
 @------------------------------------------------------------------------------
         strb r1, [r8, r1]
         strb.w r4, [r5, r2]
         strb r6, [r0, r2, lsl #3]
@------------------------------------------------------------------------------
         strh r5, [r6, #257]
         strh.w lr, [r7, #257]
         strh r5, [r8, #255]!
         strh r2, [r5, #4]!
         strh r1, [r4, #-4]!
         strh lr, [r3], #255
         strh r9, [r2], #4
         strh r3, [sp], #-4
+        strh.w r5, [r5, #-4]
+        strh.w r5, [r6, #32]
+        strh.w r5, [r8, #255]!
+        strh.w r9, [r2], #4
 
 @ CHECK: strh  r5, [r5, #-4]           @ encoding: [0x25,0xf8,0x04,0x5c]
 @ CHECK: strh  r5, [r6, #32]           @ encoding: [0x35,0x84]
 @ CHECK: strh.w  r5, [r6, #33]           @ encoding: [0xa6,0xf8,0x21,0x50]
 @ CHECK: strh.w  r5, [r6, #257]          @ encoding: [0xa6,0xf8,0x01,0x51]
 @ CHECK: strh.w  lr, [r7, #257]          @ encoding: [0xa7,0xf8,0x01,0xe1]
 @ CHECK: strh  r5, [r8, #255]!         @ encoding: [0x28,0xf8,0xff,0x5f]
 @ CHECK: strh  r2, [r5, #4]!           @ encoding: [0x25,0xf8,0x04,0x2f]
 @ CHECK: strh  r1, [r4, #-4]!          @ encoding: [0x24,0xf8,0x04,0x1d]
 @ CHECK: strh  lr, [r3], #255          @ encoding: [0x23,0xf8,0xff,0xeb]
 @ CHECK: strh  r9, [r2], #4            @ encoding: [0x22,0xf8,0x04,0x9b]
 @ CHECK: strh  r3, [sp], #-4           @ encoding: [0x2d,0xf8,0x04,0x39]
+@ CHECK: strh  r5, [r5, #-4]           @ encoding: [0x25,0xf8,0x04,0x5c]
+@ CHECK: strh.w  r5, [r6, #32]           @ encoding: [0xa6,0xf8,0x20,0x50]
+@ CHECK: strh  r5, [r8, #255]!         @ encoding: [0x28,0xf8,0xff,0x5f]
+@ CHECK: strh  r9, [r2], #4            @ encoding: [0x22,0xf8,0x04,0x9b]
 
 
 @------------------------------------------------------------------------------
 @ STRH(register)
 @------------------------------------------------------------------------------
         strh r1, [r8, r1]
         strh.w r4, [r5, r2]
         strh r6, [r0, r2, lsl #3]