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- D134529: [C++20][Clang] P2468R2 The Equality Operator You Are Looking For
D132450: StructurizeCFG: Set Undef for non-predecessors in setPhiValues()
rG3cd5696a3309: Revert "Reland "Reland "[X86][RFC] Enable `_Float16` type support on X86…
rG404843a94dbf: [MC][ARM] add .w suffixes for BL (T1) and DBG
rG1e204ac78952: [THUMB2] add .w suffixes for ldr/str (immediate) T4
D97236: [MC][ARM] add .w suffixes for BL (T1) and DBG
D96632: [THUMB2] add .w suffixes for ldr/str (immediate) T4
D86519: [SystemZ] New pass for domain reassignment from integer to vector.
D87258: [WebAssembly, LowerTypeTests] Fix control-flow integrity support
D86360: Add new hidden option -print-changed which only reports changes to IR
D82881: [DEBUGINFO]Fix debug info for packed bitfields.
D71992: [ARM] Unrestrict Armv8 IT blocks
rZORG890865c829e0: [docs] Fix troff macro (.F1 -> .Fl) in ld.lld.1
rZORGb2f5c1cdbb0c: Add a new helper function, AddOpt(F1, F1, Opt), as part of PR13574. No…
rZORG38c44ea6b03f: make jump threading recursively simplify expressions instead of doing it just…
rZORG04e3d20a5198: Increase the macro id cache to look up several recent entries, not just the…
rZORG1fae1cd3e140: Fix for PR1540: Specify F0, F1 are sub-registers of D0, etc.
rZORGab559f6e3cbf: Addition to the previous commit for getCalleeSavedRegClasses:
rZORGfbfc451ba906: The ELF ABI specifies F1-F8 registers as argument registers for double, not F1…
rZORG4480dcdceaf2: add F0 and F1 to the FP register class
rZORG4990335eb8dd: Print physreg register nodes with target names (e.g. F1) instead of numbers
rZORG421c3c1ec469: * Do not emit IMPLICIT_DEF pseudo-instructions * Convert register numbers from…
rZORG0e3a7ca53e63: SparcV8 has different types of instructions, but F1 is only used for CALL.
D64376: [MBP] Avoid tail duplication if it can't bring benefit
rG890865c829e0: [docs] Fix troff macro (.F1 -> .Fl) in ld.lld.1
rGb372259aceee: [docs] Fix troff macro (.F1 -> .Fl) in ld.lld.1
rLLD361345: [docs] Fix troff macro (.F1 -> .Fl) in ld.lld.1
rL361345: [docs] Fix troff macro (.F1 -> .Fl) in ld.lld.1
D62079: [MBP] Rotate should bring more fallthrough
D61786: [ASTImporter] Separate unittest files
rG5914ece6aace: AMDGPU: Select s_buffer_load_dword with a non-constant SGPR offset
rG21da340f7a16: [AArch64] Cortex-A57 FDIV/FSQRT scheduling fix (W-unit)
rGac1dba0fdf9c: [SystemZ] Fix FPR dwarf numbering
rG2b391ab7086b: Implement a rudimentary form of generic lambdas.
rGfd5277c0635f: Implement a rudimentary form of generic lambdas.
rGb5d9bd6f59a2: Fix double renaming bug in stack coloring pass
rG51f6fb9a189f: Delete the functions F1 and F2 to appease the valgrind bot.
rGb2f5c1cdbb0c: Add a new helper function, AddOpt(F1, F1, Opt), as part of PR13574. No…
rG38c44ea6b03f: make jump threading recursively simplify expressions instead of doing it just…
rG04e3d20a5198: Increase the macro id cache to look up several recent entries, not just the…
rG1fae1cd3e140: Fix for PR1540: Specify F0, F1 are sub-registers of D0, etc.
rGab559f6e3cbf: Addition to the previous commit for getCalleeSavedRegClasses:
rGfbfc451ba906: The ELF ABI specifies F1-F8 registers as argument registers for double, not F1…
rG4480dcdceaf2: add F0 and F1 to the FP register class
rG4990335eb8dd: Print physreg register nodes with target names (e.g. F1) instead of numbers
rG421c3c1ec469: * Do not emit IMPLICIT_DEF pseudo-instructions * Convert register numbers from…
rG0e3a7ca53e63: SparcV8 has different types of instructions, but F1 is only used for CALL.
D56393: [DebugInfo] Don't emit DW_AT_enum_class unless it's actually an 'enum class'.
D48240: Try again to implement a FIFO task queue
D45757: [XRay][profiler] Part 2: XRay Function Call Trie
rC191453: Implement a rudimentary form of generic lambdas.
rC188977: Implement a rudimentary form of generic lambdas.
rC40715: Increase the macro id cache to look up several recent entries, not just the…
rL317038: AMDGPU: Select s_buffer_load_dword with a non-constant SGPR offset
D38914: AMDGPU: Select s_buffer_load_dword with a non-constant SGPR offset
D36527: Implemented P0428R2 - Familiar template syntax for generic lambdas
D36768: [test-suite] Add -i option to fpcmp to ignore whitespace changes.
rL290426: [AArch64] Cortex-A57 FDIV/FSQRT scheduling fix (W-unit)
D27521: AArch64 Cortex-A57 FDIV/FSQRT scheduling fix (W-unit)
D26648: Clarify semantic of reserved registers.
D21663: [MBP] Enhance cost based branch prob threshold computation to handle general control flows
D8358: Fix R0 use in PowerPC VSX store for FastIsel
D7169: Jump thread llvm.expect