[AArch64] Specify Tail Duplication Size Override

[dmgreen]

This sounds OK to me, but 6 is quite a big jump up from 2. Is is possible to make the normal threshold 2 or 3, and the aggressive threshold 6?

[dmgreen]

Oh. It looks like there is already an aggressive limit. TailDuplicator is either used by itself or in MachineBlockPlacement. MachineBlockPlacement already sets the limit to 4 when optimizing aggressively. Would it work for your usecase to alter the value there based on the target instead?

[NickGuy]

Abandoning this and combining it with D95631.

llvm/lib/Target/AArch64/AArch64InstrInfo.h

public:
   static bool isSEHInstruction(const MachineInstr &MI);
 
   Optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
                                       Register Reg) const override;
 
   Optional<ParamLoadedValue> describeLoadedValue(const MachineInstr &MI,
                                                  Register Reg) const override;
 
+  unsigned int getTailDuplicateSizeOverride() const override;
+
   static void decomposeStackOffsetForFrameOffsets(const StackOffset &Offset,
                                                   int64_t &NumBytes,
                                                   int64_t &NumPredicateVectors,
                                                   int64_t &NumDataVectors);
   static void decomposeStackOffsetForDwarfOffsets(const StackOffset &Offset,
                                                   int64_t &ByteSized,
                                                   int64_t &VGSized);
 #define GET_INSTRINFO_HELPER_DECLS

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

 bool AArch64InstrInfo::isPTestLikeOpcode(unsigned Opc) const {
   return get(Opc).TSFlags & AArch64::InstrFlagIsPTestLike;
 }
 
 bool AArch64InstrInfo::isWhileOpcode(unsigned Opc) const {
   return get(Opc).TSFlags & AArch64::InstrFlagIsWhile;
 }
 
+unsigned int AArch64InstrInfo::getTailDuplicateSizeOverride() const {
+  return 6;
+}
+
 unsigned llvm::getBLRCallOpcode(const MachineFunction &MF) {
   if (MF.getSubtarget<AArch64Subtarget>().hardenSlsBlr())
     return AArch64::BLRNoIP;
   else
     return AArch64::BLR;
 }
 
 #define GET_INSTRINFO_HELPERS
 #define GET_INSTRMAP_INFO
 #include "AArch64GenInstrInfo.inc"

llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll

 ; DISABLE-NEXT:    subs w20, w20, #1 ; =1
 ; DISABLE-NEXT:    add w19, w0, w19
 ; DISABLE-NEXT:    b.ne LBB1_2
 ; DISABLE-NEXT:  ; %bb.3: ; %for.end
 ; DISABLE-NEXT:    lsl w0, w19, #3
 ; DISABLE-NEXT:    b LBB1_5
 ; DISABLE-NEXT:  LBB1_4: ; %if.else
 ; DISABLE-NEXT:    lsl w0, w1, #1
-; DISABLE-NEXT:  LBB1_5: ; %if.end
+; DISABLE-NEXT:  LBB1_5: ; %for.end
 ; DISABLE-NEXT:    ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
 ; DISABLE-NEXT:    ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
 ; DISABLE-NEXT:    ret
 entry:
   %tobool = icmp eq i32 %cond, 0
   br i1 %tobool, label %if.else, label %for.body
 
 for.body:                                         ; preds = %entry, %for.body

 ; DISABLE-NEXT:    add w19, w0, w19
 ; DISABLE-NEXT:    b.ne LBB3_2
 ; DISABLE-NEXT:  ; %bb.3: ; %for.end
 ; DISABLE-NEXT:    bl _somethingElse
 ; DISABLE-NEXT:    lsl w0, w19, #3
 ; DISABLE-NEXT:    b LBB3_5
 ; DISABLE-NEXT:  LBB3_4: ; %if.else
 ; DISABLE-NEXT:    lsl w0, w1, #1
-; DISABLE-NEXT:  LBB3_5: ; %if.end
+; DISABLE-NEXT:  LBB3_5: ; %if.else
 ; DISABLE-NEXT:    ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
 ; DISABLE-NEXT:    ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
 ; DISABLE-NEXT:    ret
 entry:
   %tobool = icmp eq i32 %cond, 0
   br i1 %tobool, label %if.else, label %for.body
 
 for.body:                                         ; preds = %entry, %for.body

 ; DISABLE-NEXT:    subs w20, w20, #1 ; =1
 ; DISABLE-NEXT:    add w19, w0, w19
 ; DISABLE-NEXT:    b.ne LBB4_2
 ; DISABLE-NEXT:  ; %bb.3: ; %for.end
 ; DISABLE-NEXT:    lsl w0, w19, #3
 ; DISABLE-NEXT:    b LBB4_5
 ; DISABLE-NEXT:  LBB4_4: ; %if.else
 ; DISABLE-NEXT:    lsl w0, w1, #1
-; DISABLE-NEXT:  LBB4_5: ; %if.end
+; DISABLE-NEXT:  LBB4_5: ; %for.end
 ; DISABLE-NEXT:    ldp x29, x30, [sp, #16] ; 16-byte Folded Reload
 ; DISABLE-NEXT:    ldp x20, x19, [sp], #32 ; 16-byte Folded Reload
 ; DISABLE-NEXT:    ret
 entry:
   %tobool = icmp eq i32 %cond, 0
   br i1 %tobool, label %if.else, label %if.then
 
 if.then:                                          ; preds = %entry

 ; DISABLE-NEXT:    cbz w0, LBB8_2
 ; DISABLE-NEXT:  ; %bb.1: ; %if.then
 ; DISABLE-NEXT:    stp x1, x1, [sp, #32]
 ; DISABLE-NEXT:    stp x1, x1, [sp, #16]
 ; DISABLE-NEXT:    stp x1, x1, [sp]
 ; DISABLE-NEXT:    mov w0, w1
 ; DISABLE-NEXT:    bl _someVariadicFunc
 ; DISABLE-NEXT:    lsl w0, w0, #3
-; DISABLE-NEXT:    b LBB8_3
+; DISABLE-NEXT:    ldp x29, x30, [sp, #48] ; 16-byte Folded Reload
+; DISABLE-NEXT:    add sp, sp, #64 ; =64
+; DISABLE-NEXT:    ret
 ; DISABLE-NEXT:  LBB8_2: ; %if.else
 ; DISABLE-NEXT:    lsl w0, w1, #1
-; DISABLE-NEXT:  LBB8_3: ; %if.end
 ; DISABLE-NEXT:    ldp x29, x30, [sp, #48] ; 16-byte Folded Reload
 ; DISABLE-NEXT:    add sp, sp, #64 ; =64
 ; DISABLE-NEXT:    ret
 entry:
   %tobool = icmp eq i32 %cond, 0
   br i1 %tobool, label %if.else, label %if.then
 
 if.then:                                          ; preds = %entry

llvm/test/CodeGen/AArch64/cgp-usubo.ll

 ; CHECK-NEXT:    mov x22, x0
 ; CHECK-NEXT:    cset w0, lo
 ; CHECK-NEXT:    mov x19, x2
 ; CHECK-NEXT:    mov x21, x1
 ; CHECK-NEXT:    bl call
 ; CHECK-NEXT:    subs x8, x22, x21
 ; CHECK-NEXT:    b.hs .LBB8_3
 ; CHECK-NEXT:  // %bb.2: // %end
-; CHECK-NEXT:    cset w0, lo
 ; CHECK-NEXT:    str x8, [x19]
-; CHECK-NEXT:    b .LBB8_4
+; CHECK-NEXT:    ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-NEXT:    ldp x22, x21, [sp, #16] // 16-byte Folded Reload
+; CHECK-NEXT:    cset w0, lo
+; CHECK-NEXT:    ldr x30, [sp], #48 // 8-byte Folded Reload
+; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB8_3: // %f
 ; CHECK-NEXT:    and w0, w20, #0x1
-; CHECK-NEXT:  .LBB8_4: // %f
 ; CHECK-NEXT:    ldp x20, x19, [sp, #32] // 16-byte Folded Reload
 ; CHECK-NEXT:    ldp x22, x21, [sp, #16] // 16-byte Folded Reload
 ; CHECK-NEXT:    ldr x30, [sp], #48 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
 entry:
   br i1 %cond, label %t, label %f
 
 t:

llvm/test/CodeGen/AArch64/ldst-paired-aliasing.ll

 ; CHECK-NEXT:    str xzr, [sp, #80]
 ; CHECK-NEXT:    str w9, [sp, #80]
 ; CHECK-NEXT:    stp q0, q0, [sp, #48]
 ; CHECK-NEXT:    ldr w8, [sp, #48]
 ; CHECK-NEXT:    cmp w8, #1 // =1
 ; CHECK-NEXT:    b.ne .LBB0_2
 ; CHECK-NEXT:  // %bb.1: // %for.inc
 ; CHECK-NEXT:    bl f
-; CHECK-NEXT:    b .LBB0_3
+; CHECK-NEXT:    ldr x30, [sp, #96] // 8-byte Folded Reload
+; CHECK-NEXT:    mov w0, wzr
+; CHECK-NEXT:    add sp, sp, #112 // =112
+; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB0_2: // %if.then
 ; CHECK-NEXT:    bl f2
-; CHECK-NEXT:  .LBB0_3: // %for.inc
 ; CHECK-NEXT:    ldr x30, [sp, #96] // 8-byte Folded Reload
 ; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    add sp, sp, #112 // =112
 ; CHECK-NEXT:    ret
 
 
 for.body.lr.ph.i.i.i.i.i.i63:
   %b1 = alloca [10 x i32], align 16

llvm/test/CodeGen/AArch64/statepoint-call-lowering.ll

 ; CHECK-NEXT:    bl return_i1
 ; CHECK-NEXT:  .Ltmp10:
 ; CHECK-NEXT:    tbz w20, #0, .LBB8_2
 ; CHECK-NEXT:  // %bb.1: // %left
 ; CHECK-NEXT:    mov w19, w0
 ; CHECK-NEXT:    ldr x0, [sp, #8]
 ; CHECK-NEXT:    bl consume
 ; CHECK-NEXT:    and w0, w19, #0x1
-; CHECK-NEXT:    b .LBB8_3
+; CHECK-NEXT:    ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-NEXT:    ldr x30, [sp], #32 // 8-byte Folded Reload
+; CHECK-NEXT:    ret
 ; CHECK-NEXT:  .LBB8_2: // %right
-; CHECK-NEXT:    mov w0, #1
-; CHECK-NEXT:  .LBB8_3: // %right
 ; CHECK-NEXT:    ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-NEXT:    mov w0, #1
 ; CHECK-NEXT:    ldr x30, [sp], #32 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
 entry:
   %safepoint_token = tail call token (i64, i32, i1 ()*, i32, i32, ...) @llvm.experimental.gc.statepoint.p0f_i1f(i64 0, i32 0, i1 ()* @return_i1, i32 0, i32 0, i32 0, i32 0) ["gc-live" (i32 addrspace(1)* %a)]
   br i1 %external_cond, label %left, label %right
 
 left:
   %call1 = call i32 addrspace(1)* @llvm.experimental.gc.relocate.p1i32(token %safepoint_token,  i32 0, i32 0)