[AMDGPU] Add more PAL metadata register names

[foad]

Summary

Add all the registers that are currently used by
LLPC: https://github.com/GPUOpen-Drivers/llpc

This only affects disassembly of PAL metadata generated by LLPC and
similar frontends.

[foad]

I couldn't work out what order the existing entries were in, so I added the new ones in alphabetical order at the end.

I couldn't find any existing test cases for these names.

[arsenm]

Testcase?

[foad]

Add tests.

[Flakebi]

We have slight problems when it comes to differences between hardware versions.
COMPUTE_USER_ACCUM_1 on gfx9 has the same number as COMPUTE_SHADER_CHKSUM on gfx10.
Also, some have slightly different names. E.g. IA_MULTI_VGT_PARAM for gfx9 is called IA_MULTI_VGT_PARAM_PIPED for gfx10.

[foad]

COMPUTE_USER_ACCUM_1 on gfx9 has the same number as COMPUTE_SHADER_CHKSUM on gfx10.

Luckily LLPC only uses COMPUTE_USER_ACCUM_1 on gfx10+.

Also, some have slightly different names. E.g. IA_MULTI_VGT_PARAM for gfx9 is called IA_MULTI_VGT_PARAM_PIPED for gfx10.

I had not noticed that.

[foad]

In D95619#2530860, @Flakebi wrote:

We have slight problems when it comes to differences between hardware versions.
COMPUTE_USER_ACCUM_1 on gfx9 has the same number as COMPUTE_SHADER_CHKSUM on gfx10.
Also, some have slightly different names. E.g. IA_MULTI_VGT_PARAM for gfx9 is called IA_MULTI_VGT_PARAM_PIPED for gfx10.

Ping! Do you think it's OK to commit despite these concerns?

[Flakebi]

If these registers keep changing, we probably want to switch between architectures at some point. But it’s easier to look at (slightly off) names than at hex numbers, so LGTM.

[kzhuravl]

I am not familiar with graphics side much, but is there any reason to not use COMPUTE_PGM_RSRC* registers from https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/Support/AMDHSAKernelDescriptor.h#L130 ?

[foad]

In D95619#2585055, @kzhuravl wrote:

I am not familiar with graphics side much, but is there any reason to not use COMPUTE_PGM_RSRC* registers from https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/Support/AMDHSAKernelDescriptor.h#L130 ?

For dumping PAL metadata all we want is the offsets of the registers. AMDHSAKernelDescriptor.h seems to define the fields within some of these registers instead. Obviously it's related, but I don't think there's actually any duplicated information there.

llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp

const char *Name;
       {0xa2e6, "VGT_STRMOUT_BUFFER_CONFIG"},
       {0xa2e5, "VGT_STRMOUT_CONFIG"},
       {0xa2b5, "VGT_STRMOUT_VTX_STRIDE_0"},
       {0xa2b9, "VGT_STRMOUT_VTX_STRIDE_1"},
       {0xa2bd, "VGT_STRMOUT_VTX_STRIDE_2"},
       {0xa2c1, "VGT_STRMOUT_VTX_STRIDE_3"},
       {0xa316, "VGT_VERTEX_REUSE_BLOCK_CNTL"},
 
+      {0x2e28, "COMPUTE_PGM_RSRC3"},
+      {0x2e2a, "COMPUTE_SHADER_CHKSUM"},
+      {0x2e24, "COMPUTE_USER_ACCUM_0"},
+      {0x2e25, "COMPUTE_USER_ACCUM_1"},
+      {0x2e26, "COMPUTE_USER_ACCUM_2"},
+      {0x2e27, "COMPUTE_USER_ACCUM_3"},
+      {0xa1ff, "GE_MAX_OUTPUT_PER_SUBGROUP"},
+      {0xa2d3, "GE_NGG_SUBGRP_CNTL"},
+      {0xc25f, "GE_STEREO_CNTL"},
+      {0xc262, "GE_USER_VGPR_EN"},
+      {0xc258, "IA_MULTI_VGT_PARAM_PIPED"},
+      {0xa210, "PA_STEREO_CNTL"},
+      {0xa1c2, "SPI_SHADER_IDX_FORMAT"},
+      {0x2c80, "SPI_SHADER_PGM_CHKSUM_GS"},
+      {0x2d00, "SPI_SHADER_PGM_CHKSUM_HS"},
+      {0x2c06, "SPI_SHADER_PGM_CHKSUM_PS"},
+      {0x2c45, "SPI_SHADER_PGM_CHKSUM_VS"},
+      {0x2c88, "SPI_SHADER_PGM_LO_GS"},
+      {0x2cb2, "SPI_SHADER_USER_ACCUM_ESGS_0"},
+      {0x2cb3, "SPI_SHADER_USER_ACCUM_ESGS_1"},
+      {0x2cb4, "SPI_SHADER_USER_ACCUM_ESGS_2"},
+      {0x2cb5, "SPI_SHADER_USER_ACCUM_ESGS_3"},
+      {0x2d32, "SPI_SHADER_USER_ACCUM_LSHS_0"},
+      {0x2d33, "SPI_SHADER_USER_ACCUM_LSHS_1"},
+      {0x2d34, "SPI_SHADER_USER_ACCUM_LSHS_2"},
+      {0x2d35, "SPI_SHADER_USER_ACCUM_LSHS_3"},
+      {0x2c32, "SPI_SHADER_USER_ACCUM_PS_0"},
+      {0x2c33, "SPI_SHADER_USER_ACCUM_PS_1"},
+      {0x2c34, "SPI_SHADER_USER_ACCUM_PS_2"},
+      {0x2c35, "SPI_SHADER_USER_ACCUM_PS_3"},
+      {0x2c72, "SPI_SHADER_USER_ACCUM_VS_0"},
+      {0x2c73, "SPI_SHADER_USER_ACCUM_VS_1"},
+      {0x2c74, "SPI_SHADER_USER_ACCUM_VS_2"},
+      {0x2c75, "SPI_SHADER_USER_ACCUM_VS_3"},
+
       {0, nullptr}};
   auto Entry = RegInfoTable;
   for (; Entry->Num && Entry->Num != RegNum; ++Entry)
     ;
   return Entry->Name;
 }
 
 // Convert the accumulated PAL metadata into an asm directive.

llvm/test/MC/AMDGPU/pal-registers.s

 // RUN: llvm-mc -triple amdgcn--amdpal %s | FileCheck %s
 
   .amdgpu_pal_metadata
 ---
 amdpal.pipelines:
   - .hardware_stages:
       .ps:
         .entry_point:    ps_amdpal
         .scratch_memory_size: 0
         .sgpr_count:     0x1
         .vgpr_count:     0x1
     .internal_pipeline_hash:
       - 0x123456789abcdef0
       - 0xfedcba9876543210
     .registers:
+      0x2c06: 0
       0x2c07: 0
       0x2c0a: 0
       0x2c0b: 0
       0x2c0c: 0
       0x2c0d: 0
       0x2c0e: 0
       0x2c0f: 0
       0x2c10: 0
.registers:
       0x2c24: 0
       0x2c25: 0
       0x2c26: 0
       0x2c27: 0
       0x2c28: 0
       0x2c29: 0
       0x2c2a: 0
       0x2c2b: 0
+      0x2c32: 0
+      0x2c33: 0
+      0x2c34: 0
+      0x2c35: 0
+      0x2c45: 0
       0x2c46: 0
       0x2c4a: 0
       0x2c4b: 0
       0x2c4c: 0
       0x2c4d: 0
       0x2c4e: 0
       0x2c4f: 0
       0x2c50: 0
.registers:
       0x2c64: 0
       0x2c65: 0
       0x2c66: 0
       0x2c67: 0
       0x2c68: 0
       0x2c69: 0
       0x2c6a: 0
       0x2c6b: 0
+      0x2c72: 0
+      0x2c73: 0
+      0x2c74: 0
+      0x2c75: 0
+      0x2c80: 0
       0x2c81: 0
       0x2c87: 0
+      0x2c88: 0
       0x2c8a: 0
       0x2c8b: 0
       0x2c8c: 0
       0x2c8d: 0
       0x2c8e: 0
       0x2c8f: 0
       0x2c90: 0
       0x2c91: 0
.registers:
       0x2ca4: 0
       0x2ca5: 0
       0x2ca6: 0
       0x2ca7: 0
       0x2ca8: 0
       0x2ca9: 0
       0x2caa: 0
       0x2cab: 0
+      0x2cb2: 0
+      0x2cb3: 0
+      0x2cb4: 0
+      0x2cb5: 0
       0x2cc7: 0
       0x2cca: 0
       0x2ccb: 0
       0x2ccc: 0
       0x2ccd: 0
       0x2cce: 0
       0x2ccf: 0
       0x2cd0: 0
.registers:
       0x2ce4: 0
       0x2ce5: 0
       0x2ce6: 0
       0x2ce7: 0
       0x2ce8: 0
       0x2ce9: 0
       0x2cea: 0
       0x2ceb: 0
+      0x2d00: 0
       0x2d07: 0
       0x2d0a: 0
       0x2d0b: 0
       0x2d0c: 0
       0x2d0d: 0
       0x2d0e: 0
       0x2d0f: 0
       0x2d10: 0
.registers:
       0x2d24: 0
       0x2d25: 0
       0x2d26: 0
       0x2d27: 0
       0x2d28: 0
       0x2d29: 0
       0x2d2a: 0
       0x2d2b: 0
+      0x2d32: 0
+      0x2d33: 0
+      0x2d34: 0
+      0x2d35: 0
       0x2d47: 0
       0x2d4a: 0
       0x2d4b: 0
       0x2d4c: 0
       0x2d4d: 0
       0x2d4e: 0
       0x2d4f: 0
       0x2d50: 0
.registers:
       0x2d5b: 0
       0x2e00: 0
       0x2e07: 0
       0x2e08: 0
       0x2e09: 0
       0x2e12: 0
       0x2e13: 0
       0x2e18: 0
+      0x2e24: 0
+      0x2e25: 0
+      0x2e26: 0
+      0x2e27: 0
+      0x2e28: 0
+      0x2e2a: 0
       0x2e40: 0
       0x2e41: 0
       0x2e42: 0
       0x2e43: 0
       0x2e44: 0
       0x2e45: 0
       0x2e46: 0
       0x2e47: 0
.registers:
       0xa1b0: 0
       0xa1b1: 0
       0xa1b3: 0
       0xa1b4: 0
       0xa1b5: 0
       0xa1b6: 0
       0xa1b8: 0
       0xa1ba: 0
+      0xa1c2: 0
       0xa1c3: 0
       0xa1c4: 0
       0xa1c5: 0
+      0xa1ff: 0
       0xa203: 0
       0xa204: 0
       0xa206: 0
       0xa207: 0
+      0xa210: 0
       0xa286: 0
       0xa287: 0
       0xa290: 0
       0xa291: 0
       0xa293: 0
       0xa297: 0
       0xa298: 0
       0xa299: 0
       0xa29a: 0
       0xa29b: 0
       0xa2a1: 0
       0xa2a5: 0
       0xa2aa: 0
       0xa2ab: 0
       0xa2ac: 0
       0xa2ad: 0
       0xa2b5: 0
       0xa2b9: 0
       0xa2bd: 0
       0xa2c1: 0
       0xa2ce: 0
+      0xa2d3: 0
       0xa2d5: 0
       0xa2d6: 0
       0xa2d7: 0
       0xa2d8: 0
       0xa2d9: 0
       0xa2da: 0
       0xa2db: 0
       0xa2e4: 0
       0xa2e5: 0
       0xa2e6: 0
       0xa2f8: 0
       0xa2f9: 0
       0xa310: 0
       0xa313: 0
       0xa316: 0
+      0xc258: 0
+      0xc25f: 0
+      0xc262: 0
 ...
   .end_amdgpu_pal_metadata
 
+// CHECK: 0x2c06 (SPI_SHADER_PGM_CHKSUM_PS)
 // CHECK: 0x2c07 (SPI_SHADER_PGM_RSRC3_PS)
 // CHECK: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS)
 // CHECK: 0x2c0b (SPI_SHADER_PGM_RSRC2_PS)
 // CHECK: 0x2c0c (SPI_SHADER_USER_DATA_PS_0)
 // CHECK: 0x2c0d (SPI_SHADER_USER_DATA_PS_1)
 // CHECK: 0x2c0e (SPI_SHADER_USER_DATA_PS_2)
 // CHECK: 0x2c0f (SPI_SHADER_USER_DATA_PS_3)
 // CHECK: 0x2c10 (SPI_SHADER_USER_DATA_PS_4)

 // CHECK: 0x2c24 (SPI_SHADER_USER_DATA_PS_24)
 // CHECK: 0x2c25 (SPI_SHADER_USER_DATA_PS_25)
 // CHECK: 0x2c26 (SPI_SHADER_USER_DATA_PS_26)
 // CHECK: 0x2c27 (SPI_SHADER_USER_DATA_PS_27)
 // CHECK: 0x2c28 (SPI_SHADER_USER_DATA_PS_28)
 // CHECK: 0x2c29 (SPI_SHADER_USER_DATA_PS_29)
 // CHECK: 0x2c2a (SPI_SHADER_USER_DATA_PS_30)
 // CHECK: 0x2c2b (SPI_SHADER_USER_DATA_PS_31)
+// CHECK: 0x2c32 (SPI_SHADER_USER_ACCUM_PS_0)
+// CHECK: 0x2c33 (SPI_SHADER_USER_ACCUM_PS_1)
+// CHECK: 0x2c34 (SPI_SHADER_USER_ACCUM_PS_2)
+// CHECK: 0x2c35 (SPI_SHADER_USER_ACCUM_PS_3)
+// CHECK: 0x2c45 (SPI_SHADER_PGM_CHKSUM_VS)
 // CHECK: 0x2c46 (SPI_SHADER_PGM_RSRC3_VS)
 // CHECK: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS)
 // CHECK: 0x2c4b (SPI_SHADER_PGM_RSRC2_VS)
 // CHECK: 0x2c4c (SPI_SHADER_USER_DATA_VS_0)
 // CHECK: 0x2c4d (SPI_SHADER_USER_DATA_VS_1)
 // CHECK: 0x2c4e (SPI_SHADER_USER_DATA_VS_2)
 // CHECK: 0x2c4f (SPI_SHADER_USER_DATA_VS_3)
 // CHECK: 0x2c50 (SPI_SHADER_USER_DATA_VS_4)

 // CHECK: 0x2c64 (SPI_SHADER_USER_DATA_VS_24)
 // CHECK: 0x2c65 (SPI_SHADER_USER_DATA_VS_25)
 // CHECK: 0x2c66 (SPI_SHADER_USER_DATA_VS_26)
 // CHECK: 0x2c67 (SPI_SHADER_USER_DATA_VS_27)
 // CHECK: 0x2c68 (SPI_SHADER_USER_DATA_VS_28)
 // CHECK: 0x2c69 (SPI_SHADER_USER_DATA_VS_29)
 // CHECK: 0x2c6a (SPI_SHADER_USER_DATA_VS_30)
 // CHECK: 0x2c6b (SPI_SHADER_USER_DATA_VS_31)
+// CHECK: 0x2c72 (SPI_SHADER_USER_ACCUM_VS_0)
+// CHECK: 0x2c73 (SPI_SHADER_USER_ACCUM_VS_1)
+// CHECK: 0x2c74 (SPI_SHADER_USER_ACCUM_VS_2)
+// CHECK: 0x2c75 (SPI_SHADER_USER_ACCUM_VS_3)
+// CHECK: 0x2c80 (SPI_SHADER_PGM_CHKSUM_GS)
 // CHECK: 0x2c81 (SPI_SHADER_PGM_RSRC4_GS)
 // CHECK: 0x2c87 (SPI_SHADER_PGM_RSRC3_GS)
+// CHECK: 0x2c88 (SPI_SHADER_PGM_LO_GS)
 // CHECK: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS)
 // CHECK: 0x2c8b (SPI_SHADER_PGM_RSRC2_GS)
 // CHECK: 0x2c8c (SPI_SHADER_USER_DATA_GS_0)
 // CHECK: 0x2c8d (SPI_SHADER_USER_DATA_GS_1)
 // CHECK: 0x2c8e (SPI_SHADER_USER_DATA_GS_2)
 // CHECK: 0x2c8f (SPI_SHADER_USER_DATA_GS_3)
 // CHECK: 0x2c90 (SPI_SHADER_USER_DATA_GS_4)
 // CHECK: 0x2c91 (SPI_SHADER_USER_DATA_GS_5)

 // CHECK: 0x2ca4 (SPI_SHADER_USER_DATA_GS_24)
 // CHECK: 0x2ca5 (SPI_SHADER_USER_DATA_GS_25)
 // CHECK: 0x2ca6 (SPI_SHADER_USER_DATA_GS_26)
 // CHECK: 0x2ca7 (SPI_SHADER_USER_DATA_GS_27)
 // CHECK: 0x2ca8 (SPI_SHADER_USER_DATA_GS_28)
 // CHECK: 0x2ca9 (SPI_SHADER_USER_DATA_GS_29)
 // CHECK: 0x2caa (SPI_SHADER_USER_DATA_GS_30)
 // CHECK: 0x2cab (SPI_SHADER_USER_DATA_GS_31)
+// CHECK: 0x2cb2 (SPI_SHADER_USER_ACCUM_ESGS_0)
+// CHECK: 0x2cb3 (SPI_SHADER_USER_ACCUM_ESGS_1)
+// CHECK: 0x2cb4 (SPI_SHADER_USER_ACCUM_ESGS_2)
+// CHECK: 0x2cb5 (SPI_SHADER_USER_ACCUM_ESGS_3)
 // CHECK: 0x2cc7 (SPI_SHADER_PGM_RSRC3_ES)
 // CHECK: 0x2cca (SPI_SHADER_PGM_RSRC1_ES)
 // CHECK: 0x2ccb (SPI_SHADER_PGM_RSRC2_ES)
 // CHECK: 0x2ccc (SPI_SHADER_USER_DATA_ES_0)
 // CHECK: 0x2ccd (SPI_SHADER_USER_DATA_ES_1)
 // CHECK: 0x2cce (SPI_SHADER_USER_DATA_ES_2)
 // CHECK: 0x2ccf (SPI_SHADER_USER_DATA_ES_3)
 // CHECK: 0x2cd0 (SPI_SHADER_USER_DATA_ES_4)

 // CHECK: 0x2ce4 (SPI_SHADER_USER_DATA_ES_24)
 // CHECK: 0x2ce5 (SPI_SHADER_USER_DATA_ES_25)
 // CHECK: 0x2ce6 (SPI_SHADER_USER_DATA_ES_26)
 // CHECK: 0x2ce7 (SPI_SHADER_USER_DATA_ES_27)
 // CHECK: 0x2ce8 (SPI_SHADER_USER_DATA_ES_28)
 // CHECK: 0x2ce9 (SPI_SHADER_USER_DATA_ES_29)
 // CHECK: 0x2cea (SPI_SHADER_USER_DATA_ES_30)
 // CHECK: 0x2ceb (SPI_SHADER_USER_DATA_ES_31)
+// CHECK: 0x2d00 (SPI_SHADER_PGM_CHKSUM_HS)
 // CHECK: 0x2d07 (SPI_SHADER_PGM_RSRC3_HS)
 // CHECK: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS)
 // CHECK: 0x2d0b (SPI_SHADER_PGM_RSRC2_HS)
 // CHECK: 0x2d0c (SPI_SHADER_USER_DATA_HS_0)
 // CHECK: 0x2d0d (SPI_SHADER_USER_DATA_HS_1)
 // CHECK: 0x2d0e (SPI_SHADER_USER_DATA_HS_2)
 // CHECK: 0x2d0f (SPI_SHADER_USER_DATA_HS_3)
 // CHECK: 0x2d10 (SPI_SHADER_USER_DATA_HS_4)

 // CHECK: 0x2d24 (SPI_SHADER_USER_DATA_HS_24)
 // CHECK: 0x2d25 (SPI_SHADER_USER_DATA_HS_25)
 // CHECK: 0x2d26 (SPI_SHADER_USER_DATA_HS_26)
 // CHECK: 0x2d27 (SPI_SHADER_USER_DATA_HS_27)
 // CHECK: 0x2d28 (SPI_SHADER_USER_DATA_HS_28)
 // CHECK: 0x2d29 (SPI_SHADER_USER_DATA_HS_29)
 // CHECK: 0x2d2a (SPI_SHADER_USER_DATA_HS_30)
 // CHECK: 0x2d2b (SPI_SHADER_USER_DATA_HS_31)
+// CHECK: 0x2d32 (SPI_SHADER_USER_ACCUM_LSHS_0)
+// CHECK: 0x2d33 (SPI_SHADER_USER_ACCUM_LSHS_1)
+// CHECK: 0x2d34 (SPI_SHADER_USER_ACCUM_LSHS_2)
+// CHECK: 0x2d35 (SPI_SHADER_USER_ACCUM_LSHS_3)
 // CHECK: 0x2d47 (SPI_SHADER_PGM_RSRC3_LS)
 // CHECK: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS)
 // CHECK: 0x2d4b (SPI_SHADER_PGM_RSRC2_LS)
 // CHECK: 0x2d4c (SPI_SHADER_USER_DATA_LS_0)
 // CHECK: 0x2d4d (SPI_SHADER_USER_DATA_LS_1)
 // CHECK: 0x2d4e (SPI_SHADER_USER_DATA_LS_2)
 // CHECK: 0x2d4f (SPI_SHADER_USER_DATA_LS_3)
 // CHECK: 0x2d50 (SPI_SHADER_USER_DATA_LS_4)

 // CHECK: 0x2d5b (SPI_SHADER_USER_DATA_LS_15)
 // CHECK: 0x2e00 (COMPUTE_DISPATCH_INITIATOR)
 // CHECK: 0x2e07 (COMPUTE_NUM_THREAD_X)
 // CHECK: 0x2e08 (COMPUTE_NUM_THREAD_Y)
 // CHECK: 0x2e09 (COMPUTE_NUM_THREAD_Z)
 // CHECK: 0x2e12 (COMPUTE_PGM_RSRC1)
 // CHECK: 0x2e13 (COMPUTE_PGM_RSRC2)
 // CHECK: 0x2e18 (COMPUTE_TMPRING_SIZE)
+// CHECK: 0x2e24 (COMPUTE_USER_ACCUM_0)
+// CHECK: 0x2e25 (COMPUTE_USER_ACCUM_1)
+// CHECK: 0x2e26 (COMPUTE_USER_ACCUM_2)
+// CHECK: 0x2e27 (COMPUTE_USER_ACCUM_3)
+// CHECK: 0x2e28 (COMPUTE_PGM_RSRC3)
+// CHECK: 0x2e2a (COMPUTE_SHADER_CHKSUM)
 // CHECK: 0x2e40 (COMPUTE_USER_DATA_0)
 // CHECK: 0x2e41 (COMPUTE_USER_DATA_1)
 // CHECK: 0x2e42 (COMPUTE_USER_DATA_2)
 // CHECK: 0x2e43 (COMPUTE_USER_DATA_3)
 // CHECK: 0x2e44 (COMPUTE_USER_DATA_4)
 // CHECK: 0x2e45 (COMPUTE_USER_DATA_5)
 // CHECK: 0x2e46 (COMPUTE_USER_DATA_6)
 // CHECK: 0x2e47 (COMPUTE_USER_DATA_7)

 // CHECK: 0xa1b0 (SPI_PS_INPUT_CNTL_31)
 // CHECK: 0xa1b1 (SPI_VS_OUT_CONFIG)
 // CHECK: 0xa1b3 (SPI_PS_INPUT_ENA)
 // CHECK: 0xa1b4 (SPI_PS_INPUT_ADDR)
 // CHECK: 0xa1b5 (SPI_INTERP_CONTROL_0)
 // CHECK: 0xa1b6 (SPI_PS_IN_CONTROL)
 // CHECK: 0xa1b8 (SPI_BARYC_CNTL)
 // CHECK: 0xa1ba (SPI_TMPRING_SIZE)
+// CHECK: 0xa1c2 (SPI_SHADER_IDX_FORMAT)
 // CHECK: 0xa1c3 (SPI_SHADER_POS_FORMAT)
 // CHECK: 0xa1c4 (SPI_SHADER_Z_FORMAT)
 // CHECK: 0xa1c5 (SPI_SHADER_COL_FORMAT)
+// CHECK: 0xa1ff (GE_MAX_OUTPUT_PER_SUBGROUP)
 // CHECK: 0xa203 (DB_SHADER_CONTROL)
 // CHECK: 0xa204 (PA_CL_CLIP_CNTL)
 // CHECK: 0xa206 (PA_CL_VTE_CNTL)
 // CHECK: 0xa207 (PA_CL_VS_OUT_CNTL)
+// CHECK: 0xa210 (PA_STEREO_CNTL)
 // CHECK: 0xa286 (VGT_HOS_MAX_TESS_LEVEL)
 // CHECK: 0xa287 (VGT_HOS_MIN_TESS_LEVEL)
 // CHECK: 0xa290 (VGT_GS_MODE)
 // CHECK: 0xa291 (VGT_GS_ONCHIP_CNTL)
 // CHECK: 0xa293 (PA_SC_MODE_CNTL_1)
 // CHECK: 0xa297 (VGT_GS_PER_VS)
 // CHECK: 0xa298 (VGT_GSVS_RING_OFFSET_1)
 // CHECK: 0xa299 (VGT_GSVS_RING_OFFSET_2)
 // CHECK: 0xa29a (VGT_GSVS_RING_OFFSET_3)
 // CHECK: 0xa29b (VGT_GS_OUT_PRIM_TYPE)
 // CHECK: 0xa2a1 (VGT_PRIMITIVEID_EN)
 // CHECK: 0xa2a5 (VGT_GS_MAX_PRIMS_PER_SUBGROUP)
 // CHECK: 0xa2aa (IA_MULTI_VGT_PARAM)
 // CHECK: 0xa2ab (VGT_ESGS_RING_ITEMSIZE)
 // CHECK: 0xa2ac (VGT_GSVS_RING_ITEMSIZE)
 // CHECK: 0xa2ad (VGT_REUSE_OFF)
 // CHECK: 0xa2b5 (VGT_STRMOUT_VTX_STRIDE_0)
 // CHECK: 0xa2b9 (VGT_STRMOUT_VTX_STRIDE_1)
 // CHECK: 0xa2bd (VGT_STRMOUT_VTX_STRIDE_2)
 // CHECK: 0xa2c1 (VGT_STRMOUT_VTX_STRIDE_3)
 // CHECK: 0xa2ce (VGT_GS_MAX_VERT_OUT)
+// CHECK: 0xa2d3 (GE_NGG_SUBGRP_CNTL)
 // CHECK: 0xa2d5 (VGT_SHADER_STAGES_EN)
 // CHECK: 0xa2d6 (VGT_LS_HS_CONFIG)
 // CHECK: 0xa2d7 (VGT_GS_VERT_ITEMSIZE)
 // CHECK: 0xa2d8 (VGT_GS_VERT_ITEMSIZE_1)
 // CHECK: 0xa2d9 (VGT_GS_VERT_ITEMSIZE_2)
 // CHECK: 0xa2da (VGT_GS_VERT_ITEMSIZE_3)
 // CHECK: 0xa2db (VGT_TF_PARAM)
 // CHECK: 0xa2e4 (VGT_GS_INSTANCE_CNT)
 // CHECK: 0xa2e5 (VGT_STRMOUT_CONFIG)
 // CHECK: 0xa2e6 (VGT_STRMOUT_BUFFER_CONFIG)
 // CHECK: 0xa2f8 (PA_SC_AA_CONFIG)
 // CHECK: 0xa2f9 (PA_SU_VTX_CNTL)
 // CHECK: 0xa310 (PA_SC_SHADER_CONTROL)
 // CHECK: 0xa313 (PA_SC_CONSERVATIVE_RASTERIZATION_CNTL)
 // CHECK: 0xa316 (VGT_VERTEX_REUSE_BLOCK_CNTL)
+// CHECK: 0xc258 (IA_MULTI_VGT_PARAM_PIPED)
+// CHECK: 0xc25f (GE_STEREO_CNTL)
+// CHECK: 0xc262 (GE_USER_VGPR_EN)