[AMDGPU] Add more PAL metadata register names

[foad]

Summary

Add all the registers that are currently used by
LLPC: https://github.com/GPUOpen-Drivers/llpc

This only affects disassembly of PAL metadata generated by LLPC and
similar frontends.

[foad]

I couldn't work out what order the existing entries were in, so I added the new ones in alphabetical order at the end.

I couldn't find any existing test cases for these names.

[arsenm]

Testcase?

[foad]

Add tests.

[Flakebi]

We have slight problems when it comes to differences between hardware versions.
COMPUTE_USER_ACCUM_1 on gfx9 has the same number as COMPUTE_SHADER_CHKSUM on gfx10.
Also, some have slightly different names. E.g. IA_MULTI_VGT_PARAM for gfx9 is called IA_MULTI_VGT_PARAM_PIPED for gfx10.

[foad]

COMPUTE_USER_ACCUM_1 on gfx9 has the same number as COMPUTE_SHADER_CHKSUM on gfx10.

Luckily LLPC only uses COMPUTE_USER_ACCUM_1 on gfx10+.

Also, some have slightly different names. E.g. IA_MULTI_VGT_PARAM for gfx9 is called IA_MULTI_VGT_PARAM_PIPED for gfx10.

I had not noticed that.

[foad]

In D95619#2530860, @Flakebi wrote:

We have slight problems when it comes to differences between hardware versions.
COMPUTE_USER_ACCUM_1 on gfx9 has the same number as COMPUTE_SHADER_CHKSUM on gfx10.
Also, some have slightly different names. E.g. IA_MULTI_VGT_PARAM for gfx9 is called IA_MULTI_VGT_PARAM_PIPED for gfx10.

Ping! Do you think it's OK to commit despite these concerns?

[Flakebi]

If these registers keep changing, we probably want to switch between architectures at some point. But it’s easier to look at (slightly off) names than at hex numbers, so LGTM.

[kzhuravl]

I am not familiar with graphics side much, but is there any reason to not use COMPUTE_PGM_RSRC* registers from https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/Support/AMDHSAKernelDescriptor.h#L130 ?

[foad]

In D95619#2585055, @kzhuravl wrote:

I am not familiar with graphics side much, but is there any reason to not use COMPUTE_PGM_RSRC* registers from https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/Support/AMDHSAKernelDescriptor.h#L130 ?

For dumping PAL metadata all we want is the offsets of the registers. AMDHSAKernelDescriptor.h seems to define the fields within some of these registers instead. Obviously it's related, but I don't think there's actually any duplicated information there.

llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp

const char *Name;
       {0xa2e6, "VGT_STRMOUT_BUFFER_CONFIG"},
       {0xa2e5, "VGT_STRMOUT_CONFIG"},
       {0xa2b5, "VGT_STRMOUT_VTX_STRIDE_0"},
       {0xa2b9, "VGT_STRMOUT_VTX_STRIDE_1"},
       {0xa2bd, "VGT_STRMOUT_VTX_STRIDE_2"},
       {0xa2c1, "VGT_STRMOUT_VTX_STRIDE_3"},
       {0xa316, "VGT_VERTEX_REUSE_BLOCK_CNTL"},
 
+      {0x2e28, "COMPUTE_PGM_RSRC3"},
+      {0x2e25, "COMPUTE_SHADER_CHKSUM"},
+      {0x2e2a, "COMPUTE_SHADER_CHKSUM"},
+      {0x2e24, "COMPUTE_USER_ACCUM_0"},
+      {0x2e25, "COMPUTE_USER_ACCUM_1"},
+      {0x2e26, "COMPUTE_USER_ACCUM_2"},
+      {0x2e27, "COMPUTE_USER_ACCUM_3"},
+      {0xa1ff, "GE_MAX_OUTPUT_PER_SUBGROUP"},
+      {0xa2d3, "GE_NGG_SUBGRP_CNTL"},
+      {0xc25f, "GE_STEREO_CNTL"},
+      {0xc262, "GE_USER_VGPR_EN"},
+      {0xc258, "IA_MULTI_VGT_PARAM_PIPED"},
+      {0xa210, "PA_STEREO_CNTL"},
+      {0xa210, "PA_STEREO_CNTL"},
+      {0xa1c2, "SPI_SHADER_IDX_FORMAT"},
+      {0x2c80, "SPI_SHADER_PGM_CHKSUM_GS"},
+      {0x2d00, "SPI_SHADER_PGM_CHKSUM_HS"},
+      {0x2c06, "SPI_SHADER_PGM_CHKSUM_PS"},
+      {0x2c45, "SPI_SHADER_PGM_CHKSUM_VS"},
+      {0x2c45, "SPI_SHADER_PGM_CHKSUM_VS"},
+      {0x2c88, "SPI_SHADER_PGM_LO_GS"},
+      {0x2cb2, "SPI_SHADER_USER_ACCUM_ESGS_0"},
+      {0x2cb3, "SPI_SHADER_USER_ACCUM_ESGS_1"},
+      {0x2cb4, "SPI_SHADER_USER_ACCUM_ESGS_2"},
+      {0x2cb5, "SPI_SHADER_USER_ACCUM_ESGS_3"},
+      {0x2d32, "SPI_SHADER_USER_ACCUM_LSHS_0"},
+      {0x2d33, "SPI_SHADER_USER_ACCUM_LSHS_1"},
+      {0x2d34, "SPI_SHADER_USER_ACCUM_LSHS_2"},
+      {0x2d35, "SPI_SHADER_USER_ACCUM_LSHS_3"},
+      {0x2c32, "SPI_SHADER_USER_ACCUM_PS_0"},
+      {0x2c33, "SPI_SHADER_USER_ACCUM_PS_1"},
+      {0x2c34, "SPI_SHADER_USER_ACCUM_PS_2"},
+      {0x2c35, "SPI_SHADER_USER_ACCUM_PS_3"},
+      {0x2c72, "SPI_SHADER_USER_ACCUM_VS_0"},
+      {0x2c73, "SPI_SHADER_USER_ACCUM_VS_1"},
+      {0x2c74, "SPI_SHADER_USER_ACCUM_VS_2"},
+      {0x2c75, "SPI_SHADER_USER_ACCUM_VS_3"},
+
       {0, nullptr}};
   auto Entry = RegInfoTable;
   for (; Entry->Num && Entry->Num != RegNum; ++Entry)
     ;
   return Entry->Name;
 }
 
 // Convert the accumulated PAL metadata into an asm directive.