[update_llc_test_checks][RISCV] Add new tests

[benshi001]

All backends have two test cases inside llvm/test/tools/UpdateTestChecks/update_llc_test_checks/ , except riscv. And my patch addes the missing test xxx_generated.funcs.ll for riscv.

[arichardson]

This used to exist but it exposed a bug and the test was removed in b8779337841bea03bc514d239ce76eceba3f01dd. The commit message states that it only happened with expensive-checks. If it works (with expensive checks) b8779337841bea03bc514d239ce76eceba3f01dd can be reverted.

[jrtc27]

Hm, there is a lot of duplication in all these tests (we currently have 12 copies of almost-identical IR), it seems like we should just add a whole load of CHECK lines to a single copy of the IR?..

[jrtc27]

In D95304#2522341, @arichardson wrote:

This used to exist but it exposed a bug and the test was removed in b8779337841bea03bc514d239ce76eceba3f01dd. The commit message states that it only happened with expensive-checks. If it works (with expensive checks) b8779337841bea03bc514d239ce76eceba3f01dd can be reverted.

That's... not a good way to fix a bug? This is news to me, and that was committed without any review (let alone by RISC-V maintainers...). And no mention of what the bug actually is in the commit message.

[luismarques]

In D95304#2522347, @jrtc27 wrote:

That's... not a good way to fix a bug? This is news to me, and that was committed without any review (let alone by RISC-V maintainers...). And no mention of what the bug actually is in the commit message.

Indeed.

In D95304#2522342, @jrtc27 wrote:

Hm, there is a lot of duplication in all these tests (we currently have 12 copies of almost-identical IR), it seems like we should just add a whole load of CHECK lines to a single copy of the IR?..

That would be nice if possible, but IMO that should be a separate patch. Wouldn't that require the bots to support all of the targets to run the combined test? I also wonder if that could become awkward in the future if the outlining started to diverge significantly between targets.

In D95304#2522341, @arichardson wrote:

This used to exist but it exposed a bug and the test was removed in b8779337841bea03bc514d239ce76eceba3f01dd. The commit message states that it only happened with expensive-checks. If it works (with expensive checks) b8779337841bea03bc514d239ce76eceba3f01dd can be reverted.

If the builbots with expensive checks are all OK for this patch, and this patch is exactly the same as what b8779337841b removed, should we then just revert b8779337841b now?

[jrtc27]

In D95304#2522758, @luismarques wrote:

In D95304#2522347, @jrtc27 wrote:

That's... not a good way to fix a bug? This is news to me, and that was committed without any review (let alone by RISC-V maintainers...). And no mention of what the bug actually is in the commit message.

Indeed.

In D95304#2522342, @jrtc27 wrote:

Hm, there is a lot of duplication in all these tests (we currently have 12 copies of almost-identical IR), it seems like we should just add a whole load of CHECK lines to a single copy of the IR?..

That would be nice if possible, but IMO that should be a separate patch. Wouldn't that require the bots to support all of the targets to run the combined test? I also wonder if that could become awkward in the future if the outlining started to diverge significantly between targets.

Ah good point, you'd want the single copy of the IR and prepend a header on the thing at test time for each architecture (each being its own .test like now)? I.e. we'd just generate all the foo_generated_funcs.ll at test time rather than have N copies of them in the tree, but everything else would be the same.

[luismarques]

In D95304#2522772, @jrtc27 wrote:

Ah good point, you'd want the single copy of the IR and prepend a header on the thing at test time for each architecture (each being its own .test like now)? I.e. we'd just generate all the foo_generated_funcs.ll at test time rather than have N copies of them in the tree, but everything else would be the same.

Yeah, that would work.

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/riscv_generated_funcs.ll

+; RUN: llc -enable-machine-outliner -mtriple=riscv32-unknown-linux < %s | FileCheck %s
+
+@x = global i32 0, align 4
+
+define dso_local i32 @check_boundaries() #0 {
+  %1 = alloca i32, align 4
+  %2 = alloca i32, align 4
+  %3 = alloca i32, align 4
+  %4 = alloca i32, align 4
+  %5 = alloca i32, align 4
+  store i32 0, i32* %1, align 4
+  store i32 0, i32* %2, align 4
+  %6 = load i32, i32* %2, align 4
+  %7 = icmp ne i32 %6, 0
+  br i1 %7, label %9, label %8
+
+  store i32 1, i32* %2, align 4
+  store i32 2, i32* %3, align 4
+  store i32 3, i32* %4, align 4
+  store i32 4, i32* %5, align 4
+  br label %10
+
+  store i32 1, i32* %4, align 4
+  br label %10
+
+  %11 = load i32, i32* %2, align 4
+  %12 = icmp ne i32 %11, 0
+  br i1 %12, label %14, label %13
+
+  store i32 1, i32* %2, align 4
+  store i32 2, i32* %3, align 4
+  store i32 3, i32* %4, align 4
+  store i32 4, i32* %5, align 4
+  br label %15
+
+  store i32 1, i32* %4, align 4
+  br label %15
+
+  ret i32 0
+}
+
+define dso_local i32 @main() #0 {
+  %1 = alloca i32, align 4
+  %2 = alloca i32, align 4
+  %3 = alloca i32, align 4
+  %4 = alloca i32, align 4
+  %5 = alloca i32, align 4
+
+  store i32 0, i32* %1, align 4
+  store i32 0, i32* @x, align 4
+  store i32 1, i32* %2, align 4
+  store i32 2, i32* %3, align 4
+  store i32 3, i32* %4, align 4
+  store i32 4, i32* %5, align 4
+  store i32 1, i32* @x, align 4
+  call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()
+  store i32 1, i32* %2, align 4
+  store i32 2, i32* %3, align 4
+  store i32 3, i32* %4, align 4
+  store i32 4, i32* %5, align 4
+  ret i32 0
+}
+
+attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" }

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/riscv_generated_funcs.ll.generated.expected

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --include-generated-funcs
+; RUN: llc -enable-machine-outliner -mtriple=riscv32-unknown-linux < %s | FileCheck %s
+
+@x = global i32 0, align 4
+
+define dso_local i32 @check_boundaries() #0 {
+  %1 = alloca i32, align 4
+  %2 = alloca i32, align 4
+  %3 = alloca i32, align 4
+  %4 = alloca i32, align 4
+  %5 = alloca i32, align 4
+  store i32 0, i32* %1, align 4
+  store i32 0, i32* %2, align 4
+  %6 = load i32, i32* %2, align 4
+  %7 = icmp ne i32 %6, 0
+  br i1 %7, label %9, label %8
+
+  store i32 1, i32* %2, align 4
+  store i32 2, i32* %3, align 4
+  store i32 3, i32* %4, align 4
+  store i32 4, i32* %5, align 4
+  br label %10
+
+  store i32 1, i32* %4, align 4
+  br label %10
+
+  %11 = load i32, i32* %2, align 4
+  %12 = icmp ne i32 %11, 0
+  br i1 %12, label %14, label %13
+
+  store i32 1, i32* %2, align 4
+  store i32 2, i32* %3, align 4
+  store i32 3, i32* %4, align 4
+  store i32 4, i32* %5, align 4
+  br label %15
+
+  store i32 1, i32* %4, align 4
+  br label %15
+
+  ret i32 0
+}
+
+define dso_local i32 @main() #0 {
+  %1 = alloca i32, align 4
+  %2 = alloca i32, align 4
+  %3 = alloca i32, align 4
+  %4 = alloca i32, align 4
+  %5 = alloca i32, align 4
+
+  store i32 0, i32* %1, align 4
+  store i32 0, i32* @x, align 4
+  store i32 1, i32* %2, align 4
+  store i32 2, i32* %3, align 4
+  store i32 3, i32* %4, align 4
+  store i32 4, i32* %5, align 4
+  store i32 1, i32* @x, align 4
+  call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()
+  store i32 1, i32* %2, align 4
+  store i32 2, i32* %3, align 4
+  store i32 3, i32* %4, align 4
+  store i32 4, i32* %5, align 4
+  ret i32 0
+}
+
+attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" }
+; CHECK-LABEL: check_boundaries:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -32
+; CHECK-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
+; CHECK-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
+; CHECK-NEXT:    .cfi_offset ra, -4
+; CHECK-NEXT:    .cfi_offset s0, -8
+; CHECK-NEXT:    addi s0, sp, 32
+; CHECK-NEXT:    .cfi_def_cfa s0, 0
+; CHECK-NEXT:    sw zero, -12(s0)
+; CHECK-NEXT:    sw zero, -16(s0)
+; CHECK-NEXT:    addi a0, zero, 1
+; CHECK-NEXT:    beqz zero, .LBB0_3
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    sw a0, -24(s0)
+; CHECK-NEXT:    lw a0, -16(s0)
+; CHECK-NEXT:    beqz a0, .LBB0_4
+; CHECK-NEXT:  .LBB0_2:
+; CHECK-NEXT:    addi a0, zero, 1
+; CHECK-NEXT:    sw a0, -24(s0)
+; CHECK-NEXT:    j .LBB0_5
+; CHECK-NEXT:  .LBB0_3:
+; CHECK-NEXT:    call t0, OUTLINED_FUNCTION_0
+; CHECK-NEXT:    lw a0, -16(s0)
+; CHECK-NEXT:    bnez a0, .LBB0_2
+; CHECK-NEXT:  .LBB0_4:
+; CHECK-NEXT:    addi a0, zero, 1
+; CHECK-NEXT:    call t0, OUTLINED_FUNCTION_0
+; CHECK-NEXT:  .LBB0_5:
+; CHECK-NEXT:    mv a0, zero
+; CHECK-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
+; CHECK-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 32
+; CHECK-NEXT:    ret
+;
+; CHECK-LABEL: main:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -32
+; CHECK-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
+; CHECK-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
+; CHECK-NEXT:    .cfi_offset ra, -4
+; CHECK-NEXT:    .cfi_offset s0, -8
+; CHECK-NEXT:    addi s0, sp, 32
+; CHECK-NEXT:    .cfi_def_cfa s0, 0
+; CHECK-NEXT:    sw zero, -12(s0)
+; CHECK-NEXT:    lui a0, %hi(x)
+; CHECK-NEXT:    addi a1, zero, 1
+; CHECK-NEXT:    sw a1, -16(s0)
+; CHECK-NEXT:    addi a2, zero, 2
+; CHECK-NEXT:    sw a2, -20(s0)
+; CHECK-NEXT:    addi a3, zero, 3
+; CHECK-NEXT:    sw a3, -24(s0)
+; CHECK-NEXT:    addi a4, zero, 4
+; CHECK-NEXT:    sw a4, -28(s0)
+; CHECK-NEXT:    sw a1, %lo(x)(a0)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    sw a1, -16(s0)
+; CHECK-NEXT:    sw a2, -20(s0)
+; CHECK-NEXT:    sw a3, -24(s0)
+; CHECK-NEXT:    sw a4, -28(s0)
+; CHECK-NEXT:    mv a0, zero
+; CHECK-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
+; CHECK-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 32
+; CHECK-NEXT:    ret
+;
+; CHECK-LABEL: OUTLINED_FUNCTION_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    sw a0, -16(s0)
+; CHECK-NEXT:    addi a0, zero, 2
+; CHECK-NEXT:    sw a0, -20(s0)
+; CHECK-NEXT:    addi a0, zero, 3
+; CHECK-NEXT:    sw a0, -24(s0)
+; CHECK-NEXT:    addi a0, zero, 4
+; CHECK-NEXT:    sw a0, -28(s0)
+; CHECK-NEXT:    jr t0

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/riscv_generated_funcs.ll.nogenerated.expected

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -enable-machine-outliner -mtriple=riscv32-unknown-linux < %s | FileCheck %s
+
+@x = global i32 0, align 4
+
+define dso_local i32 @check_boundaries() #0 {
+; CHECK-LABEL: check_boundaries:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -32
+; CHECK-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
+; CHECK-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
+; CHECK-NEXT:    .cfi_offset ra, -4
+; CHECK-NEXT:    .cfi_offset s0, -8
+; CHECK-NEXT:    addi s0, sp, 32
+; CHECK-NEXT:    .cfi_def_cfa s0, 0
+; CHECK-NEXT:    sw zero, -12(s0)
+; CHECK-NEXT:    sw zero, -16(s0)
+; CHECK-NEXT:    addi a0, zero, 1
+; CHECK-NEXT:    beqz zero, .LBB0_3
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    sw a0, -24(s0)
+; CHECK-NEXT:    lw a0, -16(s0)
+; CHECK-NEXT:    beqz a0, .LBB0_4
+; CHECK-NEXT:  .LBB0_2:
+; CHECK-NEXT:    addi a0, zero, 1
+; CHECK-NEXT:    sw a0, -24(s0)
+; CHECK-NEXT:    j .LBB0_5
+; CHECK-NEXT:  .LBB0_3:
+; CHECK-NEXT:    call t0, OUTLINED_FUNCTION_0
+; CHECK-NEXT:    lw a0, -16(s0)
+; CHECK-NEXT:    bnez a0, .LBB0_2
+; CHECK-NEXT:  .LBB0_4:
+; CHECK-NEXT:    addi a0, zero, 1
+; CHECK-NEXT:    call t0, OUTLINED_FUNCTION_0
+; CHECK-NEXT:  .LBB0_5:
+; CHECK-NEXT:    mv a0, zero
+; CHECK-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
+; CHECK-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 32
+; CHECK-NEXT:    ret
+  %1 = alloca i32, align 4
+  %2 = alloca i32, align 4
+  %3 = alloca i32, align 4
+  %4 = alloca i32, align 4
+  %5 = alloca i32, align 4
+  store i32 0, i32* %1, align 4
+  store i32 0, i32* %2, align 4
+  %6 = load i32, i32* %2, align 4
+  %7 = icmp ne i32 %6, 0
+  br i1 %7, label %9, label %8
+
+  store i32 1, i32* %2, align 4
+  store i32 2, i32* %3, align 4
+  store i32 3, i32* %4, align 4
+  store i32 4, i32* %5, align 4
+  br label %10
+
+  store i32 1, i32* %4, align 4
+  br label %10
+
+  %11 = load i32, i32* %2, align 4
+  %12 = icmp ne i32 %11, 0
+  br i1 %12, label %14, label %13
+
+  store i32 1, i32* %2, align 4
+  store i32 2, i32* %3, align 4
+  store i32 3, i32* %4, align 4
+  store i32 4, i32* %5, align 4
+  br label %15
+
+  store i32 1, i32* %4, align 4
+  br label %15
+
+  ret i32 0
+}
+
+define dso_local i32 @main() #0 {
+; CHECK-LABEL: main:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -32
+; CHECK-NEXT:    .cfi_def_cfa_offset 32
+; CHECK-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
+; CHECK-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
+; CHECK-NEXT:    .cfi_offset ra, -4
+; CHECK-NEXT:    .cfi_offset s0, -8
+; CHECK-NEXT:    addi s0, sp, 32
+; CHECK-NEXT:    .cfi_def_cfa s0, 0
+; CHECK-NEXT:    sw zero, -12(s0)
+; CHECK-NEXT:    lui a0, %hi(x)
+; CHECK-NEXT:    addi a1, zero, 1
+; CHECK-NEXT:    sw a1, -16(s0)
+; CHECK-NEXT:    addi a2, zero, 2
+; CHECK-NEXT:    sw a2, -20(s0)
+; CHECK-NEXT:    addi a3, zero, 3
+; CHECK-NEXT:    sw a3, -24(s0)
+; CHECK-NEXT:    addi a4, zero, 4
+; CHECK-NEXT:    sw a4, -28(s0)
+; CHECK-NEXT:    sw a1, %lo(x)(a0)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    sw a1, -16(s0)
+; CHECK-NEXT:    sw a2, -20(s0)
+; CHECK-NEXT:    sw a3, -24(s0)
+; CHECK-NEXT:    sw a4, -28(s0)
+; CHECK-NEXT:    mv a0, zero
+; CHECK-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
+; CHECK-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
+; CHECK-NEXT:    addi sp, sp, 32
+; CHECK-NEXT:    ret
+  %1 = alloca i32, align 4
+  %2 = alloca i32, align 4
+  %3 = alloca i32, align 4
+  %4 = alloca i32, align 4
+  %5 = alloca i32, align 4
+
+  store i32 0, i32* %1, align 4
+  store i32 0, i32* @x, align 4
+  store i32 1, i32* %2, align 4
+  store i32 2, i32* %3, align 4
+  store i32 3, i32* %4, align 4
+  store i32 4, i32* %5, align 4
+  store i32 1, i32* @x, align 4
+  call void asm sideeffect "", "~{memory},~{dirflag},~{fpsr},~{flags}"()
+  store i32 1, i32* %2, align 4
+  store i32 2, i32* %3, align 4
+  store i32 3, i32* %4, align 4
+  store i32 4, i32* %5, align 4
+  ret i32 0
+}
+
+attributes #0 = { noredzone nounwind ssp uwtable "frame-pointer"="all" }

llvm/test/tools/UpdateTestChecks/update_llc_test_checks/riscv_generated_funcs.test

+# REQUIRES: riscv-registered-target
+
+## Check that generated functions are included.
+# RUN: cp -f %S/Inputs/riscv_generated_funcs.ll %t.ll && %update_llc_test_checks --include-generated-funcs %t.ll
+# RUN: diff -u %t.ll %S/Inputs/riscv_generated_funcs.ll.generated.expected
+
+## Check that running the script again does not change the result:
+# RUN: %update_llc_test_checks --include-generated-funcs %t.ll
+# RUN: diff -u %t.ll %S/Inputs/riscv_generated_funcs.ll.generated.expected
+
+## Check that generated functions are not included.
+# RUN: cp -f %S/Inputs/riscv_generated_funcs.ll %t.ll && %update_llc_test_checks %t.ll
+# RUN: diff -u %t.ll %S/Inputs/riscv_generated_funcs.ll.nogenerated.expected
+
+## Check that running the script again does not change the result:
+# RUN: %update_llc_test_checks %t.ll
+# RUN: diff -u %t.ll %S/Inputs/riscv_generated_funcs.ll.nogenerated.expected