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Differential D95035

[GlobalISel] LegalizerHelper - Extract widenScalarAddoSubo method
ClosedPublic

Authored by porglezomp on Jan 20 2021, 4:55 AM.

Details

Reviewers
paquette
aemerson
Commits
rGc9466ede7e87: Revert "Revert "[GlobalISel] LegalizerHelper - Extract widenScalarAddoSubo…
rG2bb92bf451d7: [GlobalISel] LegalizerHelper - Extract widenScalarAddoSubo method
Summary

The widenScalar implementation for signed and unsigned overflowing
operations were very similar: both are checked by truncating the result
and then re-sign/zero-extending it and checking that it matches the
computed operation.

Using a truncate + zero-extend for the unsigned case instead of manually
producing the AND instruction like before leads to an extra copy
instruction during legalization, but this should be harmless.

Diff Detail

Unit TestsFailed

TimeTest
2,000 msx64 debian > libarcher.races::lock-unrelated.c

Event Timeline

porglezomp created this revision.Jan 20 2021, 4:55 AM
Herald added subscribers: hiraditya, kristof.beyls, rovka. · View Herald TranscriptJan 20 2021, 4:55 AM
porglezomp requested review of this revision.Jan 20 2021, 4:55 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 20 2021, 4:55 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
Harbormaster completed remote builds in B85870: Diff 317842.Jan 20 2021, 4:55 AM
porglezomp added a parent revision: D95034: [AArch64][GlobalISel] Implement widenScalar for signed overflow.Jan 20 2021, 4:55 AM
paquette accepted this revision.Jan 20 2021, 9:44 AM

LGTM

This revision is now accepted and ready to land.Jan 20 2021, 9:44 AM
aemerson added a comment.Jan 21 2021, 11:45 PM

Applying this patch to trunk on top of the previous two tests doesn't pass the test suite.

Failed Tests (5):
  LLVM-Unit :: CodeGen/GlobalISel/./GlobalISelTests/AArch64GISelMITest.WidenUADDO
  LLVM-Unit :: CodeGen/GlobalISel/./GlobalISelTests/AArch64GISelMITest.WidenUSUBO
  LLVM :: CodeGen/AArch64/legalize-uaddo.mir
  LLVM :: CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir
  LLVM :: CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir

Could you double check and update?

porglezomp updated this revision to Diff 318600.Jan 22 2021, 11:57 AM

Update tests for changed legalization

Herald added subscribers: kerbowa, nhaehnle, jvesely. · View Herald TranscriptJan 22 2021, 11:57 AM
Harbormaster completed remote builds in B86336: Diff 318600.Jan 22 2021, 1:22 PM
This revision was landed with ongoing or failed builds.Jan 22 2021, 2:09 PM
Closed by commit rG2bb92bf451d7: [GlobalISel] LegalizerHelper - Extract widenScalarAddoSubo method (authored by porglezomp, committed by aemerson). · Explain Why
This revision was automatically updated to reflect the committed changes.
aemerson added a commit: rG2bb92bf451d7: [GlobalISel] LegalizerHelper - Extract widenScalarAddoSubo method.
hctim added a reverting change: rG554b3211fefd: Revert "[GlobalISel] LegalizerHelper - Extract widenScalarAddoSubo method".Jan 22 2021, 2:32 PM
porglezomp reopened this revision.Jan 22 2021, 7:04 PM

The buildbot with the UBSan tests passed for the first commit in this stack, so I think this should be safe to re-land http://lab.llvm.org:8011/#/builders/77/builds/3112

This revision is now accepted and ready to land.Jan 22 2021, 7:04 PM
porglezomp added a child revision: D95323: [Test][AArch64] Move overflow add/sub tests to their own file. NFC.Jan 24 2021, 5:53 PM
Closed by commit rGc9466ede7e87: Revert "Revert "[GlobalISel] LegalizerHelper - Extract widenScalarAddoSubo… (authored by hctim, committed by aemerson). · Explain WhyJan 25 2021, 4:22 PM
This revision was automatically updated to reflect the committed changes.
aemerson added a commit: rGc9466ede7e87: Revert "Revert "[GlobalISel] LegalizerHelper - Extract widenScalarAddoSubo….

Revision Contents

PathSize
llvm/
include/
llvm/
CodeGen/
GlobalISel/
6 lines
lib/
CodeGen/
GlobalISel/
72 lines
test/
CodeGen/
AArch64/
GlobalISel/
3 lines
3 lines
5 lines
AMDGPU/
GlobalISel/
14 lines
14 lines
unittests/
CodeGen/
GlobalISel/
90 lines

Diff 318600

llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h

Show First 20 Lines • Show All 164 Lines • ▼ Show 20 Linesprivate:
LegalizeResult LegalizeResult
widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx, LLT WideTy); widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
LegalizeResult LegalizeResult
widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx, LLT WideTy); widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
LegalizeResult LegalizeResult
widenScalarExtract(MachineInstr &MI, unsigned TypeIdx, LLT WideTy); widenScalarExtract(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
LegalizeResult LegalizeResult
widenScalarInsert(MachineInstr &MI, unsigned TypeIdx, LLT WideTy); widenScalarInsert(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
LegalizeResult LegalizeResult widenScalarAddoSubo(MachineInstr &MI, unsigned TypeIdx,
widenScalarAddSubShlSat(MachineInstr &MI, unsigned TypeIdx, LLT WideTy); LLT WideTy);
LegalizeResult widenScalarAddSubShlSat(MachineInstr &MI, unsigned TypeIdx,
LLT WideTy);
/// Helper function to split a wide generic register into bitwise blocks with /// Helper function to split a wide generic register into bitwise blocks with
/// the given Type (which implies the number of blocks needed). The generic /// the given Type (which implies the number of blocks needed). The generic
/// registers created are appended to Ops, starting at bit 0 of Reg. /// registers created are appended to Ops, starting at bit 0 of Reg.
void extractParts(Register Reg, LLT Ty, int NumParts, void extractParts(Register Reg, LLT Ty, int NumParts,
SmallVectorImpl<Register> &VRegs); SmallVectorImpl<Register> &VRegs);
/// Version which handles irregular splits. /// Version which handles irregular splits.
▲ Show 20 Lines • Show All 213 Lines • Show Last 20 Lines

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Show First 20 Lines • Show All 1,752 Lines • ▼ Show 20 LinesLegalizerHelper::widenScalarInsert(MachineInstr &MI, unsigned TypeIdx,
Observer.changingInstr(MI); Observer.changingInstr(MI);
widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
widenScalarDst(MI, WideTy); widenScalarDst(MI, WideTy);
Observer.changedInstr(MI); Observer.changedInstr(MI);
return Legalized; return Legalized;
} }
LegalizerHelper::LegalizeResult LegalizerHelper::LegalizeResult
LegalizerHelper::widenScalarAddoSubo(MachineInstr &MI, unsigned TypeIdx,
LLT WideTy) {
if (TypeIdx == 1)
return UnableToLegalize; // TODO
unsigned Op = MI.getOpcode();
unsigned Opcode = Op == TargetOpcode::G_UADDO || Op == TargetOpcode::G_SADDO
? TargetOpcode::G_ADD
: TargetOpcode::G_SUB;
unsigned ExtOpcode =
Op == TargetOpcode::G_UADDO || Op == TargetOpcode::G_USUBO
? TargetOpcode::G_ZEXT
: TargetOpcode::G_SEXT;
auto LHSExt = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MI.getOperand(2)});
auto RHSExt = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MI.getOperand(3)});
// Do the arithmetic in the larger type.
auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSExt, RHSExt});
LLT OrigTy = MRI.getType(MI.getOperand(0).getReg());
auto TruncOp = MIRBuilder.buildTrunc(OrigTy, NewOp);
auto ExtOp = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {TruncOp});
// There is no overflow if the ExtOp is the same as NewOp.
MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1), NewOp, ExtOp);
// Now trunc the NewOp to the original result.
MIRBuilder.buildTrunc(MI.getOperand(0), NewOp);
MI.eraseFromParent();
return Legalized;
}
LegalizerHelper::LegalizeResult
LegalizerHelper::widenScalarAddSubShlSat(MachineInstr &MI, unsigned TypeIdx, LegalizerHelper::widenScalarAddSubShlSat(MachineInstr &MI, unsigned TypeIdx,
LLT WideTy) { LLT WideTy) {
bool IsSigned = MI.getOpcode() == TargetOpcode::G_SADDSAT || bool IsSigned = MI.getOpcode() == TargetOpcode::G_SADDSAT ||
MI.getOpcode() == TargetOpcode::G_SSUBSAT || MI.getOpcode() == TargetOpcode::G_SSUBSAT ||
MI.getOpcode() == TargetOpcode::G_SSHLSAT; MI.getOpcode() == TargetOpcode::G_SSHLSAT;
bool IsShift = MI.getOpcode() == TargetOpcode::G_SSHLSAT || bool IsShift = MI.getOpcode() == TargetOpcode::G_SSHLSAT ||
MI.getOpcode() == TargetOpcode::G_USHLSAT; MI.getOpcode() == TargetOpcode::G_USHLSAT;
// We can convert this to: // We can convert this to:
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines case TargetOpcode::G_EXTRACT:
return widenScalarExtract(MI, TypeIdx, WideTy); return widenScalarExtract(MI, TypeIdx, WideTy);
case TargetOpcode::G_INSERT: case TargetOpcode::G_INSERT:
return widenScalarInsert(MI, TypeIdx, WideTy); return widenScalarInsert(MI, TypeIdx, WideTy);
case TargetOpcode::G_MERGE_VALUES: case TargetOpcode::G_MERGE_VALUES:
return widenScalarMergeValues(MI, TypeIdx, WideTy); return widenScalarMergeValues(MI, TypeIdx, WideTy);
case TargetOpcode::G_UNMERGE_VALUES: case TargetOpcode::G_UNMERGE_VALUES:
return widenScalarUnmergeValues(MI, TypeIdx, WideTy); return widenScalarUnmergeValues(MI, TypeIdx, WideTy);
case TargetOpcode::G_SADDO: case TargetOpcode::G_SADDO:
case TargetOpcode::G_SSUBO: { case TargetOpcode::G_SSUBO:
if (TypeIdx == 1)
return UnableToLegalize; // TODO
auto LHSExt = MIRBuilder.buildSExt(WideTy, MI.getOperand(2));
auto RHSExt = MIRBuilder.buildSExt(WideTy, MI.getOperand(3));
unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SADDO
? TargetOpcode::G_ADD
: TargetOpcode::G_SUB;
auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSExt, RHSExt});
LLT OrigTy = MRI.getType(MI.getOperand(0).getReg());
auto TruncOp = MIRBuilder.buildTrunc(OrigTy, NewOp);
auto ExtOp = MIRBuilder.buildSExt(WideTy, TruncOp);
// There is no overflow if the re-extended result is the same as NewOp.
MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1), NewOp, ExtOp);
// Now trunc the NewOp to the original result.
MIRBuilder.buildTrunc(MI.getOperand(0), NewOp);
MI.eraseFromParent();
return Legalized;
}
case TargetOpcode::G_UADDO: case TargetOpcode::G_UADDO:
case TargetOpcode::G_USUBO: { case TargetOpcode::G_USUBO:
if (TypeIdx == 1) return widenScalarAddoSubo(MI, TypeIdx, WideTy);
return UnableToLegalize; // TODO
auto LHSZext = MIRBuilder.buildZExt(WideTy, MI.getOperand(2));
auto RHSZext = MIRBuilder.buildZExt(WideTy, MI.getOperand(3));
unsigned Opcode = MI.getOpcode() == TargetOpcode::G_UADDO
? TargetOpcode::G_ADD
: TargetOpcode::G_SUB;
// Do the arithmetic in the larger type.
auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSZext, RHSZext});
LLT OrigTy = MRI.getType(MI.getOperand(0).getReg());
APInt Mask =
APInt::getLowBitsSet(WideTy.getSizeInBits(), OrigTy.getSizeInBits());
auto AndOp = MIRBuilder.buildAnd(
WideTy, NewOp, MIRBuilder.buildConstant(WideTy, Mask));
// There is no overflow if the AndOp is the same as NewOp.
MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1), NewOp, AndOp);
// Now trunc the NewOp to the original result.
MIRBuilder.buildTrunc(MI.getOperand(0), NewOp);
MI.eraseFromParent();
return Legalized;
}
case TargetOpcode::G_SADDSAT: case TargetOpcode::G_SADDSAT:
case TargetOpcode::G_SSUBSAT: case TargetOpcode::G_SSUBSAT:
case TargetOpcode::G_SSHLSAT: case TargetOpcode::G_SSHLSAT:
case TargetOpcode::G_UADDSAT: case TargetOpcode::G_UADDSAT:
case TargetOpcode::G_USUBSAT: case TargetOpcode::G_USUBSAT:
case TargetOpcode::G_USHLSAT: case TargetOpcode::G_USHLSAT:
return widenScalarAddSubShlSat(MI, TypeIdx, WideTy); return widenScalarAddSubShlSat(MI, TypeIdx, WideTy);
case TargetOpcode::G_CTTZ: case TargetOpcode::G_CTTZ:
▲ Show 20 Lines • Show All 4,399 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir

Show First 20 Lines • Show All 81 Lines • ▼ Show 20 Lines bb.0.entry:
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]] ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]] ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]] ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD]](s32) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD]](s32)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32) ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32)
; CHECK: $x0 = COPY [[ANYEXT]](s64) ; CHECK: $x0 = COPY [[ANYEXT]](s64)
; CHECK: $x1 = COPY [[ANYEXT1]](s64) ; CHECK: $x1 = COPY [[ANYEXT1]](s64)
%0:_(s64) = COPY $x0 %0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1 %1:_(s64) = COPY $x1
%2:_(s8) = G_TRUNC %0(s64) %2:_(s8) = G_TRUNC %0(s64)
▲ Show 20 Lines • Show All 216 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir

Show First 20 Lines • Show All 101 Lines • ▼ Show 20 Lines bb.0.entry:
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1 ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64) ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]] ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]] ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]] ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD]](s32) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD]](s32)
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32) ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32)
; CHECK: $x0 = COPY [[ANYEXT]](s64) ; CHECK: $x0 = COPY [[ANYEXT]](s64)
; CHECK: $x1 = COPY [[ANYEXT1]](s64) ; CHECK: $x1 = COPY [[ANYEXT1]](s64)
%0:_(s64) = COPY $x0 %0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1 %1:_(s64) = COPY $x1
%2:_(s8) = G_TRUNC %0(s64) %2:_(s8) = G_TRUNC %0(s64)
▲ Show 20 Lines • Show All 57 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/legalize-uaddo.mir

Show All 12 Lines bb.1:
; CHECK-LABEL: name: legalize-uaddo ; CHECK-LABEL: name: legalize-uaddo
; CHECK: liveins: $x0 ; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[C1]] ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[C1]]
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]] ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[AND1]] ; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[AND1]]
; CHECK: [[COPY2:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1 ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32) ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32)
; CHECK: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C2]] ; CHECK: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C2]]
; CHECK: $x0 = COPY [[AND2]](s64) ; CHECK: $x0 = COPY [[AND2]](s64)
; CHECK: RET_ReallyLR implicit $x0 ; CHECK: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0 %0:_(s64) = COPY $x0
%4:_(s16) = G_CONSTANT i16 2 %4:_(s16) = G_CONSTANT i16 2
%1:_(s16) = G_TRUNC %0(s64) %1:_(s16) = G_TRUNC %0(s64)
%2:_(s16), %3:_(s1) = G_UADDO %1, %4 %2:_(s16), %3:_(s1) = G_UADDO %1, %4
%5:_(s64) = G_ZEXT %3(s1) %5:_(s64) = G_ZEXT %3(s1)
$x0 = COPY %5(s64) $x0 = COPY %5(s64)
RET_ReallyLR implicit $x0 RET_ReallyLR implicit $x0
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir

Show All 31 Lines bb.0:
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]] ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]] ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1) ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
; CHECK: $vgpr0 = COPY [[AND3]](s32) ; CHECK: $vgpr0 = COPY [[AND3]](s32)
; CHECK: $vgpr1 = COPY [[ZEXT]](s32) ; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s7) = G_TRUNC %0 %2:_(s7) = G_TRUNC %0
%3:_(s7) = G_TRUNC %1 %3:_(s7) = G_TRUNC %1
Show All 14 Lines bb.0:
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]] ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32) ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]] ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1) ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
; CHECK: $vgpr0 = COPY [[AND3]](s32) ; CHECK: $vgpr0 = COPY [[AND3]](s32)
; CHECK: $vgpr1 = COPY [[ZEXT]](s32) ; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0 %2:_(s16) = G_TRUNC %0
%3:_(s16) = G_TRUNC %1 %3:_(s16) = G_TRUNC %1
▲ Show 20 Lines • Show All 289 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir

Show All 31 Lines bb.0:
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 127
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]] ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]] ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1) ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
; CHECK: $vgpr0 = COPY [[AND3]](s32) ; CHECK: $vgpr0 = COPY [[AND3]](s32)
; CHECK: $vgpr1 = COPY [[ZEXT]](s32) ; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s7) = G_TRUNC %0 %2:_(s7) = G_TRUNC %0
%3:_(s7) = G_TRUNC %1 %3:_(s7) = G_TRUNC %1
Show All 14 Lines bb.0:
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]] ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) ; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]] ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]] ; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32) ; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]] ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1) ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
; CHECK: $vgpr0 = COPY [[AND3]](s32) ; CHECK: $vgpr0 = COPY [[AND3]](s32)
; CHECK: $vgpr1 = COPY [[ZEXT]](s32) ; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
%0:_(s32) = COPY $vgpr0 %0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1 %1:_(s32) = COPY $vgpr1
%2:_(s16) = G_TRUNC %0 %2:_(s16) = G_TRUNC %0
%3:_(s16) = G_TRUNC %1 %3:_(s16) = G_TRUNC %1
▲ Show 20 Lines • Show All 311 Lines • Show Last 20 Lines

llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp

Show First 20 Lines • Show All 583 Lines • ▼ Show 20 LinesTEST_F(AArch64GISelMITest, WidenUADDO) {
EXPECT_TRUE(Helper.widenScalar(*MIBUAddO, 0, s16) == EXPECT_TRUE(Helper.widenScalar(*MIBUAddO, 0, s16) ==
LegalizerHelper::LegalizeResult::Legalized); LegalizerHelper::LegalizeResult::Legalized);
auto CheckStr = R"( auto CheckStr = R"(
CHECK: [[Trunc:%[0-9]+]]:_(s8) = G_TRUNC CHECK: [[Trunc:%[0-9]+]]:_(s8) = G_TRUNC
CHECK: [[LHS:%[0-9]+]]:_(s16) = G_ZEXT [[Trunc]] CHECK: [[LHS:%[0-9]+]]:_(s16) = G_ZEXT [[Trunc]]
CHECK: [[RHS:%[0-9]+]]:_(s16) = G_ZEXT [[Trunc]] CHECK: [[RHS:%[0-9]+]]:_(s16) = G_ZEXT [[Trunc]]
CHECK: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[LHS]]:_, [[RHS]]:_ CHECK: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[LHS]]:_, [[RHS]]:_
CHECK: [[CST:%[0-9]+]]:_(s16) = G_CONSTANT i16 255 CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[ADD]]
CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[ADD]]:_, [[CST]]:_ CHECK: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[TRUNC1]]
CHECK: G_ICMP intpred(ne), [[ADD]]:_(s16), [[AND]]:_ CHECK: G_ICMP intpred(ne), [[ADD]]:_(s16), [[ZEXT]]:_
CHECK: G_TRUNC [[ADD]] CHECK: G_TRUNC [[ADD]]
)"; )";
// Check // Check
EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF; EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
} }
// USUBO widening. // USUBO widening.
Show All 20 LinesTEST_F(AArch64GISelMITest, WidenUSUBO) {
EXPECT_TRUE(Helper.widenScalar(*MIBUSUBO, 0, s16) == EXPECT_TRUE(Helper.widenScalar(*MIBUSUBO, 0, s16) ==
LegalizerHelper::LegalizeResult::Legalized); LegalizerHelper::LegalizeResult::Legalized);
auto CheckStr = R"( auto CheckStr = R"(
CHECK: [[Trunc:%[0-9]+]]:_(s8) = G_TRUNC CHECK: [[Trunc:%[0-9]+]]:_(s8) = G_TRUNC
CHECK: [[LHS:%[0-9]+]]:_(s16) = G_ZEXT [[Trunc]] CHECK: [[LHS:%[0-9]+]]:_(s16) = G_ZEXT [[Trunc]]
CHECK: [[RHS:%[0-9]+]]:_(s16) = G_ZEXT [[Trunc]] CHECK: [[RHS:%[0-9]+]]:_(s16) = G_ZEXT [[Trunc]]
CHECK: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[LHS]]:_, [[RHS]]:_ CHECK: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[LHS]]:_, [[RHS]]:_
CHECK: [[CST:%[0-9]+]]:_(s16) = G_CONSTANT i16 255 CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[SUB]]
CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[SUB]]:_, [[CST]]:_ CHECK: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[TRUNC1]]
CHECK: G_ICMP intpred(ne), [[SUB]]:_(s16), [[AND]]:_ CHECK: G_ICMP intpred(ne), [[SUB]]:_(s16), [[ZEXT]]:_
CHECK: G_TRUNC [[SUB]]
)";
// Check
EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
}
// SADDO widening.
TEST_F(AArch64GISelMITest, WidenSADDO) {
setUp();
if (!TM)
return;
// Declare your legalization info
DefineLegalizerInfo(A, {
getActionDefinitionsBuilder(G_ADD).legalFor({{s16, s16}});
});
// Build
// Trunc it to s8.
LLT s8{LLT::scalar(8)};
Lint: Pre-merge checks
Inline Actions

clang-tidy: warning: invalid case style for variable 's8' [readability-identifier-naming]
not useful

Lint: Pre-merge checks: clang-tidy: warning: invalid case style for variable 's8' [readability-identifier-naming]…
LLT s16{LLT::scalar(16)};
Lint: Pre-merge checks
Inline Actions

clang-tidy: warning: invalid case style for variable 's16' [readability-identifier-naming]
not useful

Lint: Pre-merge checks: clang-tidy: warning: invalid case style for variable 's16' [readability-identifier-naming]…
auto MIBTrunc = B.buildTrunc(s8, Copies[0]);
unsigned CarryReg = MRI->createGenericVirtualRegister(LLT::scalar(1));
Lint: Pre-merge checks
Inline Actions

clang-tidy: warning: variable 'CarryReg' declared as 'unsigned int'; use 'Register' instead [llvm-prefer-register-over-unsigned]
not useful

Lint: Pre-merge checks: clang-tidy: warning: variable 'CarryReg' declared as 'unsigned int'; use 'Register' instead…
auto MIBSAddO =
B.buildInstr(TargetOpcode::G_SADDO, {s8, CarryReg}, {MIBTrunc, MIBTrunc});
AInfo Info(MF->getSubtarget());
DummyGISelObserver Observer;
LegalizerHelper Helper(*MF, Info, Observer, B);
EXPECT_TRUE(Helper.widenScalar(*MIBSAddO, 0, s16) ==
LegalizerHelper::LegalizeResult::Legalized);
auto CheckStr = R"(
Lint: Pre-merge checks
Inline Actions

clang-tidy: warning: 'auto CheckStr' can be declared as 'const auto *CheckStr' [llvm-qualified-auto]
not useful

Lint: Pre-merge checks: clang-tidy: warning: 'auto CheckStr' can be declared as 'const auto *CheckStr' [llvm-qualified…
CHECK: [[Trunc:%[0-9]+]]:_(s8) = G_TRUNC
CHECK: [[LHS:%[0-9]+]]:_(s16) = G_SEXT [[Trunc]]
CHECK: [[RHS:%[0-9]+]]:_(s16) = G_SEXT [[Trunc]]
CHECK: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[LHS]]:_, [[RHS]]:_
CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[ADD]]
CHECK: [[SEXT:%[0-9]+]]:_(s16) = G_SEXT [[TRUNC1]]
CHECK: G_ICMP intpred(ne), [[ADD]]:_(s16), [[SEXT]]:_
CHECK: G_TRUNC [[ADD]]
)";
// Check
EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
}
// SSUBO widening.
TEST_F(AArch64GISelMITest, WidenSSUBO) {
setUp();
if (!TM)
return;
// Declare your legalization info
DefineLegalizerInfo(A, {
getActionDefinitionsBuilder(G_SUB).legalFor({{s16, s16}});
});
// Build
// Trunc it to s8.
LLT s8{LLT::scalar(8)};
Lint: Pre-merge checks
Inline Actions

clang-tidy: warning: invalid case style for variable 's8' [readability-identifier-naming]
not useful

Lint: Pre-merge checks: clang-tidy: warning: invalid case style for variable 's8' [readability-identifier-naming]…
LLT s16{LLT::scalar(16)};
Lint: Pre-merge checks
Inline Actions

clang-tidy: warning: invalid case style for variable 's16' [readability-identifier-naming]
not useful

Lint: Pre-merge checks: clang-tidy: warning: invalid case style for variable 's16' [readability-identifier-naming]…
auto MIBTrunc = B.buildTrunc(s8, Copies[0]);
unsigned CarryReg = MRI->createGenericVirtualRegister(LLT::scalar(1));
Lint: Pre-merge checks
Inline Actions

clang-tidy: warning: variable 'CarryReg' declared as 'unsigned int'; use 'Register' instead [llvm-prefer-register-over-unsigned]
not useful

Lint: Pre-merge checks: clang-tidy: warning: variable 'CarryReg' declared as 'unsigned int'; use 'Register' instead…
auto MIBSSUBO =
B.buildInstr(TargetOpcode::G_SSUBO, {s8, CarryReg}, {MIBTrunc, MIBTrunc});
AInfo Info(MF->getSubtarget());
DummyGISelObserver Observer;
LegalizerHelper Helper(*MF, Info, Observer, B);
EXPECT_TRUE(Helper.widenScalar(*MIBSSUBO, 0, s16) ==
LegalizerHelper::LegalizeResult::Legalized);
auto CheckStr = R"(
Lint: Pre-merge checks
Inline Actions

clang-tidy: warning: 'auto CheckStr' can be declared as 'const auto *CheckStr' [llvm-qualified-auto]
not useful

Lint: Pre-merge checks: clang-tidy: warning: 'auto CheckStr' can be declared as 'const auto *CheckStr' [llvm-qualified…
CHECK: [[Trunc:%[0-9]+]]:_(s8) = G_TRUNC
CHECK: [[LHS:%[0-9]+]]:_(s16) = G_SEXT [[Trunc]]
CHECK: [[RHS:%[0-9]+]]:_(s16) = G_SEXT [[Trunc]]
CHECK: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[LHS]]:_, [[RHS]]:_
CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[SUB]]
CHECK: [[SEXT:%[0-9]+]]:_(s16) = G_SEXT [[TRUNC1]]
CHECK: G_ICMP intpred(ne), [[SUB]]:_(s16), [[SEXT]]:_
CHECK: G_TRUNC [[SUB]] CHECK: G_TRUNC [[SUB]]
)"; )";
// Check // Check
EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF; EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
} }
TEST_F(AArch64GISelMITest, FewerElementsAnd) { TEST_F(AArch64GISelMITest, FewerElementsAnd) {
▲ Show 20 Lines • Show All 2,541 Lines • Show Last 20 Lines