[P10] [Power PC] Exploiting new load rightmost vector element instructions.

[Conanap]

Summary

This pull request implements patterns to exploit the load rightmost vector
element instructions for loading element 0 on little endian PowerPC subtargets
into v8i16 and v16i8 vector registers for i16 and i8 data types.

[amyk]

llvm/lib/Target/PowerPC/PPCInstrVSX.td

3940

nit: End sentences with a period.

3941

Might be a silly question, but can you clarify the "faux equivalent pattern" part?
Also a small nit, maybe end the sentence here and start the next sentence with, "The NoP10Vector predicate..."

llvm/test/CodeGen/PowerPC/load-rightmost-vector-elt.ll

8

Add P9 run line, too?

[Conanap]

Updated a comment and a test case

[amyk]

I think this LGTM aside from the minor nit on the test case. I am OK with it being updated on the commit.

llvm/test/CodeGen/PowerPC/load-rightmost-vector-elt.ll

13

For the P9 run lines, you can probably do just one CHECK-P9 (or check-prefixes if needed?) so we don't have double of the same P9 checks.

[nemanjai]

llvm/lib/Target/PowerPC/PPCInstrVSX.td

3954

The patterns appear to be the same. Why do we split this out into LE/BE if the patterns are endianness neutral? If they are the same, merge them into a single block that doesn't have an endianness predicate.

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

let AddedComplexity = 400, Predicates = [IsISA3_1, IsLittleEndian] in {
   def : Pat<(store (i32 (extractelt v4i32:$src, 0)), xoaddr:$dst),
             (STXVRWX $src, xoaddr:$dst)>;
   def : Pat<(store (f32 (extractelt v4f32:$src, 0)), xoaddr:$dst),
             (STXVRWX $src, xoaddr:$dst)>;
   def : Pat<(store (i64 (extractelt v2i64:$src, 0)), xoaddr:$dst),
             (STXVRDX $src, xoaddr:$dst)>;
   def : Pat<(store (f64 (extractelt v2f64:$src, 0)), xoaddr:$dst),
             (STXVRDX $src, xoaddr:$dst)>;
- }
+  // Load element 0 of a VSX register to memory
+  def : Pat<(v8i16 (scalar_to_vector (i32 (extloadi16 xoaddr:$src)))),
+            (v8i16 (COPY_TO_REGCLASS (LXVRHX xoaddr:$src), VSRC))>;
+  def : Pat<(v16i8 (scalar_to_vector (i32 (extloadi8 xoaddr:$src)))),
+            (v16i8 (COPY_TO_REGCLASS (LXVRBX xoaddr:$src), VSRC))>;
 
 class xxevalPattern <dag pattern, bits<8> imm> :
   Pat<(v4i32 pattern), (XXEVAL $vA, $vB, $vC, imm)> {}
 
 let AddedComplexity = 400, Predicates = [PrefixInstrs] in {
  def : Pat<(v4i32 (build_vector i32immNonAllOneNonZero:$A,
                                 i32immNonAllOneNonZero:$A,
                                 i32immNonAllOneNonZero:$A,

llvm/lib/Target/PowerPC/PPCInstrVSX.td

 def IsBigEndian : Predicate<"!Subtarget->isLittleEndian()">;
 def IsPPC64 : Predicate<"Subtarget->isPPC64()">;
 def HasOnlySwappingMemOps : Predicate<"!Subtarget->hasP9Vector()">;
 def HasP8Vector : Predicate<"Subtarget->hasP8Vector()">;
 def HasDirectMove : Predicate<"Subtarget->hasDirectMove()">;
 def NoP9Vector : Predicate<"!Subtarget->hasP9Vector()">;
 def HasP9Vector : Predicate<"Subtarget->hasP9Vector()">;
 def NoP9Altivec : Predicate<"!Subtarget->hasP9Altivec()">;
+def NoP10Vector: Predicate<"!Subtarget->hasP10Vector()">;
 
 //--------------------- VSX-specific instruction formats ---------------------//
 // By default, all VSX instructions are to be selected over their Altivec
 // counter parts and they do not have unmodeled sideeffects.
 let AddedComplexity = 400, hasSideEffects = 0 in {
 multiclass XX3Form_Rcr<bits<6> opcode, bits<7> xo, string asmbase,
                     string asmstr, InstrItinClass itin, Intrinsic Int,
                     ValueType OutTy, ValueType InTy> {

 // [HasVSX, HasDirectMove]
 // [HasVSX, HasDirectMove, IsBigEndian]
 // [HasVSX, HasDirectMove, IsLittleEndian]
 // [HasVSX, HasDirectMove, NoP9Altivec, IsBigEndian, IsPPC64]
 // [HasVSX, HasDirectMove, NoP9Vector, IsBigEndian, IsPPC64]
 // [HasVSX, HasDirectMove, NoP9Altivec, IsLittleEndian]
 // [HasVSX, HasDirectMove, NoP9Vector, IsLittleEndian]
 // [HasVSX, HasP9Vector]
+// [HasVSX, HasP9Vector, NoP10Vector]
+// [HasVSX, HasP9Vector, IsBigEndian]
 // [HasVSX, HasP9Vector, IsBigEndian, IsPPC64]
 // [HasVSX, HasP9Vector, IsLittleEndian]
 // [HasVSX, HasP9Altivec]
 // [HasVSX, HasP9Altivec, IsBigEndian, IsPPC64]
 // [HasVSX, HasP9Altivec, IsLittleEndian]
 // [HasVSX, IsISA3_0, HasDirectMove, IsBigEndian, IsPPC64]
 // [HasVSX, IsISA3_0, HasDirectMove, IsLittleEndian]
 

 def : Pat<(nonQuadwOffsetStore v4i32:$rS, xoaddr:$dst),
           (STXVX $rS, xoaddr:$dst)>;
 def : Pat<(int_ppc_vsx_stxvw4x v4i32:$rS, xoaddr:$dst),
           (STXVX $rS, xoaddr:$dst)>;
 def : Pat<(int_ppc_vsx_stxvd2x v2f64:$rS, xoaddr:$dst),
           (STXVX $rS, xoaddr:$dst)>;
 
 // Build vectors from i8 loads
-defm : ScalToVecWPermute<v16i8, ScalarLoads.Li8,
-                         (VSPLTBs 7, (LXSIBZX xoaddr:$src)),
-                         (VSPLTBs 7, (LXSIBZX xoaddr:$src))>;
 defm : ScalToVecWPermute<v8i16, ScalarLoads.ZELi8,
                          (VSPLTHs 3, (LXSIBZX xoaddr:$src)),
                          (VSPLTHs 3, (LXSIBZX xoaddr:$src))>;
 defm : ScalToVecWPermute<v4i32, ScalarLoads.ZELi8,
                          (XXSPLTWs (LXSIBZX xoaddr:$src), 1),
                          (XXSPLTWs (LXSIBZX xoaddr:$src), 1)>;
 defm : ScalToVecWPermute<v2i64, ScalarLoads.ZELi8i64,
                          (XXPERMDIs (LXSIBZX xoaddr:$src), 0),
                          (XXPERMDIs (LXSIBZX xoaddr:$src), 0)>;
 defm : ScalToVecWPermute<v4i32, ScalarLoads.SELi8,
                          (XXSPLTWs (VEXTSB2Ws (LXSIBZX xoaddr:$src)), 1),
                          (XXSPLTWs (VEXTSB2Ws (LXSIBZX xoaddr:$src)), 1)>;
 defm : ScalToVecWPermute<v2i64, ScalarLoads.SELi8i64,
                          (XXPERMDIs (VEXTSB2Ds (LXSIBZX xoaddr:$src)), 0),
                          (XXPERMDIs (VEXTSB2Ds (LXSIBZX xoaddr:$src)), 0)>;
 
 // Build vectors from i16 loads
-defm : ScalToVecWPermute<v8i16, ScalarLoads.Li16,
-                         (VSPLTHs 3, (LXSIHZX xoaddr:$src)),
-                         (VSPLTHs 3, (LXSIHZX xoaddr:$src))>;
 defm : ScalToVecWPermute<v4i32, ScalarLoads.ZELi16,
                          (XXSPLTWs (LXSIHZX xoaddr:$src), 1),
                          (XXSPLTWs (LXSIHZX xoaddr:$src), 1)>;
 defm : ScalToVecWPermute<v2i64, ScalarLoads.ZELi16i64,
                          (XXPERMDIs (LXSIHZX xoaddr:$src), 0),
                          (XXPERMDIs (LXSIHZX xoaddr:$src), 0)>;
 defm : ScalToVecWPermute<v4i32, ScalarLoads.SELi16,
                          (XXSPLTWs (VEXTSH2Ws (LXSIHZX xoaddr:$src)), 1),
(SUBREG_TO_REG
      (i64 1),
      (XSCVDPUXDS (COPY_TO_REGCLASS (DFLOADf32 iaddrX4:$A), VSFRC)), sub_64)>;
 def : Pat<(v4f32 (PPCldsplat xoaddr:$A)),
           (v4f32 (LXVWSX xoaddr:$A))>;
 def : Pat<(v4i32 (PPCldsplat xoaddr:$A)),
           (v4i32 (LXVWSX xoaddr:$A))>;
 } // HasVSX, HasP9Vector
 
+// Any Power9 VSX subtarget with equivalent length but better Power10 VSX
+// patterns.
+let Predicates = [HasVSX, HasP9Vector, NoP10Vector] in {
+// Little endian Power10 subtargets produce a shorter pattern but require a
+// COPY_TO_REGCLASS making a faux equivalent pattern, NoP10Vector predicate
+// excludes these patterns from Power10 VSX subtargets
+// Build vectors from i8 loads
+defm : ScalToVecWPermute<v16i8, ScalarLoads.Li8,
+                         (VSPLTBs 7, (LXSIBZX xoaddr:$src)),
+                         (VSPLTBs 7, (LXSIBZX xoaddr:$src))>;
+// Build vectors from i16 loads
+defm : ScalToVecWPermute<v8i16, ScalarLoads.Li16,
+                         (VSPLTHs 3, (LXSIHZX xoaddr:$src)),
+                         (VSPLTHs 3, (LXSIHZX xoaddr:$src))>;
+} // HasVSX, HasP9Vector, NoP10Vector
+
+// Any big endian Power9 VSX subtarget
+let Predicates = [HasVSX, HasP9Vector, IsBigEndian] in {
+// Power10 VSX subtargets produce a shorter pattern for little endian targets
+// but this is still the best pattern for Power9 and Power10 VSX big endian
+// Build vectors from i8 loads
+defm : ScalToVecWPermute<v16i8, ScalarLoads.Li8,
+                         (VSPLTBs 7, (LXSIBZX xoaddr:$src)),
+                         (VSPLTBs 7, (LXSIBZX xoaddr:$src))>;
+// Build vectors from i16 loads
+defm : ScalToVecWPermute<v8i16, ScalarLoads.Li16,
+                         (VSPLTHs 3, (LXSIHZX xoaddr:$src)),
+                         (VSPLTHs 3, (LXSIHZX xoaddr:$src))>;
+} // HasVSX, HasP9Vector, NoP10Vector
+
 // Big endian 64Bit Power9 subtarget.
 let Predicates = [HasVSX, HasP9Vector, IsBigEndian, IsPPC64] in {
 def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 0)))))),
           (f32 (XSCVUXDSP (XXEXTRACTUW $A, 0)))>;
 def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 1)))))),
           (f32 (XSCVUXDSP (XXEXTRACTUW $A, 4)))>;
 def : Pat<(f32 (PPCfcfidus (f64 (PPCmtvsrz (i32 (extractelt v4i32:$A, 2)))))),
           (f32 (XSCVUXDSP (XXEXTRACTUW $A, 8)))>;

llvm/test/CodeGen/PowerPC/load-rightmost-vector-elt.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:     -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
+; RUN:     < %s | FileCheck %s --check-prefix=CHECK-LE
+
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:     -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
+; RUN:     < %s | FileCheck %s --check-prefix=CHECK-BE
+
+define <8 x i16> @test1(i16*  %a) {
+; CHECK-LE-LABEL: test1:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    lxvrhx v2, 0, r3
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-BE-LABEL: test1:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    lxsihzx v2, 0, r3
+; CHECK-BE-NEXT:    vsplth v2, v2, 3
+; CHECK-BE-NEXT:    blr
+entry:
+  %0 = load i16, i16* %a, align 2
+  %vecinit = insertelement <8 x i16> undef, i16 %0, i32 0
+  ret <8 x i16> %vecinit
+}
+
+define <16 x i8> @test2(i8*  %a) {
+; CHECK-LE-LABEL: test2:
+; CHECK-LE:       # %bb.0: # %entry
+; CHECK-LE-NEXT:    lxvrbx v2, 0, r3
+; CHECK-LE-NEXT:    blr
+;
+; CHECK-BE-LABEL: test2:
+; CHECK-BE:       # %bb.0: # %entry
+; CHECK-BE-NEXT:    lxsibzx v2, 0, r3
+; CHECK-BE-NEXT:    vspltb v2, v2, 7
+; CHECK-BE-NEXT:    blr
+entry:
+  %0 = load i8, i8* %a, align 1
+  %vecins = insertelement <16 x i8> undef, i8 %0, i32 0
+  ret <16 x i8> %vecins
+}
+