[X86] Fix tile register spill issue.

[LuoYuanke]

Summary

The tile register spill need 2 instructions.
%46:gr64_nosp = MOV64ri 64
TILESTORED %stack.2, 1, killed %46:gr64_nosp, 0, $noreg, %43:tile
The first instruction load the stride to a GPR, and the second
instruction store tile register to stack slot. The optimization of merge
spill instruction is done after register allocation. And spill tile
register need create a new virtual register to for stride, so we can't
hoist tile spill instruction in postOptimization() of register
allocation. We can't hoist TILESTORED alone and we can't hoist the 2
instuctions together because MOV64ri will clobber some GPR. This patch
is to disble the spill merge for any spill which need 2 instructions.

[LuoYuanke]

Rebase.

[wxiao3]

llvm/lib/CodeGen/InlineSpiller.cpp

272

The function name is misleading since the function just get intervals for definition registers.
Suggest using more specific name such as "getVDefInterval" or something else.

BTW, I guess there may be existing code can provide similar functionality of creating intervals for new registers.
@qcolombet may provide more information.

[LuoYuanke]

Address Wei's comments.

[LuoYuanke]

llvm/lib/CodeGen/InlineSpiller.cpp

272

The proposed name looks good to me. Renamed the function to "getVDefInterval".

[wxiao3]

LGTM. But I suggest you waiting for one or two days to see if @qcolombet or others object.

[LuoYuanke]

In D93898#2483571, @wxiao3 wrote:

LGTM. But I suggest you waiting for one or two days to see if @qcolombet or others object.

Thank Wei for the review. Sure, I'll wait for a few days to see if there is any object from others.