The tile register spill need 2 instructions.
%46:gr64_nosp = MOV64ri 64
TILESTORED %stack.2, 1, killed %46:gr64_nosp, 0, $noreg, %43:tile
The first instruction load the stride to a GPR, and the second
instruction store tile register to stack slot. The optimization of merge
spill instruction is done after register allocation. And spill tile
register need create a new virtual register to for stride, so we can't
hoist tile spill instruction in postOptimization() of register
allocation. We can't hoist TILESTORED alone and we can't hoist the 2
instuctions together because MOV64ri will clobber some GPR. This patch
is to disble the spill merge for any spill which need 2 instructions.
Details
Details
Diff Detail
Diff Detail
- Repository
- rG LLVM Github Monorepo
Event Timeline
llvm/lib/CodeGen/InlineSpiller.cpp | ||
---|---|---|
272 | The function name is misleading since the function just get intervals for definition registers. BTW, I guess there may be existing code can provide similar functionality of creating intervals for new registers. |
llvm/lib/CodeGen/InlineSpiller.cpp | ||
---|---|---|
272 | The proposed name looks good to me. Renamed the function to "getVDefInterval". |
Comment Actions
LGTM. But I suggest you waiting for one or two days to see if @qcolombet or others object.
Comment Actions
Thank Wei for the review. Sure, I'll wait for a few days to see if there is any object from others.