[RISCV] Add MemOperand to the instruction created by storeRegToStackSlot/loadRegFromStackSlot

[craig.topper]

Summary

It looks like most targets do this, but not all.

[HsiangKai]

LGTM.

[lenary]

Is the code change due to the fact that the optimizer later finally knows that 12(sp) and 8(sp) don't overlap?

[craig.topper]

In D91730#2405132, @lenary wrote:

Is the code change due to the fact that the optimizer later finally knows that 12(sp) and 8(sp) don't overlap?

MachineSinking is moving the fld down. It previously couldn't do it because isSafeToMove returned false because hasOrderedMemoryRef() conservatively returned true due to the missing mem operand.

// a load across an atomic load with Ordering > Monotonic.
if (mayStore() || isCall() || isPHI() ||
    (mayLoad() && hasOrderedMemoryRef())) {
  SawStore = true;
  return false;
}

[lenary]

In D91730#2406401, @craig.topper wrote:

In D91730#2405132, @lenary wrote:

Is the code change due to the fact that the optimizer later finally knows that 12(sp) and 8(sp) don't overlap?

MachineSinking is moving the fld down. It previously couldn't do it because isSafeToMove returned false because hasOrderedMemoryRef() conservatively returned true due to the missing mem operand.

// a load across an atomic load with Ordering > Monotonic.
if (mayStore() || isCall() || isPHI() ||
    (mayLoad() && hasOrderedMemoryRef())) {
  SawStore = true;
  return false;
}

Ok, cool, as I thought. Nice patch!

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                          MachineBasicBlock::iterator I,
                                          Register SrcReg, bool IsKill, int FI,
                                          const TargetRegisterClass *RC,
                                          const TargetRegisterInfo *TRI) const {
   DebugLoc DL;
   if (I != MBB.end())
     DL = I->getDebugLoc();
 
-  unsigned Opcode;
+  MachineFunction *MF = MBB.getParent();
+  const MachineFrameInfo &MFI = MF->getFrameInfo();
+  MachineMemOperand *MMO = MF->getMachineMemOperand(
+      MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
+      MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
 
+  unsigned Opcode;
   if (RISCV::GPRRegClass.hasSubClassEq(RC))
     Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
              RISCV::SW : RISCV::SD;
   else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
     Opcode = RISCV::FSW;
   else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
     Opcode = RISCV::FSD;
   else
     llvm_unreachable("Can't store this register to stack slot");
 
   BuildMI(MBB, I, DL, get(Opcode))
       .addReg(SrcReg, getKillRegState(IsKill))
       .addFrameIndex(FI)
-      .addImm(0);
+      .addImm(0)
+      .addMemOperand(MMO);
 }
 
 void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
                                           MachineBasicBlock::iterator I,
                                           Register DstReg, int FI,
                                           const TargetRegisterClass *RC,
                                           const TargetRegisterInfo *TRI) const {
   DebugLoc DL;
   if (I != MBB.end())
     DL = I->getDebugLoc();
 
-  unsigned Opcode;
+  MachineFunction *MF = MBB.getParent();
+  const MachineFrameInfo &MFI = MF->getFrameInfo();
+  MachineMemOperand *MMO = MF->getMachineMemOperand(
+      MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
+      MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
 
+  unsigned Opcode;
   if (RISCV::GPRRegClass.hasSubClassEq(RC))
     Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
              RISCV::LW : RISCV::LD;
   else if (RISCV::FPR32RegClass.hasSubClassEq(RC))
     Opcode = RISCV::FLW;
   else if (RISCV::FPR64RegClass.hasSubClassEq(RC))
     Opcode = RISCV::FLD;
   else
     llvm_unreachable("Can't load this register from stack slot");
 
-  BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(0);
+  BuildMI(MBB, I, DL, get(Opcode), DstReg)
+    .addFrameIndex(FI)
+    .addImm(0)
+    .addMemOperand(MMO);
 }
 
 void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MBBI,
                             const DebugLoc &DL, Register DstReg, uint64_t Val,
                             MachineInstr::MIFlag Flag) const {
   MachineFunction *MF = MBB.getParent();
   MachineRegisterInfo &MRI = MF->getRegInfo();

llvm/test/CodeGen/RISCV/select-optimize-multiple.ll

 define double @cmovdouble(i1 %a, double %b, double %c) nounwind {
 ; RV32I-LABEL: cmovdouble:
 ; RV32I:       # %bb.0: # %entry
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw a3, 8(sp)
 ; RV32I-NEXT:    sw a4, 12(sp)
 ; RV32I-NEXT:    fld ft0, 8(sp)
 ; RV32I-NEXT:    sw a1, 8(sp)
-; RV32I-NEXT:    sw a2, 12(sp)
-; RV32I-NEXT:    fld ft1, 8(sp)
 ; RV32I-NEXT:    andi a0, a0, 1
-; RV32I-NEXT:    bnez a0, .LBB5_2
-; RV32I-NEXT:  # %bb.1: # %entry
-; RV32I-NEXT:    fmv.d ft1, ft0
+; RV32I-NEXT:    sw a2, 12(sp)
+; RV32I-NEXT:    beqz a0, .LBB5_2
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    fld ft0, 8(sp)
 ; RV32I-NEXT:  .LBB5_2: # %entry
-; RV32I-NEXT:    fsd ft1, 8(sp)
+; RV32I-NEXT:    fsd ft0, 8(sp)
 ; RV32I-NEXT:    lw a0, 8(sp)
 ; RV32I-NEXT:    lw a1, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: cmovdouble:
 ; RV64I:       # %bb.0: # %entry
 ; RV64I-NEXT:    andi a0, a0, 1