[RISCV]Add register constraint on riscv vector instruction

[tangxingxin1008]

Summary

On vector instruction, if the operand is a vector, it should be from
vector register groups.

Signed-off-by: tangxingxin <[e-mail]>

[jrtc27]

I'm confused why VRegAsmOperand even needs to exist; why can it not just use a register class like everything else and get this automatically? We only have AtomicMemOpOperand in order to parse both (reg) and 0(reg), but that's irrelevant for vectors.

[craig.topper]

In D91668#2401279, @jrtc27 wrote:

I'm confused why VRegAsmOperand even needs to exist; why can it not just use a register class like everything else and get this automatically? We only have AtomicMemOpOperand in order to parse both (reg) and 0(reg), but that's irrelevant for vectors.

I was wondering the same thing.

[tangxingxin1008]

In D91668#2401307, @craig.topper wrote:

In D91668#2401279, @jrtc27 wrote:

I'm confused why VRegAsmOperand even needs to exist; why can it not just use a register class like everything else and get this automatically? We only have AtomicMemOpOperand in order to parse both (reg) and 0(reg), but that's irrelevant for vectors.

I was wondering the same thing.

I am a beginner, only submit this patch for solved the problem of vector operand, but don't think so far. I'm sorry that I can't answer this question. Could the designer @HsiangKai help me to answer this question？

[HsiangKai]

In D91668#2401481, @tangxingxin1008 wrote:

In D91668#2401307, @craig.topper wrote:

In D91668#2401279, @jrtc27 wrote:

I'm confused why VRegAsmOperand even needs to exist; why can it not just use a register class like everything else and get this automatically? We only have AtomicMemOpOperand in order to parse both (reg) and 0(reg), but that's irrelevant for vectors.

I was wondering the same thing.

I am a beginner, only submit this patch for solved the problem of vector operand, but don't think so far. I'm sorry that I can't answer this question. Could the designer @HsiangKai help me to answer this question？

Initially, I model LMUL information into the instruction definitions. I created different operand classes for different LMUL register classes. After discussing with @rogfer01, we agreed to model the LMUL information into pseudo instructions. We will use the pseudo instructions to do code generation for RVV. There is no need to keep the operand class anymore.

I will create a patch to refine it. Thanks.

[tangxingxin1008]

https://reviews.llvm.org/D91712 fix it

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

public:
   bool isSystemRegister() const { return Kind == KindTy::SystemRegister; }
   bool isVType() const { return Kind == KindTy::VType; }
 
   bool isGPR() const {
     return Kind == KindTy::Register &&
            RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(Reg.RegNum);
   }
 
+  bool isVR() const {
+    return Kind == KindTy::Register &&
+           RISCVMCRegisterClasses[RISCV::VRRegClassID].contains(Reg.RegNum);
+  }
+
   static bool evaluateConstantImm(const MCExpr *Expr, int64_t &Imm,
                                   RISCVMCExpr::VariantKind &VK) {
     if (auto *RE = dyn_cast<RISCVMCExpr>(Expr)) {
       VK = RE->getKind();
       return RE->evaluateAsConstant(Imm);
     }
 
     if (auto CE = dyn_cast<MCConstantExpr>(Expr)) {

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

def VTypeIOp : Operand<XLenVT> {
   let ParserMatchClass = VTypeIAsmOperand;
   let PrintMethod = "printVTypeI";
   let DecoderMethod = "decodeUImmOperand<11>";
 }
 
 def VRegAsmOperand : AsmOperandClass {
   let Name = "RVVRegOpOperand";
   let RenderMethod = "addRegOperands";
-  let PredicateMethod = "isReg";
+  let PredicateMethod = "isVR";
   let ParserMethod = "parseRegister";
 }
 
 def VRegOp : RegisterOperand<VR> {
   let ParserMatchClass = VRegAsmOperand;
   let PrintMethod = "printOperand";
 }
 

llvm/test/MC/RISCV/rvv/invalid.s

 # CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
 
 vadd.vv v1, v3, v2, v4.t
 # CHECK-ERROR: operand must be v0.t
 
 vadd.vv v1, v3, v2, v0
 # CHECK-ERROR: expected '.t' suffix
 
+vadd.vv v1, v3, a0
+# CHECK-ERROR: invalid operand for instruction
+
 vmslt.vi v1, v2, -16
 # CHECK-ERROR: immediate must be in the range [-15, 16]
 
 vmslt.vi v1, v2, 17
 # CHECK-ERROR: immediate must be in the range [-15, 16]
 
 viota.m v0, v2, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.