[AArch64] Out-of-line atomics (-moutline-atomics) implementation.

[ilinpv]

Summary

This patch implements out of line atomics for LSE deployment
mechanism. Details how it works can be found in llvm/docs/Atomics.rst
Options -moutline-atomics and -mno-outline-atomics to enable and disable it
were added to clang driver. This is clang and llvm part of out-of-line atomics
interface, library part is already supported by libgcc. Compiler-rt
support is provided in separate patch.

[t.p.northover]

clang/lib/Driver/ToolChains/Clang.cpp

6369

This excludes aarch64_be, which is a bit weird. Might be best to check Triple.isAArch64().

llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

1818

Could you do the whitespace changes separately (if at all)?

4062

"its"

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

2179

I think this is a bit of an abuse of the LibcallName mechanism. A separate function in TargetLowering would probably be better.

llvm/lib/Target/AArch64/AArch64Subtarget.h

476

I think something is a bit weird with how your clang-format handles comments. Here and earlier line lengths are about half as long as I'd expect.

llvm/test/CodeGen/AArch64/atomic-ops.ll

534

I'd prefer not to overwrite existing CHECKS that have generic dataflow with ones produced by that tool hardcoding a particular register allocation.

[jyknight]

llvm/docs/Atomics.rst

625

I think this section needs to be put on the end of the section on __sync_*. These functions are effectively an aarch64-specific version of the the __sync libcalls -- just with the addition of the memory ordering in the function name, instead of assuming seq_cst. All of the same commentary applies otherwise, and clearly distinguishing from the __atomic_* calls is important.

Maybe something like:

On AArch64, a variant of the __sync_* routines is used which contain the memory order as part of the function name. These routines may determine at runtime whether the single-instruction atomic operations which were introduced as part of AArch64 Large System Extensions "LSE" instruction set are available, or if it needs to fall back to an LL/SC loop.

The following helper functions are implemented in both [.....]

llvm/include/llvm/IR/RuntimeLibcalls.def

547

Maybe just go ahead and define the libcalls up to size 16, even though aarch64 won't define or use the 16-byte functions, other than CAS. Can we come up with a better name for these libfuncs here? "ATOMIC_*" is an unfortunate prefix, since we already use it for the entirely-distinct set of functions above.

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

2179

I don't think that's odd or unusual -- we often condition libcall availability on getLibcallName != nullptr.

What does strike me here is the (pre-existing) code duplication between this function (DAGTypeLegalizer::ExapndAtomic) and SelectionDAGLegalize::ConvertNodeToLibcall. Not sure what's up with that...

llvm/lib/CodeGen/TargetLoweringBase.cpp

451

What's the purpose of the struct?

473

If you moved this switch to the end, you can just have each clause be "return SwpLcalls[ModeN][ModelN];", instead of storing the address of the array.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

15772

So, hold on -- AArch64 has umin/umax/smin/smax instructions, but libgcc and compiler-rt don't have helpers for those? That seems to be a remarkably unfortunate state of affairs.

Can you fix that, by implementing those functions in the compiler-rt patch, and submitting the same to libgcc?

llvm/lib/Target/AArch64/AArch64Subtarget.h

476

I think it'd be clearer to have this simply "return OutlineAtomics;". The only usage that needs to change is AArch64ISelLowering.cpp L663, and it'd be _clearer_ to have it explicitly say if (!Subtarget->hasLSE() && Subtarget->outlineAtomics()).

[t.p.northover]

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

2179

Fair enough. Didn't realise it was that common.

[ilinpv]

Work on comments has been done.

[ilinpv]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

15772

Yes, agree, initially I was going to add min/max helpers to both compiler-rt and libgcc. But the point is that gcc is not generating LSE min/max at all. So these helpers would be untested and become rotten. There is no reason for gcc community to support unused code. Hopefully after <atomic> maximum/minimum proposal approval I can easily add the helpers to libcc and compiler-rt and enable [U]Min/[U]Max RWM atomics expansion in LLVM.

[ilinpv]

Have you got any further comments?

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

2179

I noticed this existed duplication too, but find no proper place to put common functionality from DAGTypeLegalizer and SelectionDAGLegalize.

[jyknight]

LG after fixing the minor nits.

clang/lib/Driver/ToolChains/Clang.cpp

6377

We don't usually explicitly use negative features like this, do we? I think this else clause can be omitted.

llvm/lib/CodeGen/TargetLoweringBase.cpp

492–495

As with the .def file, get rid of LCALL4, and just use LCALL5 for everything here. AArch64ISelLowering won't setup libcall names for 128-bit ones, which is fine.

[ilinpv]

clang/lib/Driver/ToolChains/Clang.cpp

6377

We do, -soft-float for example in Clang.cpp:2397

if (Value.startswith("-mhard-float")) {
          CmdArgs.push_back("-target-feature");
          CmdArgs.push_back("-soft-float");
          continue;
        }

[ilinpv]

LCALL4 removed in TargetLoweringBase.

[sebpop]

I tested this change on Graviton2 aarch64-linux by building https://github.com/xianyi/OpenBLAS with clang -O3 -moutline-atomics and make test: all tests pass with and without outline-atomics.
Clang was configured to use libgcc.

I also tested https://github.com/boostorg/boost.git with and without -moutline-atomics, and there are no new fails.
Here is how I built and ran the tests for boost:

git clone --recursive https://github.com/boostorg/boost.git $HOME/boost
cd $HOME/boost
mkdir usr
./bootstrap.sh --prefix=$HOME/boost/usr
# in project-config.jam line 12
# replace `using gcc ;` with `using clang :   : $HOME/llvm-project/usr/bin/clang++ ;`
./b2 --build-type=complete --layout=versioned -a
cd status
../b2  # runs all regression tests

I also looked at the performance of some atomic operations using google-benchmark on Ubuntu 20.04 c6g instance with Graviton2 (Neoverse-N1).
Performance is better when using LSE instructions compared to generic armv8-a code.
The overhead of -moutline-atomics is negligible compared to armv8-a+lse.
clang trunk as of today produces slightly slower code than gcc-9 with and without -moutline-atomics.

$ cat a.cc
#include <benchmark/benchmark.h>
#include <atomic>

std::atomic<int> i;
static void BM_atomic_increment(benchmark::State& state) {
  for (auto _ : state)
    benchmark::DoNotOptimize(i++);
}
BENCHMARK(BM_atomic_increment);

int j;
static void BM_atomic_fetch_add(benchmark::State& state) {
  for (auto _ : state)
    benchmark::DoNotOptimize(__atomic_fetch_add(&j, 1, __ATOMIC_SEQ_CST));
}
BENCHMARK(BM_atomic_fetch_add);

int k;
static void BM_atomic_compare_exchange(benchmark::State& state) {
  for (auto _ : state)
    benchmark::DoNotOptimize(__atomic_compare_exchange
                             (&j, &k, &k, 1, __ATOMIC_ACQUIRE, __ATOMIC_ACQUIRE));
}
BENCHMARK(BM_atomic_compare_exchange);


template<class T>
struct node {
  T data;
  node* next;
  node(const T& data) : data(data), next(nullptr) {}
};

static void BM_std_atomic_compare_exchange(benchmark::State& state) {
  node<int>* new_node = new node<int>(42);
  std::atomic<node<int>*> head;
  for (auto _ : state)
    benchmark::DoNotOptimize(std::atomic_compare_exchange_weak_explicit
                             (&head, &new_node->next, new_node,
                              std::memory_order_release,
                              std::memory_order_relaxed));
}
BENCHMARK(BM_std_atomic_compare_exchange);

BENCHMARK_MAIN();

---
$ ./go.sh
+ g++ -o generic-v8 a.cc -std=c++11 -O2 -isystem benchmark/include -Lbenchmark/build/src -lbenchmark -lpthread
+ ./generic-v8
2020-12-06 01:06:26
Running ./generic-v8
Run on (64 X 243.75 MHz CPU s)
CPU Caches:
  L1 Data 64 KiB (x64)
  L1 Instruction 64 KiB (x64)
  L2 Unified 1024 KiB (x64)
  L3 Unified 32768 KiB (x1)
Load Average: 64.36, 59.36, 36.41
***WARNING*** Library was built as DEBUG. Timings may be affected.
-------------------------------------------------------------------------
Benchmark                               Time             CPU   Iterations
-------------------------------------------------------------------------
BM_atomic_increment                  7.21 ns         7.20 ns     97116662
BM_atomic_fetch_add                  7.20 ns         7.20 ns     97152394
BM_atomic_compare_exchange           7.71 ns         7.71 ns     90780423
BM_std_atomic_compare_exchange       7.61 ns         7.61 ns     92037159
+ /home/ubuntu/llvm-project/nin/bin/clang++ -o clang-generic-v8 a.cc -std=c++11 -O2 -isystem benchmark/include -Lbenchmark/build/src -lbenchmark -lpthread
+ ./clang-generic-v8
2020-12-06 01:06:30
Running ./clang-generic-v8
Run on (64 X 243.75 MHz CPU s)
CPU Caches:
  L1 Data 64 KiB (x64)
  L1 Instruction 64 KiB (x64)
  L2 Unified 1024 KiB (x64)
  L3 Unified 32768 KiB (x1)
Load Average: 64.57, 59.49, 36.57
***WARNING*** Library was built as DEBUG. Timings may be affected.
-------------------------------------------------------------------------
Benchmark                               Time             CPU   Iterations
-------------------------------------------------------------------------
BM_atomic_increment                  9.21 ns         9.21 ns     75989223
BM_atomic_fetch_add                  9.21 ns         9.21 ns     76031211
BM_atomic_compare_exchange           7.61 ns         7.61 ns     92012620
BM_std_atomic_compare_exchange       12.4 ns         12.4 ns     56421424
+ g++ -o lse -march=armv8-a+lse a.cc -std=c++11 -O2 -isystem benchmark/include -Lbenchmark/build/src -lbenchmark -lpthread
+ ./lse
2020-12-06 01:06:34
Running ./lse
Run on (64 X 243.75 MHz CPU s)
CPU Caches:
  L1 Data 64 KiB (x64)
  L1 Instruction 64 KiB (x64)
  L2 Unified 1024 KiB (x64)
  L3 Unified 32768 KiB (x1)
Load Average: 64.85, 59.63, 36.74
***WARNING*** Library was built as DEBUG. Timings may be affected.
-------------------------------------------------------------------------
Benchmark                               Time             CPU   Iterations
-------------------------------------------------------------------------
BM_atomic_increment                  5.21 ns         5.21 ns    134201945
BM_atomic_fetch_add                  5.21 ns         5.21 ns    134438848
BM_atomic_compare_exchange           6.80 ns         6.80 ns    102872012
BM_std_atomic_compare_exchange       6.80 ns         6.80 ns    102864719
+ clang++ -o clang-lse -march=armv8-a+lse a.cc -std=c++11 -O2 -isystem benchmark/include -Lbenchmark/build/src -lbenchmark -lpthread
+ ./clang-lse
2020-12-06 01:06:38
Running ./clang-lse
Run on (64 X 243.75 MHz CPU s)
CPU Caches:
  L1 Data 64 KiB (x64)
  L1 Instruction 64 KiB (x64)
  L2 Unified 1024 KiB (x64)
  L3 Unified 32768 KiB (x1)
Load Average: 64.85, 59.63, 36.74
***WARNING*** Library was built as DEBUG. Timings may be affected.
-------------------------------------------------------------------------
Benchmark                               Time             CPU   Iterations
-------------------------------------------------------------------------
BM_atomic_increment                  7.21 ns         7.21 ns     97086511
BM_atomic_fetch_add                  7.21 ns         7.21 ns     97152416
BM_atomic_compare_exchange           7.20 ns         7.20 ns     97186161
BM_std_atomic_compare_exchange       11.6 ns         11.6 ns     60302378
+ g++ -o moutline -moutline-atomics a.cc -std=c++11 -O2 -isystem benchmark/include -Lbenchmark/build/src -lbenchmark -lpthread
+ ./moutline
2020-12-06 01:06:41
Running ./moutline
Run on (64 X 243.75 MHz CPU s)
CPU Caches:
  L1 Data 64 KiB (x64)
  L1 Instruction 64 KiB (x64)
  L2 Unified 1024 KiB (x64)
  L3 Unified 32768 KiB (x1)
Load Average: 64.94, 59.74, 36.90
***WARNING*** Library was built as DEBUG. Timings may be affected.
-------------------------------------------------------------------------
Benchmark                               Time             CPU   Iterations
-------------------------------------------------------------------------
BM_atomic_increment                  5.60 ns         5.60 ns    124853685
BM_atomic_fetch_add                  5.60 ns         5.60 ns    124907943
BM_atomic_compare_exchange           7.21 ns         7.21 ns     97151664
BM_std_atomic_compare_exchange       7.21 ns         7.21 ns     97148224
+ /home/ubuntu/llvm-project/nin/bin/clang++ -o clang-moutline -moutline-atomics a.cc -std=c++11 -O2 -isystem benchmark/include -Lbenchmark/build/src -lbenchmark -lpthread
+ ./clang-moutline
2020-12-06 01:06:45
Running ./clang-moutline
Run on (64 X 243.75 MHz CPU s)
CPU Caches:
  L1 Data 64 KiB (x64)
  L1 Instruction 64 KiB (x64)
  L2 Unified 1024 KiB (x64)
  L3 Unified 32768 KiB (x1)
Load Average: 64.95, 59.82, 37.05
***WARNING*** Library was built as DEBUG. Timings may be affected.
-------------------------------------------------------------------------
Benchmark                               Time             CPU   Iterations
-------------------------------------------------------------------------
BM_atomic_increment                  7.21 ns         7.21 ns     97071465
BM_atomic_fetch_add                  7.21 ns         7.20 ns     97150580
BM_atomic_compare_exchange           7.20 ns         7.20 ns     97164566
BM_std_atomic_compare_exchange       11.6 ns         11.6 ns     60301778

[sebpop]

Hi Pavel,

We need to handle one more case for __sync_* builtins, please see testcase and patches applied to GCC:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105162

[efriedma]

https://github.com/llvm/llvm-project/issues/29472 was never fixed; whatever issues exist with -moutline-atomics also exist with -mno-outline-atomics. (I don't think anyone has run into any practical issues with this, so it hasn't been a priority for anyone.)

[ilinpv]

I think it looks reasonable to define 5th memory model, add barriers __sync_* builtins and to outline-atomics calls as well.

clang/include/clang/Basic/DiagnosticDriverKinds.td

 def warn_drv_global_isel_incomplete_opt : Warning<
   "-fglobal-isel support is incomplete for this architecture at the current optimization level">,
   InGroup<GlobalISel>;
 
 def warn_drv_moutline_unsupported_opt : Warning<
   "The '%0' architecture does not support -moutline; flag ignored">,
   InGroup<OptionIgnored>;
 
+def warn_drv_moutline_atomics_unsupported_opt : Warning<
+  "The '%0' architecture does not support -moutline-atomics; flag ignored">,
+  InGroup<OptionIgnored>;
+
 def warn_drv_darwin_sdk_invalid_settings : Warning<
   "SDK settings were ignored as 'SDKSettings.json' could not be parsed">,
   InGroup<DiagGroup<"darwin-sdk-settings">>;
 
 def err_drv_trivial_auto_var_init_zero_disabled : Error<
   "-ftrivial-auto-var-init=zero hasn't been enabled. Enable it at your own peril for benchmarking purpose only with "
   "-enable-trivial-auto-var-init-zero-knowing-it-will-be-removed-from-clang">;
 

clang/include/clang/Driver/Options.td

 def mno_incremental_linker_compatible : Flag<["-"], "mno-incremental-linker-compatible">, Group<m_Group>,
   HelpText<"(integrated-as) Emit an object file which cannot be used with an incremental linker">;
 def mrtd : Flag<["-"], "mrtd">, Group<m_Group>, Flags<[CC1Option]>,
   HelpText<"Make StdCall calling convention the default">;
 def msmall_data_threshold_EQ : Joined <["-"], "msmall-data-threshold=">,
   Group<m_Group>, Alias<G>;
 def msoft_float : Flag<["-"], "msoft-float">, Group<m_Group>, Flags<[CC1Option]>,
   HelpText<"Use software floating point">;
+def moutline_atomics : Flag<["-"], "moutline-atomics">, Group<f_clang_Group>, Flags<[CC1Option]>,
+  HelpText<"Generate local calls to out-of-line atomic operations">;
+def mno_outline_atomics : Flag<["-"], "mno-outline-atomics">, Group<f_clang_Group>, Flags<[CC1Option]>,
+  HelpText<"Don't generate local calls to out-of-line atomic operations">;
 def mno_implicit_float : Flag<["-"], "mno-implicit-float">, Group<m_Group>,
   HelpText<"Don't generate implicit floating point instructions">;
 def mimplicit_float : Flag<["-"], "mimplicit-float">, Group<m_Group>;
 def mrecip : Flag<["-"], "mrecip">, Group<m_Group>;
 def mrecip_EQ : CommaJoined<["-"], "mrecip=">, Group<m_Group>, Flags<[CC1Option]>;
 def mprefer_vector_width_EQ : Joined<["-"], "mprefer-vector-width=">, Group<m_Group>, Flags<[CC1Option]>,
   HelpText<"Specifies preferred vector width for auto-vectorization. Defaults to 'none' which allows target specific decisions.">;
 def mstack_protector_guard_EQ : Joined<["-"], "mstack-protector-guard=">, Group<m_Group>, Flags<[CC1Option]>,

clang/lib/Driver/ToolChains/Clang.cpp

if (A->getOption().matches(options::OPT_moutline)) {
       }
     } else {
       // Disable all outlining behaviour.
       CmdArgs.push_back("-mllvm");
       CmdArgs.push_back("-enable-machine-outliner=never");
     }
   }
 
+  if (Arg *A = Args.getLastArg(options::OPT_moutline_atomics,
+                               options::OPT_mno_outline_atomics)) {
+    if (A->getOption().matches(options::OPT_moutline_atomics)) {
+      // Option -moutline-atomics supported for AArch64 target only.
+      if (!Triple.isAArch64()) {
+        D.Diag(diag::warn_drv_moutline_atomics_unsupported_opt)
+            << Triple.getArchName();
+      } else {
+        CmdArgs.push_back("-target-feature");
+        CmdArgs.push_back("+outline-atomics");
+      }
+    } else {
+      CmdArgs.push_back("-target-feature");
+      CmdArgs.push_back("-outline-atomics");
+    }
+  }
+
   if (Args.hasFlag(options::OPT_faddrsig, options::OPT_fno_addrsig,
                    (TC.getTriple().isOSBinFormatELF() ||
                     TC.getTriple().isOSBinFormatCOFF()) &&
                       !TC.getTriple().isPS4() &&
                       !TC.getTriple().isOSNetBSD() &&
                       !Distro(D.getVFS(), TC.getTriple()).IsGentoo() &&
                       !TC.getTriple().isAndroid() &&
                        TC.useIntegratedAs()))

llvm/docs/Atomics.rst

 
 This list doesn't include any function for atomic load or store; all known
 architectures support atomic loads and stores directly (possibly by emitting a
 fence on either side of a normal load or store.)
 
 There's also, somewhat separately, the possibility to lower ``ATOMIC_FENCE`` to
 ``__sync_synchronize()``. This may happen or not happen independent of all the
 above, controlled purely by ``setOperationAction(ISD::ATOMIC_FENCE, ...)``.
+
+On AArch64, a variant of the __sync_* routines is used which contain the memory
+order as part of the function name. These routines may determine at runtime
+whether the single-instruction atomic operations which were introduced as part
+of AArch64 Large System Extensions "LSE" instruction set are available, or if
+it needs to fall back to an LL/SC loop. The following helper functions are
+implemented in both ``compiler-rt`` and ``libgcc`` libraries
+(``N`` is one of 1, 2, 4, 8, and ``M`` is one of 1, 2, 4, 8 and 16, and
+``ORDER`` is one of 'relax', 'acq', 'rel', 'acq_rel')::
+
+  iM __aarch64_casM_ORDER(iM expected, iM desired, iM *ptr)
+  iN __aarch64_swpN_ORDER(iN val, iN *ptr)
+  iN __aarch64_ldaddN_ORDER(iN val, iN *ptr)
+  iN __aarch64_ldclrN_ORDER(iN val, iN *ptr)
+  iN __aarch64_ldeorN_ORDER(iN val, iN *ptr)
+  iN __aarch64_ldsetN_ORDER(iN val, iN *ptr)
+
+Please note, if LSE instruction set is specified for AArch64 target then
+out-of-line atomics calls are not generated and single-instruction atomic
+operations are used in place.

llvm/include/llvm/CodeGen/RuntimeLibcalls.h

 // the backend may emit during code generation, and also some helper functions.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_CODEGEN_RUNTIMELIBCALLS_H
 #define LLVM_CODEGEN_RUNTIMELIBCALLS_H
 
 #include "llvm/CodeGen/ValueTypes.h"
+#include "llvm/Support/AtomicOrdering.h"
 
 namespace llvm {
 namespace RTLIB {
   /// RTLIB::Libcall enum - This enum defines all of the runtime library calls
   /// the backend can emit.  The various long double types cannot be merged,
   /// because 80-bit library functions use "xf" and 128-bit use "tf".
   ///
   /// When adding PPCF128 functions here, note that their names generally need
#undef HANDLE_LIBCALL
   /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
   /// UNKNOWN_LIBCALL if there is none.
   Libcall getUINTTOFP(EVT OpVT, EVT RetVT);
 
   /// Return the SYNC_FETCH_AND_* value for the given opcode and type, or
   /// UNKNOWN_LIBCALL if there is none.
   Libcall getSYNC(unsigned Opc, MVT VT);
 
+  /// Return the outline atomics value for the given opcode, atomic ordering
+  /// and type, or UNKNOWN_LIBCALL if there is none.
+  Libcall getOUTLINE_ATOMIC(unsigned Opc, AtomicOrdering Order, MVT VT);
+
   /// getMEMCPY_ELEMENT_UNORDERED_ATOMIC - Return
   /// MEMCPY_ELEMENT_UNORDERED_ATOMIC_* value for the given element size or
   /// UNKNOW_LIBCALL if there is none.
   Libcall getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize);
 
   /// getMEMMOVE_ELEMENT_UNORDERED_ATOMIC - Return
   /// MEMMOVE_ELEMENT_UNORDERED_ATOMIC_* value for the given element size or
   /// UNKNOW_LIBCALL if there is none.

llvm/include/llvm/IR/RuntimeLibcalls.def

 HANDLE_LIBCALL(ATOMIC_FETCH_XOR_8, "__atomic_fetch_xor_8")
 HANDLE_LIBCALL(ATOMIC_FETCH_XOR_16, "__atomic_fetch_xor_16")
 HANDLE_LIBCALL(ATOMIC_FETCH_NAND_1, "__atomic_fetch_nand_1")
 HANDLE_LIBCALL(ATOMIC_FETCH_NAND_2, "__atomic_fetch_nand_2")
 HANDLE_LIBCALL(ATOMIC_FETCH_NAND_4, "__atomic_fetch_nand_4")
 HANDLE_LIBCALL(ATOMIC_FETCH_NAND_8, "__atomic_fetch_nand_8")
 HANDLE_LIBCALL(ATOMIC_FETCH_NAND_16, "__atomic_fetch_nand_16")
 
+// Out-of-line atomics libcalls
+#define HLCALLS(A, N)                                                          \
+  HANDLE_LIBCALL(A##N##_RELAX, nullptr)                                        \
+  HANDLE_LIBCALL(A##N##_ACQ, nullptr)                                          \
+  HANDLE_LIBCALL(A##N##_REL, nullptr)                                          \
+  HANDLE_LIBCALL(A##N##_ACQ_REL, nullptr)
+#define HLCALL5(A)                                                             \
+  HLCALLS(A, 1) HLCALLS(A, 2) HLCALLS(A, 4) HLCALLS(A, 8) HLCALLS(A, 16)
+HLCALL5(OUTLINE_ATOMIC_CAS)
+HLCALL5(OUTLINE_ATOMIC_SWP)
+HLCALL5(OUTLINE_ATOMIC_LDADD)
+HLCALL5(OUTLINE_ATOMIC_LDSET)
+HLCALL5(OUTLINE_ATOMIC_LDCLR)
+HLCALL5(OUTLINE_ATOMIC_LDEOR)
+#undef HLCALLS
+#undef HLCALL5
+
 // Stack Protector Fail
 HANDLE_LIBCALL(STACKPROTECTOR_CHECK_FAIL, "__stack_chk_fail")
 
 // Deoptimization
 HANDLE_LIBCALL(DEOPTIMIZE, "__llvm_deoptimize")
 
 // Return address
 HANDLE_LIBCALL(RETURN_ADDRESS, nullptr)
 
 HANDLE_LIBCALL(UNKNOWN_LIBCALL, nullptr)
 

llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, EVT SlotVT,
   unsigned DestSize = DestVT.getSizeInBits();
   Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
   Align DestAlign = DAG.getDataLayout().getPrefTypeAlign(DestType);
 
   // Emit a store to the stack slot.  Use a truncstore if the input value is
   // later than DestVT.
   SDValue Store;
 
   if (SrcSize > SlotSize)
     Store = DAG.getTruncStore(Chain, dl, SrcOp, FIPtr, PtrInfo,
                               SlotVT, SrcAlign);
   else {
     assert(SrcSize == SlotSize && "Invalid store");
     Store =
         DAG.getStore(Chain, dl, SrcOp, FIPtr, PtrInfo, SrcAlign);
   }
 
void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
   case ISD::ATOMIC_LOAD_XOR:
   case ISD::ATOMIC_LOAD_NAND:
   case ISD::ATOMIC_LOAD_MIN:
   case ISD::ATOMIC_LOAD_MAX:
   case ISD::ATOMIC_LOAD_UMIN:
   case ISD::ATOMIC_LOAD_UMAX:
   case ISD::ATOMIC_CMP_SWAP: {
     MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
-    RTLIB::Libcall LC = RTLIB::getSYNC(Opc, VT);
-    assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!");
-
+    AtomicOrdering Order = cast<AtomicSDNode>(Node)->getOrdering();
+    RTLIB::Libcall LC = RTLIB::getOUTLINE_ATOMIC(Opc, Order, VT);
     EVT RetVT = Node->getValueType(0);
-    SmallVector<SDValue, 4> Ops(Node->op_begin() + 1, Node->op_end());
     TargetLowering::MakeLibCallOptions CallOptions;
+    SmallVector<SDValue, 4> Ops;
+    if (TLI.getLibcallName(LC)) {
+      // If outline atomic available, prepare its arguments and expand.
+      Ops.append(Node->op_begin() + 2, Node->op_end());
+      Ops.push_back(Node->getOperand(1));
+
+    } else {
+      LC = RTLIB::getSYNC(Opc, VT);
+      assert(LC != RTLIB::UNKNOWN_LIBCALL &&
+             "Unexpected atomic op or value type!");
+      // Arguments for expansion to sync libcall
+      Ops.append(Node->op_begin() + 1, Node->op_end());
+    }
     std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT,
                                                       Ops, CallOptions,
                                                       SDLoc(Node),
                                                       Node->getOperand(0));
     Results.push_back(Tmp.first);
     Results.push_back(Tmp.second);
     break;
   }

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

#endif
   if (Lo.getNode())
     SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
 }
 
 /// Lower an atomic node to the appropriate builtin call.
 std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
   unsigned Opc = Node->getOpcode();
   MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
-  RTLIB::Libcall LC = RTLIB::getSYNC(Opc, VT);
-  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!");
-
+  AtomicOrdering order = cast<AtomicSDNode>(Node)->getOrdering();
+  // Lower to outline atomic libcall if outline atomics enabled,
+  // or to sync libcall otherwise
+  RTLIB::Libcall LC = RTLIB::getOUTLINE_ATOMIC(Opc, order, VT);
   EVT RetVT = Node->getValueType(0);
-  SmallVector<SDValue, 4> Ops(Node->op_begin() + 1, Node->op_end());
   TargetLowering::MakeLibCallOptions CallOptions;
+  SmallVector<SDValue, 4> Ops;
+  if (TLI.getLibcallName(LC)) {
+    Ops.append(Node->op_begin() + 2, Node->op_end());
+    Ops.push_back(Node->getOperand(1));
+  } else {
+    LC = RTLIB::getSYNC(Opc, VT);
+    assert(LC != RTLIB::UNKNOWN_LIBCALL &&
+           "Unexpected atomic op or value type!");
+    Ops.append(Node->op_begin() + 1, Node->op_end());
+  }
   return TLI.makeLibCall(DAG, LC, RetVT, Ops, CallOptions, SDLoc(Node),
                          Node->getOperand(0));
 }
 
 /// N is a shift by a value that needs to be expanded,
 /// and the shift amount is a constant 'Amt'.  Expand the operation.
 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
                                              SDValue &Lo, SDValue &Hi) {

llvm/lib/CodeGen/TargetLoweringBase.cpp

if (OpVT == MVT::i32) {
     if (RetVT == MVT::f128)
       return UINTTOFP_I128_F128;
     if (RetVT == MVT::ppcf128)
       return UINTTOFP_I128_PPCF128;
   }
   return UNKNOWN_LIBCALL;
 }
 
+RTLIB::Libcall RTLIB::getOUTLINE_ATOMIC(unsigned Opc, AtomicOrdering Order,
+                                        MVT VT) {
+  unsigned ModeN, ModelN;
+  switch (VT.SimpleTy) {
+  case MVT::i8:
+    ModeN = 0;
+    break;
+  case MVT::i16:
+    ModeN = 1;
+    break;
+  case MVT::i32:
+    ModeN = 2;
+    break;
+  case MVT::i64:
+    ModeN = 3;
+    break;
+  case MVT::i128:
+    ModeN = 4;
+    break;
+  default:
+    return UNKNOWN_LIBCALL;
+  }
+
+  switch (Order) {
+  case AtomicOrdering::Monotonic:
+    ModelN = 0;
+    break;
+  case AtomicOrdering::Acquire:
+    ModelN = 1;
+    break;
+  case AtomicOrdering::Release:
+    ModelN = 2;
+    break;
+  case AtomicOrdering::AcquireRelease:
+  case AtomicOrdering::SequentiallyConsistent:
+    ModelN = 3;
+    break;
+  default:
+    return UNKNOWN_LIBCALL;
+  }
+
+#define LCALLS(A, B)                                                           \
+  { A##B##_RELAX, A##B##_ACQ, A##B##_REL, A##B##_ACQ_REL }
+#define LCALL4(A)                                                              \
+  LCALLS(A, 1), LCALLS(A, 2), LCALLS(A, 4), LCALLS(A, 8), {                    \
+    UNKNOWN_LIBCALL, UNKNOWN_LIBCALL, UNKNOWN_LIBCALL, UNKNOWN_LIBCALL         \
+  }
+#define LCALL5(A)                                                              \
+  LCALLS(A, 1), LCALLS(A, 2), LCALLS(A, 4), LCALLS(A, 8), LCALLS(A, 16)
+  switch (Opc) {
+  case ISD::ATOMIC_CMP_SWAP: {
+    const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_CAS)};
+    return LC[ModeN][ModelN];
+  }
+  case ISD::ATOMIC_SWAP: {
+    const Libcall LC[5][4] = {LCALL4(OUTLINE_ATOMIC_SWP)};
+    return LC[ModeN][ModelN];
+  }
+  case ISD::ATOMIC_LOAD_ADD: {
+    const Libcall LC[5][4] = {LCALL4(OUTLINE_ATOMIC_LDADD)};
+    return LC[ModeN][ModelN];
+  }
+  case ISD::ATOMIC_LOAD_OR: {
+    const Libcall LC[5][4] = {LCALL4(OUTLINE_ATOMIC_LDSET)};
+    return LC[ModeN][ModelN];
+  }
+  case ISD::ATOMIC_LOAD_CLR: {
+    const Libcall LC[5][4] = {LCALL4(OUTLINE_ATOMIC_LDCLR)};
+    return LC[ModeN][ModelN];
+  }
+  case ISD::ATOMIC_LOAD_XOR: {
+    const Libcall LC[5][4] = {LCALL4(OUTLINE_ATOMIC_LDEOR)};
+    return LC[ModeN][ModelN];
+  }
+  default:
+    return UNKNOWN_LIBCALL;
+  }
+#undef LCALLS
+#undef LCALL4
+#undef LCALL5
+}
+
 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) {
 #define OP_TO_LIBCALL(Name, Enum)                                              \
   case Name:                                                                   \
     switch (VT.SimpleTy) {                                                     \
     default:                                                                   \
       return UNKNOWN_LIBCALL;                                                  \
     case MVT::i8:                                                              \
       return Enum##_1;                                                         \

llvm/lib/Target/AArch64/AArch64.td

def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
   "Enable ARMv8 CRC-32 checksum instructions">;
 
 def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
   "Enable ARMv8 Reliability, Availability and Serviceability Extensions">;
 
 def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true",
   "Enable ARMv8.1 Large System Extension (LSE) atomic instructions">;
 
+def FeatureOutlineAtomics : SubtargetFeature<"outline-atomics", "OutlineAtomics", "true",
+  "Enable out of line atomics to support LSE instructions">;
+
 def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true",
   "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">;
 
 def FeaturePAN : SubtargetFeature<
     "pan", "HasPAN", "true",
     "Enables ARM v8.1 Privileged Access-Never extension">;
 
 def FeatureLOR : SubtargetFeature<

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
 
   setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom);
   setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
   setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
   setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Custom);
   setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
 
+  // Generate outline atomics library calls only if LSE was not specified for
+  // subtarget
+  if (Subtarget->outlineAtomics() && !Subtarget->hasLSE()) {
+    setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, LibCall);
+    setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, LibCall);
+    setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, LibCall);
+    setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, LibCall);
+    setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, LibCall);
+    setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, LibCall);
+    setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, LibCall);
+    setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, LibCall);
+    setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, LibCall);
+    setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, LibCall);
+    setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, LibCall);
+    setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, LibCall);
+    setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, LibCall);
+    setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i8, LibCall);
+    setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i16, LibCall);
+    setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, LibCall);
+    setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, LibCall);
+    setOperationAction(ISD::ATOMIC_LOAD_CLR, MVT::i8, LibCall);
+    setOperationAction(ISD::ATOMIC_LOAD_CLR, MVT::i16, LibCall);
+    setOperationAction(ISD::ATOMIC_LOAD_CLR, MVT::i32, LibCall);
+    setOperationAction(ISD::ATOMIC_LOAD_CLR, MVT::i64, LibCall);
+    setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i8, LibCall);
+    setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i16, LibCall);
+    setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, LibCall);
+    setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, LibCall);
+#define LCALLNAMES(A, B, N)                                                    \
+  setLibcallName(A##N##_RELAX, #B #N "_relax");                                \
+  setLibcallName(A##N##_ACQ, #B #N "_acq");                                    \
+  setLibcallName(A##N##_REL, #B #N "_rel");                                    \
+  setLibcallName(A##N##_ACQ_REL, #B #N "_acq_rel");
+#define LCALLNAME4(A, B)                                                       \
+  LCALLNAMES(A, B, 1)                                                          \
+  LCALLNAMES(A, B, 2) LCALLNAMES(A, B, 4) LCALLNAMES(A, B, 8)
+#define LCALLNAME5(A, B)                                                       \
+  LCALLNAMES(A, B, 1)                                                          \
+  LCALLNAMES(A, B, 2)                                                          \
+  LCALLNAMES(A, B, 4) LCALLNAMES(A, B, 8) LCALLNAMES(A, B, 16)
+    LCALLNAME5(RTLIB::OUTLINE_ATOMIC_CAS, __aarch64_cas)
+    LCALLNAME4(RTLIB::OUTLINE_ATOMIC_SWP, __aarch64_swp)
+    LCALLNAME4(RTLIB::OUTLINE_ATOMIC_LDADD, __aarch64_ldadd)
+    LCALLNAME4(RTLIB::OUTLINE_ATOMIC_LDSET, __aarch64_ldset)
+    LCALLNAME4(RTLIB::OUTLINE_ATOMIC_LDCLR, __aarch64_ldclr)
+    LCALLNAME4(RTLIB::OUTLINE_ATOMIC_LDEOR, __aarch64_ldeor)
+#undef LCALLNAMES
+#undef LCALLNAME4
+#undef LCALLNAME5
+  }
+
   // 128-bit loads and stores can be done without expanding
   setOperationAction(ISD::LOAD, MVT::i128, Custom);
   setOperationAction(ISD::STORE, MVT::i128, Custom);
 
   // 256 bit non-temporal stores can be lowered to STNP. Do this as part of the
   // custom lowering, as there are no un-paired non-temporal stores and
   // legalization will break up 256 bit inputs.
   setOperationAction(ISD::STORE, MVT::v32i8, Custom);
SDValue AArch64TargetLowering::LowerVECREDUCE(SDValue Op,
   default:
     llvm_unreachable("Unhandled reduction");
   }
 }
 
 SDValue AArch64TargetLowering::LowerATOMIC_LOAD_SUB(SDValue Op,
                                                     SelectionDAG &DAG) const {
   auto &Subtarget = static_cast<const AArch64Subtarget &>(DAG.getSubtarget());
-  if (!Subtarget.hasLSE())
+  if (!Subtarget.hasLSE() && !Subtarget.outlineAtomics())
     return SDValue();
 
   // LSE has an atomic load-add instruction, but not a load-sub.
   SDLoc dl(Op);
   MVT VT = Op.getSimpleValueType();
   SDValue RHS = Op.getOperand(2);
   AtomicSDNode *AN = cast<AtomicSDNode>(Op.getNode());
   RHS = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, dl, VT), RHS);
   return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, AN->getMemoryVT(),
                        Op.getOperand(0), Op.getOperand(1), RHS,
                        AN->getMemOperand());
 }
 
 SDValue AArch64TargetLowering::LowerATOMIC_LOAD_AND(SDValue Op,
                                                     SelectionDAG &DAG) const {
   auto &Subtarget = static_cast<const AArch64Subtarget &>(DAG.getSubtarget());
-  if (!Subtarget.hasLSE())
+  if (!Subtarget.hasLSE() && !Subtarget.outlineAtomics())
     return SDValue();
 
   // LSE has an atomic load-clear instruction, but not a load-and.
   SDLoc dl(Op);
   MVT VT = Op.getSimpleValueType();
   SDValue RHS = Op.getOperand(2);
   AtomicSDNode *AN = cast<AtomicSDNode>(Op.getNode());
   RHS = DAG.getNode(ISD::XOR, dl, VT, DAG.getConstant(-1ULL, dl, VT), RHS);

 
 static void ReplaceCMP_SWAP_128Results(SDNode *N,
                                        SmallVectorImpl<SDValue> &Results,
                                        SelectionDAG &DAG,
                                        const AArch64Subtarget *Subtarget) {
   assert(N->getValueType(0) == MVT::i128 &&
          "AtomicCmpSwap on types less than 128 should be legal");
 
-  if (Subtarget->hasLSE()) {
+  if (Subtarget->hasLSE() || Subtarget->outlineAtomics()) {
     // LSE has a 128-bit compare and swap (CASP), but i128 is not a legal type,
     // so lower it here, wrapped in REG_SEQUENCE and EXTRACT_SUBREG.
     SDValue Ops[] = {
         createGPRPairNode(DAG, N->getOperand(2)), // Compare value
         createGPRPairNode(DAG, N->getOperand(3)), // Store value
         N->getOperand(1), // Ptr
         N->getOperand(0), // Chain in
     };
AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
   if (AI->isFloatingPointOperation())
     return AtomicExpansionKind::CmpXChg;
 
   unsigned Size = AI->getType()->getPrimitiveSizeInBits();
   if (Size > 128) return AtomicExpansionKind::None;
   // Nand not supported in LSE.
   if (AI->getOperation() == AtomicRMWInst::Nand) return AtomicExpansionKind::LLSC;
   // Leave 128 bits to LLSC.
-  return (Subtarget->hasLSE() && Size < 128) ? AtomicExpansionKind::None : AtomicExpansionKind::LLSC;
+  if (Subtarget->hasLSE() && Size < 128)
+    return AtomicExpansionKind::None;
+  if (Subtarget->outlineAtomics() && Size < 128) {
+    // [U]Min/[U]Max RWM atomics are used in __sync_fetch_ libcalls so far.
+    // Don't outline them unless
+    // (1) high level <atomic> support approved:
+    //   http://www.open-std.org/jtc1/sc22/wg21/docs/papers/2020/p0493r1.pdf
+    // (2) low level libgcc and compiler-rt support implemented by:
+    //   min/max outline atomics helpers
+    if (AI->getOperation() != AtomicRMWInst::Min &&
+        AI->getOperation() != AtomicRMWInst::Max &&
+        AI->getOperation() != AtomicRMWInst::UMin &&
+        AI->getOperation() != AtomicRMWInst::UMax) {
+      return AtomicExpansionKind::None;
+    }
+  }
+  return AtomicExpansionKind::LLSC;
 }
 
 TargetLowering::AtomicExpansionKind
 AArch64TargetLowering::shouldExpandAtomicCmpXchgInIR(
     AtomicCmpXchgInst *AI) const {
   // If subtarget has LSE, leave cmpxchg intact for codegen.
-  if (Subtarget->hasLSE())
+  if (Subtarget->hasLSE() || Subtarget->outlineAtomics())
     return AtomicExpansionKind::None;
   // At -O0, fast-regalloc cannot cope with the live vregs necessary to
   // implement cmpxchg without spilling. If the address being exchanged is also
   // on the stack and close enough to the spill slot, this can lead to a
   // situation where the monitor always gets cleared and the atomic operation
   // can never succeed. So at -O0 we need a late-expanded pseudo-inst instead.
   if (getTargetMachine().getOptLevel() == CodeGenOpt::None)
     return AtomicExpansionKind::None;

llvm/lib/Target/AArch64/AArch64Subtarget.h

protected:
   bool StrictAlign = false;
 
   // NegativeImmediates - transform instructions with negative immediates
   bool NegativeImmediates = true;
 
   // Enable 64-bit vectorization in SLP.
   unsigned MinVectorRegisterBitWidth = 64;
 
+  bool OutlineAtomics = false;
   bool UseAA = false;
   bool PredictableSelectIsExpensive = false;
   bool BalanceFPOps = false;
   bool CustomAsCheapAsMove = false;
   bool ExynosAsCheapAsMove = false;
   bool UsePostRAScheduler = false;
   bool Misaligned128StoreIsSlow = false;
   bool Paired128IsSlow = false;
public:
   bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
 
   bool isTargetILP32() const { return TargetTriple.isArch32Bit(); }
 
   bool useAA() const override { return UseAA; }
 
+  bool outlineAtomics() const { return OutlineAtomics; }
+
   bool hasVH() const { return HasVH; }
   bool hasPAN() const { return HasPAN; }
   bool hasLOR() const { return HasLOR; }
 
   bool hasPsUAO() const { return HasPsUAO; }
   bool hasPAN_RWV() const { return HasPAN_RWV; }
   bool hasCCPP() const { return HasCCPP; }
 

llvm/test/CodeGen/AArch64/arm64-atomic-128.ll

 ; RUN: llc < %s -mtriple=arm64-linux-gnu -verify-machineinstrs -mcpu=cyclone | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-linux-gnu -verify-machineinstrs -mcpu=cyclone -mattr=+outline-atomics | FileCheck %s -check-prefix=OUTLINE-ATOMICS
 
 @var = global i128 0
 
 define i128 @val_compare_and_swap(i128* %p, i128 %oldval, i128 %newval) {
+; OUTLINE-ATOMICS: bl __aarch64_cas16_acq
 ; CHECK-LABEL: val_compare_and_swap:
 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
 ; CHECK: ldaxp   [[RESULTLO:x[0-9]+]], [[RESULTHI:x[0-9]+]], [x[[ADDR:[0-9]+]]]
 ; CHECK-DAG: eor     [[MISMATCH_LO:x[0-9]+]], [[RESULTLO]], x2
 ; CHECK-DAG: eor     [[MISMATCH_HI:x[0-9]+]], [[RESULTHI]], x3
 ; CHECK: orr [[MISMATCH:x[0-9]+]], [[MISMATCH_LO]], [[MISMATCH_HI]]
 ; CHECK: cbnz    [[MISMATCH]], [[DONE:.LBB[0-9]+_[0-9]+]]
 ; CHECK: stxp   [[SCRATCH_RES:w[0-9]+]], x4, x5, [x[[ADDR]]]

llvm/test/CodeGen/AArch64/arm64-atomic.ll

 ; RUN: llc < %s -mtriple=arm64-eabi -asm-verbose=false -verify-machineinstrs -mcpu=cyclone | FileCheck -enable-var-scope %s
+; RUN: llc < %s -mtriple=arm64-eabi -asm-verbose=false -verify-machineinstrs -mcpu=cyclone -mattr=+outline-atomics | FileCheck -enable-var-scope %s -check-prefix=OUTLINE-ATOMICS
 
 define i32 @val_compare_and_swap(i32* %p, i32 %cmp, i32 %new) #0 {
+; OUTLINE-ATOMICS: bl __aarch64_cas4_acq
 ; CHECK-LABEL: val_compare_and_swap:
 ; CHECK-NEXT: mov    x[[ADDR:[0-9]+]], x0
 ; CHECK-NEXT: [[TRYBB:.?LBB[0-9_]+]]:
 ; CHECK-NEXT: ldaxr  [[RESULT:w[0-9]+]], [x[[ADDR]]]
 ; CHECK-NEXT: cmp    [[RESULT]], w1
 ; CHECK-NEXT: b.ne   [[FAILBB:.?LBB[0-9_]+]]
 ; CHECK-NEXT: stxr   [[SCRATCH_REG:w[0-9]+]], w2, [x[[ADDR]]]
 ; CHECK-NEXT: cbnz   [[SCRATCH_REG]], [[TRYBB]]
 ; CHECK-NEXT: ret
 ; CHECK-NEXT: [[FAILBB]]:
 ; CHECK-NEXT: clrex
 ; CHECK-NEXT: ret
   %pair = cmpxchg i32* %p, i32 %cmp, i32 %new acquire acquire
   %val = extractvalue { i32, i1 } %pair, 0
   ret i32 %val
 }
 
 define i32 @val_compare_and_swap_from_load(i32* %p, i32 %cmp, i32* %pnew) #0 {
+; OUTLINE-ATOMICS: bl __aarch64_cas4_acq
 ; CHECK-LABEL: val_compare_and_swap_from_load:
 ; CHECK-NEXT: ldr    [[NEW:w[0-9]+]], [x2]
 ; CHECK-NEXT: [[TRYBB:.?LBB[0-9_]+]]:
 ; CHECK-NEXT: ldaxr  w[[RESULT:[0-9]+]], [x0]
 ; CHECK-NEXT: cmp    w[[RESULT]], w1
 ; CHECK-NEXT: b.ne   [[FAILBB:.?LBB[0-9_]+]]
 ; CHECK-NEXT: stxr   [[SCRATCH_REG:w[0-9]+]], [[NEW]], [x0]
 ; CHECK-NEXT: cbnz   [[SCRATCH_REG]], [[TRYBB]]
 ; CHECK-NEXT: mov    x0, x[[RESULT]]
 ; CHECK-NEXT: ret
 ; CHECK-NEXT: [[FAILBB]]:
 ; CHECK-NEXT: clrex
 ; CHECK-NEXT: mov    x0, x[[RESULT]]
 ; CHECK-NEXT: ret
   %new = load i32, i32* %pnew
   %pair = cmpxchg i32* %p, i32 %cmp, i32 %new acquire acquire
   %val = extractvalue { i32, i1 } %pair, 0
   ret i32 %val
 }
 
 define i32 @val_compare_and_swap_rel(i32* %p, i32 %cmp, i32 %new) #0 {
+; OUTLINE-ATOMICS: bl __aarch64_cas4_acq_rel
 ; CHECK-LABEL: val_compare_and_swap_rel:
 ; CHECK-NEXT: mov    x[[ADDR:[0-9]+]], x0
 ; CHECK-NEXT: [[TRYBB:.?LBB[0-9_]+]]:
 ; CHECK-NEXT: ldaxr  [[RESULT:w[0-9]+]], [x[[ADDR]]]
 ; CHECK-NEXT: cmp    [[RESULT]], w1
 ; CHECK-NEXT: b.ne   [[FAILBB:.?LBB[0-9_]+]]
 ; CHECK-NEXT: stlxr  [[SCRATCH_REG:w[0-9]+]], w2, [x[[ADDR]]]
 ; CHECK-NEXT: cbnz   [[SCRATCH_REG]], [[TRYBB]]
 ; CHECK-NEXT: ret
 ; CHECK-NEXT: [[FAILBB]]:
 ; CHECK-NEXT: clrex
 ; CHECK-NEXT: ret
   %pair = cmpxchg i32* %p, i32 %cmp, i32 %new acq_rel monotonic
   %val = extractvalue { i32, i1 } %pair, 0
   ret i32 %val
 }
 
 define i64 @val_compare_and_swap_64(i64* %p, i64 %cmp, i64 %new) #0 {
+; OUTLINE-ATOMICS: bl __aarch64_cas8_relax
 ; CHECK-LABEL: val_compare_and_swap_64:
 ; CHECK-NEXT: mov    x[[ADDR:[0-9]+]], x0
 ; CHECK-NEXT: [[TRYBB:.?LBB[0-9_]+]]:
 ; CHECK-NEXT: ldxr   [[RESULT:x[0-9]+]], [x[[ADDR]]]
 ; CHECK-NEXT: cmp    [[RESULT]], x1
 ; CHECK-NEXT: b.ne   [[FAILBB:.?LBB[0-9_]+]]
 ; CHECK-NEXT: stxr   [[SCRATCH_REG:w[0-9]+]], x2, [x[[ADDR]]]
 ; CHECK-NEXT: cbnz   [[SCRATCH_REG]], [[TRYBB]]

 ; CHECK: stlxr   [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x[[ADDR]]]
 ; CHECK: cbnz   [[SCRATCH_REG]], [[TRYBB]]
 
   %val = atomicrmw nand i64* %p, i64 7 acq_rel
   ret i64 %val
 }
 
 define i32 @fetch_and_or(i32* %p) #0 {
+; OUTLINE-ATOMICS: bl __aarch64_ldset4_acq_rel
 ; CHECK-LABEL: fetch_and_or:
 ; CHECK: mov   [[OLDVAL_REG:w[0-9]+]], #5
 ; CHECK: [[TRYBB:.?LBB[0-9_]+]]:
 ; CHECK: ldaxr   w[[DEST_REG:[0-9]+]], [x0]
 ; CHECK: orr    [[SCRATCH2_REG:w[0-9]+]], w[[DEST_REG]], [[OLDVAL_REG]]
 ; CHECK-NOT: stlxr [[SCRATCH2_REG]], [[SCRATCH2_REG]]
 ; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x0]
 ; CHECK: cbnz   [[SCRATCH_REG]], [[TRYBB]]
 ; CHECK: mov    x0, x[[DEST_REG]]
   %val = atomicrmw or i32* %p, i32 5 seq_cst
   ret i32 %val
 }
 
 define i64 @fetch_and_or_64(i64* %p) #0 {
+; OUTLINE-ATOMICS: bl __aarch64_ldset8_relax
 ; CHECK: fetch_and_or_64:
 ; CHECK: mov    x[[ADDR:[0-9]+]], x0
 ; CHECK: [[TRYBB:.?LBB[0-9_]+]]:
 ; CHECK: ldxr   [[DEST_REG:x[0-9]+]], [x[[ADDR]]]
 ; CHECK: orr    [[SCRATCH2_REG:x[0-9]+]], [[DEST_REG]], #0x7
 ; CHECK: stxr   [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x[[ADDR]]]
 ; CHECK: cbnz   [[SCRATCH_REG]], [[TRYBB]]
   %val = atomicrmw or i64* %p, i64 7 monotonic
; CHECK: stur {{w[0-9]+}}, [x0, #-256]
   store atomic i32 %val, i32* %ptr_random unordered, align 4
 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
 ; CHECK: str {{w[0-9]+}}, [x[[ADDR]]]
 
   ret void
 }
 
 define void @atomic_store_relaxed_64(i64* %p, i32 %off32, i64 %val) #0 {
+; OUTLINE-ATOMICS: bl __aarch64_ldadd4_acq_rel
 ; CHECK-LABEL: atomic_store_relaxed_64:
   %ptr_unsigned = getelementptr i64, i64* %p, i32 4095
   store atomic i64 %val, i64* %ptr_unsigned monotonic, align 8
 ; CHECK: str {{x[0-9]+}}, [x0, #32760]
 
   %ptr_regoff = getelementptr i64, i64* %p, i32 %off32
   store atomic i64 %val, i64* %ptr_regoff unordered, align 8
 ; CHECK: str {{x[0-9]+}}, [x0, w1, sxtw #3]

llvm/test/CodeGen/AArch64/arm64_32-atomics.ll

 ; RUN: llc -mtriple=arm64_32-apple-ios7.0 -o - %s | FileCheck %s
+; RUN: llc -mtriple=arm64_32-apple-ios7.0 -mattr=+outline-atomics -o - %s | FileCheck %s -check-prefix=OUTLINE-ATOMICS
 
 define i8 @test_load_8(i8* %addr) {
 ; CHECK-LABAL: test_load_8:
 ; CHECK: ldarb w0, [x0]
   %val = load atomic i8, i8* %addr seq_cst, align 1
   ret i8 %val
 }
 

 ; CHECK: stlxr [[TMP:w[0-9]+]], x1, [x0]
 ; CHECK: mov w0, [[TMP]]
 
   %success = call i32 @llvm.aarch64.stlxr.p0i64(i64 %val, i64* %addr)
   ret i32 %success
 }
 
 define {i8*, i1} @test_cmpxchg_ptr(i8** %addr, i8* %cmp, i8* %new) {
+; OUTLINE-ATOMICS: bl ___aarch64_cas4_acq_rel
 ; CHECK-LABEL: test_cmpxchg_ptr:
 ; CHECK: [[LOOP:LBB[0-9]+_[0-9]+]]:
 ; CHECK:     ldaxr [[OLD:w[0-9]+]], [x0]
 ; CHECK:     cmp [[OLD]], w1
 ; CHECK:     b.ne [[DONE:LBB[0-9]+_[0-9]+]]
 ; CHECK:     stlxr [[SUCCESS:w[0-9]+]], w2, [x0]
 ; CHECK:     cbnz [[SUCCESS]], [[LOOP]]
 

llvm/test/CodeGen/AArch64/atomic-ops-lse.ll

 ; RUN: llc -mtriple=aarch64-none-linux-gnu -disable-post-ra -verify-machineinstrs -mattr=+lse < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-none-linux-gnu -disable-post-ra -verify-machineinstrs -mattr=+lse -mattr=+outline-atomics < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-none-linux-gnu -disable-post-ra -verify-machineinstrs -mattr=+outline-atomics < %s | FileCheck %s --check-prefix=OUTLINE-ATOMICS
 ; RUN: llc -mtriple=aarch64_be-none-linux-gnu -disable-post-ra -verify-machineinstrs -mattr=+lse < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-none-linux-gnu -disable-post-ra -verify-machineinstrs -mattr=+lse < %s | FileCheck %s --check-prefix=CHECK-REG
 ; RUN: llc -mtriple=aarch64-none-linux-gnu -disable-post-ra -verify-machineinstrs -mcpu=saphira < %s | FileCheck %s
 
 ; Point of CHECK-REG is to make sure UNPREDICTABLE instructions aren't created
 ; (i.e. reusing a register for status & data in store exclusive).
 ; CHECK-REG-NOT: stlxrb w[[NEW:[0-9]+]], w[[NEW]], [x{{[0-9]+}}]
 ; CHECK-REG-NOT: stlxrb w[[NEW:[0-9]+]], x[[NEW]], [x{{[0-9]+}}]
 
 @var8 = global i8 0
 @var16 = global i16 0
 @var32 = global i32 0
 @var64 = global i64 0
 @var128 = global i128 0
 
 define i8 @test_atomic_load_add_i8(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i8:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i8:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd1_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw add i8* @var8, i8 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldaddalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_add_i16(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i16:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i16:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd2_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw add i16* @var16, i16 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldaddalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_add_i32(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i32:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i32:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw add i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldaddal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_add_i64(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i64:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i64:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw add i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldaddal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_add_i32_noret(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i32_noret:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i32_noret:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw add i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldaddal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_add_i64_noret(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i64_noret:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i64_noret:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw add i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldaddal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_or_i8(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i8:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i8:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset1_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw or i8* @var8, i8 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldsetalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_or_i16(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i16:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i16:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset2_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw or i16* @var16, i16 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldsetalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_or_i32(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i32:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i32:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw or i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldsetal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_or_i64(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i64:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i64:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw or i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldsetal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_or_i32_noret(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i32_noret:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i32_noret:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw or i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldsetal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_or_i64_noret(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i64_noret:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i64_noret:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw or i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldsetal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_xor_i8(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i8:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i8:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor1_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xor i8* @var8, i8 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldeoralb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_xor_i16(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i16:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i16:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor2_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xor i16* @var16, i16 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldeoralh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_xor_i32(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i32:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i32:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xor i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldeoral w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_xor_i64(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i64:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i64:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xor i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldeoral x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_xor_i32_noret(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i32_noret:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i32_noret:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw xor i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldeoral w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_xor_i64_noret(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i64_noret:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i64_noret:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw xor i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldeoral x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_min_i8(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i8:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i8:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var8
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:  .LBB18_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxrb w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    sxtb w8, w10
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, sxtb
+; OUTLINE-ATOMICS-NEXT:    csel w10, w10, w0, le
+; OUTLINE-ATOMICS-NEXT:    stlxrb w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB18_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw min i8* @var8, i8 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldsminalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_min_i16(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i16:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i16:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var16
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:  .LBB19_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxrh w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    sxth w8, w10
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, sxth
+; OUTLINE-ATOMICS-NEXT:    csel w10, w10, w0, le
+; OUTLINE-ATOMICS-NEXT:    stlxrh w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB19_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw min i16* @var16, i16 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldsminalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_min_i32(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i32:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i32:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var32
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB20_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, le
+; OUTLINE-ATOMICS-NEXT:    stlxr w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB20_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw min i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldsminal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_min_i64(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i64:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i64:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var64
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB21_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr x8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp x8, x0
+; OUTLINE-ATOMICS-NEXT:    csel x10, x8, x0, le
+; OUTLINE-ATOMICS-NEXT:    stlxr w11, x10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB21_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov x0, x8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw min i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldsminal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_min_i32_noret(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i32_noret:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i32_noret:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var32
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB22_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp w9, w0
+; OUTLINE-ATOMICS-NEXT:    csel w9, w9, w0, le
+; OUTLINE-ATOMICS-NEXT:    stlxr w10, w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB22_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw min i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldsminal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_min_i64_noret(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i64_noret:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i64_noret:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var64
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB23_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp x9, x0
+; OUTLINE-ATOMICS-NEXT:    csel x9, x9, x0, le
+; OUTLINE-ATOMICS-NEXT:    stlxr w10, x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB23_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw min i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldsminal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_umin_i8(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i8:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i8:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var8
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:  .LBB24_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxrb w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, uxtb
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, ls
+; OUTLINE-ATOMICS-NEXT:    stlxrb w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB24_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umin i8* @var8, i8 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: lduminalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_umin_i16(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i16:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i16:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var16
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:  .LBB25_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxrh w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, uxth
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, ls
+; OUTLINE-ATOMICS-NEXT:    stlxrh w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB25_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umin i16* @var16, i16 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: lduminalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_umin_i32(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i32:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i32:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var32
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB26_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, ls
+; OUTLINE-ATOMICS-NEXT:    stlxr w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB26_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umin i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: lduminal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_umin_i64(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i64:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i64:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var64
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB27_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr x8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp x8, x0
+; OUTLINE-ATOMICS-NEXT:    csel x10, x8, x0, ls
+; OUTLINE-ATOMICS-NEXT:    stlxr w11, x10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB27_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov x0, x8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umin i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: lduminal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_umin_i32_noret(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i32_noret:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i32_noret:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var32
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB28_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp w9, w0
+; OUTLINE-ATOMICS-NEXT:    csel w9, w9, w0, ls
+; OUTLINE-ATOMICS-NEXT:    stlxr w10, w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB28_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw umin i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: lduminal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_umin_i64_noret(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i64_noret:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i64_noret:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var64
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB29_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp x9, x0
+; OUTLINE-ATOMICS-NEXT:    csel x9, x9, x0, ls
+; OUTLINE-ATOMICS-NEXT:    stlxr w10, x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB29_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw umin i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: lduminal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_max_i8(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i8:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i8:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var8
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:  .LBB30_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxrb w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    sxtb w8, w10
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, sxtb
+; OUTLINE-ATOMICS-NEXT:    csel w10, w10, w0, gt
+; OUTLINE-ATOMICS-NEXT:    stlxrb w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB30_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw max i8* @var8, i8 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldsmaxalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_max_i16(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i16:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i16:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var16
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:  .LBB31_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxrh w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    sxth w8, w10
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, sxth
+; OUTLINE-ATOMICS-NEXT:    csel w10, w10, w0, gt
+; OUTLINE-ATOMICS-NEXT:    stlxrh w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB31_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw max i16* @var16, i16 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldsmaxalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_max_i32(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i32:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i32:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var32
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB32_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, gt
+; OUTLINE-ATOMICS-NEXT:    stlxr w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB32_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw max i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldsmaxal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_max_i64(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i64:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i64:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var64
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB33_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr x8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp x8, x0
+; OUTLINE-ATOMICS-NEXT:    csel x10, x8, x0, gt
+; OUTLINE-ATOMICS-NEXT:    stlxr w11, x10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB33_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov x0, x8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw max i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldsmaxal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_max_i32_noret(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i32_noret:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i32_noret:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var32
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB34_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp w9, w0
+; OUTLINE-ATOMICS-NEXT:    csel w9, w9, w0, gt
+; OUTLINE-ATOMICS-NEXT:    stlxr w10, w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB34_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw max i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldsmaxal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_max_i64_noret(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i64_noret:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i64_noret:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var64
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB35_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp x9, x0
+; OUTLINE-ATOMICS-NEXT:    csel x9, x9, x0, gt
+; OUTLINE-ATOMICS-NEXT:    stlxr w10, x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB35_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw max i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldsmaxal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_umax_i8(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i8:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i8:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var8
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:  .LBB36_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxrb w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, uxtb
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, hi
+; OUTLINE-ATOMICS-NEXT:    stlxrb w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB36_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umax i8* @var8, i8 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldumaxalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_umax_i16(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i16:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i16:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var16
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:  .LBB37_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxrh w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, uxth
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, hi
+; OUTLINE-ATOMICS-NEXT:    stlxrh w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB37_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umax i16* @var16, i16 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldumaxalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_umax_i32(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i32:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i32:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var32
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB38_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, hi
+; OUTLINE-ATOMICS-NEXT:    stlxr w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB38_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umax i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldumaxal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_umax_i64(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i64:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i64:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var64
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB39_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr x8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp x8, x0
+; OUTLINE-ATOMICS-NEXT:    csel x10, x8, x0, hi
+; OUTLINE-ATOMICS-NEXT:    stlxr w11, x10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB39_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov x0, x8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umax i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldumaxal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_umax_i32_noret(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i32_noret:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i32_noret:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var32
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB40_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp w9, w0
+; OUTLINE-ATOMICS-NEXT:    csel w9, w9, w0, hi
+; OUTLINE-ATOMICS-NEXT:    stlxr w10, w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB40_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw umax i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldumaxal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_umax_i64_noret(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i64_noret:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i64_noret:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var64
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB41_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp x9, x0
+; OUTLINE-ATOMICS-NEXT:    csel x9, x9, x0, hi
+; OUTLINE-ATOMICS-NEXT:    stlxr w10, x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB41_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw umax i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldumaxal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i8:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i8:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp1_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xchg i8* @var8, i8 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: swpalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_xchg_i16(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i16:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i16:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp2_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xchg i16* @var16, i16 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: swpalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i32:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i32:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xchg i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: swpal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_xchg_i64(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i64:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i64:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xchg i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: swpal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_xchg_i32_noret(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i32_noret:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i32_noret:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw xchg i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: swpal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret void
 }
 
 define void @test_atomic_load_xchg_i64_noret(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i64_noret:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i64_noret:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw xchg i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: swpal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret void
 }
 
 define i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind {
 ; CHECK-LABEL: test_atomic_cmpxchg_i8:
+; OUTLINE-ATOMICS-LABEL: test_atomic_cmpxchg_i8:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x2, var8
+; OUTLINE-ATOMICS-NEXT:    add x2, x2, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_cas1_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %pair = cmpxchg i8* @var8, i8 %wanted, i8 %new acquire acquire
    %old = extractvalue { i8, i1 } %pair, 0
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK-NEXT: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 ; CHECK-NEXT: casab w0, w1, [x[[ADDR]]]
 ; CHECK-NEXT: ret
 
    ret i8 %old
 }
 
 define i1 @test_atomic_cmpxchg_i8_1(i8 %wanted, i8 %new) nounwind {
 ; CHECK-LABEL: test_atomic_cmpxchg_i8_1:
+; OUTLINE-ATOMICS-LABEL: test_atomic_cmpxchg_i8_1:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mov w19, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x2, var8
+; OUTLINE-ATOMICS-NEXT:    add x2, x2, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_cas1_acq
+; OUTLINE-ATOMICS-NEXT:    cmp w0, w19, uxtb
+; OUTLINE-ATOMICS-NEXT:    cset w0, eq
+; OUTLINE-ATOMICS-NEXT:    ldp x30, x19, [sp], #16 // 16-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %pair = cmpxchg i8* @var8, i8 %wanted, i8 %new acquire acquire
    %success = extractvalue { i8, i1 } %pair, 1
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: casab w[[NEW:[0-9]+]], w1, [x[[ADDR]]]
 ; CHECK-NEXT: cmp w[[NEW]], w0, uxtb
 ; CHECK-NEXT: cset w0, eq
 ; CHECK-NEXT: ret
    ret i1 %success
 }
 
 define i16 @test_atomic_cmpxchg_i16(i16 %wanted, i16 %new) nounwind {
 ; CHECK-LABEL: test_atomic_cmpxchg_i16:
+; OUTLINE-ATOMICS-LABEL: test_atomic_cmpxchg_i16:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x2, var16
+; OUTLINE-ATOMICS-NEXT:    add x2, x2, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_cas2_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %pair = cmpxchg i16* @var16, i16 %wanted, i16 %new acquire acquire
    %old = extractvalue { i16, i1 } %pair, 0
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK-NEXT: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 ; CHECK-NEXT: casah w0, w1, [x[[ADDR]]]
 ; CHECK-NEXT: ret
 
    ret i16 %old
 }
 
 define i1 @test_atomic_cmpxchg_i16_1(i16 %wanted, i16 %new) nounwind {
 ; CHECK-LABEL: test_atomic_cmpxchg_i16_1:
+; OUTLINE-ATOMICS-LABEL: test_atomic_cmpxchg_i16_1:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mov w19, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x2, var16
+; OUTLINE-ATOMICS-NEXT:    add x2, x2, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_cas2_acq
+; OUTLINE-ATOMICS-NEXT:    cmp w0, w19, uxth
+; OUTLINE-ATOMICS-NEXT:    cset w0, eq
+; OUTLINE-ATOMICS-NEXT:    ldp x30, x19, [sp], #16 // 16-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %pair = cmpxchg i16* @var16, i16 %wanted, i16 %new acquire acquire
    %success = extractvalue { i16, i1 } %pair, 1
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK-NEXT: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: casah w[[NEW:[0-9]+]], w1, [x[[ADDR]]]
 ; CHECK-NEXT: cmp w[[NEW]], w0, uxth
 ; CHECK-NEXT: cset w0, eq
 ; CHECK-NEXT: ret
 
    ret i1 %success
 }
 
 define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind {
 ; CHECK-LABEL: test_atomic_cmpxchg_i32:
+; OUTLINE-ATOMICS-LABEL: test_atomic_cmpxchg_i32:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x2, var32
+; OUTLINE-ATOMICS-NEXT:    add x2, x2, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_cas4_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %pair = cmpxchg i32* @var32, i32 %wanted, i32 %new acquire acquire
    %old = extractvalue { i32, i1 } %pair, 0
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: casa w0, w1, [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind {
 ; CHECK-LABEL: test_atomic_cmpxchg_i64:
+; OUTLINE-ATOMICS-LABEL: test_atomic_cmpxchg_i64:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x2, var64
+; OUTLINE-ATOMICS-NEXT:    add x2, x2, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_cas8_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %pair = cmpxchg i64* @var64, i64 %wanted, i64 %new acquire acquire
    %old = extractvalue { i64, i1 } %pair, 0
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: casa x0, x1, [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define i128 @test_atomic_cmpxchg_i128(i128 %wanted, i128 %new) nounwind {
 ; CHECK-LABEL: test_atomic_cmpxchg_i128:
+; OUTLINE-ATOMICS-LABEL: test_atomic_cmpxchg_i128:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x4, var128
+; OUTLINE-ATOMICS-NEXT:    add x4, x4, :lo12:var128
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_cas16_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %pair = cmpxchg i128* @var128, i128 %wanted, i128 %new acquire acquire
    %old = extractvalue { i128, i1 } %pair, 0
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var128
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var128
 
 ; CHECK: caspa x0, x1, x2, x3, [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i128 %old
 }
 
 define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i8:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i8:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd1_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw sub i8* @var8, i8 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldaddalb w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i8 %old
 }
 
 define i16 @test_atomic_load_sub_i16(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i16:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i16:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd2_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw sub i16* @var16, i16 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldaddalh w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i16 %old
 }
 
 define i32 @test_atomic_load_sub_i32(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i32:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i32:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw sub i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldaddal w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i32 %old
 }
 
 define i64 @test_atomic_load_sub_i64(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i64:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i64:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg x0, x0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw sub i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: neg x[[NEG:[0-9]+]], x[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldaddal x[[NEG]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i64 %old
 }
 
 define void @test_atomic_load_sub_i32_noret(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i32_noret:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i32_noret:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   atomicrmw sub i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldaddal w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret void
 }
 
 define void @test_atomic_load_sub_i64_noret(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i64_noret:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i64_noret:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg x0, x0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   atomicrmw sub i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: neg x[[NEG:[0-9]+]], x[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldaddal x[[NEG]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret void
 }
 
 define i8 @test_atomic_load_sub_i8_neg_imm() nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i8_neg_imm:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i8_neg_imm:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    mov w0, #1
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd1_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw sub i8* @var8, i8 -1 seq_cst
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 ; CHECK: mov w[[IMM:[0-9]+]], #1
 ; CHECK: ldaddalb w[[IMM]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i8 %old
 }
 
 define i16 @test_atomic_load_sub_i16_neg_imm() nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i16_neg_imm:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i16_neg_imm:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    mov w0, #1
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd2_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw sub i16* @var16, i16 -1 seq_cst
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 ; CHECK: mov w[[IMM:[0-9]+]], #1
 ; CHECK: ldaddalh w[[IMM]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i16 %old
 }
 
 define i32 @test_atomic_load_sub_i32_neg_imm() nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i32_neg_imm:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i32_neg_imm:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    mov w0, #1
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw sub i32* @var32, i32 -1 seq_cst
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 ; CHECK: mov w[[IMM:[0-9]+]], #1
 ; CHECK: ldaddal w[[IMM]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i32 %old
 }
 
 define i64 @test_atomic_load_sub_i64_neg_imm() nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i64_neg_imm:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i64_neg_imm:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    mov w0, #1
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw sub i64* @var64, i64 -1 seq_cst
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 ; CHECK: mov w[[IMM:[0-9]+]], #1
 ; CHECK: ldaddal x[[IMM]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i64 %old
 }
 
 define i8 @test_atomic_load_sub_i8_neg_arg(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i8_neg_arg:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i8_neg_arg:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd1_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %neg = sub i8 0, %offset
   %old = atomicrmw sub i8* @var8, i8 %neg seq_cst
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 ; CHECK: ldaddalb w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i8 %old
 }
 
 define i16 @test_atomic_load_sub_i16_neg_arg(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i16_neg_arg:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i16_neg_arg:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd2_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %neg = sub i16 0, %offset
   %old = atomicrmw sub i16* @var16, i16 %neg seq_cst
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 ; CHECK: ldaddalh w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i16 %old
 }
 
 define i32 @test_atomic_load_sub_i32_neg_arg(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i32_neg_arg:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i32_neg_arg:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %neg = sub i32 0, %offset
   %old = atomicrmw sub i32* @var32, i32 %neg seq_cst
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 ; CHECK: ldaddal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i32 %old
 }
 
 define i64 @test_atomic_load_sub_i64_neg_arg(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i64_neg_arg:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i64_neg_arg:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %neg = sub i64 0, %offset
   %old = atomicrmw sub i64* @var64, i64 %neg seq_cst
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 ; CHECK: ldaddal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i64 %old
 }
 
 define i8 @test_atomic_load_and_i8(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i8:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i8:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr1_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw and i8* @var8, i8 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldclralb w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i8 %old
 }
 
 define i16 @test_atomic_load_and_i16(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i16:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i16:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr2_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw and i16* @var16, i16 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldclralh w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i16 %old
 }
 
 define i32 @test_atomic_load_and_i32(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i32:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i32:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw and i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldclral w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i32 %old
 }
 
 define i64 @test_atomic_load_and_i64(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i64:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i64:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn x0, x0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw and i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: mvn x[[NOT:[0-9]+]], x[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldclral x[[NOT]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i64 %old
 }
 
 define i8 @test_atomic_load_and_i8_inv_imm() nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i8_inv_imm:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i8_inv_imm:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    mov w0, #1
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr1_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw and i8* @var8, i8 -2 seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 ; CHECK: mov w[[CONST:[0-9]+]], #1
 ; CHECK: ldclralb w[[CONST]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i8 %old
 }
 
 define i16 @test_atomic_load_and_i16_inv_imm() nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i16_inv_imm:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i16_inv_imm:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    mov w0, #1
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr2_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw and i16* @var16, i16 -2 seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 ; CHECK: mov w[[CONST:[0-9]+]], #1
 ; CHECK: ldclralh w[[CONST]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i16 %old
 }
 
 define i32 @test_atomic_load_and_i32_inv_imm() nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i32_inv_imm:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i32_inv_imm:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    mov w0, #1
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw and i32* @var32, i32 -2 seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 ; CHECK: mov w[[CONST:[0-9]+]], #1
 ; CHECK: ldclral w[[CONST]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i32 %old
 }
 
 define i64 @test_atomic_load_and_i64_inv_imm() nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i64_inv_imm:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i64_inv_imm:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    mov w0, #1
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw and i64* @var64, i64 -2 seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 ; CHECK: mov w[[CONST:[0-9]+]], #1
 ; CHECK: ldclral x[[CONST]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i64 %old
 }
 
 define i8 @test_atomic_load_and_i8_inv_arg(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i8_inv_arg:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i8_inv_arg:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr1_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %inv = xor i8 %offset, -1
   %old = atomicrmw and i8* @var8, i8 %inv seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 ; CHECK: ldclralb w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i8 %old
 }
 
 define i16 @test_atomic_load_and_i16_inv_arg(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i16_inv_arg:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i16_inv_arg:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr2_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %inv = xor i16 %offset, -1
   %old = atomicrmw and i16* @var16, i16 %inv seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 ; CHECK: ldclralh w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i16 %old
 }
 
 define i32 @test_atomic_load_and_i32_inv_arg(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i32_inv_arg:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i32_inv_arg:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %inv = xor i32 %offset, -1
   %old = atomicrmw and i32* @var32, i32 %inv seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 ; CHECK: ldclral w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i32 %old
 }
 
 define i64 @test_atomic_load_and_i64_inv_arg(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i64_inv_arg:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i64_inv_arg:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %inv = xor i64 %offset, -1
   %old = atomicrmw and i64* @var64, i64 %inv seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 ; CHECK: ldclral x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i64 %old
 }
 
 define void @test_atomic_load_and_i32_noret(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i32_noret:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i32_noret:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   atomicrmw and i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldclral w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_and_i64_noret(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i64_noret:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i64_noret:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn x0, x0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   atomicrmw and i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: mvn x[[NOT:[0-9]+]], x[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldclral x[[NOT]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_add_i8_acq_rel(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i8_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i8_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd1_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw add i8* @var8, i8 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldaddalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_add_i16_acq_rel(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i16_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i16_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd2_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw add i16* @var16, i16 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldaddalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_add_i32_acq_rel(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i32_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i32_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw add i32* @var32, i32 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldaddal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_add_i64_acq_rel(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i64_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i64_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw add i64* @var64, i64 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldaddal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_add_i32_noret_acq_rel(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i32_noret_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i32_noret_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw add i32* @var32, i32 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldaddal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_add_i64_noret_acq_rel(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i64_noret_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i64_noret_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw add i64* @var64, i64 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldaddal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_add_i8_acquire(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i8_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i8_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd1_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw add i8* @var8, i8 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldaddab w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_add_i16_acquire(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i16_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i16_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd2_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw add i16* @var16, i16 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldaddah w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_add_i32_acquire(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i32_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i32_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd4_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw add i32* @var32, i32 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldadda w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_add_i64_acquire(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i64_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i64_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd8_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw add i64* @var64, i64 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldadda x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_add_i32_noret_acquire(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i32_noret_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i32_noret_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd4_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw add i32* @var32, i32 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldadda w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_add_i64_noret_acquire(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i64_noret_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i64_noret_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd8_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw add i64* @var64, i64 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldadda x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_add_i8_monotonic(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i8_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i8_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd1_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw add i8* @var8, i8 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldaddb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_add_i16_monotonic(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i16_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i16_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd2_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw add i16* @var16, i16 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldaddh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_add_i32_monotonic(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i32_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i32_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd4_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw add i32* @var32, i32 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldadd w[[OLD:[0-9]+]], w[[NEW:[0-9,a-z]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_add_i64_monotonic(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i64_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i64_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd8_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw add i64* @var64, i64 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldadd x[[OLD:[0-9]+]], x[[NEW:[0-9,a-z]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_add_i32_noret_monotonic(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i32_noret_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i32_noret_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd4_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw add i32* @var32, i32 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldadd w{{[0-9]+}}, w{{[1-9][0-9]*}}, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_add_i64_noret_monotonic(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i64_noret_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i64_noret_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd8_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw add i64* @var64, i64 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldadd x{{[0-9]}}, x{{[1-9][0-9]*}}, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_add_i8_release(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i8_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i8_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd1_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw add i8* @var8, i8 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldaddlb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_add_i16_release(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i16_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i16_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd2_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw add i16* @var16, i16 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldaddlh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_add_i32_release(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i32_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i32_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd4_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw add i32* @var32, i32 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldaddl w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_add_i64_release(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i64_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i64_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd8_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw add i64* @var64, i64 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldaddl x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_add_i32_noret_release(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i32_noret_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i32_noret_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd4_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw add i32* @var32, i32 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldaddl w{{[0-9]+}}, w{{[1-9][0-9]*}}, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_add_i64_noret_release(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i64_noret_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i64_noret_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd8_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw add i64* @var64, i64 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldaddl x{{[0-9]+}}, x{{[1-9][0-9]*}}, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_add_i8_seq_cst(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i8_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i8_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd1_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw add i8* @var8, i8 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldaddalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_add_i16_seq_cst(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i16_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i16_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd2_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw add i16* @var16, i16 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldaddalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_add_i32_seq_cst(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i32_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i32_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw add i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldaddal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_add_i64_seq_cst(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i64_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i64_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw add i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldaddal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_add_i32_noret_seq_cst(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i32_noret_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i32_noret_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw add i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldaddal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_add_i64_noret_seq_cst(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i64_noret_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_add_i64_noret_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw add i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldaddal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_and_i8_acq_rel(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i8_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i8_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr1_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw and i8* @var8, i8 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldclralb w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i8 %old
 }
 
 define i16 @test_atomic_load_and_i16_acq_rel(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i16_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i16_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr2_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw and i16* @var16, i16 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldclralh w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i16 %old
 }
 
 define i32 @test_atomic_load_and_i32_acq_rel(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i32_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i32_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw and i32* @var32, i32 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldclral w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i32 %old
 }
 
 define i64 @test_atomic_load_and_i64_acq_rel(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i64_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i64_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn x0, x0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw and i64* @var64, i64 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: mvn x[[NOT:[0-9]+]], x[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldclral x[[NOT]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i64 %old
 }
 
 define void @test_atomic_load_and_i32_noret_acq_rel(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i32_noret_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i32_noret_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   atomicrmw and i32* @var32, i32 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldclral w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_and_i64_noret_acq_rel(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i64_noret_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i64_noret_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn x0, x0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   atomicrmw and i64* @var64, i64 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: mvn x[[NOT:[0-9]+]], x[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldclral x[[NOT]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_and_i8_acquire(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i8_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i8_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr1_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw and i8* @var8, i8 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldclrab w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i8 %old
 }
 
 define i16 @test_atomic_load_and_i16_acquire(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i16_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i16_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr2_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw and i16* @var16, i16 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldclrah w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i16 %old
 }
 
 define i32 @test_atomic_load_and_i32_acquire(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i32_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i32_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr4_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw and i32* @var32, i32 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldclra w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i32 %old
 }
 
 define i64 @test_atomic_load_and_i64_acquire(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i64_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i64_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn x0, x0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr8_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw and i64* @var64, i64 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: mvn x[[NOT:[0-9]+]], x[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldclra x[[NOT]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i64 %old
 }
 
 define void @test_atomic_load_and_i32_noret_acquire(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i32_noret_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i32_noret_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr4_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   atomicrmw and i32* @var32, i32 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldclra w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_and_i64_noret_acquire(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i64_noret_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i64_noret_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn x0, x0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr8_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   atomicrmw and i64* @var64, i64 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: mvn x[[NOT:[0-9]+]], x[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldclra x[[NOT]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_and_i8_monotonic(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i8_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i8_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr1_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw and i8* @var8, i8 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldclrb w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i8 %old
 }
 
 define i16 @test_atomic_load_and_i16_monotonic(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i16_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i16_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr2_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw and i16* @var16, i16 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldclrh w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i16 %old
 }
 
 define i32 @test_atomic_load_and_i32_monotonic(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i32_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i32_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr4_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw and i32* @var32, i32 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldclr w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i32 %old
 }
 
 define i64 @test_atomic_load_and_i64_monotonic(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i64_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i64_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn x0, x0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr8_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw and i64* @var64, i64 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: mvn x[[NOT:[0-9]+]], x[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldclr x[[NOT]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i64 %old
 }
 
 define void @test_atomic_load_and_i32_noret_monotonic(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i32_noret_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i32_noret_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr4_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   atomicrmw and i32* @var32, i32 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldclr w{{[0-9]+}}, w[[NEW:[1-9][0-9]*]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_and_i64_noret_monotonic(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i64_noret_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i64_noret_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn x0, x0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr8_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   atomicrmw and i64* @var64, i64 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: mvn x[[NOT:[0-9]+]], x[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldclr x{{[0-9]+}}, x[[NEW:[1-9][0-9]*]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_and_i8_release(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i8_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i8_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr1_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw and i8* @var8, i8 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldclrlb w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i8 %old
 }
 
 define i16 @test_atomic_load_and_i16_release(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i16_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i16_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr2_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw and i16* @var16, i16 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldclrlh w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i16 %old
 }
 
 define i32 @test_atomic_load_and_i32_release(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i32_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i32_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr4_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw and i32* @var32, i32 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldclrl w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i32 %old
 }
 
 define i64 @test_atomic_load_and_i64_release(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i64_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i64_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn x0, x0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr8_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw and i64* @var64, i64 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: mvn x[[NOT:[0-9]+]], x[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldclrl x[[NOT]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i64 %old
 }
 
 define void @test_atomic_load_and_i32_noret_release(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i32_noret_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i32_noret_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr4_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   atomicrmw and i32* @var32, i32 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldclrl w{{[0-9]*}}, w[[NEW:[1-9][0-9]*]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_and_i64_noret_release(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i64_noret_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i64_noret_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn x0, x0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr8_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   atomicrmw and i64* @var64, i64 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: mvn x[[NOT:[0-9]+]], x[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldclrl x{{[0-9]*}}, x[[NEW:[1-9][0-9]*]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_and_i8_seq_cst(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i8_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i8_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr1_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw and i8* @var8, i8 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldclralb w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i8 %old
 }
 
 define i16 @test_atomic_load_and_i16_seq_cst(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i16_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i16_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr2_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw and i16* @var16, i16 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldclralh w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i16 %old
 }
 
 define i32 @test_atomic_load_and_i32_seq_cst(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i32_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i32_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw and i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldclral w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i32 %old
 }
 
 define i64 @test_atomic_load_and_i64_seq_cst(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i64_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i64_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn x0, x0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw and i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: mvn x[[NOT:[0-9]+]], x[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldclral x[[NOT]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i64 %old
 }
 
 define void @test_atomic_load_and_i32_noret_seq_cst(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i32_noret_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i32_noret_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   atomicrmw and i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: mvn w[[NOT:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldclral w[[NOT]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_and_i64_noret_seq_cst(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i64_noret_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_and_i64_noret_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    mvn x0, x0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldclr8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   atomicrmw and i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: mvn x[[NOT:[0-9]+]], x[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldclral x[[NOT]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_cmpxchg_i8_acquire(i8 %wanted, i8 %new) nounwind {
 ; CHECK-LABEL: test_atomic_cmpxchg_i8_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_cmpxchg_i8_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x2, var8
+; OUTLINE-ATOMICS-NEXT:    add x2, x2, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_cas1_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %pair = cmpxchg i8* @var8, i8 %wanted, i8 %new acquire acquire
    %old = extractvalue { i8, i1 } %pair, 0
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: casab w[[NEW:[0-9]+]], w[[OLD:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_cmpxchg_i16_acquire(i16 %wanted, i16 %new) nounwind {
 ; CHECK-LABEL: test_atomic_cmpxchg_i16_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_cmpxchg_i16_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x2, var16
+; OUTLINE-ATOMICS-NEXT:    add x2, x2, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_cas2_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %pair = cmpxchg i16* @var16, i16 %wanted, i16 %new acquire acquire
    %old = extractvalue { i16, i1 } %pair, 0
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: casah w0, w1, [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_cmpxchg_i32_acquire(i32 %wanted, i32 %new) nounwind {
 ; CHECK-LABEL: test_atomic_cmpxchg_i32_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_cmpxchg_i32_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x2, var32
+; OUTLINE-ATOMICS-NEXT:    add x2, x2, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_cas4_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %pair = cmpxchg i32* @var32, i32 %wanted, i32 %new acquire acquire
    %old = extractvalue { i32, i1 } %pair, 0
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: casa w0, w1, [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_cmpxchg_i64_acquire(i64 %wanted, i64 %new) nounwind {
 ; CHECK-LABEL: test_atomic_cmpxchg_i64_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_cmpxchg_i64_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x2, var64
+; OUTLINE-ATOMICS-NEXT:    add x2, x2, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_cas8_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %pair = cmpxchg i64* @var64, i64 %wanted, i64 %new acquire acquire
    %old = extractvalue { i64, i1 } %pair, 0
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: casa x0, x1, [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define i128 @test_atomic_cmpxchg_i128_acquire(i128 %wanted, i128 %new) nounwind {
 ; CHECK-LABEL: test_atomic_cmpxchg_i128_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_cmpxchg_i128_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x4, var128
+; OUTLINE-ATOMICS-NEXT:    add x4, x4, :lo12:var128
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_cas16_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %pair = cmpxchg i128* @var128, i128 %wanted, i128 %new acquire acquire
    %old = extractvalue { i128, i1 } %pair, 0
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var128
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var128
 
 ; CHECK: caspa x0, x1, x2, x3, [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i128 %old
 }
 
 define i8 @test_atomic_cmpxchg_i8_monotonic(i8 %wanted, i8 %new) nounwind {
 ; CHECK-LABEL: test_atomic_cmpxchg_i8_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_cmpxchg_i8_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x2, var8
+; OUTLINE-ATOMICS-NEXT:    add x2, x2, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_cas1_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %pair = cmpxchg i8* @var8, i8 %wanted, i8 %new monotonic monotonic
    %old = extractvalue { i8, i1 } %pair, 0
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: casb w[[NEW:[0-9]+]], w[[OLD:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_cmpxchg_i16_monotonic(i16 %wanted, i16 %new) nounwind {
 ; CHECK-LABEL: test_atomic_cmpxchg_i16_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_cmpxchg_i16_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x2, var16
+; OUTLINE-ATOMICS-NEXT:    add x2, x2, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_cas2_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %pair = cmpxchg i16* @var16, i16 %wanted, i16 %new monotonic monotonic
    %old = extractvalue { i16, i1 } %pair, 0
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: cash w0, w1, [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_cmpxchg_i32_monotonic(i32 %wanted, i32 %new) nounwind {
 ; CHECK-LABEL: test_atomic_cmpxchg_i32_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_cmpxchg_i32_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x2, var32
+; OUTLINE-ATOMICS-NEXT:    add x2, x2, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_cas4_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %pair = cmpxchg i32* @var32, i32 %wanted, i32 %new monotonic monotonic
    %old = extractvalue { i32, i1 } %pair, 0
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: cas w0, w1, [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_cmpxchg_i64_monotonic(i64 %wanted, i64 %new) nounwind {
 ; CHECK-LABEL: test_atomic_cmpxchg_i64_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_cmpxchg_i64_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x2, var64
+; OUTLINE-ATOMICS-NEXT:    add x2, x2, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_cas8_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %pair = cmpxchg i64* @var64, i64 %wanted, i64 %new monotonic monotonic
    %old = extractvalue { i64, i1 } %pair, 0
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: cas x0, x1, [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define i128 @test_atomic_cmpxchg_i128_monotonic(i128 %wanted, i128 %new) nounwind {
 ; CHECK-LABEL: test_atomic_cmpxchg_i128_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_cmpxchg_i128_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x4, var128
+; OUTLINE-ATOMICS-NEXT:    add x4, x4, :lo12:var128
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_cas16_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %pair = cmpxchg i128* @var128, i128 %wanted, i128 %new monotonic monotonic
    %old = extractvalue { i128, i1 } %pair, 0
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var128
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var128
 
 ; CHECK: casp x0, x1, x2, x3, [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i128 %old
 }
 
 define i8 @test_atomic_cmpxchg_i8_seq_cst(i8 %wanted, i8 %new) nounwind {
 ; CHECK-LABEL: test_atomic_cmpxchg_i8_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_cmpxchg_i8_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x2, var8
+; OUTLINE-ATOMICS-NEXT:    add x2, x2, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_cas1_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %pair = cmpxchg i8* @var8, i8 %wanted, i8 %new seq_cst seq_cst
    %old = extractvalue { i8, i1 } %pair, 0
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: casalb w[[NEW:[0-9]+]], w[[OLD:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_cmpxchg_i16_seq_cst(i16 %wanted, i16 %new) nounwind {
 ; CHECK-LABEL: test_atomic_cmpxchg_i16_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_cmpxchg_i16_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x2, var16
+; OUTLINE-ATOMICS-NEXT:    add x2, x2, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_cas2_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %pair = cmpxchg i16* @var16, i16 %wanted, i16 %new seq_cst seq_cst
    %old = extractvalue { i16, i1 } %pair, 0
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: casalh w0, w1, [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_cmpxchg_i32_seq_cst(i32 %wanted, i32 %new) nounwind {
 ; CHECK-LABEL: test_atomic_cmpxchg_i32_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_cmpxchg_i32_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x2, var32
+; OUTLINE-ATOMICS-NEXT:    add x2, x2, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_cas4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %pair = cmpxchg i32* @var32, i32 %wanted, i32 %new seq_cst seq_cst
    %old = extractvalue { i32, i1 } %pair, 0
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: casal w0, w1, [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_cmpxchg_i64_seq_cst(i64 %wanted, i64 %new) nounwind {
 ; CHECK-LABEL: test_atomic_cmpxchg_i64_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_cmpxchg_i64_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x2, var64
+; OUTLINE-ATOMICS-NEXT:    add x2, x2, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_cas8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %pair = cmpxchg i64* @var64, i64 %wanted, i64 %new seq_cst seq_cst
    %old = extractvalue { i64, i1 } %pair, 0
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: casal x0, x1, [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define i128 @test_atomic_cmpxchg_i128_seq_cst(i128 %wanted, i128 %new) nounwind {
 ; CHECK-LABEL: test_atomic_cmpxchg_i128_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_cmpxchg_i128_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x4, var128
+; OUTLINE-ATOMICS-NEXT:    add x4, x4, :lo12:var128
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_cas16_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %pair = cmpxchg i128* @var128, i128 %wanted, i128 %new seq_cst seq_cst
    %old = extractvalue { i128, i1 } %pair, 0
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var128
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var128
 
 ; CHECK: caspal x0, x1, x2, x3, [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i128 %old
 }
 
 define i8 @test_atomic_load_max_i8_acq_rel(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i8_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i8_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var8
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:  .LBB158_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxrb w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    sxtb w8, w10
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, sxtb
+; OUTLINE-ATOMICS-NEXT:    csel w10, w10, w0, gt
+; OUTLINE-ATOMICS-NEXT:    stlxrb w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB158_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw max i8* @var8, i8 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldsmaxalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_max_i16_acq_rel(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i16_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i16_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var16
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:  .LBB159_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxrh w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    sxth w8, w10
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, sxth
+; OUTLINE-ATOMICS-NEXT:    csel w10, w10, w0, gt
+; OUTLINE-ATOMICS-NEXT:    stlxrh w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB159_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw max i16* @var16, i16 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldsmaxalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_max_i32_acq_rel(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i32_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i32_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var32
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB160_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, gt
+; OUTLINE-ATOMICS-NEXT:    stlxr w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB160_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw max i32* @var32, i32 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldsmaxal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_max_i64_acq_rel(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i64_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i64_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var64
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB161_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr x8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp x8, x0
+; OUTLINE-ATOMICS-NEXT:    csel x10, x8, x0, gt
+; OUTLINE-ATOMICS-NEXT:    stlxr w11, x10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB161_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov x0, x8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw max i64* @var64, i64 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldsmaxal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_max_i32_noret_acq_rel(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i32_noret_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i32_noret_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var32
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB162_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp w9, w0
+; OUTLINE-ATOMICS-NEXT:    csel w9, w9, w0, gt
+; OUTLINE-ATOMICS-NEXT:    stlxr w10, w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB162_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw max i32* @var32, i32 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldsmaxal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_max_i64_noret_acq_rel(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i64_noret_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i64_noret_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var64
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB163_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp x9, x0
+; OUTLINE-ATOMICS-NEXT:    csel x9, x9, x0, gt
+; OUTLINE-ATOMICS-NEXT:    stlxr w10, x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB163_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw max i64* @var64, i64 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldsmaxal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_max_i8_acquire(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i8_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i8_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var8
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:  .LBB164_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxrb w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    sxtb w8, w10
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, sxtb
+; OUTLINE-ATOMICS-NEXT:    csel w10, w10, w0, gt
+; OUTLINE-ATOMICS-NEXT:    stxrb w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB164_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw max i8* @var8, i8 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldsmaxab w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_max_i16_acquire(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i16_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i16_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var16
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:  .LBB165_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxrh w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    sxth w8, w10
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, sxth
+; OUTLINE-ATOMICS-NEXT:    csel w10, w10, w0, gt
+; OUTLINE-ATOMICS-NEXT:    stxrh w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB165_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw max i16* @var16, i16 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldsmaxah w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_max_i32_acquire(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i32_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i32_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var32
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB166_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, gt
+; OUTLINE-ATOMICS-NEXT:    stxr w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB166_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw max i32* @var32, i32 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldsmaxa w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_max_i64_acquire(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i64_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i64_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var64
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB167_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr x8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp x8, x0
+; OUTLINE-ATOMICS-NEXT:    csel x10, x8, x0, gt
+; OUTLINE-ATOMICS-NEXT:    stxr w11, x10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB167_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov x0, x8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw max i64* @var64, i64 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldsmaxa x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_max_i32_noret_acquire(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i32_noret_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i32_noret_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var32
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB168_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp w9, w0
+; OUTLINE-ATOMICS-NEXT:    csel w9, w9, w0, gt
+; OUTLINE-ATOMICS-NEXT:    stxr w10, w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB168_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw max i32* @var32, i32 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldsmaxa w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_max_i64_noret_acquire(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i64_noret_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i64_noret_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var64
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB169_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp x9, x0
+; OUTLINE-ATOMICS-NEXT:    csel x9, x9, x0, gt
+; OUTLINE-ATOMICS-NEXT:    stxr w10, x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB169_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw max i64* @var64, i64 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldsmaxa x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_max_i8_monotonic(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i8_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i8_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var8
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:  .LBB170_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxrb w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    sxtb w8, w10
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, sxtb
+; OUTLINE-ATOMICS-NEXT:    csel w10, w10, w0, gt
+; OUTLINE-ATOMICS-NEXT:    stxrb w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB170_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw max i8* @var8, i8 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldsmaxb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_max_i16_monotonic(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i16_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i16_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var16
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:  .LBB171_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxrh w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    sxth w8, w10
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, sxth
+; OUTLINE-ATOMICS-NEXT:    csel w10, w10, w0, gt
+; OUTLINE-ATOMICS-NEXT:    stxrh w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB171_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw max i16* @var16, i16 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldsmaxh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_max_i32_monotonic(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i32_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i32_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var32
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB172_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxr w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, gt
+; OUTLINE-ATOMICS-NEXT:    stxr w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB172_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw max i32* @var32, i32 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldsmax w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_max_i64_monotonic(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i64_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i64_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var64
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB173_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxr x8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp x8, x0
+; OUTLINE-ATOMICS-NEXT:    csel x10, x8, x0, gt
+; OUTLINE-ATOMICS-NEXT:    stxr w11, x10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB173_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov x0, x8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw max i64* @var64, i64 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldsmax x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_max_i32_noret_monotonic(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i32_noret_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i32_noret_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var32
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB174_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxr w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp w9, w0
+; OUTLINE-ATOMICS-NEXT:    csel w9, w9, w0, gt
+; OUTLINE-ATOMICS-NEXT:    stxr w10, w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB174_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw max i32* @var32, i32 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldsmax w{{[0-9]+}}, w{{[1-9][0-9]*}}, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_max_i64_noret_monotonic(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i64_noret_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i64_noret_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var64
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB175_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxr x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp x9, x0
+; OUTLINE-ATOMICS-NEXT:    csel x9, x9, x0, gt
+; OUTLINE-ATOMICS-NEXT:    stxr w10, x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB175_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw max i64* @var64, i64 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldsmax x{{[0-9]+}}, x{{[1-9][0-9]*}}, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_max_i8_release(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i8_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i8_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var8
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:  .LBB176_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxrb w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    sxtb w8, w10
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, sxtb
+; OUTLINE-ATOMICS-NEXT:    csel w10, w10, w0, gt
+; OUTLINE-ATOMICS-NEXT:    stlxrb w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB176_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw max i8* @var8, i8 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldsmaxlb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_max_i16_release(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i16_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i16_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var16
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:  .LBB177_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxrh w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    sxth w8, w10
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, sxth
+; OUTLINE-ATOMICS-NEXT:    csel w10, w10, w0, gt
+; OUTLINE-ATOMICS-NEXT:    stlxrh w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB177_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw max i16* @var16, i16 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldsmaxlh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_max_i32_release(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i32_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i32_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var32
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB178_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxr w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, gt
+; OUTLINE-ATOMICS-NEXT:    stlxr w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB178_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw max i32* @var32, i32 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldsmaxl w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_max_i64_release(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i64_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i64_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var64
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB179_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxr x8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp x8, x0
+; OUTLINE-ATOMICS-NEXT:    csel x10, x8, x0, gt
+; OUTLINE-ATOMICS-NEXT:    stlxr w11, x10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB179_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov x0, x8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw max i64* @var64, i64 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldsmaxl x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_max_i32_noret_release(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i32_noret_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i32_noret_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var32
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB180_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxr w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp w9, w0
+; OUTLINE-ATOMICS-NEXT:    csel w9, w9, w0, gt
+; OUTLINE-ATOMICS-NEXT:    stlxr w10, w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB180_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw max i32* @var32, i32 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldsmaxl w{{[0-9]+}}, w{{[1-9][0-9]*}}, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_max_i64_noret_release(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i64_noret_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i64_noret_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var64
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB181_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxr x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp x9, x0
+; OUTLINE-ATOMICS-NEXT:    csel x9, x9, x0, gt
+; OUTLINE-ATOMICS-NEXT:    stlxr w10, x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB181_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw max i64* @var64, i64 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldsmaxl x{{[0-9]+}}, x{{[1-9][0-9]*}}, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_max_i8_seq_cst(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i8_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i8_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var8
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:  .LBB182_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxrb w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    sxtb w8, w10
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, sxtb
+; OUTLINE-ATOMICS-NEXT:    csel w10, w10, w0, gt
+; OUTLINE-ATOMICS-NEXT:    stlxrb w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB182_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw max i8* @var8, i8 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldsmaxalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_max_i16_seq_cst(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i16_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i16_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var16
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:  .LBB183_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxrh w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    sxth w8, w10
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, sxth
+; OUTLINE-ATOMICS-NEXT:    csel w10, w10, w0, gt
+; OUTLINE-ATOMICS-NEXT:    stlxrh w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB183_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw max i16* @var16, i16 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldsmaxalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_max_i32_seq_cst(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i32_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i32_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var32
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB184_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, gt
+; OUTLINE-ATOMICS-NEXT:    stlxr w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB184_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw max i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldsmaxal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_max_i64_seq_cst(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i64_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i64_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var64
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB185_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr x8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp x8, x0
+; OUTLINE-ATOMICS-NEXT:    csel x10, x8, x0, gt
+; OUTLINE-ATOMICS-NEXT:    stlxr w11, x10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB185_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov x0, x8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw max i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldsmaxal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_max_i32_noret_seq_cst(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i32_noret_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i32_noret_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var32
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB186_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp w9, w0
+; OUTLINE-ATOMICS-NEXT:    csel w9, w9, w0, gt
+; OUTLINE-ATOMICS-NEXT:    stlxr w10, w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB186_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw max i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldsmaxal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_max_i64_noret_seq_cst(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i64_noret_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_max_i64_noret_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var64
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB187_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp x9, x0
+; OUTLINE-ATOMICS-NEXT:    csel x9, x9, x0, gt
+; OUTLINE-ATOMICS-NEXT:    stlxr w10, x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB187_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw max i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldsmaxal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_min_i8_acq_rel(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i8_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i8_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var8
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:  .LBB188_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxrb w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    sxtb w8, w10
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, sxtb
+; OUTLINE-ATOMICS-NEXT:    csel w10, w10, w0, le
+; OUTLINE-ATOMICS-NEXT:    stlxrb w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB188_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw min i8* @var8, i8 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldsminalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_min_i16_acq_rel(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i16_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i16_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var16
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:  .LBB189_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxrh w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    sxth w8, w10
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, sxth
+; OUTLINE-ATOMICS-NEXT:    csel w10, w10, w0, le
+; OUTLINE-ATOMICS-NEXT:    stlxrh w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB189_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw min i16* @var16, i16 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldsminalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_min_i32_acq_rel(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i32_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i32_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var32
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB190_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, le
+; OUTLINE-ATOMICS-NEXT:    stlxr w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB190_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw min i32* @var32, i32 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldsminal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_min_i64_acq_rel(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i64_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i64_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var64
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB191_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr x8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp x8, x0
+; OUTLINE-ATOMICS-NEXT:    csel x10, x8, x0, le
+; OUTLINE-ATOMICS-NEXT:    stlxr w11, x10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB191_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov x0, x8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw min i64* @var64, i64 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldsminal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_min_i32_noret_acq_rel(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i32_noret_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i32_noret_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var32
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB192_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp w9, w0
+; OUTLINE-ATOMICS-NEXT:    csel w9, w9, w0, le
+; OUTLINE-ATOMICS-NEXT:    stlxr w10, w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB192_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw min i32* @var32, i32 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldsminal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_min_i64_noret_acq_rel(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i64_noret_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i64_noret_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var64
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB193_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp x9, x0
+; OUTLINE-ATOMICS-NEXT:    csel x9, x9, x0, le
+; OUTLINE-ATOMICS-NEXT:    stlxr w10, x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB193_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw min i64* @var64, i64 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldsminal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_min_i8_acquire(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i8_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i8_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var8
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:  .LBB194_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxrb w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    sxtb w8, w10
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, sxtb
+; OUTLINE-ATOMICS-NEXT:    csel w10, w10, w0, le
+; OUTLINE-ATOMICS-NEXT:    stxrb w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB194_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw min i8* @var8, i8 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldsminab w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_min_i16_acquire(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i16_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i16_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var16
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:  .LBB195_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxrh w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    sxth w8, w10
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, sxth
+; OUTLINE-ATOMICS-NEXT:    csel w10, w10, w0, le
+; OUTLINE-ATOMICS-NEXT:    stxrh w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB195_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw min i16* @var16, i16 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldsminah w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_min_i32_acquire(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i32_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i32_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var32
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB196_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, le
+; OUTLINE-ATOMICS-NEXT:    stxr w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB196_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw min i32* @var32, i32 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldsmina w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_min_i64_acquire(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i64_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i64_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var64
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB197_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr x8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp x8, x0
+; OUTLINE-ATOMICS-NEXT:    csel x10, x8, x0, le
+; OUTLINE-ATOMICS-NEXT:    stxr w11, x10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB197_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov x0, x8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw min i64* @var64, i64 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldsmina x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_min_i32_noret_acquire(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i32_noret_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i32_noret_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var32
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB198_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp w9, w0
+; OUTLINE-ATOMICS-NEXT:    csel w9, w9, w0, le
+; OUTLINE-ATOMICS-NEXT:    stxr w10, w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB198_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw min i32* @var32, i32 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldsmina w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_min_i64_noret_acquire(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i64_noret_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i64_noret_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var64
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB199_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp x9, x0
+; OUTLINE-ATOMICS-NEXT:    csel x9, x9, x0, le
+; OUTLINE-ATOMICS-NEXT:    stxr w10, x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB199_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw min i64* @var64, i64 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldsmina x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_min_i8_monotonic(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i8_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i8_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var8
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:  .LBB200_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxrb w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    sxtb w8, w10
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, sxtb
+; OUTLINE-ATOMICS-NEXT:    csel w10, w10, w0, le
+; OUTLINE-ATOMICS-NEXT:    stxrb w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB200_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw min i8* @var8, i8 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldsminb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_min_i16_monotonic(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i16_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i16_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var16
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:  .LBB201_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxrh w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    sxth w8, w10
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, sxth
+; OUTLINE-ATOMICS-NEXT:    csel w10, w10, w0, le
+; OUTLINE-ATOMICS-NEXT:    stxrh w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB201_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw min i16* @var16, i16 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldsminh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_min_i32_monotonic(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i32_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i32_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var32
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB202_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxr w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, le
+; OUTLINE-ATOMICS-NEXT:    stxr w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB202_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw min i32* @var32, i32 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldsmin w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_min_i64_monotonic(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i64_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i64_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var64
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB203_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxr x8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp x8, x0
+; OUTLINE-ATOMICS-NEXT:    csel x10, x8, x0, le
+; OUTLINE-ATOMICS-NEXT:    stxr w11, x10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB203_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov x0, x8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw min i64* @var64, i64 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldsmin x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_min_i32_noret_monotonic(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i32_noret_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i32_noret_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var32
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB204_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxr w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp w9, w0
+; OUTLINE-ATOMICS-NEXT:    csel w9, w9, w0, le
+; OUTLINE-ATOMICS-NEXT:    stxr w10, w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB204_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw min i32* @var32, i32 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldsmin w{{[0-9]+}}, w{{[1-9][0-9]*}}, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_min_i64_noret_monotonic(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i64_noret_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i64_noret_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var64
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB205_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxr x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp x9, x0
+; OUTLINE-ATOMICS-NEXT:    csel x9, x9, x0, le
+; OUTLINE-ATOMICS-NEXT:    stxr w10, x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB205_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw min i64* @var64, i64 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldsmin x{{[0-9]+}}, x{{[1-9][0-9]*}}, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_min_i8_release(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i8_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i8_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var8
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:  .LBB206_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxrb w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    sxtb w8, w10
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, sxtb
+; OUTLINE-ATOMICS-NEXT:    csel w10, w10, w0, le
+; OUTLINE-ATOMICS-NEXT:    stlxrb w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB206_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw min i8* @var8, i8 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldsminlb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_min_i16_release(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i16_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i16_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var16
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:  .LBB207_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxrh w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    sxth w8, w10
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, sxth
+; OUTLINE-ATOMICS-NEXT:    csel w10, w10, w0, le
+; OUTLINE-ATOMICS-NEXT:    stlxrh w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB207_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw min i16* @var16, i16 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldsminlh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_min_i32_release(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i32_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i32_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var32
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB208_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxr w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, le
+; OUTLINE-ATOMICS-NEXT:    stlxr w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB208_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw min i32* @var32, i32 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldsminl w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_min_i64_release(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i64_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i64_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var64
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB209_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxr x8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp x8, x0
+; OUTLINE-ATOMICS-NEXT:    csel x10, x8, x0, le
+; OUTLINE-ATOMICS-NEXT:    stlxr w11, x10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB209_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov x0, x8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw min i64* @var64, i64 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldsminl x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_min_i32_noret_release(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i32_noret_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i32_noret_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var32
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB210_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxr w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp w9, w0
+; OUTLINE-ATOMICS-NEXT:    csel w9, w9, w0, le
+; OUTLINE-ATOMICS-NEXT:    stlxr w10, w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB210_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw min i32* @var32, i32 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldsminl w{{[0-9]+}}, w{{[1-9][0-9]*}}, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_min_i64_noret_release(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i64_noret_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i64_noret_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var64
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB211_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxr x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp x9, x0
+; OUTLINE-ATOMICS-NEXT:    csel x9, x9, x0, le
+; OUTLINE-ATOMICS-NEXT:    stlxr w10, x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB211_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw min i64* @var64, i64 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldsminl x{{[0-9]+}}, x{{[1-9][0-9]*}}, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_min_i8_seq_cst(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i8_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i8_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var8
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:  .LBB212_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxrb w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    sxtb w8, w10
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, sxtb
+; OUTLINE-ATOMICS-NEXT:    csel w10, w10, w0, le
+; OUTLINE-ATOMICS-NEXT:    stlxrb w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB212_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw min i8* @var8, i8 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldsminalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_min_i16_seq_cst(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i16_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i16_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var16
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:  .LBB213_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxrh w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    sxth w8, w10
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, sxth
+; OUTLINE-ATOMICS-NEXT:    csel w10, w10, w0, le
+; OUTLINE-ATOMICS-NEXT:    stlxrh w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB213_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw min i16* @var16, i16 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldsminalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_min_i32_seq_cst(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i32_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i32_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var32
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB214_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, le
+; OUTLINE-ATOMICS-NEXT:    stlxr w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB214_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw min i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldsminal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_min_i64_seq_cst(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i64_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i64_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var64
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB215_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr x8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp x8, x0
+; OUTLINE-ATOMICS-NEXT:    csel x10, x8, x0, le
+; OUTLINE-ATOMICS-NEXT:    stlxr w11, x10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB215_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov x0, x8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw min i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldsminal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_min_i32_noret_seq_cst(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i32_noret_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i32_noret_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var32
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB216_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp w9, w0
+; OUTLINE-ATOMICS-NEXT:    csel w9, w9, w0, le
+; OUTLINE-ATOMICS-NEXT:    stlxr w10, w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB216_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw min i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldsminal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_min_i64_noret_seq_cst(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i64_noret_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_min_i64_noret_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var64
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB217_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp x9, x0
+; OUTLINE-ATOMICS-NEXT:    csel x9, x9, x0, le
+; OUTLINE-ATOMICS-NEXT:    stlxr w10, x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB217_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw min i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldsminal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_or_i8_acq_rel(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i8_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i8_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset1_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw or i8* @var8, i8 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldsetalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_or_i16_acq_rel(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i16_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i16_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset2_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw or i16* @var16, i16 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldsetalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_or_i32_acq_rel(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i32_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i32_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw or i32* @var32, i32 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldsetal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_or_i64_acq_rel(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i64_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i64_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw or i64* @var64, i64 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldsetal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_or_i32_noret_acq_rel(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i32_noret_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i32_noret_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw or i32* @var32, i32 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldsetal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_or_i64_noret_acq_rel(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i64_noret_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i64_noret_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw or i64* @var64, i64 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldsetal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_or_i8_acquire(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i8_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i8_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset1_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw or i8* @var8, i8 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldsetab w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_or_i16_acquire(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i16_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i16_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset2_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw or i16* @var16, i16 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldsetah w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_or_i32_acquire(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i32_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i32_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset4_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw or i32* @var32, i32 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldseta w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_or_i64_acquire(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i64_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i64_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset8_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw or i64* @var64, i64 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldseta x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_or_i32_noret_acquire(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i32_noret_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i32_noret_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset4_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw or i32* @var32, i32 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldseta w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_or_i64_noret_acquire(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i64_noret_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i64_noret_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset8_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw or i64* @var64, i64 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldseta x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_or_i8_monotonic(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i8_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i8_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset1_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw or i8* @var8, i8 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldsetb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_or_i16_monotonic(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i16_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i16_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset2_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw or i16* @var16, i16 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldseth w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_or_i32_monotonic(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i32_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i32_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset4_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw or i32* @var32, i32 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldset w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_or_i64_monotonic(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i64_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i64_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset8_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw or i64* @var64, i64 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldset x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_or_i32_noret_monotonic(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i32_noret_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i32_noret_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset4_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw or i32* @var32, i32 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldset w{{[0-9]+}}, w{{[1-9][0-9]*}}, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_or_i64_noret_monotonic(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i64_noret_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i64_noret_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset8_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw or i64* @var64, i64 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldset x{{[0-9]+}}, x{{[1-9][0-9]*}}, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_or_i8_release(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i8_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i8_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset1_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw or i8* @var8, i8 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldsetlb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_or_i16_release(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i16_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i16_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset2_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw or i16* @var16, i16 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldsetlh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_or_i32_release(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i32_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i32_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset4_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw or i32* @var32, i32 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldsetl w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_or_i64_release(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i64_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i64_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset8_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw or i64* @var64, i64 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldsetl x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_or_i32_noret_release(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i32_noret_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i32_noret_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset4_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw or i32* @var32, i32 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldsetl w{{[0-9]+}}, w{{[1-9][0-9]*}}, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_or_i64_noret_release(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i64_noret_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i64_noret_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset8_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw or i64* @var64, i64 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldsetl x{{[0-9]+}}, x{{[1-9][0-9]*}}, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_or_i8_seq_cst(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i8_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i8_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset1_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw or i8* @var8, i8 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldsetalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_or_i16_seq_cst(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i16_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i16_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset2_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw or i16* @var16, i16 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldsetalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_or_i32_seq_cst(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i32_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i32_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw or i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldsetal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_or_i64_seq_cst(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i64_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i64_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw or i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldsetal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_or_i32_noret_seq_cst(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i32_noret_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i32_noret_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw or i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldsetal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_or_i64_noret_seq_cst(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i64_noret_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_or_i64_noret_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldset8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw or i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldsetal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_sub_i8_acq_rel(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i8_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i8_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd1_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw sub i8* @var8, i8 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldaddalb w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i8 %old
 }
 
 define i16 @test_atomic_load_sub_i16_acq_rel(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i16_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i16_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd2_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw sub i16* @var16, i16 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldaddalh w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i16 %old
 }
 
 define i32 @test_atomic_load_sub_i32_acq_rel(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i32_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i32_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw sub i32* @var32, i32 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldaddal w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i32 %old
 }
 
 define i64 @test_atomic_load_sub_i64_acq_rel(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i64_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i64_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg x0, x0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw sub i64* @var64, i64 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: neg x[[NEG:[0-9]+]], x[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldaddal x[[NEG]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i64 %old
 }
 
 define void @test_atomic_load_sub_i32_noret_acq_rel(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i32_noret_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i32_noret_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   atomicrmw sub i32* @var32, i32 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldaddal w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret void
 }
 
 define void @test_atomic_load_sub_i64_noret_acq_rel(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i64_noret_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i64_noret_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg x0, x0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   atomicrmw sub i64* @var64, i64 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: neg x[[NEG:[0-9]+]], x[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldaddal x[[NEG]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret void
 }
 
 define i8 @test_atomic_load_sub_i8_acquire(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i8_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i8_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd1_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw sub i8* @var8, i8 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldaddab w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i8 %old
 }
 
 define i16 @test_atomic_load_sub_i16_acquire(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i16_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i16_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd2_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw sub i16* @var16, i16 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldaddah w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i16 %old
 }
 
 define i32 @test_atomic_load_sub_i32_acquire(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i32_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i32_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd4_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw sub i32* @var32, i32 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldadda w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i32 %old
 }
 
 define i64 @test_atomic_load_sub_i64_acquire(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i64_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i64_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg x0, x0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd8_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw sub i64* @var64, i64 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: neg x[[NEG:[0-9]+]], x[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldadda x[[NEG]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i64 %old
 }
 
 define void @test_atomic_load_sub_i32_noret_acquire(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i32_noret_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i32_noret_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd4_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   atomicrmw sub i32* @var32, i32 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldadda w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret void
 }
 
 define void @test_atomic_load_sub_i64_noret_acquire(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i64_noret_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i64_noret_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg x0, x0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd8_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   atomicrmw sub i64* @var64, i64 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: neg x[[NEG:[0-9]+]], x[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldadda x[[NEG]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret void
 }
 
 define i8 @test_atomic_load_sub_i8_monotonic(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i8_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i8_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd1_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw sub i8* @var8, i8 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldaddb w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i8 %old
 }
 
 define i16 @test_atomic_load_sub_i16_monotonic(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i16_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i16_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd2_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw sub i16* @var16, i16 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldaddh w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i16 %old
 }
 
 define i32 @test_atomic_load_sub_i32_monotonic(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i32_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i32_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd4_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw sub i32* @var32, i32 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldadd w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i32 %old
 }
 
 define i64 @test_atomic_load_sub_i64_monotonic(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i64_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i64_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg x0, x0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd8_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw sub i64* @var64, i64 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: neg x[[NEG:[0-9]+]], x[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldadd x[[NEG]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i64 %old
 }
 
 define void @test_atomic_load_sub_i32_noret_monotonic(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i32_noret_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i32_noret_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd4_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   atomicrmw sub i32* @var32, i32 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldadd w{{[0-9]+}}, w[[NEW:[1-9][0-9]*]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret void
 }
 
 define void @test_atomic_load_sub_i64_noret_monotonic(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i64_noret_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i64_noret_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg x0, x0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd8_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   atomicrmw sub i64* @var64, i64 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: neg x[[NEG:[0-9]+]], x[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldadd x{{[0-9]+}}, x[[NEW:[1-9][0-9]*]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret void
 }
 
 define i8 @test_atomic_load_sub_i8_release(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i8_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i8_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd1_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw sub i8* @var8, i8 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldaddlb w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i8 %old
 }
 
 define i16 @test_atomic_load_sub_i16_release(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i16_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i16_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd2_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw sub i16* @var16, i16 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldaddlh w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i16 %old
 }
 
 define i32 @test_atomic_load_sub_i32_release(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i32_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i32_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd4_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw sub i32* @var32, i32 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldaddl w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i32 %old
 }
 
 define i64 @test_atomic_load_sub_i64_release(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i64_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i64_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg x0, x0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd8_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw sub i64* @var64, i64 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: neg x[[NEG:[0-9]+]], x[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldaddl x[[NEG]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i64 %old
 }
 
 define void @test_atomic_load_sub_i32_noret_release(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i32_noret_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i32_noret_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd4_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   atomicrmw sub i32* @var32, i32 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldaddl w{{[0-9]*}}, w[[NEW:[1-9][0-9]*]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret void
 }
 
 define void @test_atomic_load_sub_i64_noret_release(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i64_noret_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i64_noret_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg x0, x0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd8_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   atomicrmw sub i64* @var64, i64 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: neg x[[NEG:[0-9]+]], x[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldaddl x{{[0-9]*}}, x[[NEW:[1-9][0-9]*]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret void
 }
 
 define i8 @test_atomic_load_sub_i8_seq_cst(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i8_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i8_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd1_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw sub i8* @var8, i8 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldaddalb w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i8 %old
 }
 
 define i16 @test_atomic_load_sub_i16_seq_cst(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i16_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i16_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd2_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw sub i16* @var16, i16 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldaddalh w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i16 %old
 }
 
 define i32 @test_atomic_load_sub_i32_seq_cst(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i32_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i32_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw sub i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldaddal w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i32 %old
 }
 
 define i64 @test_atomic_load_sub_i64_seq_cst(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i64_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i64_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg x0, x0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   %old = atomicrmw sub i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: neg x[[NEG:[0-9]+]], x[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldaddal x[[NEG]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret i64 %old
 }
 
 define void @test_atomic_load_sub_i32_noret_seq_cst(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i32_noret_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i32_noret_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg w0, w0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   atomicrmw sub i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: neg w[[NEG:[0-9]+]], w[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldaddal w[[NEG]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret void
 }
 
 define void @test_atomic_load_sub_i64_noret_seq_cst(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i64_noret_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_sub_i64_noret_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    neg x0, x0
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldadd8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
   atomicrmw sub i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: neg x[[NEG:[0-9]+]], x[[OLD:[0-9]+]]
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldaddal x[[NEG]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret void
 }
 
 define i8 @test_atomic_load_xchg_i8_acq_rel(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i8_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i8_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp1_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xchg i8* @var8, i8 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: swpalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_xchg_i16_acq_rel(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i16_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i16_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp2_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xchg i16* @var16, i16 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: swpalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_xchg_i32_acq_rel(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i32_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i32_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xchg i32* @var32, i32 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: swpal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_xchg_i64_acq_rel(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i64_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i64_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xchg i64* @var64, i64 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: swpal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_xchg_i32_noret_acq_rel(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i32_noret_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i32_noret_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw xchg i32* @var32, i32 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: swpal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret void
 }
 
 define void @test_atomic_load_xchg_i64_noret_acq_rel(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i64_noret_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i64_noret_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw xchg i64* @var64, i64 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: swpal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret void
 }
 
 define i8 @test_atomic_load_xchg_i8_acquire(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i8_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i8_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp1_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xchg i8* @var8, i8 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: swpab w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_xchg_i16_acquire(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i16_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i16_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp2_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xchg i16* @var16, i16 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: swpah w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_xchg_i32_acquire(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i32_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i32_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp4_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xchg i32* @var32, i32 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: swpa w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_xchg_i64_acquire(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i64_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i64_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp8_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xchg i64* @var64, i64 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: swpa x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_xchg_i32_noret_acquire(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i32_noret_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i32_noret_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp4_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw xchg i32* @var32, i32 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: swpa w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret void
 }
 
 define void @test_atomic_load_xchg_i64_noret_acquire(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i64_noret_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i64_noret_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp8_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw xchg i64* @var64, i64 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: swpa x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret void
 }
 
 define i8 @test_atomic_load_xchg_i8_monotonic(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i8_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i8_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp1_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xchg i8* @var8, i8 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: swpb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_xchg_i16_monotonic(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i16_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i16_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp2_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xchg i16* @var16, i16 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: swph w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_xchg_i32_monotonic(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i32_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i32_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp4_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xchg i32* @var32, i32 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: swp w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_xchg_i64_monotonic(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i64_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i64_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp8_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xchg i64* @var64, i64 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: swp x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_xchg_i32_noret_monotonic(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i32_noret_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i32_noret_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp4_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw xchg i32* @var32, i32 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: swp w[[OLD:[0-9]+]], w[[NEW:[0-9,a-z]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret void
 }
 
 define void @test_atomic_load_xchg_i64_noret_monotonic(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i64_noret_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i64_noret_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp8_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw xchg i64* @var64, i64 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: swp x[[OLD:[0-9]+]], x[[NEW:[0-9,a-z]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret void
 }
 
 define i8 @test_atomic_load_xchg_i8_release(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i8_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i8_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp1_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xchg i8* @var8, i8 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: swplb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_xchg_i16_release(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i16_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i16_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp2_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xchg i16* @var16, i16 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: swplh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_xchg_i32_release(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i32_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i32_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp4_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xchg i32* @var32, i32 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: swpl w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_xchg_i64_release(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i64_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i64_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp8_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xchg i64* @var64, i64 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: swpl x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_xchg_i32_noret_release(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i32_noret_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i32_noret_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp4_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw xchg i32* @var32, i32 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: swpl w[[OLD:[0-9]+]], w[[NEW:[0-9,a-z]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret void
 }
 
 define void @test_atomic_load_xchg_i64_noret_release(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i64_noret_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i64_noret_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp8_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw xchg i64* @var64, i64 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: swpl x[[OLD:[0-9]+]], x[[NEW:[0-9,a-z]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret void
 }
 
 define i8 @test_atomic_load_xchg_i8_seq_cst(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i8_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i8_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp1_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xchg i8* @var8, i8 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: swpalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_xchg_i16_seq_cst(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i16_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i16_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp2_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xchg i16* @var16, i16 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: swpalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_xchg_i32_seq_cst(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i32_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i32_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xchg i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: swpal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_xchg_i64_seq_cst(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i64_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i64_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xchg i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: swpal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_xchg_i32_noret_seq_cst(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i32_noret_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i32_noret_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw xchg i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: swpal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret void
 }
 
 define void @test_atomic_load_xchg_i64_noret_seq_cst(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i64_noret_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xchg_i64_noret_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_swp8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw xchg i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: swpal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret void
 }
 
 define i8 @test_atomic_load_umax_i8_acq_rel(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i8_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i8_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var8
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:  .LBB308_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxrb w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, uxtb
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, hi
+; OUTLINE-ATOMICS-NEXT:    stlxrb w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB308_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umax i8* @var8, i8 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldumaxalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_umax_i16_acq_rel(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i16_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i16_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var16
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:  .LBB309_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxrh w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, uxth
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, hi
+; OUTLINE-ATOMICS-NEXT:    stlxrh w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB309_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umax i16* @var16, i16 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldumaxalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_umax_i32_acq_rel(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i32_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i32_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var32
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB310_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, hi
+; OUTLINE-ATOMICS-NEXT:    stlxr w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB310_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umax i32* @var32, i32 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldumaxal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_umax_i64_acq_rel(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i64_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i64_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var64
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB311_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr x8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp x8, x0
+; OUTLINE-ATOMICS-NEXT:    csel x10, x8, x0, hi
+; OUTLINE-ATOMICS-NEXT:    stlxr w11, x10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB311_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov x0, x8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umax i64* @var64, i64 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldumaxal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_umax_i32_noret_acq_rel(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i32_noret_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i32_noret_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var32
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB312_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp w9, w0
+; OUTLINE-ATOMICS-NEXT:    csel w9, w9, w0, hi
+; OUTLINE-ATOMICS-NEXT:    stlxr w10, w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB312_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw umax i32* @var32, i32 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldumaxal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_umax_i64_noret_acq_rel(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i64_noret_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i64_noret_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var64
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB313_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp x9, x0
+; OUTLINE-ATOMICS-NEXT:    csel x9, x9, x0, hi
+; OUTLINE-ATOMICS-NEXT:    stlxr w10, x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB313_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw umax i64* @var64, i64 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldumaxal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_umax_i8_acquire(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i8_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i8_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var8
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:  .LBB314_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxrb w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, uxtb
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, hi
+; OUTLINE-ATOMICS-NEXT:    stxrb w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB314_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umax i8* @var8, i8 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldumaxab w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_umax_i16_acquire(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i16_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i16_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var16
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:  .LBB315_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxrh w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, uxth
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, hi
+; OUTLINE-ATOMICS-NEXT:    stxrh w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB315_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umax i16* @var16, i16 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldumaxah w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_umax_i32_acquire(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i32_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i32_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var32
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB316_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, hi
+; OUTLINE-ATOMICS-NEXT:    stxr w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB316_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umax i32* @var32, i32 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldumaxa w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_umax_i64_acquire(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i64_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i64_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var64
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB317_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr x8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp x8, x0
+; OUTLINE-ATOMICS-NEXT:    csel x10, x8, x0, hi
+; OUTLINE-ATOMICS-NEXT:    stxr w11, x10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB317_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov x0, x8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umax i64* @var64, i64 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldumaxa x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_umax_i32_noret_acquire(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i32_noret_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i32_noret_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var32
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB318_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp w9, w0
+; OUTLINE-ATOMICS-NEXT:    csel w9, w9, w0, hi
+; OUTLINE-ATOMICS-NEXT:    stxr w10, w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB318_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw umax i32* @var32, i32 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldumaxa w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_umax_i64_noret_acquire(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i64_noret_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i64_noret_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var64
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB319_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp x9, x0
+; OUTLINE-ATOMICS-NEXT:    csel x9, x9, x0, hi
+; OUTLINE-ATOMICS-NEXT:    stxr w10, x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB319_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw umax i64* @var64, i64 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldumaxa x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_umax_i8_monotonic(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i8_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i8_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var8
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:  .LBB320_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxrb w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, uxtb
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, hi
+; OUTLINE-ATOMICS-NEXT:    stxrb w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB320_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umax i8* @var8, i8 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldumaxb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_umax_i16_monotonic(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i16_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i16_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var16
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:  .LBB321_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxrh w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, uxth
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, hi
+; OUTLINE-ATOMICS-NEXT:    stxrh w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB321_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umax i16* @var16, i16 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldumaxh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_umax_i32_monotonic(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i32_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i32_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var32
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB322_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxr w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, hi
+; OUTLINE-ATOMICS-NEXT:    stxr w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB322_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umax i32* @var32, i32 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldumax w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_umax_i64_monotonic(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i64_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i64_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var64
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB323_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxr x8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp x8, x0
+; OUTLINE-ATOMICS-NEXT:    csel x10, x8, x0, hi
+; OUTLINE-ATOMICS-NEXT:    stxr w11, x10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB323_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov x0, x8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umax i64* @var64, i64 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldumax x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_umax_i32_noret_monotonic(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i32_noret_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i32_noret_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var32
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB324_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxr w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp w9, w0
+; OUTLINE-ATOMICS-NEXT:    csel w9, w9, w0, hi
+; OUTLINE-ATOMICS-NEXT:    stxr w10, w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB324_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw umax i32* @var32, i32 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldumax w{{[0-9]+}}, w{{[1-9][0-9]*}}, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_umax_i64_noret_monotonic(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i64_noret_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i64_noret_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var64
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB325_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxr x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp x9, x0
+; OUTLINE-ATOMICS-NEXT:    csel x9, x9, x0, hi
+; OUTLINE-ATOMICS-NEXT:    stxr w10, x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB325_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw umax i64* @var64, i64 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldumax x{{[0-9]+}}, x{{[1-9][0-9]*}}, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_umax_i8_release(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i8_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i8_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var8
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:  .LBB326_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxrb w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, uxtb
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, hi
+; OUTLINE-ATOMICS-NEXT:    stlxrb w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB326_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umax i8* @var8, i8 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldumaxlb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_umax_i16_release(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i16_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i16_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var16
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:  .LBB327_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxrh w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, uxth
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, hi
+; OUTLINE-ATOMICS-NEXT:    stlxrh w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB327_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umax i16* @var16, i16 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldumaxlh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_umax_i32_release(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i32_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i32_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var32
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB328_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxr w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, hi
+; OUTLINE-ATOMICS-NEXT:    stlxr w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB328_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umax i32* @var32, i32 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldumaxl w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_umax_i64_release(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i64_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i64_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var64
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB329_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxr x8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp x8, x0
+; OUTLINE-ATOMICS-NEXT:    csel x10, x8, x0, hi
+; OUTLINE-ATOMICS-NEXT:    stlxr w11, x10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB329_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov x0, x8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umax i64* @var64, i64 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldumaxl x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_umax_i32_noret_release(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i32_noret_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i32_noret_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var32
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB330_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxr w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp w9, w0
+; OUTLINE-ATOMICS-NEXT:    csel w9, w9, w0, hi
+; OUTLINE-ATOMICS-NEXT:    stlxr w10, w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB330_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw umax i32* @var32, i32 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldumaxl w{{[0-9]+}}, w{{[1-9][0-9]*}}, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_umax_i64_noret_release(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i64_noret_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i64_noret_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var64
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB331_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxr x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp x9, x0
+; OUTLINE-ATOMICS-NEXT:    csel x9, x9, x0, hi
+; OUTLINE-ATOMICS-NEXT:    stlxr w10, x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB331_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw umax i64* @var64, i64 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldumaxl x{{[0-9]+}}, x{{[1-9][0-9]*}}, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_umax_i8_seq_cst(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i8_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i8_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var8
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:  .LBB332_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxrb w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, uxtb
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, hi
+; OUTLINE-ATOMICS-NEXT:    stlxrb w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB332_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umax i8* @var8, i8 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldumaxalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_umax_i16_seq_cst(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i16_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i16_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var16
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:  .LBB333_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxrh w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, uxth
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, hi
+; OUTLINE-ATOMICS-NEXT:    stlxrh w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB333_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umax i16* @var16, i16 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldumaxalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_umax_i32_seq_cst(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i32_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i32_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var32
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB334_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, hi
+; OUTLINE-ATOMICS-NEXT:    stlxr w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB334_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umax i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldumaxal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_umax_i64_seq_cst(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i64_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i64_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var64
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB335_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr x8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp x8, x0
+; OUTLINE-ATOMICS-NEXT:    csel x10, x8, x0, hi
+; OUTLINE-ATOMICS-NEXT:    stlxr w11, x10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB335_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov x0, x8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umax i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldumaxal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_umax_i32_noret_seq_cst(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i32_noret_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i32_noret_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var32
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB336_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp w9, w0
+; OUTLINE-ATOMICS-NEXT:    csel w9, w9, w0, hi
+; OUTLINE-ATOMICS-NEXT:    stlxr w10, w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB336_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw umax i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldumaxal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_umax_i64_noret_seq_cst(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i64_noret_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umax_i64_noret_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var64
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB337_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp x9, x0
+; OUTLINE-ATOMICS-NEXT:    csel x9, x9, x0, hi
+; OUTLINE-ATOMICS-NEXT:    stlxr w10, x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB337_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw umax i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldumaxal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_umin_i8_acq_rel(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i8_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i8_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var8
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:  .LBB338_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxrb w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, uxtb
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, ls
+; OUTLINE-ATOMICS-NEXT:    stlxrb w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB338_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umin i8* @var8, i8 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: lduminalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_umin_i16_acq_rel(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i16_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i16_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var16
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:  .LBB339_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxrh w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, uxth
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, ls
+; OUTLINE-ATOMICS-NEXT:    stlxrh w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB339_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umin i16* @var16, i16 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: lduminalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_umin_i32_acq_rel(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i32_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i32_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var32
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB340_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, ls
+; OUTLINE-ATOMICS-NEXT:    stlxr w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB340_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umin i32* @var32, i32 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: lduminal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_umin_i64_acq_rel(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i64_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i64_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var64
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB341_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr x8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp x8, x0
+; OUTLINE-ATOMICS-NEXT:    csel x10, x8, x0, ls
+; OUTLINE-ATOMICS-NEXT:    stlxr w11, x10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB341_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov x0, x8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umin i64* @var64, i64 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: lduminal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_umin_i32_noret_acq_rel(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i32_noret_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i32_noret_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var32
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB342_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp w9, w0
+; OUTLINE-ATOMICS-NEXT:    csel w9, w9, w0, ls
+; OUTLINE-ATOMICS-NEXT:    stlxr w10, w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB342_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw umin i32* @var32, i32 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: lduminal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_umin_i64_noret_acq_rel(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i64_noret_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i64_noret_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var64
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB343_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp x9, x0
+; OUTLINE-ATOMICS-NEXT:    csel x9, x9, x0, ls
+; OUTLINE-ATOMICS-NEXT:    stlxr w10, x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB343_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw umin i64* @var64, i64 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: lduminal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_umin_i8_acquire(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i8_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i8_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var8
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:  .LBB344_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxrb w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, uxtb
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, ls
+; OUTLINE-ATOMICS-NEXT:    stxrb w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB344_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umin i8* @var8, i8 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: lduminab w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_umin_i16_acquire(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i16_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i16_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var16
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:  .LBB345_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxrh w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, uxth
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, ls
+; OUTLINE-ATOMICS-NEXT:    stxrh w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB345_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umin i16* @var16, i16 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: lduminah w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_umin_i32_acquire(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i32_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i32_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var32
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB346_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, ls
+; OUTLINE-ATOMICS-NEXT:    stxr w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB346_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umin i32* @var32, i32 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldumina w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_umin_i64_acquire(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i64_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i64_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var64
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB347_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr x8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp x8, x0
+; OUTLINE-ATOMICS-NEXT:    csel x10, x8, x0, ls
+; OUTLINE-ATOMICS-NEXT:    stxr w11, x10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB347_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov x0, x8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umin i64* @var64, i64 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldumina x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_umin_i32_noret_acquire(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i32_noret_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i32_noret_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var32
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB348_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp w9, w0
+; OUTLINE-ATOMICS-NEXT:    csel w9, w9, w0, ls
+; OUTLINE-ATOMICS-NEXT:    stxr w10, w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB348_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw umin i32* @var32, i32 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldumina w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_umin_i64_noret_acquire(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i64_noret_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i64_noret_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var64
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB349_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp x9, x0
+; OUTLINE-ATOMICS-NEXT:    csel x9, x9, x0, ls
+; OUTLINE-ATOMICS-NEXT:    stxr w10, x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB349_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw umin i64* @var64, i64 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldumina x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_umin_i8_monotonic(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i8_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i8_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var8
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:  .LBB350_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxrb w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, uxtb
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, ls
+; OUTLINE-ATOMICS-NEXT:    stxrb w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB350_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umin i8* @var8, i8 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: lduminb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_umin_i16_monotonic(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i16_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i16_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var16
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:  .LBB351_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxrh w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, uxth
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, ls
+; OUTLINE-ATOMICS-NEXT:    stxrh w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB351_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umin i16* @var16, i16 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: lduminh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_umin_i32_monotonic(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i32_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i32_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var32
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB352_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxr w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, ls
+; OUTLINE-ATOMICS-NEXT:    stxr w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB352_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umin i32* @var32, i32 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldumin w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_umin_i64_monotonic(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i64_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i64_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var64
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB353_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxr x8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp x8, x0
+; OUTLINE-ATOMICS-NEXT:    csel x10, x8, x0, ls
+; OUTLINE-ATOMICS-NEXT:    stxr w11, x10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB353_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov x0, x8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umin i64* @var64, i64 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldumin x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_umin_i32_noret_monotonic(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i32_noret_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i32_noret_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var32
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB354_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxr w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp w9, w0
+; OUTLINE-ATOMICS-NEXT:    csel w9, w9, w0, ls
+; OUTLINE-ATOMICS-NEXT:    stxr w10, w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB354_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw umin i32* @var32, i32 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldumin w{{[0-9]+}}, w{{[1-9][0-9]*}}, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_umin_i64_noret_monotonic(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i64_noret_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i64_noret_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var64
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB355_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxr x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp x9, x0
+; OUTLINE-ATOMICS-NEXT:    csel x9, x9, x0, ls
+; OUTLINE-ATOMICS-NEXT:    stxr w10, x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB355_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw umin i64* @var64, i64 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldumin x{{[0-9]+}}, x{{[1-9][0-9]*}}, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_umin_i8_release(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i8_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i8_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var8
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:  .LBB356_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxrb w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, uxtb
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, ls
+; OUTLINE-ATOMICS-NEXT:    stlxrb w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB356_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umin i8* @var8, i8 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: lduminlb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_umin_i16_release(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i16_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i16_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var16
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:  .LBB357_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxrh w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, uxth
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, ls
+; OUTLINE-ATOMICS-NEXT:    stlxrh w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB357_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umin i16* @var16, i16 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: lduminlh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_umin_i32_release(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i32_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i32_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var32
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB358_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxr w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, ls
+; OUTLINE-ATOMICS-NEXT:    stlxr w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB358_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umin i32* @var32, i32 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: lduminl w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_umin_i64_release(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i64_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i64_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var64
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB359_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxr x8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp x8, x0
+; OUTLINE-ATOMICS-NEXT:    csel x10, x8, x0, ls
+; OUTLINE-ATOMICS-NEXT:    stlxr w11, x10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB359_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov x0, x8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umin i64* @var64, i64 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: lduminl x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_umin_i32_noret_release(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i32_noret_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i32_noret_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var32
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB360_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxr w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp w9, w0
+; OUTLINE-ATOMICS-NEXT:    csel w9, w9, w0, ls
+; OUTLINE-ATOMICS-NEXT:    stlxr w10, w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB360_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw umin i32* @var32, i32 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: lduminl w{{[0-9]+}}, w{{[1-9][0-9]*}}, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_umin_i64_noret_release(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i64_noret_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i64_noret_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var64
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB361_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldxr x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp x9, x0
+; OUTLINE-ATOMICS-NEXT:    csel x9, x9, x0, ls
+; OUTLINE-ATOMICS-NEXT:    stlxr w10, x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB361_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw umin i64* @var64, i64 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: lduminl x{{[0-9]+}}, x{{[1-9][0-9]*}}, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_umin_i8_seq_cst(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i8_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i8_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var8
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:  .LBB362_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxrb w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, uxtb
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, ls
+; OUTLINE-ATOMICS-NEXT:    stlxrb w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB362_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umin i8* @var8, i8 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: lduminalb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_umin_i16_seq_cst(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i16_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i16_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var16
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:  .LBB363_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxrh w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0, uxth
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, ls
+; OUTLINE-ATOMICS-NEXT:    stlxrh w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB363_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umin i16* @var16, i16 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: lduminalh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_umin_i32_seq_cst(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i32_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i32_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var32
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB364_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr w8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp w8, w0
+; OUTLINE-ATOMICS-NEXT:    csel w10, w8, w0, ls
+; OUTLINE-ATOMICS-NEXT:    stlxr w11, w10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB364_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov w0, w8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umin i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: lduminal w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_umin_i64_seq_cst(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i64_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i64_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x9, var64
+; OUTLINE-ATOMICS-NEXT:    add x9, x9, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB365_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr x8, [x9]
+; OUTLINE-ATOMICS-NEXT:    cmp x8, x0
+; OUTLINE-ATOMICS-NEXT:    csel x10, x8, x0, ls
+; OUTLINE-ATOMICS-NEXT:    stlxr w11, x10, [x9]
+; OUTLINE-ATOMICS-NEXT:    cbnz w11, .LBB365_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    mov x0, x8
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw umin i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: lduminal x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_umin_i32_noret_seq_cst(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i32_noret_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i32_noret_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var32
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:  .LBB366_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp w9, w0
+; OUTLINE-ATOMICS-NEXT:    csel w9, w9, w0, ls
+; OUTLINE-ATOMICS-NEXT:    stlxr w10, w9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB366_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw umin i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: lduminal w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_umin_i64_noret_seq_cst(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i64_noret_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_umin_i64_noret_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    adrp x8, var64
+; OUTLINE-ATOMICS-NEXT:    add x8, x8, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:  .LBB367_1: // %atomicrmw.start
+; OUTLINE-ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE-ATOMICS-NEXT:    ldaxr x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cmp x9, x0
+; OUTLINE-ATOMICS-NEXT:    csel x9, x9, x0, ls
+; OUTLINE-ATOMICS-NEXT:    stlxr w10, x9, [x8]
+; OUTLINE-ATOMICS-NEXT:    cbnz w10, .LBB367_1
+; OUTLINE-ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw umin i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: lduminal x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_xor_i8_acq_rel(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i8_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i8_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor1_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xor i8* @var8, i8 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldeoralb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_xor_i16_acq_rel(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i16_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i16_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor2_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xor i16* @var16, i16 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldeoralh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_xor_i32_acq_rel(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i32_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i32_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xor i32* @var32, i32 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldeoral w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_xor_i64_acq_rel(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i64_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i64_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xor i64* @var64, i64 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldeoral x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_xor_i32_noret_acq_rel(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i32_noret_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i32_noret_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw xor i32* @var32, i32 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldeoral w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_xor_i64_noret_acq_rel(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i64_noret_acq_rel:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i64_noret_acq_rel:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw xor i64* @var64, i64 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldeoral x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_xor_i8_acquire(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i8_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i8_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor1_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xor i8* @var8, i8 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldeorab w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_xor_i16_acquire(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i16_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i16_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor2_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xor i16* @var16, i16 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldeorah w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_xor_i32_acquire(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i32_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i32_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor4_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xor i32* @var32, i32 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldeora w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_xor_i64_acquire(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i64_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i64_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor8_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xor i64* @var64, i64 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldeora x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_xor_i32_noret_acquire(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i32_noret_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i32_noret_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor4_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw xor i32* @var32, i32 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldeora w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_xor_i64_noret_acquire(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i64_noret_acquire:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i64_noret_acquire:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor8_acq
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw xor i64* @var64, i64 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldeora x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_xor_i8_monotonic(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i8_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i8_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor1_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xor i8* @var8, i8 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldeorb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_xor_i16_monotonic(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i16_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i16_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor2_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xor i16* @var16, i16 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldeorh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_xor_i32_monotonic(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i32_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i32_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor4_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xor i32* @var32, i32 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldeor w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_xor_i64_monotonic(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i64_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i64_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor8_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xor i64* @var64, i64 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldeor x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_xor_i32_noret_monotonic(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i32_noret_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i32_noret_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor4_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw xor i32* @var32, i32 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldeor w{{[0-9]+}}, w{{[1-9][0-9]*}}, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_xor_i64_noret_monotonic(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i64_noret_monotonic:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i64_noret_monotonic:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor8_relax
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw xor i64* @var64, i64 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldeor x{{[0-9]+}}, x{{[1-9][0-9]*}}, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_xor_i8_release(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i8_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i8_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor1_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xor i8* @var8, i8 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldeorlb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_xor_i16_release(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i16_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i16_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor2_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xor i16* @var16, i16 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldeorlh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_xor_i32_release(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i32_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i32_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor4_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xor i32* @var32, i32 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldeorl w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_xor_i64_release(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i64_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i64_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor8_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xor i64* @var64, i64 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldeorl x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_xor_i32_noret_release(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i32_noret_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i32_noret_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor4_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw xor i32* @var32, i32 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldeorl w{{[0-9]+}}, w{{[1-9][0-9]*}}, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_xor_i64_noret_release(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i64_noret_release:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i64_noret_release:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor8_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw xor i64* @var64, i64 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldeorl x{{[0-9]+}}, x{{[1-9][0-9]*}}, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define i8 @test_atomic_load_xor_i8_seq_cst(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i8_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i8_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor1_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xor i8* @var8, i8 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: ldeoralb w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i8 %old
 }
 
 define i16 @test_atomic_load_xor_i16_seq_cst(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i16_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i16_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor2_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xor i16* @var16, i16 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: ldeoralh w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i16 %old
 }
 
 define i32 @test_atomic_load_xor_i32_seq_cst(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i32_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i32_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xor i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldeoral w[[OLD:[0-9]+]], w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i32 %old
 }
 
 define i64 @test_atomic_load_xor_i64_seq_cst(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i64_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i64_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    %old = atomicrmw xor i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldeoral x[[OLD:[0-9]+]], x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
    ret i64 %old
 }
 
 define void @test_atomic_load_xor_i32_noret_seq_cst(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i32_noret_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i32_noret_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor4_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw xor i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: ldeoral w0, w[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_load_xor_i64_noret_seq_cst(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i64_noret_seq_cst:
+; OUTLINE-ATOMICS-LABEL: test_atomic_load_xor_i64_noret_seq_cst:
+; OUTLINE-ATOMICS:       // %bb.0:
+; OUTLINE-ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE-ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE-ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE-ATOMICS-NEXT:    bl __aarch64_ldeor8_acq_rel
+; OUTLINE-ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE-ATOMICS-NEXT:    ret
    atomicrmw xor i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: ldeoral x0, x[[NEW:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 

llvm/test/CodeGen/AArch64/atomic-ops-not-barriers.ll

 ; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs -mattr=+outline-atomics < %s | FileCheck %s --check-prefix=OUTLINE-ATOMICS
 
 define i32 @foo(i32* %var, i1 %cond) {
+; OUTLINE-ATOMICS: bl __aarch64_ldadd4_relax
 ; CHECK-LABEL: foo:
   br i1 %cond, label %atomic_ver, label %simple_ver
 simple_ver:
   %oldval = load i32, i32* %var
   %newval = add nsw i32 %oldval, -1
   store i32 %newval, i32* %var
   br label %somewhere
 atomic_ver:

llvm/test/CodeGen/AArch64/atomic-ops.ll

 ; RUN: llc -mtriple=aarch64-none-linux-gnu -disable-post-ra -verify-machineinstrs < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-none-linux-gnu -disable-post-ra -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-REG
+; RUN: llc -mtriple=aarch64-none-linux-gnu -disable-post-ra -verify-machineinstrs -mattr=+outline-atomics < %s | FileCheck %s --check-prefix=OUTLINE_ATOMICS
 
 
 ; Point of CHECK-REG is to make sure UNPREDICTABLE instructions aren't created
 ; (i.e. reusing a register for status & data in store exclusive).
 ; CHECK-REG-NOT: stlxrb w[[NEW:[0-9]+]], w[[NEW]], [x{{[0-9]+}}]
 ; CHECK-REG-NOT: stlxrb w[[NEW:[0-9]+]], x[[NEW]], [x{{[0-9]+}}]
 
 @var8 = global i8 0
 @var16 = global i16 0
 @var32 = global i32 0
 @var64 = global i64 0
 
 define i8 @test_atomic_load_add_i8(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i8:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_add_i8:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE_ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE_ATOMICS-NEXT:    bl __aarch64_ldadd1_acq_rel
+; OUTLINE_ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw add i8* @var8, i8 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; CHECK: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
   ; w0 below is a reasonable guess but could change: it certainly comes into the
   ;  function there.
 ; CHECK-NEXT: add [[NEW:w[0-9]+]], w[[OLD]], w0
 ; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
    ret i8 %old
 }
 
 define i16 @test_atomic_load_add_i16(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i16:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_add_i16:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE_ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE_ATOMICS-NEXT:    bl __aarch64_ldadd2_acq
+; OUTLINE_ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw add i16* @var16, i16 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; ; CHECK: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
   ; w0 below is a reasonable guess but could change: it certainly comes into the
   ;  function there.
 ; CHECK-NEXT: add [[NEW:w[0-9]+]], w[[OLD]], w0
 ; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
    ret i16 %old
 }
 
 define i32 @test_atomic_load_add_i32(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i32:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_add_i32:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE_ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE_ATOMICS-NEXT:    bl __aarch64_ldadd4_rel
+; OUTLINE_ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw add i32* @var32, i32 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; ; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
   ; w0 below is a reasonable guess but could change: it certainly comes into the
   ;  function there.
 ; CHECK-NEXT: add [[NEW:w[0-9]+]], w[[OLD]], w0
 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
    ret i32 %old
 }
 
 define i64 @test_atomic_load_add_i64(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_add_i64:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_add_i64:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE_ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE_ATOMICS-NEXT:    bl __aarch64_ldadd8_relax
+; OUTLINE_ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw add i64* @var64, i64 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; ; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
   ; x0 below is a reasonable guess but could change: it certainly comes into the
   ; function there.
 ; CHECK-NEXT: add [[NEW:x[0-9]+]], x[[OLD]], x0
 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov x0, x[[OLD]]
    ret i64 %old
 }
 
 define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i8:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_sub_i8:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE_ATOMICS-NEXT:    neg w0, w0
+; OUTLINE_ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE_ATOMICS-NEXT:    bl __aarch64_ldadd1_relax
+; OUTLINE_ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw sub i8* @var8, i8 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; ; CHECK: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
   ; w0 below is a reasonable guess but could change: it certainly comes into the
   ;  function there.
 ; CHECK-NEXT: sub [[NEW:w[0-9]+]], w[[OLD]], w0
 ; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
    ret i8 %old
 }
 
 define i16 @test_atomic_load_sub_i16(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i16:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_sub_i16:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE_ATOMICS-NEXT:    neg w0, w0
+; OUTLINE_ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE_ATOMICS-NEXT:    bl __aarch64_ldadd2_rel
+; OUTLINE_ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw sub i16* @var16, i16 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; ; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
   ; w0 below is a reasonable guess but could change: it certainly comes into the
   ;  function there.
 ; CHECK-NEXT: sub [[NEW:w[0-9]+]], w[[OLD]], w0
 ; CHECK-NEXT: stlxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
    ret i16 %old
 }
 
 define i32 @test_atomic_load_sub_i32(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i32:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_sub_i32:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE_ATOMICS-NEXT:    neg w0, w0
+; OUTLINE_ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE_ATOMICS-NEXT:    bl __aarch64_ldadd4_acq
+; OUTLINE_ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw sub i32* @var32, i32 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
   ; w0 below is a reasonable guess but could change: it certainly comes into the
   ;  function there.
 ; CHECK-NEXT: sub [[NEW:w[0-9]+]], w[[OLD]], w0
 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
    ret i32 %old
 }
 
 define i64 @test_atomic_load_sub_i64(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_sub_i64:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_sub_i64:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE_ATOMICS-NEXT:    neg x0, x0
+; OUTLINE_ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE_ATOMICS-NEXT:    bl __aarch64_ldadd8_acq_rel
+; OUTLINE_ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw sub i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
   ; x0 below is a reasonable guess but could change: it certainly comes into the
   ; function there.
 ; CHECK-NEXT: sub [[NEW:x[0-9]+]], x[[OLD]], x0
 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov x0, x[[OLD]]
    ret i64 %old
 }
 
 define i8 @test_atomic_load_and_i8(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i8:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_and_i8:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE_ATOMICS-NEXT:    mvn w0, w0
+; OUTLINE_ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE_ATOMICS-NEXT:    bl __aarch64_ldclr1_rel
+; OUTLINE_ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw and i8* @var8, i8 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; ; CHECK: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
   ; w0 below is a reasonable guess but could change: it certainly comes into the
   ;  function there.
 ; CHECK-NEXT: and [[NEW:w[0-9]+]], w[[OLD]], w0
 ; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
    ret i8 %old
 }
 
 define i16 @test_atomic_load_and_i16(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i16:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_and_i16:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE_ATOMICS-NEXT:    mvn w0, w0
+; OUTLINE_ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE_ATOMICS-NEXT:    bl __aarch64_ldclr2_relax
+; OUTLINE_ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw and i16* @var16, i16 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; ; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
   ; w0 below is a reasonable guess but could change: it certainly comes into the
   ;  function there.
 ; CHECK-NEXT: and [[NEW:w[0-9]+]], w[[OLD]], w0
 ; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
    ret i16 %old
 }
 
 define i32 @test_atomic_load_and_i32(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i32:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_and_i32:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE_ATOMICS-NEXT:    mvn w0, w0
+; OUTLINE_ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE_ATOMICS-NEXT:    bl __aarch64_ldclr4_acq_rel
+; OUTLINE_ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw and i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
   ; w0 below is a reasonable guess but could change: it certainly comes into the
   ;  function there.
 ; CHECK-NEXT: and [[NEW:w[0-9]+]], w[[OLD]], w0
 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
    ret i32 %old
 }
 
 define i64 @test_atomic_load_and_i64(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_and_i64:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_and_i64:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE_ATOMICS-NEXT:    mvn x0, x0
+; OUTLINE_ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE_ATOMICS-NEXT:    bl __aarch64_ldclr8_acq
+; OUTLINE_ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw and i64* @var64, i64 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
   ; x0 below is a reasonable guess but could change: it certainly comes into the
   ; function there.
 ; CHECK-NEXT: and [[NEW:x[0-9]+]], x[[OLD]], x0
 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov x0, x[[OLD]]
    ret i64 %old
 }
 
 define i8 @test_atomic_load_or_i8(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i8:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_or_i8:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE_ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE_ATOMICS-NEXT:    bl __aarch64_ldset1_acq_rel
+; OUTLINE_ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw or i8* @var8, i8 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; ; CHECK: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
   ; w0 below is a reasonable guess but could change: it certainly comes into the
   ;  function there.
 ; CHECK-NEXT: orr [[NEW:w[0-9]+]], w[[OLD]], w0
 ; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
    ret i8 %old
 }
 
 define i16 @test_atomic_load_or_i16(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i16:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_or_i16:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE_ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE_ATOMICS-NEXT:    bl __aarch64_ldset2_relax
+; OUTLINE_ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw or i16* @var16, i16 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; ; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
   ; w0 below is a reasonable guess but could change: it certainly comes into the
   ;  function there.
 ; CHECK-NEXT: orr [[NEW:w[0-9]+]], w[[OLD]], w0
 ; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
    ret i16 %old
 }
 
 define i32 @test_atomic_load_or_i32(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i32:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_or_i32:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE_ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE_ATOMICS-NEXT:    bl __aarch64_ldset4_acq
+; OUTLINE_ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw or i32* @var32, i32 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
   ; w0 below is a reasonable guess but could change: it certainly comes into the
   ;  function there.
 ; CHECK-NEXT: orr [[NEW:w[0-9]+]], w[[OLD]], w0
 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
    ret i32 %old
 }
 
 define i64 @test_atomic_load_or_i64(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_or_i64:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_or_i64:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE_ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE_ATOMICS-NEXT:    bl __aarch64_ldset8_rel
+; OUTLINE_ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw or i64* @var64, i64 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; ; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
   ; x0 below is a reasonable guess but could change: it certainly comes into the
   ; function there.
 ; CHECK-NEXT: orr [[NEW:x[0-9]+]], x[[OLD]], x0
 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov x0, x[[OLD]]
    ret i64 %old
 }
 
 define i8 @test_atomic_load_xor_i8(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i8:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_xor_i8:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE_ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE_ATOMICS-NEXT:    bl __aarch64_ldeor1_acq
+; OUTLINE_ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw xor i8* @var8, i8 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; ; CHECK: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
   ; w0 below is a reasonable guess but could change: it certainly comes into the
   ;  function there.
 ; CHECK-NEXT: eor [[NEW:w[0-9]+]], w[[OLD]], w0
 ; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
    ret i8 %old
 }
 
 define i16 @test_atomic_load_xor_i16(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i16:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_xor_i16:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE_ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE_ATOMICS-NEXT:    bl __aarch64_ldeor2_rel
+; OUTLINE_ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw xor i16* @var16, i16 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; ; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
   ; w0 below is a reasonable guess but could change: it certainly comes into the
   ;  function there.
 ; CHECK-NEXT: eor [[NEW:w[0-9]+]], w[[OLD]], w0
 ; CHECK-NEXT: stlxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
    ret i16 %old
 }
 
 define i32 @test_atomic_load_xor_i32(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i32:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_xor_i32:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE_ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE_ATOMICS-NEXT:    bl __aarch64_ldeor4_acq_rel
+; OUTLINE_ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw xor i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
   ; w0 below is a reasonable guess but could change: it certainly comes into the
   ;  function there.
 ; CHECK-NEXT: eor [[NEW:w[0-9]+]], w[[OLD]], w0
 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
    ret i32 %old
 }
 
 define i64 @test_atomic_load_xor_i64(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xor_i64:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_xor_i64:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE_ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE_ATOMICS-NEXT:    bl __aarch64_ldeor8_relax
+; OUTLINE_ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw xor i64* @var64, i64 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; ; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
   ; x0 below is a reasonable guess but could change: it certainly comes into the
   ; function there.
 ; CHECK-NEXT: eor [[NEW:x[0-9]+]], x[[OLD]], x0
 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov x0, x[[OLD]]
    ret i64 %old
 }
 
 define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i8:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_xchg_i8:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE_ATOMICS-NEXT:    adrp x1, var8
+; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var8
+; OUTLINE_ATOMICS-NEXT:    bl __aarch64_swp1_relax
+; OUTLINE_ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw xchg i8* @var8, i8 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; ; CHECK: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
   ; w0 below is a reasonable guess but could change: it certainly comes into the
   ; function there.
 ; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], w0, [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
    ret i8 %old
 }
 
 define i16 @test_atomic_load_xchg_i16(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i16:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_xchg_i16:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE_ATOMICS-NEXT:    adrp x1, var16
+; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var16
+; OUTLINE_ATOMICS-NEXT:    bl __aarch64_swp2_acq_rel
+; OUTLINE_ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw xchg i16* @var16, i16 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; ; CHECK: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
   ; w0 below is a reasonable guess but could change: it certainly comes into the
   ; function there.
 ; CHECK-NEXT: stlxrh [[STATUS:w[0-9]+]], w0, [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
    ret i16 %old
 }
 
 define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i32:
 ; CHECK: mov {{[xw]}}8, w[[OLD:[0-9]+]]
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_xchg_i32:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE_ATOMICS-NEXT:    adrp x1, var32
+; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var32
+; OUTLINE_ATOMICS-NEXT:    bl __aarch64_swp4_rel
+; OUTLINE_ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw xchg i32* @var32, i32 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; ; CHECK: ldxr {{[xw]}}[[OLD]], [x[[ADDR]]]
   ; w0 below is a reasonable guess but could change: it certainly comes into the
   ;  function there.
 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], w8, [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
    ret i32 %old
 }
 
 define i64 @test_atomic_load_xchg_i64(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_xchg_i64:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_xchg_i64:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE_ATOMICS-NEXT:    adrp x1, var64
+; OUTLINE_ATOMICS-NEXT:    add x1, x1, :lo12:var64
+; OUTLINE_ATOMICS-NEXT:    bl __aarch64_swp8_acq
+; OUTLINE_ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw xchg i64* @var64, i64 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
   ; x0 below is a reasonable guess but could change: it certainly comes into the
   ; function there.
 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], x0, [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov x0, x[[OLD]]
    ret i64 %old
 }
 
 
 define i8 @test_atomic_load_min_i8(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i8:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_min_i8:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    adrp x9, var8
+; OUTLINE_ATOMICS-NEXT:    add x9, x9, :lo12:var8
+; OUTLINE_ATOMICS-NEXT:  .LBB24_1: // %atomicrmw.start
+; OUTLINE_ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE_ATOMICS-NEXT:    ldaxrb w10, [x9]
+; OUTLINE_ATOMICS-NEXT:    sxtb w8, w10
+; OUTLINE_ATOMICS-NEXT:    cmp w8, w0, sxtb
+; OUTLINE_ATOMICS-NEXT:    csel w10, w10, w0, le
+; OUTLINE_ATOMICS-NEXT:    stxrb w11, w10, [x9]
+; OUTLINE_ATOMICS-NEXT:    cbnz w11, .LBB24_1
+; OUTLINE_ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE_ATOMICS-NEXT:    mov w0, w8
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw min i8* @var8, i8 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; CHECK: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
   ; w0 below is a reasonable guess but could change: it certainly comes into the
   ;  function there.
 
 ; CHECK-NEXT: sxtb w[[OLD_EXT:[0-9]+]], w[[OLD]]
 ; CHECK-NEXT: cmp w[[OLD_EXT]], w0, sxtb
 ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, le
 
 ; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD_EXT]]
    ret i8 %old
 }
 
 define i16 @test_atomic_load_min_i16(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i16:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_min_i16:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    adrp x9, var16
+; OUTLINE_ATOMICS-NEXT:    add x9, x9, :lo12:var16
+; OUTLINE_ATOMICS-NEXT:  .LBB25_1: // %atomicrmw.start
+; OUTLINE_ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE_ATOMICS-NEXT:    ldxrh w10, [x9]
+; OUTLINE_ATOMICS-NEXT:    sxth w8, w10
+; OUTLINE_ATOMICS-NEXT:    cmp w8, w0, sxth
+; OUTLINE_ATOMICS-NEXT:    csel w10, w10, w0, le
+; OUTLINE_ATOMICS-NEXT:    stlxrh w11, w10, [x9]
+; OUTLINE_ATOMICS-NEXT:    cbnz w11, .LBB25_1
+; OUTLINE_ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE_ATOMICS-NEXT:    mov w0, w8
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw min i16* @var16, i16 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
   ; w0 below is a reasonable guess but could change: it certainly comes into the

 ; CHECK-NOT: dmb
 
 ; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD_EXT]]
    ret i16 %old
 }
 
 define i32 @test_atomic_load_min_i32(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i32:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_min_i32:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    adrp x9, var32
+; OUTLINE_ATOMICS-NEXT:    add x9, x9, :lo12:var32
+; OUTLINE_ATOMICS-NEXT:  .LBB26_1: // %atomicrmw.start
+; OUTLINE_ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE_ATOMICS-NEXT:    ldxr w8, [x9]
+; OUTLINE_ATOMICS-NEXT:    cmp w8, w0
+; OUTLINE_ATOMICS-NEXT:    csel w10, w8, w0, le
+; OUTLINE_ATOMICS-NEXT:    stxr w11, w10, [x9]
+; OUTLINE_ATOMICS-NEXT:    cbnz w11, .LBB26_1
+; OUTLINE_ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE_ATOMICS-NEXT:    mov w0, w8
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw min i32* @var32, i32 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
   ; w0 below is a reasonable guess but could change: it certainly comes into the
   ;  function there.
 
 ; CHECK-NEXT: cmp w[[OLD]], w0
 ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, le
 
 
 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
    ret i32 %old
 }
 
 define i64 @test_atomic_load_min_i64(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_min_i64:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_min_i64:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    adrp x9, var64
+; OUTLINE_ATOMICS-NEXT:    add x9, x9, :lo12:var64
+; OUTLINE_ATOMICS-NEXT:  .LBB27_1: // %atomicrmw.start
+; OUTLINE_ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE_ATOMICS-NEXT:    ldaxr x8, [x9]
+; OUTLINE_ATOMICS-NEXT:    cmp x8, x0
+; OUTLINE_ATOMICS-NEXT:    csel x10, x8, x0, le
+; OUTLINE_ATOMICS-NEXT:    stlxr w11, x10, [x9]
+; OUTLINE_ATOMICS-NEXT:    cbnz w11, .LBB27_1
+; OUTLINE_ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE_ATOMICS-NEXT:    mov x0, x8
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw min i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
   ; x0 below is a reasonable guess but could change: it certainly comes into the
   ; function there.
 
 ; CHECK-NEXT: cmp x[[OLD]], x0
 ; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, le
 
 
 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov x0, x[[OLD]]
    ret i64 %old
 }
 
 define i8 @test_atomic_load_max_i8(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i8:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_max_i8:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    adrp x9, var8
+; OUTLINE_ATOMICS-NEXT:    add x9, x9, :lo12:var8
+; OUTLINE_ATOMICS-NEXT:  .LBB28_1: // %atomicrmw.start
+; OUTLINE_ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE_ATOMICS-NEXT:    ldaxrb w10, [x9]
+; OUTLINE_ATOMICS-NEXT:    sxtb w8, w10
+; OUTLINE_ATOMICS-NEXT:    cmp w8, w0, sxtb
+; OUTLINE_ATOMICS-NEXT:    csel w10, w10, w0, gt
+; OUTLINE_ATOMICS-NEXT:    stlxrb w11, w10, [x9]
+; OUTLINE_ATOMICS-NEXT:    cbnz w11, .LBB28_1
+; OUTLINE_ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE_ATOMICS-NEXT:    mov w0, w8
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw max i8* @var8, i8 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; CHECK: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
   ; w0 below is a reasonable guess but could change: it certainly comes into the

 ; CHECK-NOT: dmb
 
 ; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD_EXT]]
    ret i8 %old
 }
 
 define i16 @test_atomic_load_max_i16(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i16:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_max_i16:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    adrp x9, var16
+; OUTLINE_ATOMICS-NEXT:    add x9, x9, :lo12:var16
+; OUTLINE_ATOMICS-NEXT:  .LBB29_1: // %atomicrmw.start
+; OUTLINE_ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE_ATOMICS-NEXT:    ldaxrh w10, [x9]
+; OUTLINE_ATOMICS-NEXT:    sxth w8, w10
+; OUTLINE_ATOMICS-NEXT:    cmp w8, w0, sxth
+; OUTLINE_ATOMICS-NEXT:    csel w10, w10, w0, gt
+; OUTLINE_ATOMICS-NEXT:    stxrh w11, w10, [x9]
+; OUTLINE_ATOMICS-NEXT:    cbnz w11, .LBB29_1
+; OUTLINE_ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE_ATOMICS-NEXT:    mov w0, w8
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw max i16* @var16, i16 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; CHECK: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
   ; w0 below is a reasonable guess but could change: it certainly comes into the

 ; CHECK-NOT: dmb
 
 ; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD_EXT]]
    ret i16 %old
 }
 
 define i32 @test_atomic_load_max_i32(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i32:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_max_i32:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    adrp x9, var32
+; OUTLINE_ATOMICS-NEXT:    add x9, x9, :lo12:var32
+; OUTLINE_ATOMICS-NEXT:  .LBB30_1: // %atomicrmw.start
+; OUTLINE_ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE_ATOMICS-NEXT:    ldxr w8, [x9]
+; OUTLINE_ATOMICS-NEXT:    cmp w8, w0
+; OUTLINE_ATOMICS-NEXT:    csel w10, w8, w0, gt
+; OUTLINE_ATOMICS-NEXT:    stlxr w11, w10, [x9]
+; OUTLINE_ATOMICS-NEXT:    cbnz w11, .LBB30_1
+; OUTLINE_ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE_ATOMICS-NEXT:    mov w0, w8
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw max i32* @var32, i32 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
   ; w0 below is a reasonable guess but could change: it certainly comes into the
   ;  function there.
 
 ; CHECK-NEXT: cmp w[[OLD]], w0
 ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, gt
 
 
 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
    ret i32 %old
 }
 
 define i64 @test_atomic_load_max_i64(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_max_i64:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_max_i64:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    adrp x9, var64
+; OUTLINE_ATOMICS-NEXT:    add x9, x9, :lo12:var64
+; OUTLINE_ATOMICS-NEXT:  .LBB31_1: // %atomicrmw.start
+; OUTLINE_ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE_ATOMICS-NEXT:    ldxr x8, [x9]
+; OUTLINE_ATOMICS-NEXT:    cmp x8, x0
+; OUTLINE_ATOMICS-NEXT:    csel x10, x8, x0, gt
+; OUTLINE_ATOMICS-NEXT:    stxr w11, x10, [x9]
+; OUTLINE_ATOMICS-NEXT:    cbnz w11, .LBB31_1
+; OUTLINE_ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE_ATOMICS-NEXT:    mov x0, x8
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw max i64* @var64, i64 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
   ; x0 below is a reasonable guess but could change: it certainly comes into the
   ; function there.
 
 ; CHECK-NEXT: cmp x[[OLD]], x0
 ; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, gt
 
 
 ; CHECK-NEXT: stxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov x0, x[[OLD]]
    ret i64 %old
 }
 
 define i8 @test_atomic_load_umin_i8(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i8:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_umin_i8:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    adrp x9, var8
+; OUTLINE_ATOMICS-NEXT:    add x9, x9, :lo12:var8
+; OUTLINE_ATOMICS-NEXT:  .LBB32_1: // %atomicrmw.start
+; OUTLINE_ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE_ATOMICS-NEXT:    ldxrb w8, [x9]
+; OUTLINE_ATOMICS-NEXT:    cmp w8, w0, uxtb
+; OUTLINE_ATOMICS-NEXT:    csel w10, w8, w0, ls
+; OUTLINE_ATOMICS-NEXT:    stxrb w11, w10, [x9]
+; OUTLINE_ATOMICS-NEXT:    cbnz w11, .LBB32_1
+; OUTLINE_ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE_ATOMICS-NEXT:    mov w0, w8
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw umin i8* @var8, i8 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; CHECK: ldxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
   ; w0 below is a reasonable guess but could change: it certainly comes into the
   ;  function there.
 
 ; CHECK-NEXT: cmp w[[OLD]], w0, uxtb
 ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, ls
 
 
 ; CHECK-NEXT: stxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
    ret i8 %old
 }
 
 define i16 @test_atomic_load_umin_i16(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i16:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_umin_i16:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    adrp x9, var16
+; OUTLINE_ATOMICS-NEXT:    add x9, x9, :lo12:var16
+; OUTLINE_ATOMICS-NEXT:  .LBB33_1: // %atomicrmw.start
+; OUTLINE_ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE_ATOMICS-NEXT:    ldaxrh w8, [x9]
+; OUTLINE_ATOMICS-NEXT:    cmp w8, w0, uxth
+; OUTLINE_ATOMICS-NEXT:    csel w10, w8, w0, ls
+; OUTLINE_ATOMICS-NEXT:    stxrh w11, w10, [x9]
+; OUTLINE_ATOMICS-NEXT:    cbnz w11, .LBB33_1
+; OUTLINE_ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE_ATOMICS-NEXT:    mov w0, w8
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw umin i16* @var16, i16 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; CHECK: ldaxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
   ; w0 below is a reasonable guess but could change: it certainly comes into the
   ;  function there.
 
 ; CHECK-NEXT: cmp w[[OLD]], w0, uxth
 ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, ls
 
 
 ; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
    ret i16 %old
 }
 
 define i32 @test_atomic_load_umin_i32(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i32:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_umin_i32:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    adrp x9, var32
+; OUTLINE_ATOMICS-NEXT:    add x9, x9, :lo12:var32
+; OUTLINE_ATOMICS-NEXT:  .LBB34_1: // %atomicrmw.start
+; OUTLINE_ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE_ATOMICS-NEXT:    ldaxr w8, [x9]
+; OUTLINE_ATOMICS-NEXT:    cmp w8, w0
+; OUTLINE_ATOMICS-NEXT:    csel w10, w8, w0, ls
+; OUTLINE_ATOMICS-NEXT:    stlxr w11, w10, [x9]
+; OUTLINE_ATOMICS-NEXT:    cbnz w11, .LBB34_1
+; OUTLINE_ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE_ATOMICS-NEXT:    mov w0, w8
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw umin i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
   ; w0 below is a reasonable guess but could change: it certainly comes into the
   ;  function there.
 
 ; CHECK-NEXT: cmp w[[OLD]], w0
 ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, ls
 
 
 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
    ret i32 %old
 }
 
 define i64 @test_atomic_load_umin_i64(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umin_i64:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_umin_i64:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    adrp x9, var64
+; OUTLINE_ATOMICS-NEXT:    add x9, x9, :lo12:var64
+; OUTLINE_ATOMICS-NEXT:  .LBB35_1: // %atomicrmw.start
+; OUTLINE_ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE_ATOMICS-NEXT:    ldaxr x8, [x9]
+; OUTLINE_ATOMICS-NEXT:    cmp x8, x0
+; OUTLINE_ATOMICS-NEXT:    csel x10, x8, x0, ls
+; OUTLINE_ATOMICS-NEXT:    stlxr w11, x10, [x9]
+; OUTLINE_ATOMICS-NEXT:    cbnz w11, .LBB35_1
+; OUTLINE_ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE_ATOMICS-NEXT:    mov x0, x8
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw umin i64* @var64, i64 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; CHECK: ldaxr x[[OLD:[0-9]+]], [x[[ADDR]]]
   ; x0 below is a reasonable guess but could change: it certainly comes into the
   ; function there.
 
 ; CHECK-NEXT: cmp x[[OLD]], x0
 ; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, ls
 
 
 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov x0, x[[OLD]]
    ret i64 %old
 }
 
 define i8 @test_atomic_load_umax_i8(i8 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i8:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_umax_i8:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    adrp x9, var8
+; OUTLINE_ATOMICS-NEXT:    add x9, x9, :lo12:var8
+; OUTLINE_ATOMICS-NEXT:  .LBB36_1: // %atomicrmw.start
+; OUTLINE_ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE_ATOMICS-NEXT:    ldaxrb w8, [x9]
+; OUTLINE_ATOMICS-NEXT:    cmp w8, w0, uxtb
+; OUTLINE_ATOMICS-NEXT:    csel w10, w8, w0, hi
+; OUTLINE_ATOMICS-NEXT:    stlxrb w11, w10, [x9]
+; OUTLINE_ATOMICS-NEXT:    cbnz w11, .LBB36_1
+; OUTLINE_ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE_ATOMICS-NEXT:    mov w0, w8
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw umax i8* @var8, i8 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; CHECK: ldaxrb w[[OLD:[0-9]+]], [x[[ADDR]]]
   ; w0 below is a reasonable guess but could change: it certainly comes into the
   ;  function there.
 
 ; CHECK-NEXT: cmp w[[OLD]], w0, uxtb
 ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi
 
 
 ; CHECK-NEXT: stlxrb [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
    ret i8 %old
 }
 
 define i16 @test_atomic_load_umax_i16(i16 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i16:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_umax_i16:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    adrp x9, var16
+; OUTLINE_ATOMICS-NEXT:    add x9, x9, :lo12:var16
+; OUTLINE_ATOMICS-NEXT:  .LBB37_1: // %atomicrmw.start
+; OUTLINE_ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE_ATOMICS-NEXT:    ldxrh w8, [x9]
+; OUTLINE_ATOMICS-NEXT:    cmp w8, w0, uxth
+; OUTLINE_ATOMICS-NEXT:    csel w10, w8, w0, hi
+; OUTLINE_ATOMICS-NEXT:    stxrh w11, w10, [x9]
+; OUTLINE_ATOMICS-NEXT:    cbnz w11, .LBB37_1
+; OUTLINE_ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE_ATOMICS-NEXT:    mov w0, w8
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw umax i16* @var16, i16 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; CHECK: ldxrh w[[OLD:[0-9]+]], [x[[ADDR]]]
   ; w0 below is a reasonable guess but could change: it certainly comes into the
   ;  function there.
 
 ; CHECK-NEXT: cmp w[[OLD]], w0, uxth
 ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi
 
 
 ; CHECK-NEXT: stxrh [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
    ret i16 %old
 }
 
 define i32 @test_atomic_load_umax_i32(i32 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i32:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_umax_i32:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    adrp x9, var32
+; OUTLINE_ATOMICS-NEXT:    add x9, x9, :lo12:var32
+; OUTLINE_ATOMICS-NEXT:  .LBB38_1: // %atomicrmw.start
+; OUTLINE_ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE_ATOMICS-NEXT:    ldaxr w8, [x9]
+; OUTLINE_ATOMICS-NEXT:    cmp w8, w0
+; OUTLINE_ATOMICS-NEXT:    csel w10, w8, w0, hi
+; OUTLINE_ATOMICS-NEXT:    stlxr w11, w10, [x9]
+; OUTLINE_ATOMICS-NEXT:    cbnz w11, .LBB38_1
+; OUTLINE_ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE_ATOMICS-NEXT:    mov w0, w8
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw umax i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; CHECK: ldaxr w[[OLD:[0-9]+]], [x[[ADDR]]]
   ; w0 below is a reasonable guess but could change: it certainly comes into the
   ;  function there.
 
 ; CHECK-NEXT: cmp w[[OLD]], w0
 ; CHECK-NEXT: csel [[NEW:w[0-9]+]], w[[OLD]], w0, hi
 
 
 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
    ret i32 %old
 }
 
 define i64 @test_atomic_load_umax_i64(i64 %offset) nounwind {
 ; CHECK-LABEL: test_atomic_load_umax_i64:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_umax_i64:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    adrp x9, var64
+; OUTLINE_ATOMICS-NEXT:    add x9, x9, :lo12:var64
+; OUTLINE_ATOMICS-NEXT:  .LBB39_1: // %atomicrmw.start
+; OUTLINE_ATOMICS-NEXT:    // =>This Inner Loop Header: Depth=1
+; OUTLINE_ATOMICS-NEXT:    ldxr x8, [x9]
+; OUTLINE_ATOMICS-NEXT:    cmp x8, x0
+; OUTLINE_ATOMICS-NEXT:    csel x10, x8, x0, hi
+; OUTLINE_ATOMICS-NEXT:    stlxr w11, x10, [x9]
+; OUTLINE_ATOMICS-NEXT:    cbnz w11, .LBB39_1
+; OUTLINE_ATOMICS-NEXT:  // %bb.2: // %atomicrmw.end
+; OUTLINE_ATOMICS-NEXT:    mov x0, x8
+; OUTLINE_ATOMICS-NEXT:    ret
    %old = atomicrmw umax i64* @var64, i64 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: .LBB{{[0-9]+}}_1:
 ; CHECK: ldxr x[[OLD:[0-9]+]], [x[[ADDR]]]
   ; x0 below is a reasonable guess but could change: it certainly comes into the
   ; function there.
 
 ; CHECK-NEXT: cmp x[[OLD]], x0
 ; CHECK-NEXT: csel [[NEW:x[0-9]+]], x[[OLD]], x0, hi
 
 
 ; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], .LBB{{[0-9]+}}_1
 ; CHECK-NOT: dmb
 
 ; CHECK: mov x0, x[[OLD]]
    ret i64 %old
 }
 
 define i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind {
 ; CHECK-LABEL: test_atomic_cmpxchg_i8:
+; OUTLINE_ATOMICS-LABEL: test_atomic_cmpxchg_i8:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE_ATOMICS-NEXT:    adrp x2, var8
+; OUTLINE_ATOMICS-NEXT:    add x2, x2, :lo12:var8
+; OUTLINE_ATOMICS-NEXT:    bl __aarch64_cas1_acq
+; OUTLINE_ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE_ATOMICS-NEXT:    ret
    %pair = cmpxchg i8* @var8, i8 %wanted, i8 %new acquire acquire
    %old = extractvalue { i8, i1 } %pair, 0
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 
 ; CHECK: [[STARTAGAIN:.LBB[0-9]+_[0-9]+]]:

 ; CHECK-NOT: dmb
 
 ; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
    ret i8 %old
 }
 
 define i16 @test_atomic_cmpxchg_i16(i16 %wanted, i16 %new) nounwind {
 ; CHECK-LABEL: test_atomic_cmpxchg_i16:
+; OUTLINE_ATOMICS-LABEL: test_atomic_cmpxchg_i16:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE_ATOMICS-NEXT:    adrp x2, var16
+; OUTLINE_ATOMICS-NEXT:    add x2, x2, :lo12:var16
+; OUTLINE_ATOMICS-NEXT:    bl __aarch64_cas2_acq_rel
+; OUTLINE_ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE_ATOMICS-NEXT:    ret
    %pair = cmpxchg i16* @var16, i16 %wanted, i16 %new seq_cst seq_cst
    %old = extractvalue { i16, i1 } %pair, 0
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
 
 ; CHECK: [[STARTAGAIN:.LBB[0-9]+_[0-9]+]]:

 ; CHECK-NOT: dmb
 
 ; CHECK: mov {{[xw]}}0, {{[xw]}}[[OLD]]
    ret i16 %old
 }
 
 define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind {
 ; CHECK-LABEL: test_atomic_cmpxchg_i32:
+; OUTLINE_ATOMICS-LABEL: test_atomic_cmpxchg_i32:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
+; OUTLINE_ATOMICS-NEXT:    adrp x2, var32
+; OUTLINE_ATOMICS-NEXT:    add x2, x2, :lo12:var32
+; OUTLINE_ATOMICS-NEXT:    bl __aarch64_cas4_rel
+; OUTLINE_ATOMICS-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
+; OUTLINE_ATOMICS-NEXT:    ret
    %pair = cmpxchg i32* @var32, i32 %wanted, i32 %new release monotonic
    %old = extractvalue { i32, i1 } %pair, 0
 
 ; CHECK: mov {{[xw]}}[[WANTED:[0-9]+]], {{[xw]}}0
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var32
 
 ; CHECK: [[STARTAGAIN:.LBB[0-9]+_[0-9]+]]:
 ; CHECK: ldxr w[[OLD:[0-9]+]], [x[[ADDR]]]
 ; CHECK-NEXT: cmp w[[OLD]], w[[WANTED]]
 ; CHECK-NEXT: b.ne [[GET_OUT:.LBB[0-9]+_[0-9]+]]
 ; CHECK: stlxr [[STATUS:w[0-9]+]], {{w[0-9]+}}, [x[[ADDR]]]
 ; CHECK-NEXT: cbnz [[STATUS]], [[STARTAGAIN]]
 ; CHECK: [[GET_OUT]]:
 ; CHECK: clrex
 ; CHECK-NOT: dmb
    ret i32 %old
 }
 
 define void @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind {
 ; CHECK-LABEL: test_atomic_cmpxchg_i64:
+; OUTLINE_ATOMICS-LABEL: test_atomic_cmpxchg_i64:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
+; OUTLINE_ATOMICS-NEXT:    adrp x19, var64
+; OUTLINE_ATOMICS-NEXT:    add x19, x19, :lo12:var64
+; OUTLINE_ATOMICS-NEXT:    mov x2, x19
+; OUTLINE_ATOMICS-NEXT:    bl __aarch64_cas8_relax
+; OUTLINE_ATOMICS-NEXT:    str x0, [x19]
+; OUTLINE_ATOMICS-NEXT:    ldp x30, x19, [sp], #16 // 16-byte Folded Reload
+; OUTLINE_ATOMICS-NEXT:    ret
    %pair = cmpxchg i64* @var64, i64 %wanted, i64 %new monotonic monotonic
    %old = extractvalue { i64, i1 } %pair, 0
 
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var64
 
 ; CHECK: [[STARTAGAIN:.LBB[0-9]+_[0-9]+]]:

 
 ; CHECK: str x[[OLD]],
    store i64 %old, i64* @var64
    ret void
 }
 
 define i8 @test_atomic_load_monotonic_i8() nounwind {
 ; CHECK-LABEL: test_atomic_load_monotonic_i8:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_monotonic_i8:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    adrp x8, var8
+; OUTLINE_ATOMICS-NEXT:    ldrb w0, [x8, :lo12:var8]
+; OUTLINE_ATOMICS-NEXT:    ret
   %val = load atomic i8, i8* @var8 monotonic, align 1
 ; CHECK-NOT: dmb
 ; CHECK: adrp x[[HIADDR:[0-9]+]], var8
 ; CHECK: ldrb w0, [x[[HIADDR]], {{#?}}:lo12:var8]
 ; CHECK-NOT: dmb
 
   ret i8 %val
 }
 
 define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind {
 ; CHECK-LABEL: test_atomic_load_monotonic_regoff_i8:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_monotonic_regoff_i8:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    ldrb w0, [x0, x1]
+; OUTLINE_ATOMICS-NEXT:    ret
   %addr_int = add i64 %base, %off
   %addr = inttoptr i64 %addr_int to i8*
 
   %val = load atomic i8, i8* %addr monotonic, align 1
 ; CHECK-NOT: dmb
 ; CHECK: ldrb w0, [x0, x1]
 ; CHECK-NOT: dmb
 
   ret i8 %val
 }
 
 define i8 @test_atomic_load_acquire_i8() nounwind {
 ; CHECK-LABEL: test_atomic_load_acquire_i8:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_acquire_i8:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    adrp x8, var8
+; OUTLINE_ATOMICS-NEXT:    add x8, x8, :lo12:var8
+; OUTLINE_ATOMICS-NEXT:    ldarb w0, [x8]
+; OUTLINE_ATOMICS-NEXT:    ret
   %val = load atomic i8, i8* @var8 acquire, align 1
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
 ; CHECK-NOT: dmb
 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var8
 ; CHECK-NOT: dmb
 ; CHECK: ldarb w0, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i8 %val
 }
 
 define i8 @test_atomic_load_seq_cst_i8() nounwind {
 ; CHECK-LABEL: test_atomic_load_seq_cst_i8:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_seq_cst_i8:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    adrp x8, var8
+; OUTLINE_ATOMICS-NEXT:    add x8, x8, :lo12:var8
+; OUTLINE_ATOMICS-NEXT:    ldarb w0, [x8]
+; OUTLINE_ATOMICS-NEXT:    ret
   %val = load atomic i8, i8* @var8 seq_cst, align 1
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[HIADDR:x[0-9]+]], var8
 ; CHECK-NOT: dmb
 ; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], {{#?}}:lo12:var8
 ; CHECK-NOT: dmb
 ; CHECK: ldarb w0, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i8 %val
 }
 
 define i16 @test_atomic_load_monotonic_i16() nounwind {
 ; CHECK-LABEL: test_atomic_load_monotonic_i16:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_monotonic_i16:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    adrp x8, var16
+; OUTLINE_ATOMICS-NEXT:    ldrh w0, [x8, :lo12:var16]
+; OUTLINE_ATOMICS-NEXT:    ret
   %val = load atomic i16, i16* @var16 monotonic, align 2
 ; CHECK-NOT: dmb
 ; CHECK: adrp x[[HIADDR:[0-9]+]], var16
 ; CHECK-NOT: dmb
 ; CHECK: ldrh w0, [x[[HIADDR]], {{#?}}:lo12:var16]
 ; CHECK-NOT: dmb
 
   ret i16 %val
 }
 
 define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind {
 ; CHECK-LABEL: test_atomic_load_monotonic_regoff_i32:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_monotonic_regoff_i32:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    ldr w0, [x0, x1]
+; OUTLINE_ATOMICS-NEXT:    ret
   %addr_int = add i64 %base, %off
   %addr = inttoptr i64 %addr_int to i32*
 
   %val = load atomic i32, i32* %addr monotonic, align 4
 ; CHECK-NOT: dmb
 ; CHECK: ldr w0, [x0, x1]
 ; CHECK-NOT: dmb
 
   ret i32 %val
 }
 
 define i64 @test_atomic_load_seq_cst_i64() nounwind {
 ; CHECK-LABEL: test_atomic_load_seq_cst_i64:
+; OUTLINE_ATOMICS-LABEL: test_atomic_load_seq_cst_i64:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    adrp x8, var64
+; OUTLINE_ATOMICS-NEXT:    add x8, x8, :lo12:var64
+; OUTLINE_ATOMICS-NEXT:    ldar x0, [x8]
+; OUTLINE_ATOMICS-NEXT:    ret
   %val = load atomic i64, i64* @var64 seq_cst, align 8
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[HIADDR:x[0-9]+]], var64
 ; CHECK-NOT: dmb
 ; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], {{#?}}:lo12:var64
 ; CHECK-NOT: dmb
 ; CHECK: ldar x0, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret i64 %val
 }
 
 define void @test_atomic_store_monotonic_i8(i8 %val) nounwind {
 ; CHECK-LABEL: test_atomic_store_monotonic_i8:
+; OUTLINE_ATOMICS-LABEL: test_atomic_store_monotonic_i8:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    adrp x8, var8
+; OUTLINE_ATOMICS-NEXT:    strb w0, [x8, :lo12:var8]
+; OUTLINE_ATOMICS-NEXT:    ret
   store atomic i8 %val, i8* @var8 monotonic, align 1
 ; CHECK: adrp x[[HIADDR:[0-9]+]], var8
 ; CHECK: strb w0, [x[[HIADDR]], {{#?}}:lo12:var8]
 
   ret void
 }
 
 define void @test_atomic_store_monotonic_regoff_i8(i64 %base, i64 %off, i8 %val) nounwind {
 ; CHECK-LABEL: test_atomic_store_monotonic_regoff_i8:
-
+; OUTLINE_ATOMICS-LABEL: test_atomic_store_monotonic_regoff_i8:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    strb w2, [x0, x1]
+; OUTLINE_ATOMICS-NEXT:    ret
   %addr_int = add i64 %base, %off
   %addr = inttoptr i64 %addr_int to i8*
 
   store atomic i8 %val, i8* %addr monotonic, align 1
 ; CHECK: strb w2, [x0, x1]
 
   ret void
 }
 define void @test_atomic_store_release_i8(i8 %val) nounwind {
 ; CHECK-LABEL: test_atomic_store_release_i8:
+; OUTLINE_ATOMICS-LABEL: test_atomic_store_release_i8:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    adrp x8, var8
+; OUTLINE_ATOMICS-NEXT:    add x8, x8, :lo12:var8
+; OUTLINE_ATOMICS-NEXT:    stlrb w0, [x8]
+; OUTLINE_ATOMICS-NEXT:    ret
   store atomic i8 %val, i8* @var8 release, align 1
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[HIADDR:x[0-9]+]], var8
 ; CHECK-NOT: dmb
 ; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], {{#?}}:lo12:var8
 ; CHECK-NOT: dmb
 ; CHECK: stlrb w0, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_store_seq_cst_i8(i8 %val) nounwind {
 ; CHECK-LABEL: test_atomic_store_seq_cst_i8:
+; OUTLINE_ATOMICS-LABEL: test_atomic_store_seq_cst_i8:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    adrp x8, var8
+; OUTLINE_ATOMICS-NEXT:    add x8, x8, :lo12:var8
+; OUTLINE_ATOMICS-NEXT:    stlrb w0, [x8]
+; OUTLINE_ATOMICS-NEXT:    ret
   store atomic i8 %val, i8* @var8 seq_cst, align 1
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[HIADDR:x[0-9]+]], var8
 ; CHECK-NOT: dmb
 ; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], {{#?}}:lo12:var8
 ; CHECK-NOT: dmb
 ; CHECK: stlrb w0, [x[[ADDR]]]
 ; CHECK-NOT: dmb
 
   ret void
 }
 
 define void @test_atomic_store_monotonic_i16(i16 %val) nounwind {
 ; CHECK-LABEL: test_atomic_store_monotonic_i16:
+; OUTLINE_ATOMICS-LABEL: test_atomic_store_monotonic_i16:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    adrp x8, var16
+; OUTLINE_ATOMICS-NEXT:    strh w0, [x8, :lo12:var16]
+; OUTLINE_ATOMICS-NEXT:    ret
   store atomic i16 %val, i16* @var16 monotonic, align 2
 ; CHECK-NOT: dmb
 ; CHECK: adrp x[[HIADDR:[0-9]+]], var16
 ; CHECK-NOT: dmb
 ; CHECK: strh w0, [x[[HIADDR]], {{#?}}:lo12:var16]
 ; CHECK-NOT: dmb
   ret void
 }
 
 define void @test_atomic_store_monotonic_regoff_i32(i64 %base, i64 %off, i32 %val) nounwind {
 ; CHECK-LABEL: test_atomic_store_monotonic_regoff_i32:
-
+; OUTLINE_ATOMICS-LABEL: test_atomic_store_monotonic_regoff_i32:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    str w2, [x0, x1]
+; OUTLINE_ATOMICS-NEXT:    ret
   %addr_int = add i64 %base, %off
   %addr = inttoptr i64 %addr_int to i32*
 
   store atomic i32 %val, i32* %addr monotonic, align 4
 ; CHECK-NOT: dmb
 ; CHECK: str w2, [x0, x1]
 ; CHECK-NOT: dmb
 
   ret void
 }
 
 define void @test_atomic_store_release_i64(i64 %val) nounwind {
 ; CHECK-LABEL: test_atomic_store_release_i64:
+; OUTLINE_ATOMICS-LABEL: test_atomic_store_release_i64:
+; OUTLINE_ATOMICS:       // %bb.0:
+; OUTLINE_ATOMICS-NEXT:    adrp x8, var64
+; OUTLINE_ATOMICS-NEXT:    add x8, x8, :lo12:var64
+; OUTLINE_ATOMICS-NEXT:    stlr x0, [x8]
+; OUTLINE_ATOMICS-NEXT:    ret
   store atomic i64 %val, i64* @var64 release, align 8
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[HIADDR:x[0-9]+]], var64
 ; CHECK-NOT: dmb
 ; CHECK: add x[[ADDR:[0-9]+]], [[HIADDR]], {{#?}}:lo12:var64
 ; CHECK-NOT: dmb
 ; CHECK: stlr x0, [x[[ADDR]]]
 ; CHECK-NOT: dmb
   ret void
 }

llvm/test/CodeGen/AArch64/cmpxchg-O0.ll

 ; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -O0 -fast-isel=0 -global-isel=false %s -o - | FileCheck -enable-var-scope %s
+; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -O0 -fast-isel=0 -global-isel=false -mattr=+outline-atomics %s -o - | FileCheck -enable-var-scope %s --check-prefix=OUTLINE-ATOMICS
 
 define { i8, i1 } @test_cmpxchg_8(i8* %addr, i8 %desired, i8 %new) nounwind {
+; OUTLINE-ATOMICS: bl __aarch64_cas1_acq_rel
 ; CHECK-LABEL: test_cmpxchg_8:
 ; CHECK:     mov [[ADDR:x[0-9]+]], x0
 ; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
 ; CHECK:     ldaxrb [[OLD:w[0-9]+]], {{\[}}[[ADDR]]{{\]}}
 ; CHECK:     cmp [[OLD]], w1, uxtb
 ; CHECK:     b.ne [[DONE:.LBB[0-9]+_[0-9]+]]
 ; CHECK:     stlxrb [[STATUS:w[0-9]+]], w2, {{\[}}[[ADDR]]{{\]}}
 ; CHECK:     cbnz [[STATUS]], [[RETRY]]
 ; CHECK: [[DONE]]:
 ; CHECK:     subs {{w[0-9]+}}, [[OLD]], w1, uxtb
 ; CHECK:     cset {{w[0-9]+}}, eq
   %res = cmpxchg i8* %addr, i8 %desired, i8 %new seq_cst monotonic
   ret { i8, i1 } %res
 }
 
 define { i16, i1 } @test_cmpxchg_16(i16* %addr, i16 %desired, i16 %new) nounwind {
+; OUTLINE-ATOMICS: bl __aarch64_cas2_acq_rel
 ; CHECK-LABEL: test_cmpxchg_16:
 ; CHECK:     mov [[ADDR:x[0-9]+]], x0
 ; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
 ; CHECK:     ldaxrh [[OLD:w[0-9]+]], {{\[}}[[ADDR]]{{\]}}
 ; CHECK:     cmp [[OLD]], w1, uxth
 ; CHECK:     b.ne [[DONE:.LBB[0-9]+_[0-9]+]]
 ; CHECK:     stlxrh [[STATUS:w[3-9]]], w2, {{\[}}[[ADDR]]{{\]}}
 ; CHECK:     cbnz [[STATUS]], [[RETRY]]
 ; CHECK: [[DONE]]:
 ; CHECK:     subs {{w[0-9]+}}, [[OLD]], w1
 ; CHECK:     cset {{w[0-9]+}}, eq
   %res = cmpxchg i16* %addr, i16 %desired, i16 %new seq_cst monotonic
   ret { i16, i1 } %res
 }
 
 define { i32, i1 } @test_cmpxchg_32(i32* %addr, i32 %desired, i32 %new) nounwind {
+; OUTLINE-ATOMICS: bl __aarch64_cas4_acq_rel
 ; CHECK-LABEL: test_cmpxchg_32:
 ; CHECK:     mov [[ADDR:x[0-9]+]], x0
 ; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
 ; CHECK:     ldaxr [[OLD:w[0-9]+]], {{\[}}[[ADDR]]{{\]}}
 ; CHECK:     cmp [[OLD]], w1
 ; CHECK:     b.ne [[DONE:.LBB[0-9]+_[0-9]+]]
 ; CHECK:     stlxr [[STATUS:w[0-9]+]], w2, {{\[}}[[ADDR]]{{\]}}
 ; CHECK:     cbnz [[STATUS]], [[RETRY]]
 ; CHECK: [[DONE]]:
 ; CHECK:     subs {{w[0-9]+}}, [[OLD]], w1
 ; CHECK:     cset {{w[0-9]+}}, eq
   %res = cmpxchg i32* %addr, i32 %desired, i32 %new seq_cst monotonic
   ret { i32, i1 } %res
 }
 
 define { i64, i1 } @test_cmpxchg_64(i64* %addr, i64 %desired, i64 %new) nounwind {
+; OUTLINE-ATOMICS: bl __aarch64_cas8_acq_rel
 ; CHECK-LABEL: test_cmpxchg_64:
 ; CHECK:     mov [[ADDR:x[0-9]+]], x0
 ; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
 ; CHECK:     ldaxr [[OLD:x[0-9]+]], {{\[}}[[ADDR]]{{\]}}
 ; CHECK:     cmp [[OLD]], x1
 ; CHECK:     b.ne [[DONE:.LBB[0-9]+_[0-9]+]]
 ; CHECK:     stlxr [[STATUS:w[0-9]+]], x2, {{\[}}[[ADDR]]{{\]}}
 ; CHECK:     cbnz [[STATUS]], [[RETRY]]
 ; CHECK: [[DONE]]:
 ; CHECK:     subs {{x[0-9]+}}, [[OLD]], x1
 ; CHECK:     cset {{w[0-9]+}}, eq
   %res = cmpxchg i64* %addr, i64 %desired, i64 %new seq_cst monotonic
   ret { i64, i1 } %res
 }
 
 define { i128, i1 } @test_cmpxchg_128(i128* %addr, i128 %desired, i128 %new) nounwind {
+; OUTLINE-ATOMICS: bl __aarch64_cas16_acq_rel
 ; CHECK-LABEL: test_cmpxchg_128:
 ; CHECK:     mov [[ADDR:x[0-9]+]], x0
 ; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
 ; CHECK:     ldaxp [[OLD_LO:x[0-9]+]], [[OLD_HI:x[0-9]+]], {{\[}}[[ADDR]]{{\]}}
 ; CHECK:     cmp [[OLD_LO]], x2
 ; CHECK:     cset [[CMP_TMP:w[0-9]+]], ne
 ; CHECK:     cmp [[OLD_HI]], x3
 ; CHECK:     cinc [[CMP:w[0-9]+]], [[CMP_TMP]], ne
 ; CHECK:     cbnz [[CMP]], [[DONE:.LBB[0-9]+_[0-9]+]]
 ; CHECK:     stlxp [[STATUS:w[0-9]+]], x4, x5, {{\[}}[[ADDR]]{{\]}}
 ; CHECK:     cbnz [[STATUS]], [[RETRY]]
 ; CHECK: [[DONE]]:
   %res = cmpxchg i128* %addr, i128 %desired, i128 %new seq_cst monotonic
   ret { i128, i1 } %res
 }
 
 ; Original implementation assumed the desired & new arguments had already been
 ; type-legalized into some kind of BUILD_PAIR operation and crashed when this
 ; was false.
 @var128 = global i128 0
 define {i128, i1} @test_cmpxchg_128_unsplit(i128* %addr) {
+; OUTLINE-ATOMICS: bl __aarch64_cas16_acq_rel
 ; CHECK-LABEL: test_cmpxchg_128_unsplit:
 ; CHECK:     mov [[ADDR:x[0-9]+]], x0
 ; CHECK:     add x[[VAR128:[0-9]+]], {{x[0-9]+}}, :lo12:var128
 ; CHECK:     ldp [[DESIRED_LO:x[0-9]+]], [[DESIRED_HI:x[0-9]+]], [x[[VAR128]]]
 ; CHECK:     ldp [[NEW_LO:x[0-9]+]], [[NEW_HI:x[0-9]+]], [x[[VAR128]]]
 ; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
 ; CHECK:     ldaxp [[OLD_LO:x[0-9]+]], [[OLD_HI:x[0-9]+]], {{\[}}[[ADDR]]{{\]}}
 ; CHECK:     cmp [[OLD_LO]], [[DESIRED_LO]]

llvm/test/CodeGen/AArch64/cmpxchg-idioms.ll

 ; RUN: llc -mtriple=aarch64-apple-ios7.0 -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-apple-ios7.0 -mattr=+outline-atomics -o - %s | FileCheck %s --check-prefix=OUTLINE-ATOMICS
 
 define i32 @test_return(i32* %p, i32 %oldval, i32 %newval) {
+; OUTLINE-ATOMICS: bl ___aarch64_cas4_acq_rel
 ; CHECK-LABEL: test_return:
 
 ; CHECK: [[LOOP:LBB[0-9]+_[0-9]+]]:
 ; CHECK: ldaxr [[LOADED:w[0-9]+]], [x0]
 ; CHECK: cmp [[LOADED]], w1
 ; CHECK: b.ne [[FAILED:LBB[0-9]+_[0-9]+]]
 
 ; CHECK: stlxr [[STATUS:w[0-9]+]], {{w[0-9]+}}, [x0]
; CHECK: ret
 
   %pair = cmpxchg i32* %p, i32 %oldval, i32 %newval seq_cst seq_cst
   %success = extractvalue { i32, i1 } %pair, 1
   %conv = zext i1 %success to i32
   ret i32 %conv
 }
 
 define i1 @test_return_bool(i8* %value, i8 %oldValue, i8 %newValue) {
+; OUTLINE-ATOMICS: bl ___aarch64_cas1_acq_rel
 ; CHECK-LABEL: test_return_bool:
 
 ; CHECK: [[LOOP:LBB[0-9]+_[0-9]+]]:
 ; CHECK: ldaxrb [[LOADED:w[0-9]+]], [x0]
 ; CHECK: cmp [[LOADED]], w1, uxtb
 ; CHECK: b.ne [[FAILED:LBB[0-9]+_[0-9]+]]
 
 ; CHECK: stlxrb [[STATUS:w[0-9]+]], {{w[0-9]+}}, [x0]
; CHECK: ret
 
   %pair = cmpxchg i8* %value, i8 %oldValue, i8 %newValue acq_rel monotonic
   %success = extractvalue { i8, i1 } %pair, 1
   %failure = xor i1 %success, 1
   ret i1 %failure
 }
 
 define void @test_conditional(i32* %p, i32 %oldval, i32 %newval) {
+; OUTLINE-ATOMICS: bl ___aarch64_cas4_acq_rel
 ; CHECK-LABEL: test_conditional:
 
 ; CHECK: [[LOOP:LBB[0-9]+_[0-9]+]]:
 ; CHECK: ldaxr [[LOADED:w[0-9]+]], [x0]
 ; CHECK: cmp [[LOADED]], w1
 ; CHECK: b.ne [[FAILED:LBB[0-9]+_[0-9]+]]
 
 ; CHECK: stlxr [[STATUS:w[0-9]+]], w2, [x0]

 end:
   ret void
 }
 
 declare void @bar()
 declare void @baz()
 
 define i1 @test_conditional2(i32 %a, i32 %b, i32* %c) {
+; OUTLINE-ATOMICS: bl ___aarch64_cas4_acq_rel
 ; CHECK-LABEL: test_conditional2:
 ; CHECK: [[LOOP:LBB[0-9]+_[0-9]+]]:
 ; CHECK: ldaxr [[LOADED:w[0-9]+]], [x19]
 ; CHECK: cmp [[LOADED]], w21
 ; CHECK: b.ne [[FAILED:LBB[0-9]+_[0-9]+]]
 
 ; CHECK: stlxr [[STATUS:w[0-9]+]], w20, [x19]
 ; CHECK: cbnz [[STATUS]], [[LOOP]]

llvm/test/CodeGen/AArch64/cmpxchg-lse-even-regs.ll

 ; RUN: llc -mtriple arm64-apple-ios -mattr=+lse %s -o - | FileCheck %s
+; RUN: llc -mtriple arm64-apple-ios -mattr=+lse -mattr=+outline-atomics %s -o - | FileCheck %s
 
 ; Only "even,even+1" pairs are valid for CASP instructions. Make sure LLVM
 ; doesn't allocate odd ones and that it can copy them around properly. N.b. we
 ; don't actually check that they're sequential because FileCheck can't; odd/even
 ; will have to be good enough.
 define void @test_atomic_cmpxchg_i128_register_shuffling(i128* %addr, i128 %desired, i128 %new) nounwind {
 ; CHECK-LABEL: test_atomic_cmpxchg_i128_register_shuffling:
 ; CHECK-DAG: mov [[DESIRED_LO:x[0-9]*[02468]]], x1
 ; CHECK-DAG: mov [[DESIRED_HI:x[0-9]*[13579]]], x2
 ; CHECK-DAG: mov [[NEW_LO:x[0-9]*[02468]]], x3
 ; CHECK-DAG: mov [[NEW_HI:x[0-9]*[13579]]], x4
 ; CHECK: caspal [[DESIRED_LO]], [[DESIRED_HI]], [[NEW_LO]], [[NEW_HI]], [x0]
 
   %res = cmpxchg i128* %addr, i128 %desired, i128 %new seq_cst seq_cst
   ret void
 }

llvm/test/Transforms/AtomicExpand/AArch64/expand-atomicrmw-xchg-fp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt -S -mtriple=aarch64-- -atomic-expand %s | FileCheck %s
+; RUN: opt -S -mtriple=aarch64-- -mattr=+outline-atomics -atomic-expand %s | FileCheck %s --check-prefix=OUTLINE-ATOMICS
 
 define void @atomic_swap_f16(half* %ptr, half %val) nounwind {
 ; CHECK-LABEL: @atomic_swap_f16(
 ; CHECK-NEXT:    br label [[ATOMICRMW_START:%.*]]
 ; CHECK:       atomicrmw.start:
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i64 @llvm.aarch64.ldaxr.p0f16(half* [[PTR:%.*]])
 ; CHECK-NEXT:    [[TMP2:%.*]] = trunc i64 [[TMP1]] to i16
 ; CHECK-NEXT:    [[TMP3:%.*]] = bitcast i16 [[TMP2]] to half
 ; CHECK-NEXT:    [[TMP4:%.*]] = bitcast half [[VAL:%.*]] to i16
 ; CHECK-NEXT:    [[TMP5:%.*]] = zext i16 [[TMP4]] to i64
 ; CHECK-NEXT:    [[TMP6:%.*]] = call i32 @llvm.aarch64.stxr.p0f16(i64 [[TMP5]], half* [[PTR]])
 ; CHECK-NEXT:    [[TRYAGAIN:%.*]] = icmp ne i32 [[TMP6]], 0
 ; CHECK-NEXT:    br i1 [[TRYAGAIN]], label [[ATOMICRMW_START]], label [[ATOMICRMW_END:%.*]]
 ; CHECK:       atomicrmw.end:
 ; CHECK-NEXT:    ret void
 ;
+; OUTLINE-ATOMICS-LABEL: @atomic_swap_f16(
+; OUTLINE-ATOMICS-NEXT:    [[T1:%.*]] = atomicrmw xchg half* [[PTR:%.*]], half [[VAL:%.*]] acquire
+; OUTLINE-ATOMICS-NEXT:    ret void
+;
   %t1 = atomicrmw xchg half* %ptr, half %val acquire
   ret void
 }
 
 define void @atomic_swap_f32(float* %ptr, float %val) nounwind {
 ; CHECK-LABEL: @atomic_swap_f32(
 ; CHECK-NEXT:    br label [[ATOMICRMW_START:%.*]]
 ; CHECK:       atomicrmw.start:
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i64 @llvm.aarch64.ldaxr.p0f32(float* [[PTR:%.*]])
 ; CHECK-NEXT:    [[TMP2:%.*]] = trunc i64 [[TMP1]] to i32
 ; CHECK-NEXT:    [[TMP3:%.*]] = bitcast i32 [[TMP2]] to float
 ; CHECK-NEXT:    [[TMP4:%.*]] = bitcast float [[VAL:%.*]] to i32
 ; CHECK-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
 ; CHECK-NEXT:    [[TMP6:%.*]] = call i32 @llvm.aarch64.stxr.p0f32(i64 [[TMP5]], float* [[PTR]])
 ; CHECK-NEXT:    [[TRYAGAIN:%.*]] = icmp ne i32 [[TMP6]], 0
 ; CHECK-NEXT:    br i1 [[TRYAGAIN]], label [[ATOMICRMW_START]], label [[ATOMICRMW_END:%.*]]
 ; CHECK:       atomicrmw.end:
 ; CHECK-NEXT:    ret void
 ;
+; OUTLINE-ATOMICS-LABEL: @atomic_swap_f32(
+; OUTLINE-ATOMICS-NEXT:    [[T1:%.*]] = atomicrmw xchg float* [[PTR:%.*]], float [[VAL:%.*]] acquire
+; OUTLINE-ATOMICS-NEXT:    ret void
+;
   %t1 = atomicrmw xchg float* %ptr, float %val acquire
   ret void
 }
 
 define void @atomic_swap_f64(double* %ptr, double %val) nounwind {
 ; CHECK-LABEL: @atomic_swap_f64(
 ; CHECK-NEXT:    br label [[ATOMICRMW_START:%.*]]
 ; CHECK:       atomicrmw.start:
 ; CHECK-NEXT:    [[TMP1:%.*]] = call i64 @llvm.aarch64.ldaxr.p0f64(double* [[PTR:%.*]])
 ; CHECK-NEXT:    [[TMP2:%.*]] = bitcast i64 [[TMP1]] to double
 ; CHECK-NEXT:    [[TMP3:%.*]] = bitcast double [[VAL:%.*]] to i64
 ; CHECK-NEXT:    [[TMP4:%.*]] = call i32 @llvm.aarch64.stxr.p0f64(i64 [[TMP3]], double* [[PTR]])
 ; CHECK-NEXT:    [[TRYAGAIN:%.*]] = icmp ne i32 [[TMP4]], 0
 ; CHECK-NEXT:    br i1 [[TRYAGAIN]], label [[ATOMICRMW_START]], label [[ATOMICRMW_END:%.*]]
 ; CHECK:       atomicrmw.end:
 ; CHECK-NEXT:    ret void
 ;
+; OUTLINE-ATOMICS-LABEL: @atomic_swap_f64(
+; OUTLINE-ATOMICS-NEXT:    [[T1:%.*]] = atomicrmw xchg double* [[PTR:%.*]], double [[VAL:%.*]] acquire
+; OUTLINE-ATOMICS-NEXT:    ret void
+;
   %t1 = atomicrmw xchg double* %ptr, double %val acquire
   ret void
 }