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[RISCV] Add an ANDI to shift amount of FSL/FSR instructions
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Authored by craig.topper on Nov 5 2020, 11:09 PM.

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Summary

The fshl and fshr intrinsics are defined to modulo their shift amount by the bitwidth of one of their inputs. The FSR/FSL instructions read one extra bit from the shift amount. If that bit is set the inputs are swapped. In order to preserve the semantics of the llvm intrinsics we need to make sure that the extra bit isn't set. DAG combine or instcombine may have removed any mask that was originally present.

We could be smarter here and try to use computeKnownBits to check if the bit is known zero, but wanted to start with correctness.

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craig.topper created this revision.Nov 5 2020, 11:09 PM
Herald added a project: Restricted Project. · View Herald TranscriptNov 5 2020, 11:09 PM
craig.topper requested review of this revision.Nov 5 2020, 11:09 PM
frasercrmck accepted this revision.Nov 12 2020, 3:53 AM

LGTM.

Out of curiosity, can you use anything like computeKnownBits in TableGen patterns or would we have to do something in C++?

This revision is now accepted and ready to land.Nov 12 2020, 3:53 AM

LGTM.

Out of curiosity, can you use anything like computeKnownBits in TableGen patterns or would we have to do something in C++?

It can be called from the code part of a PatFrag. I think X86 does in a few places.