[RISCV] Add isel patterns for fshl with immediate to select FSRI/FSRIW

[craig.topper]

Summary

There is no FSLI instruction, but we can emulate it using FSRI by swapping operands and subtracting the immediate from the bitwidth.

Hopefully I've accounted for the operand order correctly here.

[frasercrmck]

LGTM.

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

if (!MCOp.evaluateAsConstantImm(Imm))
       return false;
     if (STI.getTargetTriple().isArch64Bit())
       return  isUInt<5>(Imm);
     return isUInt<4>(Imm);
   }];
 }
 
 
-// Convert rotl immediate to a rotr immediate.
+// Convert rotl immediate to a rotr immediate for XLen instructions.
 def ImmROTL2R : SDNodeXForm<imm, [{
   uint64_t XLen = Subtarget->getXLen();
   return CurDAG->getTargetConstant(XLen - N->getZExtValue(), SDLoc(N),
                                    N->getValueType(0));
 }]>;
 
+// Convert rotl immediate to a rotr immediate for W instructions.
+def ImmROTL2RW : SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant(32 - N->getZExtValue(), SDLoc(N),
+                                   N->getValueType(0));
+}]>;
+
 //===----------------------------------------------------------------------===//
 // Instruction class templates
 //===----------------------------------------------------------------------===//
 
 // Some of these templates should be moved to RISCVInstrFormats.td once the B
 // extension has been ratified.
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in

 // shift of zero, fshr will return its second operand. fsl and fsr both return
 // $rs1 so the patterns need to have different operand orders.
 def : Pat<(fshl GPR:$rs1, GPR:$rs3, GPR:$rs2),
           (FSL GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
 def : Pat<(fshr GPR:$rs3, GPR:$rs1, GPR:$rs2),
           (FSR GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
 def : Pat<(fshr GPR:$rs3, GPR:$rs1, uimmlog2xlen:$shamt),
           (FSRI GPR:$rs1, GPR:$rs3, uimmlog2xlen:$shamt)>;
+// We can use FSRI for fshl by immediate if we subtract the immediate from
+// XLen and swap the operands.
+def : Pat<(fshl GPR:$rs3, GPR:$rs1, uimmlog2xlen:$shamt),
+          (FSRI GPR:$rs1, GPR:$rs3, (ImmROTL2R uimmlog2xlen:$shamt))>;
 } // Predicates = [HasStdExtZbt]
 
 let Predicates = [HasStdExtZbb] in {
 def : Pat<(ctlz GPR:$rs1), (CLZ GPR:$rs1)>;
 def : Pat<(cttz GPR:$rs1), (CTZ GPR:$rs1)>;
 def : Pat<(ctpop GPR:$rs1), (PCNT GPR:$rs1)>;
 } // Predicates = [HasStdExtZbb]
 

 def : Pat<(sext_inreg (fshr GPR:$rs3, (shl GPR:$rs1, (i64 32)),
                             (or GPR:$rs2, (i64 32))),
                       i32),
           (FSRW GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
 def : Pat<(sext_inreg (fshr GPR:$rs3, (shl GPR:$rs1, (i64 32)),
                             uimm6gt32:$shamt),
                       i32),
           (FSRIW GPR:$rs1, GPR:$rs3, (ImmSub32 uimm6gt32:$shamt))>;
+def : Pat<(sext_inreg (fshl GPR:$rs3, (shl GPR:$rs1, (i64 32)),
+                            uimm5:$shamt),
+                      i32),
+          (FSRIW GPR:$rs1, GPR:$rs3, (ImmROTL2RW uimm5:$shamt))>;
 } // Predicates = [HasStdExtZbt, IsRV64]
 
 let Predicates = [HasStdExtZbb, IsRV64] in {
 def : Pat<(add (ctlz (and GPR:$rs1, (i64 0xFFFFFFFF))), (i64 -32)),
           (CLZW GPR:$rs1)>;
 // We don't pattern-match CTZW here as it has the same pattern and result as
 // RV64 CTZ
 def : Pat<(ctpop (and GPR:$rs1, (i64 0xFFFFFFFF))), (PCNTW GPR:$rs1)>;

llvm/test/CodeGen/RISCV/rv32Zbb.ll

 ; RV32I-NEXT:    slli a1, a1, 1
 ; RV32I-NEXT:    or a1, a1, a2
 ; RV32I-NEXT:    slli a0, a0, 1
 ; RV32I-NEXT:    ori a0, a0, 1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: sloi_i64:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    addi a2, zero, 1
-; RV32IB-NEXT:    fsl a1, a1, a0, a2
+; RV32IB-NEXT:    fsri a1, a0, a1, 31
 ; RV32IB-NEXT:    sloi a0, a0, 1
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBB-LABEL: sloi_i64:
 ; RV32IBB:       # %bb.0:
 ; RV32IBB-NEXT:    srli a2, a0, 31
 ; RV32IBB-NEXT:    slli a1, a1, 1
 ; RV32IBB-NEXT:    or a1, a1, a2

 ; RV32I-NEXT:    or a0, a0, a2
 ; RV32I-NEXT:    srli a1, a1, 1
 ; RV32I-NEXT:    lui a2, 524288
 ; RV32I-NEXT:    or a1, a1, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: sroi_i64:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    addi a2, zero, 31
-; RV32IB-NEXT:    fsl a0, a1, a0, a2
+; RV32IB-NEXT:    fsri a0, a0, a1, 1
 ; RV32IB-NEXT:    sroi a1, a1, 1
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBB-LABEL: sroi_i64:
 ; RV32IBB:       # %bb.0:
 ; RV32IBB-NEXT:    slli a2, a1, 31
 ; RV32IBB-NEXT:    srli a0, a0, 1
 ; RV32IBB-NEXT:    or a0, a0, a2

llvm/test/CodeGen/RISCV/rv32Zbbp.ll

 ; RV32I-NEXT:    srli a1, a1, 1
 ; RV32I-NEXT:    slli a0, a0, 31
 ; RV32I-NEXT:    or a1, a0, a1
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: rori_i64:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    addi a3, zero, 31
-; RV32IB-NEXT:    fsl a2, a1, a0, a3
-; RV32IB-NEXT:    fsl a1, a0, a1, a3
+; RV32IB-NEXT:    fsri a2, a0, a1, 1
+; RV32IB-NEXT:    fsri a1, a1, a0, 1
 ; RV32IB-NEXT:    mv a0, a2
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBB-LABEL: rori_i64:
 ; RV32IBB:       # %bb.0:
 ; RV32IBB-NEXT:    slli a2, a1, 31
 ; RV32IBB-NEXT:    srli a3, a0, 1
 ; RV32IBB-NEXT:    or a2, a3, a2

 ; RV32I-NEXT:    srli a0, a0, 31
 ; RV32I-NEXT:    slli a1, a1, 1
 ; RV32I-NEXT:    or a1, a1, a0
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: rori_i64_fshr:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    addi a3, zero, 1
-; RV32IB-NEXT:    fsl a2, a0, a1, a3
-; RV32IB-NEXT:    fsl a1, a1, a0, a3
+; RV32IB-NEXT:    fsri a2, a1, a0, 31
+; RV32IB-NEXT:    fsri a1, a0, a1, 31
 ; RV32IB-NEXT:    mv a0, a2
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBB-LABEL: rori_i64_fshr:
 ; RV32IBB:       # %bb.0:
 ; RV32IBB-NEXT:    slli a2, a0, 1
 ; RV32IBB-NEXT:    srli a3, a1, 31
 ; RV32IBB-NEXT:    or a2, a3, a2

llvm/test/CodeGen/RISCV/rv32Zbt.ll

 ; RV32IB-NEXT:    andn a5, a1, a4
 ; RV32IB-NEXT:    addi a1, a5, -32
 ; RV32IB-NEXT:    srli t3, a3, 1
 ; RV32IB-NEXT:    bltz a1, .LBB5_7
 ; RV32IB-NEXT:  # %bb.4:
 ; RV32IB-NEXT:    mv t0, zero
 ; RV32IB-NEXT:    bgez a1, .LBB5_8
 ; RV32IB-NEXT:  .LBB5_5:
-; RV32IB-NEXT:    fsl a1, a3, a2, a6
+; RV32IB-NEXT:    fsri a1, a2, a3, 1
 ; RV32IB-NEXT:    srl a1, a1, t1
 ; RV32IB-NEXT:    sub a2, a6, a5
 ; RV32IB-NEXT:    slli a3, t3, 1
 ; RV32IB-NEXT:    sll a2, a3, a2
 ; RV32IB-NEXT:    or a2, a1, a2
 ; RV32IB-NEXT:    or a1, a7, t0
 ; RV32IB-NEXT:    bgez t2, .LBB5_9
 ; RV32IB-NEXT:  .LBB5_6:

 ; RV32IBT-NEXT:    andi t3, a1, 63
 ; RV32IBT-NEXT:    addi a5, t3, -32
 ; RV32IBT-NEXT:    srli t2, a3, 1
 ; RV32IBT-NEXT:    bltz a5, .LBB5_7
 ; RV32IBT-NEXT:  # %bb.4:
 ; RV32IBT-NEXT:    mv t0, zero
 ; RV32IBT-NEXT:    bgez a5, .LBB5_8
 ; RV32IBT-NEXT:  .LBB5_5:
-; RV32IBT-NEXT:    fsl a2, a3, a2, a6
+; RV32IBT-NEXT:    fsri a2, a2, a3, 1
 ; RV32IBT-NEXT:    srl a1, a2, a1
 ; RV32IBT-NEXT:    sub a2, a6, t3
 ; RV32IBT-NEXT:    slli a3, t2, 1
 ; RV32IBT-NEXT:    sll a2, a3, a2
 ; RV32IBT-NEXT:    or a2, a1, a2
 ; RV32IBT-NEXT:    or a1, a7, t0
 ; RV32IBT-NEXT:    bgez t1, .LBB5_9
 ; RV32IBT-NEXT:  .LBB5_6:

 ; RV32IB-NEXT:    andn a2, a2, a4
 ; RV32IB-NEXT:    addi a5, a2, -32
 ; RV32IB-NEXT:    slli t3, a0, 1
 ; RV32IB-NEXT:    bltz a5, .LBB7_7
 ; RV32IB-NEXT:  # %bb.4:
 ; RV32IB-NEXT:    mv t0, zero
 ; RV32IB-NEXT:    bgez a5, .LBB7_8
 ; RV32IB-NEXT:  .LBB7_5:
-; RV32IB-NEXT:    addi a5, zero, 1
-; RV32IB-NEXT:    fsl a1, a1, a0, a5
-; RV32IB-NEXT:    sll a1, a1, t1
 ; RV32IB-NEXT:    sub a2, a6, a2
 ; RV32IB-NEXT:    lui a5, 524288
 ; RV32IB-NEXT:    addi a5, a5, -1
-; RV32IB-NEXT:    and a0, a0, a5
-; RV32IB-NEXT:    srl a0, a0, a2
-; RV32IB-NEXT:    or a1, a1, a0
+; RV32IB-NEXT:    and a5, a0, a5
+; RV32IB-NEXT:    srl a2, a5, a2
+; RV32IB-NEXT:    fsri a0, a0, a1, 31
+; RV32IB-NEXT:    sll a0, a0, t1
+; RV32IB-NEXT:    or a1, a0, a2
 ; RV32IB-NEXT:    or a0, t0, a7
 ; RV32IB-NEXT:    bgez t2, .LBB7_9
 ; RV32IB-NEXT:  .LBB7_6:
 ; RV32IB-NEXT:    srl a2, a3, a4
 ; RV32IB-NEXT:    or a1, a1, a2
 ; RV32IB-NEXT:    ret
 ; RV32IB-NEXT:  .LBB7_7:
 ; RV32IB-NEXT:    sll t0, t3, t1
 ; RV32IB-NEXT:    bltz a5, .LBB7_5
 ; RV32IB-NEXT:  .LBB7_8:
 ; RV32IB-NEXT:    sll a1, t3, a5
 ; RV32IB-NEXT:    or a0, t0, a7
 ; RV32IB-NEXT:    bltz t2, .LBB7_6
 ; RV32IB-NEXT:  .LBB7_9:
 ; RV32IB-NEXT:    or a1, a1, zero
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBT-LABEL: fshr_i64:
 ; RV32IBT:       # %bb.0:
-; RV32IBT-NEXT:    not a7, a4
-; RV32IBT-NEXT:    andi t1, a7, 63
-; RV32IBT-NEXT:    addi t0, zero, 31
-; RV32IBT-NEXT:    addi t2, t1, -32
-; RV32IBT-NEXT:    slli a6, a0, 1
-; RV32IBT-NEXT:    bltz t2, .LBB7_2
+; RV32IBT-NEXT:    andi a5, a4, 63
+; RV32IBT-NEXT:    addi t1, a5, -32
+; RV32IBT-NEXT:    addi a6, zero, 31
+; RV32IBT-NEXT:    bltz t1, .LBB7_2
 ; RV32IBT-NEXT:  # %bb.1:
-; RV32IBT-NEXT:    sll t1, a6, t2
+; RV32IBT-NEXT:    srl a7, a3, t1
 ; RV32IBT-NEXT:    j .LBB7_3
 ; RV32IBT-NEXT:  .LBB7_2:
-; RV32IBT-NEXT:    addi a5, zero, 1
-; RV32IBT-NEXT:    fsl a1, a1, a0, a5
-; RV32IBT-NEXT:    sll a1, a1, a7
-; RV32IBT-NEXT:    lui a5, 524288
-; RV32IBT-NEXT:    addi a5, a5, -1
-; RV32IBT-NEXT:    and a0, a0, a5
-; RV32IBT-NEXT:    sub a5, t0, t1
-; RV32IBT-NEXT:    srl a0, a0, a5
-; RV32IBT-NEXT:    or t1, a1, a0
+; RV32IBT-NEXT:    srl a7, a2, a4
+; RV32IBT-NEXT:    sub a5, a6, a5
+; RV32IBT-NEXT:    slli a2, a3, 1
+; RV32IBT-NEXT:    sll a2, a2, a5
+; RV32IBT-NEXT:    or a7, a7, a2
 ; RV32IBT-NEXT:  .LBB7_3:
-; RV32IBT-NEXT:    andi a0, a4, 63
-; RV32IBT-NEXT:    addi a5, a0, -32
+; RV32IBT-NEXT:    not a2, a4
+; RV32IBT-NEXT:    andi t2, a2, 63
+; RV32IBT-NEXT:    addi a5, t2, -32
+; RV32IBT-NEXT:    slli t3, a0, 1
 ; RV32IBT-NEXT:    bltz a5, .LBB7_7
 ; RV32IBT-NEXT:  # %bb.4:
-; RV32IBT-NEXT:    mv a1, zero
+; RV32IBT-NEXT:    mv t0, zero
 ; RV32IBT-NEXT:    bgez a5, .LBB7_8
 ; RV32IBT-NEXT:  .LBB7_5:
-; RV32IBT-NEXT:    srl a2, a2, a4
-; RV32IBT-NEXT:    sub a0, t0, a0
-; RV32IBT-NEXT:    slli a3, a3, 1
-; RV32IBT-NEXT:    sll a0, a3, a0
-; RV32IBT-NEXT:    or a2, a2, a0
-; RV32IBT-NEXT:    or a1, t1, a1
-; RV32IBT-NEXT:    bgez t2, .LBB7_9
+; RV32IBT-NEXT:    lui a5, 524288
+; RV32IBT-NEXT:    addi a5, a5, -1
+; RV32IBT-NEXT:    and t3, a0, a5
+; RV32IBT-NEXT:    sub a5, a6, t2
+; RV32IBT-NEXT:    srl a5, t3, a5
+; RV32IBT-NEXT:    fsri a0, a0, a1, 31
+; RV32IBT-NEXT:    sll a0, a0, a2
+; RV32IBT-NEXT:    or a1, a0, a5
+; RV32IBT-NEXT:    or a0, t0, a7
+; RV32IBT-NEXT:    bgez t1, .LBB7_9
 ; RV32IBT-NEXT:  .LBB7_6:
-; RV32IBT-NEXT:    sll a0, a6, a7
-; RV32IBT-NEXT:    or a0, a0, a2
+; RV32IBT-NEXT:    srl a2, a3, a4
+; RV32IBT-NEXT:    or a1, a1, a2
 ; RV32IBT-NEXT:    ret
 ; RV32IBT-NEXT:  .LBB7_7:
-; RV32IBT-NEXT:    srl a1, a3, a4
+; RV32IBT-NEXT:    sll t0, t3, a2
 ; RV32IBT-NEXT:    bltz a5, .LBB7_5
 ; RV32IBT-NEXT:  .LBB7_8:
-; RV32IBT-NEXT:    srl a2, a3, a5
-; RV32IBT-NEXT:    or a1, t1, a1
-; RV32IBT-NEXT:    bltz t2, .LBB7_6
+; RV32IBT-NEXT:    sll a1, t3, a5
+; RV32IBT-NEXT:    or a0, t0, a7
+; RV32IBT-NEXT:    bltz t1, .LBB7_6
 ; RV32IBT-NEXT:  .LBB7_9:
-; RV32IBT-NEXT:    or a0, zero, a2
+; RV32IBT-NEXT:    or a1, a1, zero
 ; RV32IBT-NEXT:    ret
   %1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %b, i64 %c)
   ret i64 %1
 }
 
 define i32 @fshri_i32(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: fshri_i32:
 ; RV32I:       # %bb.0:

 ; RV32I-NEXT:    srli a1, a3, 5
 ; RV32I-NEXT:    slli a0, a0, 27
 ; RV32I-NEXT:    or a1, a0, a1
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: fshri_i64:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    addi a1, zero, 27
-; RV32IB-NEXT:    fsl a2, a3, a2, a1
-; RV32IB-NEXT:    fsl a1, a0, a3, a1
+; RV32IB-NEXT:    fsri a2, a2, a3, 5
+; RV32IB-NEXT:    fsri a1, a3, a0, 5
 ; RV32IB-NEXT:    mv a0, a2
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBT-LABEL: fshri_i64:
 ; RV32IBT:       # %bb.0:
-; RV32IBT-NEXT:    addi a1, zero, 27
-; RV32IBT-NEXT:    fsl a2, a3, a2, a1
-; RV32IBT-NEXT:    fsl a1, a0, a3, a1
+; RV32IBT-NEXT:    fsri a2, a2, a3, 5
+; RV32IBT-NEXT:    fsri a1, a3, a0, 5
 ; RV32IBT-NEXT:    mv a0, a2
 ; RV32IBT-NEXT:    ret
   %1 = tail call i64 @llvm.fshr.i64(i64 %a, i64 %b, i64 5)
   ret i64 %1
 }
 
 define i32 @fshli_i32(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: fshli_i32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srli a1, a1, 27
 ; RV32I-NEXT:    slli a0, a0, 5
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: fshli_i32:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    addi a2, zero, 5
-; RV32IB-NEXT:    fsl a0, a0, a1, a2
+; RV32IB-NEXT:    fsri a0, a1, a0, 27
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBT-LABEL: fshli_i32:
 ; RV32IBT:       # %bb.0:
-; RV32IBT-NEXT:    addi a2, zero, 5
-; RV32IBT-NEXT:    fsl a0, a0, a1, a2
+; RV32IBT-NEXT:    fsri a0, a1, a0, 27
 ; RV32IBT-NEXT:    ret
   %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 5)
   ret i32 %1
 }
 
 define i64 @fshli_i64(i64 %a, i64 %b) nounwind {
 ; RV32I-LABEL: fshli_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srli a2, a3, 27
 ; RV32I-NEXT:    slli a3, a0, 5
 ; RV32I-NEXT:    or a2, a3, a2
 ; RV32I-NEXT:    srli a0, a0, 27
 ; RV32I-NEXT:    slli a1, a1, 5
 ; RV32I-NEXT:    or a1, a1, a0
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV32IB-LABEL: fshli_i64:
 ; RV32IB:       # %bb.0:
-; RV32IB-NEXT:    addi a4, zero, 5
-; RV32IB-NEXT:    fsl a2, a0, a3, a4
-; RV32IB-NEXT:    fsl a1, a1, a0, a4
+; RV32IB-NEXT:    fsri a2, a3, a0, 27
+; RV32IB-NEXT:    fsri a1, a0, a1, 27
 ; RV32IB-NEXT:    mv a0, a2
 ; RV32IB-NEXT:    ret
 ;
 ; RV32IBT-LABEL: fshli_i64:
 ; RV32IBT:       # %bb.0:
-; RV32IBT-NEXT:    addi a4, zero, 5
-; RV32IBT-NEXT:    fsl a2, a0, a3, a4
-; RV32IBT-NEXT:    fsl a1, a1, a0, a4
+; RV32IBT-NEXT:    fsri a2, a3, a0, 27
+; RV32IBT-NEXT:    fsri a1, a0, a1, 27
 ; RV32IBT-NEXT:    mv a0, a2
 ; RV32IBT-NEXT:    ret
   %1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %b, i64 5)
   ret i64 %1
 }

llvm/test/CodeGen/RISCV/rv64Zbt.ll

 ; RV64I-NEXT:    srliw a1, a1, 27
 ; RV64I-NEXT:    slli a0, a0, 5
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: fshli_i32:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    slli a1, a1, 32
-; RV64IB-NEXT:    addi a2, zero, 5
-; RV64IB-NEXT:    fsl a0, a0, a1, a2
-; RV64IB-NEXT:    sext.w a0, a0
+; RV64IB-NEXT:    fsriw a0, a1, a0, 27
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBT-LABEL: fshli_i32:
 ; RV64IBT:       # %bb.0:
-; RV64IBT-NEXT:    slli a1, a1, 32
-; RV64IBT-NEXT:    addi a2, zero, 5
-; RV64IBT-NEXT:    fsl a0, a0, a1, a2
-; RV64IBT-NEXT:    sext.w a0, a0
+; RV64IBT-NEXT:    fsriw a0, a1, a0, 27
 ; RV64IBT-NEXT:    ret
   %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 5)
   ret i32 %1
 }
 
 define i64 @fshli_i64(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: fshli_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srli a1, a1, 59
 ; RV64I-NEXT:    slli a0, a0, 5
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: fshli_i64:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    addi a2, zero, 5
-; RV64IB-NEXT:    fsl a0, a0, a1, a2
+; RV64IB-NEXT:    fsri a0, a1, a0, 59
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBT-LABEL: fshli_i64:
 ; RV64IBT:       # %bb.0:
-; RV64IBT-NEXT:    addi a2, zero, 5
-; RV64IBT-NEXT:    fsl a0, a0, a1, a2
+; RV64IBT-NEXT:    fsri a0, a1, a0, 59
 ; RV64IBT-NEXT:    ret
   %1 = tail call i64 @llvm.fshl.i64(i64 %a, i64 %b, i64 5)
   ret i64 %1
 }