[PowerPC] Add folding patterns for rlwinm + andi_rec.

[Esme]

Summary

This patch depends on D89855. We have patterns to fold RLWINM + RLWINM.
Pairs of RLWINM and ANDI_rec can also be folded in some cases.
Following is a scenario in C code:

int tmp = vec_test_swdiv(x,y);
if (((__builtin_rotateleft32(tmp, 62)) & (1)) != 0){
  ...
}

clang -c t.c -O3 generates the sequence:

xvtdivdp cr0,vs34,vs35
mfocrf  r3,128
rlwinm  r3,r3,4,28,31 --->generated in POST-RA
andi.   r3,r3,4

This patch will fold it to:

xvtdivdp cr0,vs34,vs35
mfocrf   r3,128
rlwinm.  r3,r3,4,29,29

[Esme]

Added the situation of Mask == 0.

[Esme]

FIXME: A deg was found in llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll

[shchenz]

This is more clear than the previous version. Some implementation comments.

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

4072

Nice catch! Then should we reuse legacy logic? If ANDI_rec mask is not runofones, we can not fold RLWINM + ANDI_rec to a single RLWINM? If ANDI_rec mask is runofones, can we treat it as special rlwinm_rec with sh = 0, and MB, ME can be got from runofones check?

[Esme]

Reused legacy logic.

[nemanjai]

llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll

78 ↗

(On Diff #308533)

Well this is less than ideal. Perhaps we should only do this if the GPR that the andi. defines is dead?

[nemanjai]

llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll

78 ↗

(On Diff #308533)

Sorry, this was meant to say that we should check that the GPR that andi. uses is killed.

[Esme]

Exclude the cases if SrcMI can't be erased and the Reg used by MI is not kill.

[Esme]

llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll

78 ↗

(On Diff #308533)

Sorry, this was meant to say that we should check that the GPR that andi. uses is killed.

@nemanjai Sorry, although I have updated the revision, I am actually a bit confused about this fix. As the comment added in last version (Diff 308919), I assumed the deg was caused by RA.

; FIXME: A redundant COPY was generated during RA.
; i.e.   rlwinm r29, r30, 0, 24, 22
;        mr r30, r29

Checking the GPR that andi. uses is killed can skip folding the case and avoid the deg, however is it the cause of the deg? I would be thankful if you have more comments about this issue.

[Esme]

Ping.

[Esme]

Rebase on D89855.

[nemanjai]

llvm/test/CodeGen/PowerPC/p10-spill-crlt.ll

78 ↗

(On Diff #308533)

Well, prior to this change, you had:

0x0: rlwinm r30, r30, 0, 24, 22
0x4: andi. r3, r30, 2
...
# some subsequent use of r30

So when you change it to an rlwinm. that produces what andi. produces, you no longer have the value that was previously produced by the existing rlwinm (on 0x0 above). Therefore, that instruction has to be kept so you get rlwinm r29, r30, 0, 24, 22.
But then you might wonder why doesn't it just end up being rlwinm r30, r30, 0, 24, 22? I suspect that is because the input register is still not marked as killed.

[Esme]

rebase

[Esme]

Add MIR test cases.

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

bool PPCInstrInfo::convertToImmediateForm(MachineInstr &MI,
   return false;
 }
 
 // Return true if SrcMI and MI are both 32-bit or both 64-bit instructions.
 static bool sameWidthMIs(MachineInstr *SrcMI, MachineInstr *MI, bool &Is64Bit) {
   unsigned Opc = MI->getOpcode();
   unsigned SrcOpc = SrcMI->getOpcode();
   if ((SrcOpc == PPC::RLWINM8 || SrcOpc == PPC::RLWINM8_rec) &&
-      (Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8_rec)) {
+      (Opc == PPC::RLWINM8 || Opc == PPC::RLWINM8_rec ||
+       Opc == PPC::ANDI8_rec)) {
     Is64Bit = true;
     return true;
   }
   if ((SrcOpc == PPC::RLWINM || SrcOpc == PPC::RLWINM_rec) &&
-      (Opc == PPC::RLWINM || Opc == PPC::RLWINM_rec))
+      (Opc == PPC::RLWINM || Opc == PPC::RLWINM_rec || Opc == PPC::ANDI_rec))
     return true;
   return false;
 }
 
-// This function tries to combine two RLWINMs. We not only perform such
-// optimization in SSA, but also after RA, since some RLWINM is generated after
-// RA.
+static void getRLWINMOps(MachineInstr &MI, uint32_t &SH, uint32_t &MB,
+                         uint32_t &ME) {
+  assert((MI.getOperand(2).isImm() && MI.getOperand(3).isImm() &&
+          MI.getOperand(4).isImm()) &&
+         "Invalid PPC::RLWINM Instruction!");
+  SH = MI.getOperand(2).getImm();
+  MB = MI.getOperand(3).getImm();
+  ME = MI.getOperand(4).getImm();
+  assert((ME < 32 && MB < 32) && "Invalid PPC::RLWINM Instruction!");
+}
+
+// This function tries to optimize rotate and mask instructions in both SSA and
+// post-RA.
 bool PPCInstrInfo::simplifyRotateAndMaskInstr(MachineInstr &MI,
                                               MachineInstr *&ToErase) const {
   unsigned UseOpc = MI.getOpcode();
   if (UseOpc != PPC::RLWINM && UseOpc != PPC::RLWINM_rec &&
-      UseOpc != PPC::RLWINM8 && UseOpc != PPC::RLWINM8_rec)
+      UseOpc != PPC::RLWINM8 && UseOpc != PPC::RLWINM8_rec &&
+      UseOpc != PPC::ANDI_rec && UseOpc != PPC::ANDI8_rec)
     return false;
 
   // Find the source MI.
   MachineRegisterInfo *MRI = &MI.getParent()->getParent()->getRegInfo();
   Register FoldingReg = MI.getOperand(1).getReg();
   MachineInstr *SrcMI = nullptr;
   bool CanErase = false;
   bool OtherIntermediateUse = true;
bool PPCInstrInfo::simplifyRotateAndMaskInstr(MachineInstr &MI,
   // Check if the registers(def and use) meet the requirements for folding.
   MachineOperand ForwardRegOp = SrcMI->getOperand(1);
   Register ForwardReg = ForwardRegOp.getReg();
   bool IsFwdFeederRegKilled = false;
   bool SeenIntermediateUse = false;
   bool IsMIUseRegKilled = MI.getOperand(1).isKill();
   if (MRI->isSSA()) {
     CanErase = !SrcMI->hasImplicitDef() && MRI->hasOneNonDBGUse(FoldingReg);
+    if (!CanErase && !MI.getOperand(1).isKill())
+      return false;
   } else {
     bool KillFwdDefMI = !OtherIntermediateUse && IsMIUseRegKilled;
     CanErase = KillFwdDefMI && !SrcMI->hasImplicitDef();
     // In post-RA, if SrcMI also defines the register to be forwarded, we can
     // only do the folding if SrcMI is going to be erased.
     if (!CanErase && SrcMI->definesRegister(ForwardReg))
       return false;
     // Check if the SrcReg can be forwarded to MI.
     if (!isRegElgibleForForwarding(ForwardRegOp, *SrcMI, MI, KillFwdDefMI,
                                    IsFwdFeederRegKilled, SeenIntermediateUse))
       return false;
   }
 
-  assert((MI.getOperand(2).isImm() && MI.getOperand(3).isImm() &&
-          MI.getOperand(4).isImm() && SrcMI->getOperand(2).isImm() &&
-          SrcMI->getOperand(3).isImm() && SrcMI->getOperand(4).isImm()) &&
-         "Invalid PPC::RLWINM Instruction!");
-  uint64_t SHSrc = SrcMI->getOperand(2).getImm();
-  uint64_t SHMI = MI.getOperand(2).getImm();
-  uint64_t MBSrc = SrcMI->getOperand(3).getImm();
-  uint64_t MBMI = MI.getOperand(3).getImm();
-  uint64_t MESrc = SrcMI->getOperand(4).getImm();
-  uint64_t MEMI = MI.getOperand(4).getImm();
-  assert((MEMI < 32 && MESrc < 32 && MBMI < 32 && MBSrc < 32) &&
-         "Invalid PPC::RLWINM Instruction!");
+  uint32_t SHSrc, MBSrc, MESrc;
+  getRLWINMOps(*SrcMI, SHSrc, MBSrc, MESrc);
+  // Note that in APInt, the least significant bit is at index 0, while in
+  // PowerPC ISA, the least significant bit is at index 63.
+  APInt MaskSrc = APInt::getBitsSetWithWrap(32, 32 - MESrc - 1, 32 - MBSrc);
+  // Mark the special cases of all bits in a 64-bit register or the low 32 bits
+  // in a 64-bit register.
+  bool SrcMaskFull = (MBSrc - MESrc == 1) || (MBSrc == 0 && MESrc == 31);
+  bool Simplified = false;
+  uint32_t SHMI, MBMI, MEMI, NewMB, NewME;
+  APInt FinalMask;
+
+  // Pattern 1: RLWINM_ + RLWINM_
+  if (MI.getOpcode() == PPC::RLWINM || MI.getOpcode() == PPC::RLWINM_rec ||
+      MI.getOpcode() == PPC::RLWINM8 || MI.getOpcode() == PPC::RLWINM8_rec) {
+    getRLWINMOps(MI, SHMI, MBMI, MEMI);
+    // For other MBMI > MEMI cases, just return.
+    if ((MBMI > MEMI) && !SrcMaskFull)
+      return false;
+    // Handle MBMI <= MEMI cases.
+    // In MI, we only need low 32 bits of SrcMI, just consider about low 32
+    // bit of SrcMI mask.
+    APInt MaskMI = APInt::getBitsSetWithWrap(32, 32 - MEMI - 1, 32 - MBMI);
+    APInt RotatedSrcMask = MaskSrc.rotl(SHMI);
+    FinalMask = RotatedSrcMask & MaskMI;
+  }
+  // Pattern 2: RLWINM_ + ANDI_
+  else {
+    assert(MI.getOperand(2).isImm() && "Invalid PPC::ANDI_rec Instruction!");
+    uint32_t AndImm = MI.getOperand(2).getImm();
+    assert(isUIntN(16, AndImm) && "Invalid PPC::ANDI_rec Instruction!");
+    // We can treat ANDI_rec as RLWINM_rec with the SH = 0 if the AndImm
+    // contains a non-empty sequence of ones with the remainder zeros
+    // (isRunOfOnes).
+    SHMI = 0;
+    FinalMask = MaskSrc & AndImm;
+    // If AndImm isn't isRunOfOnes, we can only do the folding when FinalMask
+    // equals to zero.
+    if (!isShiftedMask_32(AndImm) && FinalMask != 0)
+      return false;
+  }
+
   // If MBMI is bigger than MEMI, we always can not get run of ones.
   // RotatedSrcMask non-wrap:
   //                 0........31|32........63
   // RotatedSrcMask:   B---E        B---E
   // MaskMI:         -----------|--E  B------
   // Result:           -----          ---      (Bad candidate)
   //
   // RotatedSrcMask wrap:
   //                 0........31|32........63
   // RotatedSrcMask: --E   B----|--E    B----
   // MaskMI:         -----------|--E  B------
   // Result:         ---   -----|---    -----  (Bad candidate)
   //
   // One special case is RotatedSrcMask is a full set mask.
   // RotatedSrcMask full:
   //                 0........31|32........63
   // RotatedSrcMask: ------EB---|-------EB---
   // MaskMI:         -----------|--E  B------
   // Result:         -----------|---  -------  (Good candidate)
 
-  // Mark the special cases of all bits in a 64-bit register or the low 32 bits
-  // in a 64-bit register.
-  bool SrcMaskFull = (MBSrc - MESrc == 1) || (MBSrc == 0 && MESrc == 31);
-
-  // For other MBMI > MEMI cases, just return.
-  if ((MBMI > MEMI) && !SrcMaskFull)
-    return false;
-
-  // Handle MBMI <= MEMI cases.
-  APInt MaskMI = APInt::getBitsSetWithWrap(32, 32 - MEMI - 1, 32 - MBMI);
-  // In MI, we only need low 32 bits of SrcMI, just consider about low 32
-  // bit of SrcMI mask. Note that in APInt, the least significant bit is at
-  // index 0, while in PowerPC ISA, the least significant bit is at index 63.
-  APInt MaskSrc = APInt::getBitsSetWithWrap(32, 32 - MESrc - 1, 32 - MBSrc);
-
-  APInt RotatedSrcMask = MaskSrc.rotl(SHMI);
-  APInt FinalMask = RotatedSrcMask & MaskMI;
-  uint32_t NewMB, NewME;
-  bool Simplified = false;
-
   // If final mask is 0, replace MI with LI/LI8 0 or ANDI_rec/ANDI8_rec 0.
   if (FinalMask.isZero()) {
     Simplified = true;
     LLVM_DEBUG(dbgs() << "Replace Instr: ");
     LLVM_DEBUG(MI.dump());
 
     LoadImmediateInfo LII;
     LII.Imm = 0;
     LII.Is64Bit = Is64Bit;
-    LII.SetCR = (UseOpc == PPC::RLWINM_rec || UseOpc == PPC::RLWINM8_rec);
+    LII.SetCR = (UseOpc == PPC::RLWINM_rec || UseOpc == PPC::RLWINM8_rec ||
+                 UseOpc == PPC::ANDI_rec || UseOpc == PPC::ANDI8_rec);
     replaceInstrWithLI(MI, LII);
     if (LII.SetCR) {
       MI.getOperand(1).setReg(ForwardReg);
       // FIXME: If the register used by MI is `killed` before change, we need
       // update the kill flag on the previous use of that register. Here we only
       // considered the kill flag of the register used by SrcMI.
       if (ForwardRegOp.isKill()) {
         MI.getOperand(1).setIsKill(true);
         SrcMI->getOperand(1).setIsKill(false);
       } else
         // About to replace MI.getOperand(1), clear its kill flag.
         MI.getOperand(1).setIsKill(false);
     }
 
     LLVM_DEBUG(dbgs() << "With: ");
     LLVM_DEBUG(MI.dump());
   } else if ((isRunOfOnes((unsigned)(FinalMask.getZExtValue()), NewMB, NewME) &&
               NewMB <= NewME) ||
              SrcMaskFull) {
     // Here we only handle MBMI <= MEMI case, so NewMB must be no bigger
     // than NewME. Otherwise we get a 64 bit value after folding, but MI
     // return a 32 bit value.
     Simplified = true;
     LLVM_DEBUG(dbgs() << "Converting Instr: ");
     LLVM_DEBUG(MI.dump());
 
     MI.getOperand(2).setImm((SHSrc + SHMI) % 32);
+    if (UseOpc == PPC::ANDI_rec || UseOpc == PPC::ANDI8_rec) {
+      MI.setDesc(get(Is64Bit ? PPC::RLWINM8_rec : PPC::RLWINM_rec));
+      MI.addOperand(MachineOperand::CreateImm(NewMB));
+      MI.addOperand(MachineOperand::CreateImm(NewME));
+    }
     // If SrcMI mask is full, do not update MBMI and MEMI.
-    if (!SrcMaskFull) {
+    else if (!SrcMaskFull) {
       MI.getOperand(3).setImm(NewMB);
       MI.getOperand(4).setImm(NewME);
     }
     MI.getOperand(1).setReg(ForwardReg);
     if (ForwardRegOp.isKill()) {
       MI.getOperand(1).setIsKill(true);
       SrcMI->getOperand(1).setIsKill(false);
     } else

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

for (MachineInstr &MI : MBB) {
         NumOptADDLIs++;
         break;
       }
       case PPC::RLDICR: {
         Simplified |= emitRLDICWhenLoweringJumpTables(MI) ||
                       combineSEXTAndSHL(MI, ToErase);
         break;
       }
+      case PPC::ANDI_rec:
+      case PPC::ANDI8_rec:
       case PPC::RLWINM:
       case PPC::RLWINM_rec:
       case PPC::RLWINM8:
       case PPC::RLWINM8_rec: {
         Simplified = TII->simplifyRotateAndMaskInstr(MI, ToErase);
         if (Simplified)
           ++NumRotatesCollapsed;
         break;

llvm/test/CodeGen/PowerPC/fold-rlwinm-1.ll

 
 define void @foo_multiple_use(i32 signext %var1) {
 ; CHECK-LABEL: foo_multiple_use:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xori r3, r3, 1
 ; CHECK-NEXT:    addis r4, r2, res2@toc@ha
 ; CHECK-NEXT:    addis r6, r2, res@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
-; CHECK-NEXT:    srwi r5, r3, 5
-; CHECK-NEXT:    rlwinm r3, r3, 14, 0, 12
-; CHECK-NEXT:    stw r5, res2@toc@l(r4)
-; CHECK-NEXT:    stw r3, res@toc@l(r6)
+; CHECK-NEXT:    srwi r3, r3, 5
+; CHECK-NEXT:    slwi r5, r3, 19
+; CHECK-NEXT:    stw r3, res2@toc@l(r4)
+; CHECK-NEXT:    stw r5, res@toc@l(r6)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %var1, 1
   %conv = zext i1 %cmp to i32
   store i32 %conv, ptr @res2, align 4
   %shl = shl nuw nsw i32 %conv, 19
   store i32 %shl, ptr @res, align 4
   ret void
 }

llvm/test/CodeGen/PowerPC/fold-rlwinm-after-ra.mir

bb.0.entry:
     ; CHECK-NEXT: $x2 = LD -8, $x1 :: (load (s64) from %stack.0)
     ; CHECK-NEXT: renamable $r3 = RLWINM killed renamable $r3, 19, 0, 12, implicit-def $x3
     ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x2, implicit killed $x3
     $r3 = RLWINM killed $r2, 4, 28, 31
     $r2 = LI 0, implicit-def $x2
     dead renamable $r3 = RLWINM killed renamable $r3, 19, 0, 12, implicit-def $x3
     BLR8 implicit $lr8, implicit $rm, implicit killed $x2, implicit killed $x3
 ...
+---
+name: testFoldRLWINMAndANDI
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    liveins: $r3
+    ; CHECK-LABEL: name: testFoldRLWINMAndANDI
+    ; CHECK: liveins: $r3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: dead renamable $r3 = RLWINM_rec killed renamable $r3, 8, 29, 29, implicit-def $cr0
+    ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit killed $cr0
+    $r3 = RLWINM killed $r3, 8, 28, 31
+    dead renamable $r3 = ANDI_rec killed renamable $r3, 4, implicit-def $cr0
+    BLR8 implicit $lr8, implicit $rm, implicit killed $cr0
+...
+---
+name: testFoldRLWINMAndANDIToZero
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    liveins: $r3
+    ; CHECK-LABEL: name: testFoldRLWINMAndANDIToZero
+    ; CHECK: liveins: $r3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: dead renamable $r3 = ANDI_rec killed renamable $r3, 0, implicit-def $cr0
+    ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit killed $cr0
+    $r3 = RLWINM killed $r3, 4, 28, 31
+    dead renamable $r3 = ANDI_rec killed renamable $r3, 16, implicit-def $cr0
+    BLR8 implicit $lr8, implicit $rm, implicit killed $cr0
+...
+---
+name: testRLWINMANDIInvalidMask
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    liveins: $r3
+    ; CHECK-LABEL: name: testRLWINMANDIInvalidMask
+    ; CHECK: liveins: $r3
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: $r3 = RLWINM killed $r3, 4, 20, 31
+    ; CHECK-NEXT: dead renamable $r3 = ANDI_rec killed renamable $r3, 9, implicit-def $cr0
+    ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit killed $cr0
+    $r3 = RLWINM killed $r3, 4, 20, 31
+    dead renamable $r3 = ANDI_rec killed renamable $r3, 9, implicit-def $cr0
+    BLR8 implicit $lr8, implicit $rm, implicit killed $cr0
+...
+---
+name: testCanNotFoldRLWINMAndANDI
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    liveins: $r2, $r3
+    ; CHECK-LABEL: name: testCanNotFoldRLWINMAndANDI
+    ; CHECK: liveins: $r2, $r3, $x2
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: STD $x2, -8, $x1 :: (store (s64) into %stack.0)
+    ; CHECK-NEXT: $r3 = RLWINM killed $r2, 4, 28, 31
+    ; CHECK-NEXT: $r2 = LI 0, implicit-def $x2
+    ; CHECK-NEXT: $x2 = LD -8, $x1 :: (load (s64) from %stack.0)
+    ; CHECK-NEXT: dead renamable $r3 = ANDI_rec killed renamable $r3, 4, implicit-def $cr0
+    ; CHECK-NEXT: BLR8 implicit $lr8, implicit $rm, implicit killed $cr0, implicit $x2
+    $r3 = RLWINM killed $r2, 4, 28, 31
+    $r2 = LI 0, implicit-def $x2
+    dead renamable $r3 = ANDI_rec killed renamable $r3, 4, implicit-def $cr0
+    BLR8 implicit $lr8, implicit $rm, implicit killed $cr0, implicit killed $x2
+...

llvm/test/CodeGen/PowerPC/fold-rlwinm.mir

 #CHECK: name: testFoldRLWINMMultipleUses
 tracksRegLiveness: true
 body: |
   bb.0.entry:
     liveins: $x3
     %0:g8rc = COPY $x3
     %1:gprc = COPY %0.sub_32:g8rc
     %2:gprc = RLWINM killed %1:gprc, 27, 5, 31
-    ; CHECK: %2:gprc = RLWINM %1, 27, 5, 31
+    ; CHECK: %2:gprc = RLWINM killed %1, 27, 5, 31
     %3:gprc = RLWINM %2:gprc, 19, 0, 12
-    ; CHECK: %3:gprc = RLWINM killed %1, 14, 0, 12
+    ; CHECK: %3:gprc = RLWINM %2, 19, 0, 12
     STW %3:gprc, %2:gprc, 100 
     ; CHECK: STW %3, %2, 100
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
 name: testFoldRLWINMToZero
 #CHECK: name: testFoldRLWINMToZero
 tracksRegLiveness: true

 tracksRegLiveness: true
 body: |
   bb.0.entry:
     liveins: $x3
     %0:g8rc = COPY $x3
     %1:gprc = COPY %0.sub_32:g8rc
     %2:gprc = RLWINM_rec %1:gprc, 27, 5, 10, implicit-def $cr0
     ; CHECK: %2:gprc = RLWINM_rec %1, 27, 5, 10, implicit-def $cr0
-    %3:gprc = RLWINM_rec %2:gprc, 8, 5, 10, implicit-def $cr0
+    %3:gprc = RLWINM_rec killed %2:gprc, 8, 5, 10, implicit-def $cr0
     ; CHECK: %3:gprc = ANDI_rec %1, 0, implicit-def $cr0
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
 name: testFoldRLWINMInvalidMask
 #CHECK: name: testFoldRLWINMInvalidMask
 tracksRegLiveness: true
 body: |

 tracksRegLiveness: true
 body: |
   bb.0.entry:
     liveins: $x3
     ; CHECK-LABEL: name: testFoldRLWINMAndANDI
     ; CHECK: liveins: $x3
     ; CHECK: [[COPY:%[0-9]+]]:g8rc = COPY $x3
     ; CHECK: [[COPY1:%[0-9]+]]:gprc = COPY [[COPY]].sub_32
-    ; CHECK: [[RLWINM:%[0-9]+]]:gprc = RLWINM [[COPY1]], 4, 28, 31
-    ; CHECK: [[ANDI_rec:%[0-9]+]]:gprc = ANDI_rec [[RLWINM]], 4, implicit-def $cr0
+    ; CHECK: [[RLWINM_rec:%[0-9]+]]:gprc = RLWINM_rec [[COPY1]], 4, 29, 29, implicit-def $cr0
     ; CHECK: BLR8 implicit $lr8, implicit $rm
     %0:g8rc = COPY $x3
     %1:gprc = COPY %0.sub_32:g8rc
     %2:gprc = RLWINM %1:gprc, 4, 28, 31
     %3:gprc = ANDI_rec %2:gprc, 4, implicit-def $cr0
     BLR8 implicit $lr8, implicit $rm
 ...

llvm/test/CodeGen/PowerPC/is_fpclass.ll

 }
 
 define i1 @isqnan_float(float %x) nounwind {
 ; CHECK-LABEL: isqnan_float:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    xscvdpspn 0, 1
 ; CHECK-NEXT:    xststdcsp 1, 1, 64
 ; CHECK-NEXT:    mffprwz 3, 0
-; CHECK-NEXT:    srwi 3, 3, 22
-; CHECK-NEXT:    andi. 3, 3, 1
+; CHECK-NEXT:    rlwinm. 3, 3, 10, 31, 31
 ; CHECK-NEXT:    li 3, 1
 ; CHECK-NEXT:    crnand 20, 6, 1
 ; CHECK-NEXT:    isel 3, 0, 3, 20
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 2)
   ret i1 %1
 }
 

 }
 
 define i1 @isqnan_fp128(fp128 %x) nounwind {
 ; CHECK-LABEL: isqnan_fp128:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li 3, 12
 ; CHECK-NEXT:    xststdcqp 1, 2, 64
 ; CHECK-NEXT:    vextuwrx 3, 3, 2
-; CHECK-NEXT:    srwi 3, 3, 15
-; CHECK-NEXT:    andi. 3, 3, 1
+; CHECK-NEXT:    rlwinm. 3, 3, 17, 31, 31
 ; CHECK-NEXT:    li 3, 1
 ; CHECK-NEXT:    crnand 20, 6, 1
 ; CHECK-NEXT:    isel 3, 0, 3, 20
 ; CHECK-NEXT:    blr
   %1 = call i1 @llvm.is.fpclass.f128(fp128 %x, i32 2)
   ret i1 %1
 }
 

llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll

 
 ; Without fine-grained control over clobbering individual CR bits,
 ; it is difficult to produce a concise test case that will ensure a specific
 ; bit of any CR field is spilled. We need to test the spilling of a CR bit
 ; other than the LT bit. Hence this test case is rather complex.
 
 define dso_local fastcc void @P10_Spill_CR_GT() unnamed_addr {
 ; CHECK-LABEL: P10_Spill_CR_GT:
-; CHECK:         .localentry P10_Spill_CR_GT, 1
-; CHECK-NEXT:  # %bb.0: # %bb
+; CHECK:       # %bb.0: # %bb
 ; CHECK-NEXT:    mfcr r12
 ; CHECK-NEXT:    mflr r0
 ; CHECK-NEXT:    std r0, 16(r1)
 ; CHECK-NEXT:    stw r12, 8(r1)
 ; CHECK-NEXT:    stdu r1, -64(r1)
 ; CHECK-NEXT:    .cfi_def_cfa_offset 64
 ; CHECK-NEXT:    .cfi_offset lr, 16
 ; CHECK-NEXT:    .cfi_offset r29, -24
 ; CHECK-NEXT:    .cfi_offset r30, -16
 ; CHECK-NEXT:    .cfi_offset cr2, 8
 ; CHECK-NEXT:    .cfi_offset cr3, 8
 ; CHECK-NEXT:    .cfi_offset cr4, 8
 ; CHECK-NEXT:    lwz r3, 0(r3)
 ; CHECK-NEXT:    std r29, 40(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r30, 48(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    paddi r29, 0, .LJTI0_0@PCREL, 1
-; CHECK-NEXT:    srwi r4, r3, 4
-; CHECK-NEXT:    srwi r3, r3, 5
-; CHECK-NEXT:    andi. r4, r4, 1
+; CHECK-NEXT:    rlwinm. r4, r3, 28, 31, 31
 ; CHECK-NEXT:    li r4, 0
 ; CHECK-NEXT:    crmove 4*cr2+gt, gt
-; CHECK-NEXT:    andi. r3, r3, 1
+; CHECK-NEXT:    rlwinm. r3, r3, 27, 31, 31
 ; CHECK-NEXT:    crmove 4*cr2+lt, gt
 ; CHECK-NEXT:    cmplwi cr3, r3, 336
 ; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    sldi r30, r3, 2
 ; CHECK-NEXT:    b .LBB0_2
 ; CHECK-NEXT:  .LBB0_1: # %bb43
 ; CHECK-NEXT:    #
 ; CHECK-NEXT:    bl call_1@notoc

 ; CHECK-BE-NEXT:    .cfi_offset r29, -24
 ; CHECK-BE-NEXT:    .cfi_offset r30, -16
 ; CHECK-BE-NEXT:    .cfi_offset cr2, 8
 ; CHECK-BE-NEXT:    .cfi_offset cr2, 8
 ; CHECK-BE-NEXT:    .cfi_offset cr2, 8
 ; CHECK-BE-NEXT:    lwz r3, 0(r3)
 ; CHECK-BE-NEXT:    std r29, 120(r1) # 8-byte Folded Spill
 ; CHECK-BE-NEXT:    std r30, 128(r1) # 8-byte Folded Spill
-; CHECK-BE-NEXT:    srwi r4, r3, 4
-; CHECK-BE-NEXT:    srwi r3, r3, 5
-; CHECK-BE-NEXT:    andi. r4, r4, 1
+; CHECK-BE-NEXT:    rlwinm. r4, r3, 28, 31, 31
 ; CHECK-BE-NEXT:    li r4, 0
 ; CHECK-BE-NEXT:    crmove 4*cr2+gt, gt
-; CHECK-BE-NEXT:    andi. r3, r3, 1
+; CHECK-BE-NEXT:    rlwinm. r3, r3, 27, 31, 31
 ; CHECK-BE-NEXT:    crmove 4*cr2+lt, gt
 ; CHECK-BE-NEXT:    cmplwi cr3, r3, 336
 ; CHECK-BE-NEXT:    li r3, 0
 ; CHECK-BE-NEXT:    sldi r30, r3, 2
 ; CHECK-BE-NEXT:    addis r3, r2, .LC0@toc@ha
 ; CHECK-BE-NEXT:    ld r29, .LC0@toc@l(r3)
 ; CHECK-BE-NEXT:    b .LBB0_2
 ; CHECK-BE-NEXT:  .LBB0_1: # %bb43

llvm/test/CodeGen/PowerPC/p10-spill-crun.ll

 ; CHECK-NEXT:    mr r28, r5
 ; CHECK-NEXT:    bl call_1@notoc
 ; CHECK-NEXT:    cmpwi r3, 0
 ; CHECK-NEXT:    mr r3, r29
 ; CHECK-NEXT:    mr r4, r30
 ; CHECK-NEXT:    crnot 4*cr2+eq, eq
 ; CHECK-NEXT:    bl call_2@notoc
 ; CHECK-NEXT:    mr r27, r3
-; CHECK-NEXT:    srwi r3, r28, 4
-; CHECK-NEXT:    andi. r3, r3, 1
+; CHECK-NEXT:    rlwinm. r3, r28, 28, 31, 31
 ; CHECK-NEXT:    crmove 4*cr2+gt, gt
 ; CHECK-NEXT:    bc 12, 4*cr5+lt, .LBB0_2
 ; CHECK-NEXT:  # %bb.1: # %bb9
 ; CHECK-NEXT:    mr r3, r29
 ; CHECK-NEXT:    mr r4, r30
 ; CHECK-NEXT:    bl call_3@notoc
 ; CHECK-NEXT:  .LBB0_2: # %bb12
-; CHECK-NEXT:    srwi r3, r28, 7
-; CHECK-NEXT:    andi. r3, r3, 1
+; CHECK-NEXT:    rlwinm. r3, r28, 25, 31, 31
 ; CHECK-NEXT:    crmove 4*cr2+un, gt
 ; CHECK-NEXT:    bc 12, 4*cr2+eq, .LBB0_7
 ; CHECK-NEXT:  # %bb.3: # %bb37
 ; CHECK-NEXT:    lwz r28, 0(r3)
 ; CHECK-NEXT:    bc 12, 4*cr5+lt, .LBB0_5
 ; CHECK-NEXT:  # %bb.4: # %bb37
 ; CHECK-NEXT:    bc 4, 4*cr5+lt, .LBB0_14
 ; CHECK-NEXT:  .LBB0_5: # %bb42

 ; CHECK-BE-NEXT:    nop
 ; CHECK-BE-NEXT:    cmpwi r3, 0
 ; CHECK-BE-NEXT:    mr r3, r29
 ; CHECK-BE-NEXT:    mr r4, r30
 ; CHECK-BE-NEXT:    crnot 4*cr2+eq, eq
 ; CHECK-BE-NEXT:    bl call_2
 ; CHECK-BE-NEXT:    nop
 ; CHECK-BE-NEXT:    mr r27, r3
-; CHECK-BE-NEXT:    srwi r3, r28, 4
-; CHECK-BE-NEXT:    andi. r3, r3, 1
+; CHECK-BE-NEXT:    rlwinm. r3, r28, 28, 31, 31
 ; CHECK-BE-NEXT:    crmove 4*cr2+gt, gt
 ; CHECK-BE-NEXT:    bc 12, 4*cr5+lt, .LBB0_2
 ; CHECK-BE-NEXT:  # %bb.1: # %bb9
 ; CHECK-BE-NEXT:    mr r3, r29
 ; CHECK-BE-NEXT:    mr r4, r30
 ; CHECK-BE-NEXT:    bl call_3
 ; CHECK-BE-NEXT:    nop
 ; CHECK-BE-NEXT:  .LBB0_2: # %bb12
-; CHECK-BE-NEXT:    srwi r3, r28, 7
-; CHECK-BE-NEXT:    andi. r3, r3, 1
+; CHECK-BE-NEXT:    rlwinm. r3, r28, 25, 31, 31
 ; CHECK-BE-NEXT:    crmove 4*cr2+un, gt
 ; CHECK-BE-NEXT:    bc 12, 4*cr2+eq, .LBB0_7
 ; CHECK-BE-NEXT:  # %bb.3: # %bb37
 ; CHECK-BE-NEXT:    lwz r28, 0(r3)
 ; CHECK-BE-NEXT:    addis r3, r2, global_1@toc@ha
 ; CHECK-BE-NEXT:    bc 12, 4*cr5+lt, .LBB0_5
 ; CHECK-BE-NEXT:  # %bb.4: # %bb37
 ; CHECK-BE-NEXT:    bc 4, 4*cr5+lt, .LBB0_14

llvm/test/CodeGen/PowerPC/vsx_builtins.ll

 declare i32 @llvm.ppc.vsx.xvtsqrtsp(<4 x float>)
 
 define i32 @xvtdivdp_andi(<2 x double> %a, <2 x double> %b) {
 ; CHECK-LABEL: xvtdivdp_andi:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xvtdivdp cr0, v2, v3
 ; CHECK-NEXT:    li r4, 222
 ; CHECK-NEXT:    mfocrf r3, 128
-; CHECK-NEXT:    srwi r3, r3, 28
-; CHECK-NEXT:    andi. r3, r3, 2
+; CHECK-NEXT:    rlwinm. r3, r3, 4, 30, 30
 ; CHECK-NEXT:    li r3, 22
 ; CHECK-NEXT:    iseleq r3, r4, r3
 ; CHECK-NEXT:    blr
   entry:
     %0 = tail call i32 @llvm.ppc.vsx.xvtdivdp(<2 x double> %a, <2 x double> %b)
     %1 = and i32 %0, 2
     %cmp.not = icmp eq i32 %1, 0
     %retval.0 = select i1 %cmp.not, i32 222, i32 22