[AArch64] Redundant masks in downcast long multiply

[NickGuy]

Summary

Adds patterns to catch masks preceeding a long multiply,
and generating a single umull/smull instruction instead.

[dmgreen]

Looks nice to me. Is it worth adding mul (sext_inreg, sext i32) patterns too in case one operand is sext and the other is being masked? mul is commutative so I think it would only be two extra patterns, one for sext and one for zext.

llvm/lib/Target/AArch64/AArch64InstrInfo.td

1479

Nit: Can you line up the ('s for the input and the output
The other patterns below have output type's too. It's probably worth adding those just for consistency.

[NickGuy]

Looks nice to me. Is it worth adding mul (sext_inreg, sext i32) patterns too in case one operand is sext and the other is being masked? mul is commutative so I think it would only be two extra patterns, one for sext and one for zext.

Added, though I did have some difficulties hand-crafting something that would use these patterns (hence no specific tests)

llvm/lib/Target/AArch64/AArch64InstrInfo.td

1479

Parentheses aligned and output put types added, thanks :)

[dmgreen]

Something like https://godbolt.org/z/q376ob maybe?

llvm/lib/Target/AArch64/AArch64InstrInfo.td

1480

GPR32 I think, for the sext input. And then the output can use the GPR32 directly. Like the SMADDLrrr pattern below.

[dmgreen]

llvm/lib/Target/AArch64/AArch64InstrInfo.td

1483

This pattern isn't needed I don't think. The other four you have here look good to me, but I would remove the whitespace and maybe reorder them.

llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll

24

Can you add a commuted test too, where the and and the conv are used the other way around. Same for smull. They should match automatically I think, with the patterns that are already here.

[NickGuy]

This pattern isn't needed I don't think

Removed

but I would remove the whitespace and maybe reorder them.

Done

Can you add a commuted test too

Added, the patterns do indeed match

[dmgreen]

Brilliant, thanks. LGTM

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 } // AddedComplexity = 5
 
 let AddedComplexity = 5 in {
 def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>;
 def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>;
 def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;
 def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;
 
+def : Pat<(i64 (mul (sext_inreg GPR64:$Rn, i32), (sext_inreg GPR64:$Rm, i32))),
+          (SMADDLrrr (EXTRACT_SUBREG $Rn, sub_32), (EXTRACT_SUBREG $Rm, sub_32), XZR)>;
+
+def : Pat<(i64 (mul (sext_inreg GPR64:$Rn, i32), (sext GPR32:$Rm))),
+          (SMADDLrrr (EXTRACT_SUBREG $Rn, sub_32), $Rm, XZR)>;
+def : Pat<(i64 (mul (sext_inreg GPR64:$Rn, i32), (zext GPR32:$Rm))),
+          (SMADDLrrr (EXTRACT_SUBREG $Rn, sub_32), $Rm, XZR)>;
+def : Pat<(i64 (mul (and GPR64:$Rn, 0xFFFFFFFF), (zext GPR32:$Rm))),
+          (UMADDLrrr (EXTRACT_SUBREG $Rn, sub_32), $Rm, XZR)>;
+
+def : Pat<(i64 (mul (and GPR64:$Rn, 0xFFFFFFFF), (and GPR64:$Rm, 0xFFFFFFFF))),
+          (UMADDLrrr (EXTRACT_SUBREG $Rn, sub_32), (EXTRACT_SUBREG $Rm, sub_32), XZR)>;
+
 def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))),
           (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
 def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))),
           (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
 
 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))),
           (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))),

llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-none-linux-gnu < %s -o -| FileCheck %s
+
+define i64 @umull(i64 %x0, i64 %x1) {
+; CHECK-LABEL: umull:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    umull x0, w1, w0
+; CHECK-NEXT:    ret
+entry:
+  %and = and i64 %x0, 4294967295
+  %and1 = and i64 %x1, 4294967295
+  %mul = mul nuw i64 %and1, %and
+  ret i64 %mul
+}
+
+define i64 @umull2(i64 %x, i32 %y) {
+; CHECK-LABEL: umull2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    umull x0, w0, w1
+; CHECK-NEXT:    ret
+entry:
+  %and = and i64 %x, 4294967295
+  %conv = zext i32 %y to i64
+  %mul = mul nuw nsw i64 %and, %conv
+  ret i64 %mul
+}
+
+define i64 @smull(i64 %x0, i64 %x1) {
+; CHECK-LABEL: smull:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    smull x0, w1, w0
+; CHECK-NEXT:    ret
+entry:
+  %sext = shl i64 %x0, 32
+  %conv1 = ashr exact i64 %sext, 32
+  %sext4 = shl i64 %x1, 32
+  %conv3 = ashr exact i64 %sext4, 32
+  %mul = mul nsw i64 %conv3, %conv1
+  ret i64 %mul
+}
+
+define i64 @smull2(i64 %x, i32 %y) {
+; CHECK-LABEL: smull2:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    smull x0, w0, w1
+; CHECK-NEXT:    ret
+entry:
+  %shl = shl i64 %x, 32
+  %shr = ashr exact i64 %shl, 32
+  %conv = sext i32 %y to i64
+  %mul = mul nsw i64 %shr, %conv
+  ret i64 %mul
+}