[HazardRec] Allow inserting multiple wait-states simultaneously

[kerbowa]

Summary

If a target can encode multiple wait-states into a noop allow emitting such
instructions directly.

[foad]

Looks good modulo comments inline.

llvm/include/llvm/CodeGen/ScheduleHazardRecognizer.h

120

I think unsigned would make more sense, and WaitStates seems like AMDGPU-specific terminology.

llvm/include/llvm/CodeGen/TargetInstrInfo.h

1349

Likewise.

[foad]

There's a comment in AMDGPUTargetMachine.cpp that you could remove:

// FIXME: This stand-alone pass will emit indiv. S_NOP 0, as needed. It would
// be better for it to emit S_NOP <N> when possible.

[rampitec]

Do we properly count number of pre-existing wait states if we have s_nop > 0?

[kerbowa]

Address comments.

[kerbowa]

In D89753#2342419, @rampitec wrote:

Do we properly count number of pre-existing wait states if we have s_nop > 0?

In "HazardRecognizerMode", yes. It uses SIInstrInfo::getNumWaitStates which accounts for noops with immediates > 0.

The post-RA scheduler should not insert these combined noops so we did not handle it there.

[rampitec]

LGTM

[dmgreen]

Looks nice and clean.

llvm/include/llvm/CodeGen/ScheduleHazardRecognizer.h

public:
   virtual void RecedeCycle() {}
 
   /// EmitNoop - This callback is invoked when a noop was added to the
   /// instruction stream.
   virtual void EmitNoop() {
     // Default implementation: count it as a cycle.
     AdvanceCycle();
   }
+
+  /// EmitNoops - This callback is invoked when noops were added to the
+  /// instruction stream.
+  virtual void EmitNoops(unsigned Quantity) {
+    // Default implementation: count it as a cycle.
+    for (unsigned i = 0; i < Quantity; ++i)
+      EmitNoop();
+  }
 };
 
 } // end namespace llvm
 
 #endif // LLVM_CODEGEN_SCHEDULEHAZARDRECOGNIZER_H

llvm/include/llvm/CodeGen/TargetInstrInfo.h

public:
   reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
     return true;
   }
 
   /// Insert a noop into the instruction stream at the specified point.
   virtual void insertNoop(MachineBasicBlock &MBB,
                           MachineBasicBlock::iterator MI) const;
 
+  /// Insert noops into the instruction stream at the specified point.
+  virtual void insertNoops(MachineBasicBlock &MBB,
+                           MachineBasicBlock::iterator MI,
+                           unsigned Quantity) const;
+
   /// Return the noop instruction to use for a noop.
   virtual void getNoop(MCInst &NopInst) const;
 
   /// Return true for post-incremented instructions.
   virtual bool isPostIncrement(const MachineInstr &MI) const { return false; }
 
   /// Returns true if the instruction is already predicated.
   virtual bool isPredicated(const MachineInstr &MI) const { return false; }

llvm/lib/CodeGen/PostRAHazardRecognizer.cpp

bool PostRAHazardRecognizer::runOnMachineFunction(MachineFunction &Fn) {
 
   // Loop over all of the basic blocks
   for (auto &MBB : Fn) {
     // We do not call HazardRec->reset() here to make sure we are handling noop
     // hazards at the start of basic blocks.
     for (MachineInstr &MI : MBB) {
       // If we need to emit noops prior to this instruction, then do so.
       unsigned NumPreNoops = HazardRec->PreEmitNoops(&MI);
-      for (unsigned i = 0; i != NumPreNoops; ++i) {
-        HazardRec->EmitNoop();
-        TII->insertNoop(MBB, MachineBasicBlock::iterator(MI));
-        ++NumNoops;
-      }
+      HazardRec->EmitNoops(NumPreNoops);
+      TII->insertNoops(MBB, MachineBasicBlock::iterator(MI), NumPreNoops);
+      NumNoops += NumPreNoops;
 
       HazardRec->EmitInstruction(&MI);
       if (HazardRec->atIssueLimit()) {
         HazardRec->AdvanceCycle();
       }
     }
   }
   return true;
 }

llvm/lib/CodeGen/TargetInstrInfo.cpp

 
 /// insertNoop - Insert a noop into the instruction stream at the specified
 /// point.
 void TargetInstrInfo::insertNoop(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator MI) const {
   llvm_unreachable("Target didn't implement insertNoop!");
 }
 
+/// insertNoops - Insert noops into the instruction stream at the specified
+/// point.
+void TargetInstrInfo::insertNoops(MachineBasicBlock &MBB,
+                                  MachineBasicBlock::iterator MI,
+                                  unsigned Quantity) const {
+  for (unsigned i = 0; i < Quantity; ++i)
+    insertNoop(MBB, MI);
+}
+
 static bool isAsmComment(const char *Str, const MCAsmInfo &MAI) {
   return strncmp(Str, MAI.getCommentString().data(),
                  MAI.getCommentString().size()) == 0;
 }
 
 /// Measure the specified inline asm to determine an approximation of its
 /// length.
 /// Comments (which run till the next SeparatorString or newline) do not

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

void GCNPassConfig::addPreEmitPass() {
   // The hazard recognizer that runs as part of the post-ra scheduler does not
   // guarantee to be able handle all hazards correctly. This is because if there
   // are multiple scheduling regions in a basic block, the regions are scheduled
   // bottom up, so when we begin to schedule a region we don't know what
   // instructions were emitted directly before it.
   //
   // Here we add a stand-alone hazard recognizer pass which can handle all
   // cases.
-  //
-  // FIXME: This stand-alone pass will emit indiv. S_NOP 0, as needed. It would
-  // be better for it to emit S_NOP <N> when possible.
   addPass(&PostRAHazardRecognizerID);
   addPass(&BranchRelaxationPassID);
 }
 
 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
   return new GCNPassConfig(*this, PM);
 }
 

llvm/lib/Target/AMDGPU/SIInstrInfo.h

public:
   void legalizeOperands(MachineInstr &MI,
                         MachineDominatorTree *MDT = nullptr) const;
 
   /// Replace this instruction's opcode with the equivalent VALU
   /// opcode.  This function will also move the users of \p MI to the
   /// VALU if necessary. If present, \p MDT is updated.
   void moveToVALU(MachineInstr &MI, MachineDominatorTree *MDT = nullptr) const;
 
-  void insertWaitStates(MachineBasicBlock &MBB,MachineBasicBlock::iterator MI,
-                        int Count) const;
-
   void insertNoop(MachineBasicBlock &MBB,
                   MachineBasicBlock::iterator MI) const override;
 
+  void insertNoops(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
+                   unsigned Quantity) const override;
+
   void insertReturn(MachineBasicBlock &MBB) const;
   /// Return the number of wait states that result from executing this
   /// instruction.
   static unsigned getNumWaitStates(const MachineInstr &MI);
 
   /// Returns the operand named \p Op.  If \p MI does not have an
   /// operand named \c Op, this function returns nullptr.
   LLVM_READONLY

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

void SIInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
   BuildMI(MBB, MI, DL, get(Opcode), DestReg)
     .addFrameIndex(FrameIndex)        // vaddr
     .addReg(MFI->getScratchRSrcReg()) // scratch_rsrc
     .addReg(MFI->getStackPtrOffsetReg()) // scratch_offset
     .addImm(0)                           // offset
     .addMemOperand(MMO);
 }
 
-void SIInstrInfo::insertWaitStates(MachineBasicBlock &MBB,
-                                   MachineBasicBlock::iterator MI,
-                                   int Count) const {
+void SIInstrInfo::insertNoop(MachineBasicBlock &MBB,
+                             MachineBasicBlock::iterator MI) const {
+  insertNoops(MBB, MI, 1);
+}
+
+void SIInstrInfo::insertNoops(MachineBasicBlock &MBB,
+                              unsigned Quantity) const {
   DebugLoc DL = MBB.findDebugLoc(MI);
-  while (Count > 0) {
-    int Arg;
-    if (Count >= 8)
+  while (Quantity > 0) {
+    unsigned Arg;
+    if (Quantity >= 8)
       Arg = 7;
     else
-      Arg = Count - 1;
-    Count -= 8;
-    BuildMI(MBB, MI, DL, get(AMDGPU::S_NOP))
-            .addImm(Arg);
+      Arg = Quantity - 1;
+    Quantity -= Arg + 1;
+    BuildMI(MBB, MI, DL, get(AMDGPU::S_NOP)).addImm(Arg);
   }
 }
 
-void SIInstrInfo::insertNoop(MachineBasicBlock &MBB,
-                             MachineBasicBlock::iterator MI) const {
-  insertWaitStates(MBB, MI, 1);
-}
-
 void SIInstrInfo::insertReturn(MachineBasicBlock &MBB) const {
   auto MF = MBB.getParent();
   SIMachineFunctionInfo *Info = MF->getInfo<SIMachineFunctionInfo>();
 
   assert(Info->isEntryFunction());
 
   if (MBB.succ_empty()) {
     bool HasNoTerminator = MBB.getFirstTerminator() == MBB.end();

llvm/test/CodeGen/AMDGPU/fp-atomic-to-s_denormmode.mir

 # RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s | FileCheck -check-prefix=GCN %s
 
 # GCN-LABEL: name: flat_atomic_fcmpswap_to_s_denorm_mode
 # GCN:      FLAT_ATOMIC_FCMPSWAP
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: S_DENORM_MODE
 ---
 name:            flat_atomic_fcmpswap_to_s_denorm_mode
 body:            |
   bb.0:
     FLAT_ATOMIC_FCMPSWAP undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
     S_DENORM_MODE 0, implicit-def $mode, implicit $mode
 ...
 
 # GCN-LABEL: name: flat_atomic_fcmpswap_x2_to_s_denorm_mode
 # GCN:      FLAT_ATOMIC_FCMPSWAP_X2
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: S_DENORM_MODE
 ---
 name:            flat_atomic_fcmpswap_x2_to_s_denorm_mode
 body:            |
   bb.0:
     FLAT_ATOMIC_FCMPSWAP_X2 undef %0:vreg_64, undef %1:vreg_128, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
     S_DENORM_MODE 0, implicit-def $mode, implicit $mode
 ...
 
 # GCN-LABEL: name: flat_atomic_fmax_to_s_denorm_mode
 # GCN:      FLAT_ATOMIC_FMAX
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: S_DENORM_MODE
 ---
 name:            flat_atomic_fmax_to_s_denorm_mode
 body:            |
   bb.0:
     FLAT_ATOMIC_FMAX undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
     S_DENORM_MODE 0, implicit-def $mode, implicit $mode
 ...
 
 # GCN-LABEL: name: flat_atomic_fmax_x2_to_s_denorm_mode
 # GCN:      FLAT_ATOMIC_FMAX_X2
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: S_DENORM_MODE
 ---
 name:            flat_atomic_fmax_x2_to_s_denorm_mode
 body:            |
   bb.0:
     FLAT_ATOMIC_FMAX_X2 undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
     S_DENORM_MODE 0, implicit-def $mode, implicit $mode
 ...
 
 # GCN-LABEL: name: flat_atomic_fmin_to_s_denorm_mode
 # GCN:      FLAT_ATOMIC_FMIN
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: S_DENORM_MODE
 ---
 name:            flat_atomic_fmin_to_s_denorm_mode
 body:            |
   bb.0:
     FLAT_ATOMIC_FMIN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
     S_DENORM_MODE 0, implicit-def $mode, implicit $mode
 ...
 
 # GCN-LABEL: name: flat_atomic_fmin_x2_to_s_denorm_mode
 # GCN:      FLAT_ATOMIC_FMIN_X2
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: S_DENORM_MODE
 ---
 name:            flat_atomic_fmin_x2_to_s_denorm_mode
 body:            |
   bb.0:
     FLAT_ATOMIC_FMIN_X2 undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
     S_DENORM_MODE 0, implicit-def $mode, implicit $mode
 ...
 
 # GCN-LABEL: name: flat_atomic_fcmpswap_x2_rtn_to_s_denorm_mode
 # GCN:      FLAT_ATOMIC_FCMPSWAP_X2_RTN
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: S_DENORM_MODE
 ---
 name:            flat_atomic_fcmpswap_x2_rtn_to_s_denorm_mode
 body:            |
   bb.0:
     %2:vreg_64 = FLAT_ATOMIC_FCMPSWAP_X2_RTN undef %0:vreg_64, undef %1:vreg_128, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
     S_DENORM_MODE 0, implicit-def $mode, implicit $mode
 ...
 
 # GCN-LABEL: name: flat_atomic_fmax_rtn_to_s_denorm_mode
 # GCN:      FLAT_ATOMIC_FMAX_RTN
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: S_DENORM_MODE
 ---
 name:            flat_atomic_fmax_rtn_to_s_denorm_mode
 body:            |
   bb.0:
     %2:vgpr_32 = FLAT_ATOMIC_FMAX_RTN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
     S_DENORM_MODE 0, implicit-def $mode, implicit $mode
 ...
 
 # GCN-LABEL: name: flat_atomic_fmax_x2_rtn_to_s_denorm_mode
 # GCN:      FLAT_ATOMIC_FMAX_X2_RTN
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: S_DENORM_MODE
 ---
 name:            flat_atomic_fmax_x2_rtn_to_s_denorm_mode
 body:            |
   bb.0:
     %2:vreg_64 = FLAT_ATOMIC_FMAX_X2_RTN undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
     S_DENORM_MODE 0, implicit-def $mode, implicit $mode
 ...
 
 # GCN-LABEL: name: flat_atomic_fmin_rtn_to_s_denorm_mode
 # GCN:      FLAT_ATOMIC_FMIN_RTN
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: S_DENORM_MODE
 ---
 name:            flat_atomic_fmin_rtn_to_s_denorm_mode
 body:            |
   bb.0:
     %2:vgpr_32 = FLAT_ATOMIC_FMIN_RTN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
     S_DENORM_MODE 0, implicit-def $mode, implicit $mode
 ...
 
 # GCN-LABEL: name: flat_atomic_fmin_x2_rtn_to_s_denorm_mode
 # GCN:      FLAT_ATOMIC_FMIN_X2_RTN
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: S_DENORM_MODE
 ---
 name:            flat_atomic_fmin_x2_rtn_to_s_denorm_mode
 body:            |
   bb.0:
     %2:vreg_64 = FLAT_ATOMIC_FMIN_X2_RTN undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
     S_DENORM_MODE 0, implicit-def $mode, implicit $mode
 ...
 
 # GCN-LABEL: name: flat_atomic_fcmpswap_rtn_to_s_denorm_mode
 # GCN:      FLAT_ATOMIC_FCMPSWAP_RTN
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: S_DENORM_MODE
 ---
 name:            flat_atomic_fcmpswap_rtn_to_s_denorm_mode
 body:            |
   bb.0:
     %2:vgpr_32 = FLAT_ATOMIC_FCMPSWAP_RTN undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec, implicit $flat_scr :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
     S_DENORM_MODE 0, implicit-def $mode, implicit $mode
 ...
 
 # GCN-LABEL: name: global_atomic_fcmpswap_to_s_denorm_mode
 # GCN:      GLOBAL_ATOMIC_FCMPSWAP
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: S_DENORM_MODE
 ---
 name:            global_atomic_fcmpswap_to_s_denorm_mode
 body:            |
   bb.0:
     GLOBAL_ATOMIC_FCMPSWAP undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
     S_DENORM_MODE 0, implicit-def $mode, implicit $mode
 ...
 
 # GCN-LABEL: name: global_atomic_fcmpswap_x2_to_s_denorm_mode
 # GCN:      GLOBAL_ATOMIC_FCMPSWAP_X2
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: S_DENORM_MODE
 ---
 name:            global_atomic_fcmpswap_x2_to_s_denorm_mode
 body:            |
   bb.0:
     GLOBAL_ATOMIC_FCMPSWAP_X2 undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
     S_DENORM_MODE 0, implicit-def $mode, implicit $mode
 ...
 
 # GCN-LABEL: name: global_atomic_fmax_to_s_denorm_mode
 # GCN:      GLOBAL_ATOMIC_FMAX
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: S_DENORM_MODE
 ---
 name:            global_atomic_fmax_to_s_denorm_mode
 body:            |
   bb.0:
     GLOBAL_ATOMIC_FMAX undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
     S_DENORM_MODE 0, implicit-def $mode, implicit $mode
 ...
 
 # GCN-LABEL: name: global_atomic_fmax_x2_to_s_denorm_mode
 # GCN:      GLOBAL_ATOMIC_FMAX_X2
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: S_DENORM_MODE
 ---
 name:            global_atomic_fmax_x2_to_s_denorm_mode
 body:            |
   bb.0:
     GLOBAL_ATOMIC_FMAX_X2 undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
     S_DENORM_MODE 0, implicit-def $mode, implicit $mode
 ...
 
 # GCN-LABEL: name: global_atomic_fmin_to_s_denorm_mode
 # GCN:      GLOBAL_ATOMIC_FMIN
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: S_DENORM_MODE
 ---
 name:            global_atomic_fmin_to_s_denorm_mode
 body:            |
   bb.0:
     GLOBAL_ATOMIC_FMIN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
     S_DENORM_MODE 0, implicit-def $mode, implicit $mode
 ...
 
 # GCN-LABEL: name: global_atomic_fmin_x2_to_s_denorm_mode
 # GCN:      GLOBAL_ATOMIC_FMIN_X2
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: S_DENORM_MODE
 ---
 name:            global_atomic_fmin_x2_to_s_denorm_mode
 body:            |
   bb.0:
     GLOBAL_ATOMIC_FMIN_X2 undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
     S_DENORM_MODE 0, implicit-def $mode, implicit $mode
 ...
 
 # GCN-LABEL: name: global_atomic_fcmpswap_rtn_to_s_denorm_mode
 # GCN:      GLOBAL_ATOMIC_FCMPSWAP_RTN
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: S_DENORM_MODE
 ---
 name:            global_atomic_fcmpswap_rtn_to_s_denorm_mode
 body:            |
   bb.0:
     %2:vgpr_32 = GLOBAL_ATOMIC_FCMPSWAP_RTN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
     S_DENORM_MODE 0, implicit-def $mode, implicit $mode
 ...
 
 # GCN-LABEL: name: global_atomic_fcmpswap_x2_rtn_to_s_denorm_mode
 # GCN:      GLOBAL_ATOMIC_FCMPSWAP_X2_RTN
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: S_DENORM_MODE
 ---
 name:            global_atomic_fcmpswap_x2_rtn_to_s_denorm_mode
 body:            |
   bb.0:
     %2:vreg_64 = GLOBAL_ATOMIC_FCMPSWAP_X2_RTN undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
     S_DENORM_MODE 0, implicit-def $mode, implicit $mode
 ...
 
 # GCN-LABEL: name: global_atomic_fmax_rtn_to_s_denorm_mode
 # GCN:      GLOBAL_ATOMIC_FMAX_RTN
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: S_DENORM_MODE
 ---
 name:            global_atomic_fmax_rtn_to_s_denorm_mode
 body:            |
   bb.0:
     %2:vgpr_32 = GLOBAL_ATOMIC_FMAX_RTN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
     S_DENORM_MODE 0, implicit-def $mode, implicit $mode
 ...
 
 # GCN-LABEL: name: global_atomic_fmax_x2_rtn_to_s_denorm_mode
 # GCN:      GLOBAL_ATOMIC_FMAX_X2_RTN
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: S_DENORM_MODE
 ---
 name:            global_atomic_fmax_x2_rtn_to_s_denorm_mode
 body:            |
   bb.0:
     %2:vreg_64 = GLOBAL_ATOMIC_FMAX_X2_RTN undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
     S_DENORM_MODE 0, implicit-def $mode, implicit $mode
 ...
 
 # GCN-LABEL: name: global_atomic_fmin_rtn_to_s_denorm_mode
 # GCN:      GLOBAL_ATOMIC_FMIN_RTN
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: S_DENORM_MODE
 ---
 name:            global_atomic_fmin_rtn_to_s_denorm_mode
 body:            |
   bb.0:
     %2:vgpr_32 = GLOBAL_ATOMIC_FMIN_RTN undef %0:vreg_64, undef %1:vgpr_32, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
     S_DENORM_MODE 0, implicit-def $mode, implicit $mode
 ...
 
 # GCN-LABEL: name: global_atomic_fmin_x2_rtn_to_s_denorm_mode
 # GCN:      GLOBAL_ATOMIC_FMIN_X2_RTN
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: S_DENORM_MODE
 ---
 name:            global_atomic_fmin_x2_rtn_to_s_denorm_mode
 body:            |
   bb.0:
     %2:vreg_64 = GLOBAL_ATOMIC_FMIN_X2_RTN undef %0:vreg_64, undef %1:vreg_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
     S_DENORM_MODE 0, implicit-def $mode, implicit $mode
 ...
 
 # GCN-LABEL: name: global_atomic_fcmpswap_saddr_to_s_denorm_mode
 # GCN:      GLOBAL_ATOMIC_FCMPSWAP_SADDR
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: S_DENORM_MODE
 ---
 name:            global_atomic_fcmpswap_saddr_to_s_denorm_mode
 body:            |
   bb.0:
     GLOBAL_ATOMIC_FCMPSWAP_SADDR undef %0:vgpr_32, undef %1:vgpr_32, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
     S_DENORM_MODE 0, implicit-def $mode, implicit $mode
 ...
 
 # GCN-LABEL: name: global_atomic_fcmpswap_x2_saddr_rtn_to_s_denorm_mode
 # GCN:      GLOBAL_ATOMIC_FCMPSWAP_X2_SADDR_RTN
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: S_DENORM_MODE
 ---
 name:            global_atomic_fcmpswap_x2_saddr_rtn_to_s_denorm_mode
 body:            |
   bb.0:
     %2:vreg_64 = GLOBAL_ATOMIC_FCMPSWAP_X2_SADDR_RTN undef %0:vgpr_32, undef %1:vreg_64, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
     S_DENORM_MODE 0, implicit-def $mode, implicit $mode
 ...
 
 # GCN-LABEL: name: global_atomic_fmax_saddr_rtn_to_s_denorm_mode
 # GCN:      GLOBAL_ATOMIC_FMAX_SADDR_RTN
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: S_DENORM_MODE
 ---
 name:            global_atomic_fmax_saddr_rtn_to_s_denorm_mode
 body:            |
   bb.0:
     %2:vgpr_32 = GLOBAL_ATOMIC_FMAX_SADDR_RTN undef %0:vgpr_32, undef %1:vgpr_32, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
     S_DENORM_MODE 0, implicit-def $mode, implicit $mode
 ...
 
 # GCN-LABEL: name: global_atomic_fmax_x2_saddr_rtn_to_s_denorm_mode
 # GCN:      GLOBAL_ATOMIC_FMAX_X2_SADDR_RTN
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: S_DENORM_MODE
 ---
 name:            global_atomic_fmax_x2_saddr_rtn_to_s_denorm_mode
 body:            |
   bb.0:
     %2:vreg_64 = GLOBAL_ATOMIC_FMAX_X2_SADDR_RTN undef %0:vgpr_32, undef %1:vreg_64, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
     S_DENORM_MODE 0, implicit-def $mode, implicit $mode
 ...
 
 # GCN-LABEL: name: global_atomic_fmin_saddr_rtn_to_s_denorm_mode
 # GCN:      GLOBAL_ATOMIC_FMIN_SADDR_RTN
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: S_DENORM_MODE
 ---
 name:            global_atomic_fmin_saddr_rtn_to_s_denorm_mode
 body:            |
   bb.0:
     %2:vgpr_32 = GLOBAL_ATOMIC_FMIN_SADDR_RTN undef %0:vgpr_32, undef %1:vgpr_32, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
     S_DENORM_MODE 0, implicit-def $mode, implicit $mode
 ...
 
 # GCN-LABEL: name: global_atomic_fmin_x2_saddr_rtn_to_s_denorm_mode
 # GCN:      GLOBAL_ATOMIC_FMIN_X2_SADDR_RTN
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: S_DENORM_MODE
 ---
 name:            global_atomic_fmin_x2_saddr_rtn_to_s_denorm_mode
 body:            |
   bb.0:
     %2:vreg_64 = GLOBAL_ATOMIC_FMIN_X2_SADDR_RTN undef %0:vgpr_32, undef %1:vreg_64, undef %3:sgpr_64, 0, 0, implicit $exec :: (volatile load store seq_cst seq_cst 4 on `float addrspace(1)* undef`)
     S_DENORM_MODE 0, implicit-def $mode, implicit $mode
 ...

llvm/test/CodeGen/AMDGPU/frem.ll

 ; SI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
 ; SI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
 ; SI-NEXT:    v_div_scale_f64 v[8:9], s[0:1], v[0:1], v[2:3], v[0:1]
 ; SI-NEXT:    v_mul_f64 v[10:11], v[8:9], v[6:7]
 ; SI-NEXT:    v_fma_f64 v[12:13], -v[4:5], v[10:11], v[8:9]
 ; SI-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v5
 ; SI-NEXT:    v_cmp_eq_u32_e64 s[0:1], v1, v9
 ; SI-NEXT:    s_xor_b64 vcc, s[0:1], vcc
-; SI-NEXT:    s_nop 0
-; SI-NEXT:    s_nop 0
+; SI-NEXT:    s_nop 1
 ; SI-NEXT:    v_div_fmas_f64 v[4:5], v[12:13], v[6:7], v[10:11]
 ; SI-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
 ; SI-NEXT:    v_bfe_u32 v6, v5, 20, 11
 ; SI-NEXT:    v_add_i32_e32 v8, vcc, 0xfffffc01, v6
 ; SI-NEXT:    s_mov_b32 s1, 0xfffff
 ; SI-NEXT:    s_mov_b32 s0, s6
 ; SI-NEXT:    v_lshr_b64 v[6:7], s[0:1], v8
 ; SI-NEXT:    v_not_b32_e32 v6, v6

 ; SI-NEXT:    v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
 ; SI-NEXT:    v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
 ; SI-NEXT:    v_div_scale_f64 v[8:9], s[0:1], v[0:1], v[2:3], v[0:1]
 ; SI-NEXT:    v_mul_f64 v[10:11], v[8:9], v[6:7]
 ; SI-NEXT:    v_fma_f64 v[12:13], -v[4:5], v[10:11], v[8:9]
 ; SI-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v5
 ; SI-NEXT:    v_cmp_eq_u32_e64 s[0:1], v1, v9
 ; SI-NEXT:    s_xor_b64 vcc, s[0:1], vcc
-; SI-NEXT:    s_nop 0
-; SI-NEXT:    s_nop 0
+; SI-NEXT:    s_nop 1
 ; SI-NEXT:    v_div_fmas_f64 v[4:5], v[12:13], v[6:7], v[10:11]
 ; SI-NEXT:    v_div_fixup_f64 v[4:5], v[4:5], v[2:3], v[0:1]
 ; SI-NEXT:    v_bfe_u32 v6, v5, 20, 11
 ; SI-NEXT:    v_add_i32_e32 v8, vcc, 0xfffffc01, v6
 ; SI-NEXT:    s_mov_b32 s1, 0xfffff
 ; SI-NEXT:    s_mov_b32 s0, s6
 ; SI-NEXT:    v_lshr_b64 v[6:7], s[0:1], v8
 ; SI-NEXT:    v_not_b32_e32 v6, v6

 ; SI-NEXT:    v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
 ; SI-NEXT:    v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
 ; SI-NEXT:    v_div_scale_f64 v[12:13], s[0:1], v[2:3], v[6:7], v[2:3]
 ; SI-NEXT:    v_mul_f64 v[14:15], v[12:13], v[10:11]
 ; SI-NEXT:    v_fma_f64 v[16:17], -v[8:9], v[14:15], v[12:13]
 ; SI-NEXT:    v_cmp_eq_u32_e32 vcc, v7, v9
 ; SI-NEXT:    v_cmp_eq_u32_e64 s[0:1], v3, v13
 ; SI-NEXT:    s_xor_b64 vcc, s[0:1], vcc
-; SI-NEXT:    s_nop 0
-; SI-NEXT:    s_nop 0
+; SI-NEXT:    s_nop 1
 ; SI-NEXT:    v_div_fmas_f64 v[8:9], v[16:17], v[10:11], v[14:15]
 ; SI-NEXT:    v_div_fixup_f64 v[8:9], v[8:9], v[6:7], v[2:3]
 ; SI-NEXT:    v_bfe_u32 v10, v9, 20, 11
 ; SI-NEXT:    s_movk_i32 s8, 0xfc01
 ; SI-NEXT:    v_add_i32_e32 v12, vcc, s8, v10
 ; SI-NEXT:    s_mov_b32 s3, 0xfffff
 ; SI-NEXT:    v_lshr_b64 v[10:11], s[2:3], v12
 ; SI-NEXT:    v_not_b32_e32 v10, v10

 ; SI-NEXT:    v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
 ; SI-NEXT:    v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
 ; SI-NEXT:    v_div_scale_f64 v[10:11], s[0:1], v[0:1], v[4:5], v[0:1]
 ; SI-NEXT:    v_mul_f64 v[12:13], v[10:11], v[8:9]
 ; SI-NEXT:    v_fma_f64 v[14:15], -v[6:7], v[12:13], v[10:11]
 ; SI-NEXT:    v_cmp_eq_u32_e32 vcc, v5, v7
 ; SI-NEXT:    v_cmp_eq_u32_e64 s[0:1], v1, v11
 ; SI-NEXT:    s_xor_b64 vcc, s[0:1], vcc
-; SI-NEXT:    s_nop 0
-; SI-NEXT:    s_nop 0
+; SI-NEXT:    s_nop 1
 ; SI-NEXT:    v_div_fmas_f64 v[6:7], v[14:15], v[8:9], v[12:13]
 ; SI-NEXT:    v_div_fixup_f64 v[6:7], v[6:7], v[4:5], v[0:1]
 ; SI-NEXT:    v_bfe_u32 v8, v7, 20, 11
 ; SI-NEXT:    v_add_i32_e32 v10, vcc, s8, v8
 ; SI-NEXT:    v_lshr_b64 v[8:9], s[2:3], v10
 ; SI-NEXT:    v_not_b32_e32 v8, v8
 ; SI-NEXT:    v_and_b32_e32 v8, v6, v8
 ; SI-NEXT:    v_not_b32_e32 v9, v9

llvm/test/CodeGen/AMDGPU/hazard-hidden-bundle.mir

BUNDLE implicit-def $vgpr0 {
       $vgpr0 = V_INTERP_P1_F32 killed $vgpr4, 0, 0, implicit $mode, implicit $m0, implicit $exec
     }
     S_ENDPGM 0
 ...
 
 # GCN-LABEL: name: vmem_vcc_hazard_ignore_bundle_instr
 # GCN:      S_LOAD_DWORDX2_IMM
 # GCN-NEXT: }
-# GCN-NEXT: S_NOP
-# GCN-NEXT: S_NOP
-# GCN-NEXT: S_NOP
-# GCN-NEXT: S_NOP
+# GCN-NEXT: S_NOP 3
 # GCN:      BUFFER_LOAD_DWORD_OFFEN
 ---
 name: vmem_vcc_hazard_ignore_bundle_instr
 body: |
   bb.0:
     $sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
     $vgpr0 = IMPLICIT_DEF
     BUNDLE implicit-def $vgpr1, implicit $vgpr0, implicit $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec {
       $vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
     }
     BUNDLE implicit-def $sgpr0_sgpr1, implicit $sgpr10_sgpr11 {
       $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM $sgpr10_sgpr11, 0, 0, 0
     }
     $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, 0, implicit $exec
     S_ENDPGM 0
 ...
 
 # GCN-LABEL: name: vmem_vcc_min_of_two_after_bundle
 # GCN:      bb.2:
-# GCN-NEXT: S_NOP
-# GCN-NEXT: S_NOP
-# GCN-NEXT: S_NOP
-# GCN-NEXT: S_NOP
-# GCN-NEXT: S_NOP
+# GCN-NEXT: S_NOP 4
 # GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
 ---
 name: vmem_vcc_min_of_two_after_bundle
 body: |
   bb.0:
     successors: %bb.2
 
     BUNDLE implicit-def $vgpr1, implicit $vgpr0 {

llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir

-# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass post-RA-hazard-rec  %s -o - | FileCheck %s -check-prefixes=GCN
-# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass post-RA-hazard-rec  %s -o - | FileCheck %s -check-prefixes=GCN,CIVI
+# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass post-RA-hazard-rec  %s -o - | FileCheck %s -check-prefixes=GCN,SICI
+# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass post-RA-hazard-rec  %s -o - | FileCheck %s -check-prefixes=GCN,CIVI,SICI
 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass post-RA-hazard-rec  %s -o - | FileCheck %s -check-prefixes=GCN,CIVI,VI
 # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass post-RA-hazard-rec  %s -o - | FileCheck %s -check-prefixes=GCN,CIVI,VI,GFX9
 
 --- |
   define amdgpu_kernel void @div_fmas() { ret void }
   define amdgpu_kernel void @s_getreg() { ret void }
   define amdgpu_kernel void @s_setreg() { ret void }
   define amdgpu_kernel void @vmem_gt_8dw_store() { ret void }
   define amdgpu_kernel void @readwrite_lane() { ret void }
   define amdgpu_kernel void @rfe() { ret void }
   define amdgpu_kernel void @s_movrel() { ret void }
   define amdgpu_kernel void @v_interp() { ret void }
   define amdgpu_kernel void @dpp() { ret void }
 ...
 ---
 # GCN-LABEL: name: div_fmas
 
 # GCN-LABEL: bb.0:
 # GCN: S_MOV_B64
 # GCN-NOT: S_NOP
 # GCN: V_DIV_FMAS
 
 # GCN-LABEL: bb.1:
 # GCN: V_CMP_EQ_I32
-# GCN: S_NOP
-# GCN: S_NOP
-# GCN: S_NOP
-# GCN: S_NOP
+# GCN: S_NOP 3
 # GCN: V_DIV_FMAS_F32
 
 # GCN-LABEL: bb.2:
 # GCN: V_CMP_EQ_I32
-# GCN: S_NOP
-# GCN: S_NOP
-# GCN: S_NOP
-# GCN: S_NOP
+# GCN: S_NOP 3
 # GCN: V_DIV_FMAS_F32
 
 # GCN-LABEL: bb.3:
 # GCN: V_DIV_SCALE_F32
-# GCN: S_NOP
-# GCN: S_NOP
-# GCN: S_NOP
-# GCN: S_NOP
+# GCN: S_NOP 3
 # GCN: V_DIV_FMAS_F32
 name: div_fmas
 
 body: |
   bb.0:
     $vcc = S_MOV_B64 0
     $vgpr0 = V_DIV_FMAS_F32 0, $vgpr1, 0, $vgpr2, 0, $vgpr3, 0, 0, implicit $mode, implicit $vcc, implicit $exec
     S_BRANCH %bb.1

 ...
 
 ...
 ---
 # GCN-LABEL: name: s_getreg
 
 # GCN-LABEL: bb.0:
 # GCN: S_SETREG
-# GCN: S_NOP 0
-# GCN: S_NOP 0
+# GCN: S_NOP 1
 # GCN: S_GETREG
 
 # GCN-LABEL: bb.1:
 # GCN: S_SETREG_IMM32
-# GCN: S_NOP 0
-# GCN: S_NOP 0
+# GCN: S_NOP 1
 # GCN: S_GETREG
 
 # GCN-LABEL: bb.2:
 # GCN: S_SETREG
 # GCN: S_NOP 0
 # GCN: S_GETREG
 
 # GCN-LABEL: bb.3:

 ...
 
 ...
 ---
 # GCN-LABEL: name: s_setreg
 
 # GCN-LABEL: bb.0:
 # GCN: S_SETREG
-# GCN: S_NOP 0
-# VI: S_NOP 0
-# GCN-NEXT: S_SETREG
+# SICI: S_NOP 0
+# VI: S_NOP 1
+# GCN: S_SETREG
 
 # GCN-LABEL: bb.1:
 # GCN: S_SETREG
-# GCN: S_NOP 0
-# VI: S_NOP 0
-# GCN-NEXT: S_SETREG
+# SICI: S_NOP 0
+# VI: S_NOP 1
+# GCN: S_SETREG
 
 # GCN-LABEL: bb.2:
 # GCN: S_SETREG
 # GCN-NEXT: S_SETREG
 
 name: s_setreg
 
 body: |

 
 ...
 ---
 
 # GCN-LABEL: name: readwrite_lane
 
 # GCN-LABEL: bb.0:
 # GCN: V_ADD_CO_U32
-# GCN: S_NOP
-# GCN: S_NOP
-# GCN: S_NOP
-# GCN: S_NOP
+# GCN: S_NOP 3
 # GCN: V_READLANE_B32
 
 # GCN-LABEL: bb.1:
 # GCN: V_ADD_CO_U32
-# GCN: S_NOP
-# GCN: S_NOP
-# GCN: S_NOP
-# GCN: S_NOP
+# GCN: S_NOP 3
 # GCN: V_WRITELANE_B32
 
 # GCN-LABEL: bb.2:
 # GCN: V_ADD_CO_U32
-# GCN: S_NOP
-# GCN: S_NOP
-# GCN: S_NOP
-# GCN: S_NOP
+# GCN: S_NOP 3
 # GCN: V_READLANE_B32
 
 # GCN-LABEL: bb.3:
 # GCN: V_ADD_CO_U32
-# GCN: S_NOP
-# GCN: S_NOP
-# GCN: S_NOP
-# GCN: S_NOP
+# GCN: S_NOP 3
 # GCN: V_WRITELANE_B32
 
 name: readwrite_lane
 
 body: |
   bb.0:
     $vgpr0,$sgpr0_sgpr1 = V_ADD_CO_U32_e64 $vgpr1, $vgpr2, implicit $vcc, 0, implicit $exec
     $sgpr4 = V_READLANE_B32 $vgpr4, $sgpr0

 
 ...
 ---
 
 # GCN-LABEL: name: dpp
 
 # VI-LABEL: bb.0:
 # VI: V_MOV_B32_e32
-# VI-NEXT: S_NOP 0
-# VI-NEXT: S_NOP 0
+# VI-NEXT: S_NOP 1
 # VI-NEXT: V_MOV_B32_dpp
 
 # VI-LABEL: bb.1:
 # VI: V_CMPX_EQ_I32_e32
-# VI-NEXT: S_NOP 0
-# VI-NEXT: S_NOP 0
-# VI-NEXT: S_NOP 0
-# VI-NEXT: S_NOP 0
-# VI-NEXT: S_NOP 0
+# VI-NEXT: S_NOP 4
 # VI-NEXT: V_MOV_B32_dpp
 
 name: dpp
 
 body: |
   bb.0:
     $vgpr0 = V_MOV_B32_e32 0, implicit $exec
     $vgpr1 = V_MOV_B32_dpp $vgpr1, $vgpr0, 0, 15, 15, 0, implicit $exec
     S_BRANCH %bb.1
 
   bb.1:
     implicit $exec, implicit $vcc = V_CMPX_EQ_I32_e32 $vgpr0, $vgpr1, implicit $exec
     $vgpr3 = V_MOV_B32_dpp $vgpr3, $vgpr0, 0, 15, 15, 0, implicit $exec
     S_ENDPGM 0
 ...

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll

 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=VI,VI-OPT,PREGFX10,PREGFX10-OPT %s
 ; RUN: llc -O0 -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=VI,VI-NOOPT,PREGFX10,PREGFX10-NOOPT %s
 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefixes=VI,VI-OPT %s
 
 ; FIXME: The register allocator / scheduler should be able to avoid these hazards.
 
 ; VI-LABEL: {{^}}dpp_test:
 ; VI: v_mov_b32_e32 v0, s{{[0-9]+}}
 ; VI-NOOPT: v_mov_b32_e32 v1, s{{[0-9]+}}
-; PREGFX10-OPT: s_nop 1
-; PREGFX10-NOOPT: s_nop 0
-; PREGFX10-NOOPT: s_nop 0
+; PREGFX10: s_nop 1
 ; VI-OPT: v_mov_b32_dpp v0, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x08,0x11]
 ; VI-NOOPT: v_mov_b32_dpp v0, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x01,0x01,0x08,0x11]
 define amdgpu_kernel void @dpp_test(i32 addrspace(1)* %out, i32 %in) {
   %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in, i32 1, i32 1, i32 1, i1 1) #0
   store i32 %tmp0, i32 addrspace(1)* %out
   ret void
 }
 
 ; VI-LABEL: {{^}}dpp_wait_states:
 ; VI-NOOPT: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s{{[0-9]+}}
 ; VI: v_mov_b32_e32 [[VGPR0:v[0-9]+]], s{{[0-9]+}}
-; PREGFX10-OPT: s_nop 1
-; PREGFX10-NOOPT: s_nop 0
-; PREGFX10-NOOPT: s_nop 0
+; PREGFX10: s_nop 1
 ; VI-OPT: v_mov_b32_dpp [[VGPR0]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
 ; VI-NOOPT: v_mov_b32_dpp [[VGPR1]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:
-; PREGFX10-OPT: s_nop 1
-; PREGFX10-NOOPT: s_nop 0
-; PREGFX10-NOOPT: s_nop 0
+; PREGFX10: s_nop 1
 ; VI-OPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
 ; VI-NOOPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
 define amdgpu_kernel void @dpp_wait_states(i32 addrspace(1)* %out, i32 %in) {
   %tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in, i32 1, i32 1, i32 1, i1 1) #0
   %tmp1 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %tmp0, i32 1, i32 1, i32 1, i1 1) #0
   store i32 %tmp1, i32 addrspace(1)* %out
   ret void
 }
 
 ; VI-LABEL: {{^}}dpp_first_in_bb:
 ; VI: ; %endif
 ; PREGFX10-OPT: s_mov_b32
 ; PREGFX10-OPT: s_mov_b32
 ; PREGFX10-NOOPT: s_waitcnt
 ; PREGFX10-NOOPT: v_mov_b32_e32
-; PREGFX10-NOOPT-NEXT: s_nop 0
 ; VI: v_mov_b32_dpp [[VGPR0:v[0-9]+]], v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
-; PREGFX10-OPT: s_nop 1
+; PREGFX10: s_nop 1
 ; VI: v_mov_b32_dpp [[VGPR1:v[0-9]+]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
-; PREGFX10-OPT: s_nop 1
-; PREGFX10-NOOPT: s_nop 0
-; PREGFX10-NOOPT: s_nop 0
+; PREGFX10: s_nop 1
 ; VI: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
 define amdgpu_kernel void @dpp_first_in_bb(float addrspace(1)* %out, float addrspace(1)* %in, float %cond, float %a, float %b) {
   %cmp = fcmp oeq float %cond, 0.0
   br i1 %cmp, label %if, label %else
 
 if:
   %out_val = load float, float addrspace(1)* %out
   %if_val = fadd float %a, %out_val

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll

 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX8,GFX8-OPT,GCN-OPT %s
 ; RUN: llc -march=amdgcn -mcpu=tonga -O0 -mattr=-flat-for-global -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX8,GFX8-NOOPT %s
 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global -amdgpu-dpp-combine=false -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX10,GCN-OPT %s
 
 ; GCN-LABEL: {{^}}dpp_test:
 ; GCN:  v_mov_b32_e32 [[DST:v[0-9]+]], s{{[0-9]+}}
 ; GCN:  v_mov_b32_e32 [[SRC:v[0-9]+]], s{{[0-9]+}}
-; GFX8-OPT: s_nop 1
-; GFX8-NOOPT: s_nop 0
-; GFX8-NOOPT-NEXT: s_nop 0
+; GFX8: s_nop 1
 ; GCN:  v_mov_b32_dpp [[DST]], [[SRC]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}}
 define amdgpu_kernel void @dpp_test(i32 addrspace(1)* %out, i32 %in1, i32 %in2) {
   %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 1, i32 1, i1 0) #0
   store i32 %tmp0, i32 addrspace(1)* %out
   ret void
 }
 
 ; GCN-LABEL: {{^}}dpp_test_bc:
 ; GCN:  v_mov_b32_e32 [[DST:v[0-9]+]], s{{[0-9]+}}
 ; GCN:  v_mov_b32_e32 [[SRC:v[0-9]+]], s{{[0-9]+}}
-; GFX8-OPT: s_nop 1
-; GFX8-NOOPT: s_nop 0
-; GFX8-NOOPT-NEXT: s_nop 0
+; GFX8: s_nop 1
 ; GCN:  v_mov_b32_dpp [[DST]], [[SRC]] quad_perm:[2,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0{{$}}
 define amdgpu_kernel void @dpp_test_bc(i32 addrspace(1)* %out, i32 %in1, i32 %in2) {
   %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 2, i32 1, i32 1, i1 1) #0
   store i32 %tmp0, i32 addrspace(1)* %out
   ret void
 }
 
 
 ; GCN-LABEL: {{^}}dpp_test1:
 ; GFX10: v_add_nc_u32_e32 [[REG:v[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
 ; GFX8-OPT: v_add_u32_e32 [[REG:v[0-9]+]], vcc, v{{[0-9]+}}, v{{[0-9]+}}
 ; GFX8-NOOPT: v_add_u32_e64 [[REG:v[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, v{{[0-9]+}}
 ; GFX8-NOOPT: v_mov_b32_e32 v{{[0-9]+}}, 0
-; GFX8: s_nop 0
-; GFX8-NEXT: s_nop 0
+; GFX8-NOOPT: s_nop 1
+; GFX8-OPT: s_nop 0
+; GFX8-OPT-NEXT: s_nop 0
 ; GFX8-NEXT: v_mov_b32_dpp {{v[0-9]+}}, [[REG]] quad_perm:[1,0,3,2] row_mask:0xf bank_mask:0xf
 @0 = internal unnamed_addr addrspace(3) global [448 x i32] undef, align 4
 define weak_odr amdgpu_kernel void @dpp_test1(i32* %arg) local_unnamed_addr {
 bb:
   %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
   %tmp1 = zext i32 %tmp to i64
   %tmp2 = getelementptr inbounds [448 x i32], [448 x i32] addrspace(3)* @0, i32 0, i32 %tmp
   %tmp3 = load i32, i32 addrspace(3)* %tmp2, align 4

llvm/test/CodeGen/AMDGPU/mai-hazards.mir

 # RUN: llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs -run-pass post-RA-hazard-rec %s -o - | FileCheck -check-prefix=GCN %s
 
 # GCN-LABEL: name: valu_write_vgpr_mfma_read
 # GCN:      V_MOV_B32
 # GCN:      V_MOV_B32
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 1
 # GCN-NEXT: V_MFMA
 name:            valu_write_vgpr_mfma_read
 body:             |
   bb.0:
     $vgpr0 = V_MOV_B32_e32 1, implicit $exec
     $vgpr1 = V_MOV_B32_e32 1, implicit $exec
     $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec
 ...
 ---
 
 # GCN-LABEL: name: valu_write_vgpr_accvgpr_write_read
 # GCN:      V_MOV_B32
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 1
 # GCN-NEXT: V_ACCVGPR_WRITE_B32
 name:            valu_write_vgpr_accvgpr_write_read
 body:             |
   bb.0:
     $vgpr0 = V_MOV_B32_e32 1, implicit $exec
     $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr0, implicit $exec
 ...
 ---
 
 # GCN-LABEL: name: mfma_write_agpr_mfma_read_same_agpr
 # GCN:      V_MFMA
 # GCN-NEXT: V_MFMA
 name:            mfma_write_agpr_mfma_read_same_agpr
 body:             |
   bb.0:
     $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec
     $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec
 ...
 ---
 
 # GCN-LABEL: name: mfma_write_agpr_mfma_read_overlap
 # GCN:      V_MFMA
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 1
 # GCN-NEXT: V_MFMA
 name:            mfma_write_agpr_mfma_read_overlap
 body:             |
   bb.0:
     $agpr1_agpr2_agpr3_agpr4 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec
     $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec
 ...
 ---
 
 # GCN-LABEL: name: mfma_write_agpr_mfma_read_partial
 # GCN:      V_MFMA
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 1
 # GCN-NEXT: V_MFMA
 name:            mfma_write_agpr_mfma_read_partial
 body:             |
   bb.0:
     $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = V_MFMA_F32_16X16X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, 0, 0, 0, implicit $mode, implicit $exec
     $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec
 ...
 ---
 
 # GCN-LABEL: name: mfma_write_agpr_mfma_srca_read_overlap
 # GCN:      V_MFMA
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 3
 # GCN-NEXT: V_MFMA
 name:            mfma_write_agpr_mfma_srca_read_overlap
 body:             |
   bb.0:
     $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec
     $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $agpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec
 ...
 ---
 
 # GCN-LABEL: name: mfma_write_agpr_mfma_srcb_read_overlap
 # GCN:      V_MFMA
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 3
 # GCN-NEXT: V_MFMA
 name:            mfma_write_agpr_mfma_srcb_read_overlap
 body:             |
   bb.0:
     $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec
     $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $agpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec
 ...
 ---
 
 # GCN-LABEL: name: mfma_4x4_write_agpr_accvgpr_read
 # GCN:      V_MFMA_F32_4X4X1F32
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 3
 # GCN-NEXT: V_ACCVGPR_READ_B32
 name:            mfma_4x4_write_agpr_accvgpr_read
 body:             |
   bb.0:
     $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec
     $vgpr0 = V_ACCVGPR_READ_B32 killed $agpr0, implicit $exec
 ...
 ---
 
 # GCN-LABEL: name: mfma_16x16_write_agpr_accvgpr_read
 # GCN:      V_MFMA_F32_16X16X1F32
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 7
+# GCN-NEXT: S_NOP 1
 # GCN-NEXT: V_ACCVGPR_READ_B32
 name:            mfma_16x16_write_agpr_accvgpr_read
 body:             |
   bb.0:
     $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = V_MFMA_F32_16X16X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, 0, 0, 0, implicit $mode, implicit $exec
     $vgpr0 = V_ACCVGPR_READ_B32 killed $agpr0, implicit $exec
 ...
 ---
 
 # GCN-LABEL: name: mfma_32x32_write_agpr_accvgpr_read
 # GCN:      V_MFMA_F32_32X32X2F32
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 7
+# GCN-NEXT: S_NOP 7
+# GCN-NEXT: S_NOP 1
 # GCN-NEXT: V_ACCVGPR_READ_B32
 name:            mfma_32x32_write_agpr_accvgpr_read
 body:             |
   bb.0:
     $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = V_MFMA_F32_32X32X2F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, 0, 0, 0, implicit $mode, implicit $exec
     $vgpr0 = V_ACCVGPR_READ_B32 killed $agpr0, implicit $exec
 ...
 ---
 
 # GCN-LABEL: name: mfma_4x4_write_agpr_accvgpr_write
 # GCN:      V_MFMA_F32_4X4X1F32
 # GCN-NEXT: S_NOP 0
 # GCN-NEXT: V_ACCVGPR_WRITE_B32
 name:            mfma_4x4_write_agpr_accvgpr_write
 body:             |
   bb.0:
     $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec
     $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr0, implicit $exec
 ...
 ---
 
 # GCN-LABEL: name: mfma_16x16_write_agpr_accvgpr_write
 # GCN:      V_MFMA_F32_16X16X1F32
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 6
 # GCN-NEXT: V_ACCVGPR_WRITE_B32
 name:            mfma_16x16_write_agpr_accvgpr_write
 body:             |
   bb.0:
     $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = V_MFMA_F32_16X16X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, 0, 0, 0, implicit $mode, implicit $exec
     $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr0, implicit $exec
 ...
 ---
 
 # GCN-LABEL: name: mfma_32x32_write_agpr_accvgpr_write
 # GCN:      V_MFMA_F32_32X32X2F32
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 7
+# GCN-NEXT: S_NOP 6
 # GCN-NEXT: V_ACCVGPR_WRITE_B32
 name:            mfma_32x32_write_agpr_accvgpr_write
 body:             |
   bb.0:
     $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = V_MFMA_F32_32X32X2F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, 0, 0, 0, implicit $mode, implicit $exec
     $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr0, implicit $exec
 ...
 ---
 
 # GCN-LABEL: name: mfma_4x4_read_srcc_accvgpr_write
 # GCN:      V_MFMA_F32_4X4X1F32
 # GCN-NEXT: V_ACCVGPR_WRITE_B32
 name:            mfma_4x4_read_srcc_accvgpr_write
 body:             |
   bb.0:
     $agpr4_agpr5_agpr6_agpr7 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec
     $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr2, implicit $exec
 ...
 ---
 
 # GCN-LABEL: name: mfma_16x16_read_srcc_accvgpr_write
 # GCN:      V_MFMA_F32_16X16X1F32
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 4
 # GCN-NEXT: V_ACCVGPR_WRITE_B32
 name:            mfma_16x16_read_srcc_accvgpr_write
 body:             |
   bb.0:
     $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = V_MFMA_F32_16X16X1F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, 0, 0, 0, implicit $mode, implicit $exec
     $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr2, implicit $exec
 ...
 ---
 
 # GCN-LABEL: name: mfma_32x32_read_srcc_accvgpr_write
 # GCN:      V_MFMA_F32_32X32X2F32
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 7
+# GCN-NEXT: S_NOP 4
 # GCN-NEXT: V_ACCVGPR_WRITE_B32
 name:            mfma_32x32_read_srcc_accvgpr_write
 body:             |
   bb.0:
     $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = V_MFMA_F32_32X32X2F32 killed $vgpr1, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, 0, 0, 0, implicit $mode, implicit $exec
     $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr2, implicit $exec
 ...
 ---
 
 # GCN-LABEL: name: accvgpr_read_write_vgpr_valu_read
 # GCN:      V_ACCVGPR_READ_B32
 # GCN-NEXT: V_ADD_F32
 name:            accvgpr_read_write_vgpr_valu_read
 body:             |
   bb.0:
     $vgpr0 = V_ACCVGPR_READ_B32 killed $agpr4, implicit $exec
     $vgpr1 = V_ADD_F32_e32 0, killed $vgpr0, implicit $mode, implicit $exec
 ...
 ---
 
 # GCN-LABEL: name: accvgpr_read_write_vgpr_mfma_read
 # GCN:      V_ACCVGPR_READ_B32
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 1
 # GCN-NEXT: V_MFMA
 name:            accvgpr_read_write_vgpr_mfma_read
 body:             |
   bb.0:
     $vgpr0 = V_ACCVGPR_READ_B32 killed $agpr4, implicit $exec
     $agpr0_agpr1_agpr2_agpr3 = V_MFMA_F32_4X4X1F32 killed $vgpr0, killed $vgpr0, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec
 ...
 ---
 
 # GCN-LABEL: name: accvgpr_read_write_vgpr_accvgpr_write_read
 # GCN:      V_ACCVGPR_READ_B32
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 1
 # GCN-NEXT: V_ACCVGPR_WRITE_B32
 name:            accvgpr_read_write_vgpr_accvgpr_write_read
 body:             |
   bb.0:
     $vgpr0 = V_ACCVGPR_READ_B32 killed $agpr1, implicit $exec
     $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr0, implicit $exec
 ...
 ---
 
 # GCN-LABEL: name: accvgpr_write_agpr_mfma_read_srcc
 # GCN:      V_ACCVGPR_WRITE_B32
 # GCN-NEXT: S_NOP 0
 # GCN-NEXT: V_MFMA
 name:            accvgpr_write_agpr_mfma_read_srcc
 body:             |
   bb.0:
     $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr0, implicit $exec
     $agpr4_agpr5_agpr6_agpr7 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $vgpr2, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec
 ...
 ---
 
 # GCN-LABEL: name: accvgpr_write_agpr_mfma_read_srca
 # GCN:      V_ACCVGPR_WRITE_B32
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: V_MFMA
 name:            accvgpr_write_agpr_mfma_read_srca
 body:             |
   bb.0:
     $agpr8 = V_ACCVGPR_WRITE_B32 killed $vgpr0, implicit $exec
     $agpr4_agpr5_agpr6_agpr7 = V_MFMA_F32_4X4X1F32 killed $agpr8, killed $vgpr1, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec
 ...
 ---
 
 # GCN-LABEL: name: accvgpr_write_agpr_mfma_read_srcb
 # GCN:      V_ACCVGPR_WRITE_B32
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: V_MFMA
 name:            accvgpr_write_agpr_mfma_read_srcb
 body:             |
   bb.0:
     $agpr8 = V_ACCVGPR_WRITE_B32 killed $vgpr0, implicit $exec
     $agpr4_agpr5_agpr6_agpr7 = V_MFMA_F32_4X4X1F32 killed $vgpr1, killed $agpr8, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec
 ...
 ---
 
 # GCN-LABEL: name: accvgpr_write_agpr_accvgpr_read
 # GCN:      V_ACCVGPR_WRITE_B32
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: V_ACCVGPR_READ_B32
 name:            accvgpr_write_agpr_accvgpr_read
 body:             |
   bb.0:
     $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr0, implicit $exec
     $vgpr1 = V_ACCVGPR_READ_B32 killed $agpr0, implicit $exec
 ...
 ---
 
 # GCN-LABEL: name: vcmpx_write_exec_mfma
 # GCN:      V_CMPX_EQ_I32_e32
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 3
 # GCN-NEXT: V_MFMA
 name:            vcmpx_write_exec_mfma
 body:             |
   bb.0:
     implicit $exec, implicit $vcc = V_CMPX_EQ_I32_e32 $vgpr0, $vgpr1, implicit $exec
     $agpr4_agpr5_agpr6_agpr7 = V_MFMA_F32_4X4X1F32 killed $agpr8, killed $vgpr1, killed $agpr0_agpr1_agpr2_agpr3, 0, 0, 0, implicit $mode, implicit $exec
 ...
 ---
 
 # GCN-LABEL: name: vcmpx_write_exec_accvgpr_write
 # GCN:      V_CMPX_EQ_I32_e32
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 3
 # GCN-NEXT: V_ACCVGPR_WRITE_B32
 name:            vcmpx_write_exec_accvgpr_write
 body:             |
   bb.0:
     implicit $exec, implicit $vcc = V_CMPX_EQ_I32_e32 $vgpr0, $vgpr1, implicit $exec
     $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr2, implicit $exec
 ...
 ---
 
 # GCN-LABEL: name: accvgpr_read_write_vgpr_load
 # GCN:      V_ACCVGPR_READ_B32
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 1
 # GCN-NEXT: FLAT_LOAD_DWORD
 name:            accvgpr_read_write_vgpr_load
 body:             |
   bb.0:
     $vgpr0 = V_ACCVGPR_READ_B32 killed $agpr0, implicit $exec
     $vgpr3 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
 ...
 ---
 
 # GCN-LABEL: name: accvgpr_read_write_vgpr_ds_permute
 # GCN:      V_ACCVGPR_READ_B32
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 1
 # GCN-NEXT: DS_PERMUTE_B32
 name:            accvgpr_read_write_vgpr_ds_permute
 body:             |
   bb.0:
     $vgpr0 = V_ACCVGPR_READ_B32 killed $agpr0, implicit $exec
     $vgpr1 = DS_PERMUTE_B32 $vgpr0, $vgpr1, 0, implicit $exec
 ...
 ---
 
 # GCN-LABEL: name: accvgpr_read_write_vgpr_flat_load
 # GCN:      V_ACCVGPR_READ_B32
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 1
 # GCN-NEXT: FLAT_LOAD_DWORD
 name:            accvgpr_read_write_vgpr_flat_load
 body:             |
   bb.0:
     $vgpr0 = V_ACCVGPR_READ_B32 killed $agpr0, implicit $exec
     $vgpr4 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
 ...
 ---
 
 # GCN-LABEL: name: accvgpr_read_write_vgpr_buffer_store
 # GCN:      V_ACCVGPR_READ_B32
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 1
 # GCN-NEXT: BUFFER_STORE_DWORD_OFFSET
 name:            accvgpr_read_write_vgpr_buffer_store
 body:             |
   bb.0:
     $vgpr0 = V_ACCVGPR_READ_B32 killed $agpr0, implicit $exec
     BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, 0, implicit $exec
 ...
 ---
 
 # GCN-LABEL: name: accvgpr_read_write_vgpr_store
 # GCN:      V_ACCVGPR_READ_B32
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 1
 # GCN-NEXT: DS_WRITE_B32
 name:            accvgpr_read_write_vgpr_store
 body:             |
   bb.0:
     $vgpr0 = V_ACCVGPR_READ_B32 killed $agpr0, implicit $exec
     DS_WRITE_B32 $vgpr0, $vgpr1, 0, 0, implicit $m0, implicit $exec
 ...
 ---
bb.0:
     $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr2, implicit $exec
     $vgpr4 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
 ...
 ---
 
 # GCN-LABEL: name: valu_write_vgpr_accvgpr_read_load_2_and_3_depend
 # GCN:      V_MOV_B32
 # GCN-NEXT: V_ACCVGPR_READ_B32
-# GCN-NEXT: S_NOP 0
-# GCN-NEXT: S_NOP 0
+# GCN-NEXT: S_NOP 1
 # GCN-NEXT: FLAT_LOAD_DWORD
 name:            valu_write_vgpr_accvgpr_read_load_2_and_3_depend
 body:             |
   bb.0:
     $vgpr0 = V_MOV_B32_e32 1, implicit $exec
     $vgpr2 = V_ACCVGPR_READ_B32 killed $agpr0, implicit $exec
     $vgpr4 = FLAT_LOAD_DWORD $vgpr2_vgpr3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
 ...
 ---

llvm/test/CodeGen/AMDGPU/vmem-vcc-hazard.mir

 # RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass post-RA-hazard-rec -o - %s | FileCheck -check-prefix=GCN %s
 
 # GCN-LABEL: name: vmem_vcc_fallthrough
 # GCN:      bb.1:
-# GCN-NEXT: S_NOP
-# GCN-NEXT: S_NOP
-# GCN-NEXT: S_NOP
-# GCN-NEXT: S_NOP
-# GCN-NEXT: S_NOP
+# GCN-NEXT: S_NOP 4
 # GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
 ---
 name:            vmem_vcc_fallthrough
 body:             |
   bb.0:
     successors: %bb.1
 
     $sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
     $vgpr0 = IMPLICIT_DEF
     $vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
 
   bb.1:
     $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, 0, implicit $exec
 ...
 # GCN-LABEL: name: vmem_vcc_branch_to_next
 # GCN:      bb.1:
-# GCN-NEXT: S_NOP
-# GCN-NEXT: S_NOP
-# GCN-NEXT: S_NOP
-# GCN-NEXT: S_NOP
+# GCN-NEXT: S_NOP 3
 # GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
 ---
 name:            vmem_vcc_branch_to_next
 body:             |
   bb.0:
     successors: %bb.1
 
     $sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
bb.0:
     $vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
     S_NOP 4
 
   bb.1:
     $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, 0, implicit $exec
 ...
 # GCN-LABEL: name: vmem_vcc_branch_around
 # GCN:      bb.2:
-# GCN-NEXT: S_NOP
-# GCN-NEXT: S_NOP
-# GCN-NEXT: S_NOP
-# GCN-NEXT: S_NOP
+# GCN-NEXT: S_NOP 3
 # GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
 ---
 name:            vmem_vcc_branch_around
 body:             |
   bb.0:
     successors: %bb.2
 
     $sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
     $vgpr0 = IMPLICIT_DEF
     $vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
     S_BRANCH %bb.2
 
   bb.1:
     successors: %bb.2
 
     S_NOP 0
     S_NOP 0
     S_NOP 0
     S_NOP 0
 
   bb.2:
     $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, 0, implicit $exec
 ...
 # GCN-LABEL: name: vmem_vcc_branch_backedge
-# GCN:      S_NOP
-# GCN-NEXT: S_NOP
-# GCN-NEXT: S_NOP
-# GCN-NEXT: S_NOP
+# GCN:      S_NOP 3
 # GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
 ---
 name:            vmem_vcc_branch_backedge
 body:             |
   bb.0:
     successors: %bb.1
 
     $vgpr0 = IMPLICIT_DEF
     $sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
     $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, 0, implicit $exec
 
   bb.1:
     $vgpr0 = IMPLICIT_DEF
     $vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
     S_BRANCH %bb.0
 ...
 # GCN-LABEL: name: vmem_vcc_min_of_two
 # GCN:      bb.2:
-# GCN-NEXT: S_NOP
-# GCN-NEXT: S_NOP
-# GCN-NEXT: S_NOP
-# GCN-NEXT: S_NOP
-# GCN-NEXT: S_NOP
+# GCN-NEXT: S_NOP 4
 # GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
 ---
 name:            vmem_vcc_min_of_two
 body:             |
   bb.0:
     successors: %bb.2
 
     $sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
     $vgpr0 = IMPLICIT_DEF
     $vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
     S_NOP 0
     S_BRANCH %bb.2
 
   bb.1:
     successors: %bb.2
 
     $vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
 
   bb.2:
     $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, 0, implicit $exec
 ...
 # GCN-LABEL: name: vmem_vcc_self_loop
-# GCN:      S_NOP
-# GCN-NEXT: S_NOP
-# GCN-NEXT: S_NOP
-# GCN-NEXT: S_NOP
+# GCN:      S_NOP 3
 # GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
 ---
 name:            vmem_vcc_self_loop
 body:             |
   bb.0:
     successors: %bb.0
 
     $vgpr0 = IMPLICIT_DEF
     $sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
     $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, 0, implicit $exec
     $vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
     S_BRANCH %bb.0
 ...
 # GCN-LABEL: name: vmem_vcc_min_of_two_self_loop1
 # GCN:      bb.1:
 # GCN:      $sgpr0 = S_MOV_B32 0
-# GCN-NEXT: S_NOP
-# GCN-NEXT: S_NOP
-# GCN-NEXT: S_NOP
-# GCN-NEXT: S_NOP
+# GCN-NEXT: S_NOP 3
 # GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
 ---
 name:            vmem_vcc_min_of_two_self_loop1
 body:             |
   bb.0:
     successors: %bb.1
 
     $sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF
     $vgpr0 = IMPLICIT_DEF
     $vgpr1 = V_ADDC_U32_e32 $vgpr0, $vgpr0, implicit-def $vcc, implicit $vcc, implicit $exec
 
   bb.1:
     successors: %bb.1
 
     $sgpr0 = S_MOV_B32 0
     $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $vcc_lo, 0, 0, 0, 0, 0, 0, implicit $exec
     $vgpr1 = V_ADDC_U32_e32 $vgpr1, $vgpr1, implicit-def $vcc, implicit $vcc, implicit $exec
     S_BRANCH %bb.1
 ...
 # GCN-LABEL: name: vmem_vcc_min_of_two_self_loop2
 # GCN:      bb.1:
 # GCN:      $sgpr0 = S_MOV_B32 0
-# GCN-NEXT: S_NOP
-# GCN-NEXT: S_NOP
-# GCN-NEXT: S_NOP
+# GCN-NEXT: S_NOP 2
 # GCN-NEXT: BUFFER_LOAD_DWORD_OFFEN
 ---
 name:            vmem_vcc_min_of_two_self_loop2
 body:             |
   bb.0:
     successors: %bb.1
 
     $sgpr0_sgpr1_sgpr2_sgpr3 = IMPLICIT_DEF