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Differential D89076

AMDGPU: Update AMDHSA code object version handling
ClosedPublic

Authored by kzhuravl on Oct 8 2020, 3:27 PM.

Details

Reviewers
arsenm
kerbowa
scott.linder
t-tye
• espindola
jhenderson
MaskRay
Commits
rG3fdf3b153960: AMDGPU: Update AMDHSA code object version handling
Summary
  • Define AMDHSA's code object versions in ELF.h
  • Introduce --amdhsa-code-object-version=<num> option, where <num> can be 2, 3
  • Remove code-object-v3 subtarget feature
  • Mark -m[no-]code-object-v3 options as deprecated and substitute deprecated options with new ones

Diff Detail

Event Timeline

kzhuravl created this revision.Oct 8 2020, 3:27 PM
Herald added a reviewer: • espindola. · View Herald TranscriptOct 8 2020, 3:27 PM
Herald added a reviewer: jhenderson. · View Herald Transcript
Herald added a reviewer: MaskRay. · View Herald Transcript
Herald added a project: Restricted Project. · View Herald Transcript
Herald added subscribers: dang, rupprecht, jfb and 9 others. · View Herald Transcript
kzhuravl requested review of this revision.Oct 8 2020, 3:27 PM
Herald added a subscriber: wdng. · View Herald TranscriptOct 8 2020, 3:27 PM
scott.linder added inline comments.Oct 8 2020, 5:00 PM
clang/docs/ClangCommandLineReference.rst
179

There seem to be a lot of unrelated changes here; does the patch need to be rebased? Or are you just cleaning up the whole file?

If the latter could these be in a separate diff?

t-tye accepted this revision.Oct 8 2020, 5:29 PM
t-tye added inline comments.
clang/docs/ClangCommandLineReference.rst
179

Many changes in this file are the result of earlier changes in the options.td file not updating this file with the build result. So suggest submitting a review for updating this file without the code version changes first. Then the changes to this file in this review will just be code object version related.

Otherwise I think all the changes in this review are related to cleaning up the handling of the existing V2 and V3 code object formats in preparation for submitting the V4 code object changes.

llvm/docs/AMDGPUUsage.rst
910–911

Were there also cleanup in the ELF section that describes the e_flags and defines the usage of the new --amdhsa-code-object-version option?

This revision is now accepted and ready to land.Oct 8 2020, 5:29 PM
t-tye requested changes to this revision.Oct 8 2020, 5:30 PM

LGTM except the two suggestions.

This revision now requires changes to proceed.Oct 8 2020, 5:30 PM
kzhuravl marked 3 inline comments as done.Oct 8 2020, 5:38 PM
kzhuravl added inline comments.
clang/docs/ClangCommandLineReference.rst
179

Re-generating the whole file, as I think it might have been stale.

llvm/docs/AMDGPUUsage.rst
910–911

I think doc updates will come in a separate patch as we discussed earlier today.

kzhuravl updated this revision to Diff 297107.Oct 8 2020, 7:08 PM
kzhuravl marked an inline comment as done.

Address review feedback:

  • Regenerate docs in separate change
t-tye accepted this revision.Oct 8 2020, 7:25 PM

LGTM Requested changes will happen in a separate patch.

This revision is now accepted and ready to land.Oct 8 2020, 7:25 PM
MaskRay added inline comments.Oct 8 2020, 7:39 PM
clang/include/clang/Driver/Options.td
2464–2468

Does this still need m_amdgpu_Features_Group?

t-tye added inline comments.Oct 8 2020, 7:53 PM
clang/include/clang/Driver/Options.td
2464–2469

Would it be worth stating that the replacement option is "-mllvm --amdhsa-code-object-version=2" and "-mllvm --amdhsa-code-object-version=3" respectively?

kzhuravl marked 2 inline comments as done.Oct 8 2020, 8:00 PM
kzhuravl added inline comments.
clang/include/clang/Driver/Options.td
2464–2468

I changed it to m_Group on purpose. This way -target-feature +/-code-object-v3 is not added to cc1, which results in a warning:

'+/-code-object-v3' is not a recognized feature for this target (ignoring feature)

Since we removed this feature from our be.

2464–2469

Replacement option is already stated in the deprecated warning, in case this option is used. Do we really want to put the same suggestion here? I quickly glanced through ClangCommandLineReference.rst and did not see similar cases.

Closed by commit rG3fdf3b153960: AMDGPU: Update AMDHSA code object version handling (authored by kzhuravl). · Explain WhyOct 14 2020, 10:04 AM
This revision was automatically updated to reflect the committed changes.
kzhuravl marked 2 inline comments as done.
kzhuravl added a commit: rG3fdf3b153960: AMDGPU: Update AMDHSA code object version handling.
Herald added a project: Restricted Project. · View Herald TranscriptOct 14 2020, 10:04 AM
Herald added subscribers: cfe-commits, dexonsmith, steven_wu. · View Herald Transcript
dexonsmith removed a subscriber: dexonsmith.Oct 19 2020, 5:49 PM

Revision Contents

PathSize
clang/
docs/
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include/
clang/
Driver/
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lib/
Driver/
ToolChains/
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test/
Driver/
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lld/
test/
ELF/
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lto/
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llvm/
docs/
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include/
llvm/
BinaryFormat/
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lib/
Target/
AMDGPU/
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AsmParser/
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MCTargetDesc/
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Utils/
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CodeGen/
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Diff 298175

clang/docs/ClangCommandLineReference.rst

Show First 20 Lines • Show All 170 Lines • ▼ Show 20 Lines
.. option:: -dependency-dot <arg> .. option:: -dependency-dot <arg>
Filename to write DOT-formatted header dependencies to Filename to write DOT-formatted header dependencies to
.. option:: -dependency-file <arg> .. option:: -dependency-file <arg>
Filename (or -) to write dependency output to Filename (or -) to write dependency output to
.. option:: -dsym-dir<dir> .. option:: -dsym-dir<dir>
scott.linderUnsubmitted
Done
ReplyInline Actions

There seem to be a lot of unrelated changes here; does the patch need to be rebased? Or are you just cleaning up the whole file?

If the latter could these be in a separate diff?

scott.linder: There seem to be a lot of unrelated changes here; does the patch need to be rebased? Or are you…
t-tyeUnsubmitted
Done
ReplyInline Actions

Many changes in this file are the result of earlier changes in the options.td file not updating this file with the build result. So suggest submitting a review for updating this file without the code version changes first. Then the changes to this file in this review will just be code object version related.

Otherwise I think all the changes in this review are related to cleaning up the handling of the existing V2 and V3 code object formats in preparation for submitting the V4 code object changes.

t-tye: Many changes in this file are the result of earlier changes in the options.td file not updating…
kzhuravlAuthorUnsubmitted
Done
ReplyInline Actions

Re-generating the whole file, as I think it might have been stale.

kzhuravl: Re-generating the whole file, as I think it might have been stale.
Directory to output dSYM's (if any) to Directory to output dSYM's (if any) to
.. option:: -dumpmachine .. option:: -dumpmachine
.. option:: -dumpversion .. option:: -dumpversion
.. option:: --dyld-prefix=<arg>, --dyld-prefix <arg> .. option:: --dyld-prefix=<arg>, --dyld-prefix <arg>
▲ Show 20 Lines • Show All 2,744 Lines • ▼ Show 20 Lines
.. option:: -msve-vector-bits=<arg> .. option:: -msve-vector-bits=<arg>
Specify the size in bits of an SVE vector register. Defaults to the vector length agnostic value of "scalable". (AArch64 only) Specify the size in bits of an SVE vector register. Defaults to the vector length agnostic value of "scalable". (AArch64 only)
AMDGPU AMDGPU
------ ------
.. option:: -mcode-object-v3, -mno-code-object-v3 .. option:: -mcode-object-v3, -mno-code-object-v3
Enable code object v3 (AMDGPU only) Legacy option to specify code object v3 (AMDGPU only)
.. option:: -mcumode, -mno-cumode .. option:: -mcumode, -mno-cumode
CU wavefront execution mode is used (AMDGPU only) CU wavefront execution mode is used (AMDGPU only)
.. option:: -msram-ecc, -mno-sram-ecc .. option:: -msram-ecc, -mno-sram-ecc
Enable SRAM ECC (AMDGPU only) Enable SRAM ECC (AMDGPU only)
▲ Show 20 Lines • Show All 801 Lines • Show Last 20 Lines

clang/include/clang/Driver/Options.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 2,455 Lines • ▼ Show 20 Lines
def mtail_call : Flag<["-"], "mtail-call">, Group<m_wasm_Features_Group>; def mtail_call : Flag<["-"], "mtail-call">, Group<m_wasm_Features_Group>;
def mno_tail_call : Flag<["-"], "mno-tail-call">, Group<m_wasm_Features_Group>; def mno_tail_call : Flag<["-"], "mno-tail-call">, Group<m_wasm_Features_Group>;
def mreference_types : Flag<["-"], "mreference-types">, Group<m_wasm_Features_Group>; def mreference_types : Flag<["-"], "mreference-types">, Group<m_wasm_Features_Group>;
def mno_reference_types : Flag<["-"], "mno-reference-types">, Group<m_wasm_Features_Group>; def mno_reference_types : Flag<["-"], "mno-reference-types">, Group<m_wasm_Features_Group>;
def mexec_model_EQ : Joined<["-"], "mexec-model=">, Group<m_wasm_Features_Driver_Group>, def mexec_model_EQ : Joined<["-"], "mexec-model=">, Group<m_wasm_Features_Driver_Group>,
Values<"command,reactor">, Values<"command,reactor">,
HelpText<"Execution model (WebAssembly only)">; HelpText<"Execution model (WebAssembly only)">;
def mcode_object_v3 : Flag<["-"], "mcode-object-v3">, Group<m_amdgpu_Features_Group>, def mcode_object_v3_legacy : Flag<["-"], "mcode-object-v3">, Group<m_Group>,
HelpText<"Enable code object v3 (AMDGPU only)">; HelpText<"Legacy option to specify code object v3 (AMDGPU only)">;
def mno_code_object_v3 : Flag<["-"], "mno-code-object-v3">, Group<m_amdgpu_Features_Group>, def mno_code_object_v3_legacy : Flag<["-"], "mno-code-object-v3">, Group<m_Group>,
HelpText<"Disable code object v3 (AMDGPU only)">; HelpText<"Legacy option to specify code object v2 (AMDGPU only)">;
MaskRayUnsubmitted
Done
ReplyInline Actions

Does this still need m_amdgpu_Features_Group?

MaskRay: Does this still need `m_amdgpu_Features_Group`?
kzhuravlAuthorUnsubmitted
Done
ReplyInline Actions

I changed it to m_Group on purpose. This way -target-feature +/-code-object-v3 is not added to cc1, which results in a warning:

'+/-code-object-v3' is not a recognized feature for this target (ignoring feature)

Since we removed this feature from our be.

kzhuravl: I changed it to m_Group on purpose. This way -target-feature +/-code-object-v3 is not added to…
def mxnack : Flag<["-"], "mxnack">, Group<m_amdgpu_Features_Group>, def mxnack : Flag<["-"], "mxnack">, Group<m_amdgpu_Features_Group>,
t-tyeUnsubmitted
Done
ReplyInline Actions

Would it be worth stating that the replacement option is "-mllvm --amdhsa-code-object-version=2" and "-mllvm --amdhsa-code-object-version=3" respectively?

t-tye: Would it be worth stating that the replacement option is "-mllvm --amdhsa-code-object…
kzhuravlAuthorUnsubmitted
Done
ReplyInline Actions

Replacement option is already stated in the deprecated warning, in case this option is used. Do we really want to put the same suggestion here? I quickly glanced through ClangCommandLineReference.rst and did not see similar cases.

kzhuravl: Replacement option is already stated in the deprecated warning, in case this option is used. Do…
HelpText<"Enable XNACK (AMDGPU only)">; HelpText<"Enable XNACK (AMDGPU only)">;
def mno_xnack : Flag<["-"], "mno-xnack">, Group<m_amdgpu_Features_Group>, def mno_xnack : Flag<["-"], "mno-xnack">, Group<m_amdgpu_Features_Group>,
HelpText<"Disable XNACK (AMDGPU only)">; HelpText<"Disable XNACK (AMDGPU only)">;
def msram_ecc : Flag<["-"], "msram-ecc">, Group<m_amdgpu_Features_Group>, def msram_ecc : Flag<["-"], "msram-ecc">, Group<m_amdgpu_Features_Group>,
HelpText<"Enable SRAM ECC (AMDGPU only)">; HelpText<"Enable SRAM ECC (AMDGPU only)">;
def mno_sram_ecc : Flag<["-"], "mno-sram-ecc">, Group<m_amdgpu_Features_Group>, def mno_sram_ecc : Flag<["-"], "mno-sram-ecc">, Group<m_amdgpu_Features_Group>,
HelpText<"Disable SRAM ECC (AMDGPU only)">; HelpText<"Disable SRAM ECC (AMDGPU only)">;
▲ Show 20 Lines • Show All 2,478 Lines • Show Last 20 Lines

clang/lib/Driver/ToolChains/AMDGPU.cpp

Show First 20 Lines • Show All 519 Lines • ▼ Show 20 Linesvoid AMDGPUToolChain::addClangTargetOptions(
// Default to "hidden" visibility, as object level linking will not be // Default to "hidden" visibility, as object level linking will not be
// supported for the foreseeable future. // supported for the foreseeable future.
if (!DriverArgs.hasArg(options::OPT_fvisibility_EQ, if (!DriverArgs.hasArg(options::OPT_fvisibility_EQ,
options::OPT_fvisibility_ms_compat)) { options::OPT_fvisibility_ms_compat)) {
CC1Args.push_back("-fvisibility"); CC1Args.push_back("-fvisibility");
CC1Args.push_back("hidden"); CC1Args.push_back("hidden");
CC1Args.push_back("-fapply-global-visibility-to-externs"); CC1Args.push_back("-fapply-global-visibility-to-externs");
} }
if (DriverArgs.hasArg(options::OPT_mcode_object_v3_legacy)) {
getDriver().Diag(diag::warn_drv_deprecated_arg) << "-mcode-object-v3" <<
"-mllvm --amdhsa-code-object-version=3";
CC1Args.push_back("-mllvm");
CC1Args.push_back("--amdhsa-code-object-version=3");
}
if (DriverArgs.hasArg(options::OPT_mno_code_object_v3_legacy)) {
getDriver().Diag(diag::warn_drv_deprecated_arg) << "-mno-code-object-v3" <<
"-mllvm --amdhsa-code-object-version=2";
CC1Args.push_back("-mllvm");
CC1Args.push_back("--amdhsa-code-object-version=2");
}
} }
StringRef StringRef
AMDGPUToolChain::getGPUArch(const llvm::opt::ArgList &DriverArgs) const { AMDGPUToolChain::getGPUArch(const llvm::opt::ArgList &DriverArgs) const {
return getProcessorFromTargetID( return getProcessorFromTargetID(
getTriple(), DriverArgs.getLastArgValue(options::OPT_mcpu_EQ)); getTriple(), DriverArgs.getLastArgValue(options::OPT_mcpu_EQ));
} }
▲ Show 20 Lines • Show All 107 Lines • Show Last 20 Lines

clang/test/Driver/amdgpu-features.c

// RUN: %clang -### -target amdgcn -mcpu=gfx700 -mcode-object-v3 %s 2>&1 | FileCheck --check-prefix=CODE-OBJECT-V3 %s // RUN: %clang -### -target amdgcn-amd-amdhsa -mcpu=gfx700 -mcode-object-v3 %s 2>&1 | FileCheck --check-prefix=CODE-OBJECT-V3 %s
// CODE-OBJECT-V3: "-target-feature" "+code-object-v3" // CODE-OBJECT-V3: warning: argument '-mcode-object-v3' is deprecated, use '-mllvm --amdhsa-code-object-version=3' instead [-Wdeprecated]
// CODE-OBJECT-V3: "-mllvm" "--amdhsa-code-object-version=3"
// RUN: %clang -### -target amdgcn -mcpu=gfx700 -mno-code-object-v3 %s 2>&1 | FileCheck --check-prefix=NO-CODE-OBJECT-V3 %s
// NO-CODE-OBJECT-V3: "-target-feature" "-code-object-v3" // RUN: %clang -### -target amdgcn-amd-amdhsa amdgcn -mcpu=gfx700 -mno-code-object-v3 %s 2>&1 | FileCheck --check-prefix=NO-CODE-OBJECT-V3 %s
// NO-CODE-OBJECT-V3: warning: argument '-mno-code-object-v3' is deprecated, use '-mllvm --amdhsa-code-object-version=2' instead [-Wdeprecated]
// NO-CODE-OBJECT-V3: "-mllvm" "--amdhsa-code-object-version=2"
// RUN: %clang -### -target amdgcn-amdhsa -mcpu=gfx900:xnack+ %s 2>&1 | FileCheck --check-prefix=XNACK %s // RUN: %clang -### -target amdgcn-amdhsa -mcpu=gfx900:xnack+ %s 2>&1 | FileCheck --check-prefix=XNACK %s
// XNACK: "-target-feature" "+xnack" // XNACK: "-target-feature" "+xnack"
// RUN: %clang -### -target amdgcn-amdpal -mcpu=gfx900:xnack- %s 2>&1 | FileCheck --check-prefix=NO-XNACK %s // RUN: %clang -### -target amdgcn-amdpal -mcpu=gfx900:xnack- %s 2>&1 | FileCheck --check-prefix=NO-XNACK %s
// NO-XNACK: "-target-feature" "-xnack" // NO-XNACK: "-target-feature" "-xnack"
// RUN: %clang -### -target amdgcn-mesa3d -mcpu=gfx908:sram-ecc+ %s 2>&1 | FileCheck --check-prefix=SRAM-ECC %s // RUN: %clang -### -target amdgcn-mesa3d -mcpu=gfx908:sram-ecc+ %s 2>&1 | FileCheck --check-prefix=SRAM-ECC %s
Show All 22 Lines

lld/test/ELF/amdgpu-abi-version-err.s

# REQUIRES: amdgpu # REQUIRES: amdgpu
# RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj %s -o %t-0.o # RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj %s -o %t-0.o
# RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-code-object-v3 -filetype=obj %s -o %t-1.o # RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=2 -filetype=obj %s -o %t-1.o
# RUN: not ld.lld -shared %t-0.o %t-1.o -o /dev/null 2>&1 | FileCheck %s # RUN: not ld.lld -shared %t-0.o %t-1.o -o /dev/null 2>&1 | FileCheck %s
# CHECK: ld.lld: error: incompatible ABI version: {{.*}}-1.o # CHECK: ld.lld: error: incompatible ABI version: {{.*}}-1.o
.text .text
s_nop 0x0 s_nop 0x0
s_endpgm s_endpgm

lld/test/ELF/amdgpu-elf-flags-err.s

# REQUIRES: amdgpu # REQUIRES: amdgpu
# RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx802 -mattr=-code-object-v3 -filetype=obj %S/Inputs/amdgpu-kernel-0.s -o %t-0.o # RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx802 --amdhsa-code-object-version=2 -filetype=obj %S/Inputs/amdgpu-kernel-0.s -o %t-0.o
# RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx803 -mattr=-code-object-v3 -filetype=obj %S/Inputs/amdgpu-kernel-1.s -o %t-1.o # RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx803 --amdhsa-code-object-version=2 -filetype=obj %S/Inputs/amdgpu-kernel-1.s -o %t-1.o
# RUN: not ld.lld -shared %t-0.o %t-1.o -o /dev/null 2>&1 | FileCheck %s # RUN: not ld.lld -shared %t-0.o %t-1.o -o /dev/null 2>&1 | FileCheck %s
# CHECK: error: incompatible e_flags: {{.*}}-1.o # CHECK: error: incompatible e_flags: {{.*}}-1.o

lld/test/ELF/amdgpu-elf-flags.s

# REQUIRES: amdgpu # REQUIRES: amdgpu
# RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx803 -mattr=-code-object-v3 -filetype=obj %S/Inputs/amdgpu-kernel-0.s -o %t-0.o # RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx803 --amdhsa-code-object-version=2 -filetype=obj %S/Inputs/amdgpu-kernel-0.s -o %t-0.o
# RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx803 -mattr=-code-object-v3 -filetype=obj %S/Inputs/amdgpu-kernel-1.s -o %t-1.o # RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx803 --amdhsa-code-object-version=2 -filetype=obj %S/Inputs/amdgpu-kernel-1.s -o %t-1.o
# RUN: ld.lld -shared %t-0.o %t-1.o -o %t.so # RUN: ld.lld -shared %t-0.o %t-1.o -o %t.so
# RUN: llvm-readobj --file-headers %t.so | FileCheck %s # RUN: llvm-readobj --file-headers %t.so | FileCheck %s
# CHECK: Flags [ # CHECK: Flags [
# CHECK: EF_AMDGPU_MACH_AMDGCN_GFX803 (0x2A) # CHECK: EF_AMDGPU_MACH_AMDGCN_GFX803 (0x2A)
# CHECK: ] # CHECK: ]

lld/test/ELF/amdgpu-kernels.s

# REQUIRES: amdgpu # REQUIRES: amdgpu
# RUN: llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri -mattr=-code-object-v3 %s -o %t.o # RUN: llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 %s -o %t.o
# RUN: ld.lld -shared %t.o -o %t # RUN: ld.lld -shared %t.o -o %t
# RUN: llvm-readobj --sections --symbols -l %t | FileCheck %s # RUN: llvm-readobj --sections --symbols -l %t | FileCheck %s
.hsa_code_object_version 1,0 .hsa_code_object_version 1,0
.hsa_code_object_isa 7,0,0,"AMD","AMDGPU" .hsa_code_object_isa 7,0,0,"AMD","AMDGPU"
.text .text
.globl kernel0 .globl kernel0
▲ Show 20 Lines • Show All 46 Lines • Show Last 20 Lines

lld/test/ELF/lto/amdgcn-oses.ll

; REQUIRES: amdgpu ; REQUIRES: amdgpu
; RUN: split-file %s %t ; RUN: split-file %s %t
; RUN: llvm-as %t/amdhsa.ll -o %t/amdhsa.o ; RUN: llvm-as %t/amdhsa.ll -o %t/amdhsa.o
; RUN: ld.lld %t/amdhsa.o -o %t/amdhsa.so ; RUN: ld.lld %t/amdhsa.o -o %t/amdhsa.so
; RUN: llvm-readobj --file-headers %t/amdhsa.so | FileCheck %s --check-prefixes=GCN,AMDHSA ; RUN: llvm-readobj --file-headers %t/amdhsa.so | FileCheck %s --check-prefixes=GCN,AMDHSA
; RUN: llvm-as %t/amdpal.ll -o %t/amdpal.o ; RUN: llvm-as %t/amdpal.ll -o %t/amdpal.o
; RUN: ld.lld %t/amdpal.o -o %t/amdpal.so ; RUN: ld.lld %t/amdpal.o -o %t/amdpal.so
; RUN: llvm-readobj --file-headers %t/amdpal.so | FileCheck %s --check-prefixes=GCN,AMDPAL ; RUN: llvm-readobj --file-headers %t/amdpal.so | FileCheck %s --check-prefixes=GCN,NON-AMDHSA,AMDPAL
; RUN: llvm-as %t/mesa3d.ll -o %t/mesa3d.o ; RUN: llvm-as %t/mesa3d.ll -o %t/mesa3d.o
; RUN: ld.lld %t/mesa3d.o -o %t/mesa3d.so ; RUN: ld.lld %t/mesa3d.o -o %t/mesa3d.so
; RUN: llvm-readobj --file-headers %t/mesa3d.so | FileCheck %s --check-prefixes=GCN,MESA3D ; RUN: llvm-readobj --file-headers %t/mesa3d.so | FileCheck %s --check-prefixes=GCN,NON-AMDHSA,MESA3D
; AMDHSA: OS/ABI: AMDGPU_HSA (0x40) ; AMDHSA: OS/ABI: AMDGPU_HSA (0x40)
; AMDHSA: ABIVersion: 1
; AMDPAL: OS/ABI: AMDGPU_PAL (0x41) ; AMDPAL: OS/ABI: AMDGPU_PAL (0x41)
; MESA3D: OS/ABI: AMDGPU_MESA3D (0x42) ; MESA3D: OS/ABI: AMDGPU_MESA3D (0x42)
; GCN: ABIVersion: 0 ; NON-AMDHSA: ABIVersion: 0
;--- amdhsa.ll ;--- amdhsa.ll
target triple = "amdgcn-amd-amdhsa" target triple = "amdgcn-amd-amdhsa"
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5" target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
define void @_start() { define void @_start() {
ret void ret void
} }
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llvm/docs/AMDGPUUsage.rst

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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must be generated after the ``name`` field to ensure the ``desc`` field is 4 must be generated after the ``name`` field to ensure the ``desc`` field is 4
byte aligned. In addition, minimal zero-byte padding must be generated to byte aligned. In addition, minimal zero-byte padding must be generated to
ensure the ``desc`` field size is a multiple of 4 bytes. The ``sh_addralign`` ensure the ``desc`` field size is a multiple of 4 bytes. The ``sh_addralign``
field of the ``.note`` section must be at least 4 to indicate at least 8 byte field of the ``.note`` section must be at least 4 to indicate at least 8 byte
alignment. alignment.
.. _amdgpu-note-records-v2: .. _amdgpu-note-records-v2:
Code Object V2 Note Records (-mattr=-code-object-v3) Code Object V2 Note Records (--amdhsa-code-object-version=2)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
t-tyeUnsubmitted
Done
ReplyInline Actions

Were there also cleanup in the ELF section that describes the e_flags and defines the usage of the new --amdhsa-code-object-version option?

t-tye: Were there also cleanup in the ELF section that describes the e_flags and defines the usage of…
kzhuravlAuthorUnsubmitted
Done
ReplyInline Actions

I think doc updates will come in a separate patch as we discussed earlier today.

kzhuravl: I think doc updates will come in a separate patch as we discussed earlier today.
.. warning:: Code Object V2 is not the default code object version emitted by .. warning:: Code Object V2 is not the default code object version emitted by
this version of LLVM. For a description of the notes generated with the this version of LLVM. For a description of the notes generated with the
default configuration (Code Object V3) see :ref:`amdgpu-note-records-v3`. default configuration (Code Object V3) see :ref:`amdgpu-note-records-v3`.
The AMDGPU backend code object uses the following ELF note record in the The AMDGPU backend code object uses the following ELF note record in the
``.note`` section when compiling for Code Object V2 (-mattr=-code-object-v3). ``.note`` section when compiling for Code Object
V2 (--amdhsa-code-object-version=2).
Additional note records may be present, but any which are not documented here Additional note records may be present, but any which are not documented here
are deprecated and should not be used. are deprecated and should not be used.
.. table:: AMDGPU Code Object V2 ELF Note Records .. table:: AMDGPU Code Object V2 ELF Note Records
:name: amdgpu-elf-note-records-table-v2 :name: amdgpu-elf-note-records-table-v2
===== ============================== ====================================== ===== ============================== ======================================
Show All 19 Lines``NT_AMD_AMDGPU_HSA_METADATA``
Specifies extensible metadata associated with the code objects executed on HSA Specifies extensible metadata associated with the code objects executed on HSA
[HSA]_ compatible runtimes such as AMD's ROCm [AMD-ROCm]_. It is required when [HSA]_ compatible runtimes such as AMD's ROCm [AMD-ROCm]_. It is required when
the target triple OS is ``amdhsa`` (see :ref:`amdgpu-target-triples`). See the target triple OS is ``amdhsa`` (see :ref:`amdgpu-target-triples`). See
:ref:`amdgpu-amdhsa-code-object-metadata-v2` for the syntax of the code :ref:`amdgpu-amdhsa-code-object-metadata-v2` for the syntax of the code
object metadata string. object metadata string.
.. _amdgpu-note-records-v3: .. _amdgpu-note-records-v3:
Code Object V3 Note Records (-mattr=+code-object-v3) Code Object V3 Note Records (--amdhsa-code-object-version=3)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The AMDGPU backend code object uses the following ELF note record in the The AMDGPU backend code object uses the following ELF note record in the
``.note`` section when compiling for Code Object V3 (-mattr=+code-object-v3). ``.note`` section when compiling for Code Object V3
(--amdhsa-code-object-version=3).
Additional note records may be present, but any which are not documented here Additional note records may be present, but any which are not documented here
are deprecated and should not be used. are deprecated and should not be used.
.. table:: AMDGPU Code Object V3 ELF Note Records .. table:: AMDGPU Code Object V3 ELF Note Records
:name: amdgpu-elf-note-records-table-v3 :name: amdgpu-elf-note-records-table-v3
======== ============================== ====================================== ======== ============================== ======================================
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``amdhsa`` (see :ref:`amdgpu-target-triples`). It must contain the minimum ``amdhsa`` (see :ref:`amdgpu-target-triples`). It must contain the minimum
information necessary to support the ROCM kernel queries. For example, the information necessary to support the ROCM kernel queries. For example, the
segment sizes needed in a dispatch packet. In addition, a high-level language segment sizes needed in a dispatch packet. In addition, a high-level language
runtime may require other information to be included. For example, the AMD runtime may require other information to be included. For example, the AMD
OpenCL runtime records kernel argument information. OpenCL runtime records kernel argument information.
.. _amdgpu-amdhsa-code-object-metadata-v2: .. _amdgpu-amdhsa-code-object-metadata-v2:
Code Object V2 Metadata (-mattr=-code-object-v3) Code Object V2 Metadata (--amdhsa-code-object-version=2)
++++++++++++++++++++++++++++++++++++++++++++++++ ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
.. warning:: Code Object V2 is not the default code object version emitted by .. warning:: Code Object V2 is not the default code object version emitted by
this version of LLVM. For a description of the metadata generated with the this version of LLVM. For a description of the metadata generated with the
default configuration (Code Object V3) see default configuration (Code Object V3) see
:ref:`amdgpu-amdhsa-code-object-metadata-v3`. :ref:`amdgpu-amdhsa-code-object-metadata-v3`.
Code object V2 metadata is specified by the ``NT_AMD_AMDGPU_METADATA`` note Code object V2 metadata is specified by the ``NT_AMD_AMDGPU_METADATA`` note
record (see :ref:`amdgpu-note-records-v2`). record (see :ref:`amdgpu-note-records-v2`).
▲ Show 20 Lines • Show All 403 Lines • ▼ Show 20 Lines "NumSpilledVGPRs" integer Number of stores from
a vector register to a vector register to
a register allocator a register allocator
created spill created spill
location. location.
============================ ============== ========= ===================== ============================ ============== ========= =====================
.. _amdgpu-amdhsa-code-object-metadata-v3: .. _amdgpu-amdhsa-code-object-metadata-v3:
Code Object V3 Metadata (-mattr=+code-object-v3) Code Object V3 Metadata (--amdhsa-code-object-version=3)
++++++++++++++++++++++++++++++++++++++++++++++++ ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Code object V3 metadata is specified by the ``NT_AMDGPU_METADATA`` note record Code object V3 metadata is specified by the ``NT_AMDGPU_METADATA`` note record
(see :ref:`amdgpu-note-records-v3`). (see :ref:`amdgpu-note-records-v3`).
The metadata is represented as Message Pack formatted binary data (see The metadata is represented as Message Pack formatted binary data (see
[MsgPack]_). The top level is a Message Pack map that includes the [MsgPack]_). The top level is a Message Pack map that includes the
keys defined in table keys defined in table
:ref:`amdgpu-amdhsa-code-object-metadata-map-table-v3` and referenced :ref:`amdgpu-amdhsa-code-object-metadata-map-table-v3` and referenced
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For full list of supported instructions, refer to "Vector ALU instructions". For full list of supported instructions, refer to "Vector ALU instructions".
.. TODO:: .. TODO::
Remove once we switch to code object v3 by default. Remove once we switch to code object v3 by default.
.. _amdgpu-amdhsa-assembler-predefined-symbols-v2: .. _amdgpu-amdhsa-assembler-predefined-symbols-v2:
Code Object V2 Predefined Symbols (-mattr=-code-object-v3) Code Object V2 Predefined Symbols (--amdhsa-code-object-version=2)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. warning:: Code Object V2 is not the default code object version emitted by .. warning:: Code Object V2 is not the default code object version emitted by
this version of LLVM. For a description of the predefined symbols available this version of LLVM. For a description of the predefined symbols available
with the default configuration (Code Object V3) see with the default configuration (Code Object V3) see
:ref:`amdgpu-amdhsa-assembler-predefined-symbols-v3`. :ref:`amdgpu-amdhsa-assembler-predefined-symbols-v3`.
The AMDGPU assembler defines and updates some symbols automatically. These The AMDGPU assembler defines and updates some symbols automatically. These
symbols do not affect code generation. symbols do not affect code generation.
Show All 39 Lines
:ref:`amdgpu-amdhsa-assembler-directive-amdgpu_hsa_kernel` directive is :ref:`amdgpu-amdhsa-assembler-directive-amdgpu_hsa_kernel` directive is
encountered. At each instruction, if the current value of this symbol is less encountered. At each instruction, if the current value of this symbol is less
than or equal to the maximum VGPR number explicitly referenced within that than or equal to the maximum VGPR number explicitly referenced within that
instruction then the symbol value is updated to equal that SGPR number plus instruction then the symbol value is updated to equal that SGPR number plus
one. one.
.. _amdgpu-amdhsa-assembler-directives-v2: .. _amdgpu-amdhsa-assembler-directives-v2:
Code Object V2 Directives (-mattr=-code-object-v3) Code Object V2 Directives (--amdhsa-code-object-version=2)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. warning:: Code Object V2 is not the default code object version emitted by .. warning:: Code Object V2 is not the default code object version emitted by
this version of LLVM. For a description of the directives supported with this version of LLVM. For a description of the directives supported with
the default configuration (Code Object V3) see the default configuration (Code Object V3) see
:ref:`amdgpu-amdhsa-assembler-directives-v3`. :ref:`amdgpu-amdhsa-assembler-directives-v3`.
AMDGPU ABI defines auxiliary data in output code object. In assembly source, AMDGPU ABI defines auxiliary data in output code object. In assembly source,
one can specify them with assembler directives. one can specify them with assembler directives.
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The *.amd_kernel_code_t* directive must be placed immediately after the The *.amd_kernel_code_t* directive must be placed immediately after the
function label and before any instructions. function label and before any instructions.
For a full list of amd_kernel_code_t keys, refer to AMDGPU ABI document, For a full list of amd_kernel_code_t keys, refer to AMDGPU ABI document,
comments in lib/Target/AMDGPU/AmdKernelCodeT.h and test/CodeGen/AMDGPU/hsa.s. comments in lib/Target/AMDGPU/AmdKernelCodeT.h and test/CodeGen/AMDGPU/hsa.s.
.. _amdgpu-amdhsa-assembler-example-v2: .. _amdgpu-amdhsa-assembler-example-v2:
Code Object V2 Example Source Code (-mattr=-code-object-v3) Code Object V2 Example Source Code (--amdhsa-code-object-version=2)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
.. warning:: Code Object V2 is not the default code object version emitted by .. warning:: Code Object V2 is not the default code object version emitted by
this version of LLVM. For a description of the directives supported with this version of LLVM. For a description of the directives supported with
the default configuration (Code Object V3) see the default configuration (Code Object V3) see
:ref:`amdgpu-amdhsa-assembler-example-v3`. :ref:`amdgpu-amdhsa-assembler-example-v3`.
Here is an example of a minimal assembly source file, defining one HSA kernel: Here is an example of a minimal assembly source file, defining one HSA kernel:
Show All 28 Lines hello_world:
v_mov_b32 v2, s1 v_mov_b32 v2, s1
flat_store_dword v[1:2], v0 flat_store_dword v[1:2], v0
s_endpgm s_endpgm
.Lfunc_end0: .Lfunc_end0:
.size hello_world, .Lfunc_end0-hello_world .size hello_world, .Lfunc_end0-hello_world
.. _amdgpu-amdhsa-assembler-predefined-symbols-v3: .. _amdgpu-amdhsa-assembler-predefined-symbols-v3:
Code Object V3 Predefined Symbols (-mattr=+code-object-v3) Code Object V3 Predefined Symbols (--amdhsa-code-object-version=3)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The AMDGPU assembler defines and updates some symbols automatically. These The AMDGPU assembler defines and updates some symbols automatically. These
symbols do not affect code generation. symbols do not affect code generation.
.amdgcn.gfx_generation_number .amdgcn.gfx_generation_number
+++++++++++++++++++++++++++++ +++++++++++++++++++++++++++++
Set to the GFX major generation number of the target being assembled for. For Set to the GFX major generation number of the target being assembled for. For
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May be used to set the `.amdhsa_next_free_spgr` directive in May be used to set the `.amdhsa_next_free_spgr` directive in
:ref:`amdhsa-kernel-directives-table`. :ref:`amdhsa-kernel-directives-table`.
May be set at any time, e.g. manually set to zero at the start of each kernel. May be set at any time, e.g. manually set to zero at the start of each kernel.
.. _amdgpu-amdhsa-assembler-directives-v3: .. _amdgpu-amdhsa-assembler-directives-v3:
Code Object V3 Directives (-mattr=+code-object-v3) Code Object V3 Directives (--amdhsa-code-object-version=3)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Directives which begin with ``.amdgcn`` are valid for all ``amdgcn`` Directives which begin with ``.amdgcn`` are valid for all ``amdgcn``
architecture processors, and are not OS-specific. Directives which begin with architecture processors, and are not OS-specific. Directives which begin with
``.amdhsa`` are specific to ``amdgcn`` architecture processors when the ``.amdhsa`` are specific to ``amdgcn`` architecture processors when the
``amdhsa`` OS is specified. See :ref:`amdgpu-target-triples` and ``amdhsa`` OS is specified. See :ref:`amdgpu-target-triples` and
:ref:`amdgpu-processors`. :ref:`amdgpu-processors`.
.amdgcn_target <target> .amdgcn_target <target>
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The contents must be in the [YAML]_ markup format, with the same structure and The contents must be in the [YAML]_ markup format, with the same structure and
semantics described in :ref:`amdgpu-amdhsa-code-object-metadata-v3`. semantics described in :ref:`amdgpu-amdhsa-code-object-metadata-v3`.
This directive is terminated by an ``.end_amdgpu_metadata`` directive. This directive is terminated by an ``.end_amdgpu_metadata`` directive.
.. _amdgpu-amdhsa-assembler-example-v3: .. _amdgpu-amdhsa-assembler-example-v3:
Code Object V3 Example Source Code (-mattr=+code-object-v3) Code Object V3 Example Source Code (--amdhsa-code-object-version=3)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Here is an example of a minimal assembly source file, defining one HSA kernel: Here is an example of a minimal assembly source file, defining one HSA kernel:
.. code:: .. code::
:number-lines: :number-lines:
.amdgcn_target "amdgcn-amd-amdhsa--gfx900+xnack" // optional .amdgcn_target "amdgcn-amd-amdhsa--gfx900+xnack" // optional
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llvm/include/llvm/BinaryFormat/ELF.h

Show First 20 Lines • Show All 354 Lines • ▼ Show 20 Linesenum {
ELFOSABI_AMDGPU_MESA3D = 66, // AMD GCN GPUs (GFX6+) for MESA runtime ELFOSABI_AMDGPU_MESA3D = 66, // AMD GCN GPUs (GFX6+) for MESA runtime
ELFOSABI_ARM = 97, // ARM ELFOSABI_ARM = 97, // ARM
ELFOSABI_C6000_ELFABI = 64, // Bare-metal TMS320C6000 ELFOSABI_C6000_ELFABI = 64, // Bare-metal TMS320C6000
ELFOSABI_C6000_LINUX = 65, // Linux TMS320C6000 ELFOSABI_C6000_LINUX = 65, // Linux TMS320C6000
ELFOSABI_STANDALONE = 255, // Standalone (embedded) application ELFOSABI_STANDALONE = 255, // Standalone (embedded) application
ELFOSABI_LAST_ARCH = 255 // Last Architecture-specific OS ABI ELFOSABI_LAST_ARCH = 255 // Last Architecture-specific OS ABI
}; };
// AMDGPU OS ABI Version identification.
enum {
// ELFABIVERSION_AMDGPU_HSA_V1 does not exist because OS ABI identification
// was never defined for V1.
ELFABIVERSION_AMDGPU_HSA_V2 = 0,
ELFABIVERSION_AMDGPU_HSA_V3 = 1,
};
#define ELF_RELOC(name, value) name = value, #define ELF_RELOC(name, value) name = value,
// X86_64 relocations. // X86_64 relocations.
enum { enum {
#include "ELFRelocs/x86_64.def" #include "ELFRelocs/x86_64.def"
}; };
// i386 relocations. // i386 relocations.
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llvm/lib/Target/AMDGPU/AMDGPU.td

Show First 20 Lines • Show All 646 Lines • ▼ Show 20 Lines
def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature < def FeatureAutoWaitcntBeforeBarrier : SubtargetFeature <
"auto-waitcnt-before-barrier", "auto-waitcnt-before-barrier",
"AutoWaitcntBeforeBarrier", "AutoWaitcntBeforeBarrier",
"true", "true",
"Hardware automatically inserts waitcnt before barrier" "Hardware automatically inserts waitcnt before barrier"
>; >;
def FeatureCodeObjectV3 : SubtargetFeature <
"code-object-v3",
"CodeObjectV3",
"true",
"Generate code object version 3"
>;
def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range", def FeatureTrigReducedRange : SubtargetFeature<"trig-reduced-range",
"HasTrigReducedRange", "HasTrigReducedRange",
"true", "true",
"Requires use of fract on arguments to trig instructions" "Requires use of fract on arguments to trig instructions"
>; >;
// Dummy feature used to disable assembler instructions. // Dummy feature used to disable assembler instructions.
def FeatureDisable : SubtargetFeature<"", def FeatureDisable : SubtargetFeature<"",
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class FeatureSet<list<SubtargetFeature> Features_> { class FeatureSet<list<SubtargetFeature> Features_> {
list<SubtargetFeature> Features = Features_; list<SubtargetFeature> Features = Features_;
} }
def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands, def FeatureISAVersion6_0_0 : FeatureSet<[FeatureSouthernIslands,
FeatureFastFMAF32, FeatureFastFMAF32,
HalfRate64Ops, HalfRate64Ops,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureDoesNotSupportXNACK, FeatureDoesNotSupportXNACK]>;
FeatureCodeObjectV3]>;
def FeatureISAVersion6_0_1 : FeatureSet< def FeatureISAVersion6_0_1 : FeatureSet<
[FeatureSouthernIslands, [FeatureSouthernIslands,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureDoesNotSupportXNACK, FeatureDoesNotSupportXNACK]>;
FeatureCodeObjectV3]>;
def FeatureISAVersion6_0_2 : FeatureSet< def FeatureISAVersion6_0_2 : FeatureSet<
[FeatureSouthernIslands, [FeatureSouthernIslands,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureDoesNotSupportXNACK, FeatureDoesNotSupportXNACK]>;
FeatureCodeObjectV3]>;
def FeatureISAVersion7_0_0 : FeatureSet< def FeatureISAVersion7_0_0 : FeatureSet<
[FeatureSeaIslands, [FeatureSeaIslands,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureDoesNotSupportXNACK, FeatureDoesNotSupportXNACK]>;
FeatureCodeObjectV3]>;
def FeatureISAVersion7_0_1 : FeatureSet< def FeatureISAVersion7_0_1 : FeatureSet<
[FeatureSeaIslands, [FeatureSeaIslands,
HalfRate64Ops, HalfRate64Ops,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureFastFMAF32, FeatureFastFMAF32,
FeatureDoesNotSupportXNACK, FeatureDoesNotSupportXNACK]>;
FeatureCodeObjectV3]>;
def FeatureISAVersion7_0_2 : FeatureSet< def FeatureISAVersion7_0_2 : FeatureSet<
[FeatureSeaIslands, [FeatureSeaIslands,
FeatureLDSBankCount16, FeatureLDSBankCount16,
FeatureFastFMAF32, FeatureFastFMAF32,
FeatureDoesNotSupportXNACK, FeatureDoesNotSupportXNACK]>;
FeatureCodeObjectV3]>;
def FeatureISAVersion7_0_3 : FeatureSet< def FeatureISAVersion7_0_3 : FeatureSet<
[FeatureSeaIslands, [FeatureSeaIslands,
FeatureLDSBankCount16, FeatureLDSBankCount16,
FeatureDoesNotSupportXNACK, FeatureDoesNotSupportXNACK]>;
FeatureCodeObjectV3]>;
def FeatureISAVersion7_0_4 : FeatureSet< def FeatureISAVersion7_0_4 : FeatureSet<
[FeatureSeaIslands, [FeatureSeaIslands,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureDoesNotSupportXNACK, FeatureDoesNotSupportXNACK]>;
FeatureCodeObjectV3]>;
def FeatureISAVersion7_0_5 : FeatureSet< def FeatureISAVersion7_0_5 : FeatureSet<
[FeatureSeaIslands, [FeatureSeaIslands,
FeatureLDSBankCount16, FeatureLDSBankCount16,
FeatureDoesNotSupportXNACK, FeatureDoesNotSupportXNACK]>;
FeatureCodeObjectV3]>;
def FeatureISAVersion8_0_1 : FeatureSet< def FeatureISAVersion8_0_1 : FeatureSet<
[FeatureVolcanicIslands, [FeatureVolcanicIslands,
FeatureFastFMAF32, FeatureFastFMAF32,
HalfRate64Ops, HalfRate64Ops,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureXNACK, FeatureXNACK,
FeatureUnpackedD16VMem, FeatureUnpackedD16VMem]>;
FeatureCodeObjectV3]>;
def FeatureISAVersion8_0_2 : FeatureSet< def FeatureISAVersion8_0_2 : FeatureSet<
[FeatureVolcanicIslands, [FeatureVolcanicIslands,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureSGPRInitBug, FeatureSGPRInitBug,
FeatureUnpackedD16VMem, FeatureUnpackedD16VMem,
FeatureDoesNotSupportXNACK, FeatureDoesNotSupportXNACK]>;
FeatureCodeObjectV3]>;
def FeatureISAVersion8_0_3 : FeatureSet< def FeatureISAVersion8_0_3 : FeatureSet<
[FeatureVolcanicIslands, [FeatureVolcanicIslands,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureUnpackedD16VMem, FeatureUnpackedD16VMem,
FeatureDoesNotSupportXNACK, FeatureDoesNotSupportXNACK]>;
FeatureCodeObjectV3]>;
def FeatureISAVersion8_0_5 : FeatureSet< def FeatureISAVersion8_0_5 : FeatureSet<
[FeatureVolcanicIslands, [FeatureVolcanicIslands,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureSGPRInitBug, FeatureSGPRInitBug,
FeatureUnpackedD16VMem, FeatureUnpackedD16VMem,
FeatureDoesNotSupportXNACK, FeatureDoesNotSupportXNACK]>;
FeatureCodeObjectV3]>;
def FeatureISAVersion8_1_0 : FeatureSet< def FeatureISAVersion8_1_0 : FeatureSet<
[FeatureVolcanicIslands, [FeatureVolcanicIslands,
FeatureLDSBankCount16, FeatureLDSBankCount16,
FeatureXNACK, FeatureXNACK,
FeatureCodeObjectV3,
FeatureImageStoreD16Bug, FeatureImageStoreD16Bug,
FeatureImageGather4D16Bug]>; FeatureImageGather4D16Bug]>;
def FeatureISAVersion9_0_0 : FeatureSet< def FeatureISAVersion9_0_0 : FeatureSet<
[FeatureGFX9, [FeatureGFX9,
FeatureMadMixInsts, FeatureMadMixInsts,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureCodeObjectV3,
FeatureDoesNotSupportXNACK, FeatureDoesNotSupportXNACK,
FeatureDoesNotSupportSRAMECC, FeatureDoesNotSupportSRAMECC,
FeatureImageGather4D16Bug]>; FeatureImageGather4D16Bug]>;
def FeatureISAVersion9_0_2 : FeatureSet< def FeatureISAVersion9_0_2 : FeatureSet<
[FeatureGFX9, [FeatureGFX9,
FeatureMadMixInsts, FeatureMadMixInsts,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureXNACK, FeatureXNACK,
FeatureDoesNotSupportSRAMECC, FeatureDoesNotSupportSRAMECC,
FeatureCodeObjectV3,
FeatureImageGather4D16Bug]>; FeatureImageGather4D16Bug]>;
def FeatureISAVersion9_0_4 : FeatureSet< def FeatureISAVersion9_0_4 : FeatureSet<
[FeatureGFX9, [FeatureGFX9,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureFmaMixInsts, FeatureFmaMixInsts,
FeatureDoesNotSupportXNACK, FeatureDoesNotSupportXNACK,
FeatureDoesNotSupportSRAMECC, FeatureDoesNotSupportSRAMECC,
FeatureCodeObjectV3,
FeatureImageGather4D16Bug]>; FeatureImageGather4D16Bug]>;
def FeatureISAVersion9_0_6 : FeatureSet< def FeatureISAVersion9_0_6 : FeatureSet<
[FeatureGFX9, [FeatureGFX9,
HalfRate64Ops, HalfRate64Ops,
FeatureFmaMixInsts, FeatureFmaMixInsts,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureDLInsts, FeatureDLInsts,
FeatureDot1Insts, FeatureDot1Insts,
FeatureDot2Insts, FeatureDot2Insts,
FeatureDoesNotSupportXNACK, FeatureDoesNotSupportXNACK,
FeatureCodeObjectV3,
FeatureImageGather4D16Bug]>; FeatureImageGather4D16Bug]>;
def FeatureISAVersion9_0_8 : FeatureSet< def FeatureISAVersion9_0_8 : FeatureSet<
[FeatureGFX9, [FeatureGFX9,
HalfRate64Ops, HalfRate64Ops,
FeatureFmaMixInsts, FeatureFmaMixInsts,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureDLInsts, FeatureDLInsts,
FeatureDot1Insts, FeatureDot1Insts,
FeatureDot2Insts, FeatureDot2Insts,
FeatureDot3Insts, FeatureDot3Insts,
FeatureDot4Insts, FeatureDot4Insts,
FeatureDot5Insts, FeatureDot5Insts,
FeatureDot6Insts, FeatureDot6Insts,
FeatureMAIInsts, FeatureMAIInsts,
FeaturePkFmacF16Inst, FeaturePkFmacF16Inst,
FeatureAtomicFaddInsts, FeatureAtomicFaddInsts,
FeatureSRAMECC, FeatureSRAMECC,
FeatureMFMAInlineLiteralBug, FeatureMFMAInlineLiteralBug,
FeatureCodeObjectV3,
FeatureImageGather4D16Bug]>; FeatureImageGather4D16Bug]>;
def FeatureISAVersion9_0_9 : FeatureSet< def FeatureISAVersion9_0_9 : FeatureSet<
[FeatureGFX9, [FeatureGFX9,
FeatureMadMixInsts, FeatureMadMixInsts,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureXNACK, FeatureXNACK,
FeatureCodeObjectV3,
FeatureImageGather4D16Bug]>; FeatureImageGather4D16Bug]>;
// TODO: Organize more features into groups. // TODO: Organize more features into groups.
def FeatureGroup { def FeatureGroup {
// Bugs present on gfx10.1. // Bugs present on gfx10.1.
list<SubtargetFeature> GFX10_1_Bugs = [ list<SubtargetFeature> GFX10_1_Bugs = [
FeatureVcmpxPermlaneHazard, FeatureVcmpxPermlaneHazard,
FeatureVMEMtoScalarWriteHazard, FeatureVMEMtoScalarWriteHazard,
Show All 17 Lines !listconcat(FeatureGroup.GFX10_1_Bugs,
FeatureScalarStores, FeatureScalarStores,
FeatureScalarAtomics, FeatureScalarAtomics,
FeatureScalarFlatScratchInsts, FeatureScalarFlatScratchInsts,
FeatureGetWaveIdInst, FeatureGetWaveIdInst,
FeatureSMemTimeInst, FeatureSMemTimeInst,
FeatureMadMacF32Insts, FeatureMadMacF32Insts,
FeatureDsSrc2Insts, FeatureDsSrc2Insts,
FeatureLdsMisalignedBug, FeatureLdsMisalignedBug,
FeatureDoesNotSupportXNACK, FeatureDoesNotSupportXNACK])>;
FeatureCodeObjectV3])>;
def FeatureISAVersion10_1_1 : FeatureSet< def FeatureISAVersion10_1_1 : FeatureSet<
!listconcat(FeatureGroup.GFX10_1_Bugs, !listconcat(FeatureGroup.GFX10_1_Bugs,
[FeatureGFX10, [FeatureGFX10,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureDLInsts, FeatureDLInsts,
FeatureDot1Insts, FeatureDot1Insts,
FeatureDot2Insts, FeatureDot2Insts,
FeatureDot5Insts, FeatureDot5Insts,
FeatureDot6Insts, FeatureDot6Insts,
FeatureNSAEncoding, FeatureNSAEncoding,
FeatureWavefrontSize32, FeatureWavefrontSize32,
FeatureScalarStores, FeatureScalarStores,
FeatureScalarAtomics, FeatureScalarAtomics,
FeatureScalarFlatScratchInsts, FeatureScalarFlatScratchInsts,
FeatureGetWaveIdInst, FeatureGetWaveIdInst,
FeatureSMemTimeInst, FeatureSMemTimeInst,
FeatureMadMacF32Insts, FeatureMadMacF32Insts,
FeatureDsSrc2Insts, FeatureDsSrc2Insts,
FeatureLdsMisalignedBug, FeatureLdsMisalignedBug,
FeatureDoesNotSupportXNACK, FeatureDoesNotSupportXNACK])>;
FeatureCodeObjectV3])>;
def FeatureISAVersion10_1_2 : FeatureSet< def FeatureISAVersion10_1_2 : FeatureSet<
!listconcat(FeatureGroup.GFX10_1_Bugs, !listconcat(FeatureGroup.GFX10_1_Bugs,
[FeatureGFX10, [FeatureGFX10,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureDLInsts, FeatureDLInsts,
FeatureDot1Insts, FeatureDot1Insts,
FeatureDot2Insts, FeatureDot2Insts,
FeatureDot5Insts, FeatureDot5Insts,
FeatureDot6Insts, FeatureDot6Insts,
FeatureNSAEncoding, FeatureNSAEncoding,
FeatureWavefrontSize32, FeatureWavefrontSize32,
FeatureScalarStores, FeatureScalarStores,
FeatureScalarAtomics, FeatureScalarAtomics,
FeatureScalarFlatScratchInsts, FeatureScalarFlatScratchInsts,
FeatureGetWaveIdInst, FeatureGetWaveIdInst,
FeatureSMemTimeInst, FeatureSMemTimeInst,
FeatureMadMacF32Insts, FeatureMadMacF32Insts,
FeatureDsSrc2Insts, FeatureDsSrc2Insts,
FeatureLdsMisalignedBug, FeatureLdsMisalignedBug,
FeatureDoesNotSupportXNACK, FeatureDoesNotSupportXNACK])>;
FeatureCodeObjectV3])>;
def FeatureISAVersion10_3_0 : FeatureSet< def FeatureISAVersion10_3_0 : FeatureSet<
[FeatureGFX10, [FeatureGFX10,
FeatureGFX10_BEncoding, FeatureGFX10_BEncoding,
FeatureGFX10_3Insts, FeatureGFX10_3Insts,
FeatureLDSBankCount32, FeatureLDSBankCount32,
FeatureDLInsts, FeatureDLInsts,
FeatureDot1Insts, FeatureDot1Insts,
FeatureDot2Insts, FeatureDot2Insts,
FeatureDot5Insts, FeatureDot5Insts,
FeatureDot6Insts, FeatureDot6Insts,
FeatureNSAEncoding, FeatureNSAEncoding,
FeatureWavefrontSize32, FeatureWavefrontSize32,
FeatureDoesNotSupportXNACK, FeatureDoesNotSupportXNACK]>;
FeatureCodeObjectV3]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def AMDGPUInstrInfo : InstrInfo { def AMDGPUInstrInfo : InstrInfo {
let guessInstructionProperties = 1; let guessInstructionProperties = 1;
let noNamedPositionallyEncodedOperands = 1; let noNamedPositionallyEncodedOperands = 1;
} }
▲ Show 20 Lines • Show All 309 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

Show First 20 Lines • Show All 102 Lines • ▼ Show 20 Lines TargetRegistry::RegisterAsmPrinter(getTheAMDGPUTarget(),
llvm::createR600AsmPrinterPass); llvm::createR600AsmPrinterPass);
TargetRegistry::RegisterAsmPrinter(getTheGCNTarget(), TargetRegistry::RegisterAsmPrinter(getTheGCNTarget(),
createAMDGPUAsmPrinterPass); createAMDGPUAsmPrinterPass);
} }
AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM, AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
std::unique_ptr<MCStreamer> Streamer) std::unique_ptr<MCStreamer> Streamer)
: AsmPrinter(TM, std::move(Streamer)) { : AsmPrinter(TM, std::move(Streamer)) {
if (IsaInfo::hasCodeObjectV3(getGlobalSTI())) if (TM.getTargetTriple().getOS() == Triple::AMDHSA) {
HSAMetadataStream.reset(new MetadataStreamerV3()); if (isHsaAbiVersion2(getGlobalSTI())) {
else
HSAMetadataStream.reset(new MetadataStreamerV2()); HSAMetadataStream.reset(new MetadataStreamerV2());
} else {
HSAMetadataStream.reset(new MetadataStreamerV3());
}
}
} }
StringRef AMDGPUAsmPrinter::getPassName() const { StringRef AMDGPUAsmPrinter::getPassName() const {
return "AMDGPU Assembly Printer"; return "AMDGPU Assembly Printer";
} }
const MCSubtargetInfo *AMDGPUAsmPrinter::getGlobalSTI() const { const MCSubtargetInfo *AMDGPUAsmPrinter::getGlobalSTI() const {
return TM.getMCSubtargetInfo(); return TM.getMCSubtargetInfo();
} }
AMDGPUTargetStreamer* AMDGPUAsmPrinter::getTargetStreamer() const { AMDGPUTargetStreamer* AMDGPUAsmPrinter::getTargetStreamer() const {
if (!OutStreamer) if (!OutStreamer)
return nullptr; return nullptr;
return static_cast<AMDGPUTargetStreamer*>(OutStreamer->getTargetStreamer()); return static_cast<AMDGPUTargetStreamer*>(OutStreamer->getTargetStreamer());
} }
void AMDGPUAsmPrinter::emitStartOfAsmFile(Module &M) { void AMDGPUAsmPrinter::emitStartOfAsmFile(Module &M) {
if (IsaInfo::hasCodeObjectV3(getGlobalSTI())) { if (isHsaAbiVersion3(getGlobalSTI())) {
std::string ExpectedTarget; std::string ExpectedTarget;
raw_string_ostream ExpectedTargetOS(ExpectedTarget); raw_string_ostream ExpectedTargetOS(ExpectedTarget);
IsaInfo::streamIsaVersion(getGlobalSTI(), ExpectedTargetOS); IsaInfo::streamIsaVersion(getGlobalSTI(), ExpectedTargetOS);
getTargetStreamer()->EmitDirectiveAMDGCNTarget(ExpectedTarget); getTargetStreamer()->EmitDirectiveAMDGCNTarget(ExpectedTarget);
} }
if (TM.getTargetTriple().getOS() != Triple::AMDHSA && if (TM.getTargetTriple().getOS() != Triple::AMDHSA &&
TM.getTargetTriple().getOS() != Triple::AMDPAL) TM.getTargetTriple().getOS() != Triple::AMDPAL)
return; return;
if (TM.getTargetTriple().getOS() == Triple::AMDHSA) if (TM.getTargetTriple().getOS() == Triple::AMDHSA)
HSAMetadataStream->begin(M); HSAMetadataStream->begin(M);
if (TM.getTargetTriple().getOS() == Triple::AMDPAL) if (TM.getTargetTriple().getOS() == Triple::AMDPAL)
getTargetStreamer()->getPALMetadata()->readFromIR(M); getTargetStreamer()->getPALMetadata()->readFromIR(M);
if (IsaInfo::hasCodeObjectV3(getGlobalSTI())) if (isHsaAbiVersion3(getGlobalSTI()))
return; return;
// HSA emits NT_AMDGPU_HSA_CODE_OBJECT_VERSION for code objects v2. // HSA emits NT_AMDGPU_HSA_CODE_OBJECT_VERSION for code objects v2.
if (TM.getTargetTriple().getOS() == Triple::AMDHSA) if (TM.getTargetTriple().getOS() == Triple::AMDHSA)
getTargetStreamer()->EmitDirectiveHSACodeObjectVersion(2, 1); getTargetStreamer()->EmitDirectiveHSACodeObjectVersion(2, 1);
// HSA and PAL emit NT_AMDGPU_HSA_ISA for code objects v2. // HSA and PAL emit NT_AMDGPU_HSA_ISA for code objects v2.
IsaVersion Version = getIsaVersion(getGlobalSTI()->getCPU()); IsaVersion Version = getIsaVersion(getGlobalSTI()->getCPU());
getTargetStreamer()->EmitDirectiveHSACodeObjectISA( getTargetStreamer()->EmitDirectiveHSACodeObjectISA(
Version.Major, Version.Minor, Version.Stepping, "AMD", "AMDGPU"); Version.Major, Version.Minor, Version.Stepping, "AMD", "AMDGPU");
} }
void AMDGPUAsmPrinter::emitEndOfAsmFile(Module &M) { void AMDGPUAsmPrinter::emitEndOfAsmFile(Module &M) {
// Following code requires TargetStreamer to be present. // Following code requires TargetStreamer to be present.
if (!getTargetStreamer()) if (!getTargetStreamer())
return; return;
if (!IsaInfo::hasCodeObjectV3(getGlobalSTI())) { if (TM.getTargetTriple().getOS() != Triple::AMDHSA ||
isHsaAbiVersion2(getGlobalSTI())) {
// Emit ISA Version (NT_AMD_AMDGPU_ISA). // Emit ISA Version (NT_AMD_AMDGPU_ISA).
std::string ISAVersionString; std::string ISAVersionString;
raw_string_ostream ISAVersionStream(ISAVersionString); raw_string_ostream ISAVersionStream(ISAVersionString);
IsaInfo::streamIsaVersion(getGlobalSTI(), ISAVersionStream); IsaInfo::streamIsaVersion(getGlobalSTI(), ISAVersionStream);
getTargetStreamer()->EmitISAVersion(ISAVersionStream.str()); getTargetStreamer()->EmitISAVersion(ISAVersionStream.str());
} }
// Emit HSA Metadata (NT_AMD_AMDGPU_HSA_METADATA). // Emit HSA Metadata (NT_AMD_AMDGPU_HSA_METADATA).
Show All 21 Lines
void AMDGPUAsmPrinter::emitFunctionBodyStart() { void AMDGPUAsmPrinter::emitFunctionBodyStart() {
const SIMachineFunctionInfo &MFI = *MF->getInfo<SIMachineFunctionInfo>(); const SIMachineFunctionInfo &MFI = *MF->getInfo<SIMachineFunctionInfo>();
if (!MFI.isEntryFunction()) if (!MFI.isEntryFunction())
return; return;
const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>(); const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
const Function &F = MF->getFunction(); const Function &F = MF->getFunction();
if (!STM.hasCodeObjectV3() && STM.isAmdHsaOrMesa(F) && if ((STM.isMesaKernel(F) || isHsaAbiVersion2(getGlobalSTI())) &&
(F.getCallingConv() == CallingConv::AMDGPU_KERNEL || (F.getCallingConv() == CallingConv::AMDGPU_KERNEL ||
F.getCallingConv() == CallingConv::SPIR_KERNEL)) { F.getCallingConv() == CallingConv::SPIR_KERNEL)) {
amd_kernel_code_t KernelCode; amd_kernel_code_t KernelCode;
getAmdKernelCode(KernelCode, CurrentProgramInfo, *MF); getAmdKernelCode(KernelCode, CurrentProgramInfo, *MF);
getTargetStreamer()->EmitAMDKernelCodeT(KernelCode); getTargetStreamer()->EmitAMDKernelCodeT(KernelCode);
} }
if (STM.isAmdHsaOS()) if (STM.isAmdHsaOS())
HSAMetadataStream->emitKernel(*MF, CurrentProgramInfo); HSAMetadataStream->emitKernel(*MF, CurrentProgramInfo);
} }
void AMDGPUAsmPrinter::emitFunctionBodyEnd() { void AMDGPUAsmPrinter::emitFunctionBodyEnd() {
const SIMachineFunctionInfo &MFI = *MF->getInfo<SIMachineFunctionInfo>(); const SIMachineFunctionInfo &MFI = *MF->getInfo<SIMachineFunctionInfo>();
if (!MFI.isEntryFunction()) if (!MFI.isEntryFunction())
return; return;
if (!IsaInfo::hasCodeObjectV3(getGlobalSTI()) || if (TM.getTargetTriple().getOS() != Triple::AMDHSA ||
TM.getTargetTriple().getOS() != Triple::AMDHSA) isHsaAbiVersion2(getGlobalSTI()))
return; return;
auto &Streamer = getTargetStreamer()->getStreamer(); auto &Streamer = getTargetStreamer()->getStreamer();
auto &Context = Streamer.getContext(); auto &Context = Streamer.getContext();
auto &ObjectFileInfo = *Context.getObjectFileInfo(); auto &ObjectFileInfo = *Context.getObjectFileInfo();
auto &ReadOnlySection = *ObjectFileInfo.getReadOnlySection(); auto &ReadOnlySection = *ObjectFileInfo.getReadOnlySection();
Streamer.PushSection(); Streamer.PushSection();
Show All 18 Lines getTargetStreamer()->EmitAmdhsaKernelDescriptor(
CurrentProgramInfo.FlatUsed), CurrentProgramInfo.FlatUsed),
CurrentProgramInfo.VCCUsed, CurrentProgramInfo.FlatUsed, CurrentProgramInfo.VCCUsed, CurrentProgramInfo.FlatUsed,
hasXNACK(STI)); hasXNACK(STI));
Streamer.PopSection(); Streamer.PopSection();
} }
void AMDGPUAsmPrinter::emitFunctionEntryLabel() { void AMDGPUAsmPrinter::emitFunctionEntryLabel() {
if (IsaInfo::hasCodeObjectV3(getGlobalSTI()) && if (TM.getTargetTriple().getOS() == Triple::AMDHSA &&
TM.getTargetTriple().getOS() == Triple::AMDHSA) { isHsaAbiVersion3(getGlobalSTI())) {
AsmPrinter::emitFunctionEntryLabel(); AsmPrinter::emitFunctionEntryLabel();
return; return;
} }
const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>(); const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>(); const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
if (MFI->isEntryFunction() && STM.isAmdHsaOrMesa(MF->getFunction())) { if (MFI->isEntryFunction() && STM.isAmdHsaOrMesa(MF->getFunction())) {
SmallString<128> SymbolName; SmallString<128> SymbolName;
▲ Show 20 Lines • Show All 1,109 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h

Show First 20 Lines • Show All 310 Lines • ▼ Show 20 Linesprotected:
// Possibly statically set by tablegen, but may want to be overridden. // Possibly statically set by tablegen, but may want to be overridden.
bool FastFMAF32; bool FastFMAF32;
bool FastDenormalF32; bool FastDenormalF32;
bool HalfRate64Ops; bool HalfRate64Ops;
// Dynamially set bits that enable features. // Dynamially set bits that enable features.
bool FlatForGlobal; bool FlatForGlobal;
bool AutoWaitcntBeforeBarrier; bool AutoWaitcntBeforeBarrier;
bool CodeObjectV3;
bool UnalignedScratchAccess; bool UnalignedScratchAccess;
bool UnalignedBufferAccess; bool UnalignedBufferAccess;
bool UnalignedAccessMode; bool UnalignedAccessMode;
bool HasApertureRegs; bool HasApertureRegs;
bool EnableXNACK; bool EnableXNACK;
bool DoesNotSupportXNACK; bool DoesNotSupportXNACK;
bool EnableCuMode; bool EnableCuMode;
bool TrapHandler; bool TrapHandler;
▲ Show 20 Lines • Show All 366 Lines • ▼ Show 20 Linespublic:
bool usePRTStrictNull() const { bool usePRTStrictNull() const {
return EnablePRTStrictNull; return EnablePRTStrictNull;
} }
bool hasAutoWaitcntBeforeBarrier() const { bool hasAutoWaitcntBeforeBarrier() const {
return AutoWaitcntBeforeBarrier; return AutoWaitcntBeforeBarrier;
} }
bool hasCodeObjectV3() const {
// FIXME: Need to add code object v3 support for mesa and pal.
return isAmdHsaOS() ? CodeObjectV3 : false;
}
bool hasUnalignedBufferAccess() const { bool hasUnalignedBufferAccess() const {
return UnalignedBufferAccess; return UnalignedBufferAccess;
} }
bool hasUnalignedScratchAccess() const { bool hasUnalignedScratchAccess() const {
return UnalignedScratchAccess; return UnalignedScratchAccess;
} }
▲ Show 20 Lines • Show All 701 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp

Show First 20 Lines • Show All 178 Lines • ▼ Show 20 LinesGCNSubtarget::GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
MaxPrivateElementSize(0), MaxPrivateElementSize(0),
FastFMAF32(false), FastFMAF32(false),
FastDenormalF32(false), FastDenormalF32(false),
HalfRate64Ops(false), HalfRate64Ops(false),
FlatForGlobal(false), FlatForGlobal(false),
AutoWaitcntBeforeBarrier(false), AutoWaitcntBeforeBarrier(false),
CodeObjectV3(false),
UnalignedScratchAccess(false), UnalignedScratchAccess(false),
UnalignedBufferAccess(false), UnalignedBufferAccess(false),
UnalignedAccessMode(false), UnalignedAccessMode(false),
HasApertureRegs(false), HasApertureRegs(false),
EnableXNACK(false), EnableXNACK(false),
DoesNotSupportXNACK(false), DoesNotSupportXNACK(false),
EnableCuMode(false), EnableCuMode(false),
▲ Show 20 Lines • Show All 732 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h

Show First 20 Lines • Show All 92 Lines • ▼ Show 20 Lines const FeatureBitset InlineFeatureIgnoreList = {
AMDGPU::FeatureUnalignedAccessMode, AMDGPU::FeatureUnalignedAccessMode,
AMDGPU::FeatureAutoWaitcntBeforeBarrier, AMDGPU::FeatureAutoWaitcntBeforeBarrier,
// Property of the kernel/environment which can't actually differ. // Property of the kernel/environment which can't actually differ.
AMDGPU::FeatureSGPRInitBug, AMDGPU::FeatureSGPRInitBug,
AMDGPU::FeatureXNACK, AMDGPU::FeatureXNACK,
AMDGPU::FeatureTrapHandler, AMDGPU::FeatureTrapHandler,
AMDGPU::FeatureCodeObjectV3,
// The default assumption needs to be ecc is enabled, but no directly // The default assumption needs to be ecc is enabled, but no directly
// exposed operations depend on it, so it can be safely inlined. // exposed operations depend on it, so it can be safely inlined.
AMDGPU::FeatureSRAMECC, AMDGPU::FeatureSRAMECC,
// Perf-tuning features // Perf-tuning features
AMDGPU::FeatureFastFMAF32, AMDGPU::FeatureFastFMAF32,
AMDGPU::HalfRate64Ops AMDGPU::HalfRate64Ops
▲ Show 20 Lines • Show All 197 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Show First 20 Lines • Show All 1,127 Lines • ▼ Show 20 Lines AMDGPUAsmParser(const MCSubtargetInfo &STI, MCAsmParser &_Parser,
{ {
// TODO: make those pre-defined variables read-only. // TODO: make those pre-defined variables read-only.
// Currently there is none suitable machinery in the core llvm-mc for this. // Currently there is none suitable machinery in the core llvm-mc for this.
// MCSymbol::isRedefinable is intended for another purpose, and // MCSymbol::isRedefinable is intended for another purpose, and
// AsmParser::parseDirectiveSet() cannot be specialized for specific target. // AsmParser::parseDirectiveSet() cannot be specialized for specific target.
AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU()); AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());
MCContext &Ctx = getContext(); MCContext &Ctx = getContext();
if (ISA.Major >= 6 && AMDGPU::IsaInfo::hasCodeObjectV3(&getSTI())) { if (ISA.Major >= 6 && isHsaAbiVersion3(&getSTI())) {
MCSymbol *Sym = MCSymbol *Sym =
Ctx.getOrCreateSymbol(Twine(".amdgcn.gfx_generation_number")); Ctx.getOrCreateSymbol(Twine(".amdgcn.gfx_generation_number"));
Sym->setVariableValue(MCConstantExpr::create(ISA.Major, Ctx)); Sym->setVariableValue(MCConstantExpr::create(ISA.Major, Ctx));
Sym = Ctx.getOrCreateSymbol(Twine(".amdgcn.gfx_generation_minor")); Sym = Ctx.getOrCreateSymbol(Twine(".amdgcn.gfx_generation_minor"));
Sym->setVariableValue(MCConstantExpr::create(ISA.Minor, Ctx)); Sym->setVariableValue(MCConstantExpr::create(ISA.Minor, Ctx));
Sym = Ctx.getOrCreateSymbol(Twine(".amdgcn.gfx_generation_stepping")); Sym = Ctx.getOrCreateSymbol(Twine(".amdgcn.gfx_generation_stepping"));
Sym->setVariableValue(MCConstantExpr::create(ISA.Stepping, Ctx)); Sym->setVariableValue(MCConstantExpr::create(ISA.Stepping, Ctx));
} else { } else {
MCSymbol *Sym = MCSymbol *Sym =
Ctx.getOrCreateSymbol(Twine(".option.machine_version_major")); Ctx.getOrCreateSymbol(Twine(".option.machine_version_major"));
Sym->setVariableValue(MCConstantExpr::create(ISA.Major, Ctx)); Sym->setVariableValue(MCConstantExpr::create(ISA.Major, Ctx));
Sym = Ctx.getOrCreateSymbol(Twine(".option.machine_version_minor")); Sym = Ctx.getOrCreateSymbol(Twine(".option.machine_version_minor"));
Sym->setVariableValue(MCConstantExpr::create(ISA.Minor, Ctx)); Sym->setVariableValue(MCConstantExpr::create(ISA.Minor, Ctx));
Sym = Ctx.getOrCreateSymbol(Twine(".option.machine_version_stepping")); Sym = Ctx.getOrCreateSymbol(Twine(".option.machine_version_stepping"));
Sym->setVariableValue(MCConstantExpr::create(ISA.Stepping, Ctx)); Sym->setVariableValue(MCConstantExpr::create(ISA.Stepping, Ctx));
} }
if (ISA.Major >= 6 && AMDGPU::IsaInfo::hasCodeObjectV3(&getSTI())) { if (ISA.Major >= 6 && isHsaAbiVersion3(&getSTI())) {
initializeGprCountSymbol(IS_VGPR); initializeGprCountSymbol(IS_VGPR);
initializeGprCountSymbol(IS_SGPR); initializeGprCountSymbol(IS_SGPR);
} else } else
KernelScope.initialize(getContext()); KernelScope.initialize(getContext());
} }
} }
bool hasXNACK() const { bool hasXNACK() const {
▲ Show 20 Lines • Show All 1,324 Lines • ▼ Show 20 LinesAMDGPUAsmParser::parseRegister(bool RestoreOnFailure) {
SMLoc StartLoc = Tok.getLoc(); SMLoc StartLoc = Tok.getLoc();
SMLoc EndLoc = Tok.getEndLoc(); SMLoc EndLoc = Tok.getEndLoc();
RegisterKind RegKind; RegisterKind RegKind;
unsigned Reg, RegNum, RegWidth; unsigned Reg, RegNum, RegWidth;
if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth)) { if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth)) {
return nullptr; return nullptr;
} }
if (AMDGPU::IsaInfo::hasCodeObjectV3(&getSTI())) { if (isHsaAbiVersion3(&getSTI())) {
if (!updateGprCountSymbols(RegKind, RegNum, RegWidth)) if (!updateGprCountSymbols(RegKind, RegNum, RegWidth))
return nullptr; return nullptr;
} else } else
KernelScope.usesRegister(RegKind, RegNum, RegWidth); KernelScope.usesRegister(RegKind, RegNum, RegWidth);
return AMDGPUOperand::CreateReg(this, Reg, StartLoc, EndLoc); return AMDGPUOperand::CreateReg(this, Reg, StartLoc, EndLoc);
} }
OperandMatchResultTy OperandMatchResultTy
▲ Show 20 Lines • Show All 1,941 Lines • ▼ Show 20 Linesbool AMDGPUAsmParser::ParseDirectiveAMDGPUHsaKernel() {
if (getLexer().isNot(AsmToken::Identifier)) if (getLexer().isNot(AsmToken::Identifier))
return TokError("expected symbol name"); return TokError("expected symbol name");
StringRef KernelName = Parser.getTok().getString(); StringRef KernelName = Parser.getTok().getString();
getTargetStreamer().EmitAMDGPUSymbolType(KernelName, getTargetStreamer().EmitAMDGPUSymbolType(KernelName,
ELF::STT_AMDGPU_HSA_KERNEL); ELF::STT_AMDGPU_HSA_KERNEL);
Lex(); Lex();
if (!AMDGPU::IsaInfo::hasCodeObjectV3(&getSTI()))
KernelScope.initialize(getContext()); KernelScope.initialize(getContext());
return false; return false;
} }
bool AMDGPUAsmParser::ParseDirectiveISAVersion() { bool AMDGPUAsmParser::ParseDirectiveISAVersion() {
if (getSTI().getTargetTriple().getArch() != Triple::amdgcn) { if (getSTI().getTargetTriple().getArch() != Triple::amdgcn) {
return Error(getParser().getTok().getLoc(), return Error(getParser().getTok().getLoc(),
".amd_amdgpu_isa directive is not available on non-amdgcn " ".amd_amdgpu_isa directive is not available on non-amdgcn "
"architectures"); "architectures");
Show All 16 Linesbool AMDGPUAsmParser::ParseDirectiveISAVersion() {
return false; return false;
} }
bool AMDGPUAsmParser::ParseDirectiveHSAMetadata() { bool AMDGPUAsmParser::ParseDirectiveHSAMetadata() {
const char *AssemblerDirectiveBegin; const char *AssemblerDirectiveBegin;
const char *AssemblerDirectiveEnd; const char *AssemblerDirectiveEnd;
std::tie(AssemblerDirectiveBegin, AssemblerDirectiveEnd) = std::tie(AssemblerDirectiveBegin, AssemblerDirectiveEnd) =
AMDGPU::IsaInfo::hasCodeObjectV3(&getSTI()) isHsaAbiVersion3(&getSTI())
? std::make_tuple(HSAMD::V3::AssemblerDirectiveBegin, ? std::make_tuple(HSAMD::V3::AssemblerDirectiveBegin,
HSAMD::V3::AssemblerDirectiveEnd) HSAMD::V3::AssemblerDirectiveEnd)
: std::make_tuple(HSAMD::AssemblerDirectiveBegin, : std::make_tuple(HSAMD::AssemblerDirectiveBegin,
HSAMD::AssemblerDirectiveEnd); HSAMD::AssemblerDirectiveEnd);
if (getSTI().getTargetTriple().getOS() != Triple::AMDHSA) { if (getSTI().getTargetTriple().getOS() != Triple::AMDHSA) {
return Error(getParser().getTok().getLoc(), return Error(getParser().getTok().getLoc(),
(Twine(AssemblerDirectiveBegin) + Twine(" directive is " (Twine(AssemblerDirectiveBegin) + Twine(" directive is "
"not available on non-amdhsa OSes")).str()); "not available on non-amdhsa OSes")).str());
} }
std::string HSAMetadataString; std::string HSAMetadataString;
if (ParseToEndDirective(AssemblerDirectiveBegin, AssemblerDirectiveEnd, if (ParseToEndDirective(AssemblerDirectiveBegin, AssemblerDirectiveEnd,
HSAMetadataString)) HSAMetadataString))
return true; return true;
if (IsaInfo::hasCodeObjectV3(&getSTI())) { if (isHsaAbiVersion3(&getSTI())) {
if (!getTargetStreamer().EmitHSAMetadataV3(HSAMetadataString)) if (!getTargetStreamer().EmitHSAMetadataV3(HSAMetadataString))
return Error(getParser().getTok().getLoc(), "invalid HSA metadata"); return Error(getParser().getTok().getLoc(), "invalid HSA metadata");
} else { } else {
if (!getTargetStreamer().EmitHSAMetadataV2(HSAMetadataString)) if (!getTargetStreamer().EmitHSAMetadataV2(HSAMetadataString))
return Error(getParser().getTok().getLoc(), "invalid HSA metadata"); return Error(getParser().getTok().getLoc(), "invalid HSA metadata");
} }
return false; return false;
▲ Show 20 Lines • Show All 140 Lines • ▼ Show 20 Linesbool AMDGPUAsmParser::ParseDirectiveAMDGPULDS() {
getTargetStreamer().emitAMDGPULDS(Symbol, Size, Align(Alignment)); getTargetStreamer().emitAMDGPULDS(Symbol, Size, Align(Alignment));
return false; return false;
} }
bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) { bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {
StringRef IDVal = DirectiveID.getString(); StringRef IDVal = DirectiveID.getString();
if (AMDGPU::IsaInfo::hasCodeObjectV3(&getSTI())) { if (isHsaAbiVersion3(&getSTI())) {
if (IDVal == ".amdgcn_target") if (IDVal == ".amdgcn_target")
return ParseDirectiveAMDGCNTarget(); return ParseDirectiveAMDGCNTarget();
if (IDVal == ".amdhsa_kernel") if (IDVal == ".amdhsa_kernel")
return ParseDirectiveAMDHSAKernel(); return ParseDirectiveAMDHSAKernel();
// TODO: Restructure/combine with PAL metadata directive. // TODO: Restructure/combine with PAL metadata directive.
if (IDVal == AMDGPU::HSAMD::V3::AssemblerDirectiveBegin) if (IDVal == AMDGPU::HSAMD::V3::AssemblerDirectiveBegin)
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llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp

Show First 20 Lines • Show All 231 Lines • ▼ Show 20 Lines
}; };
} // end anonymous namespace } // end anonymous namespace
MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T, MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
const MCTargetOptions &Options) { const MCTargetOptions &Options) {
// Use 64-bit ELF for amdgcn
return new ELFAMDGPUAsmBackend(T, STI.getTargetTriple(), return new ELFAMDGPUAsmBackend(T, STI.getTargetTriple(),
IsaInfo::hasCodeObjectV3(&STI) ? 1 : 0); getHsaAbiVersion(&STI).getValueOr(0));
} }

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

Show All 31 Lines
class MCRegisterClass; class MCRegisterClass;
class MCRegisterInfo; class MCRegisterInfo;
class MCSubtargetInfo; class MCSubtargetInfo;
class StringRef; class StringRef;
class Triple; class Triple;
namespace AMDGPU { namespace AMDGPU {
/// \returns HSA OS ABI Version identification.
Optional<uint8_t> getHsaAbiVersion(const MCSubtargetInfo *STI);
/// \returns True if HSA OS ABI Version identification is 2,
/// false otherwise.
bool isHsaAbiVersion2(const MCSubtargetInfo *STI);
/// \returns True if HSA OS ABI Version identification is 3,
/// false otherwise.
bool isHsaAbiVersion3(const MCSubtargetInfo *STI);
struct GcnBufferFormatInfo { struct GcnBufferFormatInfo {
unsigned Format; unsigned Format;
unsigned BitsPerComp; unsigned BitsPerComp;
unsigned NumComponents; unsigned NumComponents;
unsigned NumFormat; unsigned NumFormat;
unsigned DataFormat; unsigned DataFormat;
}; };
Show All 11 Linesenum {
// doesn't spill SGPRs as much as when 80 is set. // doesn't spill SGPRs as much as when 80 is set.
FIXED_NUM_SGPRS_FOR_INIT_BUG = 96, FIXED_NUM_SGPRS_FOR_INIT_BUG = 96,
TRAP_NUM_SGPRS = 16 TRAP_NUM_SGPRS = 16
}; };
/// Streams isa version string for given subtarget \p STI into \p Stream. /// Streams isa version string for given subtarget \p STI into \p Stream.
void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream); void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream);
/// \returns True if given subtarget \p STI supports code object version 3,
/// false otherwise.
bool hasCodeObjectV3(const MCSubtargetInfo *STI);
/// \returns Wavefront size for given subtarget \p STI. /// \returns Wavefront size for given subtarget \p STI.
unsigned getWavefrontSize(const MCSubtargetInfo *STI); unsigned getWavefrontSize(const MCSubtargetInfo *STI);
/// \returns Local memory size in bytes for given subtarget \p STI. /// \returns Local memory size in bytes for given subtarget \p STI.
unsigned getLocalMemorySize(const MCSubtargetInfo *STI); unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
/// \returns Number of execution units per compute unit for given subtarget \p /// \returns Number of execution units per compute unit for given subtarget \p
/// STI. /// STI.
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llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

Show All 26 Lines
#include "llvm/MC/MCContext.h" #include "llvm/MC/MCContext.h"
#include "llvm/MC/MCInstrDesc.h" #include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSectionELF.h" #include "llvm/MC/MCSectionELF.h"
#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/SubtargetFeature.h" #include "llvm/MC/SubtargetFeature.h"
#include "llvm/Support/Casting.h" #include "llvm/Support/Casting.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h" #include "llvm/Support/MathExtras.h"
#include <algorithm> #include <algorithm>
#include <cassert> #include <cassert>
#include <cstdint> #include <cstdint>
#include <cstring> #include <cstring>
#include <utility> #include <utility>
#include "MCTargetDesc/AMDGPUMCTargetDesc.h" #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#define GET_INSTRINFO_NAMED_OPS #define GET_INSTRINFO_NAMED_OPS
#define GET_INSTRMAP_INFO #define GET_INSTRMAP_INFO
#include "AMDGPUGenInstrInfo.inc" #include "AMDGPUGenInstrInfo.inc"
#undef GET_INSTRMAP_INFO #undef GET_INSTRMAP_INFO
#undef GET_INSTRINFO_NAMED_OPS #undef GET_INSTRINFO_NAMED_OPS
static llvm::cl::opt<unsigned> AmdhsaCodeObjectVersion(
"amdhsa-code-object-version", llvm::cl::Hidden,
llvm::cl::desc("AMDHSA Code Object Version"), llvm::cl::init(3));
namespace { namespace {
/// \returns Bit mask for given bit \p Shift and bit \p Width. /// \returns Bit mask for given bit \p Shift and bit \p Width.
unsigned getBitMask(unsigned Shift, unsigned Width) { unsigned getBitMask(unsigned Shift, unsigned Width) {
return ((1 << Width) - 1) << Shift; return ((1 << Width) - 1) << Shift;
} }
/// Packs \p Src into \p Dst for given bit \p Shift and bit \p Width. /// Packs \p Src into \p Dst for given bit \p Shift and bit \p Width.
Show All 39 Lines
unsigned getVmcntBitWidthHi() { return 2; } unsigned getVmcntBitWidthHi() { return 2; }
} // end namespace anonymous } // end namespace anonymous
namespace llvm { namespace llvm {
namespace AMDGPU { namespace AMDGPU {
Optional<uint8_t> getHsaAbiVersion(const MCSubtargetInfo *STI) {
if (STI && STI->getTargetTriple().getOS() != Triple::AMDHSA)
return None;
switch (AmdhsaCodeObjectVersion) {
case 2:
return ELF::ELFABIVERSION_AMDGPU_HSA_V2;
case 3:
return ELF::ELFABIVERSION_AMDGPU_HSA_V3;
default:
return ELF::ELFABIVERSION_AMDGPU_HSA_V3;
}
}
bool isHsaAbiVersion2(const MCSubtargetInfo *STI) {
if (const auto &&HsaAbiVer = getHsaAbiVersion(STI))
return HsaAbiVer.getValue() == ELF::ELFABIVERSION_AMDGPU_HSA_V2;
return false;
}
bool isHsaAbiVersion3(const MCSubtargetInfo *STI) {
if (const auto &&HsaAbiVer = getHsaAbiVersion(STI))
return HsaAbiVer.getValue() == ELF::ELFABIVERSION_AMDGPU_HSA_V3;
return false;
}
#define GET_MIMGBaseOpcodesTable_IMPL #define GET_MIMGBaseOpcodesTable_IMPL
#define GET_MIMGDimInfoTable_IMPL #define GET_MIMGDimInfoTable_IMPL
#define GET_MIMGInfoTable_IMPL #define GET_MIMGInfoTable_IMPL
#define GET_MIMGLZMappingTable_IMPL #define GET_MIMGLZMappingTable_IMPL
#define GET_MIMGMIPMappingTable_IMPL #define GET_MIMGMIPMappingTable_IMPL
#define GET_MIMGG16MappingTable_IMPL #define GET_MIMGG16MappingTable_IMPL
#include "AMDGPUGenSearchableTables.inc" #include "AMDGPUGenSearchableTables.inc"
▲ Show 20 Lines • Show All 138 Lines • ▼ Show 20 Linesvoid streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream) {
if (hasXNACK(*STI)) if (hasXNACK(*STI))
Stream << "+xnack"; Stream << "+xnack";
if (hasSRAMECC(*STI)) if (hasSRAMECC(*STI))
Stream << "+sram-ecc"; Stream << "+sram-ecc";
Stream.flush(); Stream.flush();
} }
bool hasCodeObjectV3(const MCSubtargetInfo *STI) {
return STI->getTargetTriple().getOS() == Triple::AMDHSA &&
STI->getFeatureBits().test(FeatureCodeObjectV3);
}
unsigned getWavefrontSize(const MCSubtargetInfo *STI) { unsigned getWavefrontSize(const MCSubtargetInfo *STI) {
if (STI->getFeatureBits().test(FeatureWavefrontSize16)) if (STI->getFeatureBits().test(FeatureWavefrontSize16))
return 16; return 16;
if (STI->getFeatureBits().test(FeatureWavefrontSize32)) if (STI->getFeatureBits().test(FeatureWavefrontSize32))
return 32; return 32;
return 64; return 64;
} }
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llvm/test/CodeGen/AMDGPU/GlobalISel/lds-size.ll

; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa < %S/../lds-size.ll | FileCheck -check-prefix=ALL -check-prefix=HSA %S/../lds-size.ll ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=2 < %S/../lds-size.ll | FileCheck -check-prefix=ALL -check-prefix=HSA %S/../lds-size.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.dispatch.id.ll

; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -global-isel -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare i64 @llvm.amdgcn.dispatch.id() #1 declare i64 @llvm.amdgcn.dispatch.id() #1
; GCN-LABEL: {{^}}dispatch_id: ; GCN-LABEL: {{^}}dispatch_id:
; GCN: .amd_kernel_code_t ; GCN: .amd_kernel_code_t
; GCN: enable_sgpr_dispatch_id = 1 ; GCN: enable_sgpr_dispatch_id = 1
; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], s6 ; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], s6
Show All 10 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.dispatch.ptr.ll

; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-code-object-v3 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -global-isel -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; FIXME: Error on non-HSA target ; FIXME: Error on non-HSA target
; GCN-LABEL: {{^}}test: ; GCN-LABEL: {{^}}test:
; GCN: enable_sgpr_dispatch_ptr = 1 ; GCN: enable_sgpr_dispatch_ptr = 1
; GCN: s_load_dword s{{[0-9]+}}, s[4:5], 0x0 ; GCN: s_load_dword s{{[0-9]+}}, s[4:5], 0x0
define amdgpu_kernel void @test(i32 addrspace(1)* %out) { define amdgpu_kernel void @test(i32 addrspace(1)* %out) {
%dispatch_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0 %dispatch_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0
Show All 9 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll

; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mattr=-code-object-v3 -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL %s ; RUN: llc -global-isel -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -mattr=+flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,OS-MESA3D,MESA,ALL %s ; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -mattr=+flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,OS-MESA3D,MESA,ALL %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-unknown -mcpu=hawaii -mattr=+flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=OS-UNKNOWN,MESA,ALL %s ; RUN: llc -global-isel -mtriple=amdgcn-mesa-unknown -mcpu=hawaii -mattr=+flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=OS-UNKNOWN,MESA,ALL %s
; ALL-LABEL: {{^}}test: ; ALL-LABEL: {{^}}test:
; CO-V2: enable_sgpr_kernarg_segment_ptr = 1 ; CO-V2: enable_sgpr_kernarg_segment_ptr = 1
; HSA: kernarg_segment_byte_size = 8 ; HSA: kernarg_segment_byte_size = 8
; HSA: kernarg_segment_alignment = 4 ; HSA: kernarg_segment_alignment = 4
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llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.queue.ptr.ll

; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-code-object-v3 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; FIXME: Error on non-hsa target ; FIXME: Error on non-hsa target
; GCN-LABEL: {{^}}test: ; GCN-LABEL: {{^}}test:
; GCN: enable_sgpr_queue_ptr = 1 ; GCN: enable_sgpr_queue_ptr = 1
; GCN: s_load_dword s{{[0-9]+}}, s[4:5], 0x0 ; GCN: s_load_dword s{{[0-9]+}}, s[4:5], 0x0
define amdgpu_kernel void @test(i32 addrspace(1)* %out) { define amdgpu_kernel void @test(i32 addrspace(1)* %out) {
%queue_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0 %queue_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0
Show All 9 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll

; RUN: llc -global-isel -mtriple=amdgcn-unknown-amdhsa -mattr=-code-object-v3 -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=CI-HSA %s ; RUN: llc -global-isel -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=2 -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=CI-HSA %s
; RUN: llc -global-isel -mtriple=amdgcn-unknown-amdhsa -mattr=-code-object-v3 -mcpu=carrizo -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=VI-HSA %s ; RUN: llc -global-isel -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=2 -mcpu=carrizo -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=VI-HSA %s
; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=UNKNOWN-OS -check-prefix=SI-MESA %s ; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=UNKNOWN-OS -check-prefix=SI-MESA %s
; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=UNKNOWN-OS -check-prefix=VI-MESA %s ; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=UNKNOWN-OS -check-prefix=VI-MESA %s
; RUN: llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mattr=-code-object-v3 -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,SI-MESA %s ; RUN: llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,SI-MESA %s
; RUN: llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mattr=-code-object-v3 -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,VI-MESA %s ; RUN: llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,VI-MESA %s
declare i32 @llvm.amdgcn.workgroup.id.x() #0 declare i32 @llvm.amdgcn.workgroup.id.x() #0
declare i32 @llvm.amdgcn.workgroup.id.y() #0 declare i32 @llvm.amdgcn.workgroup.id.y() #0
declare i32 @llvm.amdgcn.workgroup.id.z() #0 declare i32 @llvm.amdgcn.workgroup.id.z() #0
; ALL-LABEL: {{^}}test_workgroup_id_x: ; ALL-LABEL: {{^}}test_workgroup_id_x:
; CO-V2: .amd_kernel_code_t ; CO-V2: .amd_kernel_code_t
▲ Show 20 Lines • Show All 92 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll

; RUN: llc -global-isel -mtriple=amdgcn-unknown-amdhsa -mattr=-code-object-v3 -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=CI-HSA %s ; RUN: llc -global-isel -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=2 -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=CI-HSA %s
; RUN: llc -global-isel -mtriple=amdgcn-unknown-amdhsa -mattr=-code-object-v3 -mcpu=carrizo -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=VI-HSA %s ; RUN: llc -global-isel -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=2 -mcpu=carrizo -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=VI-HSA %s
; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=hawaii -mattr=+flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MESA -check-prefix=SI-MESA %s ; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=hawaii -mattr=+flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MESA -check-prefix=SI-MESA %s
; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=tonga -mattr=+flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MESA -check-prefix=VI-MESA %s ; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=tonga -mattr=+flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MESA -check-prefix=VI-MESA %s
; RUN: llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mattr=+flat-for-global,-code-object-v3 -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,SI-MESA %s ; RUN: llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mattr=+flat-for-global -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,SI-MESA %s
; RUN: llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mattr=-code-object-v3 -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,VI-MESA %s ; RUN: llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,VI-MESA %s
declare i32 @llvm.amdgcn.workitem.id.x() #0 declare i32 @llvm.amdgcn.workitem.id.x() #0
declare i32 @llvm.amdgcn.workitem.id.y() #0 declare i32 @llvm.amdgcn.workitem.id.y() #0
declare i32 @llvm.amdgcn.workitem.id.z() #0 declare i32 @llvm.amdgcn.workitem.id.z() #0
; MESA: .section .AMDGPU.config ; MESA: .section .AMDGPU.config
; MESA: .long 47180 ; MESA: .long 47180
; MESA-NEXT: .long 132{{$}} ; MESA-NEXT: .long 132{{$}}
▲ Show 20 Lines • Show All 105 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.trap.ll

; Runs original SDAG test with -global-isel ; Runs original SDAG test with -global-isel
; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -verify-machineinstrs < %S/../trap.ll | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP -enable-var-scope %S/../trap.ll ; RUN: llc -global-isel -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -verify-machineinstrs < %S/../trap.ll | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP -enable-var-scope %S/../trap.ll
; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mattr=+trap-handler -verify-machineinstrs < %S/../trap.ll | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP -enable-var-scope %S/../trap.ll ; RUN: llc -global-isel -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -mattr=+trap-handler -verify-machineinstrs < %S/../trap.ll | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP -enable-var-scope %S/../trap.ll
; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mattr=-trap-handler -verify-machineinstrs < %S/../trap.ll | FileCheck -check-prefix=GCN -check-prefix=NO-HSA-TRAP -enable-var-scope %S/../trap.ll ; RUN: llc -global-isel -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -mattr=-trap-handler -verify-machineinstrs < %S/../trap.ll | FileCheck -check-prefix=GCN -check-prefix=NO-HSA-TRAP -enable-var-scope %S/../trap.ll
; RUN: llc -global-isel -mtriple=amdgcn--amdhsa -mattr=-trap-handler -verify-machineinstrs < %S/../trap.ll 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -enable-var-scope %S/../trap.ll ; RUN: llc -global-isel -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -mattr=-trap-handler -verify-machineinstrs < %S/../trap.ll 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -enable-var-scope %S/../trap.ll
; enable trap handler feature ; enable trap handler feature
; RUN: llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mattr=+trap-handler -verify-machineinstrs < %S/../trap.ll | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=TRAP-BIT -check-prefix=MESA-TRAP -enable-var-scope %S/../trap.ll ; RUN: llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mattr=+trap-handler -verify-machineinstrs < %S/../trap.ll | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=TRAP-BIT -check-prefix=MESA-TRAP -enable-var-scope %S/../trap.ll
; RUN: llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mattr=+trap-handler -verify-machineinstrs < %S/../trap.ll 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=TRAP-BIT -enable-var-scope %S/../trap.ll ; RUN: llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mattr=+trap-handler -verify-machineinstrs < %S/../trap.ll 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=TRAP-BIT -enable-var-scope %S/../trap.ll
; disable trap handler feature ; disable trap handler feature
; RUN: llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler -verify-machineinstrs < %S/../trap.ll | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=NO-TRAP-BIT -check-prefix=NOMESA-TRAP -enable-var-scope %S/../trap.ll ; RUN: llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler -verify-machineinstrs < %S/../trap.ll | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=NO-TRAP-BIT -check-prefix=NOMESA-TRAP -enable-var-scope %S/../trap.ll
; RUN: llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler -verify-machineinstrs < %S/../trap.ll 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=NO-TRAP-BIT -enable-var-scope %S/../trap.ll ; RUN: llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler -verify-machineinstrs < %S/../trap.ll 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=NO-TRAP-BIT -enable-var-scope %S/../trap.ll
; RUN: llc -global-isel -march=amdgcn -verify-machineinstrs < %S/../trap.ll 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -enable-var-scope %S/../trap.ll ; RUN: llc -global-isel -march=amdgcn -verify-machineinstrs < %S/../trap.ll 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -enable-var-scope %S/../trap.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/memory-legalizer-atomic-fence.ll

; RUN: llc -global-isel -mtriple=amdgcn-amd- -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX6,GFX68 %s ; RUN: llc -global-isel -mtriple=amdgcn-amd- -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX6,GFX68 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX8,GFX68 %s ; RUN: llc -global-isel -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX8,GFX68 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX8,GFX68 %s ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX8,GFX68 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+code-object-v3 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX10,GFX10WGP %s ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX10,GFX10WGP %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+code-object-v3,+cumode -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX10,GFX10CU %s ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX10,GFX10CU %s
; FUNC-LABEL: {{^}}system_one_as_acquire: ; FUNC-LABEL: {{^}}system_one_as_acquire:
; GCN: %bb.0 ; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE ; GCN-NOT: ATOMIC_FENCE
; GFX6: s_waitcnt vmcnt(0){{$}} ; GFX6: s_waitcnt vmcnt(0){{$}}
; GFX6-NEXT: buffer_wbinvl1{{$}} ; GFX6-NEXT: buffer_wbinvl1{{$}}
; GFX8: s_waitcnt vmcnt(0){{$}} ; GFX8: s_waitcnt vmcnt(0){{$}}
; GFX8-NEXT: buffer_wbinvl1_vol{{$}} ; GFX8-NEXT: buffer_wbinvl1_vol{{$}}
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llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgcn-amd-amdhsa < %s | FileCheck -check-prefixes=CHECK,GISEL %s ; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgcn-amd-amdpal < %s | FileCheck -check-prefixes=CHECK,GISEL %s
; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgcn-amd-amdhsa < %s | FileCheck -check-prefixes=CHECK,CGP %s ; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgcn-amd-amdpal < %s | FileCheck -check-prefixes=CHECK,CGP %s
; The same 32-bit expansion is implemented in the legalizer and in AMDGPUCodeGenPrepare. ; The same 32-bit expansion is implemented in the legalizer and in AMDGPUCodeGenPrepare.
define i32 @v_sdiv_i32(i32 %num, i32 %den) { define i32 @v_sdiv_i32(i32 %num, i32 %den) {
; GISEL-LABEL: v_sdiv_i32: ; GISEL-LABEL: v_sdiv_i32:
; GISEL: ; %bb.0: ; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-NEXT: v_ashrrev_i32_e32 v2, 31, v0 ; GISEL-NEXT: v_ashrrev_i32_e32 v2, 31, v0
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llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgcn-amd-amdhsa < %s | FileCheck -check-prefixes=CHECK,GISEL %s ; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgcn-amd-amdpal < %s | FileCheck -check-prefixes=CHECK,GISEL %s
; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgcn-amd-amdhsa < %s | FileCheck -check-prefixes=CHECK,CGP %s ; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgcn-amd-amdpal < %s | FileCheck -check-prefixes=CHECK,CGP %s
; The same 32-bit expansion is implemented in the legalizer and in AMDGPUCodeGenPrepare. ; The same 32-bit expansion is implemented in the legalizer and in AMDGPUCodeGenPrepare.
define i32 @v_srem_i32(i32 %num, i32 %den) { define i32 @v_srem_i32(i32 %num, i32 %den) {
; GISEL-LABEL: v_srem_i32: ; GISEL-LABEL: v_srem_i32:
; GISEL: ; %bb.0: ; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-NEXT: v_ashrrev_i32_e32 v2, 31, v0 ; GISEL-NEXT: v_ashrrev_i32_e32 v2, 31, v0
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llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgcn-amd-amdhsa < %s | FileCheck -check-prefixes=CHECK,GISEL %s ; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgcn-amd-amdpal < %s | FileCheck -check-prefixes=CHECK,GISEL %s
; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgcn-amd-amdhsa < %s | FileCheck -check-prefixes=CHECK,CGP %s ; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgcn-amd-amdpal < %s | FileCheck -check-prefixes=CHECK,CGP %s
; The same 32-bit expansion is implemented in the legalizer and in AMDGPUCodeGenPrepare. ; The same 32-bit expansion is implemented in the legalizer and in AMDGPUCodeGenPrepare.
define i32 @v_udiv_i32(i32 %num, i32 %den) { define i32 @v_udiv_i32(i32 %num, i32 %den) {
; GISEL-LABEL: v_udiv_i32: ; GISEL-LABEL: v_udiv_i32:
; GISEL: ; %bb.0: ; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-NEXT: v_cvt_f32_u32_e32 v2, v1 ; GISEL-NEXT: v_cvt_f32_u32_e32 v2, v1
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llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgcn-amd-amdhsa -denormal-fp-math-f32=preserve-sign -mattr=+mad-mac-f32-insts < %s | FileCheck -check-prefixes=CHECK,GISEL %s ; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgcn-amd-amdpal -denormal-fp-math-f32=preserve-sign -mattr=+mad-mac-f32-insts < %s | FileCheck -check-prefixes=CHECK,GISEL %s
; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgcn-amd-amdhsa -denormal-fp-math-f32=preserve-sign -mattr=+mad-mac-f32-insts < %s | FileCheck -check-prefixes=CHECK,CGP %s ; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgcn-amd-amdpal -denormal-fp-math-f32=preserve-sign -mattr=+mad-mac-f32-insts < %s | FileCheck -check-prefixes=CHECK,CGP %s
; The same 32-bit expansion is implemented in the legalizer and in AMDGPUCodeGenPrepare. ; The same 32-bit expansion is implemented in the legalizer and in AMDGPUCodeGenPrepare.
define i64 @v_udiv_i64(i64 %num, i64 %den) { define i64 @v_udiv_i64(i64 %num, i64 %den) {
; CHECK-LABEL: v_udiv_i64: ; CHECK-LABEL: v_udiv_i64:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_or_b32_e32 v5, v1, v3 ; CHECK-NEXT: v_or_b32_e32 v5, v1, v3
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llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgcn-amd-amdhsa < %s | FileCheck -check-prefixes=CHECK,GISEL %s ; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgcn-amd-amdpal < %s | FileCheck -check-prefixes=CHECK,GISEL %s
; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgcn-amd-amdhsa < %s | FileCheck -check-prefixes=CHECK,CGP %s ; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgcn-amd-amdpal < %s | FileCheck -check-prefixes=CHECK,CGP %s
; The same 32-bit expansion is implemented in the legalizer and in AMDGPUCodeGenPrepare. ; The same 32-bit expansion is implemented in the legalizer and in AMDGPUCodeGenPrepare.
define i32 @v_urem_i32(i32 %num, i32 %den) { define i32 @v_urem_i32(i32 %num, i32 %den) {
; GISEL-LABEL: v_urem_i32: ; GISEL-LABEL: v_urem_i32:
; GISEL: ; %bb.0: ; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GISEL-NEXT: v_cvt_f32_u32_e32 v2, v1 ; GISEL-NEXT: v_cvt_f32_u32_e32 v2, v1
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llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgcn-amd-amdhsa -denormal-fp-math-f32=preserve-sign -mattr=+mad-mac-f32-insts < %s | FileCheck -check-prefixes=CHECK,GISEL %s ; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgcn-amd-amdpal -denormal-fp-math-f32=preserve-sign -mattr=+mad-mac-f32-insts < %s | FileCheck -check-prefixes=CHECK,GISEL %s
; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgcn-amd-amdhsa -denormal-fp-math-f32=preserve-sign -mattr=+mad-mac-f32-insts < %s | FileCheck -check-prefixes=CHECK,CGP %s ; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgcn-amd-amdpal -denormal-fp-math-f32=preserve-sign -mattr=+mad-mac-f32-insts < %s | FileCheck -check-prefixes=CHECK,CGP %s
; The same 32-bit expansion is implemented in the legalizer and in AMDGPUCodeGenPrepare. ; The same 32-bit expansion is implemented in the legalizer and in AMDGPUCodeGenPrepare.
define i64 @v_urem_i64(i64 %num, i64 %den) { define i64 @v_urem_i64(i64 %num, i64 %den) {
; CHECK-LABEL: v_urem_i64: ; CHECK-LABEL: v_urem_i64:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_or_b32_e32 v5, v1, v3 ; CHECK-NEXT: v_or_b32_e32 v5, v1, v3
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llvm/test/CodeGen/AMDGPU/addrspacecast.ll

; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -mattr=-code-object-v3,-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=CI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=CI %s
; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-code-object-v3,-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=GFX9 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=2 -mattr=-promote-alloca -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=HSA -check-prefix=GFX9 %s
; HSA-LABEL: {{^}}use_group_to_flat_addrspacecast: ; HSA-LABEL: {{^}}use_group_to_flat_addrspacecast:
; HSA: enable_sgpr_private_segment_buffer = 1 ; HSA: enable_sgpr_private_segment_buffer = 1
; HSA: enable_sgpr_dispatch_ptr = 0 ; HSA: enable_sgpr_dispatch_ptr = 0
; CI: enable_sgpr_queue_ptr = 1 ; CI: enable_sgpr_queue_ptr = 1
; GFX9: enable_sgpr_queue_ptr = 0 ; GFX9: enable_sgpr_queue_ptr = 0
; CI-DAG: s_load_dword [[PTR:s[0-9]+]], s[6:7], 0x0{{$}} ; CI-DAG: s_load_dword [[PTR:s[0-9]+]], s[6:7], 0x0{{$}}
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llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll

; RUN: llc -show-mc-encoding -mattr=-code-object-v3,+promote-alloca -disable-promote-alloca-to-vector -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -march=amdgcn < %s | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -show-mc-encoding --amdhsa-code-object-version=2 -mattr=+promote-alloca -disable-promote-alloca-to-vector -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -march=amdgcn < %s | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -show-mc-encoding -mattr=-code-object-v3,+promote-alloca -disable-promote-alloca-to-vector -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-code-object-v3,-unaligned-buffer-access < %s | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC -check-prefix=HSA-PROMOTE %s ; RUN: llc -show-mc-encoding --amdhsa-code-object-version=2 -mattr=+promote-alloca -disable-promote-alloca-to-vector -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-unaligned-buffer-access < %s | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC -check-prefix=HSA-PROMOTE %s
; RUN: llc -show-mc-encoding -mattr=-code-object-v3,-promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -march=amdgcn < %s | FileCheck %s -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC ; RUN: llc -show-mc-encoding --amdhsa-code-object-version=2 -mattr=-promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -march=amdgcn < %s | FileCheck %s -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC
; RUN: llc -show-mc-encoding -mattr=-code-object-v3,-promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -mcpu=kaveri -mattr=-code-object-v3,-unaligned-buffer-access < %s | FileCheck -enable-var-scope -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC -check-prefix=HSA-ALLOCA %s ; RUN: llc -show-mc-encoding --amdhsa-code-object-version=2 -mattr=-promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -mcpu=kaveri -mattr=-unaligned-buffer-access < %s | FileCheck -enable-var-scope -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC -check-prefix=HSA-ALLOCA %s
; RUN: llc -show-mc-encoding -mattr=-code-object-v3,+promote-alloca -disable-promote-alloca-to-vector -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -march=amdgcn -mcpu=tonga -mattr=-code-object-v3,-unaligned-buffer-access < %s | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -show-mc-encoding --amdhsa-code-object-version=2 -mattr=+promote-alloca -disable-promote-alloca-to-vector -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -march=amdgcn -mcpu=tonga -mattr=-unaligned-buffer-access < %s | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -show-mc-encoding -mattr=-code-object-v3,+promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -march=amdgcn -mcpu=tonga -mattr=-code-object-v3,-unaligned-buffer-access < %s | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE-VECT -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -show-mc-encoding --amdhsa-code-object-version=2 -mattr=+promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -march=amdgcn -mcpu=tonga -mattr=-unaligned-buffer-access < %s | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE-VECT -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -show-mc-encoding -mattr=-code-object-v3,-promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -march=amdgcn -mcpu=tonga -mattr=-code-object-v3,-unaligned-buffer-access < %s | FileCheck -enable-var-scope -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -show-mc-encoding --amdhsa-code-object-version=2 -mattr=-promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -march=amdgcn -mcpu=tonga -mattr=-unaligned-buffer-access < %s | FileCheck -enable-var-scope -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC %s
; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -data-layout=A5 -mcpu=kaveri -amdgpu-promote-alloca -disable-promote-alloca-to-vector < %s | FileCheck -enable-var-scope -check-prefix=HSAOPT -check-prefix=OPT %s ; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -data-layout=A5 -mcpu=kaveri -amdgpu-promote-alloca -disable-promote-alloca-to-vector < %s | FileCheck -enable-var-scope -check-prefix=HSAOPT -check-prefix=OPT %s
; RUN: opt -S -mtriple=amdgcn-unknown-unknown -data-layout=A5 -mcpu=kaveri -amdgpu-promote-alloca -disable-promote-alloca-to-vector < %s | FileCheck -enable-var-scope -check-prefix=NOHSAOPT -check-prefix=OPT %s ; RUN: opt -S -mtriple=amdgcn-unknown-unknown -data-layout=A5 -mcpu=kaveri -amdgpu-promote-alloca -disable-promote-alloca-to-vector < %s | FileCheck -enable-var-scope -check-prefix=NOHSAOPT -check-prefix=OPT %s
; RUN: llc -march=r600 -mcpu=cypress -disable-promote-alloca-to-vector < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC ; RUN: llc -march=r600 -mcpu=cypress -disable-promote-alloca-to-vector < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC
; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck %s -check-prefix=R600-VECT -check-prefix=FUNC ; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck %s -check-prefix=R600-VECT -check-prefix=FUNC
; HSAOPT: @mova_same_clause.stack = internal unnamed_addr addrspace(3) global [256 x [5 x i32]] undef, align 4 ; HSAOPT: @mova_same_clause.stack = internal unnamed_addr addrspace(3) global [256 x [5 x i32]] undef, align 4
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llvm/test/CodeGen/AMDGPU/amdpal-elf.ll

; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=kaveri -filetype=obj -mattr=-code-object-v3 | llvm-readobj -symbols -s -sd - | FileCheck --check-prefix=ELF %s ; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=kaveri -filetype=obj | llvm-readobj -symbols -s -sd - | FileCheck --check-prefix=ELF %s
; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=kaveri -mattr=-code-object-v3 | llvm-mc -filetype=obj -triple amdgcn--amdpal -mcpu=kaveri -mattr=-code-object-v3 | llvm-readobj -symbols -s -sd - | FileCheck %s --check-prefix=ELF ; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=kaveri | llvm-mc -filetype=obj -triple amdgcn--amdpal -mcpu=kaveri | llvm-readobj -symbols -s -sd - | FileCheck %s --check-prefix=ELF
; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64,-code-object-v3 | FileCheck --check-prefix=GFX10-W32 %s ; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 | FileCheck --check-prefix=GFX10-W32 %s
; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64,-code-object-v3 | FileCheck --check-prefix=GFX10-W64 %s ; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 | FileCheck --check-prefix=GFX10-W64 %s
; ELF: Section { ; ELF: Section {
; ELF: Name: .text ; ELF: Name: .text
; ELF: Type: SHT_PROGBITS (0x1) ; ELF: Type: SHT_PROGBITS (0x1)
; ELF: Flags [ (0x6) ; ELF: Flags [ (0x6)
; ELF: SHF_ALLOC (0x2) ; ELF: SHF_ALLOC (0x2)
; ELF: SHF_EXECINSTR (0x4) ; ELF: SHF_EXECINSTR (0x4)
; ELF: } ; ELF: }
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llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-v3.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -mattr=+code-object-v3 < %s | FileCheck --check-prefix=CHECK %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck --check-prefix=CHECK %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -amdgpu-verify-hsa-metadata -filetype=obj -mattr=+code-object-v3 -o /dev/null < %s 2>&1 | FileCheck --check-prefix=PARSER %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -amdgpu-verify-hsa-metadata -filetype=obj -o /dev/null < %s 2>&1 | FileCheck --check-prefix=PARSER %s
; CHECK-LABEL: {{^}}min_64_max_64: ; CHECK-LABEL: {{^}}min_64_max_64:
; CHECK: SGPRBlocks: 0 ; CHECK: SGPRBlocks: 0
; CHECK: VGPRBlocks: 0 ; CHECK: VGPRBlocks: 0
; CHECK: NumSGPRsForWavesPerEU: 1 ; CHECK: NumSGPRsForWavesPerEU: 1
; CHECK: NumVGPRsForWavesPerEU: 1 ; CHECK: NumVGPRsForWavesPerEU: 1
define amdgpu_kernel void @min_64_max_64() #0 { define amdgpu_kernel void @min_64_max_64() #0 {
entry: entry:
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llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck --check-prefix=CHECK %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck --check-prefix=CHECK %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -mattr=-code-object-v3 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=HSAMD %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 --amdhsa-code-object-version=2 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=HSAMD %s
; CHECK-LABEL: {{^}}min_64_max_64: ; CHECK-LABEL: {{^}}min_64_max_64:
; CHECK: SGPRBlocks: 0 ; CHECK: SGPRBlocks: 0
; CHECK: VGPRBlocks: 0 ; CHECK: VGPRBlocks: 0
; CHECK: NumSGPRsForWavesPerEU: 1 ; CHECK: NumSGPRsForWavesPerEU: 1
; CHECK: NumVGPRsForWavesPerEU: 1 ; CHECK: NumVGPRsForWavesPerEU: 1
define amdgpu_kernel void @min_64_max_64() #0 { define amdgpu_kernel void @min_64_max_64() #0 {
entry: entry:
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llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mattr=-code-object-v3 -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,CI %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=2 -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,CI %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mattr=-code-object-v3 -mcpu=fiji -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,VI-NOBUG %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=2 -mcpu=fiji -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,VI-NOBUG %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mattr=-code-object-v3 -mcpu=iceland -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,VI-BUG %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=2 -mcpu=iceland -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,VI-BUG %s
; Make sure to run a GPU with the SGPR allocation bug. ; Make sure to run a GPU with the SGPR allocation bug.
; GCN-LABEL: {{^}}use_vcc: ; GCN-LABEL: {{^}}use_vcc:
; GCN: ; NumSgprs: 34 ; GCN: ; NumSgprs: 34
; GCN: ; NumVgprs: 0 ; GCN: ; NumVgprs: 0
define void @use_vcc() #1 { define void @use_vcc() #1 {
call void asm sideeffect "", "~{vcc}" () #0 call void asm sideeffect "", "~{vcc}" () #0
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llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -mattr=-code-object-v3 -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=GCN,CIVI %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=GCN,CIVI %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-code-object-v3 -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=GCN,GFX9 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=2 -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=GCN,GFX9 %s
; GCN-LABEL: {{^}}use_dispatch_ptr: ; GCN-LABEL: {{^}}use_dispatch_ptr:
; GCN: s_load_dword s{{[0-9]+}}, s[4:5] ; GCN: s_load_dword s{{[0-9]+}}, s[4:5]
define hidden void @use_dispatch_ptr() #1 { define hidden void @use_dispatch_ptr() #1 {
%dispatch_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0 %dispatch_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0
%header_ptr = bitcast i8 addrspace(4)* %dispatch_ptr to i32 addrspace(4)* %header_ptr = bitcast i8 addrspace(4)* %dispatch_ptr to i32 addrspace(4)*
%value = load volatile i32, i32 addrspace(4)* %header_ptr %value = load volatile i32, i32 addrspace(4)* %header_ptr
ret void ret void
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llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -mattr=-code-object-v3 -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VARABI %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VARABI %s
; RUN: llc -amdgpu-fixed-function-abi -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -mattr=-code-object-v3 -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,FIXEDABI %s ; RUN: llc -amdgpu-fixed-function-abi -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,FIXEDABI %s
; GCN-LABEL: {{^}}use_workitem_id_x: ; GCN-LABEL: {{^}}use_workitem_id_x:
; GCN: s_waitcnt ; GCN: s_waitcnt
; VARABI: v_and_b32_e32 [[ID:v[0-9]+]], 0x3ff, v0 ; VARABI: v_and_b32_e32 [[ID:v[0-9]+]], 0x3ff, v0
; FIXEDABI: v_and_b32_e32 [[ID:v[0-9]+]], 0x3ff, v31 ; FIXEDABI: v_and_b32_e32 [[ID:v[0-9]+]], 0x3ff, v31
; GCN-NEXT: {{flat|global}}_store_dword v{{\[[0-9]:[0-9]+\]}}, [[ID]] ; GCN-NEXT: {{flat|global}}_store_dword v{{\[[0-9]:[0-9]+\]}}, [[ID]]
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
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llvm/test/CodeGen/AMDGPU/code-object-v3.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=ALL-ASM,OSABI-AMDHSA-ASM %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck --check-prefixes=ALL-ASM,OSABI-AMDHSA-ASM %s
; RUN: llc -filetype=obj -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -mattr=+code-object-v3 < %s | llvm-readelf --notes -relocations -sections -symbols - | FileCheck --check-prefixes=ALL-ELF,OSABI-AMDHSA-ELF %s ; RUN: llc -filetype=obj -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | llvm-readelf --notes -relocations -sections -symbols - | FileCheck --check-prefixes=ALL-ELF,OSABI-AMDHSA-ELF %s
; ALL-ASM-LABEL: {{^}}fadd: ; ALL-ASM-LABEL: {{^}}fadd:
; OSABI-AMDHSA-ASM-NOT: .hsa_code_object_version ; OSABI-AMDHSA-ASM-NOT: .hsa_code_object_version
; OSABI-AMDHSA-ASM-NOT: .hsa_code_object_isa ; OSABI-AMDHSA-ASM-NOT: .hsa_code_object_isa
; OSABI-AMDHSA-ASM-NOT: .amdgpu_hsa_kernel ; OSABI-AMDHSA-ASM-NOT: .amdgpu_hsa_kernel
; OSABI-AMDHSA-ASM-NOT: .amd_kernel_code_t ; OSABI-AMDHSA-ASM-NOT: .amd_kernel_code_t
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llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll

; RUN: llc -O0 -mtriple=amdgcn--amdhsa -march=amdgcn -amdgpu-spill-sgpr-to-vgpr=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=VMEM -check-prefix=GCN %s ; RUN: llc -O0 -mtriple=amdgcn--amdhsa -march=amdgcn --amdhsa-code-object-version=2 -amdgpu-spill-sgpr-to-vgpr=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=VMEM -check-prefix=GCN %s
; RUN: llc -O0 -mtriple=amdgcn--amdhsa -march=amdgcn -amdgpu-spill-sgpr-to-vgpr=1 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=VGPR -check-prefix=GCN %s ; RUN: llc -O0 -mtriple=amdgcn--amdhsa -march=amdgcn --amdhsa-code-object-version=2 -amdgpu-spill-sgpr-to-vgpr=1 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=VGPR -check-prefix=GCN %s
; Verify registers used for tracking exec mask changes when all ; Verify registers used for tracking exec mask changes when all
; registers are spilled at the end of the block. The SGPR spill ; registers are spilled at the end of the block. The SGPR spill
; placement relative to the exec modifications are important. ; placement relative to the exec modifications are important.
; FIXME: This checks with SGPR to VGPR spilling disabled, but this may ; FIXME: This checks with SGPR to VGPR spilling disabled, but this may
; not work correctly in cases where no workitems take a branch. ; not work correctly in cases where no workitems take a branch.
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llvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx600 -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX600 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx600 < %s | FileCheck --check-prefixes=GFX600 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tahiti -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX600 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tahiti < %s | FileCheck --check-prefixes=GFX600 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx601 -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX601 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx601 < %s | FileCheck --check-prefixes=GFX601 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=pitcairn -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX601 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=pitcairn < %s | FileCheck --check-prefixes=GFX601 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=verde -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX601 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=verde < %s | FileCheck --check-prefixes=GFX601 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx602 -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX602 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx602 < %s | FileCheck --check-prefixes=GFX602 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hainan -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX602 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hainan < %s | FileCheck --check-prefixes=GFX602 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=oland -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX602 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=oland < %s | FileCheck --check-prefixes=GFX602 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX700 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck --check-prefixes=GFX700 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX700 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri < %s | FileCheck --check-prefixes=GFX700 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx701 -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX701 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx701 < %s | FileCheck --check-prefixes=GFX701 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX701 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii < %s | FileCheck --check-prefixes=GFX701 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx702 -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX702 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx702 < %s | FileCheck --check-prefixes=GFX702 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx703 -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX703 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx703 < %s | FileCheck --check-prefixes=GFX703 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kabini -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX703 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kabini < %s | FileCheck --check-prefixes=GFX703 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=mullins -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX703 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=mullins < %s | FileCheck --check-prefixes=GFX703 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx704 -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX704 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx704 < %s | FileCheck --check-prefixes=GFX704 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=bonaire -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX704 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=bonaire < %s | FileCheck --check-prefixes=GFX704 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx705 -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX705 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx705 < %s | FileCheck --check-prefixes=GFX705 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx801 -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX801 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx801 < %s | FileCheck --check-prefixes=GFX801 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=carrizo -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX801 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=carrizo < %s | FileCheck --check-prefixes=GFX801 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx802 -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX802 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx802 < %s | FileCheck --check-prefixes=GFX802 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=iceland -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX802 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=iceland < %s | FileCheck --check-prefixes=GFX802 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX802 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga < %s | FileCheck --check-prefixes=GFX802 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX803 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck --check-prefixes=GFX803 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX803 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck --check-prefixes=GFX803 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=polaris10 -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX803 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=polaris10 < %s | FileCheck --check-prefixes=GFX803 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=polaris11 -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX803 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=polaris11 < %s | FileCheck --check-prefixes=GFX803 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx805 -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX805 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx805 < %s | FileCheck --check-prefixes=GFX805 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tongapro -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX805 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tongapro < %s | FileCheck --check-prefixes=GFX805 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx810 -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX810 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx810 < %s | FileCheck --check-prefixes=GFX810 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=stoney -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX810 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=stoney < %s | FileCheck --check-prefixes=GFX810 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX900 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck --check-prefixes=GFX900 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx902 -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX902 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx902 < %s | FileCheck --check-prefixes=GFX902 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx904 -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX904 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx904 < %s | FileCheck --check-prefixes=GFX904 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -mattr=+code-object-v3 < %s | FileCheck --check-prefixes=GFX906 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 < %s | FileCheck --check-prefixes=GFX906 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+code-object-v3,+xnack < %s | FileCheck --check-prefixes=XNACK-GFX900 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+xnack < %s | FileCheck --check-prefixes=XNACK-GFX900 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx902 -mattr=+code-object-v3,-xnack < %s | FileCheck --check-prefixes=NO-XNACK-GFX902 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx902 -mattr=-xnack < %s | FileCheck --check-prefixes=NO-XNACK-GFX902 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx904 -mattr=+code-object-v3,+sram-ecc < %s | FileCheck --check-prefixes=SRAM-ECC-GFX904 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx904 -mattr=+sram-ecc < %s | FileCheck --check-prefixes=SRAM-ECC-GFX904 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -mattr=+code-object-v3,+sram-ecc < %s | FileCheck --check-prefixes=SRAM-ECC-GFX906 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -mattr=+sram-ecc < %s | FileCheck --check-prefixes=SRAM-ECC-GFX906 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx904 -mattr=+code-object-v3,+sram-ecc,+xnack < %s | FileCheck --check-prefixes=SRAM-ECC-XNACK-GFX904 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx904 -mattr=+sram-ecc,+xnack < %s | FileCheck --check-prefixes=SRAM-ECC-XNACK-GFX904 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -mattr=+code-object-v3,+sram-ecc,+xnack < %s | FileCheck --check-prefixes=SRAM-ECC-XNACK-GFX906 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -mattr=+sram-ecc,+xnack < %s | FileCheck --check-prefixes=SRAM-ECC-XNACK-GFX906 %s
; GFX600: .amdgcn_target "amdgcn-amd-amdhsa--gfx600" ; GFX600: .amdgcn_target "amdgcn-amd-amdhsa--gfx600"
; GFX601: .amdgcn_target "amdgcn-amd-amdhsa--gfx601" ; GFX601: .amdgcn_target "amdgcn-amd-amdhsa--gfx601"
; GFX602: .amdgcn_target "amdgcn-amd-amdhsa--gfx602" ; GFX602: .amdgcn_target "amdgcn-amd-amdhsa--gfx602"
; GFX700: .amdgcn_target "amdgcn-amd-amdhsa--gfx700" ; GFX700: .amdgcn_target "amdgcn-amd-amdhsa--gfx700"
; GFX701: .amdgcn_target "amdgcn-amd-amdhsa--gfx701" ; GFX701: .amdgcn_target "amdgcn-amd-amdhsa--gfx701"
; GFX702: .amdgcn_target "amdgcn-amd-amdhsa--gfx702" ; GFX702: .amdgcn_target "amdgcn-amd-amdhsa--gfx702"
; GFX703: .amdgcn_target "amdgcn-amd-amdhsa--gfx703" ; GFX703: .amdgcn_target "amdgcn-amd-amdhsa--gfx703"
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llvm/test/CodeGen/AMDGPU/elf-notes.ll

; RUN: llc -mtriple=amdgcn-amd-unknown -mcpu=gfx802 -mattr=-code-object-v3 < %s | FileCheck --check-prefix=GCN --check-prefix=OSABI-UNK --check-prefix=GFX802 %s ; RUN: llc -mtriple=amdgcn-amd-unknown -mcpu=gfx802 --amdhsa-code-object-version=2 < %s | FileCheck --check-prefix=GCN --check-prefix=OSABI-UNK --check-prefix=GFX802 %s
; RUN: llc -mtriple=amdgcn-amd-unknown -mcpu=iceland -mattr=-code-object-v3 < %s | FileCheck --check-prefix=GCN --check-prefix=OSABI-UNK --check-prefix=GFX802 %s ; RUN: llc -mtriple=amdgcn-amd-unknown -mcpu=iceland --amdhsa-code-object-version=2 < %s | FileCheck --check-prefix=GCN --check-prefix=OSABI-UNK --check-prefix=GFX802 %s
; RUN: llc -mtriple=amdgcn-amd-unknown -mcpu=gfx802 -filetype=obj -mattr=-code-object-v3 < %s | llvm-readelf --notes - | FileCheck --check-prefix=GCN --check-prefix=OSABI-UNK-ELF --check-prefix=GFX802 %s ; RUN: llc -mtriple=amdgcn-amd-unknown -mcpu=gfx802 -filetype=obj --amdhsa-code-object-version=2 < %s | llvm-readelf --notes - | FileCheck --check-prefix=GCN --check-prefix=OSABI-UNK-ELF --check-prefix=GFX802 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx802 -mattr=-code-object-v3 < %s | FileCheck --check-prefix=GCN --check-prefix=OSABI-HSA --check-prefix=GFX802 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx802 --amdhsa-code-object-version=2 < %s | FileCheck --check-prefix=GCN --check-prefix=OSABI-HSA --check-prefix=GFX802 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=iceland -mattr=-code-object-v3 < %s | FileCheck --check-prefix=GCN --check-prefix=OSABI-HSA --check-prefix=GFX802 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=iceland --amdhsa-code-object-version=2 < %s | FileCheck --check-prefix=GCN --check-prefix=OSABI-HSA --check-prefix=GFX802 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx802 -filetype=obj -mattr=-code-object-v3 < %s | llvm-readelf --notes - | FileCheck --check-prefix=GCN --check-prefix=OSABI-HSA-ELF --check-prefix=GFX802 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx802 -filetype=obj --amdhsa-code-object-version=2 < %s | llvm-readelf --notes - | FileCheck --check-prefix=GCN --check-prefix=OSABI-HSA-ELF --check-prefix=GFX802 %s
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx802 -mattr=-code-object-v3 < %s | FileCheck --check-prefix=GCN --check-prefix=OSABI-PAL --check-prefix=GFX802 %s ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx802 --amdhsa-code-object-version=2 < %s | FileCheck --check-prefix=GCN --check-prefix=OSABI-PAL --check-prefix=GFX802 %s
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=iceland -mattr=-code-object-v3 < %s | FileCheck --check-prefix=GCN --check-prefix=OSABI-PAL --check-prefix=GFX802 %s ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=iceland --amdhsa-code-object-version=2 < %s | FileCheck --check-prefix=GCN --check-prefix=OSABI-PAL --check-prefix=GFX802 %s
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx802 -filetype=obj -mattr=-code-object-v3 < %s | llvm-readelf --notes - | FileCheck --check-prefix=GCN --check-prefix=OSABI-PAL-ELF --check-prefix=GFX802 %s ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx802 -filetype=obj --amdhsa-code-object-version=2 < %s | llvm-readelf --notes - | FileCheck --check-prefix=GCN --check-prefix=OSABI-PAL-ELF --check-prefix=GFX802 %s
; RUN: llc -march=r600 < %s | FileCheck --check-prefix=R600 %s ; RUN: llc -march=r600 < %s | FileCheck --check-prefix=R600 %s
; OSABI-UNK-NOT: .hsa_code_object_version ; OSABI-UNK-NOT: .hsa_code_object_version
; OSABI-UNK-NOT: .hsa_code_object_isa ; OSABI-UNK-NOT: .hsa_code_object_isa
; OSABI-UNK: .amd_amdgpu_isa "amdgcn-amd-unknown--gfx802" ; OSABI-UNK: .amd_amdgpu_isa "amdgcn-amd-unknown--gfx802"
; OSABI-UNK-NOT: .amd_amdgpu_hsa_metadata ; OSABI-UNK-NOT: .amd_amdgpu_hsa_metadata
; OSABI-UNK-NOT: .amd_amdgpu_pal_metadata ; OSABI-UNK-NOT: .amd_amdgpu_pal_metadata
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llvm/test/CodeGen/AMDGPU/flat-for-global-subtarget-feature.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-code-object-v3,+flat-for-global < %s | FileCheck -check-prefix=HSA -check-prefix=HSA-DEFAULT -check-prefix=ALL %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -mattr=+flat-for-global < %s | FileCheck -check-prefix=HSA -check-prefix=HSA-DEFAULT -check-prefix=ALL %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-code-object-v3,-flat-for-global < %s | FileCheck -check-prefix=HSA -check-prefix=HSA-NODEFAULT -check-prefix=ALL %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -mattr=-flat-for-global < %s | FileCheck -check-prefix=HSA -check-prefix=HSA-NODEFAULT -check-prefix=ALL %s
; RUN: llc -mtriple=amdgcn-- -mcpu=tonga < %s | FileCheck -check-prefix=HSA-NOADDR64 -check-prefix=ALL %s ; RUN: llc -mtriple=amdgcn-- -mcpu=tonga < %s | FileCheck -check-prefix=HSA-NOADDR64 -check-prefix=ALL %s
; RUN: llc -mtriple=amdgcn-- -mcpu=kaveri -mattr=-flat-for-global < %s | FileCheck -check-prefix=NOHSA-DEFAULT -check-prefix=ALL %s ; RUN: llc -mtriple=amdgcn-- -mcpu=kaveri -mattr=-flat-for-global < %s | FileCheck -check-prefix=NOHSA-DEFAULT -check-prefix=ALL %s
; RUN: llc -mtriple=amdgcn-- -mcpu=kaveri -mattr=+flat-for-global < %s | FileCheck -check-prefix=NOHSA-NODEFAULT -check-prefix=ALL %s ; RUN: llc -mtriple=amdgcn-- -mcpu=kaveri -mattr=+flat-for-global < %s | FileCheck -check-prefix=NOHSA-NODEFAULT -check-prefix=ALL %s
; RUN: llc -mtriple=amdgcn-- -mcpu=tonga < %s | FileCheck -check-prefix=NOHSA-NOADDR64 -check-prefix=ALL %s ; RUN: llc -mtriple=amdgcn-- -mcpu=tonga < %s | FileCheck -check-prefix=NOHSA-NOADDR64 -check-prefix=ALL %s
; There are no stack objects even though flat is used by default, so ; There are no stack objects even though flat is used by default, so
; flat_scratch_init should be disabled. ; flat_scratch_init should be disabled.
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llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll

; RUN: llc -march=amdgcn -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=VI-NOXNACK -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=VI-NOXNACK -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=carrizo -mattr=-xnack -verify-machineinstrs < %s | FileCheck -check-prefix=VI-NOXNACK -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=carrizo -mattr=-xnack -verify-machineinstrs < %s | FileCheck -check-prefix=VI-NOXNACK -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=stoney -mattr=-xnack -verify-machineinstrs < %s | FileCheck -check-prefix=VI-NOXNACK -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=stoney -mattr=-xnack -verify-machineinstrs < %s | FileCheck -check-prefix=VI-NOXNACK -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=carrizo -verify-machineinstrs < %s | FileCheck -check-prefix=VI-XNACK -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=carrizo -verify-machineinstrs < %s | FileCheck -check-prefix=VI-XNACK -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=stoney -verify-machineinstrs < %s | FileCheck -check-prefix=VI-XNACK -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=stoney -verify-machineinstrs < %s | FileCheck -check-prefix=VI-XNACK -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-code-object-v3 -verify-machineinstrs < %s | FileCheck -check-prefix=HSA-CI -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -verify-machineinstrs < %s | FileCheck -check-prefix=HSA-CI -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=carrizo -mattr=-code-object-v3,-xnack -verify-machineinstrs < %s | FileCheck -check-prefix=HSA-VI-NOXNACK -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=carrizo --amdhsa-code-object-version=2 -mattr=-xnack -verify-machineinstrs < %s | FileCheck -check-prefix=HSA-VI-NOXNACK -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=carrizo -mattr=-code-object-v3,+xnack -verify-machineinstrs < %s | FileCheck -check-prefix=HSA-VI-XNACK -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=carrizo --amdhsa-code-object-version=2 -mattr=+xnack -verify-machineinstrs < %s | FileCheck -check-prefix=HSA-VI-XNACK -check-prefix=GCN %s
; GCN-LABEL: {{^}}no_vcc_no_flat: ; GCN-LABEL: {{^}}no_vcc_no_flat:
; HSA-CI: is_xnack_enabled = 0 ; HSA-CI: is_xnack_enabled = 0
; HSA-VI-NOXNACK: is_xnack_enabled = 0 ; HSA-VI-NOXNACK: is_xnack_enabled = 0
; HSA-VI-XNACK: is_xnack_enabled = 1 ; HSA-VI-XNACK: is_xnack_enabled = 1
; CI: ; NumSgprs: 8 ; CI: ; NumSgprs: 8
; VI-NOXNACK: ; NumSgprs: 8 ; VI-NOXNACK: ; NumSgprs: 8
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llvm/test/CodeGen/AMDGPU/gfx902-without-xnack.ll

; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=gfx902 -mattr=-code-object-v3,-xnack < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-amd-amdhsa -mcpu=gfx902 --amdhsa-code-object-version=2 -mattr=-xnack < %s | FileCheck %s
; CHECK: .hsa_code_object_isa 9,0,2,"AMD","AMDGPU" ; CHECK: .hsa_code_object_isa 9,0,2,"AMD","AMDGPU"
define amdgpu_kernel void @test_kernel(float addrspace(1)* %out0, double addrspace(1)* %out1) nounwind { define amdgpu_kernel void @test_kernel(float addrspace(1)* %out0, double addrspace(1)* %out1) nounwind {
store float 0.0, float addrspace(1)* %out0 store float 0.0, float addrspace(1)* %out0
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/hsa-default-device.ll

; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=2 < %s | FileCheck %s
; Make sure that with an HSA triple, we don't default to an ; Make sure that with an HSA triple, we don't default to an
; unsupported device. ; unsupported device.
; CHECK: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU" ; CHECK: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU"
define amdgpu_kernel void @test_kernel(float addrspace(1)* %out0, double addrspace(1)* %out1) nounwind { define amdgpu_kernel void @test_kernel(float addrspace(1)* %out0, double addrspace(1)* %out1) nounwind {
store float 0.0, float addrspace(1)* %out0 store float 0.0, float addrspace(1)* %out0
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll

; RUN: llc -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}test_default_ci: ; GCN-LABEL: {{^}}test_default_ci:
; GCN: float_mode = 240 ; GCN: float_mode = 240
; GCN: enable_dx10_clamp = 1 ; GCN: enable_dx10_clamp = 1
; GCN: enable_ieee_mode = 1 ; GCN: enable_ieee_mode = 1
define amdgpu_kernel void @test_default_ci(float addrspace(1)* %out0, double addrspace(1)* %out1) #0 { define amdgpu_kernel void @test_default_ci(float addrspace(1)* %out0, double addrspace(1)* %out1) #0 {
store float 0.0, float addrspace(1)* %out0 store float 0.0, float addrspace(1)* %out0
store double 0.0, double addrspace(1)* %out1 store double 0.0, double addrspace(1)* %out1
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; GCN: enable_dx10_clamp = 0 ; GCN: enable_dx10_clamp = 0
; GCN: enable_ieee_mode = 0 ; GCN: enable_ieee_mode = 0
define amdgpu_kernel void @test_no_ieee_mode_no_dx10_clamp_vi(float addrspace(1)* %out0, double addrspace(1)* %out1) #8 { define amdgpu_kernel void @test_no_ieee_mode_no_dx10_clamp_vi(float addrspace(1)* %out0, double addrspace(1)* %out1) #8 {
store float 0.0, float addrspace(1)* %out0 store float 0.0, float addrspace(1)* %out0
store double 0.0, double addrspace(1)* %out1 store double 0.0, double addrspace(1)* %out1
ret void ret void
} }
attributes #0 = { nounwind "target-cpu"="kaveri" "target-features"="-code-object-v3" } attributes #0 = { nounwind "target-cpu"="kaveri" }
attributes #1 = { nounwind "target-cpu"="fiji" "target-features"="-code-object-v3" } attributes #1 = { nounwind "target-cpu"="fiji" }
attributes #2 = { nounwind "target-features"="-code-object-v3" "denormal-fp-math-f32"="preserve-sign,preserve-sign" } attributes #2 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
attributes #3 = { nounwind "target-features"="-code-object-v3" "denormal-fp-math-f32"="ieee,ieee" "denormal-fp-math"="preserve-sign,preserve-sign" } attributes #3 = { nounwind "denormal-fp-math-f32"="ieee,ieee" "denormal-fp-math"="preserve-sign,preserve-sign" }
attributes #4 = { nounwind "target-features"="-code-object-v3" "denormal-fp-math"="ieee,ieee" } attributes #4 = { nounwind "denormal-fp-math"="ieee,ieee" }
attributes #5 = { nounwind "target-features"="-code-object-v3" "denormal-fp-math"="preserve-sign,preserve-sign" } attributes #5 = { nounwind "denormal-fp-math"="preserve-sign,preserve-sign" }
attributes #6 = { nounwind "amdgpu-dx10-clamp"="false" "target-cpu"="fiji" "target-features"="-code-object-v3" } attributes #6 = { nounwind "amdgpu-dx10-clamp"="false" "target-cpu"="fiji" }
attributes #7 = { nounwind "amdgpu-ieee"="false" "target-cpu"="fiji" "target-features"="-code-object-v3" } attributes #7 = { nounwind "amdgpu-ieee"="false" "target-cpu"="fiji" }
attributes #8 = { nounwind "amdgpu-dx10-clamp"="false" "amdgpu-ieee"="false" "target-cpu"="fiji" "target-features"="-code-object-v3" } attributes #8 = { nounwind "amdgpu-dx10-clamp"="false" "amdgpu-ieee"="false" "target-cpu"="fiji" }

llvm/test/CodeGen/AMDGPU/hsa-func.ll

; RUN: llc < %s -mtriple=amdgcn--amdhsa -mattr=-code-object-v3 -mcpu=kaveri | FileCheck --check-prefix=HSA %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -mcpu=kaveri | FileCheck --check-prefix=HSA %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mattr=-code-object-v3 -mcpu=kaveri | FileCheck --check-prefix=HSA-CI %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -mcpu=kaveri | FileCheck --check-prefix=HSA-CI %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mattr=-code-object-v3 -mcpu=carrizo | FileCheck --check-prefix=HSA %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -mcpu=carrizo | FileCheck --check-prefix=HSA %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mattr=-code-object-v3 -mcpu=carrizo | FileCheck --check-prefix=HSA-VI %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -mcpu=carrizo | FileCheck --check-prefix=HSA-VI %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mattr=-code-object-v3 -mcpu=kaveri -filetype=obj | llvm-readobj --symbols -S --sd - | FileCheck --check-prefix=ELF %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -mcpu=kaveri -filetype=obj | llvm-readobj --symbols -S --sd - | FileCheck --check-prefix=ELF %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mattr=-code-object-v3 -mcpu=kaveri | llvm-mc -filetype=obj -triple amdgcn--amdhsa -mattr=-code-object-v3 -mcpu=kaveri | llvm-readobj --symbols -S --sd - | FileCheck %s --check-prefix=ELF ; RUN: llc < %s -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -mcpu=kaveri | llvm-mc -filetype=obj -triple amdgcn--amdhsa --amdhsa-code-object-version=2 -mcpu=kaveri | llvm-readobj --symbols -S --sd - | FileCheck %s --check-prefix=ELF
; The SHT_NOTE section contains the output from the .hsa_code_object_* ; The SHT_NOTE section contains the output from the .hsa_code_object_*
; directives. ; directives.
; ELF: Section { ; ELF: Section {
; ELF: Name: .text ; ELF: Name: .text
; ELF: Type: SHT_PROGBITS (0x1) ; ELF: Type: SHT_PROGBITS (0x1)
; ELF: Flags [ (0x6) ; ELF: Flags [ (0x6)
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llvm/test/CodeGen/AMDGPU/hsa-metadata-deduce-ro-arg-v3.ll

; RUN: llc -mattr=+code-object-v3 -mtriple=amdgcn-amd-amdhsa -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s
; CHECK: - .args: ; CHECK: - .args:
; CHECK-NEXT: - .access: read_only ; CHECK-NEXT: - .access: read_only
; CHECK-NEXT: .address_space: global ; CHECK-NEXT: .address_space: global
; CHECK-NEXT: .is_const: true ; CHECK-NEXT: .is_const: true
; CHECK-NEXT: .is_restrict: true ; CHECK-NEXT: .is_restrict: true
; CHECK-NEXT: .name: in ; CHECK-NEXT: .name: in
; CHECK-NEXT: .offset: 0 ; CHECK-NEXT: .offset: 0
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llvm/test/CodeGen/AMDGPU/hsa-metadata-deduce-ro-arg.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=2 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s
; CHECK: - Name: test_ro_arg ; CHECK: - Name: test_ro_arg
; CHECK-NEXT: SymbolName: 'test_ro_arg@kd' ; CHECK-NEXT: SymbolName: 'test_ro_arg@kd'
; CHECK-NEXT: Args: ; CHECK-NEXT: Args:
; CHECK-NEXT: - Name: in ; CHECK-NEXT: - Name: in
; CHECK-NEXT: TypeName: 'float*' ; CHECK-NEXT: TypeName: 'float*'
; CHECK-NEXT: Size: 8 ; CHECK-NEXT: Size: 8
; CHECK-NEXT: Align: 8 ; CHECK-NEXT: Align: 8
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llvm/test/CodeGen/AMDGPU/hsa-metadata-enqueue-kernel-v3.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mattr=+code-object-v3 -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX900 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX900 --check-prefix=NOTES %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mattr=+code-object-v3 -mcpu=gfx900 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s
; CHECK: --- ; CHECK: ---
; CHECK: amdhsa.kernels: ; CHECK: amdhsa.kernels:
; CHECK: - .args: ; CHECK: - .args:
; CHECK-NEXT: - .name: a ; CHECK-NEXT: - .name: a
; CHECK-NEXT: .offset: 0 ; CHECK-NEXT: .offset: 0
; CHECK-NEXT: .size: 1 ; CHECK-NEXT: .size: 1
; CHECK-NEXT: .type_name: char ; CHECK-NEXT: .type_name: char
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llvm/test/CodeGen/AMDGPU/hsa-metadata-enqueue-kernel.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mattr=-code-object-v3 -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX900 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=2 -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX900 --check-prefix=NOTES %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mattr=-code-object-v3 -mcpu=gfx900 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=2 -mcpu=gfx900 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s
; CHECK: --- ; CHECK: ---
; CHECK: Version: [ 1, 0 ] ; CHECK: Version: [ 1, 0 ]
; CHECK-NOT: Printf: ; CHECK-NOT: Printf:
; CHECK: Kernels: ; CHECK: Kernels:
; CHECK: - Name: test_non_enqueue_kernel_caller ; CHECK: - Name: test_non_enqueue_kernel_caller
; CHECK-NEXT: SymbolName: 'test_non_enqueue_kernel_caller@kd' ; CHECK-NEXT: SymbolName: 'test_non_enqueue_kernel_caller@kd'
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llvm/test/CodeGen/AMDGPU/hsa-metadata-from-llvm-ir-full-v3.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -mattr=+code-object-v3 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX700 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX700 --check-prefix=NOTES %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx802 -mattr=+code-object-v3 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX802 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx802 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX802 --check-prefix=NOTES %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+code-object-v3 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX900 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX900 --check-prefix=NOTES %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -mattr=+code-object-v3 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx802 -mattr=+code-object-v3 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx802 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+code-object-v3 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s
%struct.A = type { i8, float } %struct.A = type { i8, float }
%opencl.image1d_t = type opaque %opencl.image1d_t = type opaque
%opencl.image2d_t = type opaque %opencl.image2d_t = type opaque
%opencl.image3d_t = type opaque %opencl.image3d_t = type opaque
%opencl.queue_t = type opaque %opencl.queue_t = type opaque
%opencl.pipe_t = type opaque %opencl.pipe_t = type opaque
%struct.B = type { i32 addrspace(1)*} %struct.B = type { i32 addrspace(1)*}
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llvm/test/CodeGen/AMDGPU/hsa-metadata-from-llvm-ir-full.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -mattr=-code-object-v3 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX700 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 --amdhsa-code-object-version=2 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX700 --check-prefix=NOTES %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx802 -mattr=-code-object-v3 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX802 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx802 --amdhsa-code-object-version=2 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX802 --check-prefix=NOTES %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-code-object-v3 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX900 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=2 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX900 --check-prefix=NOTES %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -mattr=-code-object-v3 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 --amdhsa-code-object-version=2 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx802 -mattr=-code-object-v3 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx802 --amdhsa-code-object-version=2 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-code-object-v3 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=2 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s
%struct.A = type { i8, float } %struct.A = type { i8, float }
%opencl.image1d_t = type opaque %opencl.image1d_t = type opaque
%opencl.image2d_t = type opaque %opencl.image2d_t = type opaque
%opencl.image3d_t = type opaque %opencl.image3d_t = type opaque
%opencl.queue_t = type opaque %opencl.queue_t = type opaque
%opencl.pipe_t = type opaque %opencl.pipe_t = type opaque
%struct.B = type { i32 addrspace(1)*} %struct.B = type { i32 addrspace(1)*}
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llvm/test/CodeGen/AMDGPU/hsa-metadata-hidden-args-v3.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -mattr=+code-object-v3 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX700 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX700 --check-prefix=NOTES %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -mattr=+code-object-v3 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX803 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX803 --check-prefix=NOTES %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+code-object-v3 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX900 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX900 --check-prefix=NOTES %s
; CHECK: --- ; CHECK: ---
; CHECK: amdhsa.kernels: ; CHECK: amdhsa.kernels:
; CHECK: - .args: ; CHECK: - .args:
; CHECK-NEXT: - .address_space: global ; CHECK-NEXT: - .address_space: global
; CHECK-NEXT: .name: r ; CHECK-NEXT: .name: r
; CHECK-NEXT: .offset: 0 ; CHECK-NEXT: .offset: 0
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llvm/test/CodeGen/AMDGPU/hsa-metadata-hidden-args.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -mattr=-code-object-v3 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX700 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 --amdhsa-code-object-version=2 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX700 --check-prefix=NOTES %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -mattr=-code-object-v3 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX803 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 --amdhsa-code-object-version=2 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX803 --check-prefix=NOTES %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-code-object-v3 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX900 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=2 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX900 --check-prefix=NOTES %s
; CHECK: --- ; CHECK: ---
; CHECK: Version: [ 1, 0 ] ; CHECK: Version: [ 1, 0 ]
; CHECK: Kernels: ; CHECK: Kernels:
; CHECK: - Name: test0 ; CHECK: - Name: test0
; CHECK: SymbolName: 'test0@kd' ; CHECK: SymbolName: 'test0@kd'
; CHECK: Args: ; CHECK: Args:
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llvm/test/CodeGen/AMDGPU/hsa-metadata-hostcall-absent-v3.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mattr=+code-object-v3 -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mattr=+code-object-v3 -mcpu=gfx900 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s
; CHECK: --- ; CHECK: ---
; CHECK: amdhsa.kernels: ; CHECK: amdhsa.kernels:
; CHECK: - .args: ; CHECK: - .args:
; CHECK-NEXT: - .name: a ; CHECK-NEXT: - .name: a
; CHECK-NEXT: .offset: 0 ; CHECK-NEXT: .offset: 0
; CHECK-NEXT: .size: 1 ; CHECK-NEXT: .size: 1
; CHECK-NEXT: .type_name: char ; CHECK-NEXT: .type_name: char
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llvm/test/CodeGen/AMDGPU/hsa-metadata-hostcall-absent.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mattr=-code-object-v3 -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=2 -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mattr=-code-object-v3 -mcpu=gfx900 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=2 -mcpu=gfx900 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s
; CHECK: --- ; CHECK: ---
; CHECK: Version: [ 1, 0 ] ; CHECK: Version: [ 1, 0 ]
; CHECK: Kernels: ; CHECK: Kernels:
; CHECK: - Name: test_kernel ; CHECK: - Name: test_kernel
; CHECK-NEXT: SymbolName: 'test_kernel@kd' ; CHECK-NEXT: SymbolName: 'test_kernel@kd'
; CHECK-NEXT: Language: OpenCL C ; CHECK-NEXT: Language: OpenCL C
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llvm/test/CodeGen/AMDGPU/hsa-metadata-hostcall-present-v3.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mattr=+code-object-v3 -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mattr=+code-object-v3 -mcpu=gfx900 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s
; CHECK: --- ; CHECK: ---
; CHECK: amdhsa.kernels: ; CHECK: amdhsa.kernels:
; CHECK: - .args: ; CHECK: - .args:
; CHECK-NEXT: - .name: a ; CHECK-NEXT: - .name: a
; CHECK-NEXT: .offset: 0 ; CHECK-NEXT: .offset: 0
; CHECK-NEXT: .size: 1 ; CHECK-NEXT: .size: 1
; CHECK-NEXT: .type_name: char ; CHECK-NEXT: .type_name: char
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llvm/test/CodeGen/AMDGPU/hsa-metadata-hostcall-present.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mattr=-code-object-v3 -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=2 -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mattr=-code-object-v3 -mcpu=gfx900 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=2 -mcpu=gfx900 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s
; CHECK: --- ; CHECK: ---
; CHECK: Version: [ 1, 0 ] ; CHECK: Version: [ 1, 0 ]
; CHECK: Kernels: ; CHECK: Kernels:
; CHECK: - Name: test_kernel ; CHECK: - Name: test_kernel
; CHECK-NEXT: SymbolName: 'test_kernel@kd' ; CHECK-NEXT: SymbolName: 'test_kernel@kd'
; CHECK-NEXT: Language: OpenCL C ; CHECK-NEXT: Language: OpenCL C
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llvm/test/CodeGen/AMDGPU/hsa-metadata-images-v3.ll

; RUN: llc -mattr=+code-object-v3 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX700 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX700 --check-prefix=NOTES %s
; RUN: llc -mattr=+code-object-v3 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx802 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX802 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx802 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX802 --check-prefix=NOTES %s
; RUN: llc -mattr=+code-object-v3 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX900 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX900 --check-prefix=NOTES %s
%opencl.image1d_t = type opaque %opencl.image1d_t = type opaque
%opencl.image1d_array_t = type opaque %opencl.image1d_array_t = type opaque
%opencl.image1d_buffer_t = type opaque %opencl.image1d_buffer_t = type opaque
%opencl.image2d_t = type opaque %opencl.image2d_t = type opaque
%opencl.image2d_array_t = type opaque %opencl.image2d_array_t = type opaque
%opencl.image2d_array_depth_t = type opaque %opencl.image2d_array_depth_t = type opaque
%opencl.image2d_array_msaa_t = type opaque %opencl.image2d_array_msaa_t = type opaque
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llvm/test/CodeGen/AMDGPU/hsa-metadata-images.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -mattr=-code-object-v3 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX700 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 --amdhsa-code-object-version=2 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX700 --check-prefix=NOTES %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx802 -mattr=-code-object-v3 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX802 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx802 --amdhsa-code-object-version=2 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX802 --check-prefix=NOTES %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-code-object-v3 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX900 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=2 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX900 --check-prefix=NOTES %s
%opencl.image1d_t = type opaque %opencl.image1d_t = type opaque
%opencl.image1d_array_t = type opaque %opencl.image1d_array_t = type opaque
%opencl.image1d_buffer_t = type opaque %opencl.image1d_buffer_t = type opaque
%opencl.image2d_t = type opaque %opencl.image2d_t = type opaque
%opencl.image2d_array_t = type opaque %opencl.image2d_array_t = type opaque
%opencl.image2d_array_depth_t = type opaque %opencl.image2d_array_depth_t = type opaque
%opencl.image2d_array_msaa_t = type opaque %opencl.image2d_array_msaa_t = type opaque
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llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-1-v3.ll

; RUN: llc -mattr=+code-object-v3 -mtriple=amdgcn-amd-amdhsa -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s
; Make sure llc does not crash for invalid opencl version metadata. ; Make sure llc does not crash for invalid opencl version metadata.
; CHECK: --- ; CHECK: ---
; CHECK: amdhsa.version: ; CHECK: amdhsa.version:
; CHECK-NEXT: - 1 ; CHECK-NEXT: - 1
; CHECK-NEXT: - 0 ; CHECK-NEXT: - 0
; CHECK: ... ; CHECK: ...
!opencl.ocl.version = !{} !opencl.ocl.version = !{}

llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-1.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=2 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s
; Make sure llc does not crash for invalid opencl version metadata. ; Make sure llc does not crash for invalid opencl version metadata.
; CHECK: --- ; CHECK: ---
; CHECK: Version: [ 1, 0 ] ; CHECK: Version: [ 1, 0 ]
; CHECK: ... ; CHECK: ...
!opencl.ocl.version = !{} !opencl.ocl.version = !{}

llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-2-v3.ll

; RUN: llc -mattr=+code-object-v3 -mtriple=amdgcn-amd-amdhsa -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s
; Make sure llc does not crash for invalid opencl version metadata. ; Make sure llc does not crash for invalid opencl version metadata.
; CHECK: --- ; CHECK: ---
; CHECK: amdhsa.version: ; CHECK: amdhsa.version:
; CHECK-NEXT: - 1 ; CHECK-NEXT: - 1
; CHECK-NEXT: - 0 ; CHECK-NEXT: - 0
; CHECK: ... ; CHECK: ...
!opencl.ocl.version = !{!0} !opencl.ocl.version = !{!0}
!0 = !{} !0 = !{}

llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-2.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=2 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s
; Make sure llc does not crash for invalid opencl version metadata. ; Make sure llc does not crash for invalid opencl version metadata.
; CHECK: --- ; CHECK: ---
; CHECK: Version: [ 1, 0 ] ; CHECK: Version: [ 1, 0 ]
; CHECK: ... ; CHECK: ...
!opencl.ocl.version = !{!0} !opencl.ocl.version = !{!0}
!0 = !{} !0 = !{}

llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-3-v3.ll

; RUN: llc -mattr=+code-object-v3 -mtriple=amdgcn-amd-amdhsa -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s
; Make sure llc does not crash for invalid opencl version metadata. ; Make sure llc does not crash for invalid opencl version metadata.
; CHECK: --- ; CHECK: ---
; CHECK: amdhsa.version: ; CHECK: amdhsa.version:
; CHECK-NEXT: - 1 ; CHECK-NEXT: - 1
; CHECK-NEXT: - 0 ; CHECK-NEXT: - 0
; CHECK: ... ; CHECK: ...
!opencl.ocl.version = !{!0} !opencl.ocl.version = !{!0}
!0 = !{i32 1} !0 = !{i32 1}

llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-3.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=2 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s
; Make sure llc does not crash for invalid opencl version metadata. ; Make sure llc does not crash for invalid opencl version metadata.
; CHECK: --- ; CHECK: ---
; CHECK: Version: [ 1, 0 ] ; CHECK: Version: [ 1, 0 ]
; CHECK: ... ; CHECK: ...
!opencl.ocl.version = !{!0} !opencl.ocl.version = !{!0}
!0 = !{i32 1} !0 = !{i32 1}

llvm/test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props-v3.ll

; RUN: llc -mattr=+code-object-v3 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -enable-misched=0 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX700 --check-prefix=WAVE64 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -enable-misched=0 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX700 --check-prefix=WAVE64 --check-prefix=NOTES %s
; RUN: llc -mattr=+code-object-v3 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -enable-misched=0 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX803 --check-prefix=WAVE64 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -enable-misched=0 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX803 --check-prefix=WAVE64 --check-prefix=NOTES %s
; RUN: llc -mattr=+code-object-v3 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -enable-misched=0 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX900 --check-prefix=WAVE64 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -enable-misched=0 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX900 --check-prefix=WAVE64 --check-prefix=NOTES %s
; RUN: llc -mattr=+code-object-v3 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -enable-misched=0 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX1010 --check-prefix=WAVE32 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -enable-misched=0 -filetype=obj -o - < %s | llvm-readobj -elf-output-style=GNU -notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX1010 --check-prefix=WAVE32 --check-prefix=NOTES %s
@var = addrspace(1) global float 0.0 @var = addrspace(1) global float 0.0
; CHECK: --- ; CHECK: ---
; CHECK: amdhsa.kernels: ; CHECK: amdhsa.kernels:
; CHECK: - .args: ; CHECK: - .args:
; CHECK: .group_segment_fixed_size: 0 ; CHECK: .group_segment_fixed_size: 0
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llvm/test/CodeGen/AMDGPU/hsa-metadata-kernel-code-props.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -mattr=-code-object-v3 -enable-misched=0 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX700 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 --amdhsa-code-object-version=2 -enable-misched=0 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX700 --check-prefix=NOTES %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -mattr=-code-object-v3 -enable-misched=0 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX803 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 --amdhsa-code-object-version=2 -enable-misched=0 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX803 --check-prefix=NOTES %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-code-object-v3 -enable-misched=0 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX900 --check-prefix=NOTES %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=2 -enable-misched=0 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK --check-prefix=GFX900 --check-prefix=NOTES %s
@var = addrspace(1) global float 0.0 @var = addrspace(1) global float 0.0
; CHECK: --- ; CHECK: ---
; CHECK: Version: [ 1, 0 ] ; CHECK: Version: [ 1, 0 ]
; CHECK: Kernels: ; CHECK: Kernels:
; CHECK-LABEL: - Name: test ; CHECK-LABEL: - Name: test
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llvm/test/CodeGen/AMDGPU/hsa-metadata-wavefrontsize.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=-code-object-v3,+wavefrontsize32,-wavefrontsize64 < %s | FileCheck -check-prefixes=GCN,GFX10-32 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 --amdhsa-code-object-version=2 -mattr=+wavefrontsize32,-wavefrontsize64 < %s | FileCheck -check-prefixes=GCN,GFX10-32 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=-code-object-v3,-wavefrontsize32,+wavefrontsize64 < %s | FileCheck -check-prefixes=GCN,GFX10-64 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 --amdhsa-code-object-version=2 -mattr=-wavefrontsize32,+wavefrontsize64 < %s | FileCheck -check-prefixes=GCN,GFX10-64 %s
; GCN: --- ; GCN: ---
; GCN: Kernels: ; GCN: Kernels:
; GCN: - Name: wavefrontsize ; GCN: - Name: wavefrontsize
; GCN: CodeProps: ; GCN: CodeProps:
; GFX10-32: WavefrontSize: 32 ; GFX10-32: WavefrontSize: 32
; GFX10-64: WavefrontSize: 64 ; GFX10-64: WavefrontSize: 64
; GCN: ... ; GCN: ...
define amdgpu_kernel void @wavefrontsize() { define amdgpu_kernel void @wavefrontsize() {
entry: entry:
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/hsa-note-no-func.ll

; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx600 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-SI600 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx600 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-SI600 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx601 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-SI601 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx601 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-SI601 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx700 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI700 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx700 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI700 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx701 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI701 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx701 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI701 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx702 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI702 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx702 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI702 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx703 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI703 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx703 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI703 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx704 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI704 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx704 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI704 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=bonaire -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI704 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=bonaire --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI704 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=mullins -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI703 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=mullins --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI703 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=hawaii -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI701 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=hawaii --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI701 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kabini -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI703 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kabini --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI703 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI700 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI700 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo -mattr=-flat-for-global,-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI801 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo --amdhsa-code-object-version=2 -mattr=-flat-for-global | FileCheck --check-prefix=HSA --check-prefix=HSA-VI801 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=tonga -mattr=-flat-for-global,-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI802 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=tonga --amdhsa-code-object-version=2 -mattr=-flat-for-global | FileCheck --check-prefix=HSA --check-prefix=HSA-VI802 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=-flat-for-global,-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI803 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=fiji --amdhsa-code-object-version=2 -mattr=-flat-for-global | FileCheck --check-prefix=HSA --check-prefix=HSA-VI803 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=polaris10 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI803 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=polaris10 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI803 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=polaris11 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI803 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=polaris11 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI803 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx801 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI801 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx801 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI801 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx802 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI802 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx802 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI802 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx803 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI803 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx803 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI803 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx810 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI810 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx810 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI810 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx900 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX900 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx900 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX900 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx902 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX902 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx902 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX902 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx904 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX904 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx904 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX904 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx906 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX906 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx906 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX906 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx908 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX908 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx908 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX908 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx909 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX909 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx909 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX909 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX1010 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1010 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX1010 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1011 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX1011 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1011 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX1011 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1012 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX1012 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1012 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX1012 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1030 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX1030 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1030 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX1030 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1031 -mattr=-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX1031 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1031 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX1031 %s
; HSA: .hsa_code_object_version 2,1 ; HSA: .hsa_code_object_version 2,1
; HSA-SI600: .hsa_code_object_isa 6,0,0,"AMD","AMDGPU" ; HSA-SI600: .hsa_code_object_isa 6,0,0,"AMD","AMDGPU"
; HSA-SI601: .hsa_code_object_isa 6,0,1,"AMD","AMDGPU" ; HSA-SI601: .hsa_code_object_isa 6,0,1,"AMD","AMDGPU"
; HSA-CI700: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU" ; HSA-CI700: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU"
; HSA-CI701: .hsa_code_object_isa 7,0,1,"AMD","AMDGPU" ; HSA-CI701: .hsa_code_object_isa 7,0,1,"AMD","AMDGPU"
; HSA-CI702: .hsa_code_object_isa 7,0,2,"AMD","AMDGPU" ; HSA-CI702: .hsa_code_object_isa 7,0,2,"AMD","AMDGPU"
; HSA-CI703: .hsa_code_object_isa 7,0,3,"AMD","AMDGPU" ; HSA-CI703: .hsa_code_object_isa 7,0,3,"AMD","AMDGPU"
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llvm/test/CodeGen/AMDGPU/hsa.ll

; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-code-object-v3 | FileCheck --check-prefix=HSA %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-code-object-v3,-flat-for-global | FileCheck --check-prefix=HSA-CI %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -mattr=-flat-for-global | FileCheck --check-prefix=HSA-CI %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo -mattr=-code-object-v3 | FileCheck --check-prefix=HSA %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo -mattr=-code-object-v3,-flat-for-global | FileCheck --check-prefix=HSA-VI %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo --amdhsa-code-object-version=2 -mattr=-flat-for-global | FileCheck --check-prefix=HSA-VI %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -filetype=obj -mattr=-code-object-v3 | llvm-readobj -symbols -s -sd - | FileCheck --check-prefix=ELF %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -filetype=obj --amdhsa-code-object-version=2 | llvm-readobj -symbols -s -sd - | FileCheck --check-prefix=ELF %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-code-object-v3 | llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri -mattr=-code-object-v3 | llvm-readobj -symbols -s -sd - | FileCheck %s --check-prefix=ELF ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 | llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 | llvm-readobj -symbols -s -sd - | FileCheck %s --check-prefix=ELF
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64,-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=GFX10 --check-prefix=GFX10-W32 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1010 --amdhsa-code-object-version=2 -mattr=+wavefrontsize32,-wavefrontsize64 | FileCheck --check-prefix=HSA --check-prefix=GFX10 --check-prefix=GFX10-W32 %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64,-code-object-v3 | FileCheck --check-prefix=HSA --check-prefix=GFX10 --check-prefix=GFX10-W64 %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1010 --amdhsa-code-object-version=2 -mattr=-wavefrontsize32,+wavefrontsize64 | FileCheck --check-prefix=HSA --check-prefix=GFX10 --check-prefix=GFX10-W64 %s
; The SHT_NOTE section contains the output from the .hsa_code_object_* ; The SHT_NOTE section contains the output from the .hsa_code_object_*
; directives. ; directives.
; ELF: Section { ; ELF: Section {
; ELF: Name: .text ; ELF: Name: .text
; ELF: Type: SHT_PROGBITS (0x1) ; ELF: Type: SHT_PROGBITS (0x1)
; ELF: Flags [ (0x6) ; ELF: Flags [ (0x6)
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llvm/test/CodeGen/AMDGPU/indirect-call.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -amdgpu-fixed-function-abi -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -amdgpu-fixed-function-abi -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=2 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
@gv.fptr0 = external hidden unnamed_addr addrspace(4) constant void()*, align 4 @gv.fptr0 = external hidden unnamed_addr addrspace(4) constant void()*, align 4
@gv.fptr1 = external hidden unnamed_addr addrspace(4) constant void(i32)*, align 4 @gv.fptr1 = external hidden unnamed_addr addrspace(4) constant void(i32)*, align 4
define amdgpu_kernel void @test_indirect_call_sgpr_ptr() { define amdgpu_kernel void @test_indirect_call_sgpr_ptr() {
; GCN-LABEL: test_indirect_call_sgpr_ptr: ; GCN-LABEL: test_indirect_call_sgpr_ptr:
; GCN: .amd_kernel_code_t ; GCN: .amd_kernel_code_t
; GCN-NEXT: amd_code_version_major = 1 ; GCN-NEXT: amd_code_version_major = 1
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llvm/test/CodeGen/AMDGPU/kernel-args.ll

; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope --check-prefixes=SI,GCN,MESA-GCN,FUNC %s ; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope --check-prefixes=SI,GCN,MESA-GCN,FUNC %s
; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=VI,GCN,MESA-VI,MESA-GCN,FUNC %s ; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=VI,GCN,MESA-VI,MESA-GCN,FUNC %s
; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx900 -mattr=-code-object-v3 -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=VI,GCN,HSA-GFX9,FUNC %s ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx900 --amdhsa-code-object-version=2 -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=VI,GCN,HSA-GFX9,FUNC %s
; RUN: llc < %s -march=r600 -mcpu=redwood -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=EG,EGCM,FUNC %s ; RUN: llc < %s -march=r600 -mcpu=redwood -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=EG,EGCM,FUNC %s
; RUN: llc < %s -march=r600 -mcpu=cayman -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope --check-prefixes=CM,EGCM,FUNC %s ; RUN: llc < %s -march=r600 -mcpu=cayman -verify-machineinstrs | FileCheck -allow-deprecated-dag-overlap -enable-var-scope --check-prefixes=CM,EGCM,FUNC %s
; FUNC-LABEL: {{^}}i8_arg: ; FUNC-LABEL: {{^}}i8_arg:
; HSA-GFX9: kernarg_segment_byte_size = 12 ; HSA-GFX9: kernarg_segment_byte_size = 12
; HSA-GFX9: kernarg_segment_alignment = 4 ; HSA-GFX9: kernarg_segment_alignment = 4
; SI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb ; SI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xb
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llvm/test/CodeGen/AMDGPU/kernel-argument-dag-lowering.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 -mattr=-code-object-v3 -amdgpu-ir-lower-kernel-arguments=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=VI,GCN,HSA-VI,FUNC %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 --amdhsa-code-object-version=2 -amdgpu-ir-lower-kernel-arguments=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=VI,GCN,HSA-VI,FUNC %s
; Repeat of some problematic tests in kernel-args.ll, with the IR ; Repeat of some problematic tests in kernel-args.ll, with the IR
; argument lowering pass disabled. Struct padding needs to be ; argument lowering pass disabled. Struct padding needs to be
; accounted for, as well as legalization of types changing offsets. ; accounted for, as well as legalization of types changing offsets.
; FUNC-LABEL: {{^}}i1_arg: ; FUNC-LABEL: {{^}}i1_arg:
; HSA-VI: kernarg_segment_byte_size = 12 ; HSA-VI: kernarg_segment_byte_size = 12
; HSA-VI: kernarg_segment_alignment = 4 ; HSA-VI: kernarg_segment_alignment = 4
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llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll

; RUN: llc -march=amdgcn -mcpu=bonaire -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=ALL %s ; RUN: llc -march=amdgcn -mcpu=bonaire -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=ALL %s
; RUN: llc -march=amdgcn -mcpu=carrizo --show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=ALL %s ; RUN: llc -march=amdgcn -mcpu=carrizo --show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=ALL %s
; RUN: llc -march=amdgcn -mcpu=gfx900 --show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=ALL %s ; RUN: llc -march=amdgcn -mcpu=gfx900 --show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=ALL %s
; RUN: llc -march=amdgcn -mcpu=bonaire -mtriple=amdgcn-unknown-amdhsa -mattr=-code-object-v3 < %s -mattr=-flat-for-global | FileCheck -check-prefix=GCNHSA -check-prefix=CIHSA -check-prefix=ALL %s ; RUN: llc -march=amdgcn -mcpu=bonaire -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=2 < %s -mattr=-flat-for-global | FileCheck -check-prefix=GCNHSA -check-prefix=CIHSA -check-prefix=ALL %s
; RUN: llc -march=amdgcn -mcpu=carrizo -mtriple=amdgcn-unknown-amdhsa -mattr=-code-object-v3,-flat-for-global < %s | FileCheck -check-prefix=GCNHSA -check-prefix=VIHSA -check-prefix=ALL %s ; RUN: llc -march=amdgcn -mcpu=carrizo -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=2 -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCNHSA -check-prefix=VIHSA -check-prefix=ALL %s
; RUN: llc -march=amdgcn -mcpu=gfx1010 -mtriple=amdgcn-unknown-amdhsa -mattr=-code-object-v3,-flat-for-global < %s | FileCheck -check-prefix=GCNHSA -check-prefix=GFX10HSA -check-prefix=ALL %s ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=2 -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCNHSA -check-prefix=GFX10HSA -check-prefix=ALL %s
; FIXME: align on alloca seems to be ignored for private_segment_alignment ; FIXME: align on alloca seems to be ignored for private_segment_alignment
; ALL-LABEL: {{^}}large_alloca_compute_shader: ; ALL-LABEL: {{^}}large_alloca_compute_shader:
; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD0 ; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD0
; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1
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llvm/test/CodeGen/AMDGPU/lds-alignment.ll

; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefix=HSA -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=2 < %s | FileCheck -check-prefix=HSA -check-prefix=FUNC %s
@lds.align16.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 16 @lds.align16.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 16
@lds.align16.1 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 16 @lds.align16.1 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 16
@lds.align8.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 8 @lds.align8.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 8
@lds.align32.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 32 @lds.align32.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 32
@lds.missing.align.0 = internal unnamed_addr addrspace(3) global [39 x i32] undef @lds.missing.align.0 = internal unnamed_addr addrspace(3) global [39 x i32] undef
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llvm/test/CodeGen/AMDGPU/lds-size.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa < %s | FileCheck -check-prefix=ALL -check-prefix=HSA %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=2 < %s | FileCheck -check-prefix=ALL -check-prefix=HSA %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=ALL -check-prefix=EG %s ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=ALL -check-prefix=EG %s
; This test makes sure we do not double count global values when they are ; This test makes sure we do not double count global values when they are
; used in different basic blocks. ; used in different basic blocks.
; GCN: .long 47180 ; GCN: .long 47180
; GCN-NEXT: .long 32900 ; GCN-NEXT: .long 32900
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llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.id.ll

; RUN: llc -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare i64 @llvm.amdgcn.dispatch.id() #1 declare i64 @llvm.amdgcn.dispatch.id() #1
; GCN-LABEL: {{^}}dispatch_id: ; GCN-LABEL: {{^}}dispatch_id:
; GCN: .amd_kernel_code_t ; GCN: .amd_kernel_code_t
; GCN: enable_sgpr_dispatch_id = 1 ; GCN: enable_sgpr_dispatch_id = 1
; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], s6 ; GCN-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], s6
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llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.ptr.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-code-object-v3 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: not llc -mtriple=amdgcn-unknown-unknown -mcpu=kaveri -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR %s ; RUN: not llc -mtriple=amdgcn-unknown-unknown -mcpu=kaveri -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR %s
; ERROR: in function test{{.*}}: unsupported hsa intrinsic without hsa target ; ERROR: in function test{{.*}}: unsupported hsa intrinsic without hsa target
; GCN-LABEL: {{^}}test: ; GCN-LABEL: {{^}}test:
; GCN: enable_sgpr_dispatch_ptr = 1 ; GCN: enable_sgpr_dispatch_ptr = 1
; GCN: s_load_dword s{{[0-9]+}}, s[4:5], 0x0 ; GCN: s_load_dword s{{[0-9]+}}, s[4:5], 0x0
define amdgpu_kernel void @test(i32 addrspace(1)* %out) { define amdgpu_kernel void @test(i32 addrspace(1)* %out) {
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llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -mattr=-code-object-v3 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,HSA %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=2 -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,HSA %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -mattr=-code-object-v3 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MESA %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MESA %s
; GCN-LABEL: {{^}}kernel_implicitarg_ptr_empty: ; GCN-LABEL: {{^}}kernel_implicitarg_ptr_empty:
; GCN: enable_sgpr_kernarg_segment_ptr = 1 ; GCN: enable_sgpr_kernarg_segment_ptr = 1
; HSA: kernarg_segment_byte_size = 0 ; HSA: kernarg_segment_byte_size = 0
; MESA: kernarg_segment_byte_size = 16 ; MESA: kernarg_segment_byte_size = 16
; HSA: s_load_dword s0, s[4:5], 0x0 ; HSA: s_load_dword s0, s[4:5], 0x0
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llvm/test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mattr=-code-object-v3 -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL %s ; RUN: llc -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,OS-MESA3D,MESA,ALL %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,OS-MESA3D,MESA,ALL %s
; RUN: llc -mtriple=amdgcn-mesa-unknown -verify-machineinstrs < %s | FileCheck -check-prefixes=OS-UNKNOWN,MESA,ALL %s ; RUN: llc -mtriple=amdgcn-mesa-unknown -verify-machineinstrs < %s | FileCheck -check-prefixes=OS-UNKNOWN,MESA,ALL %s
; ALL-LABEL: {{^}}test: ; ALL-LABEL: {{^}}test:
; CO-V2: enable_sgpr_kernarg_segment_ptr = 1 ; CO-V2: enable_sgpr_kernarg_segment_ptr = 1
; HSA: kernarg_segment_byte_size = 8 ; HSA: kernarg_segment_byte_size = 8
; HSA: kernarg_segment_alignment = 4 ; HSA: kernarg_segment_alignment = 4
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llvm/test/CodeGen/AMDGPU/llvm.amdgcn.queue.ptr.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-code-object-v3 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: not llc -mtriple=amdgcn-unknown-unknown -mcpu=kaveri -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR %s ; RUN: not llc -mtriple=amdgcn-unknown-unknown -mcpu=kaveri -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR %s
; ERROR: in function test{{.*}}: unsupported hsa intrinsic without hsa target ; ERROR: in function test{{.*}}: unsupported hsa intrinsic without hsa target
; GCN-LABEL: {{^}}test: ; GCN-LABEL: {{^}}test:
; GCN: enable_sgpr_queue_ptr = 1 ; GCN: enable_sgpr_queue_ptr = 1
; GCN: s_load_dword s{{[0-9]+}}, s[4:5], 0x0 ; GCN: s_load_dword s{{[0-9]+}}, s[4:5], 0x0
define amdgpu_kernel void @test(i32 addrspace(1)* %out) { define amdgpu_kernel void @test(i32 addrspace(1)* %out) {
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llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workgroup.id.ll

; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=-code-object-v3 -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=CI-HSA %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=2 -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=CI-HSA %s
; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=-code-object-v3 -mcpu=carrizo -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=VI-HSA %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=2 -mcpu=carrizo -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=VI-HSA %s
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=UNKNOWN-OS -check-prefix=SI-MESA %s ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=UNKNOWN-OS -check-prefix=SI-MESA %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=UNKNOWN-OS -check-prefix=VI-MESA %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=UNKNOWN-OS -check-prefix=VI-MESA %s
; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mattr=-code-object-v3 -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,SI-MESA %s ; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,SI-MESA %s
; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mattr=-code-object-v3 -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,VI-MESA %s ; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,VI-MESA %s
declare i32 @llvm.amdgcn.workgroup.id.x() #0 declare i32 @llvm.amdgcn.workgroup.id.x() #0
declare i32 @llvm.amdgcn.workgroup.id.y() #0 declare i32 @llvm.amdgcn.workgroup.id.y() #0
declare i32 @llvm.amdgcn.workgroup.id.z() #0 declare i32 @llvm.amdgcn.workgroup.id.z() #0
; ALL-LABEL: {{^}}test_workgroup_id_x: ; ALL-LABEL: {{^}}test_workgroup_id_x:
; CO-V2: .amd_kernel_code_t ; CO-V2: .amd_kernel_code_t
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llvm/test/CodeGen/AMDGPU/llvm.amdgcn.workitem.id.ll

; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=-code-object-v3 -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=CI-HSA %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=2 -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=CI-HSA %s
; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=-code-object-v3 -mcpu=carrizo -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=VI-HSA %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=2 -mcpu=carrizo -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=VI-HSA %s
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MESA -check-prefix=SI-MESA %s ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MESA -check-prefix=SI-MESA %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MESA -check-prefix=VI-MESA %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MESA -check-prefix=VI-MESA %s
; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mattr=-code-object-v3 -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,SI-MESA %s ; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,SI-MESA %s
; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mattr=-code-object-v3 -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,VI-MESA %s ; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,VI-MESA %s
declare i32 @llvm.amdgcn.workitem.id.x() #0 declare i32 @llvm.amdgcn.workitem.id.x() #0
declare i32 @llvm.amdgcn.workitem.id.y() #0 declare i32 @llvm.amdgcn.workitem.id.y() #0
declare i32 @llvm.amdgcn.workitem.id.z() #0 declare i32 @llvm.amdgcn.workitem.id.z() #0
; MESA: .section .AMDGPU.config ; MESA: .section .AMDGPU.config
; MESA: .long 47180 ; MESA: .long 47180
; MESA-NEXT: .long 132{{$}} ; MESA-NEXT: .long 132{{$}}
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llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-cmpxchg.ll

; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX8 %s ; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX8 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX8 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX8 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+code-object-v3 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,GFX10WGP %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,GFX10WGP %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+code-object-v3,+cumode -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,GFX10CU %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,GFX10CU %s
; GCN-LABEL: {{^}}system_one_as_monotonic_monotonic: ; GCN-LABEL: {{^}}system_one_as_monotonic_monotonic:
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN-NOT: s_waitcnt_v{{[ms]}}cnt {{[^,]+, (0x)*0$}} ; GCN-NOT: s_waitcnt_v{{[ms]}}cnt {{[^,]+, (0x)*0$}}
; GCN: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{( offset:[0-9]+)*}}{{$}} ; GCN: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{( offset:[0-9]+)*}}{{$}}
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GFX10-NOT: s_waitcnt_v{{[ms]}}cnt {{[^,]+, (0x)*0$}} ; GFX10-NOT: s_waitcnt_v{{[ms]}}cnt {{[^,]+, (0x)*0$}}
; GFX8-NOT: buffer_wbinvl1_vol ; GFX8-NOT: buffer_wbinvl1_vol
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llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-fence.ll

; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX6,GFX68 %s ; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX6,GFX68 %s
; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX8,GFX68 %s ; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX8,GFX68 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX8,GFX68 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX8,GFX68 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+code-object-v3 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX10,GFX10WGP %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX10,GFX10WGP %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+code-object-v3,+cumode -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX10,GFX10CU %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode -verify-machineinstrs < %s | FileCheck -check-prefixes=FUNC,GCN,GFX10,GFX10CU %s
; FUNC-LABEL: {{^}}system_one_as_acquire: ; FUNC-LABEL: {{^}}system_one_as_acquire:
; GCN: %bb.0 ; GCN: %bb.0
; GCN-NOT: ATOMIC_FENCE ; GCN-NOT: ATOMIC_FENCE
; GFX6: s_waitcnt vmcnt(0){{$}} ; GFX6: s_waitcnt vmcnt(0){{$}}
; GFX6-NEXT: buffer_wbinvl1{{$}} ; GFX6-NEXT: buffer_wbinvl1{{$}}
; GFX8: s_waitcnt vmcnt(0){{$}} ; GFX8: s_waitcnt vmcnt(0){{$}}
; GFX8-NEXT: buffer_wbinvl1_vol{{$}} ; GFX8-NEXT: buffer_wbinvl1_vol{{$}}
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llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-rmw.ll

; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX8 %s ; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX8 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX8 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX8 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+code-object-v3 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,GFX10WGP %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,GFX10WGP %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+code-object-v3,+cumode -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,GFX10CU %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,GFX10CU %s
; GCN-LABEL: {{^}}system_one_as_monotonic: ; GCN-LABEL: {{^}}system_one_as_monotonic:
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN-NOT: s_waitcnt_v{{[ms]}}cnt {{[^,]+, (0x)*0$}} ; GCN-NOT: s_waitcnt_v{{[ms]}}cnt {{[^,]+, (0x)*0$}}
; GCN: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; GCN: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN-NOT: s_waitcnt_v{{[ms]}}cnt {{[^,]+, (0x)*0$}} ; GCN-NOT: s_waitcnt_v{{[ms]}}cnt {{[^,]+, (0x)*0$}}
; GCN-NOT: buffer_{{wbinvl1_vol|gl._inv}} ; GCN-NOT: buffer_{{wbinvl1_vol|gl._inv}}
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llvm/test/CodeGen/AMDGPU/memory-legalizer-load.ll

; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX8,GFX89 %s ; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX8,GFX89 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX8,GFX89 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX8,GFX89 %s
; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9,GFX89 %s ; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9,GFX89 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9,GFX89 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9,GFX89 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+code-object-v3 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX10,GFX10WGP %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX10,GFX10WGP %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+code-object-v3,+cumode -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX10,GFX10CU %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX10,GFX10CU %s
declare i32 @llvm.amdgcn.workitem.id.x() declare i32 @llvm.amdgcn.workitem.id.x()
; GCN-LABEL: {{^}}system_one_as_unordered: ; GCN-LABEL: {{^}}system_one_as_unordered:
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GFX10-NOT: s_waitcnt_v{{[ms]}}cnt {{[^,]+, (0x)*0$}} ; GFX10-NOT: s_waitcnt_v{{[ms]}}cnt {{[^,]+, (0x)*0$}}
; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
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llvm/test/CodeGen/AMDGPU/memory-legalizer-store.ll

; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX8,GFX89 %s ; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX8,GFX89 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX8,GFX89 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX8,GFX89 %s
; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9,GFX89 %s ; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9,GFX89 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9,GFX89 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9,GFX89 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+code-object-v3 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX10,GFX10WGP %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX10,GFX10WGP %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+code-object-v3,+cumode -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX10,GFX10CU %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX10,GFX10CU %s
declare i32 @llvm.amdgcn.workitem.id.x() declare i32 @llvm.amdgcn.workitem.id.x()
; GCN-LABEL: {{^}}system_one_as_unordered: ; GCN-LABEL: {{^}}system_one_as_unordered:
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GFX10-NOT: s_waitcnt_v{{[ms]}}cnt {{[^,]+, (0x)*0$}} ; GFX10-NOT: s_waitcnt_v{{[ms]}}cnt {{[^,]+, (0x)*0$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
; GFX10: .amdhsa_kernel system_one_as_unordered ; GFX10: .amdhsa_kernel system_one_as_unordered
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llvm/test/CodeGen/AMDGPU/no-hsa-graphics-shaders.ll

; RUN: not llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa < %s 2>&1 | FileCheck %s ; RUN: not llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=2 < %s 2>&1 | FileCheck %s
; CHECK: in function pixel_s{{.*}}: unsupported non-compute shaders with HSA ; CHECK: in function pixel_s{{.*}}: unsupported non-compute shaders with HSA
define amdgpu_ps void @pixel_shader() #0 { define amdgpu_ps void @pixel_shader() #0 {
ret void ret void
} }
; CHECK: in function vertex_s{{.*}}: unsupported non-compute shaders with HSA ; CHECK: in function vertex_s{{.*}}: unsupported non-compute shaders with HSA
define amdgpu_vs void @vertex_shader() #0 { define amdgpu_vs void @vertex_shader() #0 {
ret void ret void
} }
; CHECK: in function geometry_s{{.*}}: unsupported non-compute shaders with HSA ; CHECK: in function geometry_s{{.*}}: unsupported non-compute shaders with HSA
define amdgpu_gs void @geometry_shader() #0 { define amdgpu_gs void @geometry_shader() #0 {
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/nop-data.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mattr=-code-object-v3 -mcpu=fiji -filetype=obj < %s | llvm-objdump -d - --mcpu=fiji | FileCheck %s ; RUN: llc -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -mcpu=fiji -filetype=obj < %s | llvm-objdump -d - --mcpu=fiji | FileCheck %s
; CHECK: <kernel0>: ; CHECK: <kernel0>:
; CHECK: s_endpgm ; CHECK: s_endpgm
define amdgpu_kernel void @kernel0() align 256 { define amdgpu_kernel void @kernel0() align 256 {
entry: entry:
ret void ret void
} }
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llvm/test/CodeGen/AMDGPU/private-element-size.ll

; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=-promote-alloca,+max-private-element-size-16 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=ELT16 -check-prefix=HSA -check-prefix=HSA-ELT16 -check-prefix=ALL -check-prefix=HSA_ELTGE8 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=2 -mattr=-promote-alloca,+max-private-element-size-16 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=ELT16 -check-prefix=HSA -check-prefix=HSA-ELT16 -check-prefix=ALL -check-prefix=HSA_ELTGE8 %s
; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=-promote-alloca,+max-private-element-size-8 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=ELT8 -check-prefix=HSA -check-prefix=HSA-ELT8 -check-prefix=ALL -check-prefix=HSA-ELTGE8 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=2 -mattr=-promote-alloca,+max-private-element-size-8 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=ELT8 -check-prefix=HSA -check-prefix=HSA-ELT8 -check-prefix=ALL -check-prefix=HSA-ELTGE8 %s
; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=-promote-alloca,+max-private-element-size-4 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=ELT4 -check-prefix=HSA -check-prefix=HSA-ELT4 -check-prefix=ALL %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=2 -mattr=-promote-alloca,+max-private-element-size-4 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=ELT4 -check-prefix=HSA -check-prefix=HSA-ELT4 -check-prefix=ALL %s
; ALL-LABEL: {{^}}private_elt_size_v4i32: ; ALL-LABEL: {{^}}private_elt_size_v4i32:
; HSA-ELT16: private_element_size = 3 ; HSA-ELT16: private_element_size = 3
; HSA-ELT8: private_element_size = 2 ; HSA-ELT8: private_element_size = 2
; HSA-ELT4: private_element_size = 1 ; HSA-ELT4: private_element_size = 1
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llvm/test/CodeGen/AMDGPU/promote-alloca-no-opts.ll

; RUN: llc -O0 -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -mattr=-code-object-v3,+promote-alloca < %s | FileCheck -check-prefix=NOOPTS -check-prefix=ALL %s ; RUN: llc -O0 -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -mattr=+promote-alloca < %s | FileCheck -check-prefix=NOOPTS -check-prefix=ALL %s
; RUN: llc -O1 -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -mattr=-code-object-v3,+promote-alloca < %s | FileCheck -check-prefix=OPTS -check-prefix=ALL %s ; RUN: llc -O1 -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -mattr=+promote-alloca < %s | FileCheck -check-prefix=OPTS -check-prefix=ALL %s
; ALL-LABEL: {{^}}promote_alloca_i32_array_array: ; ALL-LABEL: {{^}}promote_alloca_i32_array_array:
; NOOPTS: workgroup_group_segment_byte_size = 0{{$}} ; NOOPTS: workgroup_group_segment_byte_size = 0{{$}}
; NOOPTS-NOT: ds_write ; NOOPTS-NOT: ds_write
; OPTS: ds_write ; OPTS: ds_write
define amdgpu_kernel void @promote_alloca_i32_array_array(i32 addrspace(1)* %out, i32 %index) #0 { define amdgpu_kernel void @promote_alloca_i32_array_array(i32 addrspace(1)* %out, i32 %index) #0 {
entry: entry:
%alloca = alloca [2 x [2 x i32]], addrspace(5) %alloca = alloca [2 x [2 x i32]], addrspace(5)
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llvm/test/CodeGen/AMDGPU/promote-alloca-padding-size-estimate.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -mattr=-code-object-v3 -disable-promote-alloca-to-vector < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -disable-promote-alloca-to-vector < %s | FileCheck -check-prefix=GCN %s
; This shows that the amount LDS size estimate should try to not be ; This shows that the amount LDS size estimate should try to not be
; sensitive to the order of the LDS globals. This should try to ; sensitive to the order of the LDS globals. This should try to
; estimate the worst case padding behavior to avoid overallocating ; estimate the worst case padding behavior to avoid overallocating
; LDS. ; LDS.
; These functions use the same amount of LDS, but the total, final ; These functions use the same amount of LDS, but the total, final
; size changes depending on the visit order of first use. ; size changes depending on the visit order of first use.
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llvm/test/CodeGen/AMDGPU/trap.ll

; RUN: llc -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s ; RUN: llc -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s
; RUN: llc -mtriple=amdgcn--amdhsa -mattr=+trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s ; RUN: llc -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -mattr=+trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=HSA-TRAP %s
; RUN: llc -mtriple=amdgcn--amdhsa -mattr=-trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-HSA-TRAP %s ; RUN: llc -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -mattr=-trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-HSA-TRAP %s
; RUN: llc -mtriple=amdgcn--amdhsa -mattr=-trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s ; RUN: llc -mtriple=amdgcn--amdhsa --amdhsa-code-object-version=2 -mattr=-trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING %s
; enable trap handler feature ; enable trap handler feature
; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mattr=+trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=TRAP-BIT -check-prefix=MESA-TRAP %s ; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mattr=+trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=TRAP-BIT -check-prefix=MESA-TRAP %s
; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mattr=+trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=TRAP-BIT %s ; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mattr=+trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=TRAP-BIT %s
; disable trap handler feature ; disable trap handler feature
; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=NO-TRAP-BIT -check-prefix=NOMESA-TRAP %s ; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NO-MESA-TRAP -check-prefix=NO-TRAP-BIT -check-prefix=NOMESA-TRAP %s
; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=NO-TRAP-BIT %s ; RUN: llc -mtriple=amdgcn-unknown-mesa3d -mattr=-trap-handler -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=GCN-WARNING -check-prefix=NO-TRAP-BIT %s
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llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll

; XFAIL: * ; XFAIL: *
; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCNMESA -check-prefix=SIMESA %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCNMESA -check-prefix=SIMESA %s
; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCNMESA -check-prefix=VIMESA %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCNMESA -check-prefix=VIMESA %s
; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCNMESA -check-prefix=GFX9MESA %s ; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCNMESA -check-prefix=GFX9MESA %s
; RUN: llc -march=amdgcn -mcpu=hawaii -mtriple=amdgcn-unknown-amdhsa -mattr=-code-object-v3 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CIHSA -check-prefix=HSA %s ; RUN: llc -march=amdgcn -mcpu=hawaii -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=2 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CIHSA -check-prefix=HSA %s
; RUN: llc -march=amdgcn -mcpu=fiji -mtriple=amdgcn-unknown-amdhsa -mattr=-code-object-v3 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VIHSA -check-prefix=HSA %s ; RUN: llc -march=amdgcn -mcpu=fiji -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=2 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VIHSA -check-prefix=HSA %s
; This ends up using all 256 registers and requires register ; This ends up using all 256 registers and requires register
; scavenging which will fail to find an unsued register. ; scavenging which will fail to find an unsued register.
; Check the ScratchSize to avoid regressions from spilling ; Check the ScratchSize to avoid regressions from spilling
; intermediate register class copies. ; intermediate register class copies.
; FIXME: The same register is initialized to 0 for every spill. ; FIXME: The same register is initialized to 0 for every spill.
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llvm/test/MC/AMDGPU/hsa-diag-v3.s

// RUN: not llvm-mc -mattr=+code-object-v3 -triple amdgcn-amd-amdhsa -mcpu=gfx803 -mattr=+xnack -show-encoding %s 2>&1 >/dev/null | FileCheck %s // RUN: not llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx803 -mattr=+xnack -show-encoding %s 2>&1 >/dev/null | FileCheck %s
// RUN: not llvm-mc -mattr=+code-object-v3 -triple amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+xnack -show-encoding %s 2>&1 >/dev/null | FileCheck %s --check-prefix=GFX10 // RUN: not llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+xnack -show-encoding %s 2>&1 >/dev/null | FileCheck %s --check-prefix=GFX10
// RUN: not llvm-mc -mattr=+code-object-v3 -triple amdgcn-amd- -mcpu=gfx803 -mattr=+xnack -show-encoding %s 2>&1 >/dev/null | FileCheck %s --check-prefix=NOT-AMDHSA // RUN: not llvm-mc -triple amdgcn-amd- -mcpu=gfx803 -mattr=+xnack -show-encoding %s 2>&1 >/dev/null | FileCheck %s --check-prefix=NOT-AMDHSA
.text .text
.amdgcn_target "amdgcn--amdhsa-gfx803+xnack" .amdgcn_target "amdgcn--amdhsa-gfx803+xnack"
// CHECK: error: target must match options // CHECK: error: target must match options
.amdhsa_kernel .amdhsa_kernel
// CHECK: error: unknown directive // CHECK: error: unknown directive
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llvm/test/MC/AMDGPU/hsa-exp.s

// RUN: llvm-mc -triple amdgcn--amdhsa -mcpu=kaveri -mattr=-code-object-v3 -show-encoding %s | FileCheck %s --check-prefix=ASM // RUN: llvm-mc -triple amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -show-encoding %s | FileCheck %s --check-prefix=ASM
// RUN: llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri -mattr=-code-object-v3 -show-encoding %s | llvm-readobj --symbols -S --sd - | FileCheck %s --check-prefix=ELF // RUN: llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -show-encoding %s | llvm-readobj --symbols -S --sd - | FileCheck %s --check-prefix=ELF
// ELF: Section { // ELF: Section {
// ELF: Name: .text // ELF: Name: .text
// ELF: Type: SHT_PROGBITS (0x1) // ELF: Type: SHT_PROGBITS (0x1)
// ELF: Flags [ (0x6) // ELF: Flags [ (0x6)
// ELF: SHF_ALLOC (0x2) // ELF: SHF_ALLOC (0x2)
// ELF: SHF_EXECINSTR (0x4) // ELF: SHF_EXECINSTR (0x4)
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llvm/test/MC/AMDGPU/hsa-gfx10-v3.s

// RUN: llvm-mc -mattr=+code-object-v3 -triple amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+xnack < %s | FileCheck --check-prefix=ASM %s // RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+xnack < %s | FileCheck --check-prefix=ASM %s
// RUN: llvm-mc -mattr=+code-object-v3 -triple amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+xnack -filetype=obj < %s > %t // RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+xnack -filetype=obj < %s > %t
// RUN: llvm-readobj -elf-output-style=GNU -sections -symbols -relocations %t | FileCheck --check-prefix=READOBJ %s // RUN: llvm-readobj -elf-output-style=GNU -sections -symbols -relocations %t | FileCheck --check-prefix=READOBJ %s
// RUN: llvm-objdump -s -j .rodata %t | FileCheck --check-prefix=OBJDUMP %s // RUN: llvm-objdump -s -j .rodata %t | FileCheck --check-prefix=OBJDUMP %s
// READOBJ: Section Headers // READOBJ: Section Headers
// READOBJ: .text PROGBITS {{[0-9a-f]+}} {{[0-9a-f]+}} {{[0-9a-f]+}} {{[0-9]+}} AX {{[0-9]+}} {{[0-9]+}} 256 // READOBJ: .text PROGBITS {{[0-9a-f]+}} {{[0-9a-f]+}} {{[0-9a-f]+}} {{[0-9]+}} AX {{[0-9]+}} {{[0-9]+}} 256
// READOBJ: .rodata PROGBITS {{[0-9a-f]+}} {{[0-9a-f]+}} 0000c0 {{[0-9]+}} A {{[0-9]+}} {{[0-9]+}} 64 // READOBJ: .rodata PROGBITS {{[0-9a-f]+}} {{[0-9a-f]+}} 0000c0 {{[0-9]+}} A {{[0-9]+}} {{[0-9]+}} 64
// READOBJ: Relocation section '.rela.rodata' at offset // READOBJ: Relocation section '.rela.rodata' at offset
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llvm/test/MC/AMDGPU/hsa-gfx10.s

// RUN: llvm-mc -triple amdgcn--amdhsa -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64,-code-object-v3 -show-encoding %s | FileCheck %s --check-prefix=ASM // RUN: llvm-mc -triple amdgcn--amdhsa -mcpu=gfx1010 --amdhsa-code-object-version=2 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck %s --check-prefix=ASM
// RUN: llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64,-code-object-v3 -show-encoding %s | llvm-readobj -symbols -s -sd - | FileCheck %s --check-prefix=ELF // RUN: llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=gfx1010 --amdhsa-code-object-version=2 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | llvm-readobj -symbols -s -sd - | FileCheck %s --check-prefix=ELF
// ELF: Section { // ELF: Section {
// ELF: Name: .text // ELF: Name: .text
// ELF: Type: SHT_PROGBITS (0x1) // ELF: Type: SHT_PROGBITS (0x1)
// ELF: Flags [ (0x6) // ELF: Flags [ (0x6)
// ELF: SHF_ALLOC (0x2) // ELF: SHF_ALLOC (0x2)
// ELF: SHF_EXECINSTR (0x4) // ELF: SHF_EXECINSTR (0x4)
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llvm/test/MC/AMDGPU/hsa-metadata-kernel-args-v3.s

// RUN: llvm-mc -mattr=+code-object-v3 -triple=amdgcn-amd-amdhsa -mcpu=gfx700 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX700 %s // RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx700 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX700 %s
// RUN: llvm-mc -mattr=+code-object-v3 -triple=amdgcn-amd-amdhsa -mcpu=gfx800 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX800 %s // RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx800 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX800 %s
// RUN: llvm-mc -mattr=+code-object-v3 -triple=amdgcn-amd-amdhsa -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX900 %s // RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX900 %s
; CHECK: .amdgpu_metadata ; CHECK: .amdgpu_metadata
; CHECK: amdhsa.kernels: ; CHECK: amdhsa.kernels:
; CHECK-NEXT: - .args: ; CHECK-NEXT: - .args:
; CHECK-NEXT: - .offset: 1 ; CHECK-NEXT: - .offset: 1
; CHECK-NEXT: .size: 1 ; CHECK-NEXT: .size: 1
; CHECK-NEXT: .type_name: char ; CHECK-NEXT: .type_name: char
; CHECK-NEXT: .value_kind: by_value ; CHECK-NEXT: .value_kind: by_value
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llvm/test/MC/AMDGPU/hsa-metadata-kernel-args.s

// RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx700 -mattr=-code-object-v3 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX700 %s // RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx700 --amdhsa-code-object-version=2 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX700 %s
// RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx800 -mattr=-code-object-v3 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX800 %s // RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx800 --amdhsa-code-object-version=2 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX800 %s
// RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-code-object-v3 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX900 %s // RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=2 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX900 %s
// The legacy ValueType field should be parsed without error, but not // The legacy ValueType field should be parsed without error, but not
// re-emitted. // re-emitted.
// CHECK: .amd_amdgpu_hsa_metadata // CHECK: .amd_amdgpu_hsa_metadata
// CHECK: Version: [ 1, 0 ] // CHECK: Version: [ 1, 0 ]
// CHECK: Printf: // CHECK: Printf:
// CHECK: - '1:1:4:%d\n' // CHECK: - '1:1:4:%d\n'
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llvm/test/MC/AMDGPU/hsa-metadata-kernel-attrs-v3.s

// RUN: llvm-mc -mattr=+code-object-v3 -triple=amdgcn-amd-amdhsa -mcpu=gfx700 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX700 %s // RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx700 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX700 %s
// RUN: llvm-mc -mattr=+code-object-v3 -triple=amdgcn-amd-amdhsa -mcpu=gfx800 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX800 %s // RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx800 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX800 %s
// RUN: llvm-mc -mattr=+code-object-v3 -triple=amdgcn-amd-amdhsa -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX900 %s // RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX900 %s
// CHECK: .amdgpu_metadata // CHECK: .amdgpu_metadata
// CHECK: amdhsa.kernels: // CHECK: amdhsa.kernels:
// CHECK: - .group_segment_fixed_size: 16 // CHECK: - .group_segment_fixed_size: 16
// CHECK: .kernarg_segment_align: 64 // CHECK: .kernarg_segment_align: 64
// CHECK: .kernarg_segment_size: 8 // CHECK: .kernarg_segment_size: 8
// CHECK: .language: OpenCL C // CHECK: .language: OpenCL C
// CHECK: .language_version: // CHECK: .language_version:
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llvm/test/MC/AMDGPU/hsa-metadata-kernel-attrs.s

// RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx700 -mattr=-code-object-v3 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX700 %s // RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx700 --amdhsa-code-object-version=2 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX700 %s
// RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx800 -mattr=-code-object-v3 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX800 %s // RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx800 --amdhsa-code-object-version=2 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX800 %s
// RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-code-object-v3 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX900 %s // RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=2 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX900 %s
// CHECK: .amd_amdgpu_hsa_metadata // CHECK: .amd_amdgpu_hsa_metadata
// CHECK: Version: [ 1, 0 ] // CHECK: Version: [ 1, 0 ]
// CHECK: Printf: // CHECK: Printf:
// CHECK: - '1:1:4:%d\n' // CHECK: - '1:1:4:%d\n'
// CHECK: - '2:1:8:%g\n' // CHECK: - '2:1:8:%g\n'
// CHECK: Kernels: // CHECK: Kernels:
// CHECK: - Name: test_kernel // CHECK: - Name: test_kernel
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llvm/test/MC/AMDGPU/hsa-metadata-kernel-code-props-v3.s

// RUN: llvm-mc -mattr=+code-object-v3 -triple=amdgcn-amd-amdhsa -mcpu=gfx700 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX700 %s // RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx700 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX700 %s
// RUN: llvm-mc -mattr=+code-object-v3 -triple=amdgcn-amd-amdhsa -mcpu=gfx800 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX800 %s // RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx800 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX800 %s
// RUN: llvm-mc -mattr=+code-object-v3 -triple=amdgcn-amd-amdhsa -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX900 %s // RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx900 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX900 %s
// CHECK: .amdgpu_metadata // CHECK: .amdgpu_metadata
// CHECK: amdhsa.kernels: // CHECK: amdhsa.kernels:
// CHECK: - .group_segment_fixed_size: 24 // CHECK: - .group_segment_fixed_size: 24
// CHECK: .kernarg_segment_align: 16 // CHECK: .kernarg_segment_align: 16
// CHECK: .kernarg_segment_size: 24 // CHECK: .kernarg_segment_size: 24
// CHECK: .max_flat_workgroup_size: 256 // CHECK: .max_flat_workgroup_size: 256
// CHECK: .name: test_kernel // CHECK: .name: test_kernel
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llvm/test/MC/AMDGPU/hsa-metadata-kernel-code-props.s

// RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx700 -mattr=-code-object-v3 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX700 %s // RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx700 --amdhsa-code-object-version=2 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX700 %s
// RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx800 -mattr=-code-object-v3 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX800 %s // RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx800 --amdhsa-code-object-version=2 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX800 %s
// RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-code-object-v3 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX900 %s // RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=2 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX900 %s
// CHECK: .amd_amdgpu_hsa_metadata // CHECK: .amd_amdgpu_hsa_metadata
// CHECK: Version: [ 1, 0 ] // CHECK: Version: [ 1, 0 ]
// CHECK: Kernels: // CHECK: Kernels:
// CHECK: - Name: test_kernel // CHECK: - Name: test_kernel
// CHECK: SymbolName: 'test_kernel@kd' // CHECK: SymbolName: 'test_kernel@kd'
// CHECK: CodeProps: // CHECK: CodeProps:
// CHECK: KernargSegmentSize: 24 // CHECK: KernargSegmentSize: 24
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llvm/test/MC/AMDGPU/hsa-metadata-kernel-debug-props.s

// RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx700 -mattr=-code-object-v3 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX700 %s // RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx700 --amdhsa-code-object-version=2 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX700 %s
// RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx800 -mattr=-code-object-v3 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX800 %s // RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx800 --amdhsa-code-object-version=2 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX800 %s
// RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-code-object-v3 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX900 %s // RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=2 -show-encoding %s | FileCheck --check-prefix=CHECK --check-prefix=GFX900 %s
// CHECK: .amd_amdgpu_hsa_metadata // CHECK: .amd_amdgpu_hsa_metadata
// CHECK: Version: [ 1, 0 ] // CHECK: Version: [ 1, 0 ]
// CHECK: Kernels: // CHECK: Kernels:
// CHECK: - Name: test_kernel // CHECK: - Name: test_kernel
// CHECK: SymbolName: 'test_kernel@kd' // CHECK: SymbolName: 'test_kernel@kd'
// CHECK: DebugProps: // CHECK: DebugProps:
// CHECK: DebuggerABIVersion: [ 1, 0 ] // CHECK: DebuggerABIVersion: [ 1, 0 ]
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llvm/test/MC/AMDGPU/hsa-metadata-unknown-key.s

// RUN: not llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx700 -mattr=-code-object-v3 %s 2>&1 | FileCheck %s // RUN: not llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx700 --amdhsa-code-object-version=2 %s 2>&1 | FileCheck %s
// RUN: not llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx800 -mattr=-code-object-v3 %s 2>&1 | FileCheck %s // RUN: not llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx800 --amdhsa-code-object-version=2 %s 2>&1 | FileCheck %s
// RUN: not llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-code-object-v3 %s 2>&1 | FileCheck %s // RUN: not llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=2 %s 2>&1 | FileCheck %s
// RUN: not llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx700 -mattr=-code-object-v3 -filetype=obj %s 2>&1 | FileCheck %s // RUN: not llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx700 --amdhsa-code-object-version=2 -filetype=obj %s 2>&1 | FileCheck %s
// RUN: not llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx800 -mattr=-code-object-v3 -filetype=obj %s 2>&1 | FileCheck %s // RUN: not llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx800 --amdhsa-code-object-version=2 -filetype=obj %s 2>&1 | FileCheck %s
// RUN: not llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-code-object-v3 -filetype=obj %s 2>&1 | FileCheck %s // RUN: not llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=2 -filetype=obj %s 2>&1 | FileCheck %s
// CHECK: error: unknown key 'UnknownKey' // CHECK: error: unknown key 'UnknownKey'
.amd_amdgpu_hsa_metadata .amd_amdgpu_hsa_metadata
UnknownKey: [ 2, 0 ] UnknownKey: [ 2, 0 ]
Version: [ 1, 0 ] Version: [ 1, 0 ]
Printf: [ '1:1:4:%d\n', '2:1:8:%g\n' ] Printf: [ '1:1:4:%d\n', '2:1:8:%g\n' ]
Kernels: Kernels:
- Name: test_kernel - Name: test_kernel
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llvm/test/MC/AMDGPU/hsa-sgpr-init-bug-v3.s

// RUN: llvm-mc -mattr=+code-object-v3 -triple amdgcn-amd-amdhsa -mcpu=gfx802 -filetype=obj < %s > %t // RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx802 -filetype=obj < %s > %t
// RUN: llvm-objdump -s -j .rodata %t | FileCheck --check-prefix=OBJDUMP %s // RUN: llvm-objdump -s -j .rodata %t | FileCheck --check-prefix=OBJDUMP %s
// Check that SGPR init bug on gfx803 is corrected by the assembler, setting // Check that SGPR init bug on gfx803 is corrected by the assembler, setting
// GRANULATED_WAVEFRONT_SGPR_COUNT to 11. // GRANULATED_WAVEFRONT_SGPR_COUNT to 11.
// OBJDUMP: Contents of section .rodata // OBJDUMP: Contents of section .rodata
// OBJDUMP-NEXT: 0000 00000000 00000000 00000000 00000000 // OBJDUMP-NEXT: 0000 00000000 00000000 00000000 00000000
// OBJDUMP-NEXT: 0010 00000000 00000000 00000000 00000000 // OBJDUMP-NEXT: 0010 00000000 00000000 00000000 00000000
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llvm/test/MC/AMDGPU/hsa-text.s

// RUN: llvm-mc -triple amdgcn--amdhsa -mcpu=kaveri -mattr=-code-object-v3 -show-encoding %s | FileCheck %s --check-prefix=ASM // RUN: llvm-mc -triple amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -show-encoding %s | FileCheck %s --check-prefix=ASM
// RUN: llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri -mattr=-code-object-v3 -show-encoding %s | llvm-readobj -S --sd - | FileCheck %s --check-prefix=ELF // RUN: llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -show-encoding %s | llvm-readobj -S --sd - | FileCheck %s --check-prefix=ELF
// For compatibility reasons we treat convert .text sections to .hsatext // For compatibility reasons we treat convert .text sections to .hsatext
// ELF: Section { // ELF: Section {
// ELF: Name: .text // ELF: Name: .text
// ELF: Type: SHT_PROGBITS (0x1) // ELF: Type: SHT_PROGBITS (0x1)
// ELF: Flags [ (0x6) // ELF: Flags [ (0x6)
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llvm/test/MC/AMDGPU/hsa-v3.s

// RUN: llvm-mc -mattr=+code-object-v3 -triple amdgcn-amd-amdhsa -mcpu=gfx904 -mattr=+xnack < %s | FileCheck --check-prefix=ASM %s // RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx904 -mattr=+xnack < %s | FileCheck --check-prefix=ASM %s
// RUN: llvm-mc -mattr=+code-object-v3 -triple amdgcn-amd-amdhsa -mcpu=gfx904 -mattr=+xnack -filetype=obj < %s > %t // RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx904 -mattr=+xnack -filetype=obj < %s > %t
// RUN: llvm-readelf -sections -symbols -relocations %t | FileCheck --check-prefix=READOBJ %s // RUN: llvm-readelf -sections -symbols -relocations %t | FileCheck --check-prefix=READOBJ %s
// RUN: llvm-objdump -s -j .rodata %t | FileCheck --check-prefix=OBJDUMP %s // RUN: llvm-objdump -s -j .rodata %t | FileCheck --check-prefix=OBJDUMP %s
// READOBJ: Section Headers // READOBJ: Section Headers
// READOBJ: .text PROGBITS {{[0-9a-f]+}} {{[0-9a-f]+}} {{[0-9a-f]+}} {{[0-9]+}} AX {{[0-9]+}} {{[0-9]+}} 256 // READOBJ: .text PROGBITS {{[0-9a-f]+}} {{[0-9a-f]+}} {{[0-9a-f]+}} {{[0-9]+}} AX {{[0-9]+}} {{[0-9]+}} 256
// READOBJ: .rodata PROGBITS {{[0-9a-f]+}} {{[0-9a-f]+}} 000100 {{[0-9]+}} A {{[0-9]+}} {{[0-9]+}} 64 // READOBJ: .rodata PROGBITS {{[0-9a-f]+}} {{[0-9a-f]+}} 000100 {{[0-9]+}} A {{[0-9]+}} {{[0-9]+}} 64
// READOBJ: Relocation section '.rela.rodata' at offset // READOBJ: Relocation section '.rela.rodata' at offset
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llvm/test/MC/AMDGPU/hsa-wave-size.s

// RUN: not llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx700 -mattr=-code-object-v3 %s | FileCheck --check-prefixes=GCN,GFX7 %s // RUN: not llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx700 --amdhsa-code-object-version=2 %s | FileCheck --check-prefixes=GCN,GFX7 %s
// RUN: not llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=-code-object-v3,+wavefrontsize32,-wavefrontsize64 %s | FileCheck --check-prefixes=GCN,GFX10-W32 %s // RUN: not llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx1010 --amdhsa-code-object-version=2 -mattr=+wavefrontsize32,-wavefrontsize64 %s | FileCheck --check-prefixes=GCN,GFX10-W32 %s
// RUN: not llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=-code-object-v3,-wavefrontsize32,+wavefrontsize64 %s | FileCheck --check-prefixes=GCN,GFX10-W64 %s // RUN: not llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx1010 --amdhsa-code-object-version=2 -mattr=-wavefrontsize32,+wavefrontsize64 %s | FileCheck --check-prefixes=GCN,GFX10-W64 %s
// RUN: not llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx700 -mattr=-code-object-v3 %s 2>&1 | FileCheck --check-prefixes=GCN-ERR,GFX7-ERR %s // RUN: not llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx700 --amdhsa-code-object-version=2 %s 2>&1 | FileCheck --check-prefixes=GCN-ERR,GFX7-ERR %s
// RUN: not llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=-code-object-v3,+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GCN-ERR,GFX10-W32-ERR %s // RUN: not llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx1010 --amdhsa-code-object-version=2 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GCN-ERR,GFX10-W32-ERR %s
// RUN: not llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=-code-object-v3,-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GCN-ERR,GFX10-W64-ERR %s // RUN: not llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx1010 --amdhsa-code-object-version=2 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefixes=GCN-ERR,GFX10-W64-ERR %s
// GCN: test0: // GCN: test0:
// GFX7: enable_wavefront_size32 = 0 // GFX7: enable_wavefront_size32 = 0
// GFX7: wavefront_size = 6 // GFX7: wavefront_size = 6
// GFX10-W32: enable_wavefront_size32 = 1 // GFX10-W32: enable_wavefront_size32 = 1
// GFX10-W32: wavefront_size = 5 // GFX10-W32: wavefront_size = 5
// GFX10-W64: enable_wavefront_size32 = 0 // GFX10-W64: enable_wavefront_size32 = 0
// GFX10-W64: wavefront_size = 6 // GFX10-W64: wavefront_size = 6
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llvm/test/MC/AMDGPU/hsa.s

// RUN: llvm-mc -triple amdgcn--amdhsa -mcpu=kaveri -mattr=-code-object-v3 -show-encoding %s | FileCheck %s --check-prefix=ASM // RUN: llvm-mc -triple amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -show-encoding %s | FileCheck %s --check-prefix=ASM
// RUN: llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri -mattr=-code-object-v3 -show-encoding %s | llvm-readobj --symbols -S --sd - | FileCheck %s --check-prefix=ELF // RUN: llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -show-encoding %s | llvm-readobj --symbols -S --sd - | FileCheck %s --check-prefix=ELF
// ELF: Section { // ELF: Section {
// ELF: Name: .text // ELF: Name: .text
// ELF: Type: SHT_PROGBITS (0x1) // ELF: Type: SHT_PROGBITS (0x1)
// ELF: Flags [ (0x6) // ELF: Flags [ (0x6)
// ELF: SHF_ALLOC (0x2) // ELF: SHF_ALLOC (0x2)
// ELF: SHF_EXECINSTR (0x4) // ELF: SHF_EXECINSTR (0x4)
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llvm/test/MC/AMDGPU/hsa_code_object_isa_args.s

// RUN: llvm-mc -triple amdgcn--amdhsa -mcpu=kaveri -mattr=-code-object-v3 -show-encoding %s | FileCheck %s --check-prefix=ASM --check-prefix=ASM_700 // RUN: llvm-mc -triple amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -show-encoding %s | FileCheck %s --check-prefix=ASM --check-prefix=ASM_700
// RUN: llvm-mc -triple amdgcn--amdhsa -mcpu=gfx803 -mattr=-code-object-v3 -show-encoding %s | FileCheck %s --check-prefix=ASM --check-prefix=ASM_803 // RUN: llvm-mc -triple amdgcn--amdhsa -mcpu=gfx803 --amdhsa-code-object-version=2 -show-encoding %s | FileCheck %s --check-prefix=ASM --check-prefix=ASM_803
// RUN: llvm-mc -triple amdgcn--amdhsa -mcpu=stoney -mattr=-code-object-v3 -show-encoding %s | FileCheck %s --check-prefix=ASM --check-prefix=ASM_810 // RUN: llvm-mc -triple amdgcn--amdhsa -mcpu=stoney --amdhsa-code-object-version=2 -show-encoding %s | FileCheck %s --check-prefix=ASM --check-prefix=ASM_810
// RUN: llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri -mattr=-code-object-v3 -show-encoding %s | llvm-readobj -S --sd - | FileCheck %s --check-prefix=ELF --check-prefix=ELF_700 // RUN: llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -show-encoding %s | llvm-readobj -S --sd - | FileCheck %s --check-prefix=ELF --check-prefix=ELF_700
// RUN: llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=gfx803 -mattr=-code-object-v3 -show-encoding %s | llvm-readobj -S --sd - | FileCheck %s --check-prefix=ELF --check-prefix=ELF_803 // RUN: llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=gfx803 --amdhsa-code-object-version=2 -show-encoding %s | llvm-readobj -S --sd - | FileCheck %s --check-prefix=ELF --check-prefix=ELF_803
// RUN: llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=stoney -mattr=-code-object-v3 -show-encoding %s | llvm-readobj -S --sd - | FileCheck %s --check-prefix=ELF --check-prefix=ELF_810 // RUN: llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=stoney --amdhsa-code-object-version=2 -show-encoding %s | llvm-readobj -S --sd - | FileCheck %s --check-prefix=ELF --check-prefix=ELF_810
// ELF: SHT_NOTE // ELF: SHT_NOTE
// ELF: 0000: 04000000 08000000 01000000 414D4400 // ELF: 0000: 04000000 08000000 01000000 414D4400
// ELF: 0010: 01000000 00000000 04000000 1B000000 // ELF: 0010: 01000000 00000000 04000000 1B000000
// ELF_700: 0020: 03000000 414D4400 04000700 07000000 // ELF_700: 0020: 03000000 414D4400 04000700 07000000
// ELF_700: 0030: 00000000 00000000 414D4400 414D4447 // ELF_700: 0030: 00000000 00000000 414D4400 414D4447
// ELF_803: 0020: 03000000 414D4400 04000700 08000000 // ELF_803: 0020: 03000000 414D4400 04000700 08000000
// ELF_803: 0030: 00000000 03000000 414D4400 414D4447 // ELF_803: 0030: 00000000 03000000 414D4400 414D4447
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llvm/test/MC/AMDGPU/hsa_isa_version_attrs.s

// RUN: llvm-mc -arch=amdgcn -mcpu=gfx801 -mattr=-code-object-v3,-fast-fmaf -show-encoding %s | FileCheck --check-prefix=GFX8 %s // RUN: llvm-mc -arch=amdgcn -mcpu=gfx801 -mattr=-fast-fmaf -show-encoding %s | FileCheck --check-prefix=GFX8 %s
// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -mattr=-code-object-v3,-mad-mix-insts -show-encoding %s | FileCheck --check-prefix=GFX9 %s // RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -mattr=-mad-mix-insts -show-encoding %s | FileCheck --check-prefix=GFX9 %s
// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-code-object-v3,-wavefrontsize32 -show-encoding %s | FileCheck --check-prefix=GFX10 %s // RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
.hsa_code_object_isa .hsa_code_object_isa
// GFX8: .hsa_code_object_isa 8,0,1,"AMD","AMDGPU" // GFX8: .hsa_code_object_isa 8,0,1,"AMD","AMDGPU"
// GFX9: .hsa_code_object_isa 9,0,0,"AMD","AMDGPU" // GFX9: .hsa_code_object_isa 9,0,0,"AMD","AMDGPU"
// GFX10: .hsa_code_object_isa 10,1,0,"AMD","AMDGPU" // GFX10: .hsa_code_object_isa 10,1,0,"AMD","AMDGPU"

llvm/test/MC/AMDGPU/isa-version-hsa.s

// RUN: not llvm-mc -triple amdgcn-amd-unknown -mattr=-code-object-v3 -mcpu=gfx802 %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=OSABI-UNK-ERR %s // RUN: not llvm-mc -triple amdgcn-amd-unknown -mcpu=gfx802 %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=OSABI-UNK-ERR %s
// RUN: not llvm-mc -triple amdgcn-amd-unknown -mattr=-code-object-v3 -mcpu=iceland %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=OSABI-UNK-ERR %s // RUN: not llvm-mc -triple amdgcn-amd-unknown -mcpu=iceland %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=OSABI-UNK-ERR %s
// RUN: llvm-mc -triple amdgcn-amd-amdhsa -mattr=-code-object-v3 -mcpu=gfx802 %s | FileCheck --check-prefix=GCN --check-prefix=OSABI-HSA %s // RUN: llvm-mc -triple amdgcn-amd-amdhsa --amdhsa-code-object-version=2 -mcpu=gfx802 %s | FileCheck --check-prefix=GCN --check-prefix=OSABI-HSA %s
// RUN: llvm-mc -triple amdgcn-amd-amdhsa -mattr=-code-object-v3 -mcpu=iceland %s | FileCheck --check-prefix=GCN --check-prefix=OSABI-HSA %s // RUN: llvm-mc -triple amdgcn-amd-amdhsa --amdhsa-code-object-version=2 -mcpu=iceland %s | FileCheck --check-prefix=GCN --check-prefix=OSABI-HSA %s
// RUN: not llvm-mc -triple amdgcn-amd-amdhsa -mattr=-code-object-v3 -mcpu=gfx803 %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=OSABI-HSA-ERR %s // RUN: not llvm-mc -triple amdgcn-amd-amdhsa --amdhsa-code-object-version=2 -mcpu=gfx803 %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=OSABI-HSA-ERR %s
// RUN: not llvm-mc -triple amdgcn-amd-amdpal -mattr=-code-object-v3 -mcpu=gfx802 %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=OSABI-PAL-ERR %s // RUN: not llvm-mc -triple amdgcn-amd-amdpal -mcpu=gfx802 %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=OSABI-PAL-ERR %s
// RUN: not llvm-mc -triple amdgcn-amd-amdpal -mattr=-code-object-v3 -mcpu=iceland %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=OSABI-PAL-ERR %s // RUN: not llvm-mc -triple amdgcn-amd-amdpal -mcpu=iceland %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=OSABI-PAL-ERR %s
// OSABI-HSA: .amd_amdgpu_isa "amdgcn-amd-amdhsa--gfx802" // OSABI-HSA: .amd_amdgpu_isa "amdgcn-amd-amdhsa--gfx802"
// OSABI-UNK-ERR: error: .amd_amdgpu_isa directive does not match triple and/or mcpu arguments specified through the command line // OSABI-UNK-ERR: error: .amd_amdgpu_isa directive does not match triple and/or mcpu arguments specified through the command line
// OSABI-HSA-ERR: error: .amd_amdgpu_isa directive does not match triple and/or mcpu arguments specified through the command line // OSABI-HSA-ERR: error: .amd_amdgpu_isa directive does not match triple and/or mcpu arguments specified through the command line
// OSABI-PAL-ERR: error: .amd_amdgpu_isa directive does not match triple and/or mcpu arguments specified through the command line // OSABI-PAL-ERR: error: .amd_amdgpu_isa directive does not match triple and/or mcpu arguments specified through the command line
.amd_amdgpu_isa "amdgcn-amd-amdhsa--gfx802" .amd_amdgpu_isa "amdgcn-amd-amdhsa--gfx802"

llvm/test/MC/AMDGPU/isa-version-pal.s

// RUN: not llvm-mc -triple amdgcn-amd-unknown -mattr=-code-object-v3 -mcpu=gfx802 %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=OSABI-UNK-ERR %s // RUN: not llvm-mc -triple amdgcn-amd-unknown -mcpu=gfx802 %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=OSABI-UNK-ERR %s
// RUN: not llvm-mc -triple amdgcn-amd-unknown -mattr=-code-object-v3 -mcpu=iceland %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=OSABI-UNK-ERR %s // RUN: not llvm-mc -triple amdgcn-amd-unknown -mcpu=iceland %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=OSABI-UNK-ERR %s
// RUN: not llvm-mc -triple amdgcn-amd-amdhsa -mattr=-code-object-v3 -mcpu=gfx802 %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=OSABI-HSA-ERR %s // RUN: not llvm-mc -triple amdgcn-amd-amdhsa --amdhsa-code-object-version=2 -mcpu=gfx802 %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=OSABI-HSA-ERR %s
// RUN: not llvm-mc -triple amdgcn-amd-amdhsa -mattr=-code-object-v3 -mcpu=iceland %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=OSABI-HSA-ERR %s // RUN: not llvm-mc -triple amdgcn-amd-amdhsa --amdhsa-code-object-version=2 -mcpu=iceland %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=OSABI-HSA-ERR %s
// RUN: llvm-mc -triple amdgcn-amd-amdpal -mattr=-code-object-v3 -mcpu=gfx802 %s | FileCheck --check-prefix=GCN --check-prefix=OSABI-PAL %s // RUN: llvm-mc -triple amdgcn-amd-amdpal -mcpu=gfx802 %s | FileCheck --check-prefix=GCN --check-prefix=OSABI-PAL %s
// RUN: llvm-mc -triple amdgcn-amd-amdpal -mattr=-code-object-v3 -mcpu=iceland %s | FileCheck --check-prefix=GCN --check-prefix=OSABI-PAL %s // RUN: llvm-mc -triple amdgcn-amd-amdpal -mcpu=iceland %s | FileCheck --check-prefix=GCN --check-prefix=OSABI-PAL %s
// RUN: not llvm-mc -triple amdgcn-amd-unknown -mattr=-code-object-v3 -mcpu=gfx802 %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=OSABI-UNK-ERR %s // RUN: not llvm-mc -triple amdgcn-amd-unknown -mcpu=gfx802 %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=OSABI-UNK-ERR %s
// OSABI-PAL: .amd_amdgpu_isa "amdgcn-amd-amdpal--gfx802" // OSABI-PAL: .amd_amdgpu_isa "amdgcn-amd-amdpal--gfx802"
// OSABI-UNK-ERR: error: .amd_amdgpu_isa directive does not match triple and/or mcpu arguments specified through the command line // OSABI-UNK-ERR: error: .amd_amdgpu_isa directive does not match triple and/or mcpu arguments specified through the command line
// OSABI-HSA-ERR: error: .amd_amdgpu_isa directive does not match triple and/or mcpu arguments specified through the command line // OSABI-HSA-ERR: error: .amd_amdgpu_isa directive does not match triple and/or mcpu arguments specified through the command line
// OSABI-PAL-ERR: error: .amd_amdgpu_isa directive does not match triple and/or mcpu arguments specified through the command line // OSABI-PAL-ERR: error: .amd_amdgpu_isa directive does not match triple and/or mcpu arguments specified through the command line
.amd_amdgpu_isa "amdgcn-amd-amdpal--gfx802" .amd_amdgpu_isa "amdgcn-amd-amdpal--gfx802"

llvm/test/MC/AMDGPU/isa-version-unk.s

// RUN: llvm-mc -triple amdgcn-amd-unknown -mattr=-code-object-v3 -mcpu=gfx802 %s | FileCheck --check-prefix=GCN --check-prefix=OSABI-UNK %s // RUN: llvm-mc -triple amdgcn-amd-unknown -mcpu=gfx802 %s | FileCheck --check-prefix=GCN --check-prefix=OSABI-UNK %s
// RUN: llvm-mc -triple amdgcn-amd-unknown -mattr=-code-object-v3 -mcpu=iceland %s | FileCheck --check-prefix=GCN --check-prefix=OSABI-UNK %s // RUN: llvm-mc -triple amdgcn-amd-unknown -mcpu=iceland %s | FileCheck --check-prefix=GCN --check-prefix=OSABI-UNK %s
// RUN: not llvm-mc -triple amdgcn-amd-unknown -mattr=-code-object-v3 -mcpu=gfx803 %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=OSABI-UNK-ERR %s // RUN: not llvm-mc -triple amdgcn-amd-unknown -mcpu=gfx803 %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=OSABI-UNK-ERR %s
// RUN: not llvm-mc -triple amdgcn-amd-amdhsa -mattr=-code-object-v3 -mcpu=gfx802 %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=OSABI-HSA-ERR %s // RUN: not llvm-mc -triple amdgcn-amd-amdhsa --amdhsa-code-object-version=2 -mcpu=gfx802 %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=OSABI-HSA-ERR %s
// RUN: not llvm-mc -triple amdgcn-amd-amdhsa -mattr=-code-object-v3 -mcpu=iceland %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=OSABI-HSA-ERR %s // RUN: not llvm-mc -triple amdgcn-amd-amdhsa --amdhsa-code-object-version=2 -mcpu=iceland %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=OSABI-HSA-ERR %s
// RUN: not llvm-mc -triple amdgcn-amd-amdpal -mattr=-code-object-v3 -mcpu=gfx802 %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=OSABI-PAL-ERR %s // RUN: not llvm-mc -triple amdgcn-amd-amdpal -mcpu=gfx802 %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=OSABI-PAL-ERR %s
// RUN: not llvm-mc -triple amdgcn-amd-amdpal -mattr=-code-object-v3 -mcpu=iceland %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=OSABI-PAL-ERR %s // RUN: not llvm-mc -triple amdgcn-amd-amdpal -mcpu=iceland %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=OSABI-PAL-ERR %s
// OSABI-UNK: .amd_amdgpu_isa "amdgcn-amd-unknown--gfx802" // OSABI-UNK: .amd_amdgpu_isa "amdgcn-amd-unknown--gfx802"
// OSABI-UNK-ERR: error: .amd_amdgpu_isa directive does not match triple and/or mcpu arguments specified through the command line // OSABI-UNK-ERR: error: .amd_amdgpu_isa directive does not match triple and/or mcpu arguments specified through the command line
// OSABI-HSA-ERR: error: .amd_amdgpu_isa directive does not match triple and/or mcpu arguments specified through the command line // OSABI-HSA-ERR: error: .amd_amdgpu_isa directive does not match triple and/or mcpu arguments specified through the command line
// OSABI-PAL-ERR: error: .amd_amdgpu_isa directive does not match triple and/or mcpu arguments specified through the command line // OSABI-PAL-ERR: error: .amd_amdgpu_isa directive does not match triple and/or mcpu arguments specified through the command line
.amd_amdgpu_isa "amdgcn-amd-unknown--gfx802" .amd_amdgpu_isa "amdgcn-amd-unknown--gfx802"

llvm/test/MC/AMDGPU/sym_option.s

// RUN: llvm-mc -arch=amdgcn -mattr=-code-object-v3 -mcpu=tahiti %s | FileCheck %s --check-prefix=SI // RUN: llvm-mc -arch=amdgcn -mcpu=tahiti %s | FileCheck %s --check-prefix=SI
// RUN: llvm-mc -arch=amdgcn -mattr=-code-object-v3 -mcpu=bonaire %s | FileCheck %s --check-prefix=BONAIRE // RUN: llvm-mc -arch=amdgcn -mcpu=bonaire %s | FileCheck %s --check-prefix=BONAIRE
// RUN: llvm-mc -arch=amdgcn -mattr=-code-object-v3 -mcpu=hawaii %s | FileCheck %s --check-prefix=HAWAII // RUN: llvm-mc -arch=amdgcn -mcpu=hawaii %s | FileCheck %s --check-prefix=HAWAII
// RUN: llvm-mc -arch=amdgcn -mattr=-code-object-v3 -mcpu=kabini %s | FileCheck %s --check-prefix=KABINI // RUN: llvm-mc -arch=amdgcn -mcpu=kabini %s | FileCheck %s --check-prefix=KABINI
// RUN: llvm-mc -arch=amdgcn -mattr=-code-object-v3 -mcpu=iceland %s | FileCheck %s --check-prefix=ICELAND // RUN: llvm-mc -arch=amdgcn -mcpu=iceland %s | FileCheck %s --check-prefix=ICELAND
// RUN: llvm-mc -arch=amdgcn -mattr=-code-object-v3 -mcpu=carrizo %s | FileCheck %s --check-prefix=CARRIZO // RUN: llvm-mc -arch=amdgcn -mcpu=carrizo %s | FileCheck %s --check-prefix=CARRIZO
// RUN: llvm-mc -arch=amdgcn -mattr=-code-object-v3 -mcpu=tonga %s | FileCheck %s --check-prefix=TONGA // RUN: llvm-mc -arch=amdgcn -mcpu=tonga %s | FileCheck %s --check-prefix=TONGA
// RUN: llvm-mc -arch=amdgcn -mattr=-code-object-v3 -mcpu=fiji %s | FileCheck %s --check-prefix=FIJI // RUN: llvm-mc -arch=amdgcn -mcpu=fiji %s | FileCheck %s --check-prefix=FIJI
// RUN: llvm-mc -arch=amdgcn -mattr=-code-object-v3 -mcpu=stoney %s | FileCheck %s --check-prefix=STONEY // RUN: llvm-mc -arch=amdgcn -mcpu=stoney %s | FileCheck %s --check-prefix=STONEY
.byte .option.machine_version_major .byte .option.machine_version_major
// SI: .byte 6 // SI: .byte 6
// BONAIRE: .byte 7 // BONAIRE: .byte 7
// HAWAII: .byte 7 // HAWAII: .byte 7
// KABINI: .byte 7 // KABINI: .byte 7
// ICELAND: .byte 8 // ICELAND: .byte 8
// CARRIZO: .byte 8 // CARRIZO: .byte 8
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llvm/test/Object/AMDGPU/objdump.s

// RUN: llvm-mc -arch=amdgcn -mcpu=tonga %s -mattr=-code-object-v3 -filetype=obj | llvm-objdump -d --arch-name=amdgcn --mcpu=tonga - | FileCheck %s // RUN: llvm-mc -arch=amdgcn -mcpu=tonga %s -filetype=obj | llvm-objdump -d --arch-name=amdgcn --mcpu=tonga - | FileCheck %s
.text .text
.amdgpu_hsa_kernel hello_world .amdgpu_hsa_kernel hello_world
hello_world: hello_world:
.amd_kernel_code_t .amd_kernel_code_t
.end_amd_kernel_code_t .end_amd_kernel_code_t
▲ Show 20 Lines • Show All 74 Lines • Show Last 20 Lines

llvm/test/Transforms/Inline/AMDGPU/inline-target-cpu.ll

Show First 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
; CHECK-LABEL: @call_func_without_loadstoreopt( ; CHECK-LABEL: @call_func_without_loadstoreopt(
; CHECK-NEXT: ret i32 0 ; CHECK-NEXT: ret i32 0
define i32 @call_func_without_loadstoreopt() #6 { define i32 @call_func_without_loadstoreopt() #6 {
%call = call i32 @func_no_loadstoreopt() %call = call i32 @func_no_loadstoreopt()
ret i32 %call ret i32 %call
} }
define i32 @enable_codeobjectv3() #7 {
ret i32 999
}
; CHECK-LABEL: @disable_codeobjectv3_call_codeobjectv3(
; CHECK-NEXT: ret i32 999
define i32 @disable_codeobjectv3_call_codeobjectv3() #8 {
%call = call i32 @enable_codeobjectv3()
ret i32 %call
}
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind "target-cpu"="fiji" } attributes #1 = { nounwind "target-cpu"="fiji" }
attributes #2 = { nounwind "target-cpu"="gfx900" } attributes #2 = { nounwind "target-cpu"="gfx900" }
attributes #3 = { nounwind "target-features"="-half-rate-64-ops" } attributes #3 = { nounwind "target-features"="-half-rate-64-ops" }
attributes #4 = { nounwind "target-features"="+half-rate-64-ops" } attributes #4 = { nounwind "target-features"="+half-rate-64-ops" }
attributes #5 = { nounwind "target-features"="-load-store-opt" } attributes #5 = { nounwind "target-features"="-load-store-opt" }
attributes #6 = { nounwind "target-features"="+load-store-opt" } attributes #6 = { nounwind "target-features"="+load-store-opt" }
attributes #7 = { nounwind "target-features"="+code-object-v3" }
attributes #8 = { nounwind "target-features"="-code-object-v3" }

llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-failure.s

;; Failure test. We create a malformed kernel descriptor (KD) by manually ;; Failure test. We create a malformed kernel descriptor (KD) by manually
;; setting the bytes, because one can't create a malformed KD using the ;; setting the bytes, because one can't create a malformed KD using the
;; assembler directives. ;; assembler directives.
; RUN: llvm-mc %s -mattr=+code-object-v3 --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t.o ; RUN: llvm-mc %s --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t.o
; RUN: printf ".type my_kernel.kd, @object \nmy_kernel.kd:\n.size my_kernel.kd, 64\n" > %t1.sym_info ; RUN: printf ".type my_kernel.kd, @object \nmy_kernel.kd:\n.size my_kernel.kd, 64\n" > %t1.sym_info
; RUN: llvm-objdump --disassemble-symbols=my_kernel.kd %t.o \ ; RUN: llvm-objdump --disassemble-symbols=my_kernel.kd %t.o \
; RUN: | tail -n +9 > %t1.sym_content ; RUN: | tail -n +9 > %t1.sym_content
; RUN: cat %t1.sym_info %t1.sym_content > %t1.s ; RUN: cat %t1.sym_info %t1.sym_content > %t1.s
; RUN: llvm-mc %t1.s -mattr=+code-object-v3 --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t-re-assemble.o ; RUN: llvm-mc %t1.s --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t-re-assemble.o
; RUN: diff %t.o %t-re-assemble.o ; RUN: diff %t.o %t-re-assemble.o
;; Test failure by setting one of the reserved bytes to non-zero value. ;; Test failure by setting one of the reserved bytes to non-zero value.
.type my_kernel.kd, @object .type my_kernel.kd, @object
.size my_kernel.kd, 64 .size my_kernel.kd, 64
my_kernel.kd: my_kernel.kd:
.long 0x00000000 ;; group_segment_fixed_size .long 0x00000000 ;; group_segment_fixed_size
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llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-sgpr.s

;; Test disassembly for GRANULATED_WAVEFRONT_SGPR_COUNT in the kernel descriptor. ;; Test disassembly for GRANULATED_WAVEFRONT_SGPR_COUNT in the kernel descriptor.
; RUN: split-file %s %t.dir ; RUN: split-file %s %t.dir
; RUN: llvm-mc %t.dir/1.s -mattr=+code-object-v3 --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t1 ; RUN: llvm-mc %t.dir/1.s --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t1
; RUN: llvm-objdump --disassemble-symbols=my_kernel_1.kd %t1 | tail -n +8 \ ; RUN: llvm-objdump --disassemble-symbols=my_kernel_1.kd %t1 | tail -n +8 \
; RUN: | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t1-re-assemble ; RUN: | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t1-re-assemble
; RUN: diff %t1 %t1-re-assemble ; RUN: diff %t1 %t1-re-assemble
; RUN: llvm-mc %t.dir/2.s -mattr=+code-object-v3 --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t2 ; RUN: llvm-mc %t.dir/2.s --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t2
; RUN: llvm-objdump --disassemble-symbols=my_kernel_2.kd %t2 | tail -n +8 \ ; RUN: llvm-objdump --disassemble-symbols=my_kernel_2.kd %t2 | tail -n +8 \
; RUN: | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t2-re-assemble ; RUN: | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t2-re-assemble
; RUN: diff %t2 %t2-re-assemble ; RUN: diff %t2 %t2-re-assemble
; RUN: llvm-mc %t.dir/3.s -mattr=+code-object-v3 --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t3 ; RUN: llvm-mc %t.dir/3.s --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t3
; RUN: llvm-objdump --disassemble-symbols=my_kernel_3.kd %t3 | tail -n +8 \ ; RUN: llvm-objdump --disassemble-symbols=my_kernel_3.kd %t3 | tail -n +8 \
; RUN: | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t3-re-assemble ; RUN: | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t3-re-assemble
; RUN: diff %t3 %t3-re-assemble ; RUN: diff %t3 %t3-re-assemble
;--- 1.s ;--- 1.s
;; Only set next_free_sgpr. ;; Only set next_free_sgpr.
.amdhsa_kernel my_kernel_1 .amdhsa_kernel my_kernel_1
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llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-vgpr.s

;; Test disassembly for GRANULATED_WORKITEM_VGPR_COUNT in the kernel descriptor. ;; Test disassembly for GRANULATED_WORKITEM_VGPR_COUNT in the kernel descriptor.
; RUN: split-file %s %t.dir ; RUN: split-file %s %t.dir
; RUN: llvm-mc %t.dir/1.s -mattr=+code-object-v3 --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t1 ; RUN: llvm-mc %t.dir/1.s --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t1
; RUN: llvm-objdump --disassemble-symbols=my_kernel_1.kd %t1 | tail -n +8 \ ; RUN: llvm-objdump --disassemble-symbols=my_kernel_1.kd %t1 | tail -n +8 \
; RUN: | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t1-re-assemble ; RUN: | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t1-re-assemble
; RUN: diff %t1 %t1-re-assemble ; RUN: diff %t1 %t1-re-assemble
; RUN: llvm-mc %t.dir/2.s -mattr=+code-object-v3 --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t2 ; RUN: llvm-mc %t.dir/2.s --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t2
; RUN: llvm-objdump --disassemble-symbols=my_kernel_2.kd %t2 | tail -n +8 \ ; RUN: llvm-objdump --disassemble-symbols=my_kernel_2.kd %t2 | tail -n +8 \
; RUN: | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t2-re-assemble ; RUN: | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t2-re-assemble
; RUN: diff %t2 %t2-re-assemble ; RUN: diff %t2 %t2-re-assemble
; RUN: llvm-mc %t.dir/3.s -mattr=+code-object-v3 --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t3 ; RUN: llvm-mc %t.dir/3.s --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t3
; RUN: llvm-objdump --disassemble-symbols=my_kernel_3.kd %t3 | tail -n +8 \ ; RUN: llvm-objdump --disassemble-symbols=my_kernel_3.kd %t3 | tail -n +8 \
; RUN: | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t3-re-assemble ; RUN: | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t3-re-assemble
; RUN: diff %t3 %t3-re-assemble ; RUN: diff %t3 %t3-re-assemble
;--- 1.s ;--- 1.s
.amdhsa_kernel my_kernel_1 .amdhsa_kernel my_kernel_1
.amdhsa_next_free_vgpr 23 .amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 0 .amdhsa_next_free_sgpr 0
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llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-gfx10.s

;; Entirely zeroed kernel descriptor (for GFX10). ;; Entirely zeroed kernel descriptor (for GFX10).
; RUN: llvm-mc %s -mattr=+code-object-v3 --triple=amdgcn-amd-amdhsa -mcpu=gfx1010 -filetype=obj -o %t ; RUN: llvm-mc %s --triple=amdgcn-amd-amdhsa -mcpu=gfx1010 -filetype=obj -o %t
; RUN: llvm-objdump -s -j .text %t | FileCheck --check-prefix=OBJDUMP %s ; RUN: llvm-objdump -s -j .text %t | FileCheck --check-prefix=OBJDUMP %s
;; TODO: ;; TODO:
;; This file and kd-zeroed-raw.s should produce the same output for the kernel ;; This file and kd-zeroed-raw.s should produce the same output for the kernel
;; descriptor - a block of 64 zeroed bytes. But looks like the assembler sets ;; descriptor - a block of 64 zeroed bytes. But looks like the assembler sets
;; the FWD_PROGRESS bit in COMPUTE_PGM_RSRC1 to 1 even when the directive ;; the FWD_PROGRESS bit in COMPUTE_PGM_RSRC1 to 1 even when the directive
;; mentions 0 (see line 36). ;; mentions 0 (see line 36).
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llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-gfx9.s

;; Entirely zeroed kernel descriptor (for GFX9). ;; Entirely zeroed kernel descriptor (for GFX9).
; RUN: llvm-mc %s -mattr=+code-object-v3 --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t1 ; RUN: llvm-mc %s --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t1
; RUN: llvm-objdump --disassemble-symbols=my_kernel.kd %t1 \ ; RUN: llvm-objdump --disassemble-symbols=my_kernel.kd %t1 \
; RUN: | tail -n +8 | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t2 ; RUN: | tail -n +8 | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t2
; RUN: diff %t1 %t2 ; RUN: diff %t1 %t2
; RUN: llvm-objdump -s -j .text %t1 | FileCheck --check-prefix=OBJDUMP %s ; RUN: llvm-objdump -s -j .text %t1 | FileCheck --check-prefix=OBJDUMP %s
; OBJDUMP: 0000 00000000 00000000 00000000 00000000 ; OBJDUMP: 0000 00000000 00000000 00000000 00000000
; OBJDUMP-NEXT: 0010 00000000 00000000 00000000 00000000 ; OBJDUMP-NEXT: 0010 00000000 00000000 00000000 00000000
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llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-raw.s

; RUN: llvm-mc %s -mattr=+code-object-v3 --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t1 ; RUN: llvm-mc %s --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t1
; RUN: llvm-objdump --disassemble-symbols=my_kernel.kd %t1 \ ; RUN: llvm-objdump --disassemble-symbols=my_kernel.kd %t1 \
; RUN: | tail -n +8 | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t2 ; RUN: | tail -n +8 | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t2
; RUN: llvm-objdump -s -j .text %t2 | FileCheck --check-prefix=OBJDUMP %s ; RUN: llvm-objdump -s -j .text %t2 | FileCheck --check-prefix=OBJDUMP %s
;; Not running lit-test over gfx10 (see kd-zeroed-gfx10.s for details). ;; Not running lit-test over gfx10 (see kd-zeroed-gfx10.s for details).
;; kd-zeroed-raw.s and kd-zeroed-*.s should produce the same output for the ;; kd-zeroed-raw.s and kd-zeroed-*.s should produce the same output for the
;; kernel descriptor - a block of 64 zeroed bytes. ;; kernel descriptor - a block of 64 zeroed bytes.
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llvm/test/tools/llvm-readobj/ELF/note-amdgpu.test

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# LLVM-NEXT: ... # LLVM-NEXT: ...
# LLVM-EMPTY: # LLVM-EMPTY:
# LLVM-NEXT: } # LLVM-NEXT: }
# LLVM-NEXT: } # LLVM-NEXT: }
# LLVM-NEXT: ] # LLVM-NEXT: ]
## Use yaml2obj instead of llvm-mc for more test portability. This was ## Use yaml2obj instead of llvm-mc for more test portability. This was
## generated by grabbing section data from an object built via: ## generated by grabbing section data from an object built via:
# $ llvm-mc -filetype=obj -triple amdgcn-amd-amdhsa -mattr=+code-object-v3 %s -o %t.o # $ llvm-mc -filetype=obj -triple amdgcn-amd-amdhsa %s -o %t.o
## On input: ## On input:
# .amdgpu_metadata # .amdgpu_metadata
# amdhsa.version: # amdhsa.version:
# - 1 # - 1
# - 0 # - 0
# amdhsa.kernels: # amdhsa.kernels:
# - .name: foo # - .name: foo
# .symbol: foo # .symbol: foo
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