[AArch64] Avoid pairing loads with same result reg

[congzhe]

Summary

When pairing ldr instructions to an ldp instruction, we cannot pair two ldr
destination registers where one is a sub or super register of the other.

[fhahn]

llvm/test/CodeGen/AArch64/aarch64-ldst-subsuperReg-no-ldp.mir

30

Is it possible to strip the IR references from the MIR test? Ideally most/all of the IR function here can be dropped.

187

Are all the loads/stores and the different BBs needed for the test? Also, are the different functions needed or do they test different scenarios?

[congzhe]

llvm/test/CodeGen/AArch64/aarch64-ldst-subsuperReg-no-ldp.mir

187

Thanks for the comment!
The different functions do not test different scenarios. This is one single program (one single test) that exposes the bug, so probably all functions/BBs are still needed but I can try to reduce the program. I'm not very hopeful though because this test file is already a very much reduced version compared to its original version.

[congzhe]

Revision:

• Fixed code style
• Reduce the length of the test file

[congzhe]

llvm/test/CodeGen/AArch64/aarch64-ldst-subsuperReg-no-ldp.mir

30

I spent effort trying to drop out the IR, but since some global variables such as @_MergedGlobals or @i are used in the mir, if I were to drop the IR llc would report undefined global variables error. Is there a way that I can drop the IR while still being able to run the mir? @fhahn

187

Now reduced the size of the test file, resulting in only one function in the mir which exposes the LDR-to-LDP-conversion bug.

[fhahn]

llvm/test/CodeGen/AArch64/aarch64-ldst-subsuperReg-no-ldp.mir

30

I think it should be possible to get rid of the IR references by re-writing the address computations to use the same base register but with different offsets to ensure it is clear there is no aliasing going on. Reduced test case:

---
name:            test
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x9, $x11

    renamable $w10 = LDRWui renamable $x9, 2 :: (load 4)
    STRWui killed renamable $w10, renamable $x9, 2 :: (store 4)
    renamable $x10 = LDRSWui renamable $x9, 3 :: (load 4)
    STRWui renamable $w11, renamable $x9, 8 :: (store 4)
    renamable $w10 = LDRWui renamable $x9, 2 :: (load 4)
    RET undef $lr, implicit undef $w0

...

[congzhe]

llvm/test/CodeGen/AArch64/aarch64-ldst-subsuperReg-no-ldp.mir

30

@fhahn Thank you very much for this comment, now further reduced this mir test case.

Also the mir test case in https://reviews.llvm.org/D86956 has been further reduced.

[fhahn]

LGTM, thanks!

llvm/test/CodeGen/AArch64/aarch64-ldst-subsuperReg-no-ldp.mir

13

Given that the test is very short now, could you check for the full instruction sequence (LDR, LDR, RET)? Just to make sure the loads are not dropped completely (as $w10 is not really used any more)/.

Also, it might eb good to add another test with the order of LDRSW/LDRW flipped.

[congzhe]

llvm/test/CodeGen/AArch64/aarch64-ldst-subsuperReg-no-ldp.mir

13

@fhahn Thanks, now checking the full instruction sequence;

Also added another test with the order of LDRSW/LDRW flipped.

[congzhe]

llvm/test/CodeGen/AArch64/aarch64-ldst-subsuperReg-no-ldp.mir

13

Also made similar updates in the other patch
https://reviews.llvm.org/D86956

[fhahn]

llvm/test/CodeGen/AArch64/aarch64-ldst-subsuperReg-no-ldp.mir

13

Thanks, that looks good!

[fhahn]

oh, it might be good to slightly adjust the commit message to be a bit more compact and also mention what actual bug is fixed, e.g. something like [AArch64] Avoid paring loads with same result reg.

[congzhe]

In D86906#2279815, @fhahn wrote:

oh, it might be good to slightly adjust the commit message to be a bit more compact and also mention what actual bug is fixed, e.g. something like [AArch64] Avoid paring loads with same result reg.

Thanks, updated the commit message accordingly.

[fhahn]

Great. Please let us know if you need someone to commit the change on your behalf.

llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

if (areCandidatesToMergeOrPair(FirstMI, MI, Flags, TII) &&
           // looking.
           if (IsUnscaled && (alignTo(MinOffset, OffsetStride) != MinOffset)) {
             LiveRegUnits::accumulateUsedDefed(MI, ModifiedRegUnits,
                                               UsedRegUnits, TRI);
             MemInsns.push_back(&MI);
             continue;
           }
         }
-        // If the destination register of the loads is the same register, bail
-        // and keep looking. A load-pair instruction with both destination
-        // registers the same is UNPREDICTABLE and will result in an exception.
-        if (MayLoad && Reg == getLdStRegOp(MI).getReg()) {
+        // If the destination register of one load is the same register or a
+        // sub/super register of the other load, bail and keep looking. A
+        // load-pair instruction with both destination registers the same is
+        // UNPREDICTABLE and will result in an exception.
+        if (MayLoad && TRI->isSuperOrSubRegisterEq(Reg, getLdStRegOp(MI).getReg())) {
           LiveRegUnits::accumulateUsedDefed(MI, ModifiedRegUnits, UsedRegUnits,
                                             TRI);
           MemInsns.push_back(&MI);
           continue;
         }
 
         // If the Rt of the second instruction was not modified or used between
         // the two instructions and none of the instructions between the second

llvm/test/CodeGen/AArch64/aarch64-ldst-subsuperReg-no-ldp.mir

+# RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs -run-pass=aarch64-ldst-opt %s -o - | FileCheck %s
+#
+# The test below test that when the AArch64 Load Store Optimization pass tries to
+# convert to load instructions into a ldp instruction, and when the destination
+# registers are sub/super register of each other, then the convertion should not occur.
+#
+# For example, for the fillowing pattern:
+#     ldr x11 [x10]
+#     ldr w11 [x10, 8],
+# We cannot convert it to ldp x11, w11, [x10].
+#
+# The pattern we check in this test file is the following pattern in function b:
+#
+#     renamable $x11 = LDRSWui renamable $x10, 3 :: (dereferenceable load 4 from `i32* getelementptr inbounds (<{ i16, [2 x i8], i32, i32, [2 x i32] }>, <{ i16, [2 x i8], i32, i32, [2 x i32] }>* @_MergedGlobals, i32 0, i32 4, i64 0)`, !tbaa !2)
+#     renamable $w11 = LDRWui renamable $x10, 2 :: (dereferenceable load 4 from `i32* getelementptr inbounds (<{ i16, [2 x i8], i32, i32, [2 x i32] }>, <{ i16, [2 x i8], i32, i32, [2 x i32] }>* @_MergedGlobals, i32 0, i32 3)`, !tbaa !2)
+#
+# These two LDR instructions cannot be converted into a LDP instruction.
+#
+# CHECK-NOT: LDP
+--- |
+  ; ModuleID = 'test.ll'
+  source_filename = "test.c"
+  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+  target triple = "aarch64-unknown-linux-gnu"
+
+  %struct.a = type { i8 }
+  %union.e = type { %struct.c }
+  %struct.c = type { i32 }
+
+  @m = common dso_local local_unnamed_addr global %struct.a zeroinitializer, align 1
+  @n = common dso_local local_unnamed_addr global i32 0, align 4
+  @i = common dso_local local_unnamed_addr global i32 0, align 4
+  @g = common dso_local local_unnamed_addr global i32 0, align 4
+  @k = common dso_local local_unnamed_addr global %union.e zeroinitializer, align 4
+  @o = common dso_local local_unnamed_addr global [1 x [8 x i32]] zeroinitializer, align 4
+  @_MergedGlobals = private global <{ i16, [2 x i8], i32, i32, [2 x i32] }> <{ i16 3, [2 x i8] zeroinitializer, i32 3, i32 1, [2 x i32] [i32 1, i32 1] }>, align 4
+
+  @l = internal alias i16, getelementptr inbounds (<{ i16, [2 x i8], i32, i32, [2 x i32] }>, <{ i16, [2 x i8], i32, i32, [2 x i32] }>* @_MergedGlobals, i32 0, i32 0)
+  @j = internal alias i32, getelementptr inbounds (<{ i16, [2 x i8], i32, i32, [2 x i32] }>, <{ i16, [2 x i8], i32, i32, [2 x i32] }>* @_MergedGlobals, i32 0, i32 2)
+  @q.5 = internal alias i32, getelementptr inbounds (<{ i16, [2 x i8], i32, i32, [2 x i32] }>, <{ i16, [2 x i8], i32, i32, [2 x i32] }>* @_MergedGlobals, i32 0, i32 3)
+  @f = internal alias [2 x i32], getelementptr inbounds (<{ i16, [2 x i8], i32, i32, [2 x i32] }>, <{ i16, [2 x i8], i32, i32, [2 x i32] }>* @_MergedGlobals, i32 0, i32 4)
+
+  ; Function Attrs: nofree norecurse nounwind
+  define dso_local i32 @b() local_unnamed_addr #0 {
+  entry:
+    store i32 0, i32* @g, align 4, !tbaa !2
+    %0 = load i32, i32* getelementptr inbounds ([1 x [8 x i32]], [1 x [8 x i32]]* @o, i64 0, i64 0, i64 0), align 4, !tbaa !2
+    %tobool.i = icmp eq i32 %0, 0
+    br i1 %tobool.i, label %s.exit, label %for.cond1.preheader.preheader.i
+
+  for.cond1.preheader.preheader.i:                  ; preds = %entry
+    store i32 7, i32* @i, align 4, !tbaa !2
+    br label %s.exit
+
+  s.exit:                                           ; preds = %for.cond1.preheader.preheader.i, %entry
+    store i32 8, i32* getelementptr inbounds (%union.e, %union.e* @k, i64 0, i32 0, i32 0), align 4, !tbaa !6
+    store i32 2, i32* @g, align 4, !tbaa !2
+    %1 = load i8, i8* getelementptr inbounds (%struct.a, %struct.a* @m, i64 0, i32 0), align 1, !tbaa !7
+    %2 = load i32, i32* getelementptr inbounds (<{ i16, [2 x i8], i32, i32, [2 x i32] }>, <{ i16, [2 x i8], i32, i32, [2 x i32] }>* @_MergedGlobals, i32 0, i32 3), align 4, !tbaa !2
+    %dec = add nsw i32 %2, -1
+    store i32 %dec, i32* getelementptr inbounds (<{ i16, [2 x i8], i32, i32, [2 x i32] }>, <{ i16, [2 x i8], i32, i32, [2 x i32] }>* @_MergedGlobals, i32 0, i32 3), align 4, !tbaa !2
+    store i32 ptrtoint (i32* getelementptr inbounds (<{ i16, [2 x i8], i32, i32, [2 x i32] }>, <{ i16, [2 x i8], i32, i32, [2 x i32] }>* @_MergedGlobals, i32 0, i32 2) to i32), i32* @i, align 4, !tbaa !2
+    %conv1.i = sext i8 %1 to i16
+    store i16 %conv1.i, i16* getelementptr inbounds (<{ i16, [2 x i8], i32, i32, [2 x i32] }>, <{ i16, [2 x i8], i32, i32, [2 x i32] }>* @_MergedGlobals, i32 0, i32 0), align 4, !tbaa !9
+    %conv4.i = sext i8 %1 to i32
+    %3 = load i32, i32* getelementptr inbounds (<{ i16, [2 x i8], i32, i32, [2 x i32] }>, <{ i16, [2 x i8], i32, i32, [2 x i32] }>* @_MergedGlobals, i32 0, i32 2), align 4, !tbaa !2
+    %cmp.i = icmp sle i32 %3, %conv4.i
+    %conv6.i = zext i1 %cmp.i to i64
+    %4 = load i32, i32* getelementptr inbounds (<{ i16, [2 x i8], i32, i32, [2 x i32] }>, <{ i16, [2 x i8], i32, i32, [2 x i32] }>* @_MergedGlobals, i32 0, i32 4, i64 0), align 4, !tbaa !2
+    %conv7.i = sext i32 %4 to i64
+    %cmp.i.i = icmp eq i32 %4, 0
+    br i1 %cmp.i.i, label %r.exit, label %cond.false.i.i
+
+  cond.false.i.i:                                   ; preds = %s.exit
+    %div.i.i = udiv i64 %conv6.i, %conv7.i
+    br label %r.exit
+
+  r.exit:                                           ; preds = %cond.false.i.i, %s.exit
+    %cond.i.i = phi i64 [ %div.i.i, %cond.false.i.i ], [ %conv6.i, %s.exit ]
+    %conv8.i = trunc i64 %cond.i.i to i32
+    store i32 %conv8.i, i32* @g, align 4, !tbaa !2
+    store i32 ptrtoint ([2 x i32]* getelementptr inbounds (<{ i16, [2 x i8], i32, i32, [2 x i32] }>, <{ i16, [2 x i8], i32, i32, [2 x i32] }>* @_MergedGlobals, i32 0, i32 4) to i32), i32* @i, align 4, !tbaa !2
+    %5 = load i32, i32* getelementptr inbounds (<{ i16, [2 x i8], i32, i32, [2 x i32] }>, <{ i16, [2 x i8], i32, i32, [2 x i32] }>* @_MergedGlobals, i32 0, i32 3), align 4, !tbaa !2
+    store i32 %5, i32* @g, align 4, !tbaa !2
+    ret i32 undef
+  }
+
+  ; Function Attrs: nofree norecurse nounwind
+  define dso_local noalias i32* @p(i16 %ai, i32 %aj) local_unnamed_addr #0 {
+  entry:
+    %0 = load i32, i32* getelementptr inbounds (<{ i16, [2 x i8], i32, i32, [2 x i32] }>, <{ i16, [2 x i8], i32, i32, [2 x i32] }>* @_MergedGlobals, i32 0, i32 3), align 4, !tbaa !2
+    store i32 %0, i32* @g, align 4, !tbaa !2
+    ret i32* undef
+  }
+
+  ; Function Attrs: nofree norecurse nounwind
+  define dso_local noalias i32* @r(i32* %ak, i8 %al, i32 %am) local_unnamed_addr #0 {
+  entry:
+    %0 = ptrtoint i32* %ak to i64
+    %1 = trunc i64 %0 to i32
+    store i32 %1, i32* @i, align 4, !tbaa !2
+    %conv1 = sext i8 %al to i16
+    %2 = load i16, i16* getelementptr inbounds (<{ i16, [2 x i8], i32, i32, [2 x i32] }>, <{ i16, [2 x i8], i32, i32, [2 x i32] }>* @_MergedGlobals, i32 0, i32 0), align 4, !tbaa !9
+    %xor = xor i16 %2, %conv1
+    store i16 %xor, i16* getelementptr inbounds (<{ i16, [2 x i8], i32, i32, [2 x i32] }>, <{ i16, [2 x i8], i32, i32, [2 x i32] }>* @_MergedGlobals, i32 0, i32 0), align 4, !tbaa !9
+    %conv4 = sext i16 %xor to i32
+    %3 = load i32, i32* %ak, align 4, !tbaa !2
+    %cmp = icmp sle i32 %3, %conv4
+    %conv6 = zext i1 %cmp to i64
+    %4 = load i32, i32* getelementptr inbounds (<{ i16, [2 x i8], i32, i32, [2 x i32] }>, <{ i16, [2 x i8], i32, i32, [2 x i32] }>* @_MergedGlobals, i32 0, i32 4, i64 0), align 4, !tbaa !2
+    %conv7 = sext i32 %4 to i64
+    %cmp.i = icmp eq i32 %4, 0
+    br i1 %cmp.i, label %safe_div_func_uint64_t_u_u.exit, label %cond.false.i
+
+  cond.false.i:                                     ; preds = %entry
+    %div.i = udiv i64 %conv6, %conv7
+    br label %safe_div_func_uint64_t_u_u.exit
+
+  safe_div_func_uint64_t_u_u.exit:                  ; preds = %cond.false.i, %entry
+    %cond.i = phi i64 [ %div.i, %cond.false.i ], [ %conv6, %entry ]
+    %conv8 = trunc i64 %cond.i to i32
+    store i32 %conv8, i32* @g, align 4, !tbaa !2
+    store i32 ptrtoint ([2 x i32]* getelementptr inbounds (<{ i16, [2 x i8], i32, i32, [2 x i32] }>, <{ i16, [2 x i8], i32, i32, [2 x i32] }>* @_MergedGlobals, i32 0, i32 4) to i32), i32* @i, align 4, !tbaa !2
+    ret i32* undef
+  }
+
+  ; Function Attrs: norecurse nounwind readnone
+  define dso_local i32* @t(i32* nocapture readnone %ar, i32 %a, i32* nocapture readnone %as, i32* nocapture readnone %at, i16 %au) local_unnamed_addr #1 {
+  entry:
+    ret i32* inttoptr (i64 sext (i32 ptrtoint ([2 x i32]* getelementptr inbounds (<{ i16, [2 x i8], i32, i32, [2 x i32] }>, <{ i16, [2 x i8], i32, i32, [2 x i32] }>* @_MergedGlobals, i32 0, i32 4) to i32) to i64) to i32*)
+  }
+
+  ; Function Attrs: nofree norecurse nounwind
+  define dso_local nonnull i32* @s() local_unnamed_addr #0 {
+  entry:
+    store i32 0, i32* @g, align 4, !tbaa !2
+    %0 = load i32, i32* getelementptr inbounds ([1 x [8 x i32]], [1 x [8 x i32]]* @o, i64 0, i64 0, i64 0), align 4, !tbaa !2
+    %tobool = icmp eq i32 %0, 0
+    br i1 %tobool, label %for.end6, label %for.cond1.preheader.preheader
+
+  for.cond1.preheader.preheader:                    ; preds = %entry
+    store i32 7, i32* @i, align 4, !tbaa !2
+    br label %for.end6
+
+  for.end6:                                         ; preds = %for.cond1.preheader.preheader, %entry
+    store i32 8, i32* getelementptr inbounds (%union.e, %union.e* @k, i64 0, i32 0, i32 0), align 4, !tbaa !6
+    store i16 0, i16* getelementptr inbounds (<{ i16, [2 x i8], i32, i32, [2 x i32] }>, <{ i16, [2 x i8], i32, i32, [2 x i32] }>* @_MergedGlobals, i32 0, i32 0), align 4, !tbaa !9
+    store i32 2, i32* @g, align 4, !tbaa !2
+    ret i32* getelementptr inbounds (<{ i16, [2 x i8], i32, i32, [2 x i32] }>, <{ i16, [2 x i8], i32, i32, [2 x i32] }>* @_MergedGlobals, i32 0, i32 2)
+  }
+
+  ; Function Attrs: norecurse nounwind readnone
+  define dso_local i32 @main() local_unnamed_addr #1 {
+  entry:
+    ret i32 0
+  }
+
+  attributes #0 = { nofree norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="non-leaf" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+neon" "unsafe-fp-math"="false" "use-soft-float"="false" }
+  attributes #1 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="non-leaf" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+neon" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+  !llvm.module.flags = !{!0}
+  !llvm.ident = !{!1}
+
+  !0 = !{i32 1, !"wchar_size", i32 4}
+  !1 = !{!"Huawei Boole Compiler clang version 10.0.0 (clang-37cc7054ea8d flang-917030d95b7a)"}
+  !2 = !{!3, !3, i64 0}
+  !3 = !{!"int", !4, i64 0}
+  !4 = !{!"omnipotent char", !5, i64 0}
+  !5 = !{!"Simple C/C++ TBAA"}
+  !6 = !{!4, !4, i64 0}
+  !7 = !{!8, !4, i64 0}
+  !8 = !{!"a", !4, i64 0}
+  !9 = !{!10, !10, i64 0}
+  !10 = !{!"short", !4, i64 0}
+
+...
+---
+name:            b
+alignment:       4
+tracksRegLiveness: true
+frameInfo:
+  maxAlignment:    1
+  maxCallFrameSize: 0
+machineFunctionInfo: {}
+body:             |
+  bb.0.entry:
+    renamable $x8 = ADRP target-flags(aarch64-page) @o
+    renamable $w10 = LDRWui killed renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @o :: (dereferenceable load 4 from `i32* getelementptr inbounds ([1 x [8 x i32]], [1 x [8 x i32]]* @o, i64 0, i64 0, i64 0)`, !tbaa !2)
+    renamable $x8 = ADRP target-flags(aarch64-page) @g
+    STRWui $wzr, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @g :: (store 4 into @g, !tbaa !2)
+    renamable $x9 = ADRP target-flags(aarch64-page) @i
+    CBZW killed renamable $w10, %bb.2
+
+  bb.1.for.cond1.preheader.preheader.i:
+    liveins: $x8, $x9
+
+    renamable $w10 = MOVZWi 7, 0
+    STRWui killed renamable $w10, renamable $x9, target-flags(aarch64-pageoff, aarch64-nc) @i :: (store 4 into @i, !tbaa !2)
+
+  bb.2.s.exit:
+    liveins: $x8, $x9
+
+    renamable $x11 = ADRP target-flags(aarch64-page) @k
+    renamable $w12 = MOVZWi 8, 0
+    renamable $w13 = MOVZWi 2, 0
+    $x10 = ADRP target-flags(aarch64-page) @_MergedGlobals
+    renamable $x10 = ADDXri $x10, target-flags(aarch64-pageoff, aarch64-nc) @_MergedGlobals, 0
+    STRWui killed renamable $w12, killed renamable $x11, target-flags(aarch64-pageoff, aarch64-nc) @k :: (store 4 into `i32* getelementptr inbounds (%union.e, %union.e* @k, i64 0, i32 0, i32 0)`, !tbaa !6)
+    renamable $w11 = LDRWui renamable $x10, 2 :: (dereferenceable load 4 from `i32* getelementptr inbounds (<{ i16, [2 x i8], i32, i32, [2 x i32] }>, <{ i16, [2 x i8], i32, i32, [2 x i32] }>* @_MergedGlobals, i32 0, i32 3)`, !tbaa !2)
+    renamable $x12 = ADRP target-flags(aarch64-page) @m
+    STRWui killed renamable $w13, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @g :: (store 4 into @g, !tbaa !2)
+    renamable $w12 = LDRSBWui killed renamable $x12, target-flags(aarch64-pageoff, aarch64-nc) @m :: (dereferenceable load 1 from `i8* getelementptr inbounds (%struct.a, %struct.a* @m, i64 0, i32 0)`, !tbaa !7)
+    $x13 = ORRXrs $xzr, $x10, 0
+    renamable $w11 = nsw SUBWri killed renamable $w11, 1, 0
+    STRWui killed renamable $w11, renamable $x10, 2 :: (store 4 into `i32* getelementptr inbounds (<{ i16, [2 x i8], i32, i32, [2 x i32] }>, <{ i16, [2 x i8], i32, i32, [2 x i32] }>* @_MergedGlobals, i32 0, i32 3)`, !tbaa !2)
+    early-clobber renamable $x13, dead $wzr = LDRWpre killed renamable $x13, 4
+    renamable $x11 = LDRSWui renamable $x10, 3 :: (dereferenceable load 4 from `i32* getelementptr inbounds (<{ i16, [2 x i8], i32, i32, [2 x i32] }>, <{ i16, [2 x i8], i32, i32, [2 x i32] }>* @_MergedGlobals, i32 0, i32 4, i64 0)`, !tbaa !2)
+    STRWui renamable $w13, renamable $x9, target-flags(aarch64-pageoff, aarch64-nc) @i, implicit killed $x13 :: (store 4 into @i, !tbaa !2)
+    STRHHui killed renamable $w12, renamable $x10, 0 :: (store 2 into `i16* getelementptr inbounds (<{ i16, [2 x i8], i32, i32, [2 x i32] }>, <{ i16, [2 x i8], i32, i32, [2 x i32] }>* @_MergedGlobals, i32 0, i32 0)`, align 4, !tbaa !9)
+    renamable $w11 = LDRWui renamable $x10, 2 :: (dereferenceable load 4 from `i32* getelementptr inbounds (<{ i16, [2 x i8], i32, i32, [2 x i32] }>, <{ i16, [2 x i8], i32, i32, [2 x i32] }>* @_MergedGlobals, i32 0, i32 3)`, !tbaa !2)
+    renamable $w10 = ADDWri renamable $w10, 12, 0, implicit killed $x10, implicit-def $x10
+    STRWui renamable $w10, killed renamable $x9, target-flags(aarch64-pageoff, aarch64-nc) @i, implicit killed $x10 :: (store 4 into @i, !tbaa !2)
+    STRWui killed renamable $w11, killed renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @g :: (store 4 into @g, !tbaa !2)
+    RET undef $lr, implicit undef $w0
+
+...
+---
+name:            p
+alignment:       4
+tracksRegLiveness: true
+frameInfo:
+  maxAlignment:    1
+  maxCallFrameSize: 0
+machineFunctionInfo: {}
+body:             |
+  bb.0.entry:
+    renamable $x8 = ADRP target-flags(aarch64-page) @_MergedGlobals + 8
+    renamable $w8 = LDRWui killed renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @_MergedGlobals + 8 :: (dereferenceable load 4 from `i32* getelementptr inbounds (<{ i16, [2 x i8], i32, i32, [2 x i32] }>, <{ i16, [2 x i8], i32, i32, [2 x i32] }>* @_MergedGlobals, i32 0, i32 3)`, !tbaa !2)
+    renamable $x9 = ADRP target-flags(aarch64-page) @g
+    STRWui killed renamable $w8, killed renamable $x9, target-flags(aarch64-pageoff, aarch64-nc) @g :: (store 4 into @g, !tbaa !2)
+    RET undef $lr, implicit undef $x0
+
+...
+---
+name:            r
+alignment:       4
+tracksRegLiveness: true
+liveins:
+  - { reg: '$x0' }
+  - { reg: '$w1' }
+frameInfo:
+  maxAlignment:    1
+  maxCallFrameSize: 0
+machineFunctionInfo: {}
+body:             |
+  bb.0.entry:
+    liveins: $w1, $x0
+
+    $x9 = ADRP target-flags(aarch64-page) @_MergedGlobals
+    renamable $x9 = ADDXri $x9, target-flags(aarch64-pageoff, aarch64-nc) @_MergedGlobals, 0
+    renamable $w10 = LDRHHui renamable $x9, 0 :: (dereferenceable load 2 from `i16* getelementptr inbounds (<{ i16, [2 x i8], i32, i32, [2 x i32] }>, <{ i16, [2 x i8], i32, i32, [2 x i32] }>* @_MergedGlobals, i32 0, i32 0)`, align 4, !tbaa !9)
+    renamable $x8 = ADRP target-flags(aarch64-page) @i
+    STRWui renamable $w0, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @i :: (store 4 into @i, !tbaa !2)
+    renamable $w11 = SBFMWri killed renamable $w1, 0, 7
+    $w11 = EORWrs killed renamable $w10, killed renamable $w11, 0
+    STRHHui renamable $w11, renamable $x9, 0 :: (store 2 into `i16* getelementptr inbounds (<{ i16, [2 x i8], i32, i32, [2 x i32] }>, <{ i16, [2 x i8], i32, i32, [2 x i32] }>* @_MergedGlobals, i32 0, i32 0)`, align 4, !tbaa !9)
+    renamable $w12 = LDRWui killed renamable $x0, 0 :: (load 4 from %ir.ak, !tbaa !2)
+    renamable $x10 = LDRSWui killed renamable $x9, 3 :: (dereferenceable load 4 from `i32* getelementptr inbounds (<{ i16, [2 x i8], i32, i32, [2 x i32] }>, <{ i16, [2 x i8], i32, i32, [2 x i32] }>* @_MergedGlobals, i32 0, i32 4, i64 0)`, !tbaa !2)
+    dead $wzr = SUBSWrx killed renamable $w12, killed renamable $w11, 40, implicit-def $nzcv
+    renamable $w9 = CSINCWr $wzr, $wzr, 12, implicit $nzcv, implicit-def $x9
+    CBZW renamable $w10, %bb.2
+
+  bb.1.cond.false.i:
+    liveins: $x8, $x9, $x10
+
+    renamable $x9 = UDIVXr killed renamable $x9, killed renamable $x10
+
+  bb.2.safe_div_func_uint64_t_u_u.exit:
+    liveins: $x8, $x9
+
+    renamable $x10 = ADRP target-flags(aarch64-page) @g
+    $x11 = ADRP target-flags(aarch64-page) @_MergedGlobals
+    renamable $x11 = ADDXri $x11, target-flags(aarch64-pageoff, aarch64-nc) @_MergedGlobals, 0
+    STRWui renamable $w9, killed renamable $x10, target-flags(aarch64-pageoff, aarch64-nc) @g, implicit killed $x9 :: (store 4 into @g, !tbaa !2)
+    renamable $w9 = ADDWri renamable $w11, 12, 0, implicit killed $x11, implicit-def $x9
+    STRWui renamable $w9, killed renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @i, implicit killed $x9 :: (store 4 into @i, !tbaa !2)
+    RET undef $lr, implicit undef $x0
+
+...
+---
+name:            t
+alignment:       4
+tracksRegLiveness: true
+frameInfo:
+  maxAlignment:    1
+  maxCallFrameSize: 0
+machineFunctionInfo: {}
+body:             |
+  bb.0.entry:
+    $x8 = ADRP target-flags(aarch64-page) @_MergedGlobals
+    renamable $x8 = ADDXri $x8, target-flags(aarch64-pageoff, aarch64-nc) @_MergedGlobals, 0
+    renamable $w8 = ADDWri renamable $w8, 12, 0, implicit killed $x8, implicit-def $x8
+    renamable $x0 = SBFMXri killed renamable $x8, 0, 31
+    RET undef $lr, implicit $x0
+
+...
+---
+name:            s
+alignment:       4
+tracksRegLiveness: true
+frameInfo:
+  maxAlignment:    1
+  maxCallFrameSize: 0
+machineFunctionInfo: {}
+body:             |
+  bb.0.entry:
+    renamable $x8 = ADRP target-flags(aarch64-page) @o
+    renamable $w9 = LDRWui killed renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @o :: (dereferenceable load 4 from `i32* getelementptr inbounds ([1 x [8 x i32]], [1 x [8 x i32]]* @o, i64 0, i64 0, i64 0)`, !tbaa !2)
+    renamable $x8 = ADRP target-flags(aarch64-page) @g
+    STRWui $wzr, renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @g :: (store 4 into @g, !tbaa !2)
+    CBZW killed renamable $w9, %bb.2
+
+  bb.1.for.cond1.preheader.preheader:
+    liveins: $x8
+
+    renamable $x9 = ADRP target-flags(aarch64-page) @i
+    renamable $w10 = MOVZWi 7, 0
+    STRWui killed renamable $w10, killed renamable $x9, target-flags(aarch64-pageoff, aarch64-nc) @i :: (store 4 into @i, !tbaa !2)
+
+  bb.2.for.end6:
+    liveins: $x8
+
+    renamable $x9 = ADRP target-flags(aarch64-page) @k
+    renamable $w10 = MOVZWi 8, 0
+    $x0 = ADRP target-flags(aarch64-page) @_MergedGlobals
+    renamable $x0 = ADDXri $x0, target-flags(aarch64-pageoff, aarch64-nc) @_MergedGlobals, 0
+    STRWui killed renamable $w10, killed renamable $x9, target-flags(aarch64-pageoff, aarch64-nc) @k :: (store 4 into `i32* getelementptr inbounds (%union.e, %union.e* @k, i64 0, i32 0, i32 0)`, !tbaa !6)
+    early-clobber renamable $x0 = STRHHpost $wzr, killed renamable $x0, 4 :: (store 2 into `i16* getelementptr inbounds (<{ i16, [2 x i8], i32, i32, [2 x i32] }>, <{ i16, [2 x i8], i32, i32, [2 x i32] }>* @_MergedGlobals, i32 0, i32 0)`, align 4, !tbaa !9)
+    renamable $w9 = MOVZWi 2, 0
+    STRWui killed renamable $w9, killed renamable $x8, target-flags(aarch64-pageoff, aarch64-nc) @g :: (store 4 into @g, !tbaa !2)
+    RET undef $lr, implicit $x0
+
+...
+---
+name:            main
+alignment:       4
+tracksRegLiveness: true
+frameInfo:
+  maxAlignment:    1
+  maxCallFrameSize: 0
+machineFunctionInfo: {}
+body:             |
+  bb.0.entry:
+    $w0 = ORRWrs $wzr, $wzr, 0
+    RET undef $lr, implicit killed $w0
+
+...