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[DAGCombiner] allow store merging non-i8 truncated ops
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Authored by spatel on Aug 23 2020, 6:25 AM.

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Summary

We have a gap in our store merging capabilities for shift+truncate patterns as discussed in:
https://llvm.org/PR46662

I generalized the code/comments for this function in earlier commits, so we only need ease the type restriction and adjust the address/endian checking to make this work.
AArch64 lets us switch endian to make sure that patterns are matched either way.

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Event Timeline

spatel created this revision.Aug 23 2020, 6:25 AM
spatel requested review of this revision.Aug 23 2020, 6:25 AM
RKSimon edited the summary of this revision. (Show Details)Aug 26 2020, 2:35 AM
RKSimon accepted this revision.Aug 26 2020, 2:42 AM

LGTM - would you be able to get the "pair swap" rotate tweak done as a followup? Ideally with x86 test coverage as well.

This revision is now accepted and ready to land.Aug 26 2020, 2:42 AM

LGTM - would you be able to get the "pair swap" rotate tweak done as a followup? Ideally with x86 test coverage as well.

Yes, that doesn't seem like a big add-on. We allowed something like that in D83567.
Also, this code sits outside of all of the other store merging that we do in DAGCombiner, so there's potential for refactoring.

This revision was automatically updated to reflect the committed changes.