[AMDGPU] Spill register and offset register cannot be same

[hsmhsm]

Summary

Mark spill register as used so we will not choose it as offset register,
Otherwise, spill register may possibly get killed even before spill

[arsenm]

Needs test

[hsmhsm]

Added LLVM lit test

[arsenm]

llvm/test/CodeGen/AMDGPU/frame-pointer-spill.mir

4 ↗

(On Diff #285306)

Could use better name and comment what this is testing

6–45 ↗

(On Diff #285306)

You don't need most of these fields, probably just the stack related ones in machineFunctionInfo and tracksRegLiveness

46 ↗

(On Diff #285306)

Why do you need so many stack objects? Can you just add one artificial object that's big enough to force the huge frame?

[hsmhsm]

Fixed further review comments by Matt

[hsmhsm]

Add a comment

[hsmhsm]

Looks like this patch and the patch https://reviews.llvm.org/D85772 fix the same issue. Me and Austin discussed about it, and decided to go ahead with https://reviews.llvm.org/D85772 instead of this patch. So, I will close this patch once https://reviews.llvm.org/D85772 is merged.

[arsenm]

Can this be abandoned now?

[hsmhsm]

The fix is already taken care in the patch https://reviews.llvm.org/D85772, hence, I am closing this patch.

llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::BUFFER_STORE_DWORD_OFFSET))
       .addImm(0) // slc
       .addImm(0) // tfe
       .addImm(0) // dlc
       .addImm(0) // swz
       .addMemOperand(MMO);
     return;
   }
 
+  // Mark spill register as used so we will not choose it as `OffsetReg`,
+  // Otherwise, spill register may possibly get killed even before spill
+  LiveRegs.addReg(SpillReg);
+
   MCPhysReg OffsetReg = findScratchNonCalleeSaveRegister(
     MF->getRegInfo(), LiveRegs, AMDGPU::VGPR_32RegClass);
 
   BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32), OffsetReg)
     .addImm(Offset);
 
   BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::BUFFER_STORE_DWORD_OFFEN))
     .addReg(SpillReg, RegState::Kill)