CodeGen: Don't drop AA metadata when splitting MachineMemOperands

[arsenm]

Summary

Assuming this is used to split a memory access into smaller pieces,
the new access should still have the same aliasing properties as the
original memory access. As far as I can tell, this wasn't
intentionally dropped. It may be necessary to drop this if you are
moving the operand outside of the bounds of the original object in
such a way that it may alias another IR object, but I don't think any
of the existing users are doing this. Some of the uses widen into
unused alignment padding, which I think is OK.

[jdoerfert]

I don't know the operations performed here :(

[efriedma]

This is consistent with how we handle load splitting in other places; LGTM

llvm/lib/CodeGen/MachineFunction.cpp

483

Only tangentially related, but I think this comment isn't true anymore.

[arsenm]

79ce9bb3803998fc2a20ce1c88392cf292f35f92

llvm/lib/CodeGen/MachineFunction.cpp

 }
 
 MachineMemOperand *
 MachineFunction::getMachineMemOperand(const MachineMemOperand *MMO,
                                       int64_t Offset, uint64_t Size) {
   const MachinePointerInfo &PtrInfo = MMO->getPointerInfo();
 
   // If there is no pointer value, the offset isn't tracked so we need to adjust
   // the base alignment.
   Align Alignment = PtrInfo.V.isNull()
                         ? commonAlignment(MMO->getBaseAlign(), Offset)
                         : MMO->getBaseAlign();
 
+  // Do not preserve ranges, since we don't necessarily know what the high bits
+  // are anymore.
   return new (Allocator)
       MachineMemOperand(PtrInfo.getWithOffset(Offset), MMO->getFlags(), Size,
-                        Alignment, AAMDNodes(), nullptr, MMO->getSyncScopeID(),
+                        Alignment, MMO->getAAInfo(), nullptr, MMO->getSyncScopeID(),
                         MMO->getOrdering(), MMO->getFailureOrdering());
 }
 
 MachineMemOperand *
 MachineFunction::getMachineMemOperand(const MachineMemOperand *MMO,
                                       const AAMDNodes &AAInfo) {
   MachinePointerInfo MPI = MMO->getValue() ?
              MachinePointerInfo(MMO->getValue(), MMO->getOffset()) :

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

bool AMDGPULegalizerInfo::legalizeLoad(LegalizerHelper &Helper,
   if (shouldWidenLoad(ST, MemSize, AlignInBits, AddrSpace, MI.getOpcode())) {
     const unsigned WideMemSize = PowerOf2Ceil(MemSize);
 
     // This was already the correct extending load result type, so just adjust
     // the memory type.
     if (WideMemSize == ValSize) {
       MachineFunction &MF = B.getMF();
 
-      // FIXME: This is losing AA metadata
       MachineMemOperand *WideMMO =
           MF.getMachineMemOperand(MMO, 0, WideMemSize / 8);
       Observer.changingInstr(MI);
       MI.setMemRefs(MF, {WideMMO});
       Observer.changedInstr(MI);
       return true;
     }
 
     // Don't bother handling edge case that should probably never be produced.
     if (ValSize > WideMemSize)
       return false;
 
     LLT WideTy = widenToNextPowerOf2(ValTy);
 
-    // FIXME: This is losing AA metadata
     Register WideLoad;
     if (!WideTy.isVector()) {
       WideLoad = B.buildLoadFromOffset(WideTy, PtrReg, *MMO, 0).getReg(0);
       B.buildTrunc(ValReg, WideLoad).getReg(0);
     } else {
       // Extract the subvector.
 
       if (isRegisterType(ValTy)) {

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-memory-metadata.mir

 # tbaa is.
 ---
 name: widen_load_range0_tbaa
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1
     ; SI-LABEL: name: widen_load_range0_tbaa
     ; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
-    ; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load 4, addrspace 1)
+    ; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load 4, !tbaa !1, addrspace 1)
     ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
     ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
     ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
     ; SI: $vgpr0 = COPY [[AND]](s32)
     %0:_(p1) = COPY $vgpr0_vgpr1
     %1:_(s24) = G_LOAD %0 :: (load 3, align 4, addrspace 1, !range !0, !tbaa !1)
     %2:_(s32) = G_ZEXT %1
     $vgpr0 = COPY %2
 
 ...
 
 # Result register type already matches the widened memory type.
 ---
 name: widen_load_range1_tbaa
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1
     ; SI-LABEL: name: widen_load_range1_tbaa
     ; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
-    ; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load 4, addrspace 1)
+    ; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load 4, !tbaa !1, addrspace 1)
     ; SI: $vgpr0 = COPY [[LOAD]](s32)
     %0:_(p1) = COPY $vgpr0_vgpr1
     %1:_(s32) = G_LOAD %0 :: (load 3, align 4, addrspace 1, !range !0, !tbaa !1)
     $vgpr0 = COPY %1
 
 ...
 ---
 name: widen_load_tbaa0
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1
     ; SI-LABEL: name: widen_load_tbaa0
     ; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
-    ; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load 4, addrspace 1)
+    ; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load 4, !tbaa !1, addrspace 1)
     ; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
     ; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
     ; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
     ; SI: $vgpr0 = COPY [[AND]](s32)
     %0:_(p1) = COPY $vgpr0_vgpr1
     %1:_(s24) = G_LOAD %0 :: (load 3, align 4, addrspace 1, !tbaa !1)
     %2:_(s32) = G_ZEXT %1
     $vgpr0 = COPY %2
 
 ...
 
 # Result register type already matches the widened memory type.
 ---
 name: widen_load_tbaa1
 body: |
   bb.0:
     liveins: $vgpr0_vgpr1
     ; SI-LABEL: name: widen_load_tbaa1
     ; SI: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
-    ; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load 4, addrspace 1)
+    ; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load 4, !tbaa !1, addrspace 1)
     ; SI: $vgpr0 = COPY [[LOAD]](s32)
     %0:_(p1) = COPY $vgpr0_vgpr1
     %1:_(s32) = G_LOAD %0 :: (load 3, align 4, addrspace 1, !tbaa !1)
     $vgpr0 = COPY %1
 
 ...

llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-split-scalar-load-metadata.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -run-pass=regbankselect %s -o - | FileCheck -check-prefix=SI %s
+
+--- |
+
+  define amdgpu_ps i96 @split_smrd_load_range(i96 addrspace(4)* %ptr) {
+    %load = load i96, i96 addrspace(4)* %ptr, !range !0
+    ret i96 %load
+  }
+
+  define amdgpu_ps <3 x i32> @split_smrd_load_tbaa(<3 x i32> addrspace(4)* %ptr) {
+    %load = load <3 x i32>, <3 x i32> addrspace(4)* %ptr, !tbaa !1
+    ret <3 x i32> %load
+  }
+
+  !0 = !{i96 0, i96 9223372036854775808}
+  !1 = !{!"omnipotent char", !2}
+  !2 = !{!"Simple C/C++ TBAA"}
+...
+
+# Make sure range metadata is not preserved when widening loads, but
+# tbaa is.
+
+---
+name: split_smrd_load_range
+legalized: true
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1
+
+    ; SI-LABEL: name: split_smrd_load_range
+    ; SI: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
+    ; SI: [[LOAD:%[0-9]+]]:sgpr(<2 x s32>) = G_LOAD [[COPY]](p4) :: (load 8, addrspace 4)
+    ; SI: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 8
+    ; SI: [[PTR_ADD:%[0-9]+]]:sgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+    ; SI: [[LOAD1:%[0-9]+]]:sgpr(s32) = G_LOAD [[PTR_ADD]](p4) :: (load 4 + 8, align 8, addrspace 4)
+    ; SI: [[DEF:%[0-9]+]]:sgpr(<3 x s32>) = G_IMPLICIT_DEF
+    ; SI: [[INSERT:%[0-9]+]]:sgpr(<3 x s32>) = G_INSERT [[DEF]], [[LOAD]](<2 x s32>), 0
+    ; SI: [[INSERT1:%[0-9]+]]:sgpr(<3 x s32>) = G_INSERT [[INSERT]], [[LOAD1]](s32), 64
+    ; SI: $sgpr0_sgpr1_sgpr2 = COPY [[INSERT1]](<3 x s32>)
+    %0:_(p4) = COPY $sgpr0_sgpr1
+    %1:_(<3 x s32>) = G_LOAD %0 :: (load 12, align 8, addrspace 4, !range !0)
+    $sgpr0_sgpr1_sgpr2 = COPY %1
+
+...
+
+---
+name: split_smrd_load_tbaa
+legalized: true
+body: |
+  bb.0:
+    liveins: $sgpr0_sgpr1
+
+    ; SI-LABEL: name: split_smrd_load_tbaa
+    ; SI: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1
+    ; SI: [[LOAD:%[0-9]+]]:sgpr(<2 x s32>) = G_LOAD [[COPY]](p4) :: (load 8, !tbaa !2, addrspace 4)
+    ; SI: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 8
+    ; SI: [[PTR_ADD:%[0-9]+]]:sgpr(p4) = G_PTR_ADD [[COPY]], [[C]](s64)
+    ; SI: [[LOAD1:%[0-9]+]]:sgpr(s32) = G_LOAD [[PTR_ADD]](p4) :: (load 4 + 8, align 8, !tbaa !2, addrspace 4)
+    ; SI: [[DEF:%[0-9]+]]:sgpr(<3 x s32>) = G_IMPLICIT_DEF
+    ; SI: [[INSERT:%[0-9]+]]:sgpr(<3 x s32>) = G_INSERT [[DEF]], [[LOAD]](<2 x s32>), 0
+    ; SI: [[INSERT1:%[0-9]+]]:sgpr(<3 x s32>) = G_INSERT [[INSERT]], [[LOAD1]](s32), 64
+    ; SI: $sgpr0_sgpr1_sgpr2 = COPY [[INSERT1]](<3 x s32>)
+    %0:_(p4) = COPY $sgpr0_sgpr1
+    %1:_(<3 x s32>) = G_LOAD %0 :: (load 12, align 8, addrspace 4, !tbaa !1)
+    $sgpr0_sgpr1_sgpr2 = COPY %1
+
+...