[PowerPC][PCRelative] Set TLS unsupported with PC relative memops

[kamaub]

Summary

Introduce a fatal error if any thread local storage code is compiled
using pc relative memory operations as well as a hidden override
option -enable-ppc-pcrel-tls so that this support can be incrementally
added if possible.

[kamaub]

Replacing assert() with report_fatal_error()

[nemanjai]

Feel free to address the comment when committing the patch.

llvm/test/CodeGen/PowerPC/pcrel-tls.ll

5

This doesn't work on every configuration. Please remove it and we can add a run line once PC-Rel TLS is implemented and no longer trips the assert.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

 cl::desc("disable sibling call optimization on ppc"), cl::Hidden);
 
 static cl::opt<bool> DisableInnermostLoopAlign32("disable-ppc-innermost-loop-align32",
 cl::desc("don't always align innermost loop to 32 bytes on ppc"), cl::Hidden);
 
 static cl::opt<bool> UseAbsoluteJumpTables("ppc-use-absolute-jumptables",
 cl::desc("use absolute jump tables on ppc"), cl::Hidden);
 
+static cl::opt<bool> EnablePPCPCRelTLS(
+    "enable-ppc-pcrel-tls",
+    cl::desc("enable the use of PC relative memops in TLS instructions on PPC"),
+    cl::Hidden);
+
 STATISTIC(NumTailCalls, "Number of tail calls");
 STATISTIC(NumSiblingCalls, "Number of sibling calls");
 STATISTIC(ShufflesHandledWithVPERM, "Number of shuffles lowered to a VPERM");
 STATISTIC(NumDynamicAllocaProbed, "Number of dynamic stack allocation probed");
 
 static bool isNByteElemShuffleMask(ShuffleVectorSDNode *, unsigned, int);
 
 static SDValue widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl);

 }
 
 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
                                               SelectionDAG &DAG) const {
   // FIXME: TLS addresses currently use medium model code sequences,
   // which is the most useful form.  Eventually support for small and
   // large models could be added if users need it, at the cost of
   // additional complexity.
+  if (Subtarget.isUsingPCRelativeCalls())
+    assert(EnablePPCPCRelTLS &&
+           "Thread local storage is not supported with pc-relative addressing "
+           "- please compile with -mno-pcrel");
   GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
   if (DAG.getTarget().useEmulatedTLS())
     return LowerToTLSEmulatedModel(GA, DAG);
 
   SDLoc dl(GA);
   const GlobalValue *GV = GA->getGlobal();
   EVT PtrVT = getPointerTy(DAG.getDataLayout());
   bool is64bit = Subtarget.isPPC64();

llvm/test/CodeGen/PowerPC/pcrel-tls.ll

+; RUN: not --crash llc -mcpu=pwr10 -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -verify-machineinstrs -mattr=+pcrelative-memops -o - < %s 2>&1 | \
+; RUN:   FileCheck %s --check-prefix=CHECK-PCREL
+; RUN: not --crash llc -mcpu=pwr10 -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -verify-machineinstrs -mattr=+pcrelative-memops -enable-ppc-pcrel-tls \
+; RUN:   -o - < %s 2>&1 | FileCheck %s --check-prefix=CHECK-PCREL-TLS
+; RUN: llc -mcpu=pwr10 -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -verify-machineinstrs -mattr=-pcrelative-memops -o - < %s 2>&1 | \
+; RUN:   FileCheck %s --check-prefix=CHECK-NOPCREL
+
+; CHECK-PCREL:     Thread local storage is not supported with pc-relative addressing
+; CHECK-PCREL-TLS: TOC pointer used in a function using PC-Relative addressing!
+; CHECK-NOPCREL:   blr
+
+@x = external thread_local global i32, align 4
+
+define i32* @testTLS() {
+entry:
+  ret i32* @x
+}