[RISCV] add the MC layer support of riscv vector Zvamo extension

[HsiangKai]

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

988

"If index EEW is greater than XLEN, an illegal instruction exception is raised."

We could collect all AMO instructions with EEW = 64 into one place and use "Predicates = [IsRV64]" to ensure XLEN >= EEW.

[HsiangKai]

llvm/lib/Target/RISCV/RISCV.td

152

Zvamo should imply 'A' extension and 'V' extension.

def FeatureExtZvamo
    : SubtargetFeature<"experimental-zvamo", "HasStdExtZvamo", "true",
                      "'Zvamo'(Vector AMO Operations)",
                      [FeatureStdExtA, FeatureStdExtV]>;

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

984

Zvamo should imply 'A' extension and 'V' extension. So, use HasStdExtZvamo is enough.

1029

Ditto.

llvm/test/MC/RISCV/rvv/zvamo.s

2

--mattr=+experimental-zvamo is enough.

16

instruction requires the following: 'Zvamo'(Vector AMO Operations)

[StephenFan]

remove the hasStdExtV and hasStdExtA predicates, and add the IsRV64 predicates

[HsiangKai]

I confused the relationship of sub-extensions before. Sorry for that.
There are some discussions[0] about the relationship between vector sub-extensions. It seems that


V-extension implies Zvamo + Zvlsseg

Zvqmac, Zvamo and Zvlsseg are stand alone sub extensions. That is, Zvamo does not imply V extension.

Zvqmac has no implied extensions.
Zvamo implies A-extension.
Zvlsseg has no implied extensions.

Do you agree with that?

[0] https://github.com/riscv/riscv-v-spec/issues/546

[kito-cheng]

Zvamo implies A-extension.

I think it's require instead of imply?

RVV Spec 8. Vector AMO Operations:

If vector AMO instructions are supported, then the scalar Zaamo instructions (atomic operations from the standard A extension) must be present.

[StephenFan]

In D85069#2201754, @HsiangKai wrote:

I confused the relationship of sub-extensions before. Sorry for that.
There are some discussions[0] about the relationship between vector sub-extensions. It seems that


V-extension implies Zvamo + Zvlsseg

Zvqmac, Zvamo and Zvlsseg are stand alone sub extensions. That is, Zvamo does not imply V extension.

Zvqmac has no implied extensions.
Zvamo implies A-extension.
Zvlsseg has no implied extensions.

Do you agree with that?

[0] https://github.com/riscv/riscv-v-spec/issues/546

So, let me summarize:
Zvlsseg has no implied extensions
Zvqmac has no implied extensions
Zvamo required A extension ? If so, is it suitable that use -mattr=+a, +experimental-zvamo to enable the zvamo extension?

[HsiangKai]

In D85069#2204470, @StephenFan wrote:

In D85069#2201754, @HsiangKai wrote:

I confused the relationship of sub-extensions before. Sorry for that.
There are some discussions[0] about the relationship between vector sub-extensions. It seems that


V-extension implies Zvamo + Zvlsseg

Zvqmac, Zvamo and Zvlsseg are stand alone sub extensions. That is, Zvamo does not imply V extension.

Zvqmac has no implied extensions.
Zvamo implies A-extension.
Zvlsseg has no implied extensions.

Do you agree with that?

[0] https://github.com/riscv/riscv-v-spec/issues/546

So, let me summarize:
Zvlsseg has no implied extensions
Zvqmac has no implied extensions
Zvamo required A extension ? If so, is it suitable that use -mattr=+a, +experimental-zvamo to enable the zvamo extension?

Currently, FeatureStdExtV is the base V instructions. So, I will suggest the following relationships

Zvamo -> V (Does Zvamo -> A? I create an issue about it. https://github.com/riscv/riscv-v-spec/issues/555)
Zvqmac -> V
Zvlsseg -> V

The implementation looks like

def FeatureExtZvamo
    : SubtargetFeature<"experimental-zvamo", "HasStdExtZvamo", "true",
                       "'Zvamo'(Vector AMO Operations)",
                       [FeatureStdExtV]>;

def FeatureExtZvqmac
    : SubtargetFeature<"experimental-zvqmac", "HasStdExtZvqmac", "true",
                       "'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)",
                       [FeatureStdExtV]>;

def FeatureStdExtZvlsseg
    : SubtargetFeature<"experimental-zvlsseg", "HasStdExtZvlsseg", "true",
                       "'Zvlsseg' (Vector segment load/store instructions)”,
                       [FeatureStdExtV]>;

In the future, “current V” may be changed to Zvbase in the specification. And “new V” will imply Zvbase + Zvamo + Zvlsseg. As described in https://github.com/riscv/riscv-v-spec/issues/547#issuecomment-670667964.

[HsiangKai]

llvm/lib/Target/RISCV/RISCV.td

161

There is no conclusion from 'V' specification. I think we could be conservative as Kito said. Zvamo does not imply 'A'.

Please remove FeatureStdExtA from the list. Sorry for that.

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

984

Add HasStdExtA.

1022

Add HasStdExtA.

llvm/test/MC/RISCV/rvv/zvamo.s

3

--mattr=+a,experimental-zvamo

[HsiangKai]

Just a couple of nits, but otherwise it LGTM.

llvm/lib/Target/RISCV/RISCVInstrFormatsV.td

330

Redundant space at the end.

llvm/lib/Target/RISCV/RISCVSchedRocket32.td

20

Rebase on master to include HasStdExtZvlsseg.

llvm/lib/Target/RISCV/RISCVSchedRocket64.td

19

Rebase on master to include HasStdExtZvlsseg.

[StephenFan]

rebase to latest master

llvm/lib/Target/RISCV/RISCV.td

def FeatureNoRVCHints
     : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
                        "Disable RVC Hint Instructions.">;
 def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
                   AssemblerPredicate<(all_of(not FeatureNoRVCHints)),
                                      "RVC Hint Instructions">;
 
 def FeatureStdExtV
     : SubtargetFeature<"experimental-v", "HasStdExtV", "true",
                        "'V' (Vector Instructions)",
                        [FeatureStdExtF]>;
 def HasStdExtV : Predicate<"Subtarget->hasStdExtV()">,
                            AssemblerPredicate<(all_of FeatureStdExtV),
                            "'V' (Vector Instructions)">;
 
 def FeatureStdExtZvlsseg
     : SubtargetFeature<"experimental-zvlsseg", "HasStdExtZvlsseg", "true",
                        "'Zvlsseg' (Vector segment load/store instructions)",
                        [FeatureStdExtV]>;
 def HasStdExtZvlsseg : Predicate<"Subtarget->hasStdExtZvlsseg()">,
                         AssemblerPredicate<(all_of FeatureStdExtZvlsseg),
                         "'Zvlsseg' (Vector segment load/store instructions)">;
+def FeatureExtZvamo
+    : SubtargetFeature<"experimental-zvamo", "HasStdExtZvamo", "true",
+                       "'Zvamo'(Vector AMO Operations)",
+                       [FeatureStdExtV]>;
+def HasStdExtZvamo : Predicate<"Subtarget->hasStdExtZvamo()">,
+                              AssemblerPredicate<(all_of FeatureExtZvamo),
+                              "'Zvamo'(Vector AMO Operations)">;
 
 def Feature64Bit
     : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
 def IsRV64 : Predicate<"Subtarget->is64Bit()">,
                        AssemblerPredicate<(all_of Feature64Bit),
                        "RV64I Base Instruction Set">;
 def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
                        AssemblerPredicate<(all_of (not Feature64Bit)),

llvm/lib/Target/RISCV/RISCVInstrFormatsV.td

class RISCVLSUMOP<bits<5> val> {
   bits<5> Value = val;
 }
 def LUMOPUnitStride  : RISCVLSUMOP<0b00000>;
 def LUMOPUnitStrideWholeReg : RISCVLSUMOP<0b01000>;
 def LUMOPUnitStrideFF: RISCVLSUMOP<0b10000>;
 def SUMOPUnitStride  : RISCVLSUMOP<0b00000>;
 def SUMOPUnitStrideWholeReg : RISCVLSUMOP<0b01000>;
 
+class RISCVAMOOP<bits<5> val> {
+  bits<5> Value = val;
+}
+def AMOOPVamoSwap : RISCVAMOOP<0b00001>;
+def AMOOPVamoAdd : RISCVAMOOP<0b00000>;
+def AMOOPVamoXor : RISCVAMOOP<0b00100>;
+def AMOOPVamoAnd : RISCVAMOOP<0b01100>;
+def AMOOPVamoOr : RISCVAMOOP<0b01000>;
+def AMOOPVamoMin : RISCVAMOOP<0b10000>;
+def AMOOPVamoMax : RISCVAMOOP<0b10100>;
+def AMOOPVamoMinu : RISCVAMOOP<0b11000>;
+def AMOOPVamoMaxu : RISCVAMOOP<0b11100>;
+
 class RISCVWidth<bits<4> val> {
   bits<4> Value = val;
 }
 def LSWidth8     : RISCVWidth<0b0000>;
 def LSWidth16    : RISCVWidth<0b0101>;
 def LSWidth32    : RISCVWidth<0b0110>;
 def LSWidth64    : RISCVWidth<0b0111>;
 def LSWidth128   : RISCVWidth<0b1000>;
class RVInstVSX<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
   let Inst{24-20} = vs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = width;
   let Inst{11-7} = vs3;
   let Opcode = OPC_STORE_FP.Value;
 
   let Uses = [VTYPE, VL];
 }
+
+class RVInstVAMO<RISCVAMOOP amoop, bits<3> width, dag outs, 
+                 dag ins, string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+  bits<5> vs2;
+  bits<5> rs1;
+  bit wd;
+  bit vm;
+
+  let Inst{31-27} = amoop.Value;
+  let Inst{26} = wd;
+  let Inst{25} = vm;
+  let Inst{24-20} = vs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = width;
+  let Opcode = OPC_AMO.Value;
+
+  let Uses = [VTYPE, VL];
+}

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

 
 // op vd, vs2, vm (use vs1 as instruction encoding)
 class VALUVs2<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr>
     : RVInstV<funct6, vs1, opv, (outs VRegOp:$vd),
                (ins VRegOp:$vs2, VMaskOp:$vm),
                opcodestr, "$vd, $vs2$vm">;
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 
+let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in {
+// vamo vd, (rs1), vs2, vd, vm
+class VAMOWd<RISCVAMOOP amoop, RISCVWidth width, string opcodestr>
+    : RVInstVAMO<amoop, width.Value{2-0}, (outs VRegOp:$vd_wd),
+            (ins GPR:$rs1, VRegOp:$vs2, VRegOp:$vd, VMaskOp:$vm),
+            opcodestr, "$vd_wd, (${rs1}), $vs2, $vd$vm"> {
+    let Constraints = "$vd_wd = $vd";
+    let wd = 1;
+    bits<5> vd;
+    let Inst{11-7} = vd;
+}
+
+// vamo x0, (rs1), vs2, vs3, vm
+class VAMONoWd<RISCVAMOOP amoop, RISCVWidth width, string opcodestr>
+    : RVInstVAMO<amoop, width.Value{2-0}, (outs),
+            (ins GPR:$rs1, VRegOp:$vs2, VRegOp:$vs3, VMaskOp:$vm),
+            opcodestr, "x0, (${rs1}), $vs2, $vs3$vm"> {
+    bits<5> vs3;
+    let Inst{11-7} = vs3;
+}
+
+} // hasSideEffects = 0, mayLoad = 1, mayStore = 1
+
 //===----------------------------------------------------------------------===//
 // Combination of instruction classes.
 // Use these multiclasses to define instructions more easily.
 //===----------------------------------------------------------------------===//
 multiclass VALU_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
   def V  : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">;
   def X  : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">;
   def I  : VALUVI<funct6, opcodestr # "." # vw # "i", optype>;

 multiclass VALU_FV_V<string opcodestr, bits<6> funct6> {
   def _VS : VALUVV<funct6, OPFVV, opcodestr # ".vs">;
 }
 
 multiclass VALU_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
   def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>;
 }
 
+multiclass VAMO<RISCVAMOOP amoop, RISCVWidth width, string opcodestr> {
+  def _WD : VAMOWd<amoop, width, opcodestr>;
+  def _UNWD : VAMONoWd<amoop, width, opcodestr>;
+}
+
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtV] in {
 let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
 def VSETVLI : RVInstSetVLi<(outs GPR:$rd), (ins GPR:$rs1, VTypeIOp:$vtypei),
                            "vsetvli", "$rd, $rs1, $vtypei">;
def VMV#nf#R_V  : RVInstV<0b100111, !add(nf, -1), OPIVI, (outs VRegOp:$vd),
                             "$vd, $vs2"> {
     let Uses = [];
     let vm = 1;
   }
 }
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 } // Predicates = [HasStdExtV]
 
 let Predicates = [HasStdExtZvlsseg] in {
   foreach nf=2-8 in {
     def VLSEG#nf#E8_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth8, "vlseg"#nf#"e8.v">;
     def VLSEG#nf#E16_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth16, "vlseg"#nf#"e16.v">;
     def VLSEG#nf#E32_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth32, "vlseg"#nf#"e32.v">;
     def VLSEG#nf#E64_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth64, "vlseg"#nf#"e64.v">;
     def VLSEG#nf#E128_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth128, "vlseg"#nf#"e128.v">;
     def VLSEG#nf#E256_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth256, "vlseg"#nf#"e256.v">;
     def VLSEG#nf#E512_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth512, "vlseg"#nf#"e512.v">;
     def VLSEG#nf#E1024_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth1024, "vlseg"#nf#"e1024.v">;
 
     def VLSEG#nf#E8FF_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStrideFF, LSWidth8, "vlseg"#nf#"e8ff.v">;
     def VLSEG#nf#E16FF_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStrideFF, LSWidth16, "vlseg"#nf#"e16ff.v">;
foreach nf=2-8 in {
     def VLSSEG#nf#E8_V : VStridedSegmentLoad<!add(nf, -1), LSWidth8, "vlsseg"#nf#"e8.v">;
     def VLSSEG#nf#E16_V : VStridedSegmentLoad<!add(nf, -1), LSWidth16, "vlsseg"#nf#"e16.v">;
     def VLSSEG#nf#E32_V : VStridedSegmentLoad<!add(nf, -1), LSWidth32, "vlsseg"#nf#"e32.v">;
     def VLSSEG#nf#E64_V : VStridedSegmentLoad<!add(nf, -1), LSWidth64, "vlsseg"#nf#"e64.v">;
     def VLSSEG#nf#E128_V : VStridedSegmentLoad<!add(nf, -1), LSWidth128, "vlsseg"#nf#"e128.v">;
     def VLSSEG#nf#E256_V : VStridedSegmentLoad<!add(nf, -1), LSWidth256, "vlsseg"#nf#"e256.v">;
     def VLSSEG#nf#E512_V : VStridedSegmentLoad<!add(nf, -1), LSWidth512, "vlsseg"#nf#"e512.v">;
     def VLSSEG#nf#E1024_V : VStridedSegmentLoad<!add(nf, -1), LSWidth1024, "vlsseg"#nf#"e1024.v">;
 
     def VSSSEG#nf#E8_V : VStridedSegmentStore<!add(nf, -1), LSWidth8, "vssseg"#nf#"e8.v">;
     def VSSSEG#nf#E16_V : VStridedSegmentStore<!add(nf, -1), LSWidth16, "vssseg"#nf#"e16.v">;
     def VSSSEG#nf#E32_V : VStridedSegmentStore<!add(nf, -1), LSWidth32, "vssseg"#nf#"e32.v">;
     def VSSSEG#nf#E64_V : VStridedSegmentStore<!add(nf, -1), LSWidth64, "vssseg"#nf#"e64.v">;
     def VSSSEG#nf#E128_V : VStridedSegmentStore<!add(nf, -1), LSWidth128, "vssseg"#nf#"e128.v">;
     def VSSSEG#nf#E256_V : VStridedSegmentStore<!add(nf, -1), LSWidth256, "vssseg"#nf#"e256.v">;
     def VSSSEG#nf#E512_V : VStridedSegmentStore<!add(nf, -1), LSWidth512, "vssseg"#nf#"e512.v">;
     def VSSSEG#nf#E1024_V : VStridedSegmentStore<!add(nf, -1), LSWidth1024, "vssseg"#nf#"e1024.v">;
 
     // Vector Indexed Instructions
     def VLXSEG#nf#EI8_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth8, "vlxseg"#nf#"ei8.v">;
     def VLXSEG#nf#EI16_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth16, "vlxseg"#nf#"ei16.v">;
     def VLXSEG#nf#EI32_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth32, "vlxseg"#nf#"ei32.v">;
     def VLXSEG#nf#EI64_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth64, "vlxseg"#nf#"ei64.v">;
     def VLXSEG#nf#EI128_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth128, "vlxseg"#nf#"ei128.v">;
     def VLXSEG#nf#EI256_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth256, "vlxseg"#nf#"ei256.v">;
     def VLXSEG#nf#EI512_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth512, "vlxseg"#nf#"ei512.v">;
     def VLXSEG#nf#EI1024_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth1024, "vlxseg"#nf#"ei1024.v">;
 
     def VSXSEG#nf#EI8_V : VIndexedSegmentStore<!add(nf, -1), LSWidth8, "vsxseg"#nf#"ei8.v">;
     def VSXSEG#nf#EI16_V : VIndexedSegmentStore<!add(nf, -1), LSWidth16, "vsxseg"#nf#"ei16.v">;
     def VSXSEG#nf#EI32_V : VIndexedSegmentStore<!add(nf, -1), LSWidth32, "vsxseg"#nf#"ei32.v">;
     def VSXSEG#nf#EI64_V : VIndexedSegmentStore<!add(nf, -1), LSWidth64, "vsxseg"#nf#"ei64.v">;
     def VSXSEG#nf#EI128_V : VIndexedSegmentStore<!add(nf, -1), LSWidth128, "vsxseg"#nf#"ei128.v">;
     def VSXSEG#nf#EI256_V : VIndexedSegmentStore<!add(nf, -1), LSWidth256, "vsxseg"#nf#"ei256.v">;
     def VSXSEG#nf#EI512_V : VIndexedSegmentStore<!add(nf, -1), LSWidth512, "vsxseg"#nf#"ei512.v">;
     def VSXSEG#nf#EI1024_V : VIndexedSegmentStore<!add(nf, -1), LSWidth1024, "vsxseg"#nf#"ei1024.v">;
   }
 } // Predicates = [HasStdExtZvlsseg]
+
+let Predicates = [HasStdExtZvamo, HasStdExtA] in {
+  defm VAMOSWAPEI8 : VAMO<AMOOPVamoSwap, LSWidth8, "vamoswapei8.v">;
+  defm VAMOSWAPEI16 : VAMO<AMOOPVamoSwap, LSWidth16, "vamoswapei16.v">;
+  defm VAMOSWAPEI32 : VAMO<AMOOPVamoSwap, LSWidth32, "vamoswapei32.v">;
+
+  defm VAMOADDEI8 : VAMO<AMOOPVamoAdd, LSWidth8, "vamoaddei8.v">;
+  defm VAMOADDEI16 : VAMO<AMOOPVamoAdd, LSWidth16, "vamoaddei16.v">;
+  defm VAMOADDEI32 : VAMO<AMOOPVamoAdd, LSWidth32, "vamoaddei32.v">;
+
+  defm VAMOXOREI8 : VAMO<AMOOPVamoXor, LSWidth8, "vamoxorei8.v">;
+  defm VAMOXOREI16 : VAMO<AMOOPVamoXor, LSWidth16, "vamoxorei16.v">;
+  defm VAMOXOREI32 : VAMO<AMOOPVamoXor, LSWidth32, "vamoxorei32.v">;
+
+  defm VAMOANDEI8 : VAMO<AMOOPVamoAnd, LSWidth8, "vamoandei8.v">;
+  defm VAMOANDEI16 : VAMO<AMOOPVamoAnd, LSWidth16, "vamoandei16.v">;
+  defm VAMOANDEI32 : VAMO<AMOOPVamoAnd, LSWidth32, "vamoandei32.v">;
+
+  defm VAMOOREI8 : VAMO<AMOOPVamoOr, LSWidth8, "vamoorei8.v">;
+  defm VAMOOREI16 : VAMO<AMOOPVamoOr, LSWidth16, "vamoorei16.v">;
+  defm VAMOOREI32 : VAMO<AMOOPVamoOr, LSWidth32, "vamoorei32.v">;
+
+  defm VAMOMINEI8 : VAMO<AMOOPVamoMin, LSWidth8, "vamominei8.v">;
+  defm VAMOMINEI16 : VAMO<AMOOPVamoMin, LSWidth16, "vamominei16.v">;
+  defm VAMOMINEI32 : VAMO<AMOOPVamoMin, LSWidth32, "vamominei32.v">;
+
+  defm VAMOMAXEI8 : VAMO<AMOOPVamoMax, LSWidth8, "vamomaxei8.v">;
+  defm VAMOMAXEI16 : VAMO<AMOOPVamoMax, LSWidth16, "vamomaxei16.v">;
+  defm VAMOMAXEI32 : VAMO<AMOOPVamoMax, LSWidth32, "vamomaxei32.v">;
+
+  defm VAMOMINUEI8 : VAMO<AMOOPVamoMinu, LSWidth8, "vamominuei8.v">;
+  defm VAMOMINUEI16 : VAMO<AMOOPVamoMinu, LSWidth16, "vamominuei16.v">;
+  defm VAMOMINUEI32 : VAMO<AMOOPVamoMinu, LSWidth32, "vamominuei32.v">;
+
+  defm VAMOMAXUEI8 : VAMO<AMOOPVamoMaxu, LSWidth8, "vamomaxuei8.v">;
+  defm VAMOMAXUEI16 : VAMO<AMOOPVamoMaxu, LSWidth16, "vamomaxuei16.v">;
+  defm VAMOMAXUEI32 : VAMO<AMOOPVamoMaxu, LSWidth32, "vamomaxuei32.v">;
+} // Predicates = [HasStdExtZvamo, HasStdExtA]
+
+let Predicates = [HasStdExtZvamo, HasStdExtA, IsRV64] in {
+  defm VAMOSWAPEI64 : VAMO<AMOOPVamoSwap, LSWidth64, "vamoswapei64.v">;
+  defm VAMOADDEI64 : VAMO<AMOOPVamoAdd, LSWidth64, "vamoaddei64.v">;
+  defm VAMOXOREI64 : VAMO<AMOOPVamoXor, LSWidth64, "vamoxorei64.v">;
+  defm VAMOANDEI64 : VAMO<AMOOPVamoAnd, LSWidth64, "vamoandei64.v">;
+  defm VAMOOREI64 : VAMO<AMOOPVamoOr, LSWidth64, "vamoorei64.v">;
+  defm VAMOMINEI64 : VAMO<AMOOPVamoMin, LSWidth64, "vamominei64.v">;
+  defm VAMOMAXEI64 : VAMO<AMOOPVamoMax, LSWidth64, "vamomaxei64.v">;
+  defm VAMOMINUEI64 : VAMO<AMOOPVamoMinu, LSWidth64, "vamominuei64.v">;
+  defm VAMOMAXUEI64 : VAMO<AMOOPVamoMaxu, LSWidth64, "vamomaxuei64.v">;
+} // Predicates = [HasStdExtZvamo, HasStdExtA, IsRV64]

llvm/lib/Target/RISCV/RISCVSchedRocket32.td

 
 // Rocket machine model for scheduling and other instruction cost heuristics.
 def Rocket32Model : SchedMachineModel {
   let MicroOpBufferSize = 0; // Explicitly set to zero since Rocket is in-order.
   let IssueWidth = 1;        // 1 micro-ops are dispatched per cycle.
   let LoadLatency = 3;
   let MispredictPenalty = 3;
   let CompleteModel = 1;
-  let UnsupportedFeatures = [HasStdExtV, HasStdExtZvlsseg];
+  let UnsupportedFeatures = [HasStdExtV, HasStdExtZvlsseg, HasStdExtZvamo];
 }
 
 //===----------------------------------------------------------------------===//
 // Define each kind of processor resource and number available.
 
 // Modeling each pipeline as a ProcResource using the BufferSize = 0 since
 // Rocket is in-order.
 

llvm/lib/Target/RISCV/RISCVSchedRocket64.td

 // This works with MachineScheduler. See MCSchedule.h for details.
 
 // Rocket machine model for scheduling and other instruction cost heuristics.
 def Rocket64Model : SchedMachineModel {
   let MicroOpBufferSize = 0; // Explicitly set to zero since Rocket is in-order.
   let IssueWidth = 1;        // 1 micro-ops are dispatched per cycle.
   let LoadLatency = 3;
   let MispredictPenalty = 3;
-  let UnsupportedFeatures = [HasStdExtV, HasStdExtZvlsseg];
+  let UnsupportedFeatures = [HasStdExtV, HasStdExtZvlsseg, HasStdExtZvamo];
 }
 
 //===----------------------------------------------------------------------===//
 // Define each kind of processor resource and number available.
 
 // Modeling each pipeline as a ProcResource using the BufferSize = 0 since
 // Rocket is in-order.
 

llvm/lib/Target/RISCV/RISCVSubtarget.h

class RISCVSubtarget : public RISCVGenSubtargetInfo {
   bool HasStdExtZbm = false;
   bool HasStdExtZbp = false;
   bool HasStdExtZbr = false;
   bool HasStdExtZbs = false;
   bool HasStdExtZbt = false;
   bool HasStdExtZbproposedc = false;
   bool HasStdExtV = false;
   bool HasStdExtZvlsseg = false;
+  bool HasStdExtZvamo = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
   bool EnableLinkerRelax = false;
   bool EnableRVCHintInstrs = true;
   bool EnableSaveRestore = false;
   unsigned XLen = 32;
   MVT XLenVT = MVT::i32;
   RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
public:
   bool hasStdExtZbm() const { return HasStdExtZbm; }
   bool hasStdExtZbp() const { return HasStdExtZbp; }
   bool hasStdExtZbr() const { return HasStdExtZbr; }
   bool hasStdExtZbs() const { return HasStdExtZbs; }
   bool hasStdExtZbt() const { return HasStdExtZbt; }
   bool hasStdExtZbproposedc() const { return HasStdExtZbproposedc; }
   bool hasStdExtV() const { return HasStdExtV; }
   bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; }
+  bool hasStdExtZvamo() const { return HasStdExtZvamo; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
   bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; }
   bool enableSaveRestore() const { return EnableSaveRestore; }
   MVT getXLenVT() const { return XLenVT; }
   unsigned getXLen() const { return XLen; }
   RISCVABI::ABI getTargetABI() const { return TargetABI; }

llvm/test/MC/RISCV/rvv/zvamo.s

+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+a,+experimental-zvamo %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+a,+experimental-zvamo %s \
+# RUN:        | llvm-objdump -d --mattr=+a,+experimental-zvamo - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+a,+experimental-zvamo %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+vamoswapei8.v v8, (a0), v4, v8
+# CHECK-INST: vamoswapei8.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x04,0x45,0x0e]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 04 45 0e <unknown>
+
+vamoswapei16.v v8, (a0), v4, v8
+# CHECK-INST: vamoswapei16.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x54,0x45,0x0e]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 54 45 0e <unknown>
+
+vamoswapei32.v v8, (a0), v4, v8
+# CHECK-INST: vamoswapei32.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x64,0x45,0x0e]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 64 45 0e <unknown>
+
+vamoswapei64.v v8, (a0), v4, v8
+# CHECK-INST: vamoswapei64.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x74,0x45,0x0e]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 74 45 0e <unknown>
+
+vamoswapei8.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamoswapei8.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x04,0x45,0x0c]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 04 45 0c <unknown>
+
+vamoswapei16.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamoswapei16.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x54,0x45,0x0c]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 54 45 0c <unknown>
+
+vamoswapei32.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamoswapei32.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x64,0x45,0x0c]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 64 45 0c <unknown>
+
+vamoswapei64.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamoswapei64.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x74,0x45,0x0c]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 74 45 0c <unknown>
+
+vamoaddei8.v v8, (a0), v4, v8
+# CHECK-INST: vamoaddei8.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x04,0x45,0x06]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 04 45 06 <unknown>
+
+vamoaddei16.v v8, (a0), v4, v8
+# CHECK-INST: vamoaddei16.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x54,0x45,0x06]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 54 45 06 <unknown>
+
+vamoaddei32.v v8, (a0), v4, v8
+# CHECK-INST: vamoaddei32.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x64,0x45,0x06]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 64 45 06 <unknown>
+
+vamoaddei64.v v8, (a0), v4, v8
+# CHECK-INST: vamoaddei64.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x74,0x45,0x06]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 74 45 06 <unknown>
+
+vamoaddei8.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamoaddei8.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x04,0x45,0x04]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 04 45 04 <unknown>
+
+vamoaddei16.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamoaddei16.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x54,0x45,0x04]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 54 45 04 <unknown>
+
+vamoaddei32.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamoaddei32.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x64,0x45,0x04]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 64 45 04 <unknown>
+
+vamoaddei64.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamoaddei64.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x74,0x45,0x04]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 74 45 04 <unknown>
+
+vamoxorei8.v v8, (a0), v4, v8
+# CHECK-INST: vamoxorei8.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x04,0x45,0x26]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 04 45 26 <unknown>
+
+vamoxorei16.v v8, (a0), v4, v8
+# CHECK-INST: vamoxorei16.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x54,0x45,0x26]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 54 45 26 <unknown>
+
+vamoxorei32.v v8, (a0), v4, v8
+# CHECK-INST: vamoxorei32.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x64,0x45,0x26]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 64 45 26 <unknown>
+
+vamoxorei64.v v8, (a0), v4, v8
+# CHECK-INST: vamoxorei64.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x74,0x45,0x26]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 74 45 26 <unknown>
+
+vamoxorei8.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamoxorei8.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x04,0x45,0x24]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 04 45 24 <unknown>
+
+vamoxorei16.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamoxorei16.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x54,0x45,0x24]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 54 45 24 <unknown>
+
+vamoxorei32.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamoxorei32.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x64,0x45,0x24]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 64 45 24 <unknown>
+
+vamoxorei64.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamoxorei64.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x74,0x45,0x24]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 74 45 24 <unknown>
+
+vamoandei8.v v8, (a0), v4, v8
+# CHECK-INST: vamoandei8.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x04,0x45,0x66]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 04 45 66 <unknown>
+
+vamoandei16.v v8, (a0), v4, v8
+# CHECK-INST: vamoandei16.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x54,0x45,0x66]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 54 45 66 <unknown>
+
+vamoandei32.v v8, (a0), v4, v8
+# CHECK-INST: vamoandei32.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x64,0x45,0x66]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 64 45 66 <unknown>
+
+vamoandei64.v v8, (a0), v4, v8
+# CHECK-INST: vamoandei64.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x74,0x45,0x66]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 74 45 66 <unknown>
+
+vamoandei8.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamoandei8.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x04,0x45,0x64]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 04 45 64 <unknown>
+
+vamoandei16.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamoandei16.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x54,0x45,0x64]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 54 45 64 <unknown>
+
+vamoandei32.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamoandei32.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x64,0x45,0x64]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 64 45 64 <unknown>
+
+vamoandei64.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamoandei64.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x74,0x45,0x64]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 74 45 64 <unknown>
+
+vamoorei8.v v8, (a0), v4, v8
+# CHECK-INST: vamoorei8.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x04,0x45,0x46]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 04 45 46 <unknown>
+
+vamoorei16.v v8, (a0), v4, v8
+# CHECK-INST: vamoorei16.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x54,0x45,0x46]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 54 45 46 <unknown>
+
+vamoorei32.v v8, (a0), v4, v8
+# CHECK-INST: vamoorei32.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x64,0x45,0x46]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 64 45 46 <unknown>
+
+vamoorei64.v v8, (a0), v4, v8
+# CHECK-INST: vamoorei64.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x74,0x45,0x46]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 74 45 46 <unknown>
+
+vamoorei8.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamoorei8.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x04,0x45,0x44]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 04 45 44 <unknown>
+
+vamoorei16.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamoorei16.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x54,0x45,0x44]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 54 45 44 <unknown>
+
+vamoorei32.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamoorei32.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x64,0x45,0x44]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 64 45 44 <unknown>
+
+vamoorei64.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamoorei64.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x74,0x45,0x44]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 74 45 44 <unknown>
+
+vamominei8.v v8, (a0), v4, v8
+# CHECK-INST: vamominei8.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x04,0x45,0x86]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 04 45 86 <unknown>
+
+vamominei16.v v8, (a0), v4, v8
+# CHECK-INST: vamominei16.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x54,0x45,0x86]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 54 45 86 <unknown>
+
+vamominei32.v v8, (a0), v4, v8
+# CHECK-INST: vamominei32.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x64,0x45,0x86]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 64 45 86 <unknown>
+
+vamominei64.v v8, (a0), v4, v8
+# CHECK-INST: vamominei64.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x74,0x45,0x86]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 74 45 86 <unknown>
+
+vamominei8.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamominei8.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x04,0x45,0x84]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 04 45 84 <unknown>
+
+vamominei16.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamominei16.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x54,0x45,0x84]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 54 45 84 <unknown>
+
+vamominei32.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamominei32.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x64,0x45,0x84]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 64 45 84 <unknown>
+
+vamominei64.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamominei64.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x74,0x45,0x84]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 74 45 84 <unknown>
+
+vamomaxei8.v v8, (a0), v4, v8
+# CHECK-INST: vamomaxei8.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x04,0x45,0xa6]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 04 45 a6 <unknown>
+
+vamomaxei16.v v8, (a0), v4, v8
+# CHECK-INST: vamomaxei16.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x54,0x45,0xa6]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 54 45 a6 <unknown>
+
+vamomaxei32.v v8, (a0), v4, v8
+# CHECK-INST: vamomaxei32.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x64,0x45,0xa6]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 64 45 a6 <unknown>
+
+vamomaxei64.v v8, (a0), v4, v8
+# CHECK-INST: vamomaxei64.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x74,0x45,0xa6]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 74 45 a6 <unknown>
+
+vamomaxei8.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamomaxei8.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x04,0x45,0xa4]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 04 45 a4 <unknown>
+
+vamomaxei16.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamomaxei16.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x54,0x45,0xa4]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 54 45 a4 <unknown>
+
+vamomaxei32.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamomaxei32.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x64,0x45,0xa4]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 64 45 a4 <unknown>
+
+vamomaxei64.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamomaxei64.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x74,0x45,0xa4]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 74 45 a4 <unknown>
+
+vamominuei8.v v8, (a0), v4, v8
+# CHECK-INST: vamominuei8.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x04,0x45,0xc6]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 04 45 c6 <unknown>
+
+vamominuei16.v v8, (a0), v4, v8
+# CHECK-INST: vamominuei16.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x54,0x45,0xc6]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 54 45 c6 <unknown>
+
+vamominuei32.v v8, (a0), v4, v8
+# CHECK-INST: vamominuei32.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x64,0x45,0xc6]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 64 45 c6 <unknown>
+
+vamominuei64.v v8, (a0), v4, v8
+# CHECK-INST: vamominuei64.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x74,0x45,0xc6]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 74 45 c6 <unknown>
+
+vamominuei8.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamominuei8.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x04,0x45,0xc4]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 04 45 c4 <unknown>
+
+vamominuei16.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamominuei16.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x54,0x45,0xc4]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 54 45 c4 <unknown>
+
+vamominuei32.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamominuei32.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x64,0x45,0xc4]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 64 45 c4 <unknown>
+
+vamominuei64.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamominuei64.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x74,0x45,0xc4]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 74 45 c4 <unknown>
+
+vamomaxuei8.v v8, (a0), v4, v8
+# CHECK-INST: vamomaxuei8.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x04,0x45,0xe6]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 04 45 e6 <unknown>
+
+vamomaxuei16.v v8, (a0), v4, v8
+# CHECK-INST: vamomaxuei16.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x54,0x45,0xe6]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 54 45 e6 <unknown>
+
+vamomaxuei32.v v8, (a0), v4, v8
+# CHECK-INST: vamomaxuei32.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x64,0x45,0xe6]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 64 45 e6 <unknown>
+
+vamomaxuei64.v v8, (a0), v4, v8
+# CHECK-INST: vamomaxuei64.v v8, (a0), v4, v8
+# CHECK-ENCODING: [0x2f,0x74,0x45,0xe6]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 74 45 e6 <unknown>
+
+vamomaxuei8.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamomaxuei8.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x04,0x45,0xe4]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 04 45 e4 <unknown>
+
+vamomaxuei16.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamomaxuei16.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x54,0x45,0xe4]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 54 45 e4 <unknown>
+
+vamomaxuei32.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamomaxuei32.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x64,0x45,0xe4]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 64 45 e4 <unknown>
+
+vamomaxuei64.v v8, (a0), v4, v8, v0.t
+# CHECK-INST: vamomaxuei64.v v8, (a0), v4, v8, v0.t
+# CHECK-ENCODING: [0x2f,0x74,0x45,0xe4]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 74 45 e4 <unknown>
+
+vamoswapei8.v x0, (a0), v4, v24
+# CHECK-INST: vamoswapei8.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x0c,0x45,0x0a]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 0c 45 0a <unknown>
+
+vamoswapei16.v x0, (a0), v4, v24
+# CHECK-INST: vamoswapei16.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x5c,0x45,0x0a]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 5c 45 0a <unknown>
+
+vamoswapei32.v x0, (a0), v4, v24
+# CHECK-INST: vamoswapei32.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x6c,0x45,0x0a]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 6c 45 0a <unknown>
+
+vamoswapei64.v x0, (a0), v4, v24
+# CHECK-INST: vamoswapei64.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x7c,0x45,0x0a]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 7c 45 0a <unknown>
+
+vamoswapei8.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamoswapei8.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x0c,0x45,0x08]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 0c 45 08 <unknown>
+
+vamoswapei16.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamoswapei16.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x5c,0x45,0x08]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 5c 45 08 <unknown>
+
+vamoswapei32.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamoswapei32.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x6c,0x45,0x08]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 6c 45 08 <unknown>
+
+vamoswapei64.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamoswapei64.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x7c,0x45,0x08]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 7c 45 08 <unknown>
+
+vamoaddei8.v x0, (a0), v4, v24
+# CHECK-INST: vamoaddei8.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x0c,0x45,0x02]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 0c 45 02 <unknown>
+
+vamoaddei16.v x0, (a0), v4, v24
+# CHECK-INST: vamoaddei16.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x5c,0x45,0x02]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 5c 45 02 <unknown>
+
+vamoaddei32.v x0, (a0), v4, v24
+# CHECK-INST: vamoaddei32.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x6c,0x45,0x02]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 6c 45 02 <unknown>
+
+vamoaddei64.v x0, (a0), v4, v24
+# CHECK-INST: vamoaddei64.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x7c,0x45,0x02]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 7c 45 02 <unknown>
+
+vamoaddei8.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamoaddei8.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x0c,0x45,0x00]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 0c 45 00 <unknown>
+
+vamoaddei16.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamoaddei16.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x5c,0x45,0x00]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 5c 45 00 <unknown>
+
+vamoaddei32.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamoaddei32.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x6c,0x45,0x00]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 6c 45 00 <unknown>
+
+vamoaddei64.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamoaddei64.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x7c,0x45,0x00]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 7c 45 00 <unknown>
+
+vamoxorei8.v x0, (a0), v4, v24
+# CHECK-INST: vamoxorei8.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x0c,0x45,0x22]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 0c 45 22 <unknown>
+
+vamoxorei16.v x0, (a0), v4, v24
+# CHECK-INST: vamoxorei16.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x5c,0x45,0x22]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 5c 45 22 <unknown>
+
+vamoxorei32.v x0, (a0), v4, v24
+# CHECK-INST: vamoxorei32.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x6c,0x45,0x22]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 6c 45 22 <unknown>
+
+vamoxorei64.v x0, (a0), v4, v24
+# CHECK-INST: vamoxorei64.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x7c,0x45,0x22]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 7c 45 22 <unknown>
+
+vamoxorei8.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamoxorei8.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x0c,0x45,0x20]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 0c 45 20 <unknown>
+
+vamoxorei16.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamoxorei16.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x5c,0x45,0x20]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 5c 45 20 <unknown>
+
+vamoxorei32.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamoxorei32.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x6c,0x45,0x20]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 6c 45 20 <unknown>
+
+vamoxorei64.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamoxorei64.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x7c,0x45,0x20]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 7c 45 20 <unknown>
+
+vamoandei8.v x0, (a0), v4, v24
+# CHECK-INST: vamoandei8.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x0c,0x45,0x62]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 0c 45 62 <unknown>
+
+vamoandei16.v x0, (a0), v4, v24
+# CHECK-INST: vamoandei16.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x5c,0x45,0x62]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 5c 45 62 <unknown>
+
+vamoandei32.v x0, (a0), v4, v24
+# CHECK-INST: vamoandei32.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x6c,0x45,0x62]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 6c 45 62 <unknown>
+
+vamoandei64.v x0, (a0), v4, v24
+# CHECK-INST: vamoandei64.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x7c,0x45,0x62]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 7c 45 62 <unknown>
+
+vamoandei8.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamoandei8.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x0c,0x45,0x60]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 0c 45 60 <unknown>
+
+vamoandei16.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamoandei16.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x5c,0x45,0x60]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 5c 45 60 <unknown>
+
+vamoandei32.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamoandei32.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x6c,0x45,0x60]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 6c 45 60 <unknown>
+
+vamoandei64.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamoandei64.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x7c,0x45,0x60]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 7c 45 60 <unknown>
+
+vamoorei8.v x0, (a0), v4, v24
+# CHECK-INST: vamoorei8.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x0c,0x45,0x42]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 0c 45 42 <unknown>
+
+vamoorei16.v x0, (a0), v4, v24
+# CHECK-INST: vamoorei16.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x5c,0x45,0x42]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 5c 45 42 <unknown>
+
+vamoorei32.v x0, (a0), v4, v24
+# CHECK-INST: vamoorei32.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x6c,0x45,0x42]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 6c 45 42 <unknown>
+
+vamoorei64.v x0, (a0), v4, v24
+# CHECK-INST: vamoorei64.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x7c,0x45,0x42]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 7c 45 42 <unknown>
+
+vamoorei8.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamoorei8.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x0c,0x45,0x40]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 0c 45 40 <unknown>
+
+vamoorei16.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamoorei16.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x5c,0x45,0x40]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 5c 45 40 <unknown>
+
+vamoorei32.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamoorei32.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x6c,0x45,0x40]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 6c 45 40 <unknown>
+
+vamoorei64.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamoorei64.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x7c,0x45,0x40]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 7c 45 40 <unknown>
+
+vamominei8.v x0, (a0), v4, v24
+# CHECK-INST: vamominei8.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x0c,0x45,0x82]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 0c 45 82 <unknown>
+
+vamominei16.v x0, (a0), v4, v24
+# CHECK-INST: vamominei16.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x5c,0x45,0x82]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 5c 45 82 <unknown>
+
+vamominei32.v x0, (a0), v4, v24
+# CHECK-INST: vamominei32.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x6c,0x45,0x82]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 6c 45 82 <unknown>
+
+vamominei64.v x0, (a0), v4, v24
+# CHECK-INST: vamominei64.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x7c,0x45,0x82]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 7c 45 82 <unknown>
+
+vamominei8.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamominei8.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x0c,0x45,0x80]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 0c 45 80 <unknown>
+
+vamominei16.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamominei16.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x5c,0x45,0x80]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 5c 45 80 <unknown>
+
+vamominei32.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamominei32.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x6c,0x45,0x80]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 6c 45 80 <unknown>
+
+vamominei64.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamominei64.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x7c,0x45,0x80]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 7c 45 80 <unknown>
+
+vamomaxei8.v x0, (a0), v4, v24
+# CHECK-INST: vamomaxei8.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x0c,0x45,0xa2]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 0c 45 a2 <unknown>
+
+vamomaxei16.v x0, (a0), v4, v24
+# CHECK-INST: vamomaxei16.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x5c,0x45,0xa2]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 5c 45 a2 <unknown>
+
+vamomaxei32.v x0, (a0), v4, v24
+# CHECK-INST: vamomaxei32.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x6c,0x45,0xa2]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 6c 45 a2 <unknown>
+
+vamomaxei64.v x0, (a0), v4, v24
+# CHECK-INST: vamomaxei64.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x7c,0x45,0xa2]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 7c 45 a2 <unknown>
+
+vamomaxei8.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamomaxei8.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x0c,0x45,0xa0]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 0c 45 a0 <unknown>
+
+vamomaxei16.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamomaxei16.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x5c,0x45,0xa0]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 5c 45 a0 <unknown>
+
+vamomaxei32.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamomaxei32.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x6c,0x45,0xa0]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 6c 45 a0 <unknown>
+
+vamomaxei64.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamomaxei64.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x7c,0x45,0xa0]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 7c 45 a0 <unknown>
+
+vamominuei8.v x0, (a0), v4, v24
+# CHECK-INST: vamominuei8.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x0c,0x45,0xc2]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 0c 45 c2 <unknown>
+
+vamominuei16.v x0, (a0), v4, v24
+# CHECK-INST: vamominuei16.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x5c,0x45,0xc2]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 5c 45 c2 <unknown>
+
+vamominuei32.v x0, (a0), v4, v24
+# CHECK-INST: vamominuei32.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x6c,0x45,0xc2]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 6c 45 c2 <unknown>
+
+vamominuei64.v x0, (a0), v4, v24
+# CHECK-INST: vamominuei64.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x7c,0x45,0xc2]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 7c 45 c2 <unknown>
+
+vamominuei8.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamominuei8.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x0c,0x45,0xc0]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 0c 45 c0 <unknown>
+
+vamominuei16.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamominuei16.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x5c,0x45,0xc0]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 5c 45 c0 <unknown>
+
+vamominuei32.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamominuei32.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x6c,0x45,0xc0]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 6c 45 c0 <unknown>
+
+vamominuei64.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamominuei64.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x7c,0x45,0xc0]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 7c 45 c0 <unknown>
+
+vamomaxuei8.v x0, (a0), v4, v24
+# CHECK-INST: vamomaxuei8.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x0c,0x45,0xe2]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 0c 45 e2 <unknown>
+
+vamomaxuei16.v x0, (a0), v4, v24
+# CHECK-INST: vamomaxuei16.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x5c,0x45,0xe2]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 5c 45 e2 <unknown>
+
+vamomaxuei32.v x0, (a0), v4, v24
+# CHECK-INST: vamomaxuei32.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x6c,0x45,0xe2]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 6c 45 e2 <unknown>
+
+vamomaxuei64.v x0, (a0), v4, v24
+# CHECK-INST: vamomaxuei64.v x0, (a0), v4, v24
+# CHECK-ENCODING: [0x2f,0x7c,0x45,0xe2]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 7c 45 e2 <unknown>
+
+vamomaxuei8.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamomaxuei8.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x0c,0x45,0xe0]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 0c 45 e0 <unknown>
+
+vamomaxuei16.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamomaxuei16.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x5c,0x45,0xe0]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 5c 45 e0 <unknown>
+
+vamomaxuei32.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamomaxuei32.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x6c,0x45,0xe0]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 6c 45 e0 <unknown>
+
+vamomaxuei64.v x0, (a0), v4, v24, v0.t
+# CHECK-INST: vamomaxuei64.v x0, (a0), v4, v24, v0.t
+# CHECK-ENCODING: [0x2f,0x7c,0x45,0xe0]
+# CHECK-ERROR: instruction requires the following: 'A' (Atomic Instructions), 'Zvamo'(Vector AMO Operations)
+# CHECK-UNKNOWN: 2f 7c 45 e0 <unknown>
 No newline at end of file