[RISCV] add the assemble and disassemble support of Zvlsseg instructions

[StephenFan]

Summary

This implements the assemble and disassemble support of RISCV Vector extension Zvlsseg instructions, base on the 0.9 spec version.

[HsiangKai]

D80802 is landed. Please rebase on master.

Please merge D83775 and this revision into one revision.

[StephenFan]

In D84416#2192037, @HsiangKai wrote:

D80802 is landed. Please rebase on master.

Please merge D83775 and this revision into one revision.

I have rebased to the latest master branch

[HsiangKai]

llvm/lib/Target/RISCV/RISCV.td

152

def FeatureStdExtZvlsseg
    : SubtargetFeature<"experimental-zvlsseg", "HasStdExtZvlsseg", "true",
                       "'Zvlsseg' (Vector segment load/store instructions)",
                       [FeatureStdExtV]>;

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

131

RVInstVLU<nf, width.Value{3}, MOPLDUnitStride, lumop, width.Value{2-0}

137

RVInstVLS<nf, width.Value{3}, MOPLDStrided, width.Value{2-0}

145

RVInstVLX<nf, width.Value{3}, MOPLDIndexed, width.Value{2-0}

181

Remove sumop.

183

RVInstVSU<nf, width.Value{3}, MOPSTUnitStride, SUMOPUnitStride, width.Value{2-0},

189

RVInstVSS<nf, width.Value{3}, MOPSTStrided, width.Value{2-0}, (outs),

194

Remove mop

195

RVInstVSX<nf, width.Value{3}, MOPSTIndexedOrder, width.Value{2-0}, (outs),

950

HasStdExtZvlsseg is enough.

970

Remove SUMOPUnitStride.

1008

Remove MOPSTIndexedOrder.

llvm/test/MC/RISCV/rvv/zvlsseg.s

2

+experimental-zvlsseg is enough.

15

CHECK-ERROR: instruction requires the following: 'Zvlsseg' (Vector segment load/store instructions)

[StephenFan]

Remove sumop, Remove MOPSTIndexedOrder. zvlsseg -> FeatureStdExtV

[HsiangKai]

LGTM.

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

enum class VSEW {
     SEW_32,
     SEW_64,
     SEW_128,
     SEW_256,
     SEW_512,
     SEW_1024,
   };
 
-  enum class VLMUL { LMUL_1 = 0, LMUL_2, LMUL_4, LMUL_8 };
+  enum class VLMUL {
+    LMUL_1 = 0,
+    LMUL_2,
+    LMUL_4,
+    LMUL_8,
+    LMUL_F8 = 5,
+    LMUL_F4,
+    LMUL_F2
+  };
 
   struct VTypeOp {
     VSEW Sew;
     VLMUL Lmul;
+    bool TailAgnostic;
+    bool MaskedoffAgnostic;
     unsigned Encoding;
   };
 
   SMLoc StartLoc, EndLoc;
   union {
     StringRef Tok;
     RegOp Reg;
     ImmOp Imm;
public:
 
   StringRef getToken() const {
     assert(Kind == KindTy::Token && "Invalid type access!");
     return Tok;
   }
 
   static StringRef getSEWStr(VSEW Sew) {
     switch (Sew) {
+    default:
+      llvm_unreachable("Unknown SEW.");
     case VSEW::SEW_8:
       return "e8";
     case VSEW::SEW_16:
       return "e16";
     case VSEW::SEW_32:
       return "e32";
     case VSEW::SEW_64:
       return "e64";
     case VSEW::SEW_128:
       return "e128";
     case VSEW::SEW_256:
       return "e256";
     case VSEW::SEW_512:
       return "e512";
     case VSEW::SEW_1024:
       return "e1024";
     }
-    return "";
   }
 
   static StringRef getLMULStr(VLMUL Lmul) {
     switch (Lmul) {
+    default:
+      llvm_unreachable("Unknown LMUL.");
     case VLMUL::LMUL_1:
       return "m1";
     case VLMUL::LMUL_2:
       return "m2";
     case VLMUL::LMUL_4:
       return "m4";
     case VLMUL::LMUL_8:
       return "m8";
+    case VLMUL::LMUL_F2:
+      return "mf2";
+    case VLMUL::LMUL_F4:
+      return "mf4";
+    case VLMUL::LMUL_F8:
+      return "mf8";
     }
-    return "";
   }
 
   StringRef getVType(SmallString<32> &Buf) const {
     assert(Kind == KindTy::VType && "Invalid access!");
     Buf.append(getSEWStr(VType.Sew));
     Buf.append(",");
     Buf.append(getLMULStr(VType.Lmul));
 
createSysReg(StringRef Str, SMLoc S, unsigned Encoding, bool IsRV64) {
     Op->SysReg.Data = Str.data();
     Op->SysReg.Length = Str.size();
     Op->SysReg.Encoding = Encoding;
     Op->StartLoc = S;
     Op->IsRV64 = IsRV64;
     return Op;
   }
 
-  static std::unique_ptr<RISCVOperand> createVType(APInt Sew, APInt Lmul,
-                                                   SMLoc S, bool IsRV64) {
+  static std::unique_ptr<RISCVOperand>
+  createVType(APInt Sew, APInt Lmul, bool Fractional, bool TailAgnostic,
+              bool MaskedoffAgnostic, SMLoc S, bool IsRV64) {
     auto Op = std::make_unique<RISCVOperand>(KindTy::VType);
     Sew.ashrInPlace(3);
     unsigned SewLog2 = Sew.logBase2();
     unsigned LmulLog2 = Lmul.logBase2();
     Op->VType.Sew = static_cast<VSEW>(SewLog2);
+    if (Fractional) {
+      unsigned Flmul = 8 - LmulLog2;
+      Op->VType.Lmul = static_cast<VLMUL>(Flmul);
+      Op->VType.Encoding =
+          ((Flmul & 0x4) << 3) | ((SewLog2 & 0x7) << 2) | (Flmul & 0x3);
+    } else {
       Op->VType.Lmul = static_cast<VLMUL>(LmulLog2);
       Op->VType.Encoding = (SewLog2 << 2) | LmulLog2;
+    }
+    if (TailAgnostic) {
+      Op->VType.Encoding |= 0x40;
+    }
+    if (MaskedoffAgnostic) {
+      Op->VType.Encoding |= 0x80;
+    }
+    Op->VType.TailAgnostic = TailAgnostic;
+    Op->VType.MaskedoffAgnostic = MaskedoffAgnostic;
     Op->StartLoc = S;
     Op->IsRV64 = IsRV64;
     return Op;
   }
 
   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
     assert(Expr && "Expr shouldn't be null!");
     int64_t Imm = 0;
case Match_InvalidCallSymbol: {
     return Error(ErrorLoc, "operand must be a bare symbol name");
   }
   case Match_InvalidTPRelAddSymbol: {
     SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
     return Error(ErrorLoc, "operand must be a symbol with %tprel_add modifier");
   }
   case Match_InvalidVTypeI: {
     SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
-    return Error(ErrorLoc,
-                 "operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]");
+    return Error(
+        ErrorLoc,
+        "operand must be "
+        "e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]");
   }
   case Match_InvalidVMaskRegister: {
     SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
     return Error(ErrorLoc, "operand must be v0.t");
   }
   case Match_InvalidSImm5Plus1: {
     return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 4) + 1,
                                       (1 << 4),
OperandMatchResultTy RISCVAsmParser::parseJALOffset(OperandVector &Operands) {
   return parseImmediate(Operands);
 }
 
 OperandMatchResultTy RISCVAsmParser::parseVTypeI(OperandVector &Operands) {
   SMLoc S = getLoc();
   if (getLexer().getKind() != AsmToken::Identifier)
     return MatchOperand_NoMatch;
 
-  // Parse "e8,m1"
+  // Parse "e8,m1,t[a|u],m[a|u]"
   StringRef Name = getLexer().getTok().getIdentifier();
   if (!Name.consume_front("e"))
     return MatchOperand_NoMatch;
   APInt Sew(16, Name, 10);
   if (Sew != 8 && Sew != 16 && Sew != 32 && Sew != 64 && Sew != 128 &&
       Sew != 256 && Sew != 512 && Sew != 1024)
     return MatchOperand_NoMatch;
   getLexer().Lex();
 
-  if (getLexer().getKind() == AsmToken::EndOfStatement) {
-    Operands.push_back(
-        RISCVOperand::createVType(Sew, APInt(16, 1), S, isRV64()));
-
-    return MatchOperand_Success;
-  }
-
   if (!getLexer().is(AsmToken::Comma))
     return MatchOperand_NoMatch;
   getLexer().Lex();
 
   Name = getLexer().getTok().getIdentifier();
   if (!Name.consume_front("m"))
     return MatchOperand_NoMatch;
+  // "m" or "mf"
+  bool Fractional = false;
+  if (Name.consume_front("f")) {
+    Fractional = true;
+  }
   APInt Lmul(16, Name, 10);
   if (Lmul != 1 && Lmul != 2 && Lmul != 4 && Lmul != 8)
     return MatchOperand_NoMatch;
   getLexer().Lex();
 
+  if (!getLexer().is(AsmToken::Comma))
+    return MatchOperand_NoMatch;
+  getLexer().Lex();
+
+  Name = getLexer().getTok().getIdentifier();
+  // ta or tu
+  bool TailAgnostic;
+  if (Name.consume_front("ta"))
+    TailAgnostic = true;
+  else if (Name.consume_front("tu"))
+    TailAgnostic = false;
+  else
+    return MatchOperand_NoMatch;
+  getLexer().Lex();
+
+  if (!getLexer().is(AsmToken::Comma))
+    return MatchOperand_NoMatch;
+  getLexer().Lex();
+
+  Name = getLexer().getTok().getIdentifier();
+  // ma or mu
+  bool MaskedoffAgnostic;
+  if (Name.consume_front("ma"))
+    MaskedoffAgnostic = true;
+  else if (Name.consume_front("mu"))
+    MaskedoffAgnostic = false;
+  else
+    return MatchOperand_NoMatch;
+  getLexer().Lex();
+
   if (getLexer().getKind() != AsmToken::EndOfStatement)
     return MatchOperand_NoMatch;
 
-  Operands.push_back(RISCVOperand::createVType(Sew, Lmul, S, isRV64()));
+  Operands.push_back(RISCVOperand::createVType(
+      Sew, Lmul, Fractional, TailAgnostic, MaskedoffAgnostic, S, isRV64()));
 
   return MatchOperand_Success;
 }
 
 OperandMatchResultTy RISCVAsmParser::parseMaskReg(OperandVector &Operands) {
   switch (getLexer().getKind()) {
   default:
     return MatchOperand_NoMatch;
bool RISCVAsmParser::validateInstruction(MCInst &Inst,
                                          OperandVector &Operands) {
   const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
   unsigned TargetFlags =
       (MCID.TSFlags >> RISCV::ConstraintOffset) & RISCV::ConstraintMask;
   if (TargetFlags == RISCV::NoConstraint)
     return false;
 
   unsigned DestReg = Inst.getOperand(0).getReg();
+  unsigned CheckReg;
   // Operands[1] will be the first operand, DestReg.
   SMLoc Loc = Operands[1]->getStartLoc();
-  if ((TargetFlags == RISCV::WidenV) || (TargetFlags == RISCV::WidenW) ||
-      (TargetFlags == RISCV::SlideUp) || (TargetFlags == RISCV::Vrgather) ||
-      (TargetFlags == RISCV::Vcompress)) {
-    if (TargetFlags != RISCV::WidenW) {
-      unsigned Src2Reg = Inst.getOperand(1).getReg();
-      if (DestReg == Src2Reg)
-        return Error(Loc, "The destination vector register group cannot overlap"
-                          " the source vector register group.");
-      if (TargetFlags == RISCV::WidenV) {
-        // Assume DestReg LMUL is 2 at least for widening/narrowing operations.
-        if (DestReg + 1 == Src2Reg)
-          return Error(Loc,
-                       "The destination vector register group cannot overlap"
-                       " the source vector register group.");
-      }
-    }
-    if (Inst.getOperand(2).isReg()) {
-      unsigned Src1Reg = Inst.getOperand(2).getReg();
-      if (DestReg == Src1Reg)
-        return Error(Loc, "The destination vector register group cannot overlap"
-                          " the source vector register group.");
-      if (TargetFlags == RISCV::WidenV || TargetFlags == RISCV::WidenW) {
-        // Assume DestReg LMUL is 2 at least for widening/narrowing operations.
-        if (DestReg + 1 == Src1Reg)
-          return Error(Loc,
-                       "The destination vector register group cannot overlap"
-                       " the source vector register group.");
-      }
-    }
-    if (Inst.getNumOperands() == 4) {
-      unsigned MaskReg = Inst.getOperand(3).getReg();
-
-      if (DestReg == MaskReg)
-        return Error(Loc, "The destination vector register group cannot overlap"
-                          " the mask register.");
-    }
-  } else if (TargetFlags == RISCV::Narrow) {
-    unsigned Src2Reg = Inst.getOperand(1).getReg();
-    if (DestReg == Src2Reg)
-      return Error(Loc, "The destination vector register group cannot overlap"
-                        " the source vector register group.");
-    // Assume Src2Reg LMUL is 2 at least for widening/narrowing operations.
-    if (DestReg == Src2Reg + 1)
-      return Error(Loc, "The destination vector register group cannot overlap"
-                        " the source vector register group.");
-  } else if (TargetFlags == RISCV::WidenCvt || TargetFlags == RISCV::Iota) {
-    unsigned Src2Reg = Inst.getOperand(1).getReg();
-    if (DestReg == Src2Reg)
-      return Error(Loc, "The destination vector register group cannot overlap"
-                        " the source vector register group.");
-    if (TargetFlags == RISCV::WidenCvt) {
-      // Assume DestReg LMUL is 2 at least for widening/narrowing operations.
-      if (DestReg + 1 == Src2Reg)
-        return Error(Loc, "The destination vector register group cannot overlap"
-                          " the source vector register group.");
-    }
-    if (Inst.getNumOperands() == 3) {
-      unsigned MaskReg = Inst.getOperand(2).getReg();
-
-      if (DestReg == MaskReg)
-        return Error(Loc, "The destination vector register group cannot overlap"
-                          " the mask register.");
-    }
-  }
+  if (TargetFlags & RISCV::VS2Constraint) {
+    CheckReg = Inst.getOperand(1).getReg();
+    if (DestReg == CheckReg)
+  if ((TargetFlags & RISCV::VS1Constraint) && (Inst.getOperand(2).isReg())) {
+    CheckReg = Inst.getOperand(2).getReg();
+    if (DestReg == CheckReg)
+  if ((TargetFlags & RISCV::VMConstraint) && (DestReg == RISCV::V0)) {
+    // vadc, vsbc are special cases. These instructions have no mask register.
+    // The destination register could not be V0.
+    unsigned Opcode = Inst.getOpcode();
+    if (Opcode == RISCV::VADC_VVM || Opcode == RISCV::VADC_VXM ||
+        Opcode == RISCV::VADC_VIM || Opcode == RISCV::VSBC_VVM ||
+        Opcode == RISCV::VSBC_VXM)
+      return Error(Loc, "The destination vector register group cannot be V0.");
+
+    // Regardless masked or unmasked version, the number of operands is the
+    // same. For example, "viota.m v0, v2" is "viota.m v0, v2, NoRegister"
+    // actually. We need to check the last operand to ensure whether it is
+    // masked or not.
+    if ((TargetFlags & RISCV::OneInput) && (Inst.getNumOperands() == 3))
+      CheckReg = Inst.getOperand(2).getReg();
+    else if (Inst.getNumOperands() == 4)
+      CheckReg = Inst.getOperand(3).getReg();
+    if (DestReg == CheckReg)
   return false;
 }
 
 bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
                                         OperandVector &Operands,
                                         MCStreamer &Out) {
   Inst.setLoc(IDLoc);
 

llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp

void RISCVInstPrinter::printAtomicMemOp(const MCInst *MI, unsigned OpNo,
   return;
 }
 
 void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
                                    const MCSubtargetInfo &STI, raw_ostream &O) {
   unsigned Imm = MI->getOperand(OpNo).getImm();
   unsigned Sew = (Imm >> 2) & 0x7;
   unsigned Lmul = Imm & 0x3;
+  bool Fractional = (Imm >> 5) & 0x1;
 
-  Lmul = 0x1 << Lmul;
   Sew = 0x1 << (Sew + 3);
-  O << "e" << Sew << ",m" << Lmul;
+  O << "e" << Sew;
+  if (Fractional) {
+    Lmul = 4 - Lmul;
+    Lmul = 0x1 << Lmul;
+    O << ",mf" << Lmul;
+  } else {
+    Lmul = 0x1 << Lmul;
+    O << ",m" << Lmul;
+  }
+  bool TailAgnostic = Imm & 0x40;
+  bool MaskedoffAgnostic = Imm & 0x80;
+  if (TailAgnostic)
+    O << ",ta";
+  else
+    O << ",tu";
+  if (MaskedoffAgnostic)
+    O << ",ma";
+  else
+    O << ",mu";
 }
 
 void RISCVInstPrinter::printVMaskReg(const MCInst *MI, unsigned OpNo,
                                      const MCSubtargetInfo &STI,
                                      raw_ostream &O) {
   const MCOperand &MO = MI->getOperand(OpNo);
 
   assert(MO.isReg() && "printVMaskReg can only print register operands");

llvm/lib/Target/RISCV/RISCV.td

 
 def FeatureNoRVCHints
     : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
                        "Disable RVC Hint Instructions.">;
 def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
                   AssemblerPredicate<(all_of(not FeatureNoRVCHints)),
                                      "RVC Hint Instructions">;
 
+def FeatureStdExtZvlsseg
+    : SubtargetFeature<"experimental-zvlsseg", "HasStdExtZvlsseg", "true",
+                       "'Zvlsseg' (Vector segment load/store instructions)">;
+def HasStdExtZvlsseg : Predicate<"Subtarget->hasStdExtZvlsseg()">,
+                        AssemblerPredicate<(all_of FeatureStdExtZvlsseg),
+                        "'Zvlsseg' (Vector segment load/store instructions)">;
+                        
 def FeatureStdExtV
     : SubtargetFeature<"experimental-v", "HasStdExtV", "true",
                        "'V' (Vector Instructions)",
                        [FeatureStdExtF]>;
 def HasStdExtV : Predicate<"Subtarget->hasStdExtV()">,
                            AssemblerPredicate<(all_of FeatureStdExtV),
                            "'V' (Vector Instructions)">;
 

llvm/lib/Target/RISCV/RISCVInstrFormats.td

 def InstFormatCA     : InstFormat<14>;
 def InstFormatCB     : InstFormat<15>;
 def InstFormatCJ     : InstFormat<16>;
 def InstFormatOther  : InstFormat<17>;
 
 class RISCVVConstraint<bits<4> val> {
   bits<4> Value = val;
 }
-def NoConstraint : RISCVVConstraint<0>;
-def WidenV       : RISCVVConstraint<1>;
-def WidenW       : RISCVVConstraint<2>;
-def WidenCvt     : RISCVVConstraint<3>;
-def Narrow       : RISCVVConstraint<4>;
-def Iota         : RISCVVConstraint<5>;
-def SlideUp      : RISCVVConstraint<6>;
-def Vrgather     : RISCVVConstraint<7>;
-def Vcompress    : RISCVVConstraint<8>;
+def NoConstraint  : RISCVVConstraint<0b0000>;
+def VS2Constraint : RISCVVConstraint<0b0001>;
+def VS1Constraint : RISCVVConstraint<0b0010>;
+def VMConstraint  : RISCVVConstraint<0b0100>;
+def OneInput      : RISCVVConstraint<0b1000>;
+
+def WidenV       : RISCVVConstraint<!or(VS2Constraint.Value,
+                                        VS1Constraint.Value,
+                                        VMConstraint.Value)>;
+def WidenW       : RISCVVConstraint<!or(VS1Constraint.Value,
+                                        VMConstraint.Value)>;
+def WidenCvt     : RISCVVConstraint<!or(VS2Constraint.Value,
+                                        VMConstraint.Value,
+                                        OneInput.Value)>;
+def Narrow       : RISCVVConstraint<!or(VS2Constraint.Value,
+                                        VMConstraint.Value)>;
+def NarrowCvt    : RISCVVConstraint<!or(VS2Constraint.Value,
+                                        VMConstraint.Value,
+                                        OneInput.Value)>;
+def Vmadc        : RISCVVConstraint<!or(VS2Constraint.Value,
+                                        VS1Constraint.Value)>;
+def Iota         : RISCVVConstraint<!or(VS2Constraint.Value,
+                                        VMConstraint.Value,
+                                        OneInput.Value)>;
+def SlideUp      : RISCVVConstraint<!or(VS2Constraint.Value,
+                                        VMConstraint.Value)>;
+def Vrgather     : RISCVVConstraint<!or(VS2Constraint.Value,
+                                        VS1Constraint.Value,
+                                        VMConstraint.Value)>;
+def Vcompress    : RISCVVConstraint<!or(VS2Constraint.Value,
+                                        VS1Constraint.Value)>;
 
 // The following opcode names match those given in Table 19.1 in the
 // RISC-V User-level ISA specification ("RISC-V base opcode map").
 class RISCVOpcode<bits<7> val> {
   bits<7> Value = val;
 }
 def OPC_LOAD      : RISCVOpcode<0b0000011>;
 def OPC_LOAD_FP   : RISCVOpcode<0b0000111>;

llvm/lib/Target/RISCV/RISCVInstrFormatsV.td

 def OPIVV : RISCVVFormat<0b000>;
 def OPFVV : RISCVVFormat<0b001>;
 def OPMVV : RISCVVFormat<0b010>;
 def OPIVI : RISCVVFormat<0b011>;
 def OPIVX : RISCVVFormat<0b100>;
 def OPFVF : RISCVVFormat<0b101>;
 def OPMVX : RISCVVFormat<0b110>;
 
-class RISCVMOP<bits<3> val> {
-  bits<3> Value = val;
+class RISCVMOP<bits<2> val> {
+  bits<2> Value = val;
 }
-def MOPLDUnitStrideU : RISCVMOP<0b000>;
-def MOPLDStridedU    : RISCVMOP<0b010>;
-def MOPLDIndexedU    : RISCVMOP<0b011>;
-def MOPLDUnitStrideS : RISCVMOP<0b100>;
-def MOPLDStridedS    : RISCVMOP<0b110>;
-def MOPLDIndexedS    : RISCVMOP<0b111>;
-
-def MOPSTUnitStride  : RISCVMOP<0b000>;
-def MOPSTStrided     : RISCVMOP<0b010>;
-def MOPSTIndexedOrder: RISCVMOP<0b011>;
-def MOPSTIndexedUnOrd: RISCVMOP<0b111>;
+def MOPLDUnitStride : RISCVMOP<0b00>;
+def MOPLDStrided    : RISCVMOP<0b10>;
+def MOPLDIndexed    : RISCVMOP<0b11>;
+
+def MOPSTUnitStride   : RISCVMOP<0b00>;
+def MOPSTIndexedUnord : RISCVMOP<0b01>;
+def MOPSTStrided      : RISCVMOP<0b10>;
+def MOPSTIndexedOrder : RISCVMOP<0b11>;
 
 class RISCVLSUMOP<bits<5> val> {
   bits<5> Value = val;
 }
 def LUMOPUnitStride  : RISCVLSUMOP<0b00000>;
 def LUMOPUnitStrideWholeReg : RISCVLSUMOP<0b01000>;
 def LUMOPUnitStrideFF: RISCVLSUMOP<0b10000>;
 def SUMOPUnitStride  : RISCVLSUMOP<0b00000>;
 def SUMOPUnitStrideWholeReg : RISCVLSUMOP<0b01000>;
 
-class RISCVWidth<bits<3> val> {
-  bits<3> Value = val;
+class RISCVWidth<bits<4> val> {
+  bits<4> Value = val;
 }
-def LSWidthVByte : RISCVWidth<0b000>;
-def LSWidthVHalf : RISCVWidth<0b101>;
-def LSWidthVWord : RISCVWidth<0b110>;
-def LSWidthVSEW  : RISCVWidth<0b111>;
+def LSWidth8     : RISCVWidth<0b0000>;
+def LSWidth16    : RISCVWidth<0b0101>;
+def LSWidth32    : RISCVWidth<0b0110>;
+def LSWidth64    : RISCVWidth<0b0111>;
+def LSWidth128   : RISCVWidth<0b1000>;
+def LSWidth256   : RISCVWidth<0b1101>;
+def LSWidth512   : RISCVWidth<0b1110>;
+def LSWidth1024  : RISCVWidth<0b1111>;
 
 class RVInstSetVLi<dag outs, dag ins, string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
   bits<5> rs1;
   bits<5> rd;
   bits<11> vtypei;
 
   let Inst{31} = 0;
class RVInstVV<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
   let Inst{25} = vm;
   let Inst{24-20} = vs2;
   let Inst{19-15} = vs1;
   let Inst{14-12} = opv.Value;
   let Inst{11-7} = vd;
   let Opcode = OPC_OP_V.Value;
 
   let Uses = [VTYPE, VL];
+  let RVVConstraint = VMConstraint;
 }
 
 class RVInstVX<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
                 string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> vs2;
   bits<5> rs1;
   bits<5> vd;
   bit vm;
 
   let Inst{31-26} = funct6;
   let Inst{25} = vm;
   let Inst{24-20} = vs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = opv.Value;
   let Inst{11-7} = vd;
   let Opcode = OPC_OP_V.Value;
 
   let Uses = [VTYPE, VL];
+  let RVVConstraint = VMConstraint;
 }
 
 class RVInstV2<bits<6> funct6, bits<5> vs2, RISCVVFormat opv, dag outs, dag ins,
                 string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> rs1;
   bits<5> vd;
   bit vm;
 
   let Inst{31-26} = funct6;
   let Inst{25} = vm;
   let Inst{24-20} = vs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = opv.Value;
   let Inst{11-7} = vd;
   let Opcode = OPC_OP_V.Value;
 
   let Uses = [VTYPE, VL];
+  let RVVConstraint = VMConstraint;
 }
 
 class RVInstIVI<bits<6> funct6, dag outs, dag ins, string opcodestr,
                 string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> vs2;
   bits<5> imm;
   bits<5> vd;
   bit vm;
 
   let Inst{31-26} = funct6;
   let Inst{25} = vm;
   let Inst{24-20} = vs2;
   let Inst{19-15} = imm;
   let Inst{14-12} = 0b011;
   let Inst{11-7} = vd;
   let Opcode = OPC_OP_V.Value;
 
   let Uses = [VTYPE, VL];
+  let RVVConstraint = VMConstraint;
 }
 
 class RVInstV<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, dag outs,
               dag ins, string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> vs2;
   bits<5> vd;
   bit vm;
 
   let Inst{31-26} = funct6;
   let Inst{25} = vm;
   let Inst{24-20} = vs2;
   let Inst{19-15} = vs1;
   let Inst{14-12} = opv.Value;
   let Inst{11-7} = vd;
   let Opcode = OPC_OP_V.Value;
 
   let Uses = [VTYPE, VL];
+  let RVVConstraint = VMConstraint;
 }
 
-class RVInstVLU<bits<3> nf, RISCVMOP mop, RISCVLSUMOP lumop,
-                RISCVWidth width, dag outs, dag ins, string opcodestr,
+class RVInstVLU<bits<3> nf, bit mew, RISCVLSUMOP lumop,
+                bits<3> width, dag outs, dag ins, string opcodestr,
                 string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> rs1;
   bits<5> vd;
   bit vm;
 
   let Inst{31-29} = nf;
-  let Inst{28-26} = mop.Value;
+  let Inst{28} = mew;
+  let Inst{27-26} = MOPLDUnitStride.Value;
   let Inst{25} = vm;
   let Inst{24-20} = lumop.Value;
   let Inst{19-15} = rs1;
-  let Inst{14-12} = width.Value;
+  let Inst{14-12} = width;
   let Inst{11-7} = vd;
   let Opcode = OPC_LOAD_FP.Value;
 
   let Uses = [VTYPE, VL];
+  let RVVConstraint = VMConstraint;
 }
 
-class RVInstVLS<bits<3> nf, RISCVMOP mop, RISCVWidth width,
+class RVInstVLS<bits<3> nf, bit mew, bits<3> width,
                 dag outs, dag ins, string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> rs2;
   bits<5> rs1;
   bits<5> vd;
   bit vm;
 
   let Inst{31-29} = nf;
-  let Inst{28-26} = mop.Value;
+  let Inst{28} = mew;
+  let Inst{27-26} = MOPLDStrided.Value;
   let Inst{25} = vm;
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
-  let Inst{14-12} = width.Value;
+  let Inst{14-12} = width;
   let Inst{11-7} = vd;
   let Opcode = OPC_LOAD_FP.Value;
 
   let Uses = [VTYPE, VL];
+  let RVVConstraint = VMConstraint;
 }
 
-class RVInstVLX<bits<3> nf, RISCVMOP mop, RISCVWidth width,
+class RVInstVLX<bits<3> nf, bit mew, bits<3> width,
                 dag outs, dag ins, string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> vs2;
   bits<5> rs1;
   bits<5> vd;
   bit vm;
 
   let Inst{31-29} = nf;
-  let Inst{28-26} = mop.Value;
+  let Inst{28} = mew;
+  let Inst{27-26} = MOPLDIndexed.Value;
   let Inst{25} = vm;
   let Inst{24-20} = vs2;
   let Inst{19-15} = rs1;
-  let Inst{14-12} = width.Value;
+  let Inst{14-12} = width;
   let Inst{11-7} = vd;
   let Opcode = OPC_LOAD_FP.Value;
 
   let Uses = [VTYPE, VL];
+  let RVVConstraint = VMConstraint;
 }
 
-class RVInstVSU<bits<3> nf, RISCVMOP mop, RISCVLSUMOP sumop,
-                RISCVWidth width, dag outs, dag ins, string opcodestr,
+class RVInstVSU<bits<3> nf, bit mew, RISCVLSUMOP sumop,
+                bits<3> width, dag outs, dag ins, string opcodestr,
                 string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> rs1;
   bits<5> vs3;
   bit vm;
 
   let Inst{31-29} = nf;
-  let Inst{28-26} = mop.Value;
+  let Inst{28} = mew;
+  let Inst{27-26} = MOPSTUnitStride.Value;
   let Inst{25} = vm;
   let Inst{24-20} = sumop.Value;
   let Inst{19-15} = rs1;
-  let Inst{14-12} = width.Value;
+  let Inst{14-12} = width;
   let Inst{11-7} = vs3;
   let Opcode = OPC_STORE_FP.Value;
 
   let Uses = [VTYPE, VL];
 }
 
-class RVInstVSS<bits<3> nf, RISCVMOP mop, RISCVWidth width,
+class RVInstVSS<bits<3> nf, bit mew, bits<3> width,
                 dag outs, dag ins, string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> rs2;
   bits<5> rs1;
   bits<5> vs3;
   bit vm;
 
   let Inst{31-29} = nf;
-  let Inst{28-26} = mop.Value;
+  let Inst{28} = mew;
+  let Inst{27-26} = MOPSTStrided.Value;
   let Inst{25} = vm;
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
-  let Inst{14-12} = width.Value;
+  let Inst{14-12} = width;
   let Inst{11-7} = vs3;
   let Opcode = OPC_STORE_FP.Value;
 
   let Uses = [VTYPE, VL];
 }
 
-class RVInstVSX<bits<3> nf, RISCVMOP mop, RISCVWidth width,
+class RVInstVSX<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
                 dag outs, dag ins, string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> vs2;
   bits<5> rs1;
   bits<5> vs3;
   bit vm;
 
   let Inst{31-29} = nf;
-  let Inst{28-26} = mop.Value;
+  let Inst{28} = mew;
+  let Inst{27-26} = mop.Value;
   let Inst{25} = vm;
   let Inst{24-20} = vs2;
   let Inst{19-15} = rs1;
-  let Inst{14-12} = width.Value;
+  let Inst{14-12} = width;
   let Inst{11-7} = vs3;
   let Opcode = OPC_STORE_FP.Value;
 
   let Uses = [VTYPE, VL];
 }

llvm/lib/Target/RISCV/RISCVInstrInfo.h

 protected:
   const RISCVSubtarget &STI;
 };
 
 namespace RISCV {
 // Match with the definitions in RISCVInstrFormatsV.td
 enum RVVConstraintType {
   NoConstraint = 0,
-  WidenV = 1,
-  WidenW = 2,
-  WidenCvt = 3,
-  Narrow = 4,
-  Iota = 5,
-  SlideUp = 6,
-  Vrgather = 7,
-  Vcompress = 8,
+  VS2Constraint = 0b0001,
+  VS1Constraint = 0b0010,
+  VMConstraint = 0b0100,
+  OneInput = 0b1000,
+
+  // Illegal instructions:
+  //
+  // * The destination vector register group for a masked vector instruction
+  // cannot overlap the source mask register (v0), unless the destination vector
+  // register is being written with a mask value (e.g., comparisons) or the
+  // scalar result of a reduction.
+  //
+  // * Widening: The destination vector register group cannot overlap a source
+  // vector register group of a different EEW
+  //
+  // * Narrowing: The destination vector register group cannot overlap the
+  // first source vector register group
+  //
+  // * For vadc and vsbc, an illegal instruction exception is raised if the
+  // destination vector register is v0.
+  //
+  // * For vmadc and vmsbc, an illegal instruction exception is raised if the
+  // destination vector register overlaps a source vector register group.
+  //
+  // * viota: An illegal instruction exception is raised if the destination
+  // vector register group overlaps the source vector mask register. If the
+  // instruction is masked, an illegal instruction exception is issued if the
+  // destination vector register group overlaps v0.
+  //
+  // * v[f]slide[1]up: The destination vector register group for vslideup cannot
+  // overlap the source vector register group.
+  //
+  // * vrgather: The destination vector register group cannot overlap with the
+  // source vector register groups.
+  //
+  // * vcompress: The destination vector register group cannot overlap the
+  // source vector register group or the source mask register
+  WidenV = VS2Constraint | VS1Constraint | VMConstraint,
+  WidenW = VS1Constraint | VMConstraint,
+  WidenCvt = VS2Constraint | VMConstraint | OneInput,
+  Narrow = VS2Constraint | VMConstraint,
+  NarrowCvt = VS2Constraint | VMConstraint | OneInput,
+  Vmadc = VS2Constraint | VS1Constraint,
+  Iota = VS2Constraint | VMConstraint | OneInput,
+  SlideUp = VS2Constraint | VMConstraint,
+  Vrgather = VS2Constraint | VS1Constraint | VMConstraint,
+  Vcompress = VS2Constraint | VS1Constraint,
 
   ConstraintOffset = 5,
   ConstraintMask = 0b1111
 };
 } // end namespace RISCV
 
 } // end namespace llvm
 #endif

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

 //===-- RISCVInstrInfoV.td - RISC-V 'V' instructions -------*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 ///
 /// This file describes the RISC-V instructions from the standard 'V' Vector
-/// extension, version 0.8.
+/// extension, version 0.9.
 /// This version is still experimental as the 'V' extension hasn't been
 /// ratified yet.
 ///
 //===----------------------------------------------------------------------===//
 
 include "RISCVInstrFormatsV.td"
 
 //===----------------------------------------------------------------------===//

 }
 
 //===----------------------------------------------------------------------===//
 // Instruction class templates
 //===----------------------------------------------------------------------===//
 
 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
 // load vd, (rs1), vm
-class VUnitStrideLoad<RISCVMOP mop, RISCVLSUMOP lumop, RISCVWidth width,
-                        string opcodestr>
-    : RVInstVLU<0b000, mop, lumop, width, (outs VRegOp:$vd),
+class VUnitStrideLoad<RISCVLSUMOP lumop, RISCVWidth width,
+    : RVInstVLU<0b000, width.Value{3}, lumop, width.Value{2-0},
+                (outs VRegOp:$vd),
                 (ins GPR:$rs1, VMaskOp:$vm), opcodestr, "$vd, (${rs1})$vm">;
 
 // load vd, (rs1), rs2, vm
-class VStridedLoad<RISCVMOP mop, RISCVWidth width, string opcodestr>
-    : RVInstVLS<0b000, mop, width, (outs VRegOp:$vd),
+class VStridedLoad<RISCVWidth width, string opcodestr>
+    : RVInstVLS<0b000, width.Value{3}, width.Value{2-0},
+                (outs VRegOp:$vd),
                 (ins GPR:$rs1, GPR:$rs2, VMaskOp:$vm), opcodestr,
                 "$vd, (${rs1}), $rs2$vm">;
 
 // load vd, (rs1), vs2, vm
-class VIndexedLoad<RISCVMOP mop, RISCVWidth width, string opcodestr>
-    : RVInstVLX<0b000, mop, width, (outs VRegOp:$vd),
+class VIndexedLoad<RISCVWidth width, string opcodestr>
+    : RVInstVLX<0b000, width.Value{3}, width.Value{2-0},
+                (outs VRegOp:$vd),
                 (ins GPR:$rs1, VRegOp:$vs2, VMaskOp:$vm), opcodestr,
                 "$vd, (${rs1}), $vs2$vm">;
 
 // vl<nf>r.v vd, (rs1)
 class VWholeLoad<bits<3> nf, string opcodestr>
-    : RVInstVLU<nf, MOPLDUnitStrideU, LUMOPUnitStrideWholeReg,
-                LSWidthVSEW, (outs VRegOp:$vd), (ins GPR:$rs1),
+    : RVInstVLU<nf, 0b0, LUMOPUnitStrideWholeReg,
+                0b000, (outs VRegOp:$vd), (ins GPR:$rs1),
                 opcodestr, "$vd, (${rs1})"> {
   let vm = 1;
   let Uses = [];
 }
+
+// segment load vd, (rs1), vm
+class VUnitStrideSegmentLoad<bits<3> nf, RISCVLSUMOP lumop,
+                             RISCVWidth width, string opcodestr>
+    : RVInstVLU<nf, width.Value{3}, lumop, width.Value{2-0},
+                (outs VRegOp:$vd),
+                (ins GPR:$rs1, VMaskOp:$vm), opcodestr, "$vd, (${rs1})$vm">;
+
+// segment load vd, (rs1), rs2, vm
+class VStridedSegmentLoad<bits<3> nf, RISCVWidth width, string opcodestr>
+    : RVInstVLS<nf, width.Value{3}, width.Value{2-0},
+                (outs VRegOp:$vd),
+                (ins GPR:$rs1, GPR:$rs2, VMaskOp:$vm), opcodestr,
+                "$vd, (${rs1}), $rs2$vm">;
+
+
+// segment load vd, (rs1), vs2, vm
+class VIndexedSegmentLoad<bits<3> nf, RISCVWidth width, string opcodestr>
+    : RVInstVLX<nf, width.Value{3}, width.Value{2-0},
+                (outs VRegOp:$vd),
+                (ins GPR:$rs1, VRegOp:$vs2, VMaskOp:$vm), opcodestr,
+                "$vd, (${rs1}), $vs2$vm">;
 } // hasSideEffects = 0, mayLoad = 1, mayStore = 0
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
 // store vd, vs3, (rs1), vm
-class VUnitStrideStore<RISCVMOP mop, RISCVLSUMOP sumop, RISCVWidth width,
+class VUnitStrideStore<RISCVLSUMOP sumop, RISCVWidth width,
                          string opcodestr>
-    : RVInstVSU<0b000, mop, sumop, width, (outs),
-                (ins VRegOp:$vs3, GPR:$rs1, VMaskOp:$vm), opcodestr,
+    : RVInstVSU<0b000, width.Value{3}, sumop, width.Value{2-0},
+                (outs), (ins VRegOp:$vs3, GPR:$rs1, VMaskOp:$vm), opcodestr,
                 "$vs3, (${rs1})$vm">;
 
 // store vd, vs3, (rs1), rs2, vm
-class VStridedStore<RISCVMOP mop, RISCVWidth width, string opcodestr>
-    : RVInstVSS<0b000, mop, width, (outs),
+class VStridedStore<RISCVWidth width, string opcodestr>
+    : RVInstVSS<0b000, width.Value{3}, width.Value{2-0}, (outs),
                 (ins VRegOp:$vs3, GPR:$rs1, GPR:$rs2, VMaskOp:$vm),
                 opcodestr, "$vs3, (${rs1}), $rs2$vm">;
 
 // store vd, vs3, (rs1), vs2, vm
 class VIndexedStore<RISCVMOP mop, RISCVWidth width, string opcodestr>
-    : RVInstVSX<0b000, mop, width, (outs),
+    : RVInstVSX<0b000, width.Value{3}, mop, width.Value{2-0}, (outs),
                 (ins VRegOp:$vs3, GPR:$rs1, VRegOp:$vs2, VMaskOp:$vm),
                 opcodestr, "$vs3, (${rs1}), $vs2$vm">;
 
 // vs<nf>r.v vd, (rs1)
 class VWholeStore<bits<3> nf, string opcodestr>
-    : RVInstVSU<nf, MOPSTUnitStride, SUMOPUnitStrideWholeReg,
-                LSWidthVSEW, (outs), (ins VRegOp:$vs3, GPR:$rs1),
+    : RVInstVSU<nf, 0b0, SUMOPUnitStrideWholeReg,
+                0b000, (outs), (ins VRegOp:$vs3, GPR:$rs1),
                 opcodestr, "$vs3, (${rs1})"> {
   let vm = 1;
   let Uses = [];
 }
+
+// segment store vd, vs3, (rs1), vm
+class VUnitStrideSegmentStore<bits<3> nf, RISCVLSUMOP sumop, 
+                              RISCVWidth width, string opcodestr>
+    : RVInstVSU<nf, width.Value{3}, sumop, width.Value{2-0},
+                (outs), (ins VRegOp:$vs3, GPR:$rs1, VMaskOp:$vm), opcodestr,
+                "$vs3, (${rs1})$vm">;
+
+// segment store vd, vs3, (rs1), rs2, vm
+class VStridedSegmentStore<bits<3> nf, RISCVWidth width, string opcodestr>
+    : RVInstVSS<nf, width.Value{3}, width.Value{2-0}, (outs),
+                (ins VRegOp:$vs3, GPR:$rs1, GPR:$rs2, VMaskOp:$vm),
+                opcodestr, "$vs3, (${rs1}), $rs2$vm">;
+
+// segment store vd, vs3, (rs1), vs2, vm
+class VIndexedSegmentStore<bits<3> nf, RISCVMOP mop, RISCVWidth width, string opcodestr>
+    : RVInstVSX<nf, width.Value{3}, mop, width.Value{2-0}, (outs),
+                (ins VRegOp:$vs3, GPR:$rs1, VRegOp:$vs2, VMaskOp:$vm),
+                opcodestr, "$vs3, (${rs1}), $vs2$vm">;
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 1
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 // op vd, vs2, vs1, vm
 class VALUVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
     : RVInstVV<funct6, opv, (outs VRegOp:$vd),
                 (ins VRegOp:$vs2, VRegOp:$vs1, VMaskOp:$vm),
                 opcodestr, "$vd, $vs2, $vs1$vm">;

 def VSETVLI : RVInstSetVLi<(outs GPR:$rd), (ins GPR:$rs1, VTypeIOp:$vtypei),
                            "vsetvli", "$rd, $rs1, $vtypei">;
 
 def VSETVL : RVInstSetVL<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
                          "vsetvl", "$rd, $rs1, $rs2">;
 } // hasSideEffects = 1, mayLoad = 0, mayStore = 0
 
 // Vector Unit-Stride Instructions
-def VLB_V : VUnitStrideLoad<MOPLDUnitStrideS, LUMOPUnitStride, LSWidthVByte, "vlb.v">;
-def VLH_V : VUnitStrideLoad<MOPLDUnitStrideS, LUMOPUnitStride, LSWidthVHalf, "vlh.v">;
-def VLW_V : VUnitStrideLoad<MOPLDUnitStrideS, LUMOPUnitStride, LSWidthVWord, "vlw.v">;
-
-def VLBU_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStride, LSWidthVByte, "vlbu.v">;
-def VLHU_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStride, LSWidthVHalf, "vlhu.v">;
-def VLWU_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStride, LSWidthVWord, "vlwu.v">;
-
-def VLE_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStride, LSWidthVSEW, "vle.v">;
-
-def VLBFF_V : VUnitStrideLoad<MOPLDUnitStrideS, LUMOPUnitStrideFF, LSWidthVByte, "vlbff.v">;
-def VLHFF_V : VUnitStrideLoad<MOPLDUnitStrideS, LUMOPUnitStrideFF, LSWidthVHalf, "vlhff.v">;
-def VLWFF_V : VUnitStrideLoad<MOPLDUnitStrideS, LUMOPUnitStrideFF, LSWidthVWord, "vlwff.v">;
-
-def VLBUFF_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStrideFF, LSWidthVByte, "vlbuff.v">;
-def VLHUFF_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStrideFF, LSWidthVHalf, "vlhuff.v">;
-def VLWUFF_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStrideFF, LSWidthVWord, "vlwuff.v">;
-
-def VLEFF_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStrideFF, LSWidthVSEW, "vleff.v">;
-
-def VSB_V : VUnitStrideStore<MOPSTUnitStride, SUMOPUnitStride, LSWidthVByte, "vsb.v">;
-def VSH_V : VUnitStrideStore<MOPSTUnitStride, SUMOPUnitStride, LSWidthVHalf, "vsh.v">;
-def VSW_V : VUnitStrideStore<MOPSTUnitStride, SUMOPUnitStride, LSWidthVWord, "vsw.v">;
-
-def VSE_V : VUnitStrideStore<MOPSTUnitStride, SUMOPUnitStride, LSWidthVSEW, "vse.v">;
+def VLE8_V : VUnitStrideLoad<LUMOPUnitStride, LSWidth8, "vle8.v">;
+def VLE16_V : VUnitStrideLoad<LUMOPUnitStride, LSWidth16, "vle16.v">;
+def VLE32_V : VUnitStrideLoad<LUMOPUnitStride, LSWidth32, "vle32.v">;
+def VLE64_V : VUnitStrideLoad<LUMOPUnitStride, LSWidth64, "vle64.v">;
+def VLE128_V : VUnitStrideLoad<LUMOPUnitStride, LSWidth128, "vle128.v">;
+def VLE256_V : VUnitStrideLoad<LUMOPUnitStride, LSWidth256, "vle256.v">;
+def VLE512_V : VUnitStrideLoad<LUMOPUnitStride, LSWidth512, "vle512.v">;
+def VLE1024_V : VUnitStrideLoad<LUMOPUnitStride, LSWidth1024, "vle1024.v">;
+
+def VLE8FF_V : VUnitStrideLoad<LUMOPUnitStrideFF, LSWidth8, "vle8ff.v">;
+def VLE16FF_V : VUnitStrideLoad<LUMOPUnitStrideFF, LSWidth16, "vle16ff.v">;
+def VLE32FF_V : VUnitStrideLoad<LUMOPUnitStrideFF, LSWidth32, "vle32ff.v">;
+def VLE64FF_V : VUnitStrideLoad<LUMOPUnitStrideFF, LSWidth64, "vle64ff.v">;
+def VLE128FF_V : VUnitStrideLoad<LUMOPUnitStrideFF, LSWidth128, "vle128ff.v">;
+def VLE256FF_V : VUnitStrideLoad<LUMOPUnitStrideFF, LSWidth256, "vle256ff.v">;
+def VLE512FF_V : VUnitStrideLoad<LUMOPUnitStrideFF, LSWidth512, "vle512ff.v">;
+def VLE1024FF_V : VUnitStrideLoad<LUMOPUnitStrideFF, LSWidth1024, "vle1024ff.v">;
+
+def VSE8_V : VUnitStrideStore<SUMOPUnitStride, LSWidth8, "vse8.v">;
+def VSE16_V : VUnitStrideStore<SUMOPUnitStride, LSWidth16, "vse16.v">;
+def VSE32_V : VUnitStrideStore<SUMOPUnitStride, LSWidth32, "vse32.v">;
+def VSE64_V : VUnitStrideStore<SUMOPUnitStride, LSWidth64, "vse64.v">;
+def VSE128_V : VUnitStrideStore<SUMOPUnitStride, LSWidth128, "vse128.v">;
+def VSE256_V : VUnitStrideStore<SUMOPUnitStride, LSWidth256, "vse256.v">;
+def VSE512_V : VUnitStrideStore<SUMOPUnitStride, LSWidth512, "vse512.v">;
+def VSE1024_V : VUnitStrideStore<SUMOPUnitStride, LSWidth1024, "vse1024.v">;
 
 // Vector Strided Instructions
-def VLSB_V : VStridedLoad<MOPLDStridedS, LSWidthVByte, "vlsb.v">;
-def VLSH_V : VStridedLoad<MOPLDStridedS, LSWidthVHalf, "vlsh.v">;
-def VLSW_V : VStridedLoad<MOPLDStridedS, LSWidthVWord, "vlsw.v">;
-
-def VLSBU_V : VStridedLoad<MOPLDStridedU, LSWidthVByte, "vlsbu.v">;
-def VLSHU_V : VStridedLoad<MOPLDStridedU, LSWidthVHalf, "vlshu.v">;
-def VLSWU_V : VStridedLoad<MOPLDStridedU, LSWidthVWord, "vlswu.v">;
-
-def VLSE_V : VStridedLoad<MOPLDStridedU, LSWidthVSEW, "vlse.v">;
-
-def VSSB_V : VStridedStore<MOPSTStrided, LSWidthVByte, "vssb.v">;
-def VSSH_V : VStridedStore<MOPSTStrided, LSWidthVHalf, "vssh.v">;
-def VSSW_V : VStridedStore<MOPSTStrided, LSWidthVWord, "vssw.v">;
-def VSSE_V : VStridedStore<MOPSTStrided, LSWidthVSEW, "vsse.v">;
+def VLSE8_V : VStridedLoad<LSWidth8, "vlse8.v">;
+def VLSE16_V : VStridedLoad<LSWidth16, "vlse16.v">;
+def VLSE32_V : VStridedLoad<LSWidth32, "vlse32.v">;
+def VLSE64_V : VStridedLoad<LSWidth64, "vlse64.v">;
+def VLSE128_V : VStridedLoad<LSWidth128, "vlse128.v">;
+def VLSE256_V : VStridedLoad<LSWidth256, "vlse256.v">;
+def VLSE512_V : VStridedLoad<LSWidth512, "vlse512.v">;
+def VLSE1024_V : VStridedLoad<LSWidth1024, "vlse1024.v">;
+
+def VSSE8_V : VStridedStore<LSWidth8, "vsse8.v">;
+def VSSE16_V : VStridedStore<LSWidth16, "vsse16.v">;
+def VSSE32_V : VStridedStore<LSWidth32, "vsse32.v">;
+def VSSE64_V : VStridedStore<LSWidth64, "vsse64.v">;
+def VSSE128_V : VStridedStore<LSWidth128, "vsse128.v">;
+def VSSE256_V : VStridedStore<LSWidth256, "vsse256.v">;
+def VSSE512_V : VStridedStore<LSWidth512, "vsse512.v">;
+def VSSE1024_V : VStridedStore<LSWidth1024, "vsse1024.v">;
 
 // Vector Indexed Instructions
-def VLXB_V : VIndexedLoad<MOPLDIndexedS, LSWidthVByte, "vlxb.v">;
-def VLXH_V : VIndexedLoad<MOPLDIndexedS, LSWidthVHalf, "vlxh.v">;
-def VLXW_V : VIndexedLoad<MOPLDIndexedS, LSWidthVWord, "vlxw.v">;
-
-def VLXBU_V : VIndexedLoad<MOPLDIndexedU, LSWidthVByte, "vlxbu.v">;
-def VLXHU_V : VIndexedLoad<MOPLDIndexedU, LSWidthVHalf, "vlxhu.v">;
-def VLXWU_V : VIndexedLoad<MOPLDIndexedU, LSWidthVWord, "vlxwu.v">;
-
-def VLXE_V : VIndexedLoad<MOPLDIndexedU, LSWidthVSEW, "vlxe.v">;
-
-def VSXB_V : VIndexedStore<MOPSTIndexedOrder, LSWidthVByte, "vsxb.v">;
-def VSXH_V : VIndexedStore<MOPSTIndexedOrder, LSWidthVHalf, "vsxh.v">;
-def VSXW_V : VIndexedStore<MOPSTIndexedOrder, LSWidthVWord, "vsxw.v">;
-def VSXE_V : VIndexedStore<MOPSTIndexedOrder, LSWidthVSEW, "vsxe.v">;
-
-def VSUXB_V : VIndexedStore<MOPSTIndexedUnOrd, LSWidthVByte, "vsuxb.v">;
-def VSUXH_V : VIndexedStore<MOPSTIndexedUnOrd, LSWidthVHalf, "vsuxh.v">;
-def VSUXW_V : VIndexedStore<MOPSTIndexedUnOrd, LSWidthVWord, "vsuxw.v">;
-def VSUXE_V : VIndexedStore<MOPSTIndexedUnOrd, LSWidthVSEW, "vsuxe.v">;
+def VLXEI8_V : VIndexedLoad<LSWidth8, "vlxei8.v">;
+def VLXEI16_V : VIndexedLoad<LSWidth16, "vlxei16.v">;
+def VLXEI32_V : VIndexedLoad<LSWidth32, "vlxei32.v">;
+def VLXEI64_V : VIndexedLoad<LSWidth64, "vlxei64.v">;
+def VLXEI128_V : VIndexedLoad<LSWidth128, "vlxei128.v">;
+def VLXEI256_V : VIndexedLoad<LSWidth256, "vlxei256.v">;
+def VLXEI512_V : VIndexedLoad<LSWidth512, "vlxei512.v">;
+def VLXEI1024_V : VIndexedLoad<LSWidth1024, "vlxei1024.v">;
+
+def VSXEI8_V : VIndexedStore<MOPSTIndexedOrder, LSWidth8, "vsxei8.v">;
+def VSXEI16_V : VIndexedStore<MOPSTIndexedOrder, LSWidth16, "vsxei16.v">;
+def VSXEI32_V : VIndexedStore<MOPSTIndexedOrder, LSWidth32, "vsxei32.v">;
+def VSXEI64_V : VIndexedStore<MOPSTIndexedOrder, LSWidth64, "vsxei64.v">;
+def VSXEI128_V : VIndexedStore<MOPSTIndexedOrder, LSWidth128, "vsxei128.v">;
+def VSXEI256_V : VIndexedStore<MOPSTIndexedOrder, LSWidth256, "vsxei256.v">;
+def VSXEI512_V : VIndexedStore<MOPSTIndexedOrder, LSWidth512, "vsxei512.v">;
+def VSXEI1024_V : VIndexedStore<MOPSTIndexedOrder, LSWidth1024, "vsxei1024.v">;
+
+def VSUXEI8_V : VIndexedStore<MOPSTIndexedUnord, LSWidth8, "vsuxei8.v">;
+def VSUXEI16_V : VIndexedStore<MOPSTIndexedUnord, LSWidth16, "vsuxei16.v">;
+def VSUXEI32_V : VIndexedStore<MOPSTIndexedUnord, LSWidth32, "vsuxei32.v">;
+def VSUXEI64_V : VIndexedStore<MOPSTIndexedUnord, LSWidth64, "vsuxei64.v">;
+def VSUXEI128_V : VIndexedStore<MOPSTIndexedUnord, LSWidth128, "vsuxei128.v">;
+def VSUXEI256_V : VIndexedStore<MOPSTIndexedUnord, LSWidth256, "vsuxei256.v">;
+def VSUXEI512_V : VIndexedStore<MOPSTIndexedUnord, LSWidth512, "vsuxei512.v">;
+def VSUXEI1024_V : VIndexedStore<MOPSTIndexedUnord, LSWidth1024, "vsuxei1024.v">;
 
 def VL1R_V : VWholeLoad<0, "vl1r.v">;
 def VS1R_V : VWholeStore<0, "vs1r.v">;
 
 // Vector Single-Width Integer Add and Subtract
 defm VADD_V : VALU_IV_V_X_I<"vadd", 0b000000>;
 defm VSUB_V : VALU_IV_V_X<"vsub", 0b000010>;
 defm VRSUB_V : VALU_IV_X_I<"vrsub", 0b000011>;

 } // RVVConstraint = WidenW
 } // Constraints = "@earlyclobber $vd"
 
 def : InstAlias<"vwcvt.x.x.v $vd, $vs$vm",
                 (VWADD_VX VRegOp:$vd, VRegOp:$vs, X0, VMaskOp:$vm)>;
 def : InstAlias<"vwcvtu.x.x.v $vd, $vs$vm",
                 (VWADDU_VX VRegOp:$vd, VRegOp:$vs, X0, VMaskOp:$vm)>;
 
+// Vector Integer Extension
+defm VZEXT_VF8 : VALU_MV_VS2<"vzext.vf8", 0b010010, 0b00010>;
+defm VSEXT_VF8 : VALU_MV_VS2<"vsext.vf8", 0b010010, 0b00011>;
+defm VZEXT_VF4 : VALU_MV_VS2<"vzext.vf4", 0b010010, 0b00100>;
+defm VSEXT_VF4 : VALU_MV_VS2<"vsext.vf4", 0b010010, 0b00101>;
+defm VZEXT_VF2 : VALU_MV_VS2<"vzext.vf2", 0b010010, 0b00110>;
+defm VSEXT_VF2 : VALU_MV_VS2<"vsext.vf2", 0b010010, 0b00111>;
+
 // Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
 defm VADC_V : VALUm_IV_V_X_I<"vadc", 0b010000>;
+let Constraints = "@earlyclobber $vd", RVVConstraint = Vmadc in {
 defm VMADC_V : VALUm_IV_V_X_I<"vmadc", 0b010001>;
 defm VMADC_V : VALUNoVm_IV_V_X_I<"vmadc", 0b010001>;
+} // Constraints = "@earlyclobber $vd", RVVConstraint = Vmadc
 defm VSBC_V : VALUm_IV_V_X<"vsbc", 0b010010>;
+let Constraints = "@earlyclobber $vd", RVVConstraint = Vmadc in {
 defm VMSBC_V : VALUm_IV_V_X<"vmsbc", 0b010011>;
 defm VMSBC_V : VALUNoVm_IV_V_X<"vmsbc", 0b010011>;
+} // Constraints = "@earlyclobber $vd", RVVConstraint = Vmadc
 
 // Vector Bitwise Logical Instructions
 defm VAND_V : VALU_IV_V_X_I<"vand", 0b001001>;
 defm VOR_V : VALU_IV_V_X_I<"vor", 0b001010>;
 defm VXOR_V : VALU_IV_V_X_I<"vxor", 0b001011>;
 
 def : InstAlias<"vnot.v $vd, $vs$vm",
                 (VXOR_VI VRegOp:$vd, VRegOp:$vs, -1, VMaskOp:$vm)>;

 let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in {
 defm VFWMACC_V : VALUr_FV_V_F<"vfwmacc", 0b111100>;
 defm VFWNMACC_V : VALUr_FV_V_F<"vfwnmacc", 0b111101>;
 defm VFWMSAC_V : VALUr_FV_V_F<"vfwmsac", 0b111110>;
 defm VFWNMSAC_V : VALUr_FV_V_F<"vfwnmsac", 0b111111>;
 } // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV
 
 // Vector Floating-Point Square-Root Instruction
-defm VFSQRT_V : VALU_FV_VS2<"vfsqrt.v", 0b100011, 0b00000>;
+defm VFSQRT_V : VALU_FV_VS2<"vfsqrt.v", 0b010011, 0b00000>;
 
 // Vector Floating-Point MIN/MAX Instructions
 defm VFMIN_V : VALU_FV_V_F<"vfmin", 0b000100>;
 defm VFMAX_V : VALU_FV_V_F<"vfmax", 0b000110>;
 
 // Vector Floating-Point Sign-Injection Instructions
 defm VFSGNJ_V : VALU_FV_V_F<"vfsgnj", 0b001000>;
 defm VFSGNJN_V : VALU_FV_V_F<"vfsgnjn", 0b001001>;
 defm VFSGNJX_V : VALU_FV_V_F<"vfsgnjx", 0b001010>;
 
 // Vector Floating-Point Compare Instructions
 defm VMFEQ_V : VALU_FV_V_F<"vmfeq", 0b011000>;
 defm VMFNE_V : VALU_FV_V_F<"vmfne", 0b011100>;
 defm VMFLT_V : VALU_FV_V_F<"vmflt", 0b011011>;
 defm VMFLE_V : VALU_FV_V_F<"vmfle", 0b011001>;
 defm VMFGT_V : VALU_FV_F<"vmfgt", 0b011101>;
 defm VMFGE_V : VALU_FV_F<"vmfge", 0b011111>;
 
 def : InstAlias<"vmfgt.vv $vd, $va, $vb$vm",
                 (VMFLT_VV VRegOp:$vd, VRegOp:$vb, VRegOp:$va, VMaskOp:$vm), 0>;
 def : InstAlias<"vmfge.vv $vd, $va, $vb$vm",
                 (VMFLE_VV VRegOp:$vd, VRegOp:$vb, VRegOp:$va, VMaskOp:$vm), 0>;
 
 // Vector Floating-Point Classify Instruction
-defm VFCLASS_V : VALU_FV_VS2<"vfclass.v", 0b100011, 0b10000>;
+defm VFCLASS_V : VALU_FV_VS2<"vfclass.v", 0b010011, 0b10000>;
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 // Vector Floating-Point Merge Instruction
 def VFMERGE_VFM : RVInstVX<0b010111, OPFVF, (outs VRegOp:$vd),
                            (ins VRegOp:$vs2, FPR32:$rs1, VMV0:$v0),
                            "vfmerge.vfm", "$vd, $vs2, $rs1, v0"> {
   let vm = 0;
 }
 
 // Vector Floating-Point Move Instruction
 def VFMV_V_F : RVInstVX<0b010111, OPFVF, (outs VRegOp:$vd),
                        (ins FPR32:$rs1), "vfmv.v.f", "$vd, $rs1"> {
   let vs2 = 0;
   let vm = 1;
 }
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 
 // Single-Width Floating-Point/Integer Type-Convert Instructions
-defm VFCVT_XU_F_V : VALU_FV_VS2<"vfcvt.xu.f.v", 0b100010, 0b00000>;
-defm VFCVT_X_F_V : VALU_FV_VS2<"vfcvt.x.f.v", 0b100010, 0b00001>;
-defm VFCVT_F_XU_V : VALU_FV_VS2<"vfcvt.f.xu.v", 0b100010, 0b00010>;
-defm VFCVT_F_X_V : VALU_FV_VS2<"vfcvt.f.x.v", 0b100010, 0b00011>;
+defm VFCVT_XU_F_V : VALU_FV_VS2<"vfcvt.xu.f.v", 0b010010, 0b00000>;
+defm VFCVT_X_F_V : VALU_FV_VS2<"vfcvt.x.f.v", 0b010010, 0b00001>;
+defm VFCVT_RTZ_XU_F_V : VALU_FV_VS2<"vfcvt.rtz.xu.f.v", 0b010010, 0b00110>;
+defm VFCVT_RTZ_X_F_V : VALU_FV_VS2<"vfcvt.rtz.x.f.v", 0b010010, 0b00111>;
+defm VFCVT_F_XU_V : VALU_FV_VS2<"vfcvt.f.xu.v", 0b010010, 0b00010>;
+defm VFCVT_F_X_V : VALU_FV_VS2<"vfcvt.f.x.v", 0b010010, 0b00011>;
 
 // Widening Floating-Point/Integer Type-Convert Instructions
 let Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt in {
-defm VFWCVT_XU_F_V : VALU_FV_VS2<"vfwcvt.xu.f.v", 0b100010, 0b01000>;
-defm VFWCVT_X_F_V : VALU_FV_VS2<"vfwcvt.x.f.v", 0b100010, 0b01001>;
-defm VFWCVT_F_XU_V : VALU_FV_VS2<"vfwcvt.f.xu.v", 0b100010, 0b01010>;
-defm VFWCVT_F_X_V : VALU_FV_VS2<"vfwcvt.f.x.v", 0b100010, 0b01011>;
-defm VFWCVT_F_F_V : VALU_FV_VS2<"vfwcvt.f.f.v", 0b100010, 0b01100>;
+defm VFWCVT_XU_F_V : VALU_FV_VS2<"vfwcvt.xu.f.v", 0b010010, 0b01000>;
+defm VFWCVT_X_F_V : VALU_FV_VS2<"vfwcvt.x.f.v", 0b010010, 0b01001>;
+defm VFWCVT_RTZ_XU_F_V : VALU_FV_VS2<"vfwcvt.rtz.xu.f.v", 0b010010, 0b01110>;
+defm VFWCVT_RTZ_X_F_V : VALU_FV_VS2<"vfwcvt.rtz.x.f.v", 0b010010, 0b01111>;
+defm VFWCVT_F_XU_V : VALU_FV_VS2<"vfwcvt.f.xu.v", 0b010010, 0b01010>;
+defm VFWCVT_F_X_V : VALU_FV_VS2<"vfwcvt.f.x.v", 0b010010, 0b01011>;
+defm VFWCVT_F_F_V : VALU_FV_VS2<"vfwcvt.f.f.v", 0b010010, 0b01100>;
 } // Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt
 
 // Narrowing Floating-Point/Integer Type-Convert Instructions
-let Constraints = "@earlyclobber $vd", RVVConstraint = Narrow in {
-defm VFNCVT_XU_F_W : VALU_FV_VS2<"vfncvt.xu.f.w", 0b100010, 0b10000>;
-defm VFNCVT_X_F_W : VALU_FV_VS2<"vfncvt.x.f.w", 0b100010, 0b10001>;
-defm VFNCVT_F_XU_W : VALU_FV_VS2<"vfncvt.f.xu.w", 0b100010, 0b10010>;
-defm VFNCVT_F_X_W : VALU_FV_VS2<"vfncvt.f.x.w", 0b100010, 0b10011>;
-defm VFNCVT_F_F_W : VALU_FV_VS2<"vfncvt.f.f.w", 0b100010, 0b10100>;
-defm VFNCVT_ROD_F_F_W : VALU_FV_VS2<"vfncvt.rod.f.f.w", 0b100010, 0b10101>;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = Narrow
+let Constraints = "@earlyclobber $vd", RVVConstraint = NarrowCvt in {
+defm VFNCVT_XU_F_W : VALU_FV_VS2<"vfncvt.xu.f.w", 0b010010, 0b10000>;
+defm VFNCVT_X_F_W : VALU_FV_VS2<"vfncvt.x.f.w", 0b010010, 0b10001>;
+defm VFNCVT_RTZ_XU_F_W : VALU_FV_VS2<"vfncvt.rtz.xu.f.w", 0b010010, 0b10110>;
+defm VFNCVT_RTZ_X_F_W : VALU_FV_VS2<"vfncvt.rtz.x.f.w", 0b010010, 0b10111>;
+defm VFNCVT_F_XU_W : VALU_FV_VS2<"vfncvt.f.xu.w", 0b010010, 0b10010>;
+defm VFNCVT_F_X_W : VALU_FV_VS2<"vfncvt.f.x.w", 0b010010, 0b10011>;
+defm VFNCVT_F_F_W : VALU_FV_VS2<"vfncvt.f.f.w", 0b010010, 0b10100>;
+defm VFNCVT_ROD_F_F_W : VALU_FV_VS2<"vfncvt.rod.f.f.w", 0b010010, 0b10101>;
+} // Constraints = "@earlyclobber $vd", RVVConstraint = NarrowCvt
 
 // Vector Single-Width Integer Reduction Instructions
 defm VREDSUM : VALU_MV_V<"vredsum", 0b000000>;
 defm VREDMAXU : VALU_MV_V<"vredmaxu", 0b000110>;
 defm VREDMAX : VALU_MV_V<"vredmax", 0b000111>;
 defm VREDMINU : VALU_MV_V<"vredminu", 0b000100>;
 defm VREDMIN : VALU_MV_V<"vredmin", 0b000101>;
 defm VREDAND : VALU_MV_V<"vredand", 0b000001>;

 defm VMNAND_M : VALU_MV_Mask<"vmnand", 0b011101, "m">;
 defm VMANDNOT_M : VALU_MV_Mask<"vmandnot", 0b011000, "m">;
 defm VMXOR_M : VALU_MV_Mask<"vmxor", 0b011011, "m">;
 defm VMOR_M : VALU_MV_Mask<"vmor", 0b011010, "m">;
 defm VMNOR_M : VALU_MV_Mask<"vmnor", 0b011110, "m">;
 defm VMORNOT_M : VALU_MV_Mask<"vmornot", 0b011100, "m">;
 defm VMXNOR_M : VALU_MV_Mask<"vmxnor", 0b011111, "m">;
 
-def : InstAlias<"vmcpy.m $vd, $vs",
+def : InstAlias<"vmmv.m $vd, $vs",
                 (VMAND_MM VRegOp:$vd, VRegOp:$vs, VRegOp:$vs)>;
 def : InstAlias<"vmclr.m $vd",
                 (VMXOR_MM VRegOp:$vd, VRegOp:$vd, VRegOp:$vd)>;
 def : InstAlias<"vmset.m $vd",
                 (VMXNOR_MM VRegOp:$vd, VRegOp:$vd, VRegOp:$vd)>;
 def : InstAlias<"vmnot.m $vd, $vs",
                 (VMNAND_MM VRegOp:$vd, VRegOp:$vs, VRegOp:$vs)>;
 

 // Vector Slide Instructions
 let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in {
 defm VSLIDEUP_V : VALU_IV_X_I<"vslideup", 0b001110, uimm5>;
 } // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp
 defm VSLIDEDOWN_V : VALU_IV_X_I<"vslidedown", 0b001111, uimm5>;
 
 let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in {
 defm VSLIDE1UP_V : VALU_MV_X<"vslide1up", 0b001110>;
+defm VFSLIDE1UP_V : VALU_FV_F<"vfslide1up", 0b001110>;
 } // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp
 defm VSLIDE1DOWN_V : VALU_MV_X<"vslide1down", 0b001111>;
+defm VFSLIDE1DOWN_V : VALU_FV_F<"vfslide1down", 0b001111>;
 
 // Vector Register Gather Instruction
 let Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather in {
 defm VRGATHER_V : VALU_IV_V_X_I<"vrgather", 0b001100, uimm5>;
 } // Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather
 
 // Vector Compress Instruction
 let Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress in {
 defm VCOMPRESS_V : VALU_MV_Mask<"vcompress", 0b010111>;
 } // Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 foreach nf = [1, 2, 4, 8] in {
   def VMV#nf#R_V  : RVInstV<0b100111, !add(nf, -1), OPIVI, (outs VRegOp:$vd),
                             (ins VRegOp:$vs2), "vmv" # nf # "r.v",
                             "$vd, $vs2"> {
     let Uses = [];
     let vm = 1;
   }
 }
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 } // Predicates = [HasStdExtV]
+
+let Predicates = [HasStdExtV, HasStdExtZvlsseg] in {
+  foreach nf=2-8 in {
+    def VLSEG#nf#E8_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth8, "vlseg"#nf#"e8.v">;
+    def VLSEG#nf#E16_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth16, "vlseg"#nf#"e16.v">;
+    def VLSEG#nf#E32_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth32, "vlseg"#nf#"e32.v">;
+    def VLSEG#nf#E64_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth64, "vlseg"#nf#"e64.v">;
+    def VLSEG#nf#E128_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth128, "vlseg"#nf#"e128.v">;
+    def VLSEG#nf#E256_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth256, "vlseg"#nf#"e256.v">;
+    def VLSEG#nf#E512_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth512, "vlseg"#nf#"e512.v">;
+    def VLSEG#nf#E1024_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStride, LSWidth1024, "vlseg"#nf#"e1024.v">;
+
+    def VLSEG#nf#E8FF_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStrideFF, LSWidth8, "vlseg"#nf#"e8ff.v">;
+    def VLSEG#nf#E16FF_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStrideFF, LSWidth16, "vlseg"#nf#"e16ff.v">;
+    def VLSEG#nf#E32FF_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStrideFF, LSWidth32, "vlseg"#nf#"e32ff.v">;
+    def VLSEG#nf#E64FF_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStrideFF, LSWidth64, "vlseg"#nf#"e64ff.v">;
+    def VLSEG#nf#E128FF_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStrideFF, LSWidth128, "vlseg"#nf#"e128ff.v">;
+    def VLSEG#nf#E256FF_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStrideFF, LSWidth256, "vlseg"#nf#"e256ff.v">;
+    def VLSEG#nf#E512FF_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStrideFF, LSWidth512, "vlseg"#nf#"e512ff.v">;
+    def VLSEG#nf#E1024FF_V : VUnitStrideSegmentLoad<!add(nf, -1), LUMOPUnitStrideFF, LSWidth1024, "vlseg"#nf#"e1024ff.v">;
+
+    def VSSEG#nf#E8_V : VUnitStrideSegmentStore<!add(nf, -1), SUMOPUnitStride, LSWidth8, "vsseg"#nf#"e8.v">;
+    def VSSEG#nf#E16_V : VUnitStrideSegmentStore<!add(nf, -1), SUMOPUnitStride, LSWidth16, "vsseg"#nf#"e16.v">;
+    def VSSEG#nf#E32_V : VUnitStrideSegmentStore<!add(nf, -1), SUMOPUnitStride, LSWidth32, "vsseg"#nf#"e32.v">;
+    def VSSEG#nf#E64_V : VUnitStrideSegmentStore<!add(nf, -1), SUMOPUnitStride, LSWidth64, "vsseg"#nf#"e64.v">;
+    def VSSEG#nf#E128_V : VUnitStrideSegmentStore<!add(nf, -1), SUMOPUnitStride, LSWidth128, "vsseg"#nf#"e128.v">;
+    def VSSEG#nf#E256_V : VUnitStrideSegmentStore<!add(nf, -1), SUMOPUnitStride, LSWidth256, "vsseg"#nf#"e256.v">;
+    def VSSEG#nf#E512_V : VUnitStrideSegmentStore<!add(nf, -1), SUMOPUnitStride, LSWidth512, "vsseg"#nf#"e512.v">;
+    def VSSEG#nf#E1024_V : VUnitStrideSegmentStore<!add(nf, -1), SUMOPUnitStride, LSWidth1024, "vsseg"#nf#"e1024.v">;
+
+    // Vector Strided Instructions
+    def VLSSEG#nf#E8_V : VStridedSegmentLoad<!add(nf, -1), LSWidth8, "vlsseg"#nf#"e8.v">;
+    def VLSSEG#nf#E16_V : VStridedSegmentLoad<!add(nf, -1), LSWidth16, "vlsseg"#nf#"e16.v">;
+    def VLSSEG#nf#E32_V : VStridedSegmentLoad<!add(nf, -1), LSWidth32, "vlsseg"#nf#"e32.v">;
+    def VLSSEG#nf#E64_V : VStridedSegmentLoad<!add(nf, -1), LSWidth64, "vlsseg"#nf#"e64.v">;
+    def VLSSEG#nf#E128_V : VStridedSegmentLoad<!add(nf, -1), LSWidth128, "vlsseg"#nf#"e128.v">;
+    def VLSSEG#nf#E256_V : VStridedSegmentLoad<!add(nf, -1), LSWidth256, "vlsseg"#nf#"e256.v">;
+    def VLSSEG#nf#E512_V : VStridedSegmentLoad<!add(nf, -1), LSWidth512, "vlsseg"#nf#"e512.v">;
+    def VLSSEG#nf#E1024_V : VStridedSegmentLoad<!add(nf, -1), LSWidth1024, "vlsseg"#nf#"e1024.v">;
+
+    def VSSSEG#nf#E8_V : VStridedSegmentStore<!add(nf, -1), LSWidth8, "vssseg"#nf#"e8.v">;
+    def VSSSEG#nf#E16_V : VStridedSegmentStore<!add(nf, -1), LSWidth16, "vssseg"#nf#"e16.v">;
+    def VSSSEG#nf#E32_V : VStridedSegmentStore<!add(nf, -1), LSWidth32, "vssseg"#nf#"e32.v">;
+    def VSSSEG#nf#E64_V : VStridedSegmentStore<!add(nf, -1), LSWidth64, "vssseg"#nf#"e64.v">;
+    def VSSSEG#nf#E128_V : VStridedSegmentStore<!add(nf, -1), LSWidth128, "vssseg"#nf#"e128.v">;
+    def VSSSEG#nf#E256_V : VStridedSegmentStore<!add(nf, -1), LSWidth256, "vssseg"#nf#"e256.v">;
+    def VSSSEG#nf#E512_V : VStridedSegmentStore<!add(nf, -1), LSWidth512, "vssseg"#nf#"e512.v">;
+    def VSSSEG#nf#E1024_V : VStridedSegmentStore<!add(nf, -1), LSWidth1024, "vssseg"#nf#"e1024.v">;
+
+    // Vector Indexed Instructions
+    def VLXSEG#nf#EI8_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth8, "vlxseg"#nf#"ei8.v">;
+    def VLXSEG#nf#EI16_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth16, "vlxseg"#nf#"ei16.v">;
+    def VLXSEG#nf#EI32_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth32, "vlxseg"#nf#"ei32.v">;
+    def VLXSEG#nf#EI64_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth64, "vlxseg"#nf#"ei64.v">;
+    def VLXSEG#nf#EI128_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth128, "vlxseg"#nf#"ei128.v">;
+    def VLXSEG#nf#EI256_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth256, "vlxseg"#nf#"ei256.v">;
+    def VLXSEG#nf#EI512_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth512, "vlxseg"#nf#"ei512.v">;
+    def VLXSEG#nf#EI1024_V : VIndexedSegmentLoad<!add(nf, -1), LSWidth1024, "vlxseg"#nf#"ei1024.v">;
+
+    def VSXSEG#nf#EI8_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, LSWidth8, "vsxseg"#nf#"ei8.v">;
+    def VSXSEG#nf#EI16_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, LSWidth16, "vsxseg"#nf#"ei16.v">;
+    def VSXSEG#nf#EI32_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, LSWidth32, "vsxseg"#nf#"ei32.v">;
+    def VSXSEG#nf#EI64_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, LSWidth64, "vsxseg"#nf#"ei64.v">;
+    def VSXSEG#nf#EI128_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, LSWidth128, "vsxseg"#nf#"ei128.v">;
+    def VSXSEG#nf#EI256_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, LSWidth256, "vsxseg"#nf#"ei256.v">;
+    def VSXSEG#nf#EI512_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, LSWidth512, "vsxseg"#nf#"ei512.v">;
+    def VSXSEG#nf#EI1024_V : VIndexedSegmentStore<!add(nf, -1), MOPSTIndexedOrder, LSWidth1024, "vsxseg"#nf#"ei1024.v">;
+  }
+} // Predicates = [HasStdExtV, HasStdExtZvlsseg]

llvm/lib/Target/RISCV/RISCVSchedRocket32.td

 
 // Rocket machine model for scheduling and other instruction cost heuristics.
 def Rocket32Model : SchedMachineModel {
   let MicroOpBufferSize = 0; // Explicitly set to zero since Rocket is in-order.
   let IssueWidth = 1;        // 1 micro-ops are dispatched per cycle.
   let LoadLatency = 3;
   let MispredictPenalty = 3;
   let CompleteModel = 1;
-  let UnsupportedFeatures = [HasStdExtV];
+  let UnsupportedFeatures = [HasStdExtV, HasStdExtZvlsseg];
 }
 
 //===----------------------------------------------------------------------===//
 // Define each kind of processor resource and number available.
 
 // Modeling each pipeline as a ProcResource using the BufferSize = 0 since
 // Rocket is in-order.
 

llvm/lib/Target/RISCV/RISCVSchedRocket64.td

 // This works with MachineScheduler. See MCSchedule.h for details.
 
 // Rocket machine model for scheduling and other instruction cost heuristics.
 def Rocket64Model : SchedMachineModel {
   let MicroOpBufferSize = 0; // Explicitly set to zero since Rocket is in-order.
   let IssueWidth = 1;        // 1 micro-ops are dispatched per cycle.
   let LoadLatency = 3;
   let MispredictPenalty = 3;
-  let UnsupportedFeatures = [HasStdExtV];
+  let UnsupportedFeatures = [HasStdExtV, HasStdExtZvlsseg];
 }
 
 //===----------------------------------------------------------------------===//
 // Define each kind of processor resource and number available.
 
 // Modeling each pipeline as a ProcResource using the BufferSize = 0 since
 // Rocket is in-order.
 

llvm/lib/Target/RISCV/RISCVSubtarget.h

class RISCVSubtarget : public RISCVGenSubtargetInfo {
   bool HasStdExtZbf = false;
   bool HasStdExtZbm = false;
   bool HasStdExtZbp = false;
   bool HasStdExtZbr = false;
   bool HasStdExtZbs = false;
   bool HasStdExtZbt = false;
   bool HasStdExtZbproposedc = false;
   bool HasStdExtV = false;
+  bool HasStdExtZvlsseg = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
   bool EnableLinkerRelax = false;
   bool EnableRVCHintInstrs = true;
   bool EnableSaveRestore = false;
   unsigned XLen = 32;
   MVT XLenVT = MVT::i32;
   RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
public:
   bool hasStdExtZbf() const { return HasStdExtZbf; }
   bool hasStdExtZbm() const { return HasStdExtZbm; }
   bool hasStdExtZbp() const { return HasStdExtZbp; }
   bool hasStdExtZbr() const { return HasStdExtZbr; }
   bool hasStdExtZbs() const { return HasStdExtZbs; }
   bool hasStdExtZbt() const { return HasStdExtZbt; }
   bool hasStdExtZbproposedc() const { return HasStdExtZbproposedc; }
   bool hasStdExtV() const { return HasStdExtV; }
+  bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
   bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; }
   bool enableSaveRestore() const { return EnableSaveRestore; }
   MVT getXLenVT() const { return XLenVT; }
   unsigned getXLen() const { return XLen; }
   RISCVABI::ABI getTargetABI() const { return TargetABI; }

llvm/test/MC/RISCV/rvv/convert.s

 # RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
 # RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
 # RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
 # RUN:        | llvm-objdump -d --mattr=+experimental-v - \
 # RUN:        | FileCheck %s --check-prefix=CHECK-INST
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
 # RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
 vfcvt.xu.f.v v8, v4, v0.t
 # CHECK-INST: vfcvt.xu.f.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x14,0x40,0x88]
+# CHECK-ENCODING: [0x57,0x14,0x40,0x48]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 40 88 <unknown>
+# CHECK-UNKNOWN: 57 14 40 48 <unknown>
 
 vfcvt.xu.f.v v8, v4
 # CHECK-INST: vfcvt.xu.f.v v8, v4
-# CHECK-ENCODING: [0x57,0x14,0x40,0x8a]
+# CHECK-ENCODING: [0x57,0x14,0x40,0x4a]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 40 8a <unknown>
+# CHECK-UNKNOWN: 57 14 40 4a <unknown>
 
 vfcvt.x.f.v v8, v4, v0.t
 # CHECK-INST: vfcvt.x.f.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x94,0x40,0x88]
+# CHECK-ENCODING: [0x57,0x94,0x40,0x48]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 40 88 <unknown>
+# CHECK-UNKNOWN: 57 94 40 48 <unknown>
 
 vfcvt.x.f.v v8, v4
 # CHECK-INST: vfcvt.x.f.v v8, v4
-# CHECK-ENCODING: [0x57,0x94,0x40,0x8a]
+# CHECK-ENCODING: [0x57,0x94,0x40,0x4a]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 40 8a <unknown>
+# CHECK-UNKNOWN: 57 94 40 4a <unknown>
 
 vfcvt.f.xu.v v8, v4, v0.t
 # CHECK-INST: vfcvt.f.xu.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x14,0x41,0x88]
+# CHECK-ENCODING: [0x57,0x14,0x41,0x48]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 41 88 <unknown>
+# CHECK-UNKNOWN: 57 14 41 48 <unknown>
 
 vfcvt.f.xu.v v8, v4
 # CHECK-INST: vfcvt.f.xu.v v8, v4
-# CHECK-ENCODING: [0x57,0x14,0x41,0x8a]
+# CHECK-ENCODING: [0x57,0x14,0x41,0x4a]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 41 8a <unknown>
+# CHECK-UNKNOWN: 57 14 41 4a <unknown>
 
 vfcvt.f.x.v v8, v4, v0.t
 # CHECK-INST: vfcvt.f.x.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x94,0x41,0x88]
+# CHECK-ENCODING: [0x57,0x94,0x41,0x48]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 41 88 <unknown>
+# CHECK-UNKNOWN: 57 94 41 48 <unknown>
 
 vfcvt.f.x.v v8, v4
 # CHECK-INST: vfcvt.f.x.v v8, v4
-# CHECK-ENCODING: [0x57,0x94,0x41,0x8a]
+# CHECK-ENCODING: [0x57,0x94,0x41,0x4a]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 41 8a <unknown>
+# CHECK-UNKNOWN: 57 94 41 4a <unknown>
+
+vfcvt.rtz.xu.f.v v8, v4, v0.t
+# CHECK-INST: vfcvt.rtz.xu.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x43,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 43 48 <unknown>
+
+vfcvt.rtz.xu.f.v v8, v4
+# CHECK-INST: vfcvt.rtz.xu.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x43,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 43 4a <unknown>
+
+vfcvt.rtz.x.f.v v8, v4, v0.t
+# CHECK-INST: vfcvt.rtz.x.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x43,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 43 48 <unknown>
+
+vfcvt.rtz.x.f.v v8, v4
+# CHECK-INST: vfcvt.rtz.x.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x43,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 43 4a <unknown>
 
 vfwcvt.xu.f.v v8, v4, v0.t
 # CHECK-INST: vfwcvt.xu.f.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x14,0x44,0x88]
+# CHECK-ENCODING: [0x57,0x14,0x44,0x48]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 44 88 <unknown>
+# CHECK-UNKNOWN: 57 14 44 48 <unknown>
 
 vfwcvt.xu.f.v v8, v4
 # CHECK-INST: vfwcvt.xu.f.v v8, v4
-# CHECK-ENCODING: [0x57,0x14,0x44,0x8a]
+# CHECK-ENCODING: [0x57,0x14,0x44,0x4a]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 44 8a <unknown>
+# CHECK-UNKNOWN: 57 14 44 4a <unknown>
 
 vfwcvt.x.f.v v8, v4, v0.t
 # CHECK-INST: vfwcvt.x.f.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x94,0x44,0x88]
+# CHECK-ENCODING: [0x57,0x94,0x44,0x48]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 44 88 <unknown>
+# CHECK-UNKNOWN: 57 94 44 48 <unknown>
 
 vfwcvt.x.f.v v8, v4
 # CHECK-INST: vfwcvt.x.f.v v8, v4
-# CHECK-ENCODING: [0x57,0x94,0x44,0x8a]
+# CHECK-ENCODING: [0x57,0x94,0x44,0x4a]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 44 8a <unknown>
+# CHECK-UNKNOWN: 57 94 44 4a <unknown>
 
 vfwcvt.f.xu.v v8, v4, v0.t
 # CHECK-INST: vfwcvt.f.xu.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x14,0x45,0x88]
+# CHECK-ENCODING: [0x57,0x14,0x45,0x48]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 45 88 <unknown>
+# CHECK-UNKNOWN: 57 14 45 48 <unknown>
 
 vfwcvt.f.xu.v v8, v4
 # CHECK-INST: vfwcvt.f.xu.v v8, v4
-# CHECK-ENCODING: [0x57,0x14,0x45,0x8a]
+# CHECK-ENCODING: [0x57,0x14,0x45,0x4a]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 45 8a <unknown>
+# CHECK-UNKNOWN: 57 14 45 4a <unknown>
 
 vfwcvt.f.x.v v8, v4, v0.t
 # CHECK-INST: vfwcvt.f.x.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x94,0x45,0x88]
+# CHECK-ENCODING: [0x57,0x94,0x45,0x48]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 45 88 <unknown>
+# CHECK-UNKNOWN: 57 94 45 48 <unknown>
 
 vfwcvt.f.x.v v8, v4
 # CHECK-INST: vfwcvt.f.x.v v8, v4
-# CHECK-ENCODING: [0x57,0x94,0x45,0x8a]
+# CHECK-ENCODING: [0x57,0x94,0x45,0x4a]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 45 8a <unknown>
+# CHECK-UNKNOWN: 57 94 45 4a <unknown>
 
 vfwcvt.f.f.v v8, v4, v0.t
 # CHECK-INST: vfwcvt.f.f.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x14,0x46,0x88]
+# CHECK-ENCODING: [0x57,0x14,0x46,0x48]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 46 88 <unknown>
+# CHECK-UNKNOWN: 57 14 46 48 <unknown>
 
 vfwcvt.f.f.v v8, v4
 # CHECK-INST: vfwcvt.f.f.v v8, v4
-# CHECK-ENCODING: [0x57,0x14,0x46,0x8a]
+# CHECK-ENCODING: [0x57,0x14,0x46,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 46 4a <unknown>
+
+vfwcvt.rtz.xu.f.v v8, v4, v0.t
+# CHECK-INST: vfwcvt.rtz.xu.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x47,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 47 48 <unknown>
+
+vfwcvt.rtz.xu.f.v v8, v4
+# CHECK-INST: vfwcvt.rtz.xu.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x47,0x4a]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 46 8a <unknown>
+# CHECK-UNKNOWN: 57 14 47 4a <unknown>
+
+vfwcvt.rtz.x.f.v v8, v4, v0.t
+# CHECK-INST: vfwcvt.rtz.x.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x47,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 47 48 <unknown>
+
+vfwcvt.rtz.x.f.v v8, v4
+# CHECK-INST: vfwcvt.rtz.x.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x47,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 47 4a <unknown>
 
 vfncvt.xu.f.w v8, v4, v0.t
 # CHECK-INST: vfncvt.xu.f.w v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x14,0x48,0x88]
+# CHECK-ENCODING: [0x57,0x14,0x48,0x48]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 48 88 <unknown>
+# CHECK-UNKNOWN: 57 14 48 48 <unknown>
 
 vfncvt.xu.f.w v8, v4
 # CHECK-INST: vfncvt.xu.f.w v8, v4
-# CHECK-ENCODING: [0x57,0x14,0x48,0x8a]
+# CHECK-ENCODING: [0x57,0x14,0x48,0x4a]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 48 8a <unknown>
+# CHECK-UNKNOWN: 57 14 48 4a <unknown>
 
 vfncvt.x.f.w v8, v4, v0.t
 # CHECK-INST: vfncvt.x.f.w v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x94,0x48,0x88]
+# CHECK-ENCODING: [0x57,0x94,0x48,0x48]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 48 88 <unknown>
+# CHECK-UNKNOWN: 57 94 48 48 <unknown>
 
 vfncvt.x.f.w v8, v4
 # CHECK-INST: vfncvt.x.f.w v8, v4
-# CHECK-ENCODING: [0x57,0x94,0x48,0x8a]
+# CHECK-ENCODING: [0x57,0x94,0x48,0x4a]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 48 8a <unknown>
+# CHECK-UNKNOWN: 57 94 48 4a <unknown>
 
 vfncvt.f.xu.w v8, v4, v0.t
 # CHECK-INST: vfncvt.f.xu.w v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x14,0x49,0x88]
+# CHECK-ENCODING: [0x57,0x14,0x49,0x48]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 49 88 <unknown>
+# CHECK-UNKNOWN: 57 14 49 48 <unknown>
 
 vfncvt.f.xu.w v8, v4
 # CHECK-INST: vfncvt.f.xu.w v8, v4
-# CHECK-ENCODING: [0x57,0x14,0x49,0x8a]
+# CHECK-ENCODING: [0x57,0x14,0x49,0x4a]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 49 8a <unknown>
+# CHECK-UNKNOWN: 57 14 49 4a <unknown>
 
 vfncvt.f.x.w v8, v4, v0.t
 # CHECK-INST: vfncvt.f.x.w v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x94,0x49,0x88]
+# CHECK-ENCODING: [0x57,0x94,0x49,0x48]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 49 88 <unknown>
+# CHECK-UNKNOWN: 57 94 49 48 <unknown>
 
 vfncvt.f.x.w v8, v4
 # CHECK-INST: vfncvt.f.x.w v8, v4
-# CHECK-ENCODING: [0x57,0x94,0x49,0x8a]
+# CHECK-ENCODING: [0x57,0x94,0x49,0x4a]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 49 8a <unknown>
+# CHECK-UNKNOWN: 57 94 49 4a <unknown>
 
 vfncvt.f.f.w v8, v4, v0.t
 # CHECK-INST: vfncvt.f.f.w v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x14,0x4a,0x88]
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x48]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 4a 88 <unknown>
+# CHECK-UNKNOWN: 57 14 4a 48 <unknown>
 
 vfncvt.f.f.w v8, v4
 # CHECK-INST: vfncvt.f.f.w v8, v4
-# CHECK-ENCODING: [0x57,0x14,0x4a,0x8a]
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x4a]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 4a 8a <unknown>
+# CHECK-UNKNOWN: 57 14 4a 4a <unknown>
 
 vfncvt.rod.f.f.w v8, v4, v0.t
 # CHECK-INST: vfncvt.rod.f.f.w v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x94,0x4a,0x88]
+# CHECK-ENCODING: [0x57,0x94,0x4a,0x48]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 4a 88 <unknown>
+# CHECK-UNKNOWN: 57 94 4a 48 <unknown>
 
 vfncvt.rod.f.f.w v8, v4
 # CHECK-INST: vfncvt.rod.f.f.w v8, v4
-# CHECK-ENCODING: [0x57,0x94,0x4a,0x8a]
+# CHECK-ENCODING: [0x57,0x94,0x4a,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 4a 4a <unknown>
+
+vfncvt.rtz.xu.f.w v8, v4, v0.t
+# CHECK-INST: vfncvt.rtz.xu.f.w v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4b,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4b 48 <unknown>
+
+vfncvt.rtz.xu.f.w v8, v4
+# CHECK-INST: vfncvt.rtz.xu.f.w v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x4b,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4b 4a <unknown>
+
+vfncvt.rtz.x.f.w v8, v4, v0.t
+# CHECK-INST: vfncvt.rtz.x.f.w v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x4b,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 4b 48 <unknown>
+
+vfncvt.rtz.x.f.w v8, v4
+# CHECK-INST: vfncvt.rtz.x.f.w v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x4b,0x4a]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 94 4a 8a <unknown>
+# CHECK-UNKNOWN: 57 94 4b 4a <unknown>

llvm/test/MC/RISCV/rvv/ext.s

+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-v - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vzext.vf2 v8, v4, v0.t
+# CHECK-INST: vzext.vf2 v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x43,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 43 48 <unknown>
+
+vzext.vf2 v8, v4
+# CHECK-INST: vzext.vf2 v8, v4
+# CHECK-ENCODING: [0x57,0x24,0x43,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 43 4a <unknown>
+
+vsext.vf2 v8, v4, v0.t
+# CHECK-INST: vsext.vf2 v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0xa4,0x43,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 a4 43 48 <unknown>
+
+vsext.vf2 v8, v4
+# CHECK-INST: vsext.vf2 v8, v4
+# CHECK-ENCODING: [0x57,0xa4,0x43,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 a4 43 4a <unknown>
+
+vzext.vf4 v8, v4, v0.t
+# CHECK-INST: vzext.vf4 v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x42,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 42 48 <unknown>
+
+vzext.vf4 v8, v4
+# CHECK-INST: vzext.vf4 v8, v4
+# CHECK-ENCODING: [0x57,0x24,0x42,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 42 4a <unknown>
+
+vsext.vf4 v8, v4, v0.t
+# CHECK-INST: vsext.vf4 v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0xa4,0x42,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 a4 42 48 <unknown>
+
+vsext.vf4 v8, v4
+# CHECK-INST: vsext.vf4 v8, v4
+# CHECK-ENCODING: [0x57,0xa4,0x42,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 a4 42 4a <unknown>
+
+vzext.vf8 v8, v4, v0.t
+# CHECK-INST: vzext.vf8 v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x41,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 41 48 <unknown>
+
+vzext.vf8 v8, v4
+# CHECK-INST: vzext.vf8 v8, v4
+# CHECK-ENCODING: [0x57,0x24,0x41,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 41 4a <unknown>
+
+vsext.vf8 v8, v4, v0.t
+# CHECK-INST: vsext.vf8 v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0xa4,0x41,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 a4 41 48 <unknown>
+
+vsext.vf8 v8, v4
+# CHECK-INST: vsext.vf8 v8, v4
+# CHECK-ENCODING: [0x57,0xa4,0x41,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 a4 41 4a <unknown>

llvm/test/MC/RISCV/rvv/fothers.s

 # RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
 # RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
 # RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
 # RUN:        | llvm-objdump -d --mattr=+experimental-v - \
 # RUN:        | FileCheck %s --check-prefix=CHECK-INST
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
 # RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
 vfsqrt.v v8, v4, v0.t
 # CHECK-INST: vfsqrt.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x14,0x40,0x8c]
+# CHECK-ENCODING: [0x57,0x14,0x40,0x4c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 40 8c <unknown>
+# CHECK-UNKNOWN: 57 14 40 4c <unknown>
 
 vfsqrt.v v8, v4
 # CHECK-INST: vfsqrt.v v8, v4
-# CHECK-ENCODING: [0x57,0x14,0x40,0x8e]
+# CHECK-ENCODING: [0x57,0x14,0x40,0x4e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 40 8e <unknown>
+# CHECK-UNKNOWN: 57 14 40 4e <unknown>
 
 vfclass.v v8, v4, v0.t
 # CHECK-INST: vfclass.v v8, v4, v0.t
-# CHECK-ENCODING: [0x57,0x14,0x48,0x8c]
+# CHECK-ENCODING: [0x57,0x14,0x48,0x4c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 48 8c <unknown>
+# CHECK-UNKNOWN: 57 14 48 4c <unknown>
 
 vfclass.v v8, v4
 # CHECK-INST: vfclass.v v8, v4
-# CHECK-ENCODING: [0x57,0x14,0x48,0x8e]
+# CHECK-ENCODING: [0x57,0x14,0x48,0x4e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 14 48 8e <unknown>
+# CHECK-UNKNOWN: 57 14 48 4e <unknown>
 
 vfmerge.vfm v8, v4, fa0, v0
 # CHECK-INST: vfmerge.vfm v8, v4, fa0, v0
 # CHECK-ENCODING: [0x57,0x54,0x45,0x5c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 57 54 45 5c <unknown>
+
+vfslide1up.vf v8, v4, fa0, v0.t
+# CHECK-INST: vfslide1up.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x38]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 38 <unknown>
+
+vfslide1up.vf v8, v4, fa0
+# CHECK-INST: vfslide1up.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x3a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 3a <unknown>
+
+vfslide1down.vf v8, v4, fa0, v0.t
+# CHECK-INST: vfslide1down.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x3c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 3c <unknown>
+
+vfslide1down.vf v8, v4, fa0
+# CHECK-INST: vfslide1down.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x3e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 3e <unknown>

llvm/test/MC/RISCV/rvv/invalid.s

 # RUN: not llvm-mc -triple=riscv64 --mattr=+experimental-v --mattr=+f %s 2>&1 \
 # RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 
 vsetvli a2, a0, e31
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
 
 vsetvli a2, a0, e32,m3
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
 
 vsetvli a2, a0, m1,e32
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
 
 vsetvli a2, a0, e32,m16
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
 
 vsetvli a2, a0, e2048,m8
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
 
 vsetvli a2, a0, e1,m8
-# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+
+vsetvli a2, a0, e8,m1,tx
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+
+vsetvli a2, a0, e8,m1,ta,mx
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+
+vsetvli a2, a0, e8,m1,ma
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
+
+vsetvli a2, a0, e8,m1,mu
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8|f2|f4|f8],[ta|tu],[ma|mu]
 
 vadd.vv v1, v3, v2, v4.t
 # CHECK-ERROR: operand must be v0.t
 
 vadd.vv v1, v3, v2, v0
 # CHECK-ERROR: expected '.t' suffix
 
 vmslt.vi v1, v2, -16

 vfwcvt.xu.f.v v0, v2, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vfwcvt.xu.f.v v0, v2, v0.t
 
 vfwcvt.xu.f.v v2, v2
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vfwcvt.xu.f.v v2, v2
 
-vfwcvt.xu.f.v v2, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwcvt.xu.f.v v2, v3
-
 vfwcvt.x.f.v v0, v2, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vfwcvt.x.f.v v0, v2, v0.t
 
 vfwcvt.x.f.v v2, v2
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vfwcvt.x.f.v v2, v2
 
-vfwcvt.x.f.v v2, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwcvt.x.f.v v2, v3
-
 vfwcvt.f.xu.v v0, v2, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vfwcvt.f.xu.v v0, v2, v0.t
 
 vfwcvt.f.xu.v v2, v2
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vfwcvt.f.xu.v v2, v2
 
-vfwcvt.f.xu.v v2, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwcvt.f.xu.v v2, v3
-
 vfwcvt.f.x.v v0, v2, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vfwcvt.f.x.v v0, v2, v0.t
 
 vfwcvt.f.x.v v2, v2
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vfwcvt.f.x.v v2, v2
 
-vfwcvt.f.x.v v2, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwcvt.f.x.v v2, v3
-
 vfwcvt.f.f.v v0, v2, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vfwcvt.f.f.v v0, v2, v0.t
 
 vfwcvt.f.f.v v2, v2
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vfwcvt.f.f.v v2, v2
 
-vfwcvt.f.f.v v2, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwcvt.f.f.v v2, v3
-
 vslideup.vx v0, v2, a0, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vslideup.vx v0, v2, a0, v0.t
 
 vslideup.vx v2, v2, a0
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vslideup.vx v2, v2, a0
 

 vslide1up.vx v2, v2, a0
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vslide1up.vx v2, v2, a0
 
 vnsrl.wv v2, v2, v4
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vnsrl.wv v2, v2, v4
 
-vnsrl.wv v3, v2, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vnsrl.wv v3, v2, v4
-
 vnsrl.wx v2, v2, a0
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vnsrl.wx v2, v2, a0
 
 vnsrl.wi v2, v2, 31
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vnsrl.wi v2, v2, 31
 
 vnsra.wv v2, v2, v4
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vnsra.wv v2, v2, v4
 
-vnsra.wv v3, v2, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vnsra.wv v3, v2, v4
-
 vnsra.wx v2, v2, a0
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vnsra.wx v2, v2, a0
 
 vnsra.wi v2, v2, 31
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vnsra.wi v2, v2, 31
 
 vnclipu.wv v2, v2, v4
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vnclipu.wv v2, v2, v4
 
-vnclipu.wv v3, v2, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vnclipu.wv v3, v2, v4
-
 vnclipu.wx v2, v2, a0
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vnclipu.wx v2, v2, a0
 
 vnclipu.wi v2, v2, 31
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vnclipu.wi v2, v2, 31
 
 vnclip.wv v2, v2, v4
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vnclip.wv v2, v2, v4
 
-vnclip.wv v3, v2, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vnclip.wv v3, v2, v4
-
 vnclip.wx v2, v2, a0
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vnclip.wx v2, v2, a0
 
 vnclip.wi v2, v2, 31
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vnclip.wi v2, v2, 31
 
 vfncvt.xu.f.w v2, v2
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vfncvt.xu.f.w v2, v2
 
-vfncvt.xu.f.w v3, v2
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfncvt.xu.f.w v3, v2
-
 vfncvt.x.f.w v2, v2
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vfncvt.x.f.w v2, v2
 
-vfncvt.x.f.w v3, v2
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfncvt.x.f.w v3, v2
-
 vfncvt.f.xu.w v2, v2
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vfncvt.f.xu.w v2, v2
 
-vfncvt.f.xu.w v3, v2
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfncvt.f.xu.w v3, v2
-
 vfncvt.f.x.w v2, v2
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vfncvt.f.x.w v2, v2
 
-vfncvt.f.x.w v3, v2
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfncvt.f.x.w v3, v2
-
 vfncvt.f.f.w v2, v2
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vfncvt.f.f.w v2, v2
 
-vfncvt.f.f.w v3, v2
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfncvt.f.f.w v3, v2
-
 vfncvt.rod.f.f.w v2, v2
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vfncvt.rod.f.f.w v2, v2
 
-vfncvt.rod.f.f.w v3, v2
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfncvt.rod.f.f.w v3, v2
-
 vrgather.vv v0, v2, v4, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vrgather.vv v0, v2, v4, v0.t
 
 vrgather.vv v2, v2, v4
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vrgather.vv v2, v2, v4
 

 vwaddu.vv v0, v2, v4, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vwaddu.vv v0, v2, v4, v0.t
 
 vwaddu.vv v2, v2, v4
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vwaddu.vv v2, v2, v4
 
-vwaddu.vv v2, v3, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwaddu.vv v2, v3, v4
-
 vwsubu.vv v0, v2, v4, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vwsubu.vv v0, v2, v4, v0.t
 
 vwsubu.vv v2, v2, v4
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vwsubu.vv v2, v2, v4
 
-vwsubu.vv v2, v3, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwsubu.vv v2, v3, v4
-
 vwadd.vv v0, v2, v4, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vwadd.vv v0, v2, v4, v0.t
 
 vwadd.vv v2, v2, v4
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vwadd.vv v2, v2, v4
 
-vwadd.vv v2, v3, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwadd.vv v2, v3, v4
-
 vwsub.vv v0, v2, v4, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vwsub.vv v0, v2, v4, v0.t
 
 vwsub.vv v2, v2, v4
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vwsub.vv v2, v2, v4
 
-vwsub.vv v2, v3, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwsub.vv v2, v3, v4
-
 vwmul.vv v0, v2, v4, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vwmul.vv v0, v2, v4, v0.t
 
 vwmul.vv v2, v2, v4
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vwmul.vv v2, v2, v4
 
-vwmul.vv v2, v3, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwmul.vv v2, v3, v4
-
 vwmulu.vv v0, v2, v4, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vwmulu.vv v0, v2, v4, v0.t
 
 vwmulu.vv v2, v2, v4
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vwmulu.vv v2, v2, v4
 
-vwmulu.vv v2, v3, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwmulu.vv v2, v3, v4
-
 vwmulsu.vv v0, v2, v4, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vwmulsu.vv v0, v2, v4, v0.t
 
 vwmulsu.vv v2, v2, v4
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vwmulsu.vv v2, v2, v4
 
-vwmulsu.vv v2, v3, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwmulsu.vv v2, v3, v4
-
 vwmaccu.vv v0, v4, v2, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vwmaccu.vv v0, v4, v2, v0.t
 
 vwmaccu.vv v2, v4, v2
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vwmaccu.vv v2, v4, v2
 
-vwmaccu.vv v2, v4, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwmaccu.vv v2, v4, v3
-
 vwmacc.vv v0, v4, v2, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vwmacc.vv v0, v4, v2, v0.t
 
 vwmacc.vv v2, v4, v2
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vwmacc.vv v2, v4, v2
 
-vwmacc.vv v2, v4, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwmacc.vv v2, v4, v3
-
 vwmaccsu.vv v0, v4, v2, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vwmaccsu.vv v0, v4, v2, v0.t
 
 vwmaccsu.vv v2, v4, v2
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vwmaccsu.vv v2, v4, v2
 
-vwmaccsu.vv v2, v4, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwmaccsu.vv v2, v4, v3
-
 vfwadd.vv v0, v2, v4, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vfwadd.vv v0, v2, v4, v0.t
 
 vfwadd.vv v2, v2, v4
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vfwadd.vv v2, v2, v4
 
-vfwadd.vv v2, v3, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwadd.vv v2, v3, v4
-
 vfwsub.vv v0, v2, v4, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vfwsub.vv v0, v2, v4, v0.t
 
 vfwsub.vv v2, v2, v4
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vfwsub.vv v2, v2, v4
 
-vfwsub.vv v2, v3, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwsub.vv v2, v3, v4
-
 vfwmul.vv v0, v2, v4, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vfwmul.vv v0, v2, v4, v0.t
 
 vfwmul.vv v2, v2, v4
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vfwmul.vv v2, v2, v4
 
-vfwmul.vv v2, v3, v4
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwmul.vv v2, v3, v4
-
 vfwmacc.vv v0, v4, v2, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vfwmacc.vv v0, v4, v2, v0.t
 
 vfwmacc.vv v2, v4, v2
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vfwmacc.vv v2, v4, v2
 
-vfwmacc.vv v2, v4, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwmacc.vv v2, v4, v3
-
 vfwnmacc.vv v0, v4, v2, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vfwnmacc.vv v0, v4, v2, v0.t
 
 vfwnmacc.vv v2, v4, v2
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vfwnmacc.vv v2, v4, v2
 
-vfwnmacc.vv v2, v4, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwnmacc.vv v2, v4, v3
-
 vfwmsac.vv v0, v4, v2, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vfwmsac.vv v0, v4, v2, v0.t
 
 vfwmsac.vv v2, v4, v2
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vfwmsac.vv v2, v4, v2
 
-vfwmsac.vv v2, v4, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwmsac.vv v2, v4, v3
-
 vfwnmsac.vv v0, v4, v2, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vfwnmsac.vv v0, v4, v2, v0.t
 
 vfwnmsac.vv v2, v4, v2
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vfwnmsac.vv v2, v4, v2
 
-vfwnmsac.vv v2, v4, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwnmsac.vv v2, v4, v3
-
 vwaddu.vx v0, v2, a0, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vwaddu.vx v0, v2, a0, v0.t
 
 vwaddu.vx v2, v2, a0
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vwaddu.vx v2, v2, a0
 
-vwaddu.vx v2, v3, a0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwaddu.vx v2, v3, a0
-
 vwsubu.vx v0, v2, a0, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vwsubu.vx v0, v2, a0, v0.t
 
 vwsubu.vx v2, v2, a0
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vwsubu.vx v2, v2, a0
 
-vwsubu.vx v2, v3, a0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwsubu.vx v2, v3, a0
-
 vwadd.vx v0, v2, a0, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vwadd.vx v0, v2, a0, v0.t
 
 vwadd.vx v2, v2, a0
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vwadd.vx v2, v2, a0
 
-vwadd.vx v2, v3, a0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwadd.vx v2, v3, a0
-
 vwsub.vx v0, v2, a0, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vwsub.vx v0, v2, a0, v0.t
 
 vwsub.vx v2, v2, a0
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vwsub.vx v2, v2, a0
 
-vwsub.vx v2, v3, a0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwsub.vx v2, v3, a0
-
 vwmul.vx v0, v2, a0, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vwmul.vx v0, v2, a0, v0.t
 
 vwmul.vx v2, v2, a0
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vwmul.vx v2, v2, a0
 
-vwmul.vx v2, v3, a0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwmul.vx v2, v3, a0
-
 vwmulu.vx v0, v2, a0, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vwmulu.vx v0, v2, a0, v0.t
 
 vwmulu.vx v2, v2, a0
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vwmulu.vx v2, v2, a0
 
-vwmulu.vx v2, v3, a0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwmulu.vx v2, v3, a0
-
 vwmulsu.vx v0, v2, a0, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vwmulsu.vx v0, v2, a0, v0.t
 
 vwmulsu.vx v2, v2, a0
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vwmulsu.vx v2, v2, a0
 
-vwmulsu.vx v2, v3, a0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwmulsu.vx v2, v3, a0
-
 vwmaccu.vx v0, a0, v2, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vwmaccu.vx v0, a0, v2, v0.t
 
 vwmaccu.vx v2, a0, v2
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vwmaccu.vx v2, a0, v2
 
-vwmaccu.vx v2, a0, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwmaccu.vx v2, a0, v3
-
 vwmacc.vx v0, a0, v2, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vwmacc.vx v0, a0, v2, v0.t
 
 vwmacc.vx v2, a0, v2
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vwmacc.vx v2, a0, v2
 
-vwmacc.vx v2, a0, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwmacc.vx v2, a0, v3
-
 vwmaccsu.vx v0, a0, v2, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vwmaccsu.vx v0, a0, v2, v0.t
 
 vwmaccsu.vx v2, a0, v2
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vwmaccsu.vx v2, a0, v2
 
-vwmaccsu.vx v2, a0, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwmaccsu.vx v2, a0, v3
-
 vwmaccus.vx v0, a0, v2, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vwmaccus.vx v0, a0, v2, v0.t
 
 vwmaccus.vx v2, a0, v2
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vwmaccus.vx v2, a0, v2
 
-vwmaccus.vx v2, a0, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwmaccus.vx v2, a0, v3
-
 vfwadd.vf v0, v2, fa0, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vfwadd.vf v0, v2, fa0, v0.t
 
 vfwadd.vf v2, v2, fa0
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vfwadd.vf v2, v2, fa0
 
-vfwadd.vf v2, v3, fa0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwadd.vf v2, v3, fa0
-
 vfwsub.vf v0, v2, fa0, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vfwsub.vf v0, v2, fa0, v0.t
 
 vfwsub.vf v2, v2, fa0
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vfwsub.vf v2, v2, fa0
 
-vfwsub.vf v2, v3, fa0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwsub.vf v2, v3, fa0
-
 vfwmul.vf v0, v2, fa0, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vfwmul.vf v0, v2, fa0, v0.t
 
 vfwmul.vf v2, v2, fa0
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vfwmul.vf v2, v2, fa0
 
-vfwmul.vf v2, v3, fa0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwmul.vf v2, v3, fa0
-
 vfwmacc.vf v0, fa0, v2, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vfwmacc.vf v0, fa0, v2, v0.t
 
 vfwmacc.vf v2, fa0, v2
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vfwmacc.vf v2, fa0, v2
 
-vfwmacc.vf v2, fa0, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwmacc.vf v2, fa0, v3
-
 vfwnmacc.vf v0, fa0, v2, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vfwnmacc.vf v0, fa0, v2, v0.t
 
 vfwnmacc.vf v2, fa0, v2
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vfwnmacc.vf v2, fa0, v2
 
-vfwnmacc.vf v2, fa0, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwnmacc.vf v2, fa0, v3
-
 vfwmsac.vf v0, fa0, v2, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vfwmsac.vf v0, fa0, v2, v0.t
 
 vfwmsac.vf v2, fa0, v2
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vfwmsac.vf v2, fa0, v2
 
-vfwmsac.vf v2, fa0, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwmsac.vf v2, fa0, v3
-
 vfwnmsac.vf v0, fa0, v2, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vfwnmsac.vf v0, fa0, v2, v0.t
 
 vfwnmsac.vf v2, fa0, v2
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vfwnmsac.vf v2, fa0, v2
 
-vfwnmsac.vf v2, fa0, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwnmsac.vf v2, fa0, v3
-
 vcompress.vm v2, v2, v4
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vcompress.vm v2, v2, v4
 
 vwaddu.wv v0, v2, v4, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vwaddu.wv v0, v2, v4, v0.t
 
 vwaddu.wv v2, v4, v2
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vwaddu.wv v2, v4, v2
 
-vwaddu.wv v2, v4, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwaddu.wv v2, v4, v3
-
 vwsubu.wv v0, v2, v4, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vwsubu.wv v0, v2, v4, v0.t
 
 vwsubu.wv v2, v4, v2
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vwsubu.wv v2, v4, v2
 
-vwsubu.wv v2, v4, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwsubu.wv v2, v4, v3
-
 vwadd.wv v0, v2, v4, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vwadd.wv v0, v2, v4, v0.t
 
 vwadd.wv v2, v4, v2
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vwadd.wv v2, v4, v2
 
-vwadd.wv v2, v4, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwadd.wv v2, v4, v3
-
 vwsub.wv v0, v2, v4, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vwsub.wv v0, v2, v4, v0.t
 
 vwsub.wv v2, v4, v2
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vwsub.wv v2, v4, v2
 
-vwsub.wv v2, v4, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vwsub.wv v2, v4, v3
-
 vfwadd.wv v0, v2, v4, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vfwadd.wv v0, v2, v4, v0.t
 
 vfwadd.wv v2, v4, v2
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vfwadd.wv v2, v4, v2
 
-vfwadd.wv v2, v4, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwadd.wv v2, v4, v3
-
 vfwsub.wv v0, v2, v4, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vfwsub.wv v0, v2, v4, v0.t
 
 vfwsub.wv v2, v4, v2
 # CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
 # CHECK-ERROR-LABEL: vfwsub.wv v2, v4, v2
 
-vfwsub.wv v2, v4, v3
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vfwsub.wv v2, v4, v3
-
 vwaddu.wx v0, v2, a0, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vwaddu.wx v0, v2, a0, v0.t
 
 vwsubu.wx v0, v2, a0, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vwsubu.wx v0, v2, a0, v0.t
 
 vwadd.wx v0, v2, a0, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vwadd.wx v0, v2, a0, v0.t
 
 vwsub.wx v0, v2, a0, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vwsub.wx v0, v2, a0, v0.t
 
 vfwadd.wf v0, v2, fa0, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vfwadd.wf v0, v2, fa0, v0.t
 
 vfwsub.wf v0, v2, fa0, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vfwsub.wf v0, v2, fa0, v0.t
+
+vadc.vvm v0, v2, v4, v0
+# CHECK-ERROR: The destination vector register group cannot be V0.
+# CHECK-ERROR-LABEL: vadc.vvm v0, v2, v4, v0
+
+vmadc.vvm v2, v2, v4, v0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vmadc.vvm v2, v2, v4, v0
+
+vmadc.vvm v4, v2, v4, v0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vmadc.vvm v4, v2, v4, v0
+
+vadd.vv v0, v2, v4, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vadd.vv v0, v2, v4, v0.t
+
+vadd.vx v0, v2, a0, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vadd.vx v0, v2, a0, v0.t
+
+vadd.vi v0, v2, 1, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vadd.vi v0, v2, 1, v0.t

llvm/test/MC/RISCV/rvv/load.s

 # RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
 # RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
 # RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
 # RUN:        | llvm-objdump -d --mattr=+experimental-v - \
 # RUN:        | FileCheck %s --check-prefix=CHECK-INST
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
 # RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
-vlb.v v8, (a0), v0.t
-# CHECK-INST: vlb.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x10]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 04 05 10 <unknown>
-
-vlb.v v8, (a0)
-# CHECK-INST: vlb.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x12]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 04 05 12 <unknown>
-
-vlh.v v8, (a0), v0.t
-# CHECK-INST: vlh.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x10]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 54 05 10 <unknown>
-
-vlh.v v8, (a0)
-# CHECK-INST: vlh.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x12]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 54 05 12 <unknown>
-
-vlw.v v8, (a0), v0.t
-# CHECK-INST: vlw.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x10]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 64 05 10 <unknown>
-
-vlw.v v8, (a0)
-# CHECK-INST: vlw.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x12]
-# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 64 05 12 <unknown>
-
-vlbu.v v8, (a0), v0.t
-# CHECK-INST: vlbu.v v8, (a0), v0.t
+vle8.v v8, (a0), v0.t
+# CHECK-INST: vle8.v v8, (a0), v0.t
 # CHECK-ENCODING: [0x07,0x04,0x05,0x00]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 04 05 00 <unknown>
 
-vlbu.v v8, (a0)
-# CHECK-INST: vlbu.v v8, (a0)
+vle8.v v8, (a0)
+# CHECK-INST: vle8.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x04,0x05,0x02]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 04 05 02 <unknown>
 
-vlhu.v v8, (a0), v0.t
-# CHECK-INST: vlhu.v v8, (a0), v0.t
+vle16.v v8, (a0), v0.t
+# CHECK-INST: vle16.v v8, (a0), v0.t
 # CHECK-ENCODING: [0x07,0x54,0x05,0x00]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 54 05 00 <unknown>
 
-vlhu.v v8, (a0)
-# CHECK-INST: vlhu.v v8, (a0)
+vle16.v v8, (a0)
+# CHECK-INST: vle16.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x54,0x05,0x02]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 54 05 02 <unknown>
 
-vlwu.v v8, (a0), v0.t
-# CHECK-INST: vlwu.v v8, (a0), v0.t
+vle32.v v8, (a0), v0.t
+# CHECK-INST: vle32.v v8, (a0), v0.t
 # CHECK-ENCODING: [0x07,0x64,0x05,0x00]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 64 05 00 <unknown>
 
-vlwu.v v8, (a0)
-# CHECK-INST: vlwu.v v8, (a0)
+vle32.v v8, (a0)
+# CHECK-INST: vle32.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x64,0x05,0x02]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 64 05 02 <unknown>
 
-vlbff.v v8, (a0), v0.t
-# CHECK-INST: vlbff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x04,0x05,0x11]
+vle64.v v8, (a0), v0.t
+# CHECK-INST: vle64.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x00]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 04 05 11 <unknown>
+# CHECK-UNKNOWN: 07 74 05 00 <unknown>
 
-vlbff.v v8, (a0)
-# CHECK-INST: vlbff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x04,0x05,0x13]
+vle64.v v8, (a0)
+# CHECK-INST: vle64.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x02]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 04 05 13 <unknown>
+# CHECK-UNKNOWN: 07 74 05 02 <unknown>
 
-vlhff.v v8, (a0), v0.t
-# CHECK-INST: vlhff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x54,0x05,0x11]
+vle128.v v8, (a0), v0.t
+# CHECK-INST: vle128.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x10]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 54 05 11 <unknown>
+# CHECK-UNKNOWN: 07 04 05 10 <unknown>
 
-vlhff.v v8, (a0)
-# CHECK-INST: vlhff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x54,0x05,0x13]
+vle128.v v8, (a0)
+# CHECK-INST: vle128.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x12]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 54 05 13 <unknown>
+# CHECK-UNKNOWN: 07 04 05 12 <unknown>
 
-vlwff.v v8, (a0), v0.t
-# CHECK-INST: vlwff.v v8, (a0), v0.t
-# CHECK-ENCODING: [0x07,0x64,0x05,0x11]
+vle256.v v8, (a0), v0.t
+# CHECK-INST: vle256.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x10]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 64 05 11 <unknown>
+# CHECK-UNKNOWN: 07 54 05 10 <unknown>
 
-vlwff.v v8, (a0)
-# CHECK-INST: vlwff.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x64,0x05,0x13]
+vle256.v v8, (a0)
+# CHECK-INST: vle256.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x12]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 64 05 13 <unknown>
+# CHECK-UNKNOWN: 07 54 05 12 <unknown>
 
-vlbuff.v v8, (a0), v0.t
-# CHECK-INST: vlbuff.v v8, (a0), v0.t
+vle512.v v8, (a0), v0.t
+# CHECK-INST: vle512.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x10]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 05 10 <unknown>
+
+vle512.v v8, (a0)
+# CHECK-INST: vle512.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 05 12 <unknown>
+
+vle1024.v v8, (a0), v0.t
+# CHECK-INST: vle1024.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x10]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 05 10 <unknown>
+
+vle1024.v v8, (a0)
+# CHECK-INST: vle1024.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 05 12 <unknown>
+
+vle8ff.v v8, (a0), v0.t
+# CHECK-INST: vle8ff.v v8, (a0), v0.t
 # CHECK-ENCODING: [0x07,0x04,0x05,0x01]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 04 05 01 <unknown>
 
-vlbuff.v v8, (a0)
-# CHECK-INST: vlbuff.v v8, (a0)
+vle8ff.v v8, (a0)
+# CHECK-INST: vle8ff.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x04,0x05,0x03]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 04 05 03 <unknown>
 
-vlhuff.v v8, (a0), v0.t
-# CHECK-INST: vlhuff.v v8, (a0), v0.t
+vle16ff.v v8, (a0), v0.t
+# CHECK-INST: vle16ff.v v8, (a0), v0.t
 # CHECK-ENCODING: [0x07,0x54,0x05,0x01]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 54 05 01 <unknown>
 
-vlhuff.v v8, (a0)
-# CHECK-INST: vlhuff.v v8, (a0)
+vle16ff.v v8, (a0)
+# CHECK-INST: vle16ff.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x54,0x05,0x03]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 54 05 03 <unknown>
 
-vlwuff.v v8, (a0), v0.t
-# CHECK-INST: vlwuff.v v8, (a0), v0.t
+vle32ff.v v8, (a0), v0.t
+# CHECK-INST: vle32ff.v v8, (a0), v0.t
 # CHECK-ENCODING: [0x07,0x64,0x05,0x01]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 64 05 01 <unknown>
 
-vlwuff.v v8, (a0)
-# CHECK-INST: vlwuff.v v8, (a0)
+vle32ff.v v8, (a0)
+# CHECK-INST: vle32ff.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x64,0x05,0x03]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 64 05 03 <unknown>
 
-vleff.v v8, (a0), v0.t
-# CHECK-INST: vleff.v v8, (a0), v0.t
+vle64ff.v v8, (a0), v0.t
+# CHECK-INST: vle64ff.v v8, (a0), v0.t
 # CHECK-ENCODING: [0x07,0x74,0x05,0x01]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 74 05 01 <unknown>
 
-vleff.v v8, (a0)
-# CHECK-INST: vleff.v v8, (a0)
+vle64ff.v v8, (a0)
+# CHECK-INST: vle64ff.v v8, (a0)
 # CHECK-ENCODING: [0x07,0x74,0x05,0x03]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 74 05 03 <unknown>
 
-vlsb.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsb.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x18]
+vle128ff.v v8, (a0), v0.t
+# CHECK-INST: vle128ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x11]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 04 b5 18 <unknown>
+# CHECK-UNKNOWN: 07 04 05 11 <unknown>
 
-vlsb.v v8, (a0), a1
-# CHECK-INST: vlsb.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x04,0xb5,0x1a]
+vle128ff.v v8, (a0)
+# CHECK-INST: vle128ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x13]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 04 b5 1a <unknown>
+# CHECK-UNKNOWN: 07 04 05 13 <unknown>
 
-vlsh.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsh.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x18]
+vle256ff.v v8, (a0), v0.t
+# CHECK-INST: vle256ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x11]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 54 b5 18 <unknown>
+# CHECK-UNKNOWN: 07 54 05 11 <unknown>
 
-vlsh.v v8, (a0), a1
-# CHECK-INST: vlsh.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x54,0xb5,0x1a]
+vle256ff.v v8, (a0)
+# CHECK-INST: vle256ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x13]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 54 b5 1a <unknown>
+# CHECK-UNKNOWN: 07 54 05 13 <unknown>
 
-vlsw.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsw.v v8, (a0), a1, v0.t
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x18]
+vle512ff.v v8, (a0), v0.t
+# CHECK-INST: vle512ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x11]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 64 b5 18 <unknown>
+# CHECK-UNKNOWN: 07 64 05 11 <unknown>
 
-vlsw.v v8, (a0), a1
-# CHECK-INST: vlsw.v v8, (a0), a1
-# CHECK-ENCODING: [0x07,0x64,0xb5,0x1a]
+vle512ff.v v8, (a0)
+# CHECK-INST: vle512ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x13]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 64 b5 1a <unknown>
+# CHECK-UNKNOWN: 07 64 05 13 <unknown>
+
+vle1024ff.v v8, (a0), v0.t
+# CHECK-INST: vle1024ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x11]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 05 11 <unknown>
+
+vle1024ff.v v8, (a0)
+# CHECK-INST: vle1024ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x13]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 05 13 <unknown>
 
-vlsbu.v v8, (a0), a1, v0.t
-# CHECK-INST: vlsbu.v v8, (a0), a1, v0.t
+vlse8.v v8, (a0), a1, v0.t
+# CHECK-INST: vlse8.v v8, (a0), a1, v0.t
 # CHECK-ENCODING: [0x07,0x04,0xb5,0x08]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 04 b5 08 <unknown>
 
-vlsbu.v v8, (a0), a1
-# CHECK-INST: vlsbu.v v8, (a0), a1
+vlse8.v v8, (a0), a1
+# CHECK-INST: vlse8.v v8, (a0), a1
 # CHECK-ENCODING: [0x07,0x04,0xb5,0x0a]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 04 b5 0a <unknown>
 
-vlshu.v v8, (a0), a1, v0.t
-# CHECK-INST: vlshu.v v8, (a0), a1, v0.t
+vlse16.v v8, (a0), a1, v0.t
+# CHECK-INST: vlse16.v v8, (a0), a1, v0.t
 # CHECK-ENCODING: [0x07,0x54,0xb5,0x08]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 54 b5 08 <unknown>
 
-vlshu.v v8, (a0), a1
-# CHECK-INST: vlshu.v v8, (a0), a1
+vlse16.v v8, (a0), a1
+# CHECK-INST: vlse16.v v8, (a0), a1
 # CHECK-ENCODING: [0x07,0x54,0xb5,0x0a]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 54 b5 0a <unknown>
 
-vlswu.v v8, (a0), a1, v0.t
-# CHECK-INST: vlswu.v v8, (a0), a1, v0.t
+vlse32.v v8, (a0), a1, v0.t
+# CHECK-INST: vlse32.v v8, (a0), a1, v0.t
 # CHECK-ENCODING: [0x07,0x64,0xb5,0x08]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 64 b5 08 <unknown>
 
-vlswu.v v8, (a0), a1
-# CHECK-INST: vlswu.v v8, (a0), a1
+vlse32.v v8, (a0), a1
+# CHECK-INST: vlse32.v v8, (a0), a1
 # CHECK-ENCODING: [0x07,0x64,0xb5,0x0a]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 64 b5 0a <unknown>
 
-vlse.v v8, (a0), a1, v0.t
-# CHECK-INST: vlse.v v8, (a0), a1, v0.t
+vlse64.v v8, (a0), a1, v0.t
+# CHECK-INST: vlse64.v v8, (a0), a1, v0.t
 # CHECK-ENCODING: [0x07,0x74,0xb5,0x08]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 74 b5 08 <unknown>
 
-vlse.v v8, (a0), a1
-# CHECK-INST: vlse.v v8, (a0), a1
+vlse64.v v8, (a0), a1
+# CHECK-INST: vlse64.v v8, (a0), a1
 # CHECK-ENCODING: [0x07,0x74,0xb5,0x0a]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 74 b5 0a <unknown>
 
-vlxb.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxb.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x04,0x45,0x1c]
+vlse128.v v8, (a0), a1, v0.t
+# CHECK-INST: vlse128.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x18]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 04 45 1c <unknown>
+# CHECK-UNKNOWN: 07 04 b5 18 <unknown>
 
-vlxb.v v8, (a0), v4
-# CHECK-INST: vlxb.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x04,0x45,0x1e]
+vlse128.v v8, (a0), a1
+# CHECK-INST: vlse128.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x1a]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 04 45 1e <unknown>
+# CHECK-UNKNOWN: 07 04 b5 1a <unknown>
 
-vlxh.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxh.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x54,0x45,0x1c]
+vlse256.v v8, (a0), a1, v0.t
+# CHECK-INST: vlse256.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x18]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 54 45 1c <unknown>
+# CHECK-UNKNOWN: 07 54 b5 18 <unknown>
 
-vlxh.v v8, (a0), v4
-# CHECK-INST: vlxh.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x54,0x45,0x1e]
+vlse256.v v8, (a0), a1
+# CHECK-INST: vlse256.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x1a]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 54 45 1e <unknown>
+# CHECK-UNKNOWN: 07 54 b5 1a <unknown>
 
-vlxw.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxw.v v8, (a0), v4, v0.t
-# CHECK-ENCODING: [0x07,0x64,0x45,0x1c]
+vlse512.v v8, (a0), a1, v0.t
+# CHECK-INST: vlse512.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x18]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 64 45 1c <unknown>
+# CHECK-UNKNOWN: 07 64 b5 18 <unknown>
 
-vlxw.v v8, (a0), v4
-# CHECK-INST: vlxw.v v8, (a0), v4
-# CHECK-ENCODING: [0x07,0x64,0x45,0x1e]
+vlse512.v v8, (a0), a1
+# CHECK-INST: vlse512.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x1a]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 64 45 1e <unknown>
+# CHECK-UNKNOWN: 07 64 b5 1a <unknown>
+
+vlse1024.v v8, (a0), a1, v0.t
+# CHECK-INST: vlse1024.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x18]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 b5 18 <unknown>
 
-vlxbu.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxbu.v v8, (a0), v4, v0.t
+vlse1024.v v8, (a0), a1
+# CHECK-INST: vlse1024.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x1a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 b5 1a <unknown>
+
+vlxei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxei8.v v8, (a0), v4, v0.t
 # CHECK-ENCODING: [0x07,0x04,0x45,0x0c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 04 45 0c <unknown>
 
-vlxbu.v v8, (a0), v4
-# CHECK-INST: vlxbu.v v8, (a0), v4
+vlxei8.v v8, (a0), v4
+# CHECK-INST: vlxei8.v v8, (a0), v4
 # CHECK-ENCODING: [0x07,0x04,0x45,0x0e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 04 45 0e <unknown>
 
-vlxhu.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxhu.v v8, (a0), v4, v0.t
+vlxei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxei16.v v8, (a0), v4, v0.t
 # CHECK-ENCODING: [0x07,0x54,0x45,0x0c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 54 45 0c <unknown>
 
-vlxhu.v v8, (a0), v4
-# CHECK-INST: vlxhu.v v8, (a0), v4
+vlxei16.v v8, (a0), v4
+# CHECK-INST: vlxei16.v v8, (a0), v4
 # CHECK-ENCODING: [0x07,0x54,0x45,0x0e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 54 45 0e <unknown>
 
-vlxwu.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxwu.v v8, (a0), v4, v0.t
+vlxei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxei32.v v8, (a0), v4, v0.t
 # CHECK-ENCODING: [0x07,0x64,0x45,0x0c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 64 45 0c <unknown>
 
-vlxwu.v v8, (a0), v4
-# CHECK-INST: vlxwu.v v8, (a0), v4
+vlxei32.v v8, (a0), v4
+# CHECK-INST: vlxei32.v v8, (a0), v4
 # CHECK-ENCODING: [0x07,0x64,0x45,0x0e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 64 45 0e <unknown>
 
-vlxe.v v8, (a0), v4, v0.t
-# CHECK-INST: vlxe.v v8, (a0), v4, v0.t
+vlxei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxei64.v v8, (a0), v4, v0.t
 # CHECK-ENCODING: [0x07,0x74,0x45,0x0c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 74 45 0c <unknown>
 
-vlxe.v v8, (a0), v4
-# CHECK-INST: vlxe.v v8, (a0), v4
+vlxei64.v v8, (a0), v4
+# CHECK-INST: vlxei64.v v8, (a0), v4
 # CHECK-ENCODING: [0x07,0x74,0x45,0x0e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 07 74 45 0e <unknown>
 
+vlxei128.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxei128.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 45 1c <unknown>
+
+vlxei128.v v8, (a0), v4
+# CHECK-INST: vlxei128.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x1e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 45 1e <unknown>
+
+vlxei256.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxei256.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 45 1c <unknown>
+
+vlxei256.v v8, (a0), v4
+# CHECK-INST: vlxei256.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x1e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 45 1e <unknown>
+
+vlxei512.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxei512.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 45 1c <unknown>
+
+vlxei512.v v8, (a0), v4
+# CHECK-INST: vlxei512.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x1e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 45 1e <unknown>
+
+vlxei1024.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxei1024.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 45 1c <unknown>
+
+vlxei1024.v v8, (a0), v4
+# CHECK-INST: vlxei1024.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x1e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 45 1e <unknown>
+
 vl1r.v v8, (a0)
 # CHECK-INST: vl1r.v v8, (a0)
-# CHECK-ENCODING: [0x07,0x74,0x85,0x02]
+# CHECK-ENCODING: [0x07,0x04,0x85,0x02]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 07 74 85 02 <unknown>
+# CHECK-UNKNOWN: 07 04 85 02 <unknown>

llvm/test/MC/RISCV/rvv/mask.s

 # CHECK-UNKNOWN: 57 a4 08 50 <unknown>
 
 vid.v v8
 # CHECK-INST: vid.v v8
 # CHECK-ENCODING: [0x57,0xa4,0x08,0x52]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 57 a4 08 52 <unknown>
 
-vmcpy.m v8, v4
-# CHECK-INST: vmcpy.m v8, v4
+vmmv.m v8, v4
+# CHECK-INST: vmmv.m v8, v4
 # CHECK-ENCODING: [0x57,0x24,0x42,0x66]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 57 24 42 66 <unknown>
 
 vmclr.m v8
 # CHECK-INST: vmclr.m v8
 # CHECK-ENCODING: [0x57,0x24,0x84,0x6e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)

llvm/test/MC/RISCV/rvv/snippet.s

 ## A snippet from https://github.com/riscv/riscv-v-spec.
 
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v < %s \
 # RUN: | llvm-objdump -d --mattr=+experimental-v - \
 # RUN: | FileCheck %s --check-prefix=CHECK-INST
 
 loop:
-    vsetvli a3, a0, e16,m4  # vtype = 16-bit integer vectors
-# CHECK-INST: d7 76 65 00    vsetvli a3, a0, e16,m4
-    vlh.v v4, (a1)          # Get 16b vector
-# CHECK-INST: 07 d2 05 12    vlh.v   v4, (a1)
-    slli t1, a3, 1          # Multiply length by two bytes/element
+    vsetvli a3, a0, e16,m4,ta,ma  # vtype = 16-bit integer vectors
+# CHECK-INST: d7 76 65 0c    vsetvli a3, a0, e16,m4,ta,ma
+    vle16.v v4, (a1)              # Get 16b vector
+# CHECK-INST: 07 d2 05 02    vle16.v   v4, (a1)
+    slli t1, a3, 1                # Multiply length by two bytes/element
 # CHECK-INST: 13 93 16 00    slli    t1, a3, 1
-    add a1, a1, t1          # Bump pointer
+    add a1, a1, t1                # Bump pointer
 # CHECK-INST: b3 85 65 00    add     a1, a1, t1
-    vwmul.vx v8, v4, x10    # 32b in <v8--v15>
+    vwmul.vx v8, v4, x10          # 32b in <v8--v15>
 # CHECK-INST: 57 64 45 ee    vwmul.vx        v8, v4, a0
 
-    vsetvli x0, a0, e32,m8  # Operate on 32b values
-# CHECK-INST: 57 70 b5 00    vsetvli zero, a0, e32,m8
+    vsetvli x0, a0, e32,m8,ta,ma  # Operate on 32b values
+# CHECK-INST: 57 70 b5 0c    vsetvli zero, a0, e32,m8,ta,ma
     vsrl.vi v8, v8, 3
 # CHECK-INST: 57 b4 81 a2    vsrl.vi v8, v8, 3
-    vsw.v v8, (a2)          # Store vector of 32b
-# CHECK-INST: 27 64 06 02    vsw.v   v8, (a2)
-    slli t1, a3, 2          # Multiply length by four bytes/element
+    vse32.v v8, (a2)              # Store vector of 32b
+# CHECK-INST: 27 64 06 02    vse32.v   v8, (a2)
+    slli t1, a3, 2                # Multiply length by four bytes/element
 # CHECK-INST: 13 93 26 00    slli    t1, a3, 2
-    add a2, a2, t1          # Bump pointer
+    add a2, a2, t1                # Bump pointer
 # CHECK-INST: 33 06 66 00    add     a2, a2, t1
-    sub a0, a0, a3          # Decrement count
+    sub a0, a0, a3                # Decrement count
 # CHECK-INST: 33 05 d5 40    sub     a0, a0, a3
-    bnez a0, loop           # Any more?
+    bnez a0, loop                 # Any more?
 # CHECK-INST: e3 1a 05 fc    bnez    a0, -44

llvm/test/MC/RISCV/rvv/store.s

 # RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
 # RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
 # RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
 # RUN:        | llvm-objdump -d --mattr=+experimental-v - \
 # RUN:        | FileCheck %s --check-prefix=CHECK-INST
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
 # RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
-vsb.v v24, (a0), v0.t
-# CHECK-INST: vsb.v v24, (a0), v0.t
+vse8.v v24, (a0), v0.t
+# CHECK-INST: vse8.v v24, (a0), v0.t
 # CHECK-ENCODING: [0x27,0x0c,0x05,0x00]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 0c 05 00 <unknown>
 
-vsb.v v24, (a0)
-# CHECK-INST: vsb.v v24, (a0)
+vse8.v v24, (a0)
+# CHECK-INST: vse8.v v24, (a0)
 # CHECK-ENCODING: [0x27,0x0c,0x05,0x02]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 0c 05 02 <unknown>
 
-vsh.v v24, (a0), v0.t
-# CHECK-INST: vsh.v v24, (a0), v0.t
+vse16.v v24, (a0), v0.t
+# CHECK-INST: vse16.v v24, (a0), v0.t
 # CHECK-ENCODING: [0x27,0x5c,0x05,0x00]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 5c 05 00 <unknown>
 
-vsh.v v24, (a0)
-# CHECK-INST: vsh.v v24, (a0)
+vse16.v v24, (a0)
+# CHECK-INST: vse16.v v24, (a0)
 # CHECK-ENCODING: [0x27,0x5c,0x05,0x02]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 5c 05 02 <unknown>
 
-vsw.v v24, (a0), v0.t
-# CHECK-INST: vsw.v v24, (a0), v0.t
+vse32.v v24, (a0), v0.t
+# CHECK-INST: vse32.v v24, (a0), v0.t
 # CHECK-ENCODING: [0x27,0x6c,0x05,0x00]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 6c 05 00 <unknown>
 
-vsw.v v24, (a0)
-# CHECK-INST: vsw.v v24, (a0)
+vse32.v v24, (a0)
+# CHECK-INST: vse32.v v24, (a0)
 # CHECK-ENCODING: [0x27,0x6c,0x05,0x02]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 6c 05 02 <unknown>
 
-vse.v v24, (a0), v0.t
-# CHECK-INST: vse.v v24, (a0), v0.t
+vse64.v v24, (a0), v0.t
+# CHECK-INST: vse64.v v24, (a0), v0.t
 # CHECK-ENCODING: [0x27,0x7c,0x05,0x00]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 7c 05 00 <unknown>
 
-vse.v v24, (a0)
-# CHECK-INST: vse.v v24, (a0)
+vse64.v v24, (a0)
+# CHECK-INST: vse64.v v24, (a0)
 # CHECK-ENCODING: [0x27,0x7c,0x05,0x02]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 7c 05 02 <unknown>
 
-vssb.v v24, (a0), a1, v0.t
-# CHECK-INST: vssb.v v24, (a0), a1, v0.t
+vse128.v v24, (a0), v0.t
+# CHECK-INST: vse128.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x10]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 0c 05 10 <unknown>
+
+vse128.v v24, (a0)
+# CHECK-INST: vse128.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 0c 05 12 <unknown>
+
+vse256.v v24, (a0), v0.t
+# CHECK-INST: vse256.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x10]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 5c 05 10 <unknown>
+
+vse256.v v24, (a0)
+# CHECK-INST: vse256.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 5c 05 12 <unknown>
+
+vse512.v v24, (a0), v0.t
+# CHECK-INST: vse512.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x10]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 6c 05 10 <unknown>
+
+vse512.v v24, (a0)
+# CHECK-INST: vse512.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 6c 05 12 <unknown>
+
+vse1024.v v24, (a0), v0.t
+# CHECK-INST: vse1024.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x10]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 7c 05 10 <unknown>
+
+vse1024.v v24, (a0)
+# CHECK-INST: vse1024.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 7c 05 12 <unknown>
+
+vsse8.v v24, (a0), a1, v0.t
+# CHECK-INST: vsse8.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x0c,0xb5,0x08]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 0c b5 08 <unknown>
 
-vssb.v v24, (a0), a1
-# CHECK-INST: vssb.v v24, (a0), a1
+vsse8.v v24, (a0), a1
+# CHECK-INST: vsse8.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x0c,0xb5,0x0a]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 0c b5 0a <unknown>
 
-vssh.v v24, (a0), a1, v0.t
-# CHECK-INST: vssh.v v24, (a0), a1, v0.t
+vsse16.v v24, (a0), a1, v0.t
+# CHECK-INST: vsse16.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x5c,0xb5,0x08]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 5c b5 08 <unknown>
 
-vssh.v v24, (a0), a1
-# CHECK-INST: vssh.v v24, (a0), a1
+vsse16.v v24, (a0), a1
+# CHECK-INST: vsse16.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x5c,0xb5,0x0a]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 5c b5 0a <unknown>
 
-vssw.v v24, (a0), a1, v0.t
-# CHECK-INST: vssw.v v24, (a0), a1, v0.t
+vsse32.v v24, (a0), a1, v0.t
+# CHECK-INST: vsse32.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x6c,0xb5,0x08]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 6c b5 08 <unknown>
 
-vssw.v v24, (a0), a1
-# CHECK-INST: vssw.v v24, (a0), a1
+vsse32.v v24, (a0), a1
+# CHECK-INST: vsse32.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x6c,0xb5,0x0a]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 6c b5 0a <unknown>
 
-vsse.v v24, (a0), a1, v0.t
-# CHECK-INST: vsse.v v24, (a0), a1, v0.t
+vsse64.v v24, (a0), a1, v0.t
+# CHECK-INST: vsse64.v v24, (a0), a1, v0.t
 # CHECK-ENCODING: [0x27,0x7c,0xb5,0x08]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 7c b5 08 <unknown>
 
-vsse.v v24, (a0), a1
-# CHECK-INST: vsse.v v24, (a0), a1
+vsse64.v v24, (a0), a1
+# CHECK-INST: vsse64.v v24, (a0), a1
 # CHECK-ENCODING: [0x27,0x7c,0xb5,0x0a]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 7c b5 0a <unknown>
 
-vsxb.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxb.v v24, (a0), v4, v0.t
+vsse128.v v24, (a0), a1, v0.t
+# CHECK-INST: vsse128.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x18]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 0c b5 18 <unknown>
+
+vsse128.v v24, (a0), a1
+# CHECK-INST: vsse128.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x1a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 0c b5 1a <unknown>
+
+vsse256.v v24, (a0), a1, v0.t
+# CHECK-INST: vsse256.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x18]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 5c b5 18 <unknown>
+
+vsse256.v v24, (a0), a1
+# CHECK-INST: vsse256.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x1a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 5c b5 1a <unknown>
+
+vsse512.v v24, (a0), a1, v0.t
+# CHECK-INST: vsse512.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x18]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 6c b5 18 <unknown>
+
+vsse512.v v24, (a0), a1
+# CHECK-INST: vsse512.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x1a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 6c b5 1a <unknown>
+
+vsse1024.v v24, (a0), a1, v0.t
+# CHECK-INST: vsse1024.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x18]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 7c b5 18 <unknown>
+
+vsse1024.v v24, (a0), a1
+# CHECK-INST: vsse1024.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x1a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 7c b5 1a <unknown>
+
+vsxei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxei8.v v24, (a0), v4, v0.t
 # CHECK-ENCODING: [0x27,0x0c,0x45,0x0c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 0c 45 0c <unknown>
 
-vsxb.v v24, (a0), v4
-# CHECK-INST: vsxb.v v24, (a0), v4
+vsxei8.v v24, (a0), v4
+# CHECK-INST: vsxei8.v v24, (a0), v4
 # CHECK-ENCODING: [0x27,0x0c,0x45,0x0e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 0c 45 0e <unknown>
 
-vsxh.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxh.v v24, (a0), v4, v0.t
+vsxei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxei16.v v24, (a0), v4, v0.t
 # CHECK-ENCODING: [0x27,0x5c,0x45,0x0c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 5c 45 0c <unknown>
 
-vsxh.v v24, (a0), v4
-# CHECK-INST: vsxh.v v24, (a0), v4
+vsxei16.v v24, (a0), v4
+# CHECK-INST: vsxei16.v v24, (a0), v4
 # CHECK-ENCODING: [0x27,0x5c,0x45,0x0e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 5c 45 0e <unknown>
 
-vsxw.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxw.v v24, (a0), v4, v0.t
+vsxei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxei32.v v24, (a0), v4, v0.t
 # CHECK-ENCODING: [0x27,0x6c,0x45,0x0c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 6c 45 0c <unknown>
 
-vsxw.v v24, (a0), v4
-# CHECK-INST: vsxw.v v24, (a0), v4
+vsxei32.v v24, (a0), v4
+# CHECK-INST: vsxei32.v v24, (a0), v4
 # CHECK-ENCODING: [0x27,0x6c,0x45,0x0e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 6c 45 0e <unknown>
 
-vsxe.v v24, (a0), v4, v0.t
-# CHECK-INST: vsxe.v v24, (a0), v4, v0.t
+vsxei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxei64.v v24, (a0), v4, v0.t
 # CHECK-ENCODING: [0x27,0x7c,0x45,0x0c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 7c 45 0c <unknown>
 
-vsxe.v v24, (a0), v4
-# CHECK-INST: vsxe.v v24, (a0), v4
+vsxei64.v v24, (a0), v4
+# CHECK-INST: vsxei64.v v24, (a0), v4
 # CHECK-ENCODING: [0x27,0x7c,0x45,0x0e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 7c 45 0e <unknown>
 
-vsuxb.v v24, (a0), v4, v0.t
-# CHECK-INST: vsuxb.v v24, (a0), v4, v0.t
+vsxei128.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxei128.v v24, (a0), v4, v0.t
 # CHECK-ENCODING: [0x27,0x0c,0x45,0x1c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 0c 45 1c <unknown>
 
-vsuxb.v v24, (a0), v4
-# CHECK-INST: vsuxb.v v24, (a0), v4
+vsxei128.v v24, (a0), v4
+# CHECK-INST: vsxei128.v v24, (a0), v4
 # CHECK-ENCODING: [0x27,0x0c,0x45,0x1e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 0c 45 1e <unknown>
 
-vsuxh.v v24, (a0), v4, v0.t
-# CHECK-INST: vsuxh.v v24, (a0), v4, v0.t
+vsxei256.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxei256.v v24, (a0), v4, v0.t
 # CHECK-ENCODING: [0x27,0x5c,0x45,0x1c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 5c 45 1c <unknown>
 
-vsuxh.v v24, (a0), v4
-# CHECK-INST: vsuxh.v v24, (a0), v4
+vsxei256.v v24, (a0), v4
+# CHECK-INST: vsxei256.v v24, (a0), v4
 # CHECK-ENCODING: [0x27,0x5c,0x45,0x1e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 5c 45 1e <unknown>
 
-vsuxw.v v24, (a0), v4, v0.t
-# CHECK-INST: vsuxw.v v24, (a0), v4, v0.t
+vsxei512.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxei512.v v24, (a0), v4, v0.t
 # CHECK-ENCODING: [0x27,0x6c,0x45,0x1c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 6c 45 1c <unknown>
 
-vsuxw.v v24, (a0), v4
-# CHECK-INST: vsuxw.v v24, (a0), v4
+vsxei512.v v24, (a0), v4
+# CHECK-INST: vsxei512.v v24, (a0), v4
 # CHECK-ENCODING: [0x27,0x6c,0x45,0x1e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 6c 45 1e <unknown>
 
-vsuxe.v v24, (a0), v4, v0.t
-# CHECK-INST: vsuxe.v v24, (a0), v4, v0.t
+vsxei1024.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxei1024.v v24, (a0), v4, v0.t
 # CHECK-ENCODING: [0x27,0x7c,0x45,0x1c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 7c 45 1c <unknown>
 
-vsuxe.v v24, (a0), v4
-# CHECK-INST: vsuxe.v v24, (a0), v4
+vsxei1024.v v24, (a0), v4
+# CHECK-INST: vsxei1024.v v24, (a0), v4
 # CHECK-ENCODING: [0x27,0x7c,0x45,0x1e]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 27 7c 45 1e <unknown>
 
 vs1r.v v24, (a0)
 # CHECK-INST: vs1r.v v24, (a0)
-# CHECK-ENCODING: [0x27,0x7c,0x85,0x02]
+# CHECK-ENCODING: [0x27,0x0c,0x85,0x02]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 27 7c 85 02 <unknown>
+# CHECK-UNKNOWN: 27 0c 85 02 <unknown>

llvm/test/MC/RISCV/rvv/vsetvl.s

 # RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
 # RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 # RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
 # RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
 # RUN:        | llvm-objdump -d --mattr=+experimental-v - \
 # RUN:        | FileCheck %s --check-prefix=CHECK-INST
 # RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
 # RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
-vsetvli a2, a0, e32,m4
-# CHECK-INST: vsetvli a2, a0, e32,m4
-# CHECK-ENCODING: [0x57,0x76,0xa5,0x00]
+vsetvli a2, a0, e32,m1,ta,ma
+# CHECK-INST: vsetvli a2, a0, e32,m1,ta,ma
+# CHECK-ENCODING: [0x57,0x76,0x85,0x0c]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
-# CHECK-UNKNOWN: 57 76 a5 00 <unknown>
+# CHECK-UNKNOWN: 57 76 85 0c <unknown>
+
+vsetvli a2, a0, e32,m2,ta,ma
+# CHECK-INST: vsetvli a2, a0, e32,m2,ta,ma
+# CHECK-ENCODING: [0x57,0x76,0x95,0x0c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 95 0c <unknown>
+
+vsetvli a2, a0, e32,m4,ta,ma
+# CHECK-INST: vsetvli a2, a0, e32,m4,ta,ma
+# CHECK-ENCODING: [0x57,0x76,0xa5,0x0c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 a5 0c <unknown>
+
+vsetvli a2, a0, e32,m8,ta,ma
+# CHECK-INST: vsetvli a2, a0, e32,m8,ta,ma
+# CHECK-ENCODING: [0x57,0x76,0xb5,0x0c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 b5 0c <unknown>
+
+vsetvli a2, a0, e32,mf2,ta,ma
+# CHECK-INST: vsetvli a2, a0, e32,mf2,ta,ma
+# CHECK-ENCODING: [0x57,0x76,0xb5,0x0e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 b5 0e <unknown>
+
+vsetvli a2, a0, e32,mf4,ta,ma
+# CHECK-INST: vsetvli a2, a0, e32,mf4,ta,ma
+# CHECK-ENCODING: [0x57,0x76,0xa5,0x0e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 a5 0e <unknown>
+
+vsetvli a2, a0, e32,mf8,ta,ma
+# CHECK-INST: vsetvli a2, a0, e32,mf8,ta,ma
+# CHECK-ENCODING: [0x57,0x76,0x95,0x0e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 95 0e <unknown>
+
+vsetvli a2, a0, e32,m1,ta,ma
+# CHECK-INST: vsetvli a2, a0, e32,m1,ta,ma
+# CHECK-ENCODING: [0x57,0x76,0x85,0x0c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 0c <unknown>
+
+vsetvli a2, a0, e32,m1,tu,ma
+# CHECK-INST: vsetvli a2, a0, e32,m1,tu,ma
+# CHECK-ENCODING: [0x57,0x76,0x85,0x08]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 08 <unknown>
+
+vsetvli a2, a0, e32,m1,ta,mu
+# CHECK-INST: vsetvli a2, a0, e32,m1,ta,mu
+# CHECK-ENCODING: [0x57,0x76,0x85,0x04]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 04 <unknown>
+
+vsetvli a2, a0, e32,m1,tu,mu
+# CHECK-INST: vsetvli a2, a0, e32,m1
+# CHECK-ENCODING: [0x57,0x76,0x85,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 85 00 <unknown>
 
 vsetvl a2, a0, a1
 # CHECK-INST: vsetvl a2, a0, a1
 # CHECK-ENCODING: [0x57,0x76,0xb5,0x80]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
 # CHECK-UNKNOWN: 57 76 b5 80 <unknown>

llvm/test/MC/RISCV/rvv/zvlsseg.s

+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v,experimental-zvlsseg %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v,experimental-zvlsseg %s \
+# RUN:        | llvm-objdump -d --mattr=+experimental-v,experimental-zvlsseg - \
+# RUN:        | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v,experimental-zvlsseg %s \
+# RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vlseg2e8.v v8, (a0)
+# CHECK-INST: vlseg2e8.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x22]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 22 <unknown>
+
+vlseg2e16.v v8, (a0)
+# CHECK-INST: vlseg2e16.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x22]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 22 <unknown>
+
+vlseg2e32.v v8, (a0)
+# CHECK-INST: vlseg2e32.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x22]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 22 <unknown>
+
+vlseg2e64.v v8, (a0)
+# CHECK-INST: vlseg2e64.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x22]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 22 <unknown>
+
+vlseg2e128.v v8, (a0)
+# CHECK-INST: vlseg2e128.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x32]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 32 <unknown>
+
+vlseg2e256.v v8, (a0)
+# CHECK-INST: vlseg2e256.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x32]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 32 <unknown>
+
+vlseg2e512.v v8, (a0)
+# CHECK-INST: vlseg2e512.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x32]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 32 <unknown>
+
+vlseg2e1024.v v8, (a0)
+# CHECK-INST: vlseg2e1024.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x32]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 32 <unknown>
+
+vlseg2e8.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e8.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x20]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 20 <unknown>
+
+vlseg2e16.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e16.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x20]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 20 <unknown>
+
+vlseg2e32.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e32.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x20]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 20 <unknown>
+
+vlseg2e64.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e64.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x20]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 20 <unknown>
+
+vlseg2e128.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e128.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x30]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 30 <unknown>
+
+vlseg2e256.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e256.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x30]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 30 <unknown>
+
+vlseg2e512.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e512.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x30]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 30 <unknown>
+
+vlseg2e1024.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e1024.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x30]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 30 <unknown>
+
+vlseg3e8.v v8, (a0)
+# CHECK-INST: vlseg3e8.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 42 <unknown>
+
+vlseg3e16.v v8, (a0)
+# CHECK-INST: vlseg3e16.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 42 <unknown>
+
+vlseg3e32.v v8, (a0)
+# CHECK-INST: vlseg3e32.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 42 <unknown>
+
+vlseg3e64.v v8, (a0)
+# CHECK-INST: vlseg3e64.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 42 <unknown>
+
+vlseg3e128.v v8, (a0)
+# CHECK-INST: vlseg3e128.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x52]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 52 <unknown>
+
+vlseg3e256.v v8, (a0)
+# CHECK-INST: vlseg3e256.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x52]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 52 <unknown>
+
+vlseg3e512.v v8, (a0)
+# CHECK-INST: vlseg3e512.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x52]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 52 <unknown>
+
+vlseg3e1024.v v8, (a0)
+# CHECK-INST: vlseg3e1024.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x52]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 52 <unknown>
+
+vlseg3e8.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e8.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x40]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 40 <unknown>
+
+vlseg3e16.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e16.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x40]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 40 <unknown>
+
+vlseg3e32.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e32.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x40]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 40 <unknown>
+
+vlseg3e64.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e64.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x40]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 40 <unknown>
+
+vlseg3e128.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e128.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x50]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 50 <unknown>
+
+vlseg3e256.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e256.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x50]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 50 <unknown>
+
+vlseg3e512.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e512.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x50]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 50 <unknown>
+
+vlseg3e1024.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e1024.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x50]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 50 <unknown>
+
+vlseg4e8.v v8, (a0)
+# CHECK-INST: vlseg4e8.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x62]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 62 <unknown>
+
+vlseg4e16.v v8, (a0)
+# CHECK-INST: vlseg4e16.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x62]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 62 <unknown>
+
+vlseg4e32.v v8, (a0)
+# CHECK-INST: vlseg4e32.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x62]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 62 <unknown>
+
+vlseg4e64.v v8, (a0)
+# CHECK-INST: vlseg4e64.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x62]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 62 <unknown>
+
+vlseg4e128.v v8, (a0)
+# CHECK-INST: vlseg4e128.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x72]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 72 <unknown>
+
+vlseg4e256.v v8, (a0)
+# CHECK-INST: vlseg4e256.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x72]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 72 <unknown>
+
+vlseg4e512.v v8, (a0)
+# CHECK-INST: vlseg4e512.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x72]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 72 <unknown>
+
+vlseg4e1024.v v8, (a0)
+# CHECK-INST: vlseg4e1024.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x72]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 72 <unknown>
+
+vlseg4e8.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e8.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x60]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 60 <unknown>
+
+vlseg4e16.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e16.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x60]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 60 <unknown>
+
+vlseg4e32.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e32.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x60]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 60 <unknown>
+
+vlseg4e64.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e64.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x60]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 60 <unknown>
+
+vlseg4e128.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e128.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x70]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 70 <unknown>
+
+vlseg4e256.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e256.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x70]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 70 <unknown>
+
+vlseg4e512.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e512.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x70]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 70 <unknown>
+
+vlseg4e1024.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e1024.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x70]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 70 <unknown>
+
+vlseg5e8.v v8, (a0)
+# CHECK-INST: vlseg5e8.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x82]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 82 <unknown>
+
+vlseg5e16.v v8, (a0)
+# CHECK-INST: vlseg5e16.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x82]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 82 <unknown>
+
+vlseg5e32.v v8, (a0)
+# CHECK-INST: vlseg5e32.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x82]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 82 <unknown>
+
+vlseg5e64.v v8, (a0)
+# CHECK-INST: vlseg5e64.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x82]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 82 <unknown>
+
+vlseg5e128.v v8, (a0)
+# CHECK-INST: vlseg5e128.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x92]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 92 <unknown>
+
+vlseg5e256.v v8, (a0)
+# CHECK-INST: vlseg5e256.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x92]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 92 <unknown>
+
+vlseg5e512.v v8, (a0)
+# CHECK-INST: vlseg5e512.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x92]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 92 <unknown>
+
+vlseg5e1024.v v8, (a0)
+# CHECK-INST: vlseg5e1024.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x92]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 92 <unknown>
+
+vlseg5e8.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e8.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x80]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 80 <unknown>
+
+vlseg5e16.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e16.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x80]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 80 <unknown>
+
+vlseg5e32.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e32.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x80]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 80 <unknown>
+
+vlseg5e64.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e64.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x80]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 80 <unknown>
+
+vlseg5e128.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e128.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x90]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 90 <unknown>
+
+vlseg5e256.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e256.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x90]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 90 <unknown>
+
+vlseg5e512.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e512.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x90]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 90 <unknown>
+
+vlseg5e1024.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e1024.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x90]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 90 <unknown>
+
+vlseg6e8.v v8, (a0)
+# CHECK-INST: vlseg6e8.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xa2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 a2 <unknown>
+
+vlseg6e16.v v8, (a0)
+# CHECK-INST: vlseg6e16.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xa2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 a2 <unknown>
+
+vlseg6e32.v v8, (a0)
+# CHECK-INST: vlseg6e32.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xa2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 a2 <unknown>
+
+vlseg6e64.v v8, (a0)
+# CHECK-INST: vlseg6e64.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xa2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 a2 <unknown>
+
+vlseg6e128.v v8, (a0)
+# CHECK-INST: vlseg6e128.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xb2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 b2 <unknown>
+
+vlseg6e256.v v8, (a0)
+# CHECK-INST: vlseg6e256.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xb2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 b2 <unknown>
+
+vlseg6e512.v v8, (a0)
+# CHECK-INST: vlseg6e512.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xb2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 b2 <unknown>
+
+vlseg6e1024.v v8, (a0)
+# CHECK-INST: vlseg6e1024.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xb2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 b2 <unknown>
+
+vlseg6e8.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e8.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xa0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 a0 <unknown>
+
+vlseg6e16.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e16.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xa0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 a0 <unknown>
+
+vlseg6e32.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e32.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xa0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 a0 <unknown>
+
+vlseg6e64.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e64.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xa0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 a0 <unknown>
+
+vlseg6e128.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e128.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xb0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 b0 <unknown>
+
+vlseg6e256.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e256.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xb0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 b0 <unknown>
+
+vlseg6e512.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e512.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xb0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 b0 <unknown>
+
+vlseg6e1024.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e1024.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xb0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 b0 <unknown>
+
+vlseg7e8.v v8, (a0)
+# CHECK-INST: vlseg7e8.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xc2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 c2 <unknown>
+
+vlseg7e16.v v8, (a0)
+# CHECK-INST: vlseg7e16.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xc2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 c2 <unknown>
+
+vlseg7e32.v v8, (a0)
+# CHECK-INST: vlseg7e32.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xc2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 c2 <unknown>
+
+vlseg7e64.v v8, (a0)
+# CHECK-INST: vlseg7e64.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xc2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 c2 <unknown>
+
+vlseg7e128.v v8, (a0)
+# CHECK-INST: vlseg7e128.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xd2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 d2 <unknown>
+
+vlseg7e256.v v8, (a0)
+# CHECK-INST: vlseg7e256.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xd2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 d2 <unknown>
+
+vlseg7e512.v v8, (a0)
+# CHECK-INST: vlseg7e512.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xd2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 d2 <unknown>
+
+vlseg7e1024.v v8, (a0)
+# CHECK-INST: vlseg7e1024.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xd2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 d2 <unknown>
+
+vlseg7e8.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e8.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xc0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 c0 <unknown>
+
+vlseg7e16.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e16.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xc0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 c0 <unknown>
+
+vlseg7e32.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e32.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xc0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 c0 <unknown>
+
+vlseg7e64.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e64.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xc0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 c0 <unknown>
+
+vlseg7e128.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e128.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xd0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 d0 <unknown>
+
+vlseg7e256.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e256.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xd0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 d0 <unknown>
+
+vlseg7e512.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e512.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xd0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 d0 <unknown>
+
+vlseg7e1024.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e1024.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xd0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 d0 <unknown>
+
+vlseg8e8.v v8, (a0)
+# CHECK-INST: vlseg8e8.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xe2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 e2 <unknown>
+
+vlseg8e16.v v8, (a0)
+# CHECK-INST: vlseg8e16.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xe2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 e2 <unknown>
+
+vlseg8e32.v v8, (a0)
+# CHECK-INST: vlseg8e32.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xe2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 e2 <unknown>
+
+vlseg8e64.v v8, (a0)
+# CHECK-INST: vlseg8e64.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xe2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 e2 <unknown>
+
+vlseg8e128.v v8, (a0)
+# CHECK-INST: vlseg8e128.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xf2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 f2 <unknown>
+
+vlseg8e256.v v8, (a0)
+# CHECK-INST: vlseg8e256.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xf2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 f2 <unknown>
+
+vlseg8e512.v v8, (a0)
+# CHECK-INST: vlseg8e512.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xf2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 f2 <unknown>
+
+vlseg8e1024.v v8, (a0)
+# CHECK-INST: vlseg8e1024.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xf2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 f2 <unknown>
+
+vlseg8e8.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e8.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xe0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 e0 <unknown>
+
+vlseg8e16.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e16.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xe0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 e0 <unknown>
+
+vlseg8e32.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e32.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xe0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 e0 <unknown>
+
+vlseg8e64.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e64.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xe0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 e0 <unknown>
+
+vlseg8e128.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e128.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xf0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 f0 <unknown>
+
+vlseg8e256.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e256.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xf0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 f0 <unknown>
+
+vlseg8e512.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e512.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xf0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 f0 <unknown>
+
+vlseg8e1024.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e1024.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xf0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 f0 <unknown>
+
+vlsseg2e8.v v8, (a0), a1
+# CHECK-INST: vlsseg2e8.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x2a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 b5 2a <unknown>
+
+vlsseg2e16.v v8, (a0), a1
+# CHECK-INST: vlsseg2e16.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x2a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 b5 2a <unknown>
+
+vlsseg2e32.v v8, (a0), a1
+# CHECK-INST: vlsseg2e32.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x2a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 b5 2a <unknown>
+
+vlsseg2e64.v v8, (a0), a1
+# CHECK-INST: vlsseg2e64.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x2a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 b5 2a <unknown>
+
+vlsseg2e128.v v8, (a0), a1
+# CHECK-INST: vlsseg2e128.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x3a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 b5 3a <unknown>
+
+vlsseg2e256.v v8, (a0), a1
+# CHECK-INST: vlsseg2e256.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x3a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 b5 3a <unknown>
+
+vlsseg2e512.v v8, (a0), a1
+# CHECK-INST: vlsseg2e512.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x3a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 b5 3a <unknown>
+
+vlsseg2e1024.v v8, (a0), a1
+# CHECK-INST: vlsseg2e1024.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x3a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 b5 3a <unknown>
+
+vlsseg2e8.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg2e8.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x28]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 b5 28 <unknown>
+
+vlsseg2e16.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg2e16.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x28]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 b5 28 <unknown>
+
+vlsseg2e32.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg2e32.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x28]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 b5 28 <unknown>
+
+vlsseg2e64.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg2e64.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x28]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 b5 28 <unknown>
+
+vlsseg2e128.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg2e128.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x38]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 b5 38 <unknown>
+
+vlsseg2e256.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg2e256.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x38]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 b5 38 <unknown>
+
+vlsseg2e512.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg2e512.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x38]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 b5 38 <unknown>
+
+vlsseg2e1024.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg2e1024.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x38]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 b5 38 <unknown>
+
+vlsseg3e8.v v8, (a0), a1
+# CHECK-INST: vlsseg3e8.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 b5 4a <unknown>
+
+vlsseg3e16.v v8, (a0), a1
+# CHECK-INST: vlsseg3e16.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 b5 4a <unknown>
+
+vlsseg3e32.v v8, (a0), a1
+# CHECK-INST: vlsseg3e32.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 b5 4a <unknown>
+
+vlsseg3e64.v v8, (a0), a1
+# CHECK-INST: vlsseg3e64.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 b5 4a <unknown>
+
+vlsseg3e128.v v8, (a0), a1
+# CHECK-INST: vlsseg3e128.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x5a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 b5 5a <unknown>
+
+vlsseg3e256.v v8, (a0), a1
+# CHECK-INST: vlsseg3e256.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x5a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 b5 5a <unknown>
+
+vlsseg3e512.v v8, (a0), a1
+# CHECK-INST: vlsseg3e512.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x5a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 b5 5a <unknown>
+
+vlsseg3e1024.v v8, (a0), a1
+# CHECK-INST: vlsseg3e1024.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x5a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 b5 5a <unknown>
+
+vlsseg3e8.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg3e8.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 b5 48 <unknown>
+
+vlsseg3e16.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg3e16.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 b5 48 <unknown>
+
+vlsseg3e32.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg3e32.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 b5 48 <unknown>
+
+vlsseg3e64.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg3e64.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 b5 48 <unknown>
+
+vlsseg3e128.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg3e128.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x58]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 b5 58 <unknown>
+
+vlsseg3e256.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg3e256.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x58]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 b5 58 <unknown>
+
+vlsseg3e512.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg3e512.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x58]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 b5 58 <unknown>
+
+vlsseg3e1024.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg3e1024.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x58]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 b5 58 <unknown>
+
+vlsseg4e8.v v8, (a0), a1
+# CHECK-INST: vlsseg4e8.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x6a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 b5 6a <unknown>
+
+vlsseg4e16.v v8, (a0), a1
+# CHECK-INST: vlsseg4e16.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x6a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 b5 6a <unknown>
+
+vlsseg4e32.v v8, (a0), a1
+# CHECK-INST: vlsseg4e32.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x6a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 b5 6a <unknown>
+
+vlsseg4e64.v v8, (a0), a1
+# CHECK-INST: vlsseg4e64.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x6a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 b5 6a <unknown>
+
+vlsseg4e128.v v8, (a0), a1
+# CHECK-INST: vlsseg4e128.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x7a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 b5 7a <unknown>
+
+vlsseg4e256.v v8, (a0), a1
+# CHECK-INST: vlsseg4e256.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x7a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 b5 7a <unknown>
+
+vlsseg4e512.v v8, (a0), a1
+# CHECK-INST: vlsseg4e512.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x7a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 b5 7a <unknown>
+
+vlsseg4e1024.v v8, (a0), a1
+# CHECK-INST: vlsseg4e1024.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x7a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 b5 7a <unknown>
+
+vlsseg4e8.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg4e8.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x68]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 b5 68 <unknown>
+
+vlsseg4e16.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg4e16.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x68]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 b5 68 <unknown>
+
+vlsseg4e32.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg4e32.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x68]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 b5 68 <unknown>
+
+vlsseg4e64.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg4e64.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x68]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 b5 68 <unknown>
+
+vlsseg4e128.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg4e128.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x78]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 b5 78 <unknown>
+
+vlsseg4e256.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg4e256.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x78]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 b5 78 <unknown>
+
+vlsseg4e512.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg4e512.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x78]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 b5 78 <unknown>
+
+vlsseg4e1024.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg4e1024.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x78]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 b5 78 <unknown>
+
+vlsseg5e8.v v8, (a0), a1
+# CHECK-INST: vlsseg5e8.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 b5 8a <unknown>
+
+vlsseg5e16.v v8, (a0), a1
+# CHECK-INST: vlsseg5e16.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 b5 8a <unknown>
+
+vlsseg5e32.v v8, (a0), a1
+# CHECK-INST: vlsseg5e32.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 b5 8a <unknown>
+
+vlsseg5e64.v v8, (a0), a1
+# CHECK-INST: vlsseg5e64.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 b5 8a <unknown>
+
+vlsseg5e128.v v8, (a0), a1
+# CHECK-INST: vlsseg5e128.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x9a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 b5 9a <unknown>
+
+vlsseg5e256.v v8, (a0), a1
+# CHECK-INST: vlsseg5e256.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x9a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 b5 9a <unknown>
+
+vlsseg5e512.v v8, (a0), a1
+# CHECK-INST: vlsseg5e512.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x9a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 b5 9a <unknown>
+
+vlsseg5e1024.v v8, (a0), a1
+# CHECK-INST: vlsseg5e1024.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x9a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 b5 9a <unknown>
+
+vlsseg5e8.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg5e8.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 b5 88 <unknown>
+
+vlsseg5e16.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg5e16.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 b5 88 <unknown>
+
+vlsseg5e32.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg5e32.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 b5 88 <unknown>
+
+vlsseg5e64.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg5e64.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 b5 88 <unknown>
+
+vlsseg5e128.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg5e128.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x98]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 b5 98 <unknown>
+
+vlsseg5e256.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg5e256.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x98]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 b5 98 <unknown>
+
+vlsseg5e512.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg5e512.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x98]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 b5 98 <unknown>
+
+vlsseg5e1024.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg5e1024.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x98]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 b5 98 <unknown>
+
+vlsseg6e8.v v8, (a0), a1
+# CHECK-INST: vlsseg6e8.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xaa]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 b5 aa <unknown>
+
+vlsseg6e16.v v8, (a0), a1
+# CHECK-INST: vlsseg6e16.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xaa]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 b5 aa <unknown>
+
+vlsseg6e32.v v8, (a0), a1
+# CHECK-INST: vlsseg6e32.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xaa]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 b5 aa <unknown>
+
+vlsseg6e64.v v8, (a0), a1
+# CHECK-INST: vlsseg6e64.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xaa]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 b5 aa <unknown>
+
+vlsseg6e128.v v8, (a0), a1
+# CHECK-INST: vlsseg6e128.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xba]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 b5 ba <unknown>
+
+vlsseg6e256.v v8, (a0), a1
+# CHECK-INST: vlsseg6e256.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xba]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 b5 ba <unknown>
+
+vlsseg6e512.v v8, (a0), a1
+# CHECK-INST: vlsseg6e512.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xba]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 b5 ba <unknown>
+
+vlsseg6e1024.v v8, (a0), a1
+# CHECK-INST: vlsseg6e1024.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xba]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 b5 ba <unknown>
+
+vlsseg6e8.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg6e8.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xa8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 b5 a8 <unknown>
+
+vlsseg6e16.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg6e16.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xa8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 b5 a8 <unknown>
+
+vlsseg6e32.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg6e32.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xa8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 b5 a8 <unknown>
+
+vlsseg6e64.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg6e64.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xa8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 b5 a8 <unknown>
+
+vlsseg6e128.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg6e128.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xb8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 b5 b8 <unknown>
+
+vlsseg6e256.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg6e256.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xb8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 b5 b8 <unknown>
+
+vlsseg6e512.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg6e512.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xb8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 b5 b8 <unknown>
+
+vlsseg6e1024.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg6e1024.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xb8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 b5 b8 <unknown>
+
+vlsseg7e8.v v8, (a0), a1
+# CHECK-INST: vlsseg7e8.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xca]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 b5 ca <unknown>
+
+vlsseg7e16.v v8, (a0), a1
+# CHECK-INST: vlsseg7e16.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xca]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 b5 ca <unknown>
+
+vlsseg7e32.v v8, (a0), a1
+# CHECK-INST: vlsseg7e32.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xca]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 b5 ca <unknown>
+
+vlsseg7e64.v v8, (a0), a1
+# CHECK-INST: vlsseg7e64.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xca]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 b5 ca <unknown>
+
+vlsseg7e128.v v8, (a0), a1
+# CHECK-INST: vlsseg7e128.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xda]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 b5 da <unknown>
+
+vlsseg7e256.v v8, (a0), a1
+# CHECK-INST: vlsseg7e256.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xda]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 b5 da <unknown>
+
+vlsseg7e512.v v8, (a0), a1
+# CHECK-INST: vlsseg7e512.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xda]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 b5 da <unknown>
+
+vlsseg7e1024.v v8, (a0), a1
+# CHECK-INST: vlsseg7e1024.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xda]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 b5 da <unknown>
+
+vlsseg7e8.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg7e8.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xc8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 b5 c8 <unknown>
+
+vlsseg7e16.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg7e16.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xc8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 b5 c8 <unknown>
+
+vlsseg7e32.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg7e32.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xc8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 b5 c8 <unknown>
+
+vlsseg7e64.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg7e64.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xc8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 b5 c8 <unknown>
+
+vlsseg7e128.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg7e128.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xd8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 b5 d8 <unknown>
+
+vlsseg7e256.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg7e256.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xd8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 b5 d8 <unknown>
+
+vlsseg7e512.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg7e512.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xd8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 b5 d8 <unknown>
+
+vlsseg7e1024.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg7e1024.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xd8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 b5 d8 <unknown>
+
+vlsseg8e8.v v8, (a0), a1
+# CHECK-INST: vlsseg8e8.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xea]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 b5 ea <unknown>
+
+vlsseg8e16.v v8, (a0), a1
+# CHECK-INST: vlsseg8e16.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xea]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 b5 ea <unknown>
+
+vlsseg8e32.v v8, (a0), a1
+# CHECK-INST: vlsseg8e32.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xea]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 b5 ea <unknown>
+
+vlsseg8e64.v v8, (a0), a1
+# CHECK-INST: vlsseg8e64.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xea]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 b5 ea <unknown>
+
+vlsseg8e128.v v8, (a0), a1
+# CHECK-INST: vlsseg8e128.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xfa]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 b5 fa <unknown>
+
+vlsseg8e256.v v8, (a0), a1
+# CHECK-INST: vlsseg8e256.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xfa]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 b5 fa <unknown>
+
+vlsseg8e512.v v8, (a0), a1
+# CHECK-INST: vlsseg8e512.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xfa]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 b5 fa <unknown>
+
+vlsseg8e1024.v v8, (a0), a1
+# CHECK-INST: vlsseg8e1024.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xfa]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 b5 fa <unknown>
+
+vlsseg8e8.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg8e8.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xe8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 b5 e8 <unknown>
+
+vlsseg8e16.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg8e16.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xe8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 b5 e8 <unknown>
+
+vlsseg8e32.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg8e32.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xe8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 b5 e8 <unknown>
+
+vlsseg8e64.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg8e64.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xe8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 b5 e8 <unknown>
+
+vlsseg8e128.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg8e128.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0xf8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 b5 f8 <unknown>
+
+vlsseg8e256.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg8e256.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0xf8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 b5 f8 <unknown>
+
+vlsseg8e512.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg8e512.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0xf8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 b5 f8 <unknown>
+
+vlsseg8e1024.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsseg8e1024.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0xf8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 b5 f8 <unknown>
+
+vlxseg2ei8.v v8, (a0), v4
+# CHECK-INST: vlxseg2ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 45 2e <unknown>
+
+vlxseg2ei16.v v8, (a0), v4
+# CHECK-INST: vlxseg2ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 45 2e <unknown>
+
+vlxseg2ei32.v v8, (a0), v4
+# CHECK-INST: vlxseg2ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 45 2e <unknown>
+
+vlxseg2ei64.v v8, (a0), v4
+# CHECK-INST: vlxseg2ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 45 2e <unknown>
+
+vlxseg2ei128.v v8, (a0), v4
+# CHECK-INST: vlxseg2ei128.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x3e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 45 3e <unknown>
+
+vlxseg2ei256.v v8, (a0), v4
+# CHECK-INST: vlxseg2ei256.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x3e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 45 3e <unknown>
+
+vlxseg2ei512.v v8, (a0), v4
+# CHECK-INST: vlxseg2ei512.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x3e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 45 3e <unknown>
+
+vlxseg2ei1024.v v8, (a0), v4
+# CHECK-INST: vlxseg2ei1024.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x3e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 45 3e <unknown>
+
+vlxseg2ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg2ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 45 2c <unknown>
+
+vlxseg2ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg2ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 45 2c <unknown>
+
+vlxseg2ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg2ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 45 2c <unknown>
+
+vlxseg2ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg2ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 45 2c <unknown>
+
+vlxseg2ei128.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg2ei128.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x3c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 45 3c <unknown>
+
+vlxseg2ei256.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg2ei256.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x3c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 45 3c <unknown>
+
+vlxseg2ei512.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg2ei512.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x3c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 45 3c <unknown>
+
+vlxseg2ei1024.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg2ei1024.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x3c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 45 3c <unknown>
+
+vlxseg3ei8.v v8, (a0), v4
+# CHECK-INST: vlxseg3ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 45 4e <unknown>
+
+vlxseg3ei16.v v8, (a0), v4
+# CHECK-INST: vlxseg3ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 45 4e <unknown>
+
+vlxseg3ei32.v v8, (a0), v4
+# CHECK-INST: vlxseg3ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 45 4e <unknown>
+
+vlxseg3ei64.v v8, (a0), v4
+# CHECK-INST: vlxseg3ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 45 4e <unknown>
+
+vlxseg3ei128.v v8, (a0), v4
+# CHECK-INST: vlxseg3ei128.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x5e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 45 5e <unknown>
+
+vlxseg3ei256.v v8, (a0), v4
+# CHECK-INST: vlxseg3ei256.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x5e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 45 5e <unknown>
+
+vlxseg3ei512.v v8, (a0), v4
+# CHECK-INST: vlxseg3ei512.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x5e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 45 5e <unknown>
+
+vlxseg3ei1024.v v8, (a0), v4
+# CHECK-INST: vlxseg3ei1024.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x5e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 45 5e <unknown>
+
+vlxseg3ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg3ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 45 4c <unknown>
+
+vlxseg3ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg3ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 45 4c <unknown>
+
+vlxseg3ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg3ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 45 4c <unknown>
+
+vlxseg3ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg3ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 45 4c <unknown>
+
+vlxseg3ei128.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg3ei128.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x5c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 45 5c <unknown>
+
+vlxseg3ei256.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg3ei256.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x5c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 45 5c <unknown>
+
+vlxseg3ei512.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg3ei512.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x5c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 45 5c <unknown>
+
+vlxseg3ei1024.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg3ei1024.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x5c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 45 5c <unknown>
+
+vlxseg4ei8.v v8, (a0), v4
+# CHECK-INST: vlxseg4ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 45 6e <unknown>
+
+vlxseg4ei16.v v8, (a0), v4
+# CHECK-INST: vlxseg4ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 45 6e <unknown>
+
+vlxseg4ei32.v v8, (a0), v4
+# CHECK-INST: vlxseg4ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 45 6e <unknown>
+
+vlxseg4ei64.v v8, (a0), v4
+# CHECK-INST: vlxseg4ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 45 6e <unknown>
+
+vlxseg4ei128.v v8, (a0), v4
+# CHECK-INST: vlxseg4ei128.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x7e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 45 7e <unknown>
+
+vlxseg4ei256.v v8, (a0), v4
+# CHECK-INST: vlxseg4ei256.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x7e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 45 7e <unknown>
+
+vlxseg4ei512.v v8, (a0), v4
+# CHECK-INST: vlxseg4ei512.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x7e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 45 7e <unknown>
+
+vlxseg4ei1024.v v8, (a0), v4
+# CHECK-INST: vlxseg4ei1024.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x7e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 45 7e <unknown>
+
+vlxseg4ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg4ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 45 6c <unknown>
+
+vlxseg4ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg4ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 45 6c <unknown>
+
+vlxseg4ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg4ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 45 6c <unknown>
+
+vlxseg4ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg4ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 45 6c <unknown>
+
+vlxseg4ei128.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg4ei128.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x7c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 45 7c <unknown>
+
+vlxseg4ei256.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg4ei256.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x7c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 45 7c <unknown>
+
+vlxseg4ei512.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg4ei512.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x7c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 45 7c <unknown>
+
+vlxseg4ei1024.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg4ei1024.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x7c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 45 7c <unknown>
+
+vlxseg5ei8.v v8, (a0), v4
+# CHECK-INST: vlxseg5ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 45 8e <unknown>
+
+vlxseg5ei16.v v8, (a0), v4
+# CHECK-INST: vlxseg5ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 45 8e <unknown>
+
+vlxseg5ei32.v v8, (a0), v4
+# CHECK-INST: vlxseg5ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 45 8e <unknown>
+
+vlxseg5ei64.v v8, (a0), v4
+# CHECK-INST: vlxseg5ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 45 8e <unknown>
+
+vlxseg5ei128.v v8, (a0), v4
+# CHECK-INST: vlxseg5ei128.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x9e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 45 9e <unknown>
+
+vlxseg5ei256.v v8, (a0), v4
+# CHECK-INST: vlxseg5ei256.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x9e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 45 9e <unknown>
+
+vlxseg5ei512.v v8, (a0), v4
+# CHECK-INST: vlxseg5ei512.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x9e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 45 9e <unknown>
+
+vlxseg5ei1024.v v8, (a0), v4
+# CHECK-INST: vlxseg5ei1024.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x9e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 45 9e <unknown>
+
+vlxseg5ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg5ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 45 8c <unknown>
+
+vlxseg5ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg5ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 45 8c <unknown>
+
+vlxseg5ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg5ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 45 8c <unknown>
+
+vlxseg5ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg5ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 45 8c <unknown>
+
+vlxseg5ei128.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg5ei128.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x9c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 45 9c <unknown>
+
+vlxseg5ei256.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg5ei256.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x9c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 45 9c <unknown>
+
+vlxseg5ei512.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg5ei512.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x9c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 45 9c <unknown>
+
+vlxseg5ei1024.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg5ei1024.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x9c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 45 9c <unknown>
+
+vlxseg6ei8.v v8, (a0), v4
+# CHECK-INST: vlxseg6ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 45 ae <unknown>
+
+vlxseg6ei16.v v8, (a0), v4
+# CHECK-INST: vlxseg6ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 45 ae <unknown>
+
+vlxseg6ei32.v v8, (a0), v4
+# CHECK-INST: vlxseg6ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 45 ae <unknown>
+
+vlxseg6ei64.v v8, (a0), v4
+# CHECK-INST: vlxseg6ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 45 ae <unknown>
+
+vlxseg6ei128.v v8, (a0), v4
+# CHECK-INST: vlxseg6ei128.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0xbe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 45 be <unknown>
+
+vlxseg6ei256.v v8, (a0), v4
+# CHECK-INST: vlxseg6ei256.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0xbe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 45 be <unknown>
+
+vlxseg6ei512.v v8, (a0), v4
+# CHECK-INST: vlxseg6ei512.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0xbe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 45 be <unknown>
+
+vlxseg6ei1024.v v8, (a0), v4
+# CHECK-INST: vlxseg6ei1024.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0xbe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 45 be <unknown>
+
+vlxseg6ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg6ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 45 ac <unknown>
+
+vlxseg6ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg6ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 45 ac <unknown>
+
+vlxseg6ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg6ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 45 ac <unknown>
+
+vlxseg6ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg6ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 45 ac <unknown>
+
+vlxseg6ei128.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg6ei128.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0xbc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 45 bc <unknown>
+
+vlxseg6ei256.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg6ei256.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0xbc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 45 bc <unknown>
+
+vlxseg6ei512.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg6ei512.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0xbc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 45 bc <unknown>
+
+vlxseg6ei1024.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg6ei1024.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0xbc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 45 bc <unknown>
+
+vlxseg7ei8.v v8, (a0), v4
+# CHECK-INST: vlxseg7ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 45 ce <unknown>
+
+vlxseg7ei16.v v8, (a0), v4
+# CHECK-INST: vlxseg7ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 45 ce <unknown>
+
+vlxseg7ei32.v v8, (a0), v4
+# CHECK-INST: vlxseg7ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 45 ce <unknown>
+
+vlxseg7ei64.v v8, (a0), v4
+# CHECK-INST: vlxseg7ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 45 ce <unknown>
+
+vlxseg7ei128.v v8, (a0), v4
+# CHECK-INST: vlxseg7ei128.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0xde]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 45 de <unknown>
+
+vlxseg7ei256.v v8, (a0), v4
+# CHECK-INST: vlxseg7ei256.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0xde]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 45 de <unknown>
+
+vlxseg7ei512.v v8, (a0), v4
+# CHECK-INST: vlxseg7ei512.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0xde]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 45 de <unknown>
+
+vlxseg7ei1024.v v8, (a0), v4
+# CHECK-INST: vlxseg7ei1024.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0xde]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 45 de <unknown>
+
+vlxseg7ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg7ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 45 cc <unknown>
+
+vlxseg7ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg7ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 45 cc <unknown>
+
+vlxseg7ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg7ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 45 cc <unknown>
+
+vlxseg7ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg7ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 45 cc <unknown>
+
+vlxseg7ei128.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg7ei128.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0xdc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 45 dc <unknown>
+
+vlxseg7ei256.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg7ei256.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0xdc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 45 dc <unknown>
+
+vlxseg7ei512.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg7ei512.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0xdc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 45 dc <unknown>
+
+vlxseg7ei1024.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg7ei1024.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0xdc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 45 dc <unknown>
+
+vlxseg8ei8.v v8, (a0), v4
+# CHECK-INST: vlxseg8ei8.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0xee]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 45 ee <unknown>
+
+vlxseg8ei16.v v8, (a0), v4
+# CHECK-INST: vlxseg8ei16.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0xee]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 45 ee <unknown>
+
+vlxseg8ei32.v v8, (a0), v4
+# CHECK-INST: vlxseg8ei32.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0xee]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 45 ee <unknown>
+
+vlxseg8ei64.v v8, (a0), v4
+# CHECK-INST: vlxseg8ei64.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0xee]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 45 ee <unknown>
+
+vlxseg8ei128.v v8, (a0), v4
+# CHECK-INST: vlxseg8ei128.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0xfe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 45 fe <unknown>
+
+vlxseg8ei256.v v8, (a0), v4
+# CHECK-INST: vlxseg8ei256.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0xfe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 45 fe <unknown>
+
+vlxseg8ei512.v v8, (a0), v4
+# CHECK-INST: vlxseg8ei512.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0xfe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 45 fe <unknown>
+
+vlxseg8ei1024.v v8, (a0), v4
+# CHECK-INST: vlxseg8ei1024.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0xfe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 45 fe <unknown>
+
+vlxseg8ei8.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg8ei8.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0xec]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 45 ec <unknown>
+
+vlxseg8ei16.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg8ei16.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0xec]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 45 ec <unknown>
+
+vlxseg8ei32.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg8ei32.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0xec]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 45 ec <unknown>
+
+vlxseg8ei64.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg8ei64.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0xec]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 45 ec <unknown>
+
+vlxseg8ei128.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg8ei128.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0xfc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 45 fc <unknown>
+
+vlxseg8ei256.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg8ei256.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0xfc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 45 fc <unknown>
+
+vlxseg8ei512.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg8ei512.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0xfc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 45 fc <unknown>
+
+vlxseg8ei1024.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxseg8ei1024.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0xfc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 45 fc <unknown>
+
+vlseg2e8ff.v v8, (a0)
+# CHECK-INST: vlseg2e8ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x23]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 23 <unknown>
+
+vlseg2e16ff.v v8, (a0)
+# CHECK-INST: vlseg2e16ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x23]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 23 <unknown>
+
+vlseg2e32ff.v v8, (a0)
+# CHECK-INST: vlseg2e32ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x23]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 23 <unknown>
+
+vlseg2e64ff.v v8, (a0)
+# CHECK-INST: vlseg2e64ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x23]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 23 <unknown>
+
+vlseg2e128ff.v v8, (a0)
+# CHECK-INST: vlseg2e128ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x33]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 33 <unknown>
+
+vlseg2e256ff.v v8, (a0)
+# CHECK-INST: vlseg2e256ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x33]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 33 <unknown>
+
+vlseg2e512ff.v v8, (a0)
+# CHECK-INST: vlseg2e512ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x33]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 33 <unknown>
+
+vlseg2e1024ff.v v8, (a0)
+# CHECK-INST: vlseg2e1024ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x33]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 33 <unknown>
+
+vlseg2e8ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e8ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x21]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 21 <unknown>
+
+vlseg2e16ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e16ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x21]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 21 <unknown>
+
+vlseg2e32ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e32ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x21]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 21 <unknown>
+
+vlseg2e64ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e64ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x21]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 21 <unknown>
+
+vlseg2e128ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e128ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x31]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 31 <unknown>
+
+vlseg2e256ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e256ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x31]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 31 <unknown>
+
+vlseg2e512ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e512ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x31]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 31 <unknown>
+
+vlseg2e1024ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg2e1024ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x31]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 31 <unknown>
+
+vlseg3e8ff.v v8, (a0)
+# CHECK-INST: vlseg3e8ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x43]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 43 <unknown>
+
+vlseg3e16ff.v v8, (a0)
+# CHECK-INST: vlseg3e16ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x43]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 43 <unknown>
+
+vlseg3e32ff.v v8, (a0)
+# CHECK-INST: vlseg3e32ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x43]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 43 <unknown>
+
+vlseg3e64ff.v v8, (a0)
+# CHECK-INST: vlseg3e64ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x43]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 43 <unknown>
+
+vlseg3e128ff.v v8, (a0)
+# CHECK-INST: vlseg3e128ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x53]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 53 <unknown>
+
+vlseg3e256ff.v v8, (a0)
+# CHECK-INST: vlseg3e256ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x53]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 53 <unknown>
+
+vlseg3e512ff.v v8, (a0)
+# CHECK-INST: vlseg3e512ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x53]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 53 <unknown>
+
+vlseg3e1024ff.v v8, (a0)
+# CHECK-INST: vlseg3e1024ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x53]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 53 <unknown>
+
+vlseg3e8ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e8ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x41]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 41 <unknown>
+
+vlseg3e16ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e16ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x41]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 41 <unknown>
+
+vlseg3e32ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e32ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x41]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 41 <unknown>
+
+vlseg3e64ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e64ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x41]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 41 <unknown>
+
+vlseg3e128ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e128ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x51]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 51 <unknown>
+
+vlseg3e256ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e256ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x51]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 51 <unknown>
+
+vlseg3e512ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e512ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x51]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 51 <unknown>
+
+vlseg3e1024ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg3e1024ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x51]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 51 <unknown>
+
+vlseg4e8ff.v v8, (a0)
+# CHECK-INST: vlseg4e8ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x63]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 63 <unknown>
+
+vlseg4e16ff.v v8, (a0)
+# CHECK-INST: vlseg4e16ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x63]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 63 <unknown>
+
+vlseg4e32ff.v v8, (a0)
+# CHECK-INST: vlseg4e32ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x63]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 63 <unknown>
+
+vlseg4e64ff.v v8, (a0)
+# CHECK-INST: vlseg4e64ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x63]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 63 <unknown>
+
+vlseg4e128ff.v v8, (a0)
+# CHECK-INST: vlseg4e128ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x73]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 73 <unknown>
+
+vlseg4e256ff.v v8, (a0)
+# CHECK-INST: vlseg4e256ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x73]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 73 <unknown>
+
+vlseg4e512ff.v v8, (a0)
+# CHECK-INST: vlseg4e512ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x73]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 73 <unknown>
+
+vlseg4e1024ff.v v8, (a0)
+# CHECK-INST: vlseg4e1024ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x73]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 73 <unknown>
+
+vlseg4e8ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e8ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x61]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 61 <unknown>
+
+vlseg4e16ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e16ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x61]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 61 <unknown>
+
+vlseg4e32ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e32ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x61]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 61 <unknown>
+
+vlseg4e64ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e64ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x61]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 61 <unknown>
+
+vlseg4e128ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e128ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x71]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 71 <unknown>
+
+vlseg4e256ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e256ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x71]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 71 <unknown>
+
+vlseg4e512ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e512ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x71]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 71 <unknown>
+
+vlseg4e1024ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg4e1024ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x71]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 71 <unknown>
+
+vlseg5e8ff.v v8, (a0)
+# CHECK-INST: vlseg5e8ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x83]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 83 <unknown>
+
+vlseg5e16ff.v v8, (a0)
+# CHECK-INST: vlseg5e16ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x83]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 83 <unknown>
+
+vlseg5e32ff.v v8, (a0)
+# CHECK-INST: vlseg5e32ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x83]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 83 <unknown>
+
+vlseg5e64ff.v v8, (a0)
+# CHECK-INST: vlseg5e64ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x83]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 83 <unknown>
+
+vlseg5e128ff.v v8, (a0)
+# CHECK-INST: vlseg5e128ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x93]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 93 <unknown>
+
+vlseg5e256ff.v v8, (a0)
+# CHECK-INST: vlseg5e256ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x93]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 93 <unknown>
+
+vlseg5e512ff.v v8, (a0)
+# CHECK-INST: vlseg5e512ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x93]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 93 <unknown>
+
+vlseg5e1024ff.v v8, (a0)
+# CHECK-INST: vlseg5e1024ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x93]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 93 <unknown>
+
+vlseg5e8ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e8ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x81]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 81 <unknown>
+
+vlseg5e16ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e16ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x81]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 81 <unknown>
+
+vlseg5e32ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e32ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x81]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 81 <unknown>
+
+vlseg5e64ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e64ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x81]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 81 <unknown>
+
+vlseg5e128ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e128ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x91]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 91 <unknown>
+
+vlseg5e256ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e256ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x91]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 91 <unknown>
+
+vlseg5e512ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e512ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x91]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 91 <unknown>
+
+vlseg5e1024ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg5e1024ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x91]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 91 <unknown>
+
+vlseg6e8ff.v v8, (a0)
+# CHECK-INST: vlseg6e8ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xa3]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 a3 <unknown>
+
+vlseg6e16ff.v v8, (a0)
+# CHECK-INST: vlseg6e16ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xa3]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 a3 <unknown>
+
+vlseg6e32ff.v v8, (a0)
+# CHECK-INST: vlseg6e32ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xa3]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 a3 <unknown>
+
+vlseg6e64ff.v v8, (a0)
+# CHECK-INST: vlseg6e64ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xa3]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 a3 <unknown>
+
+vlseg6e128ff.v v8, (a0)
+# CHECK-INST: vlseg6e128ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xb3]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 b3 <unknown>
+
+vlseg6e256ff.v v8, (a0)
+# CHECK-INST: vlseg6e256ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xb3]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 b3 <unknown>
+
+vlseg6e512ff.v v8, (a0)
+# CHECK-INST: vlseg6e512ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xb3]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 b3 <unknown>
+
+vlseg6e1024ff.v v8, (a0)
+# CHECK-INST: vlseg6e1024ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xb3]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 b3 <unknown>
+
+vlseg6e8ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e8ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xa1]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 a1 <unknown>
+
+vlseg6e16ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e16ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xa1]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 a1 <unknown>
+
+vlseg6e32ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e32ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xa1]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 a1 <unknown>
+
+vlseg6e64ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e64ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xa1]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 a1 <unknown>
+
+vlseg6e128ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e128ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xb1]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 b1 <unknown>
+
+vlseg6e256ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e256ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xb1]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 b1 <unknown>
+
+vlseg6e512ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e512ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xb1]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 b1 <unknown>
+
+vlseg6e1024ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg6e1024ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xb1]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 b1 <unknown>
+
+vlseg7e8ff.v v8, (a0)
+# CHECK-INST: vlseg7e8ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xc3]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 c3 <unknown>
+
+vlseg7e16ff.v v8, (a0)
+# CHECK-INST: vlseg7e16ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xc3]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 c3 <unknown>
+
+vlseg7e32ff.v v8, (a0)
+# CHECK-INST: vlseg7e32ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xc3]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 c3 <unknown>
+
+vlseg7e64ff.v v8, (a0)
+# CHECK-INST: vlseg7e64ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xc3]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 c3 <unknown>
+
+vlseg7e128ff.v v8, (a0)
+# CHECK-INST: vlseg7e128ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xd3]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 d3 <unknown>
+
+vlseg7e256ff.v v8, (a0)
+# CHECK-INST: vlseg7e256ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xd3]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 d3 <unknown>
+
+vlseg7e512ff.v v8, (a0)
+# CHECK-INST: vlseg7e512ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xd3]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 d3 <unknown>
+
+vlseg7e1024ff.v v8, (a0)
+# CHECK-INST: vlseg7e1024ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xd3]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 d3 <unknown>
+
+vlseg7e8ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e8ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xc1]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 c1 <unknown>
+
+vlseg7e16ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e16ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xc1]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 c1 <unknown>
+
+vlseg7e32ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e32ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xc1]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 c1 <unknown>
+
+vlseg7e64ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e64ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xc1]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 c1 <unknown>
+
+vlseg7e128ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e128ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xd1]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 d1 <unknown>
+
+vlseg7e256ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e256ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xd1]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 d1 <unknown>
+
+vlseg7e512ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e512ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xd1]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 d1 <unknown>
+
+vlseg7e1024ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg7e1024ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xd1]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 d1 <unknown>
+
+vlseg8e8ff.v v8, (a0)
+# CHECK-INST: vlseg8e8ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xe3]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 e3 <unknown>
+
+vlseg8e16ff.v v8, (a0)
+# CHECK-INST: vlseg8e16ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xe3]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 e3 <unknown>
+
+vlseg8e32ff.v v8, (a0)
+# CHECK-INST: vlseg8e32ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xe3]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 e3 <unknown>
+
+vlseg8e64ff.v v8, (a0)
+# CHECK-INST: vlseg8e64ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xe3]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 e3 <unknown>
+
+vlseg8e128ff.v v8, (a0)
+# CHECK-INST: vlseg8e128ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0xf3]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 f3 <unknown>
+
+vlseg8e256ff.v v8, (a0)
+# CHECK-INST: vlseg8e256ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0xf3]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 f3 <unknown>
+
+vlseg8e512ff.v v8, (a0)
+# CHECK-INST: vlseg8e512ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0xf3]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 f3 <unknown>
+
+vlseg8e1024ff.v v8, (a0)
+# CHECK-INST: vlseg8e1024ff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0xf3]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 f3 <unknown>
+
+vlseg8e8ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e8ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xe1]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 e1 <unknown>
+
+vlseg8e16ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e16ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xe1]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 e1 <unknown>
+
+vlseg8e32ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e32ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xe1]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 e1 <unknown>
+
+vlseg8e64ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e64ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xe1]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 e1 <unknown>
+
+vlseg8e128ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e128ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0xf1]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 04 05 f1 <unknown>
+
+vlseg8e256ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e256ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0xf1]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 54 05 f1 <unknown>
+
+vlseg8e512ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e512ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0xf1]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 64 05 f1 <unknown>
+
+vlseg8e1024ff.v v8, (a0), v0.t
+# CHECK-INST: vlseg8e1024ff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0xf1]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 07 74 05 f1 <unknown>
+
+vsseg2e8.v v24, (a0)
+# CHECK-INST: vsseg2e8.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x22]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 05 22 <unknown>
+
+vsseg2e16.v v24, (a0)
+# CHECK-INST: vsseg2e16.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x22]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 05 22 <unknown>
+
+vsseg2e32.v v24, (a0)
+# CHECK-INST: vsseg2e32.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x22]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 05 22 <unknown>
+
+vsseg2e64.v v24, (a0)
+# CHECK-INST: vsseg2e64.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x22]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 05 22 <unknown>
+
+vsseg2e128.v v24, (a0)
+# CHECK-INST: vsseg2e128.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x32]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 05 32 <unknown>
+
+vsseg2e256.v v24, (a0)
+# CHECK-INST: vsseg2e256.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x32]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 05 32 <unknown>
+
+vsseg2e512.v v24, (a0)
+# CHECK-INST: vsseg2e512.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x32]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 05 32 <unknown>
+
+vsseg2e1024.v v24, (a0)
+# CHECK-INST: vsseg2e1024.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x32]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 05 32 <unknown>
+
+vsseg2e8.v v24, (a0), v0.t
+# CHECK-INST: vsseg2e8.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x20]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 05 20 <unknown>
+
+vsseg2e16.v v24, (a0), v0.t
+# CHECK-INST: vsseg2e16.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x20]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 05 20 <unknown>
+
+vsseg2e32.v v24, (a0), v0.t
+# CHECK-INST: vsseg2e32.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x20]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 05 20 <unknown>
+
+vsseg2e64.v v24, (a0), v0.t
+# CHECK-INST: vsseg2e64.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x20]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 05 20 <unknown>
+
+vsseg2e128.v v24, (a0), v0.t
+# CHECK-INST: vsseg2e128.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x30]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 05 30 <unknown>
+
+vsseg2e256.v v24, (a0), v0.t
+# CHECK-INST: vsseg2e256.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x30]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 05 30 <unknown>
+
+vsseg2e512.v v24, (a0), v0.t
+# CHECK-INST: vsseg2e512.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x30]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 05 30 <unknown>
+
+vsseg2e1024.v v24, (a0), v0.t
+# CHECK-INST: vsseg2e1024.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x30]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 05 30 <unknown>
+
+vsseg3e8.v v24, (a0)
+# CHECK-INST: vsseg3e8.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 05 42 <unknown>
+
+vsseg3e16.v v24, (a0)
+# CHECK-INST: vsseg3e16.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 05 42 <unknown>
+
+vsseg3e32.v v24, (a0)
+# CHECK-INST: vsseg3e32.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 05 42 <unknown>
+
+vsseg3e64.v v24, (a0)
+# CHECK-INST: vsseg3e64.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 05 42 <unknown>
+
+vsseg3e128.v v24, (a0)
+# CHECK-INST: vsseg3e128.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x52]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 05 52 <unknown>
+
+vsseg3e256.v v24, (a0)
+# CHECK-INST: vsseg3e256.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x52]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 05 52 <unknown>
+
+vsseg3e512.v v24, (a0)
+# CHECK-INST: vsseg3e512.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x52]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 05 52 <unknown>
+
+vsseg3e1024.v v24, (a0)
+# CHECK-INST: vsseg3e1024.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x52]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 05 52 <unknown>
+
+vsseg3e8.v v24, (a0), v0.t
+# CHECK-INST: vsseg3e8.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x40]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 05 40 <unknown>
+
+vsseg3e16.v v24, (a0), v0.t
+# CHECK-INST: vsseg3e16.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x40]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 05 40 <unknown>
+
+vsseg3e32.v v24, (a0), v0.t
+# CHECK-INST: vsseg3e32.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x40]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 05 40 <unknown>
+
+vsseg3e64.v v24, (a0), v0.t
+# CHECK-INST: vsseg3e64.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x40]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 05 40 <unknown>
+
+vsseg3e128.v v24, (a0), v0.t
+# CHECK-INST: vsseg3e128.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x50]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 05 50 <unknown>
+
+vsseg3e256.v v24, (a0), v0.t
+# CHECK-INST: vsseg3e256.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x50]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 05 50 <unknown>
+
+vsseg3e512.v v24, (a0), v0.t
+# CHECK-INST: vsseg3e512.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x50]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 05 50 <unknown>
+
+vsseg3e1024.v v24, (a0), v0.t
+# CHECK-INST: vsseg3e1024.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x50]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 05 50 <unknown>
+
+vsseg4e8.v v24, (a0)
+# CHECK-INST: vsseg4e8.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x62]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 05 62 <unknown>
+
+vsseg4e16.v v24, (a0)
+# CHECK-INST: vsseg4e16.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x62]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 05 62 <unknown>
+
+vsseg4e32.v v24, (a0)
+# CHECK-INST: vsseg4e32.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x62]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 05 62 <unknown>
+
+vsseg4e64.v v24, (a0)
+# CHECK-INST: vsseg4e64.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x62]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 05 62 <unknown>
+
+vsseg4e128.v v24, (a0)
+# CHECK-INST: vsseg4e128.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x72]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 05 72 <unknown>
+
+vsseg4e256.v v24, (a0)
+# CHECK-INST: vsseg4e256.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x72]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 05 72 <unknown>
+
+vsseg4e512.v v24, (a0)
+# CHECK-INST: vsseg4e512.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x72]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 05 72 <unknown>
+
+vsseg4e1024.v v24, (a0)
+# CHECK-INST: vsseg4e1024.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x72]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 05 72 <unknown>
+
+vsseg4e8.v v24, (a0), v0.t
+# CHECK-INST: vsseg4e8.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x60]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 05 60 <unknown>
+
+vsseg4e16.v v24, (a0), v0.t
+# CHECK-INST: vsseg4e16.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x60]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 05 60 <unknown>
+
+vsseg4e32.v v24, (a0), v0.t
+# CHECK-INST: vsseg4e32.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x60]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 05 60 <unknown>
+
+vsseg4e64.v v24, (a0), v0.t
+# CHECK-INST: vsseg4e64.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x60]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 05 60 <unknown>
+
+vsseg4e128.v v24, (a0), v0.t
+# CHECK-INST: vsseg4e128.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x70]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 05 70 <unknown>
+
+vsseg4e256.v v24, (a0), v0.t
+# CHECK-INST: vsseg4e256.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x70]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 05 70 <unknown>
+
+vsseg4e512.v v24, (a0), v0.t
+# CHECK-INST: vsseg4e512.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x70]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 05 70 <unknown>
+
+vsseg4e1024.v v24, (a0), v0.t
+# CHECK-INST: vsseg4e1024.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x70]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 05 70 <unknown>
+
+vsseg5e8.v v24, (a0)
+# CHECK-INST: vsseg5e8.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x82]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 05 82 <unknown>
+
+vsseg5e16.v v24, (a0)
+# CHECK-INST: vsseg5e16.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x82]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 05 82 <unknown>
+
+vsseg5e32.v v24, (a0)
+# CHECK-INST: vsseg5e32.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x82]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 05 82 <unknown>
+
+vsseg5e64.v v24, (a0)
+# CHECK-INST: vsseg5e64.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x82]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 05 82 <unknown>
+
+vsseg5e128.v v24, (a0)
+# CHECK-INST: vsseg5e128.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x92]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 05 92 <unknown>
+
+vsseg5e256.v v24, (a0)
+# CHECK-INST: vsseg5e256.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x92]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 05 92 <unknown>
+
+vsseg5e512.v v24, (a0)
+# CHECK-INST: vsseg5e512.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x92]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 05 92 <unknown>
+
+vsseg5e1024.v v24, (a0)
+# CHECK-INST: vsseg5e1024.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x92]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 05 92 <unknown>
+
+vsseg5e8.v v24, (a0), v0.t
+# CHECK-INST: vsseg5e8.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x80]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 05 80 <unknown>
+
+vsseg5e16.v v24, (a0), v0.t
+# CHECK-INST: vsseg5e16.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x80]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 05 80 <unknown>
+
+vsseg5e32.v v24, (a0), v0.t
+# CHECK-INST: vsseg5e32.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x80]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 05 80 <unknown>
+
+vsseg5e64.v v24, (a0), v0.t
+# CHECK-INST: vsseg5e64.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x80]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 05 80 <unknown>
+
+vsseg5e128.v v24, (a0), v0.t
+# CHECK-INST: vsseg5e128.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x90]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 05 90 <unknown>
+
+vsseg5e256.v v24, (a0), v0.t
+# CHECK-INST: vsseg5e256.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x90]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 05 90 <unknown>
+
+vsseg5e512.v v24, (a0), v0.t
+# CHECK-INST: vsseg5e512.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x90]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 05 90 <unknown>
+
+vsseg5e1024.v v24, (a0), v0.t
+# CHECK-INST: vsseg5e1024.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x90]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 05 90 <unknown>
+
+vsseg6e8.v v24, (a0)
+# CHECK-INST: vsseg6e8.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xa2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 05 a2 <unknown>
+
+vsseg6e16.v v24, (a0)
+# CHECK-INST: vsseg6e16.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xa2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 05 a2 <unknown>
+
+vsseg6e32.v v24, (a0)
+# CHECK-INST: vsseg6e32.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xa2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 05 a2 <unknown>
+
+vsseg6e64.v v24, (a0)
+# CHECK-INST: vsseg6e64.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xa2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 05 a2 <unknown>
+
+vsseg6e128.v v24, (a0)
+# CHECK-INST: vsseg6e128.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xb2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 05 b2 <unknown>
+
+vsseg6e256.v v24, (a0)
+# CHECK-INST: vsseg6e256.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xb2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 05 b2 <unknown>
+
+vsseg6e512.v v24, (a0)
+# CHECK-INST: vsseg6e512.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xb2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 05 b2 <unknown>
+
+vsseg6e1024.v v24, (a0)
+# CHECK-INST: vsseg6e1024.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xb2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 05 b2 <unknown>
+
+vsseg6e8.v v24, (a0), v0.t
+# CHECK-INST: vsseg6e8.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xa0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 05 a0 <unknown>
+
+vsseg6e16.v v24, (a0), v0.t
+# CHECK-INST: vsseg6e16.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xa0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 05 a0 <unknown>
+
+vsseg6e32.v v24, (a0), v0.t
+# CHECK-INST: vsseg6e32.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xa0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 05 a0 <unknown>
+
+vsseg6e64.v v24, (a0), v0.t
+# CHECK-INST: vsseg6e64.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xa0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 05 a0 <unknown>
+
+vsseg6e128.v v24, (a0), v0.t
+# CHECK-INST: vsseg6e128.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xb0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 05 b0 <unknown>
+
+vsseg6e256.v v24, (a0), v0.t
+# CHECK-INST: vsseg6e256.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xb0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 05 b0 <unknown>
+
+vsseg6e512.v v24, (a0), v0.t
+# CHECK-INST: vsseg6e512.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xb0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 05 b0 <unknown>
+
+vsseg6e1024.v v24, (a0), v0.t
+# CHECK-INST: vsseg6e1024.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xb0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 05 b0 <unknown>
+
+vsseg7e8.v v24, (a0)
+# CHECK-INST: vsseg7e8.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xc2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 05 c2 <unknown>
+
+vsseg7e16.v v24, (a0)
+# CHECK-INST: vsseg7e16.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xc2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 05 c2 <unknown>
+
+vsseg7e32.v v24, (a0)
+# CHECK-INST: vsseg7e32.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xc2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 05 c2 <unknown>
+
+vsseg7e64.v v24, (a0)
+# CHECK-INST: vsseg7e64.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xc2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 05 c2 <unknown>
+
+vsseg7e128.v v24, (a0)
+# CHECK-INST: vsseg7e128.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xd2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 05 d2 <unknown>
+
+vsseg7e256.v v24, (a0)
+# CHECK-INST: vsseg7e256.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xd2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 05 d2 <unknown>
+
+vsseg7e512.v v24, (a0)
+# CHECK-INST: vsseg7e512.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xd2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 05 d2 <unknown>
+
+vsseg7e1024.v v24, (a0)
+# CHECK-INST: vsseg7e1024.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xd2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 05 d2 <unknown>
+
+vsseg7e8.v v24, (a0), v0.t
+# CHECK-INST: vsseg7e8.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xc0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 05 c0 <unknown>
+
+vsseg7e16.v v24, (a0), v0.t
+# CHECK-INST: vsseg7e16.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xc0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 05 c0 <unknown>
+
+vsseg7e32.v v24, (a0), v0.t
+# CHECK-INST: vsseg7e32.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xc0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 05 c0 <unknown>
+
+vsseg7e64.v v24, (a0), v0.t
+# CHECK-INST: vsseg7e64.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xc0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 05 c0 <unknown>
+
+vsseg7e128.v v24, (a0), v0.t
+# CHECK-INST: vsseg7e128.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xd0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 05 d0 <unknown>
+
+vsseg7e256.v v24, (a0), v0.t
+# CHECK-INST: vsseg7e256.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xd0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 05 d0 <unknown>
+
+vsseg7e512.v v24, (a0), v0.t
+# CHECK-INST: vsseg7e512.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xd0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 05 d0 <unknown>
+
+vsseg7e1024.v v24, (a0), v0.t
+# CHECK-INST: vsseg7e1024.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xd0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 05 d0 <unknown>
+
+vsseg8e8.v v24, (a0)
+# CHECK-INST: vsseg8e8.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xe2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 05 e2 <unknown>
+
+vsseg8e16.v v24, (a0)
+# CHECK-INST: vsseg8e16.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xe2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 05 e2 <unknown>
+
+vsseg8e32.v v24, (a0)
+# CHECK-INST: vsseg8e32.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xe2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 05 e2 <unknown>
+
+vsseg8e64.v v24, (a0)
+# CHECK-INST: vsseg8e64.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xe2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 05 e2 <unknown>
+
+vsseg8e128.v v24, (a0)
+# CHECK-INST: vsseg8e128.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xf2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 05 f2 <unknown>
+
+vsseg8e256.v v24, (a0)
+# CHECK-INST: vsseg8e256.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xf2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 05 f2 <unknown>
+
+vsseg8e512.v v24, (a0)
+# CHECK-INST: vsseg8e512.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xf2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 05 f2 <unknown>
+
+vsseg8e1024.v v24, (a0)
+# CHECK-INST: vsseg8e1024.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xf2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 05 f2 <unknown>
+
+vsseg8e8.v v24, (a0), v0.t
+# CHECK-INST: vsseg8e8.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xe0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 05 e0 <unknown>
+
+vsseg8e16.v v24, (a0), v0.t
+# CHECK-INST: vsseg8e16.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xe0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 05 e0 <unknown>
+
+vsseg8e32.v v24, (a0), v0.t
+# CHECK-INST: vsseg8e32.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xe0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 05 e0 <unknown>
+
+vsseg8e64.v v24, (a0), v0.t
+# CHECK-INST: vsseg8e64.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xe0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 05 e0 <unknown>
+
+vsseg8e128.v v24, (a0), v0.t
+# CHECK-INST: vsseg8e128.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0xf0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 05 f0 <unknown>
+
+vsseg8e256.v v24, (a0), v0.t
+# CHECK-INST: vsseg8e256.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0xf0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 05 f0 <unknown>
+
+vsseg8e512.v v24, (a0), v0.t
+# CHECK-INST: vsseg8e512.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0xf0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 05 f0 <unknown>
+
+vsseg8e1024.v v24, (a0), v0.t
+# CHECK-INST: vsseg8e1024.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0xf0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 05 f0 <unknown>
+
+vssseg2e8.v v24, (a0), a1
+# CHECK-INST: vssseg2e8.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x2a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c b5 2a <unknown>
+
+vssseg2e16.v v24, (a0), a1
+# CHECK-INST: vssseg2e16.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x2a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c b5 2a <unknown>
+
+vssseg2e32.v v24, (a0), a1
+# CHECK-INST: vssseg2e32.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x2a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c b5 2a <unknown>
+
+vssseg2e64.v v24, (a0), a1
+# CHECK-INST: vssseg2e64.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x2a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c b5 2a <unknown>
+
+vssseg2e128.v v24, (a0), a1
+# CHECK-INST: vssseg2e128.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x3a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c b5 3a <unknown>
+
+vssseg2e256.v v24, (a0), a1
+# CHECK-INST: vssseg2e256.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x3a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c b5 3a <unknown>
+
+vssseg2e512.v v24, (a0), a1
+# CHECK-INST: vssseg2e512.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x3a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c b5 3a <unknown>
+
+vssseg2e1024.v v24, (a0), a1
+# CHECK-INST: vssseg2e1024.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x3a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c b5 3a <unknown>
+
+vssseg2e8.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg2e8.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x28]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c b5 28 <unknown>
+
+vssseg2e16.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg2e16.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x28]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c b5 28 <unknown>
+
+vssseg2e32.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg2e32.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x28]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c b5 28 <unknown>
+
+vssseg2e64.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg2e64.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x28]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c b5 28 <unknown>
+
+vssseg2e128.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg2e128.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x38]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c b5 38 <unknown>
+
+vssseg2e256.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg2e256.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x38]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c b5 38 <unknown>
+
+vssseg2e512.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg2e512.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x38]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c b5 38 <unknown>
+
+vssseg2e1024.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg2e1024.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x38]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c b5 38 <unknown>
+
+vssseg3e8.v v24, (a0), a1
+# CHECK-INST: vssseg3e8.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c b5 4a <unknown>
+
+vssseg3e16.v v24, (a0), a1
+# CHECK-INST: vssseg3e16.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c b5 4a <unknown>
+
+vssseg3e32.v v24, (a0), a1
+# CHECK-INST: vssseg3e32.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c b5 4a <unknown>
+
+vssseg3e64.v v24, (a0), a1
+# CHECK-INST: vssseg3e64.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x4a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c b5 4a <unknown>
+
+vssseg3e128.v v24, (a0), a1
+# CHECK-INST: vssseg3e128.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x5a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c b5 5a <unknown>
+
+vssseg3e256.v v24, (a0), a1
+# CHECK-INST: vssseg3e256.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x5a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c b5 5a <unknown>
+
+vssseg3e512.v v24, (a0), a1
+# CHECK-INST: vssseg3e512.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x5a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c b5 5a <unknown>
+
+vssseg3e1024.v v24, (a0), a1
+# CHECK-INST: vssseg3e1024.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x5a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c b5 5a <unknown>
+
+vssseg3e8.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg3e8.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c b5 48 <unknown>
+
+vssseg3e16.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg3e16.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c b5 48 <unknown>
+
+vssseg3e32.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg3e32.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c b5 48 <unknown>
+
+vssseg3e64.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg3e64.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c b5 48 <unknown>
+
+vssseg3e128.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg3e128.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x58]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c b5 58 <unknown>
+
+vssseg3e256.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg3e256.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x58]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c b5 58 <unknown>
+
+vssseg3e512.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg3e512.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x58]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c b5 58 <unknown>
+
+vssseg3e1024.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg3e1024.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x58]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c b5 58 <unknown>
+
+vssseg4e8.v v24, (a0), a1
+# CHECK-INST: vssseg4e8.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x6a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c b5 6a <unknown>
+
+vssseg4e16.v v24, (a0), a1
+# CHECK-INST: vssseg4e16.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x6a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c b5 6a <unknown>
+
+vssseg4e32.v v24, (a0), a1
+# CHECK-INST: vssseg4e32.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x6a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c b5 6a <unknown>
+
+vssseg4e64.v v24, (a0), a1
+# CHECK-INST: vssseg4e64.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x6a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c b5 6a <unknown>
+
+vssseg4e128.v v24, (a0), a1
+# CHECK-INST: vssseg4e128.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x7a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c b5 7a <unknown>
+
+vssseg4e256.v v24, (a0), a1
+# CHECK-INST: vssseg4e256.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x7a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c b5 7a <unknown>
+
+vssseg4e512.v v24, (a0), a1
+# CHECK-INST: vssseg4e512.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x7a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c b5 7a <unknown>
+
+vssseg4e1024.v v24, (a0), a1
+# CHECK-INST: vssseg4e1024.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x7a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c b5 7a <unknown>
+
+vssseg4e8.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg4e8.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x68]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c b5 68 <unknown>
+
+vssseg4e16.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg4e16.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x68]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c b5 68 <unknown>
+
+vssseg4e32.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg4e32.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x68]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c b5 68 <unknown>
+
+vssseg4e64.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg4e64.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x68]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c b5 68 <unknown>
+
+vssseg4e128.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg4e128.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x78]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c b5 78 <unknown>
+
+vssseg4e256.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg4e256.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x78]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c b5 78 <unknown>
+
+vssseg4e512.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg4e512.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x78]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c b5 78 <unknown>
+
+vssseg4e1024.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg4e1024.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x78]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c b5 78 <unknown>
+
+vssseg5e8.v v24, (a0), a1
+# CHECK-INST: vssseg5e8.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c b5 8a <unknown>
+
+vssseg5e16.v v24, (a0), a1
+# CHECK-INST: vssseg5e16.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c b5 8a <unknown>
+
+vssseg5e32.v v24, (a0), a1
+# CHECK-INST: vssseg5e32.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c b5 8a <unknown>
+
+vssseg5e64.v v24, (a0), a1
+# CHECK-INST: vssseg5e64.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c b5 8a <unknown>
+
+vssseg5e128.v v24, (a0), a1
+# CHECK-INST: vssseg5e128.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x9a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c b5 9a <unknown>
+
+vssseg5e256.v v24, (a0), a1
+# CHECK-INST: vssseg5e256.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x9a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c b5 9a <unknown>
+
+vssseg5e512.v v24, (a0), a1
+# CHECK-INST: vssseg5e512.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x9a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c b5 9a <unknown>
+
+vssseg5e1024.v v24, (a0), a1
+# CHECK-INST: vssseg5e1024.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x9a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c b5 9a <unknown>
+
+vssseg5e8.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg5e8.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c b5 88 <unknown>
+
+vssseg5e16.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg5e16.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c b5 88 <unknown>
+
+vssseg5e32.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg5e32.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c b5 88 <unknown>
+
+vssseg5e64.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg5e64.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c b5 88 <unknown>
+
+vssseg5e128.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg5e128.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x98]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c b5 98 <unknown>
+
+vssseg5e256.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg5e256.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x98]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c b5 98 <unknown>
+
+vssseg5e512.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg5e512.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x98]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c b5 98 <unknown>
+
+vssseg5e1024.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg5e1024.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x98]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c b5 98 <unknown>
+
+vssseg6e8.v v24, (a0), a1
+# CHECK-INST: vssseg6e8.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0xaa]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c b5 aa <unknown>
+
+vssseg6e16.v v24, (a0), a1
+# CHECK-INST: vssseg6e16.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0xaa]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c b5 aa <unknown>
+
+vssseg6e32.v v24, (a0), a1
+# CHECK-INST: vssseg6e32.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0xaa]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c b5 aa <unknown>
+
+vssseg6e64.v v24, (a0), a1
+# CHECK-INST: vssseg6e64.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0xaa]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c b5 aa <unknown>
+
+vssseg6e128.v v24, (a0), a1
+# CHECK-INST: vssseg6e128.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0xba]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c b5 ba <unknown>
+
+vssseg6e256.v v24, (a0), a1
+# CHECK-INST: vssseg6e256.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0xba]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c b5 ba <unknown>
+
+vssseg6e512.v v24, (a0), a1
+# CHECK-INST: vssseg6e512.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0xba]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c b5 ba <unknown>
+
+vssseg6e1024.v v24, (a0), a1
+# CHECK-INST: vssseg6e1024.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0xba]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c b5 ba <unknown>
+
+vssseg6e8.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg6e8.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0xa8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c b5 a8 <unknown>
+
+vssseg6e16.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg6e16.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0xa8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c b5 a8 <unknown>
+
+vssseg6e32.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg6e32.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0xa8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c b5 a8 <unknown>
+
+vssseg6e64.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg6e64.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0xa8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c b5 a8 <unknown>
+
+vssseg6e128.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg6e128.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0xb8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c b5 b8 <unknown>
+
+vssseg6e256.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg6e256.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0xb8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c b5 b8 <unknown>
+
+vssseg6e512.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg6e512.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0xb8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c b5 b8 <unknown>
+
+vssseg6e1024.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg6e1024.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0xb8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c b5 b8 <unknown>
+
+vssseg7e8.v v24, (a0), a1
+# CHECK-INST: vssseg7e8.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0xca]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c b5 ca <unknown>
+
+vssseg7e16.v v24, (a0), a1
+# CHECK-INST: vssseg7e16.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0xca]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c b5 ca <unknown>
+
+vssseg7e32.v v24, (a0), a1
+# CHECK-INST: vssseg7e32.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0xca]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c b5 ca <unknown>
+
+vssseg7e64.v v24, (a0), a1
+# CHECK-INST: vssseg7e64.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0xca]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c b5 ca <unknown>
+
+vssseg7e128.v v24, (a0), a1
+# CHECK-INST: vssseg7e128.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0xda]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c b5 da <unknown>
+
+vssseg7e256.v v24, (a0), a1
+# CHECK-INST: vssseg7e256.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0xda]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c b5 da <unknown>
+
+vssseg7e512.v v24, (a0), a1
+# CHECK-INST: vssseg7e512.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0xda]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c b5 da <unknown>
+
+vssseg7e1024.v v24, (a0), a1
+# CHECK-INST: vssseg7e1024.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0xda]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c b5 da <unknown>
+
+vssseg7e8.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg7e8.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0xc8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c b5 c8 <unknown>
+
+vssseg7e16.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg7e16.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0xc8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c b5 c8 <unknown>
+
+vssseg7e32.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg7e32.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0xc8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c b5 c8 <unknown>
+
+vssseg7e64.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg7e64.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0xc8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c b5 c8 <unknown>
+
+vssseg7e128.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg7e128.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0xd8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c b5 d8 <unknown>
+
+vssseg7e256.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg7e256.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0xd8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c b5 d8 <unknown>
+
+vssseg7e512.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg7e512.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0xd8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c b5 d8 <unknown>
+
+vssseg7e1024.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg7e1024.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0xd8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c b5 d8 <unknown>
+
+vssseg8e8.v v24, (a0), a1
+# CHECK-INST: vssseg8e8.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0xea]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c b5 ea <unknown>
+
+vssseg8e16.v v24, (a0), a1
+# CHECK-INST: vssseg8e16.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0xea]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c b5 ea <unknown>
+
+vssseg8e32.v v24, (a0), a1
+# CHECK-INST: vssseg8e32.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0xea]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c b5 ea <unknown>
+
+vssseg8e64.v v24, (a0), a1
+# CHECK-INST: vssseg8e64.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0xea]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c b5 ea <unknown>
+
+vssseg8e128.v v24, (a0), a1
+# CHECK-INST: vssseg8e128.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0xfa]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c b5 fa <unknown>
+
+vssseg8e256.v v24, (a0), a1
+# CHECK-INST: vssseg8e256.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0xfa]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c b5 fa <unknown>
+
+vssseg8e512.v v24, (a0), a1
+# CHECK-INST: vssseg8e512.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0xfa]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c b5 fa <unknown>
+
+vssseg8e1024.v v24, (a0), a1
+# CHECK-INST: vssseg8e1024.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0xfa]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c b5 fa <unknown>
+
+vssseg8e8.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg8e8.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0xe8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c b5 e8 <unknown>
+
+vssseg8e16.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg8e16.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0xe8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c b5 e8 <unknown>
+
+vssseg8e32.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg8e32.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0xe8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c b5 e8 <unknown>
+
+vssseg8e64.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg8e64.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0xe8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c b5 e8 <unknown>
+
+vssseg8e128.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg8e128.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0xf8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c b5 f8 <unknown>
+
+vssseg8e256.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg8e256.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0xf8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c b5 f8 <unknown>
+
+vssseg8e512.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg8e512.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0xf8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c b5 f8 <unknown>
+
+vssseg8e1024.v v24, (a0), a1, v0.t
+# CHECK-INST: vssseg8e1024.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0xf8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c b5 f8 <unknown>
+
+vsxseg2ei8.v v24, (a0), v4
+# CHECK-INST: vsxseg2ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 45 2e <unknown>
+
+vsxseg2ei16.v v24, (a0), v4
+# CHECK-INST: vsxseg2ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 45 2e <unknown>
+
+vsxseg2ei32.v v24, (a0), v4
+# CHECK-INST: vsxseg2ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 45 2e <unknown>
+
+vsxseg2ei64.v v24, (a0), v4
+# CHECK-INST: vsxseg2ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 45 2e <unknown>
+
+vsxseg2ei128.v v24, (a0), v4
+# CHECK-INST: vsxseg2ei128.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x3e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 45 3e <unknown>
+
+vsxseg2ei256.v v24, (a0), v4
+# CHECK-INST: vsxseg2ei256.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x3e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 45 3e <unknown>
+
+vsxseg2ei512.v v24, (a0), v4
+# CHECK-INST: vsxseg2ei512.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x3e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 45 3e <unknown>
+
+vsxseg2ei1024.v v24, (a0), v4
+# CHECK-INST: vsxseg2ei1024.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x3e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 45 3e <unknown>
+
+vsxseg2ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg2ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 45 2c <unknown>
+
+vsxseg2ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg2ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 45 2c <unknown>
+
+vsxseg2ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg2ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 45 2c <unknown>
+
+vsxseg2ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg2ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 45 2c <unknown>
+
+vsxseg2ei128.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg2ei128.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x3c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 45 3c <unknown>
+
+vsxseg2ei256.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg2ei256.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x3c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 45 3c <unknown>
+
+vsxseg2ei512.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg2ei512.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x3c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 45 3c <unknown>
+
+vsxseg2ei1024.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg2ei1024.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x3c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 45 3c <unknown>
+
+vsxseg3ei8.v v24, (a0), v4
+# CHECK-INST: vsxseg3ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 45 4e <unknown>
+
+vsxseg3ei16.v v24, (a0), v4
+# CHECK-INST: vsxseg3ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 45 4e <unknown>
+
+vsxseg3ei32.v v24, (a0), v4
+# CHECK-INST: vsxseg3ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 45 4e <unknown>
+
+vsxseg3ei64.v v24, (a0), v4
+# CHECK-INST: vsxseg3ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 45 4e <unknown>
+
+vsxseg3ei128.v v24, (a0), v4
+# CHECK-INST: vsxseg3ei128.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x5e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 45 5e <unknown>
+
+vsxseg3ei256.v v24, (a0), v4
+# CHECK-INST: vsxseg3ei256.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x5e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 45 5e <unknown>
+
+vsxseg3ei512.v v24, (a0), v4
+# CHECK-INST: vsxseg3ei512.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x5e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 45 5e <unknown>
+
+vsxseg3ei1024.v v24, (a0), v4
+# CHECK-INST: vsxseg3ei1024.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x5e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 45 5e <unknown>
+
+vsxseg3ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg3ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 45 4c <unknown>
+
+vsxseg3ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg3ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 45 4c <unknown>
+
+vsxseg3ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg3ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 45 4c <unknown>
+
+vsxseg3ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg3ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 45 4c <unknown>
+
+vsxseg3ei128.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg3ei128.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x5c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 45 5c <unknown>
+
+vsxseg3ei256.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg3ei256.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x5c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 45 5c <unknown>
+
+vsxseg3ei512.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg3ei512.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x5c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 45 5c <unknown>
+
+vsxseg3ei1024.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg3ei1024.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x5c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 45 5c <unknown>
+
+vsxseg4ei8.v v24, (a0), v4
+# CHECK-INST: vsxseg4ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 45 6e <unknown>
+
+vsxseg4ei16.v v24, (a0), v4
+# CHECK-INST: vsxseg4ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 45 6e <unknown>
+
+vsxseg4ei32.v v24, (a0), v4
+# CHECK-INST: vsxseg4ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 45 6e <unknown>
+
+vsxseg4ei64.v v24, (a0), v4
+# CHECK-INST: vsxseg4ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 45 6e <unknown>
+
+vsxseg4ei128.v v24, (a0), v4
+# CHECK-INST: vsxseg4ei128.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x7e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 45 7e <unknown>
+
+vsxseg4ei256.v v24, (a0), v4
+# CHECK-INST: vsxseg4ei256.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x7e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 45 7e <unknown>
+
+vsxseg4ei512.v v24, (a0), v4
+# CHECK-INST: vsxseg4ei512.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x7e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 45 7e <unknown>
+
+vsxseg4ei1024.v v24, (a0), v4
+# CHECK-INST: vsxseg4ei1024.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x7e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 45 7e <unknown>
+
+vsxseg4ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg4ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 45 6c <unknown>
+
+vsxseg4ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg4ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 45 6c <unknown>
+
+vsxseg4ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg4ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 45 6c <unknown>
+
+vsxseg4ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg4ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 45 6c <unknown>
+
+vsxseg4ei128.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg4ei128.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x7c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 45 7c <unknown>
+
+vsxseg4ei256.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg4ei256.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x7c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 45 7c <unknown>
+
+vsxseg4ei512.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg4ei512.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x7c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 45 7c <unknown>
+
+vsxseg4ei1024.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg4ei1024.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x7c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 45 7c <unknown>
+
+vsxseg5ei8.v v24, (a0), v4
+# CHECK-INST: vsxseg5ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 45 8e <unknown>
+
+vsxseg5ei16.v v24, (a0), v4
+# CHECK-INST: vsxseg5ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 45 8e <unknown>
+
+vsxseg5ei32.v v24, (a0), v4
+# CHECK-INST: vsxseg5ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 45 8e <unknown>
+
+vsxseg5ei64.v v24, (a0), v4
+# CHECK-INST: vsxseg5ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 45 8e <unknown>
+
+vsxseg5ei128.v v24, (a0), v4
+# CHECK-INST: vsxseg5ei128.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x9e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 45 9e <unknown>
+
+vsxseg5ei256.v v24, (a0), v4
+# CHECK-INST: vsxseg5ei256.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x9e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 45 9e <unknown>
+
+vsxseg5ei512.v v24, (a0), v4
+# CHECK-INST: vsxseg5ei512.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x9e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 45 9e <unknown>
+
+vsxseg5ei1024.v v24, (a0), v4
+# CHECK-INST: vsxseg5ei1024.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x9e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 45 9e <unknown>
+
+vsxseg5ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg5ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 45 8c <unknown>
+
+vsxseg5ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg5ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 45 8c <unknown>
+
+vsxseg5ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg5ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 45 8c <unknown>
+
+vsxseg5ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg5ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 45 8c <unknown>
+
+vsxseg5ei128.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg5ei128.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x9c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 45 9c <unknown>
+
+vsxseg5ei256.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg5ei256.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x9c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 45 9c <unknown>
+
+vsxseg5ei512.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg5ei512.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x9c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 45 9c <unknown>
+
+vsxseg5ei1024.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg5ei1024.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x9c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 45 9c <unknown>
+
+vsxseg6ei8.v v24, (a0), v4
+# CHECK-INST: vsxseg6ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 45 ae <unknown>
+
+vsxseg6ei16.v v24, (a0), v4
+# CHECK-INST: vsxseg6ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 45 ae <unknown>
+
+vsxseg6ei32.v v24, (a0), v4
+# CHECK-INST: vsxseg6ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 45 ae <unknown>
+
+vsxseg6ei64.v v24, (a0), v4
+# CHECK-INST: vsxseg6ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 45 ae <unknown>
+
+vsxseg6ei128.v v24, (a0), v4
+# CHECK-INST: vsxseg6ei128.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xbe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 45 be <unknown>
+
+vsxseg6ei256.v v24, (a0), v4
+# CHECK-INST: vsxseg6ei256.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xbe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 45 be <unknown>
+
+vsxseg6ei512.v v24, (a0), v4
+# CHECK-INST: vsxseg6ei512.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xbe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 45 be <unknown>
+
+vsxseg6ei1024.v v24, (a0), v4
+# CHECK-INST: vsxseg6ei1024.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xbe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 45 be <unknown>
+
+vsxseg6ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg6ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 45 ac <unknown>
+
+vsxseg6ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg6ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 45 ac <unknown>
+
+vsxseg6ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg6ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 45 ac <unknown>
+
+vsxseg6ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg6ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 45 ac <unknown>
+
+vsxseg6ei128.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg6ei128.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xbc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 45 bc <unknown>
+
+vsxseg6ei256.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg6ei256.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xbc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 45 bc <unknown>
+
+vsxseg6ei512.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg6ei512.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xbc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 45 bc <unknown>
+
+vsxseg6ei1024.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg6ei1024.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xbc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 45 bc <unknown>
+
+vsxseg7ei8.v v24, (a0), v4
+# CHECK-INST: vsxseg7ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 45 ce <unknown>
+
+vsxseg7ei16.v v24, (a0), v4
+# CHECK-INST: vsxseg7ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 45 ce <unknown>
+
+vsxseg7ei32.v v24, (a0), v4
+# CHECK-INST: vsxseg7ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 45 ce <unknown>
+
+vsxseg7ei64.v v24, (a0), v4
+# CHECK-INST: vsxseg7ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 45 ce <unknown>
+
+vsxseg7ei128.v v24, (a0), v4
+# CHECK-INST: vsxseg7ei128.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xde]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 45 de <unknown>
+
+vsxseg7ei256.v v24, (a0), v4
+# CHECK-INST: vsxseg7ei256.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xde]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 45 de <unknown>
+
+vsxseg7ei512.v v24, (a0), v4
+# CHECK-INST: vsxseg7ei512.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xde]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 45 de <unknown>
+
+vsxseg7ei1024.v v24, (a0), v4
+# CHECK-INST: vsxseg7ei1024.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xde]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 45 de <unknown>
+
+vsxseg7ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg7ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 45 cc <unknown>
+
+vsxseg7ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg7ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 45 cc <unknown>
+
+vsxseg7ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg7ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 45 cc <unknown>
+
+vsxseg7ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg7ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 45 cc <unknown>
+
+vsxseg7ei128.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg7ei128.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xdc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 45 dc <unknown>
+
+vsxseg7ei256.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg7ei256.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xdc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 45 dc <unknown>
+
+vsxseg7ei512.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg7ei512.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xdc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 45 dc <unknown>
+
+vsxseg7ei1024.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg7ei1024.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xdc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 45 dc <unknown>
+
+vsxseg8ei8.v v24, (a0), v4
+# CHECK-INST: vsxseg8ei8.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xee]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 45 ee <unknown>
+
+vsxseg8ei16.v v24, (a0), v4
+# CHECK-INST: vsxseg8ei16.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xee]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 45 ee <unknown>
+
+vsxseg8ei32.v v24, (a0), v4
+# CHECK-INST: vsxseg8ei32.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xee]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 45 ee <unknown>
+
+vsxseg8ei64.v v24, (a0), v4
+# CHECK-INST: vsxseg8ei64.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xee]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 45 ee <unknown>
+
+vsxseg8ei128.v v24, (a0), v4
+# CHECK-INST: vsxseg8ei128.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xfe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 45 fe <unknown>
+
+vsxseg8ei256.v v24, (a0), v4
+# CHECK-INST: vsxseg8ei256.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xfe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 45 fe <unknown>
+
+vsxseg8ei512.v v24, (a0), v4
+# CHECK-INST: vsxseg8ei512.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xfe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 45 fe <unknown>
+
+vsxseg8ei1024.v v24, (a0), v4
+# CHECK-INST: vsxseg8ei1024.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xfe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 45 fe <unknown>
+
+vsxseg8ei8.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg8ei8.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xec]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 45 ec <unknown>
+
+vsxseg8ei16.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg8ei16.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xec]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 45 ec <unknown>
+
+vsxseg8ei32.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg8ei32.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xec]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 45 ec <unknown>
+
+vsxseg8ei64.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg8ei64.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xec]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 45 ec <unknown>
+
+vsxseg8ei128.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg8ei128.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0xfc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 0c 45 fc <unknown>
+
+vsxseg8ei256.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg8ei256.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0xfc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 5c 45 fc <unknown>
+
+vsxseg8ei512.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg8ei512.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0xfc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 6c 45 fc <unknown>
+
+vsxseg8ei1024.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxseg8ei1024.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0xfc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions), 'Zvlsseg' (Vector segment load/store instructions)
+# CHECK-UNKNOWN: 27 7c 45 fc <unknown>
 No newline at end of file