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[RISCV] add the assemble and disassemble support of Zvlsseg instructions
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Authored by StephenFan on Jul 14 2020, 7:35 AM.

Details

Summary

This implement the assemble and disassemble support of RISCV Vector extension Zvlsseg instructions, base on the 0.8 spec version.

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Event Timeline

StephenFan created this revision.Jul 14 2020, 7:35 AM
StephenFan retitled this revision from add the assemble and disassemble support of Zvlsseg instructions to [RISCV] add the assemble and disassemble support of Zvlsseg instructions.Jul 14 2020, 7:39 AM

I'm not familiar with the vector extension, but given the title of the patch, I have an integration question: It looks like this is enabled by use of the vector target feature, but the name 'Zvlsseg' suggests it's something optional/extra. If the intent to have this enabled unconditionally with 'v', or does it make sense to add features like what was done for bitmanip, where each 'Zb*' part can be enabled/disabled indepenently?

StephenFan added a comment.EditedJul 16 2020, 12:52 AM

I'm not familiar with the vector extension, but given the title of the patch, I have an integration question: It looks like this is enabled by use of the vector target feature, but the name 'Zvlsseg' suggests it's something optional/extra. If the intent to have this enabled unconditionally with 'v', or does it make sense to add features like what was done for bitmanip, where each 'Zb*' part can be enabled/disabled indepenently?

Following your suggestion, I added the experimental-zvlsseg feature to enable the zvlsseg instructions,thanks

Duplicated in D84416. Abandon this one.

StephenFan abandoned this revision.Aug 26 2020, 11:23 PM
llvm/test/MC/RISCV/rvv/load.s